[Mesa-dev] [PATCH] R600: Fix typo in R600Schedule.td
From: Tom Stellard
This should only make a difference in programs that use a lot of the
vector ALU instructions like BFI_INT and BIT_ALIGN. There is a slight
improvement in the phatk bitcoin mining kernel with this patch on
Evergreen (vector size == 1):
Before:
1173 Instruction Groups / 9520 dwords
After:
1167 Instruction Groups / 9510 dwords
---
lib/Target/R600/R600Schedule.td | 4 ++--
test/CodeGen/R600/packetizer.ll | 34 ++
2 files changed, 36 insertions(+), 2 deletions(-)
create mode 100644 test/CodeGen/R600/packetizer.ll
diff --git a/lib/Target/R600/R600Schedule.td b/lib/Target/R600/R600Schedule.td
index 78a460a..207233d 100644
--- a/lib/Target/R600/R600Schedule.td
+++ b/lib/Target/R600/R600Schedule.td
@@ -29,7 +29,7 @@ def R600_VLIW5_Itin : ProcessorItineraries <
[],
[
InstrItinData]>,
-InstrItinData]>,
+InstrItinData]>,
InstrItinData]>,
InstrItinData]>
]
@@ -40,7 +40,7 @@ def R600_VLIW4_Itin : ProcessorItineraries <
[],
[
InstrItinData]>,
-InstrItinData]>,
+InstrItinData]>,
InstrItinData]>,
InstrItinData]>
]
diff --git a/test/CodeGen/R600/packetizer.ll b/test/CodeGen/R600/packetizer.ll
new file mode 100644
index 000..0a405c5
--- /dev/null
+++ b/test/CodeGen/R600/packetizer.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
+
+; CHECK: @test
+; CHECK: BIT_ALIGN_INT T{{[0-9]}}.X
+; CHECK: BIT_ALIGN_INT T{{[0-9]}}.Y
+; CHECK: BIT_ALIGN_INT T{{[0-9]}}.Z
+; CHECK: BIT_ALIGN_INT * T{{[0-9]}}.W
+
+define void @test(i32 addrspace(1)* %out, i32 %x_arg, i32 %y_arg, i32 %z_arg,
i32 %w_arg, i32 %e) {
+entry:
+ %shl = sub i32 32, %e
+ %x = add i32 %x_arg, 1
+ %x.0 = shl i32 %x, %shl
+ %x.1 = lshr i32 %x, %e
+ %x.2 = or i32 %x.0, %x.1
+ %y = add i32 %y_arg, 1
+ %y.0 = shl i32 %y, %shl
+ %y.1 = lshr i32 %y, %e
+ %y.2 = or i32 %y.0, %y.1
+ %z = add i32 %z_arg, 1
+ %z.0 = shl i32 %z, %shl
+ %z.1 = lshr i32 %z, %e
+ %z.2 = or i32 %z.0, %z.1
+ %w = add i32 %w_arg, 1
+ %w.0 = shl i32 %w, %shl
+ %w.1 = lshr i32 %w, %e
+ %w.2 = or i32 %w.0, %w.1
+ %xy = or i32 %x.2, %y.2
+ %zw = or i32 %z.2, %w.2
+ %xyzw = or i32 %xy, %zw
+ store i32 %xyzw, i32 addrspace(1)* %out
+ ret void
+}
--
1.8.1.5
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Re: [Mesa-dev] [PATCH] gen7: fix GPU hang on WebGL texture-size test
On 18 June 2013 01:09, Jordan Justen wrote: > When rendering to a texture with BaseLevel set, the miptree may be laid > out such that BaseLevel is in level 0 of the miptree (to avoid wasting > memory on unused levels between 0 and BaseLevel-1). In that case, we > have to shift our render target's level down to the appropriate level of > the smaller miptree. > > The WebGL test in combination with a meta code relating to > glGenerateMipmap also triggered a similar failure scenario. > > This GPU hang regression was introduced by c754f7a8. > > Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=65324 > Signed-off-by: Jordan Justen > Cc: Eric Anholt > Cc: Kenneth Graunke > Cc: Paul Berry > --- > Given all of Eric's help, this is probably more his patch than mine... :) > > src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c > b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c > index 22ceaa5..620eafe 100644 > --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c > +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c > @@ -595,7 +595,7 @@ gen7_update_renderbuffer_surface(struct brw_context > *brw, > > assert(brw->has_surface_tile_offset); > > - surf[5] = irb->mt_level; > + surf[5] = irb->mt_level - irb->mt->first_level; > > surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) | > SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT); > -- > 1.7.10.4 > > How difficult would it be to make a Piglit test to validate this, preferably one that verifies that depth/stencil rendering properly accounts for first_level != 0? I want to make sure that when we make the corresponding changes to depth/stencil rendering we don't accidentally introduce the same bug. In any case, this patch is: Reviwed-by: Paul Berry ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 6/6] mesa: Move the common _mesa_glsl_compile_shader() code to glsl/.
On 18 June 2013 02:10, Eric Anholt wrote:
> ... and move the mesa-core-specific code into Mesa core. This code had no
> relation to ir_to_mesa.cpp, since it was also used by intel and
> state_tracker, and most of it was duplicated with the standalone compiler
> (which has periodically drifted from the Mesa copy).
>
This patch is:
Acked-by: Paul Berry
The remainder of the series is:
Reviewed-by: Paul Berry
> ---
> src/glsl/glsl_parser_extras.cpp | 83
> src/glsl/glsl_parser_extras.h | 2 +
> src/glsl/main.cpp | 59 +-
> src/glsl/program.h | 16 ++-
> src/mesa/main/shaderapi.c | 57 -
> src/mesa/program/ir_to_mesa.cpp | 94
> -
> src/mesa/program/ir_to_mesa.h | 1 -
> 7 files changed, 146 insertions(+), 166 deletions(-)
>
> diff --git a/src/glsl/glsl_parser_extras.cpp
> b/src/glsl/glsl_parser_extras.cpp
> index 7b827ba..f142d73 100644
> --- a/src/glsl/glsl_parser_extras.cpp
> +++ b/src/glsl/glsl_parser_extras.cpp
> @@ -28,6 +28,7 @@
> extern "C" {
> #include "main/core.h" /* for struct gl_context */
> #include "main/context.h"
> +#include "main/shaderobj.h"
> }
>
> #include "ralloc.h"
> @@ -1237,6 +1238,88 @@ ast_struct_specifier::ast_struct_specifier(const
> char *identifier,
>
> this->declarations.push_degenerate_list_at_head(&declarator_list->link);
> }
>
> +extern "C" {
> +
> +void
> +_mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader
> *shader,
> + bool dump_ast, bool dump_hir)
> +{
> + struct _mesa_glsl_parse_state *state =
> + new(shader) _mesa_glsl_parse_state(ctx, shader->Type, shader);
> + const char *source = shader->Source;
> +
> + state->error = glcpp_preprocess(state, &source, &state->info_log,
> +&ctx->Extensions, ctx);
> +
> + if (!state->error) {
> + _mesa_glsl_lexer_ctor(state, source);
> + _mesa_glsl_parse(state);
> + _mesa_glsl_lexer_dtor(state);
> + }
> +
> + if (dump_ast) {
> + foreach_list_const(n, &state->translation_unit) {
> +ast_node *ast = exec_node_data(ast_node, n, link);
> +ast->print();
> + }
> + printf("\n\n");
> + }
> +
> + ralloc_free(shader->ir);
> + shader->ir = new(shader) exec_list;
> + if (!state->error && !state->translation_unit.is_empty())
> + _mesa_ast_to_hir(shader->ir, state);
> +
> + if (!state->error) {
> + validate_ir_tree(shader->ir);
> +
> + /* Print out the unoptimized IR. */
> + if (dump_hir) {
> +_mesa_print_ir(shader->ir, state);
> + }
> + }
> +
> +
> + if (!state->error && !shader->ir->is_empty()) {
> + struct gl_shader_compiler_options *options =
> +
> &ctx->ShaderCompilerOptions[_mesa_shader_type_to_index(shader->Type)];
> +
> + /* Do some optimization at compile time to reduce shader IR size
> + * and reduce later work if the same shader is linked multiple times
> + */
> + while (do_common_optimization(shader->ir, false, false, 32,
> options))
> +;
> +
> + validate_ir_tree(shader->ir);
> + }
> +
> + if (shader->InfoLog)
> + ralloc_free(shader->InfoLog);
> +
> + shader->symbols = state->symbols;
> + shader->CompileStatus = !state->error;
> + shader->InfoLog = state->info_log;
> + shader->Version = state->language_version;
> + shader->InfoLog = state->info_log;
> + shader->IsES = state->es_shader;
> +
> + memcpy(shader->builtins_to_link, state->builtins_to_link,
> + sizeof(shader->builtins_to_link[0]) *
> state->num_builtins_to_link);
> + shader->num_builtins_to_link = state->num_builtins_to_link;
> +
> + if (shader->UniformBlocks)
> + ralloc_free(shader->UniformBlocks);
> + shader->NumUniformBlocks = state->num_uniform_blocks;
> + shader->UniformBlocks = state->uniform_blocks;
> + ralloc_steal(shader, shader->UniformBlocks);
> +
> + /* Retain any live IR, but trash the rest. */
> + reparent_ir(shader->ir, shader->ir);
> +
> + ralloc_free(state);
> +}
> +
> +} /* extern "C" */
> /**
> * Do the set of common optimizations passes
> *
> diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
> index 7f478df..cf296e9 100644
> --- a/src/glsl/glsl_parser_extras.h
> +++ b/src/glsl/glsl_parser_extras.h
> @@ -342,6 +342,8 @@ extern int _mesa_glsl_lex(union YYSTYPE *yylval,
> YYLTYPE *yylloc,
>
> extern int _mesa_glsl_parse(struct _mesa_glsl_parse_state *);
>
> +extern void compile_shader();
> +
> /**
> * Process elements of the #extension directive
> *
> diff --git a/src/glsl/main.cpp b/src/glsl/main.cpp
> index 5713ee5..60bc628 100644
> --- a/src/glsl/main.cpp
> +++ b/src/glsl/main.cpp
> @@ -143,70 +143,13 @@ compile_shader(struct gl_context *ctx, struct
> gl_shader *shader)
> struct _mesa_glsl_parse_state *state =
>new(shader) _mesa_glsl_parse_state(ctx, shader->Type, shade
[Mesa-dev] [Bug 65874] New: piglit ext_transform_feedback-intervening-read output regression
https://bugs.freedesktop.org/show_bug.cgi?id=65874
Priority: medium
Bug ID: 65874
Keywords: regression
CC: za...@vmware.com
Assignee: mesa-dev@lists.freedesktop.org
Summary: piglit ext_transform_feedback-intervening-read output
regression
Severity: normal
Classification: Unclassified
OS: Linux (All)
Reporter: v...@freedesktop.org
Hardware: x86-64 (AMD64)
Status: NEW
Version: git
Component: Mesa core
Product: Mesa
mesa: eb2021507556633cd6ba64cda26653e3c43e80df (master)
$ ./bin/ext_transform_feedback-intervening-read output -auto
Read incorrect data for vertex 0.
Readback: position=(0.00, -1.00, 0.00, 1.00), color=(0.00,
0.00, 1.00, 1.00)
Expected: position=(-1.00, -1.00, 0.00, 1.00), color=(1.00,
1.00, 0.00, 1.00)
Read incorrect data for vertex 1.
Readback: position=(1.00, -1.00, 0.00, 1.00), color=(0.00,
0.00, 1.00, 1.00)
Expected: position=(0.00, -1.00, 0.00, 1.00), color=(1.00,
1.00, 0.00, 1.00)
Read incorrect data for vertex 2.
Readback: position=(0.00, 1.00, 0.00, 1.00), color=(0.00,
0.00, 1.00, 1.00)
Expected: position=(-1.00, 1.00, 0.00, 1.00), color=(1.00,
1.00, 0.00, 1.00)
Read incorrect data for vertex 3.
Readback: position=(0.00, 1.00, 0.00, 1.00), color=(0.00,
0.00, 1.00, 1.00)
Expected: position=(-1.00, 1.00, 0.00, 1.00), color=(1.00,
1.00, 0.00, 1.00)
Read incorrect data for vertex 4.
Readback: position=(1.00, -1.00, 0.00, 1.00), color=(0.00,
0.00, 1.00, 1.00)
Expected: position=(0.00, -1.00, 0.00, 1.00), color=(1.00,
1.00, 0.00, 1.00)
Read incorrect data for vertex 5.
Readback: position=(1.00, 1.00, 0.00, 1.00), color=(0.00,
0.00, 1.00, 1.00)
Expected: position=(0.00, 1.00, 0.00, 1.00), color=(1.00,
1.00, 0.00, 1.00)
Read incorrect data for vertex 6.
Readback: position=(12345.00, 12345.00, 12345.00, 12345.00),
color=(12345.00, 12345.00, 12345.00, 12345.00)
Expected: position=(0.00, -1.00, 0.00, 1.00), color=(0.00,
0.00, 1.00, 1.00)
Read incorrect data for vertex 7.
Readback: position=(12345.00, 12345.00, 12345.00, 12345.00),
color=(12345.00, 12345.00, 12345.00, 12345.00)
Expected: position=(1.00, -1.00, 0.00, 1.00), color=(0.00,
0.00, 1.00, 1.00)
Read incorrect data for vertex 8.
Readback: position=(12345.00, 12345.00, 12345.00, 12345.00),
color=(12345.00, 12345.00, 12345.00, 12345.00)
Expected: position=(0.00, 1.00, 0.00, 1.00), color=(0.00,
0.00, 1.00, 1.00)
PIGLIT: {'result': 'fail' }
41966fdb3b71c0b70aeb095e0eb3c5626c144a3a is the first bad commit
commit 41966fdb3b71c0b70aeb095e0eb3c5626c144a3a
Author: Zack Rusin
Date: Thu Jun 13 17:57:47 2013 -0400
draw: clear the draw buffers in draw
Moves clearing of the draw so target buffers to the draw
module. They had to be cleared in the drivers before
which was quite messy.
Signed-off-by: Zack Rusin
Reviewed-by: Jose Fonseca
Reviewed-by: Brian Paul
:04 04 c836c139da6f4f91be2b86bc65f9e1ccc3bc3e14
1de6a5310e52318edaba24ceba214c29c2e78e6a Msrc
bisect run success
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[Mesa-dev] [PATCH 6/6] mesa: Move the common _mesa_glsl_compile_shader() code to glsl/.
... and move the mesa-core-specific code into Mesa core. This code had no
relation to ir_to_mesa.cpp, since it was also used by intel and
state_tracker, and most of it was duplicated with the standalone compiler
(which has periodically drifted from the Mesa copy).
---
src/glsl/glsl_parser_extras.cpp | 83
src/glsl/glsl_parser_extras.h | 2 +
src/glsl/main.cpp | 59 +-
src/glsl/program.h | 16 ++-
src/mesa/main/shaderapi.c | 57 -
src/mesa/program/ir_to_mesa.cpp | 94 -
src/mesa/program/ir_to_mesa.h | 1 -
7 files changed, 146 insertions(+), 166 deletions(-)
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 7b827ba..f142d73 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -28,6 +28,7 @@
extern "C" {
#include "main/core.h" /* for struct gl_context */
#include "main/context.h"
+#include "main/shaderobj.h"
}
#include "ralloc.h"
@@ -1237,6 +1238,88 @@ ast_struct_specifier::ast_struct_specifier(const char
*identifier,
this->declarations.push_degenerate_list_at_head(&declarator_list->link);
}
+extern "C" {
+
+void
+_mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader,
+ bool dump_ast, bool dump_hir)
+{
+ struct _mesa_glsl_parse_state *state =
+ new(shader) _mesa_glsl_parse_state(ctx, shader->Type, shader);
+ const char *source = shader->Source;
+
+ state->error = glcpp_preprocess(state, &source, &state->info_log,
+&ctx->Extensions, ctx);
+
+ if (!state->error) {
+ _mesa_glsl_lexer_ctor(state, source);
+ _mesa_glsl_parse(state);
+ _mesa_glsl_lexer_dtor(state);
+ }
+
+ if (dump_ast) {
+ foreach_list_const(n, &state->translation_unit) {
+ast_node *ast = exec_node_data(ast_node, n, link);
+ast->print();
+ }
+ printf("\n\n");
+ }
+
+ ralloc_free(shader->ir);
+ shader->ir = new(shader) exec_list;
+ if (!state->error && !state->translation_unit.is_empty())
+ _mesa_ast_to_hir(shader->ir, state);
+
+ if (!state->error) {
+ validate_ir_tree(shader->ir);
+
+ /* Print out the unoptimized IR. */
+ if (dump_hir) {
+_mesa_print_ir(shader->ir, state);
+ }
+ }
+
+
+ if (!state->error && !shader->ir->is_empty()) {
+ struct gl_shader_compiler_options *options =
+ &ctx->ShaderCompilerOptions[_mesa_shader_type_to_index(shader->Type)];
+
+ /* Do some optimization at compile time to reduce shader IR size
+ * and reduce later work if the same shader is linked multiple times
+ */
+ while (do_common_optimization(shader->ir, false, false, 32, options))
+;
+
+ validate_ir_tree(shader->ir);
+ }
+
+ if (shader->InfoLog)
+ ralloc_free(shader->InfoLog);
+
+ shader->symbols = state->symbols;
+ shader->CompileStatus = !state->error;
+ shader->InfoLog = state->info_log;
+ shader->Version = state->language_version;
+ shader->InfoLog = state->info_log;
+ shader->IsES = state->es_shader;
+
+ memcpy(shader->builtins_to_link, state->builtins_to_link,
+ sizeof(shader->builtins_to_link[0]) * state->num_builtins_to_link);
+ shader->num_builtins_to_link = state->num_builtins_to_link;
+
+ if (shader->UniformBlocks)
+ ralloc_free(shader->UniformBlocks);
+ shader->NumUniformBlocks = state->num_uniform_blocks;
+ shader->UniformBlocks = state->uniform_blocks;
+ ralloc_steal(shader, shader->UniformBlocks);
+
+ /* Retain any live IR, but trash the rest. */
+ reparent_ir(shader->ir, shader->ir);
+
+ ralloc_free(state);
+}
+
+} /* extern "C" */
/**
* Do the set of common optimizations passes
*
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 7f478df..cf296e9 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -342,6 +342,8 @@ extern int _mesa_glsl_lex(union YYSTYPE *yylval, YYLTYPE
*yylloc,
extern int _mesa_glsl_parse(struct _mesa_glsl_parse_state *);
+extern void compile_shader();
+
/**
* Process elements of the #extension directive
*
diff --git a/src/glsl/main.cpp b/src/glsl/main.cpp
index 5713ee5..60bc628 100644
--- a/src/glsl/main.cpp
+++ b/src/glsl/main.cpp
@@ -143,70 +143,13 @@ compile_shader(struct gl_context *ctx, struct gl_shader
*shader)
struct _mesa_glsl_parse_state *state =
new(shader) _mesa_glsl_parse_state(ctx, shader->Type, shader);
- const char *source = shader->Source;
- state->error = glcpp_preprocess(state, &source, &state->info_log,
-state->extensions, ctx) != 0;
-
- if (!state->error) {
- _mesa_glsl_lexer_ctor(state, source);
- _mesa_glsl_parse(state);
- _mesa_glsl_lexer_dtor(state);
- }
-
- if (dump_ast) {
- foreach_list_const(n, &state->translation_unit) {
-a
[Mesa-dev] [PATCH 5/6] mesa: Fix missing setting of shader->IsES.
I noticed this while trying to merge code with the builtin compiler, which does set it. Note that this causes two regressions in piglit in default-precision-sampler.* which try to link without a vertex or fragment shader, due to being run under the desktop glslparsertest binary (using ARB_ES3_compatibility) that doesn't know about this requirement. --- src/mesa/program/ir_to_mesa.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp index 2739df7..a915974 100644 --- a/src/mesa/program/ir_to_mesa.cpp +++ b/src/mesa/program/ir_to_mesa.cpp @@ -3155,6 +3155,7 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader) shader->CompileStatus = !state->error; shader->InfoLog = state->info_log; shader->Version = state->language_version; + shader->IsES = state->es_shader; memcpy(shader->builtins_to_link, state->builtins_to_link, sizeof(shader->builtins_to_link[0]) * state->num_builtins_to_link); shader->num_builtins_to_link = state->num_builtins_to_link; -- 1.8.3.rc0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/6] mesa: Use shared code for converting shader targets to short strings.
We were duplicating this code all over the place, and they all would need
updating for the next set of shader targets.
---
src/glsl/glsl_parser_extras.cpp| 35 ++
src/glsl/glsl_parser_extras.h | 3 +++
src/glsl/link_varyings.cpp | 15 -
src/glsl/linker.cpp| 4 ++--
src/mesa/drivers/dri/i965/brw_shader.cpp | 9
src/mesa/main/shaderapi.c | 17 ++-
src/mesa/main/uniform_query.cpp| 9 ++--
src/mesa/program/ir_to_mesa.cpp| 5 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 7 ++
9 files changed, 61 insertions(+), 43 deletions(-)
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 9862714..7b827ba 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -302,6 +302,41 @@ _mesa_glsl_parse_state::process_version_directive(YYLTYPE
*locp, int version,
}
}
+extern "C" {
+
+/**
+ * The most common use of _mesa_glsl_shader_target_name(), which is
+ * shared with C code in Mesa core to translate a GLenum to a short
+ * shader stage name in debug printouts.
+ *
+ * It recognizes the PROGRAM variants of the names so it can be used
+ * with a struct gl_program->Target, not just a struct
+ * gl_shader->Type.
+ */
+const char *
+_mesa_glsl_shader_target_name(GLenum type)
+{
+ switch (type) {
+ case GL_VERTEX_SHADER:
+ case GL_VERTEX_PROGRAM_ARB:
+ return "vertex";
+ case GL_FRAGMENT_SHADER:
+ case GL_FRAGMENT_PROGRAM_ARB:
+ return "fragment";
+ case GL_GEOMETRY_SHADER:
+ return "geometry";
+ default:
+ assert(!"Should not get here.");
+ return "unknown";
+ }
+}
+
+} /* extern "C" */
+
+/**
+ * Overloaded C++ variant usable within the compiler for translating
+ * our internal enum into short stage names.
+ */
const char *
_mesa_glsl_shader_target_name(enum _mesa_glsl_parser_targets target)
{
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 95918de..7f478df 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -371,6 +371,9 @@ _mesa_glsl_shader_target_name(enum
_mesa_glsl_parser_targets target);
extern "C" {
#endif
+extern const char *
+_mesa_glsl_shader_target_name(GLenum type);
+
extern int glcpp_preprocess(void *ctx, const char **shader, char **info_log,
const struct gl_extensions *extensions, struct
gl_context *gl_ctx);
diff --git a/src/glsl/link_varyings.cpp b/src/glsl/link_varyings.cpp
index 34e3440..4fdbdc1 100644
--- a/src/glsl/link_varyings.cpp
+++ b/src/glsl/link_varyings.cpp
@@ -31,6 +31,7 @@
#include "main/mtypes.h"
#include "glsl_symbol_table.h"
+#include "glsl_parser_extras.h"
#include "ir_optimization.h"
#include "linker.h"
#include "link_varyings.h"
@@ -47,9 +48,10 @@ cross_validate_outputs_to_inputs(struct gl_shader_program
*prog,
gl_shader *producer, gl_shader *consumer)
{
glsl_symbol_table parameters;
- /* FINISHME: Figure these out dynamically. */
- const char *const producer_stage = "vertex";
- const char *const consumer_stage = "fragment";
+ const char *const producer_stage =
+ _mesa_glsl_shader_target_name(producer->Type);
+ const char *const consumer_stage =
+ _mesa_glsl_shader_target_name(consumer->Type);
/* Find all shader outputs in the "producer" stage.
*/
@@ -1135,8 +1137,11 @@ assign_varying_locations(struct gl_context *ctx,
* "glsl1-varying read but not written" in piglit.
*/
- linker_error(prog, "fragment shader varying %s not written "
-"by vertex shader\n.", var->name);
+ linker_error(prog, "%s shader varying %s not written "
+"by %s shader\n.",
+_mesa_glsl_shader_target_name(consumer->Type),
+ var->name,
+_mesa_glsl_shader_target_name(producer->Type));
}
/* An 'in' variable is only really a shader input if its
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index cd8d680..c168e47 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -66,6 +66,7 @@
#include "main/core.h"
#include "glsl_symbol_table.h"
+#include "glsl_parser_extras.h"
#include "ir.h"
#include "program.h"
#include "program/hash_table.h"
@@ -1009,8 +1010,7 @@ link_intrastage_shaders(void *mem_ctx,
if (main == NULL) {
linker_error(prog, "%s shader lacks `main'\n",
- (shader_list[0]->Type == GL_VERTEX_SHADER)
- ? "vertex" : "fragment");
+ _mesa_glsl_shader_target_name(shader_list[0]->Type));
return NULL;
}
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 65df931..12986cc 100644
--- a/src/mesa/
[Mesa-dev] [PATCH 3/6] glsl: Remove ir_print_visitor.h includes and usage
We have ir->print() to do the old declaration of a visitor and having the
IR accept the visitor (yuck!). And now you can call _mesa_print_ir()
safely anywhere that you know what an ir_instruction is.
A couple of missing printf("\n")s are added in error paths -- when an
expression is handed to the visitor, it doesn't print '\n' (since it might
be a step in printing a whole expression tree).
---
src/glsl/ir_rvalue_visitor.cpp | 1 -
src/glsl/main.cpp | 1 -
src/glsl/opt_array_splitting.cpp| 1 -
src/glsl/opt_noop_swizzle.cpp | 1 -
src/glsl/opt_structure_splitting.cpp| 1 -
src/glsl/test_optpass.cpp | 1 -
src/mesa/drivers/dri/i965/brw_fs.cpp| 1 -
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 1 -
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 1 -
src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp | 1 -
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp| 5 ++---
src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 1 -
src/mesa/drivers/dri/i965/brw_shader.cpp| 1 -
src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 -
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 1 -
src/mesa/main/ff_fragment_shader.cpp| 1 -
src/mesa/program/ir_to_mesa.cpp | 9 -
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 5 ++---
18 files changed, 8 insertions(+), 26 deletions(-)
diff --git a/src/glsl/ir_rvalue_visitor.cpp b/src/glsl/ir_rvalue_visitor.cpp
index 3504a4d..8eb1c62 100644
--- a/src/glsl/ir_rvalue_visitor.cpp
+++ b/src/glsl/ir_rvalue_visitor.cpp
@@ -32,7 +32,6 @@
#include "ir.h"
#include "ir_visitor.h"
#include "ir_rvalue_visitor.h"
-#include "ir_print_visitor.h"
#include "glsl_types.h"
ir_visitor_status
diff --git a/src/glsl/main.cpp b/src/glsl/main.cpp
index d7e35bc..5713ee5 100644
--- a/src/glsl/main.cpp
+++ b/src/glsl/main.cpp
@@ -34,7 +34,6 @@
#include "ast.h"
#include "glsl_parser_extras.h"
#include "ir_optimization.h"
-#include "ir_print_visitor.h"
#include "program.h"
#include "loop_analysis.h"
#include "standalone_scaffolding.h"
diff --git a/src/glsl/opt_array_splitting.cpp b/src/glsl/opt_array_splitting.cpp
index 67733ca..f4a7ef9 100644
--- a/src/glsl/opt_array_splitting.cpp
+++ b/src/glsl/opt_array_splitting.cpp
@@ -36,7 +36,6 @@
#include "ir.h"
#include "ir_visitor.h"
#include "ir_rvalue_visitor.h"
-#include "ir_print_visitor.h"
#include "glsl_types.h"
static bool debug = false;
diff --git a/src/glsl/opt_noop_swizzle.cpp b/src/glsl/opt_noop_swizzle.cpp
index 693719e..586ad5e 100644
--- a/src/glsl/opt_noop_swizzle.cpp
+++ b/src/glsl/opt_noop_swizzle.cpp
@@ -32,7 +32,6 @@
#include "ir.h"
#include "ir_visitor.h"
#include "ir_rvalue_visitor.h"
-#include "ir_print_visitor.h"
#include "glsl_types.h"
namespace {
diff --git a/src/glsl/opt_structure_splitting.cpp
b/src/glsl/opt_structure_splitting.cpp
index 806c079..9f4b3dd 100644
--- a/src/glsl/opt_structure_splitting.cpp
+++ b/src/glsl/opt_structure_splitting.cpp
@@ -34,7 +34,6 @@
#include "ir.h"
#include "ir_visitor.h"
-#include "ir_print_visitor.h"
#include "ir_rvalue_visitor.h"
#include "glsl_types.h"
diff --git a/src/glsl/test_optpass.cpp b/src/glsl/test_optpass.cpp
index fc10cbbd..67e2ab2 100644
--- a/src/glsl/test_optpass.cpp
+++ b/src/glsl/test_optpass.cpp
@@ -39,7 +39,6 @@
#include "ast.h"
#include "ir_optimization.h"
-#include "ir_print_visitor.h"
#include "program.h"
#include "ir_reader.h"
#include "standalone_scaffolding.h"
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 7f8edff..97cd291 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -48,7 +48,6 @@ extern "C" {
}
#include "brw_fs.h"
#include "glsl/glsl_types.h"
-#include "glsl/ir_print_visitor.h"
void
fs_inst::init()
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 9e1cf4a..f390989 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -35,7 +35,6 @@ extern "C" {
#include "brw_fs.h"
#include "brw_cfg.h"
-#include "glsl/ir_print_visitor.h"
fs_generator::fs_generator(struct brw_context *brw,
struct brw_wm_compile *c,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index acd9846..be55533 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -28,7 +28,6 @@
#include "brw_fs.h"
#include "glsl/glsl_types.h"
#include "glsl/ir_optimization.h"
-#include "glsl/ir_print_visitor.h"
static void
assign_reg(int *reg_hw_locations, fs_reg *reg, int reg_width)
diff --git a/src/
[Mesa-dev] [PATCH 1/6] glsl: Make some files safe to include from C
From: Paul Berry
Reviewed-by: Eric Anholt
---
src/glsl/ir.h | 4
src/glsl/ir_hierarchical_visitor.h | 2 ++
src/glsl/ir_visitor.h | 2 ++
3 files changed, 8 insertions(+)
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 6d41501..9442681 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -36,6 +36,8 @@
#include "ir_hierarchical_visitor.h"
#include "main/mtypes.h"
+#ifdef __cplusplus
+
/**
* \defgroup IR Intermediate representation nodes
*
@@ -2050,4 +2052,6 @@ extern char *
prototype_string(const glsl_type *return_type, const char *name,
exec_list *parameters);
+#endif /* __cplusplus */
+
#endif /* IR_H */
diff --git a/src/glsl/ir_hierarchical_visitor.h
b/src/glsl/ir_hierarchical_visitor.h
index 143eb7c..1988ad0 100644
--- a/src/glsl/ir_hierarchical_visitor.h
+++ b/src/glsl/ir_hierarchical_visitor.h
@@ -36,6 +36,7 @@ enum ir_visitor_status {
};
+#ifdef __cplusplus
/**
* Base class of hierarchical visitors of IR instruction trees
*
@@ -181,5 +182,6 @@ void visit_tree(ir_instruction *ir,
ir_visitor_status visit_list_elements(ir_hierarchical_visitor *v, exec_list *l,
bool statement_list = true);
+#endif /* __cplusplus */
#endif /* IR_HIERARCHICAL_VISITOR_H */
diff --git a/src/glsl/ir_visitor.h b/src/glsl/ir_visitor.h
index 4a00155..bd47ef7 100644
--- a/src/glsl/ir_visitor.h
+++ b/src/glsl/ir_visitor.h
@@ -26,6 +26,7 @@
#ifndef IR_VISITOR_H
#define IR_VISITOR_H
+#ifdef __cplusplus
/**
* Abstract base class of visitors of IR instruction trees
*/
@@ -81,5 +82,6 @@ public:
virtual void visit(class ir_constant *) {}
virtual void visit(class ir_call *) {}
};
+#endif /* __cplusplus */
#endif /* IR_VISITOR_H */
--
1.8.3.rc0
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[Mesa-dev] [PATCH 2/6] glsl: Make _mesa_print_ir() available from anything including ir.h.
No more forgetting to #include "ir_print_visitor.h" when doing temporary
debug code, or forgetting and leaving it in after removing your temporary
debug code. Also, available from C code so you don't need to move the
caller to C++ just to call it (see also: ir_to_mesa.cpp).
---
src/glsl/ir.h | 8
src/glsl/ir_print_visitor.cpp | 3 +++
src/glsl/ir_print_visitor.h | 3 ---
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 9442681..1f0dc09 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -2052,6 +2052,14 @@ extern char *
prototype_string(const glsl_type *return_type, const char *name,
exec_list *parameters);
+extern "C" {
#endif /* __cplusplus */
+extern void _mesa_print_ir(struct exec_list *instructions,
+ struct _mesa_glsl_parse_state *state);
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
#endif /* IR_H */
diff --git a/src/glsl/ir_print_visitor.cpp b/src/glsl/ir_print_visitor.cpp
index f01019c..ca973a5 100644
--- a/src/glsl/ir_print_visitor.cpp
+++ b/src/glsl/ir_print_visitor.cpp
@@ -38,6 +38,7 @@ ir_instruction::print(void) const
deconsted->accept(&v);
}
+extern "C" {
void
_mesa_print_ir(exec_list *instructions,
struct _mesa_glsl_parse_state *state)
@@ -69,6 +70,8 @@ _mesa_print_ir(exec_list *instructions,
printf("\n)");
}
+} /* extern "C" */
+
ir_print_visitor::ir_print_visitor()
{
indentation = 0;
diff --git a/src/glsl/ir_print_visitor.h b/src/glsl/ir_print_visitor.h
index 6c308f3..a84056d 100644
--- a/src/glsl/ir_print_visitor.h
+++ b/src/glsl/ir_print_visitor.h
@@ -33,9 +33,6 @@ extern "C" {
#include "program/symbol_table.h"
}
-extern void _mesa_print_ir(exec_list *instructions,
- struct _mesa_glsl_parse_state *state);
-
/**
* Abstract base class of visitors of IR instruction trees
*/
--
1.8.3.rc0
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Re: [Mesa-dev] [PATCH] gen7: fix GPU hang on WebGL texture-size test
Jordan Justen writes: > When rendering to a texture with BaseLevel set, the miptree may be laid > out such that BaseLevel is in level 0 of the miptree (to avoid wasting > memory on unused levels between 0 and BaseLevel-1). In that case, we > have to shift our render target's level down to the appropriate level of > the smaller miptree. > > The WebGL test in combination with a meta code relating to > glGenerateMipmap also triggered a similar failure scenario. > > This GPU hang regression was introduced by c754f7a8. > > Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=65324 > Signed-off-by: Jordan Justen > Cc: Eric Anholt > Cc: Kenneth Graunke > Cc: Paul Berry > --- > Given all of Eric's help, this is probably more his patch than mine... :) Hey, if I'd put in the effort, I would have had a patch on the list first. You win. Reviewed-by: Eric Anholt pgpGltSwnJ7RV.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] gen7: fix GPU hang on WebGL texture-size test
When rendering to a texture with BaseLevel set, the miptree may be laid out such that BaseLevel is in level 0 of the miptree (to avoid wasting memory on unused levels between 0 and BaseLevel-1). In that case, we have to shift our render target's level down to the appropriate level of the smaller miptree. The WebGL test in combination with a meta code relating to glGenerateMipmap also triggered a similar failure scenario. This GPU hang regression was introduced by c754f7a8. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=65324 Signed-off-by: Jordan Justen Cc: Eric Anholt Cc: Kenneth Graunke Cc: Paul Berry --- Given all of Eric's help, this is probably more his patch than mine... :) src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 22ceaa5..620eafe 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -595,7 +595,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, assert(brw->has_surface_tile_offset); - surf[5] = irb->mt_level; + surf[5] = irb->mt_level - irb->mt->first_level; surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) | SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT); -- 1.7.10.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/3] R600/SI: Expand sub for v2i32 and v4i32 for SI
Also add a v2i32 test to the existing v4i32 test.
Note: v2i32 for EG seems slightly out of order based on the normal
ordering. i.e. "SUB_INT * T..." comes before the "SUB_INT T..."
I am not sure if this is correct, but it's how the current R600 back-end
emits the operation order.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 3 +++
test/CodeGen/R600/sub.ll | 37 +++--
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index bf4918a..ea2b123 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -68,6 +68,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::ADD, MVT::v4i32, Expand);
setOperationAction(ISD::ADD, MVT::v2i32, Expand);
+ setOperationAction(ISD::SUB, MVT::v2i32, Expand);
+ setOperationAction(ISD::SUB, MVT::v4i32, Expand);
+
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll
index 12bfba3..10fce6c 100644
--- a/test/CodeGen/R600/sub.ll
+++ b/test/CodeGen/R600/sub.ll
@@ -1,11 +1,36 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
-;CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @test2
+;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;SI-CHECK: @test2
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = sub <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test4
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
%a = load <4 x i32> addrspace(1) * %in
%b = load <4 x i32> addrspace(1) * %b_ptr
--
1.8.1.2
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[Mesa-dev] [PATCH 2/3] R600/SI: Expand add for v2i32 and v4i32
Also add SI tests to existing file and a v2i32 test for both
R600 and SI.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 2 ++
test/CodeGen/R600/add.ll | 37 +++--
2 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index d74f401..bf4918a 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -65,6 +65,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::ADD, MVT::i64, Legal);
setOperationAction(ISD::ADD, MVT::i32, Legal);
+ setOperationAction(ISD::ADD, MVT::v4i32, Expand);
+ setOperationAction(ISD::ADD, MVT::v2i32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll
index 185998b..dd590e5 100644
--- a/test/CodeGen/R600/add.ll
+++ b/test/CodeGen/R600/add.ll
@@ -1,11 +1,36 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK
%s
+; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
-;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @test2
+;EG-CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], literal\.[xyzw]}}
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;SI-CHECK: @test2
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = add <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test4
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
%a = load <4 x i32> addrspace(1) * %in
%b = load <4 x i32> addrspace(1) * %b_ptr
--
1.8.1.2
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[Mesa-dev] [PATCH 1/3] R600: Expand v2i32 load/store instead of custom lowering
The custom lowering causes llc to crash with a segfault.
Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without crashing.
Signed-off-by: Aaron Watry
---
lib/Target/R600/R600ISelLowering.cpp | 4 ++--
test/CodeGen/R600/load.vec.ll| 6 ++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/lib/Target/R600/R600ISelLowering.cpp
b/lib/Target/R600/R600ISelLowering.cpp
index 9cedadb..812df83 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -86,7 +86,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
// Legalize loads and stores to the private address space.
setOperationAction(ISD::LOAD, MVT::i32, Custom);
- setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
+ setOperationAction(ISD::LOAD, MVT::v2i32, Expand);
setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
@@ -94,7 +94,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom);
setOperationAction(ISD::STORE, MVT::i8, Custom);
setOperationAction(ISD::STORE, MVT::i32, Custom);
- setOperationAction(ISD::STORE, MVT::v2i32, Custom);
+ setOperationAction(ISD::STORE, MVT::v2i32, Expand);
setOperationAction(ISD::STORE, MVT::v4i32, Custom);
setOperationAction(ISD::LOAD, MVT::i32, Custom);
diff --git a/test/CodeGen/R600/load.vec.ll b/test/CodeGen/R600/load.vec.ll
index 08e034e..da1149a 100644
--- a/test/CodeGen/R600/load.vec.ll
+++ b/test/CodeGen/R600/load.vec.ll
@@ -1,6 +1,10 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK
%s
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
; load a v2i32 value from the global address space.
+; EG-CHECK: @load_v2i32
+; EG-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4
+; EG-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
; SI-CHECK: @load_v2i32
; SI-CHECK: BUFFER_LOAD_DWORDX2 VGPR{{[0-9]+}}
define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)*
%in) {
@@ -10,6 +14,8 @@ define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x
i32> addrspace(1)* %i
}
; load a v4i32 value from the global address space.
+; EG-CHECK: @load_v4i32
+; EG-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0
; SI-CHECK: @load_v4i32
; SI-CHECK: BUFFER_LOAD_DWORDX4 VGPR{{[0-9]+}}
define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)*
%in) {
--
1.8.1.2
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[Mesa-dev] R600: Various fixes for R600 and SI
First patch fixes load/store for v2i32 on R600. Without this, the other two will cause make check failures. I've verified the changes using a Radeon 5400 (Cedar). Note that the previous custom lowering of v2i32 store was causing silent data corruption. The other two patches expand add/sub on SI for both v2i32 and v4i32 types. There's lit tests for v2i32 that have been added. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/vs: Combine code generation's inst->opcode switch statements.
Kenneth Graunke writes: > vec4_visitor::generate_code() switches on vec4_instruction::opcode and > calls into the brw_eu_emit.c layer to generate code for some of them. > It then has a default case which calls generate_vec4_instruction() to > handle the rest...which switches on opcode and handles the rest of the > cases. Reviewed-by: Eric Anholt pgpg4qszra5ka.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] prog_parameter.c ASAN Patch
Sure. I was under the impression that |size| couldn't be both greater than
4 and a non-multiple of 4, but I've reworked the patch to incorporate this
and to be a little more straightforward.
Is the only way to replace "ASAN" with "Address Sanitizer" to change the
subject of this email thread?
Anyway, here's a similar but modified patch:
From: Myles C. Maxfield
Date: Mon, 17 Jun 2013 11:50:05 -0700
Subject: [PATCH] Appeasing Address Sanitizer
---
src/mesa/program/prog_parameter.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/mesa/program/prog_parameter.c
b/src/mesa/program/prog_parameter.c
index 95b153e..1d46476 100644
--- a/src/mesa/program/prog_parameter.c
+++ b/src/mesa/program/prog_parameter.c
@@ -155,7 +155,18 @@ _mesa_add_parameter(struct gl_program_parameter_list
*paramList,
p->Size = size;
p->DataType = datatype;
if (values) {
-COPY_4V(paramList->ParameterValues[oldNum + i], values);
+if (size >= (i+1)*4) {
+COPY_4V(paramList->ParameterValues[oldNum + i], values);
+} else {
+/* silence asan */
+for (j = 0; j < 4; j++) {
+if (i*4+j < size) {
+paramList->ParameterValues[oldNum + i][j] =
values[i*4+j];
+} else {
+paramList->ParameterValues[oldNum + i][j].f = 0.0f;
+}
+}
+}
values += 4;
p->Initialized = GL_TRUE;
}
--
1.7.12.4 (Apple Git-37)
On Mon, Jun 17, 2013 at 8:13 AM, Brian Paul wrote:
> On 06/14/2013 05:12 PM, Myles C. Maxfield wrote:
>
>> Sorry for the triple post; I received a bounce email the first time and
>> got sent to the spam folder the second time, so I'm trying a third time.
>>
>> Hello, all. I was running Mesa with Address Sanitizer [1] turned on, and
>> found one place where ASAN pointed out a read-before-initialized problem.
>> In particular, in _mesa_add_parameter, in prog_parameter.c, |values|
>> represents an array holding a variable number of values. These values get
>> copied out of the array 4 at a time with the COPY_4V macro, however, the
>> array might only contain a single element. In this case, ASAN reports a
>> read-before-initialize because the last 3 of the 4 elements haven't been
>> written to yet. I was hoping to contribute a patch that will silence this
>> problem that ASAN reports. I'm happy to incorporate any feedback anyone has
>> into this patch.
>>
>> Thanks,
>> Myles C. Maxfield
>>
>> [1]https://code.google.com/p/**address-sanitizer/
Re: [Mesa-dev] [PATCH 03/13] gallium: Introduce 32-bit bytewise format names
Jose Fonseca writes:
> - Original Message -
>> On Sun, 2013-06-16 at 10:22 -0700, Jose Fonseca wrote:
>>
>> > Ok. I think this patch series is sound from an implementation POV. I
>> > see no point in delaying further. We can tweak things afterwards if
>> > deemed necessary.
>> >
>> > Lets squash the commits, rename the XYZW formats to go from
>> > low->high bit, and commit this into master.
Thanks.
>> Just so I'm clear, when you say "go from low to high bit", you mean that
>> in the new format names the first component in the name maps to the
>> least-significant bits in memory, thus:
>>
>> #if defined(PIPE_ARCH_LITTLE_ENDIAN)
>> #define PIPE_FORMAT_RGBA_UNORM PIPE_FORMAT_R8G8B8A8_UNORM
>> #elif defined(PIPE_ARCH_BIG_ENDIAN)
>> #define PIPE_FORMAT_RGBA_UNORM PIPE_FORMAT_A8B8G8R8_UNORM
>> #endif
>>
>> If I have this correct I'll send out a corrected series so we can get
>> this landed.
>
> Yep. That seems correct to me.
>
> PIPE_FORMAT_XYZW_UNORM goes from least to most significant bit in
> integer: uint32 color = (X << 0) | (Y << 8) | ...
>
> PIPE_FORMAT_X8Y8Z8W8_UNORM matches memory ordering: uint8 color[4] =
> {X, Y, Z, W};
>
>> (The patch series as given plugs the XYZW formats into enum
>> pipe_format; I think it'd be clearer to do the #define the other way
>> around at the end, as I have it above, since that way enum pipe_format
>> remains endian-independent.)
>
> I didn't want to nitpick any further than I already have so far, but I
> agree with you entirely.
What do you think about the alternative "util: big-endian fixes for
format generator" implementation of the python bits:
http://lists.freedesktop.org/archives/mesa-dev/2013-June/040594.html
? Would it be OK to use that instead of the original? I have some
follow-up patches for things like the zs, 565 and 10/10/10/2 formats
that apply on top of that series.
Thanks,
Richard
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Re: [Mesa-dev] [PATCH 03/13] gallium: Introduce 32-bit bytewise format names
- Original Message -
> On Sun, 2013-06-16 at 10:22 -0700, Jose Fonseca wrote:
>
> > Ok. I think this patch series is sound from an implementation POV. I
> > see no point in delaying further. We can tweak things afterwards if
> > deemed necessary.
> >
> > Lets squash the commits, rename the XYZW formats to go from
> > low->high bit, and commit this into master.
>
> Just so I'm clear, when you say "go from low to high bit", you mean that
> in the new format names the first component in the name maps to the
> least-significant bits in memory, thus:
>
> #if defined(PIPE_ARCH_LITTLE_ENDIAN)
> #define PIPE_FORMAT_RGBA_UNORM PIPE_FORMAT_R8G8B8A8_UNORM
> #elif defined(PIPE_ARCH_BIG_ENDIAN)
> #define PIPE_FORMAT_RGBA_UNORM PIPE_FORMAT_A8B8G8R8_UNORM
> #endif
>
> If I have this correct I'll send out a corrected series so we can get
> this landed.
Yep. That seems correct to me.
PIPE_FORMAT_XYZW_UNORM goes from least to most significant bit in
integer: uint32 color = (X << 0) | (Y << 8) | ...
PIPE_FORMAT_X8Y8Z8W8_UNORM matches memory ordering: uint8 color[4] = {X, Y,
Z, W};
> (The patch series as given plugs the XYZW formats into enum
> pipe_format; I think it'd be clearer to do the #define the other way
> around at the end, as I have it above, since that way enum pipe_format
> remains endian-independent.)
I didn't want to nitpick any further than I already have so far, but I agree
with you entirely.
Jose
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Re: [Mesa-dev] [PATCH] texobj: add verbose api trace messages to several routines
José Fonseca writes: >> Do you know why this is? > > No, I don't have a clear understanding. OK. Thanks for letting me know. >> I'd definitely be interested in making apitrace work more transparently > here. > > Me too. But there are so many apps that only work well with > LD_LIBRARY_PATH, that make think that the best way forward is not to keep > adding hacks for LD_PRELOAD to work, but rather making apitrace seemingly > use LD_LIBRARY_PATH out of the box. Yes. Given that one approach is observed to work, and one is observed to fail for unknown reasons, it makes sense to transparently use the known-to-work approach. -Carl -- carl.d.wo...@intel.com pgpbSqfY2CraQ.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 03/13] gallium: Introduce 32-bit bytewise format names
On Sun, 2013-06-16 at 10:22 -0700, Jose Fonseca wrote: > Ok. I think this patch series is sound from an implementation POV. I > see no point in delaying further. We can tweak things afterwards if > deemed necessary. > > Lets squash the commits, rename the XYZW formats to go from > low->high bit, and commit this into master. Just so I'm clear, when you say "go from low to high bit", you mean that in the new format names the first component in the name maps to the least-significant bits in memory, thus: #if defined(PIPE_ARCH_LITTLE_ENDIAN) #define PIPE_FORMAT_RGBA_UNORM PIPE_FORMAT_R8G8B8A8_UNORM #elif defined(PIPE_ARCH_BIG_ENDIAN) #define PIPE_FORMAT_RGBA_UNORM PIPE_FORMAT_A8B8G8R8_UNORM #endif If I have this correct I'll send out a corrected series so we can get this landed. (The patch series as given plugs the XYZW formats into enum pipe_format; I think it'd be clearer to do the #define the other way around at the end, as I have it above, since that way enum pipe_format remains endian-independent.) - ajax ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallium: replace bswap_32 calls with util_bswap32
On Mon, 2013-06-17 at 01:11 +1000, Jonathan Gray wrote: > byteswap.h and bswap_32 aren't portable, replace them with calls to > gallium's util_bswap32 as suggested by Mark Kettenis. Lets these files > build on OpenBSD. > > Signed-off-by: Jonathan Gray Pushed, thanks! -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Debian, X and DRI developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] prog_parameter.c ASAN Patch
On 06/14/2013 05:12 PM, Myles C. Maxfield wrote:
Sorry for the triple post; I received a bounce email the first time and got
sent to the spam folder the second time, so I'm trying a third time.
Hello, all. I was running Mesa with Address Sanitizer [1] turned on, and found
one place where ASAN pointed out a read-before-initialized problem. In
particular, in _mesa_add_parameter, in prog_parameter.c, |values| represents an
array holding a variable number of values. These values get copied out of the
array 4 at a time with the COPY_4V macro, however, the array might only contain
a single element. In this case, ASAN reports a read-before-initialize because
the last 3 of the 4 elements haven't been written to yet. I was hoping to
contribute a patch that will silence this problem that ASAN reports. I'm happy
to incorporate any feedback anyone has into this patch.
Thanks,
Myles C. Maxfield
[1]https://code.google.com/p/address-sanitizer/
diff --git a/src/mesa/program/prog_parameter.c
b/src/mesa/program/prog_parameter.c
index 2018fa5..63915fb 100644
--- a/src/mesa/program/prog_parameter.c
+++ b/src/mesa/program/prog_parameter.c
@@ -158,7 +158,17 @@ _mesa_add_parameter(struct gl_program_parameter_list
*paramList,
p->DataType = datatype;
p->Flags = flags;
if (values) {
-COPY_4V(paramList->ParameterValues[oldNum + i], values);
+if (size & 3) {
+ for (j = 0; j < size; j++) {
+paramList->ParameterValues[oldNum + i][j] = values[j];
+ }
+ /* silence asan */
+ for (j = size; j < 4; j++) {
+paramList->ParameterValues[oldNum + i][j].f = 0;
+ }
+} else {
+ COPY_4V(paramList->ParameterValues[oldNum + i], values);
+}
values += 4;
p->Initialized = GL_TRUE;
}
The value of 'size' can actually be greater than 4 (IIRC, and the
function comment are still correct). For example, for a matrix,
size=16. So the first for-loop should be fixed, just to be safe.
In the commit message, let's not use "ASAN" since it's not obvious that
it means Address Sanitizer.
-Brian
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Re: [Mesa-dev] [PATCH] tgsi_test: fix parsing of array in declaration
On 06/16/2013 05:24 AM, Dave Airlie wrote:
I noticed this code didn't work as advertised while doing some passing around
of TGSI shaders and trying to reparse them, and things failing.
This seems to fix it here for at least the small test case I hacked into a
graw test.
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi/tgsi_text.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c
b/src/gallium/auxiliary/tgsi/tgsi_text.c
index 688c5bc..4c5ae4f 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -1129,8 +1129,13 @@ static boolean parse_declaration( struct translate_ctx
*ctx )
cur2 = cur;
cur2++;
eat_opt_white( &cur2 );
- if (str_match_nocase_whole( &cur2, "ARRAY(" )) {
+ if (str_match_nocase_whole( &cur2, "ARRAY" )) {
int arrayid;
+ if (*cur2 != '(') {
+report_error( ctx, "Expected `('" );
+return FALSE;
+ }
+ cur2++;
eat_opt_white( &cur2 );
if (!parse_int( &cur2, &arrayid )) {
report_error( ctx, "Expected `,'" );
@@ -1138,12 +1143,13 @@ static boolean parse_declaration( struct translate_ctx
*ctx )
}
eat_opt_white( &cur2 );
if (*cur2 != ')') {
-report_error( ctx, "Expected `,'" );
+report_error( ctx, "Expected `)'" );
return FALSE;
}
+ cur2++;
decl.Declaration.Array = 1;
decl.Array.ArrayID = arrayid;
- cur = cur2;
+ ctx->cur = cur = cur2;
}
}
LGTM.
Reviewed-by: Brian Paul
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Re: [Mesa-dev] llvm compiler cache
On 06/16/2013 11:57 AM, Frank Henigman wrote: This works (has been in Chrome OS for a while) but only for vertex shaders, not geometry shaders nor llvmpipe. I'm afraid I'm completely ignorant about AMD drivers. This applies on top of my recently posted memory saving patches. Without them the cache would take up too much memory, ~1MB per item compared to ~10KB. If this is interesting to anyone maybe it can be pushed farther down and leveraged by geometry shaders, llvmpipe, and more. I don't know how much other apps care but it's a big win for Chrome because just opening an empty tab recompiles some shaders and takes hundreds of milliseconds on a low-end chromebook. Revisiting a page with a bunch of shaders is seconds faster. Only works with JIT right now, not MCJIT which is perhaps the future. I see in LLVM 3.3 they've added some kind of caching to MCJIT. My cache comes in before generating LLVM source however, thus should have bigger savings than can be realized at the LLVM level. Thanks in advance for any comments, and thanks to Jose Fonseca for some earlier suggestions. All shortcomings are purely my fault however. I just took a quick look at the code for now (I might have time for a closer review later). 1. I wonder if this new cache-related code should go into a new draw_llvm_cache.c file. 2. We have a pipe_reference type for reference counting objects that you might want to use. 3. The code looks a bit light on comments. You might want to scan the code and put comments on anything that's not obvious. For example, what does LLVM_CACHE_MAX_UNUSED mean? Thanks. -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallium: add condition parameter to render_condition
Looks good to me.
Jose
- Original Message -
> From: Roland Scheidegger
>
> For conditional rendering this makes it possible to skip rendering
> if either the predicate is true or false, as supported by d3d10
> (in fact previously it was sort of implied skip rendering if predicate
> is false for occlusion predicate, and true for so_overflow predicate).
> There's no cap bit for this as presumably all drivers could do it trivially
> (but this patch does not implement it for the drivers using true
> hw predicates, nvxx, r600, radeonsi, no change is expected for OpenGL
> functionality).
> ---
> src/gallium/auxiliary/cso_cache/cso_context.c | 13 ++---
> src/gallium/auxiliary/cso_cache/cso_context.h |3 ++-
> src/gallium/auxiliary/hud/hud_context.c |2 +-
> src/gallium/auxiliary/postprocess/pp_run.c|2 +-
> src/gallium/auxiliary/util/u_blit.c |2 +-
> src/gallium/auxiliary/util/u_blitter.c|3 ++-
> src/gallium/auxiliary/util/u_blitter.h|3 +++
> src/gallium/auxiliary/util/u_gen_mipmap.c |2 +-
> src/gallium/docs/source/context.rst | 14 +-
> src/gallium/drivers/galahad/glhd_context.c|3 ++-
> src/gallium/drivers/ilo/ilo_3d.c |4 +++-
> src/gallium/drivers/ilo/ilo_3d.h |1 +
> src/gallium/drivers/llvmpipe/lp_context.c |2 ++
> src/gallium/drivers/llvmpipe/lp_context.h |1 +
> src/gallium/drivers/llvmpipe/lp_query.c |3 ++-
> src/gallium/drivers/llvmpipe/lp_surface.c |2 +-
> src/gallium/drivers/nv30/nv30_context.h |1 +
> src/gallium/drivers/nv30/nv30_miptree.c |2 +-
> src/gallium/drivers/nv30/nv30_query.c |4 +++-
> src/gallium/drivers/nv50/nv50_context.h |1 +
> src/gallium/drivers/nv50/nv50_query.c |4 +++-
> src/gallium/drivers/nv50/nv50_surface.c |2 +-
> src/gallium/drivers/nvc0/nvc0_context.h |1 +
> src/gallium/drivers/nvc0/nvc0_query.c |4 +++-
> src/gallium/drivers/nvc0/nvc0_surface.c |2 +-
> src/gallium/drivers/r300/r300_query.c |7 ---
> src/gallium/drivers/r600/r600_blit.c |1 +
> src/gallium/drivers/r600/r600_pipe.c |6 --
> src/gallium/drivers/r600/r600_pipe.h |1 +
> src/gallium/drivers/r600/r600_query.c |2 ++
> src/gallium/drivers/radeonsi/r600_blit.c |4 +++-
> src/gallium/drivers/radeonsi/r600_query.c |4 +++-
> src/gallium/drivers/radeonsi/radeonsi_pipe.c |6 --
> src/gallium/drivers/radeonsi/radeonsi_pipe.h |2 ++
> src/gallium/drivers/softpipe/sp_context.c |2 ++
> src/gallium/drivers/softpipe/sp_context.h |1 +
> src/gallium/drivers/softpipe/sp_query.c |2 +-
> src/gallium/drivers/softpipe/sp_surface.c |2 +-
> src/gallium/drivers/svga/svga_pipe_blit.c |2 +-
> src/gallium/drivers/trace/tr_context.c|4 +++-
> src/gallium/include/pipe/p_context.h |2 ++
> src/mesa/state_tracker/st_cb_condrender.c |6 +++---
> 42 files changed, 95 insertions(+), 40 deletions(-)
>
> diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c
> b/src/gallium/auxiliary/cso_cache/cso_context.c
> index b06a070..6805427 100644
> --- a/src/gallium/auxiliary/cso_cache/cso_context.c
> +++ b/src/gallium/auxiliary/cso_cache/cso_context.c
> @@ -111,6 +111,7 @@ struct cso_context {
> void *velements, *velements_saved;
> struct pipe_query *render_condition, *render_condition_saved;
> uint render_condition_mode, render_condition_mode_saved;
> + boolean render_condition_cond, render_condition_cond_saved;
>
> struct pipe_clip_state clip;
> struct pipe_clip_state clip_saved;
> @@ -723,13 +724,17 @@ void cso_restore_stencil_ref(struct cso_context *ctx)
> }
>
> void cso_set_render_condition(struct cso_context *ctx,
> - struct pipe_query *query, uint mode)
> + struct pipe_query *query,
> + boolean condition, uint mode)
> {
> struct pipe_context *pipe = ctx->pipe;
>
> - if (ctx->render_condition != query || ctx->render_condition_mode != mode)
> {
> - pipe->render_condition(pipe, query, mode);
> + if (ctx->render_condition != query ||
> + ctx->render_condition_mode != mode ||
> + ctx->render_condition_cond != condition) {
> + pipe->render_condition(pipe, query, condition, mode);
>ctx->render_condition = query;
> + ctx->render_condition_cond = condition;
>ctx->render_condition_mode = mode;
> }
> }
> @@ -737,12 +742,14 @@ void cso_set_render_condition(struct cso_context *ctx,
> void cso_save_render_condition(struct cso_context *ctx)
> {
> ctx->render_condition_saved = ctx->render_condition;
> + ctx->render_condition_cond_saved = ctx->render_condition_cond;
> ctx->render_condition_mode_saved =
Re: [Mesa-dev] R600: Bugfixes
On Mon, Jun 17, 2013 at 06:43:09AM -0700, Vincent Lejeune wrote: > Hi, > > these patches fix 2 bugs in R600 backend. > The first one use the rv710/rv730 correct encoding for TEX clause with more > than 8 instructions. > This bug has been spoted there : > > https://bugs.freedesktop.org/show_bug.cgi?id=64257 > The other patch fix a typo that causes instructions not to use PV/PS register > when R600Packetizers evaluates read port limitations. > It prevents some bundling opportunities in some (not so frequent) situation. > > Vincent Both patches are Reviewed-by: Tom Stellard Can you add the bugzilla link to the commit message of patch #1 ? -Tom > ___ > llvm-commits mailing list > llvm-comm...@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] R600: Bugfixes
On Mon, Jun 17, 2013 at 9:43 AM, Vincent Lejeune wrote: > Hi, > > these patches fix 2 bugs in R600 backend. > The first one use the rv710/rv730 correct encoding for TEX clause with more > than 8 instructions. > This bug has been spoted there : > > https://bugs.freedesktop.org/show_bug.cgi?id=64257 > The other patch fix a typo that causes instructions not to use PV/PS register > when R600Packetizers evaluates read port limitations. > It prevents some bundling opportunities in some (not so frequent) situation. Reviewed-by: Alex Deucher ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] R600: Bugfixes
Hi, these patches fix 2 bugs in R600 backend. The first one use the rv710/rv730 correct encoding for TEX clause with more than 8 instructions. This bug has been spoted there : https://bugs.freedesktop.org/show_bug.cgi?id=64257 The other patch fix a typo that causes instructions not to use PV/PS register when R600Packetizers evaluates read port limitations. It prevents some bundling opportunities in some (not so frequent) situation. Vincent 0001-R600-Properly-set-COUNT_3-bit-in-TEX-clause-initiati.patch Description: Binary data 0002-R600-PV-stores-Reg-id-not-index.patch Description: Binary data ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 63435] [Regression since 9.0] Flickering in EGL OpenGL full-screen window with swap interval 1
https://bugs.freedesktop.org/show_bug.cgi?id=63435 Stefan Dirsch changed: What|Removed |Added CC||sndir...@suse.de -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallium: replace bswap_32 calls with util_bswap32
On Mon, Jun 17, 2013 at 07:47:11AM +0200, Michel Dänzer wrote: > On Mon, 2013-06-17 at 01:11 +1000, Jonathan Gray wrote: > > byteswap.h and bswap_32 aren't portable, replace them with calls to > > gallium's util_bswap32 as suggested by Mark Kettenis. Lets these files > > build on OpenBSD. > > > > Signed-off-by: Jonathan Gray > > Reviewed-by: Michel Dänzer > > Do you need someone to apply this for you? Yes, I don't have access. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
