[Mesa-dev] [PATCH 07/11] intel: Stop doing special _NEW_STENCIL state flagging on drawbuffers.
2/3 packets depending on Stencil._Enabled already checked for
_NEW_BUFFERS, so just add _NEW_BUFFERS to the remaining one.
---
src/mesa/drivers/dri/i965/brw_cc.c| 4 ++--
src/mesa/drivers/dri/i965/brw_vtbl.c | 7 +--
src/mesa/drivers/dri/i965/brw_wm.c| 2 +-
src/mesa/drivers/dri/i965/gen6_depthstencil.c | 2 +-
4 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c
b/src/mesa/drivers/dri/i965/brw_cc.c
index 71f9366..698af6d 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -104,7 +104,7 @@ static void upload_cc_unit(struct brw_context *brw)
sizeof(*cc), 64, &brw->cc.state_offset);
memset(cc, 0, sizeof(*cc));
- /* _NEW_STENCIL */
+ /* _NEW_STENCIL | _NEW_BUFFERS */
if (ctx->Stencil._Enabled) {
const unsigned back = ctx->Stencil._BackFace;
@@ -230,7 +230,7 @@ static void upload_cc_unit(struct brw_context *brw)
const struct brw_tracked_state brw_cc_unit = {
.dirty = {
- .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH,
+ .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH | _NEW_BUFFERS,
.brw = BRW_NEW_BATCH | BRW_NEW_STATS_WM,
.cache = CACHE_NEW_CC_VP
},
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c
b/src/mesa/drivers/dri/i965/brw_vtbl.c
index a47b7a3..2c71c08 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -130,12 +130,7 @@ brw_update_draw_buffer(struct intel_context *intel)
return;
}
- /* Mesa's Stencil._Enabled field is updated when
-* _NEW_BUFFERS | _NEW_STENCIL, but i965 code assumes that the value
-* only changes with _NEW_STENCIL (which seems sensible). So flag it
-* here since this is the _NEW_BUFFERS path.
-*/
- intel->NewGLState |= (_NEW_DEPTH | _NEW_STENCIL);
+ intel->NewGLState |= _NEW_DEPTH;
/* The driver uses this in places that need to look up
* renderbuffers' buffer objects.
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c
b/src/mesa/drivers/dri/i965/brw_wm.c
index 60dc14a..6eb4a1d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -379,7 +379,7 @@ static void brw_wm_populate_key( struct brw_context *brw,
if (ctx->Depth.Test && ctx->Depth.Mask) /* ?? */
lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
- /* _NEW_STENCIL */
+ /* _NEW_STENCIL | _NEW_BUFFERS */
if (ctx->Stencil._Enabled) {
lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index a8dbc62..8c47147 100644
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -47,7 +47,7 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
&brw->cc.depth_stencil_state_offset);
memset(ds, 0, sizeof(*ds));
- /* _NEW_STENCIL */
+ /* _NEW_STENCIL | _NEW_BUFFERS */
if (ctx->Stencil._Enabled) {
int back = ctx->Stencil._BackFace;
--
1.8.3.rc0
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[Mesa-dev] [PATCH 10/11] i965: Stop updating FBO state on drawbuffers change.
The computed fields are updated appropriately as part of the normal draw
call path due to _NEW_BUFFERS being set.
---
src/mesa/drivers/dri/i965/brw_vtbl.c | 8
1 file changed, 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c
b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 4bf1ba9..16d1bd1 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -112,14 +112,6 @@ brw_update_draw_buffer(struct intel_context *intel)
return;
}
- /* Do this here, not core Mesa, since this function is called from
-* many places within the driver.
-*/
- if (ctx->NewState & _NEW_BUFFERS) {
- /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
- _mesa_update_framebuffer(ctx);
- }
-
if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
/* this may occur when we're called by glBindFrameBuffer() during
* the process of someone setting up renderbuffers, etc.
--
1.8.3.rc0
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[Mesa-dev] [PATCH 08/11] i965: Remove _NEW_DEPTH state flagging on drawbuffers change.
Of the places noting a _NEW_DEPTH dependency, all were already checking for _NEW_BUFFERS if appropriate. --- src/mesa/drivers/dri/i965/brw_vtbl.c| 2 -- src/mesa/drivers/dri/i965/gen7_misc_state.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 2c71c08..99d661f 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -130,8 +130,6 @@ brw_update_draw_buffer(struct intel_context *intel) return; } - intel->NewGLState |= _NEW_DEPTH; - /* The driver uses this in places that need to look up * renderbuffers' buffer objects. */ diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 12b752c..539fc32 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -44,7 +44,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, intel_emit_depth_stall_flushes(intel); - /* _NEW_DEPTH, _NEW_STENCIL */ + /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */ BEGIN_BATCH(7); OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); OUT_BATCH((depth_mt ? depth_mt->region->pitch - 1 : 0) | -- 1.8.3.rc0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 11/11] i965: Remove the rest of brw_update_draw_buffer().
The last piece of code with an effect was flagging _NEW_BUFFERS. Only,
that is already flagged from everything that calls this function: Mesa GL
state updates flag it before even calling down into the driver, and the
calls from the DRI2 window system framebuffer update path end up flagging
it as part of the ResizeBuffers() hook.
---
src/mesa/drivers/dri/i965/brw_vtbl.c | 32 +---
1 file changed, 5 insertions(+), 27 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c
b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 16d1bd1..5bc4eb2 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -92,38 +92,16 @@ static void brw_destroy_context( struct intel_context
*intel )
}
/**
- * Update the hardware state for drawing into a window or framebuffer object.
+ * Stub state update function for i915.
*
- * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
- * places within the driver.
- *
- * Basically, this needs to be called any time the current framebuffer
- * changes, the renderbuffers change, or we need to draw into different
- * color buffers.
+ * In i915, hardware state updates for drawbuffer changes are driven by
+ * driver-internal calls to GL state update hooks. In i965, we recompute the
+ * apporpriate state at draw time as a result of _NEW_BUFFERS being set, so we
+ * don't need this hook.
*/
static void
brw_update_draw_buffer(struct intel_context *intel)
{
- struct gl_context *ctx = &intel->ctx;
- struct gl_framebuffer *fb = ctx->DrawBuffer;
-
- if (!fb) {
- /* this can happen during the initial context initialization */
- return;
- }
-
- if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
- /* this may occur when we're called by glBindFrameBuffer() during
- * the process of someone setting up renderbuffers, etc.
- */
- /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
- return;
- }
-
- /* The driver uses this in places that need to look up
-* renderbuffers' buffer objects.
-*/
- intel->NewGLState |= _NEW_BUFFERS;
}
/**
--
1.8.3.rc0
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[Mesa-dev] [PATCH 09/11] i965: Stop recomputing drawbuffer bounds on drawbuffer change.
For winsys FBOs, the bounds are appropriately updated immediately upon
_mesa_resize_framebuffer(). For user FBOs, they're updated as part of the
normal draw path state update due to _NEW_BUFFERS having been flagged.
---
src/mesa/drivers/dri/i965/brw_vtbl.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c
b/src/mesa/drivers/dri/i965/brw_vtbl.c
index 99d661f..4bf1ba9 100644
--- a/src/mesa/drivers/dri/i965/brw_vtbl.c
+++ b/src/mesa/drivers/dri/i965/brw_vtbl.c
@@ -118,8 +118,6 @@ brw_update_draw_buffer(struct intel_context *intel)
if (ctx->NewState & _NEW_BUFFERS) {
/* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
_mesa_update_framebuffer(ctx);
- /* this updates the DrawBuffer's Width/Height if it's a FBO */
- _mesa_update_draw_buffer_bounds(ctx);
}
if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
--
1.8.3.rc0
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[Mesa-dev] [PATCH 06/11] i965: Stop flagging viewport/scissor change on drawbuffers change.
The viewport (ctx->Viewport._WindowMap) doesn't change with drawable size changes, and we update scissor (ctx->DrawBuffer->_Xmin and friends) on _NEW_BUFFERS in things like brw_sf_state.c. --- src/mesa/drivers/dri/i965/brw_vtbl.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index ba5fadf..a47b7a3 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -141,9 +141,6 @@ brw_update_draw_buffer(struct intel_context *intel) * renderbuffers' buffer objects. */ intel->NewGLState |= _NEW_BUFFERS; - - /* update viewport/scissor since it depends on window size */ - intel->NewGLState |= _NEW_VIEWPORT | _NEW_SCISSOR; } /** -- 1.8.3.rc0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 04/11] radeon: Remove gratuitous custom framebuffer resize code.
_mesa_resize_framebuffer(), the default value of the ResizeBuffers hook,
already checks for a window system framebuffer and walks the renderbuffers
calling AllocStorage().
---
src/mesa/drivers/dri/radeon/radeon_fbo.c | 31 ---
1 file changed, 31 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c
b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index 29a6d79..1e6cd1b 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -621,36 +621,6 @@ radeon_alloc_window_storage(struct gl_context * ctx,
struct gl_renderbuffer *rb,
return GL_TRUE;
}
-
-static void
-radeon_resize_buffers(struct gl_context *ctx, struct gl_framebuffer *fb,
-GLuint width, GLuint height)
-{
- struct radeon_framebuffer *radeon_fb = (struct radeon_framebuffer*)fb;
- int i;
-
- radeon_print(RADEON_TEXTURE, RADEON_TRACE,
- "%s(%p, fb %p) \n",
- __func__, ctx, fb);
-
- _mesa_resize_framebuffer(ctx, fb, width, height);
-
- if (fb->Name != 0) {
- return;
- }
-
- /* Make sure all window system renderbuffers are up to date */
- for (i = 0; i < 2; i++) {
- struct gl_renderbuffer *rb = &radeon_fb->color_rb[i]->base.Base;
-
- /* only resize if size is changing */
- if (rb && (rb->Width != width || rb->Height != height)) {
-rb->AllocStorage(ctx, rb, rb->InternalFormat, width, height);
- }
- }
-}
-
-
/** Dummy function for gl_renderbuffer::AllocStorage() */
static GLboolean
radeon_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
@@ -903,7 +873,6 @@ void radeon_fbo_init(struct radeon_context *radeon)
radeon->glCtx.Driver.FramebufferRenderbuffer =
radeon_framebuffer_renderbuffer;
radeon->glCtx.Driver.RenderTexture = radeon_render_texture;
radeon->glCtx.Driver.FinishRenderTexture = radeon_finish_render_texture;
- radeon->glCtx.Driver.ResizeBuffers = radeon_resize_buffers;
radeon->glCtx.Driver.ValidateFramebuffer = radeon_validate_framebuffer;
radeon->glCtx.Driver.BlitFramebuffer = _mesa_meta_BlitFramebuffer;
radeon->glCtx.Driver.EGLImageTargetRenderbufferStorage =
--
1.8.3.rc0
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[Mesa-dev] [PATCH 05/11] i965: Stop flagging _NEW_POLYGON on drawbuffers change.
Things like brw_sf.c that need to know about orientation are already recomputing on _NEW_BUFFERS. --- src/mesa/drivers/dri/i965/brw_vtbl.c | 5 - 1 file changed, 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 96a6cd5..ba5fadf 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -144,11 +144,6 @@ brw_update_draw_buffer(struct intel_context *intel) /* update viewport/scissor since it depends on window size */ intel->NewGLState |= _NEW_VIEWPORT | _NEW_SCISSOR; - - /* Update culling direction which changes depending on the -* orientation of the buffer: -*/ - intel->NewGLState |= _NEW_POLYGON; } /** -- 1.8.3.rc0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 02/11] mesa: Remove the Initialized field from framebuffers.
This existed to tell the core not to call GetBufferSize, except that even
if you didn't set it nothing happened because nobody had a GetBufferSize.
---
src/mesa/drivers/dri/intel/intel_fbo.c | 2 --
src/mesa/drivers/dri/radeon/radeon_common.c | 2 --
src/mesa/drivers/dri/radeon/radeon_fbo.c| 2 --
src/mesa/main/mtypes.h | 2 --
src/mesa/state_tracker/st_manager.c | 2 --
5 files changed, 10 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 5fe3dc7..32d1797 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -339,8 +339,6 @@ intel_resize_buffers(struct gl_context *ctx, struct
gl_framebuffer *fb,
_mesa_resize_framebuffer(ctx, fb, width, height);
- fb->Initialized = true; /* XXX remove someday */
-
if (_mesa_is_user_fbo(fb)) {
return;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c
b/src/mesa/drivers/dri/radeon/radeon_common.c
index 0cf656b..0f0945d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -85,7 +85,6 @@ void radeonSetCliprects(radeonContextPtr radeon)
(draw_rfb->base.Height != drawable->h)) {
_mesa_resize_framebuffer(&radeon->glCtx, &draw_rfb->base,
drawable->w, drawable->h);
- draw_rfb->base.Initialized = GL_TRUE;
}
if (drawable != readable) {
@@ -93,7 +92,6 @@ void radeonSetCliprects(radeonContextPtr radeon)
(read_rfb->base.Height != readable->h)) {
_mesa_resize_framebuffer(&radeon->glCtx,
&read_rfb->base,
readable->w, readable->h);
- read_rfb->base.Initialized = GL_TRUE;
}
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c
b/src/mesa/drivers/dri/radeon/radeon_fbo.c
index 63bc7e8..29a6d79 100644
--- a/src/mesa/drivers/dri/radeon/radeon_fbo.c
+++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
@@ -635,8 +635,6 @@ radeon_resize_buffers(struct gl_context *ctx, struct
gl_framebuffer *fb,
_mesa_resize_framebuffer(ctx, fb, width, height);
- fb->Initialized = GL_TRUE; /* XXX remove someday */
-
if (fb->Name != 0) {
return;
}
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 0002da5..5d5b534 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2680,8 +2680,6 @@ struct gl_framebuffer
*/
struct gl_config Visual;
- GLboolean Initialized;
-
GLuint Width, Height; /**< size of frame buffer in pixels */
/** \name Drawing bounds (Intersection of buffer size and scissor box) */
diff --git a/src/mesa/state_tracker/st_manager.c
b/src/mesa/state_tracker/st_manager.c
index ec87608..9c2b4d2 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -431,8 +431,6 @@ st_framebuffer_create(struct st_framebuffer_iface *stfbi)
stfb->stamp = 0;
st_framebuffer_update_attachments(stfb);
- stfb->Base.Initialized = GL_TRUE;
-
return stfb;
}
--
1.8.3.rc0
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[Mesa-dev] [PATCH 03/11] intel: Remove gratuitous custom framebuffer resize code.
_mesa_resize_framebuffer(), the default value of the ResizeBuffers hook,
already checks for a window system framebuffer and walks the renderbuffers
calling AllocStorage().
---
src/mesa/drivers/dri/intel/intel_fbo.c | 36 ++
1 file changed, 6 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 32d1797..d16523b 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -314,9 +314,12 @@ intel_image_target_renderbuffer_storage(struct gl_context
*ctx,
}
/**
- * Called for each hardware renderbuffer when a _window_ is resized.
- * Just update fields.
- * Not used for user-created renderbuffers!
+ * Called by _mesa_resize_framebuffer() for each hardware renderbuffer when a
+ * window system framebuffer is resized.
+ *
+ * Any actual buffer reallocations for hardware renderbuffers (which would
+ * have triggered _mesa_resize_framebuffer()) were done by
+ * intel_process_dri2_buffer().
*/
static GLboolean
intel_alloc_window_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
@@ -330,32 +333,6 @@ intel_alloc_window_storage(struct gl_context * ctx, struct
gl_renderbuffer *rb,
return true;
}
-
-static void
-intel_resize_buffers(struct gl_context *ctx, struct gl_framebuffer *fb,
-GLuint width, GLuint height)
-{
- int i;
-
- _mesa_resize_framebuffer(ctx, fb, width, height);
-
- if (_mesa_is_user_fbo(fb)) {
- return;
- }
-
-
- /* Make sure all window system renderbuffers are up to date */
- for (i = BUFFER_FRONT_LEFT; i <= BUFFER_BACK_RIGHT; i++) {
- struct gl_renderbuffer *rb = fb->Attachment[i].Renderbuffer;
-
- /* only resize if size is changing */
- if (rb && (rb->Width != width || rb->Height != height)) {
-rb->AllocStorage(ctx, rb, rb->InternalFormat, width, height);
- }
- }
-}
-
-
/** Dummy function for gl_renderbuffer::AllocStorage() */
static GLboolean
intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
@@ -965,7 +942,6 @@ intel_fbo_init(struct intel_context *intel)
intel->ctx.Driver.FramebufferRenderbuffer = intel_framebuffer_renderbuffer;
intel->ctx.Driver.RenderTexture = intel_render_texture;
intel->ctx.Driver.FinishRenderTexture = intel_finish_render_texture;
- intel->ctx.Driver.ResizeBuffers = intel_resize_buffers;
intel->ctx.Driver.ValidateFramebuffer = intel_validate_framebuffer;
intel->ctx.Driver.BlitFramebuffer = intel_blit_framebuffer;
intel->ctx.Driver.EGLImageTargetRenderbufferStorage =
--
1.8.3.rc0
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[Mesa-dev] [PATCH 01/11] mesa: Remove Driver.GetBufferSize and its callers.
Only the GDI driver set it to non-NULL any more, and that driver has a
Viewport hook that should keep it limping along as well as it ever has.
---
src/mesa/drivers/common/driverfuncs.c| 1 -
src/mesa/drivers/dri/r200/r200_context.c | 1 -
src/mesa/drivers/dri/swrast/swrast.c | 1 -
src/mesa/drivers/osmesa/osmesa.c | 1 -
src/mesa/drivers/windows/gdi/wmesa.c | 1 -
src/mesa/drivers/x11/xm_dd.c | 1 -
src/mesa/main/context.c | 45 -
src/mesa/main/dd.h | 9 -
src/mesa/main/framebuffer.c | 69
9 files changed, 129 deletions(-)
diff --git a/src/mesa/drivers/common/driverfuncs.c
b/src/mesa/drivers/common/driverfuncs.c
index 016c0e8..5faa98a 100644
--- a/src/mesa/drivers/common/driverfuncs.c
+++ b/src/mesa/drivers/common/driverfuncs.c
@@ -75,7 +75,6 @@ _mesa_init_driver_functions(struct dd_function_table *driver)
driver->GetString = NULL; /* REQUIRED! */
driver->UpdateState = NULL; /* REQUIRED! */
- driver->GetBufferSize = NULL; /* REQUIRED! */
driver->ResizeBuffers = _mesa_resize_framebuffer;
driver->Finish = NULL;
diff --git a/src/mesa/drivers/dri/r200/r200_context.c
b/src/mesa/drivers/dri/r200/r200_context.c
index 391fa90..3484478 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -139,7 +139,6 @@ static const struct tnl_pipeline_stage *r200_pipeline[] = {
*/
static void r200InitDriverFuncs( struct dd_function_table *functions )
{
-functions->GetBufferSize = NULL; /* OBSOLETE */
functions->GetString = r200GetString;
}
diff --git a/src/mesa/drivers/dri/swrast/swrast.c
b/src/mesa/drivers/dri/swrast/swrast.c
index 91bcc59..ee80c1f 100644
--- a/src/mesa/drivers/dri/swrast/swrast.c
+++ b/src/mesa/drivers/dri/swrast/swrast.c
@@ -642,7 +642,6 @@ swrast_init_driver_functions(struct dd_function_table
*driver)
{
driver->GetString = get_string;
driver->UpdateState = update_state;
-driver->GetBufferSize = NULL;
driver->Viewport = viewport;
driver->ChooseTextureFormat = swrastChooseTextureFormat;
driver->MapRenderbuffer = swrast_map_renderbuffer;
diff --git a/src/mesa/drivers/osmesa/osmesa.c b/src/mesa/drivers/osmesa/osmesa.c
index 0d62712..241e74f 100644
--- a/src/mesa/drivers/osmesa/osmesa.c
+++ b/src/mesa/drivers/osmesa/osmesa.c
@@ -710,7 +710,6 @@ OSMesaCreateContextExt( GLenum format, GLint depthBits,
GLint stencilBits,
/* override with our functions */
functions.GetString = get_string;
functions.UpdateState = osmesa_update_state;
- functions.GetBufferSize = NULL;
if (!_mesa_initialize_context(&osmesa->mesa,
API_OPENGL_COMPAT,
diff --git a/src/mesa/drivers/windows/gdi/wmesa.c
b/src/mesa/drivers/windows/gdi/wmesa.c
index 35ec65a..ef791ab 100644
--- a/src/mesa/drivers/windows/gdi/wmesa.c
+++ b/src/mesa/drivers/windows/gdi/wmesa.c
@@ -605,7 +605,6 @@ WMesaContext WMesaCreateContext(HDC hDC,
_mesa_init_driver_functions(&functions);
functions.GetString = wmesa_get_string;
functions.UpdateState = wmesa_update_state;
-functions.GetBufferSize = wmesa_get_buffer_size;
functions.Flush = wmesa_flush;
functions.Clear = clear;
functions.ResizeBuffers = wmesa_resize_buffers;
diff --git a/src/mesa/drivers/x11/xm_dd.c b/src/mesa/drivers/x11/xm_dd.c
index d0adea5..676411a 100644
--- a/src/mesa/drivers/x11/xm_dd.c
+++ b/src/mesa/drivers/x11/xm_dd.c
@@ -841,7 +841,6 @@ xmesa_init_driver_functions( XMesaVisual xmvisual,
{
driver->GetString = get_string;
driver->UpdateState = xmesa_update_state;
- driver->GetBufferSize = NULL; /* OBSOLETE */
driver->Flush = finish_or_flush;
driver->Finish = finish_or_flush;
driver->ColorMask = color_mask;
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index c59f755..5ad04cc 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa/main/context.c
@@ -1388,25 +1388,6 @@ check_compatible(const struct gl_context *ctx,
/**
- * Do one-time initialization for the given framebuffer. Specifically,
- * ask the driver for the window's current size and update the framebuffer
- * object to match.
- * Really, the device driver should totally take care of this.
- */
-static void
-initialize_framebuffer_size(struct gl_context *ctx, struct gl_framebuffer *fb)
-{
- GLuint width, height;
- if (ctx->Driver.GetBufferSize) {
- ctx->Driver.GetBufferSize(fb, &width, &height);
- if (ctx->Driver.ResizeBuffers)
- ctx->Driver.ResizeBuffers(ctx, fb, width, height);
- fb->Initialized = GL_TRUE;
- }
-}
-
-
-/**
* Check if the viewport/scissor size has not yet been initialized.
* Initialize the size if the given width and height are non-zero.
*/
@@ -1508,32 +1489,6 @@ _mesa_make_current( struct gl_context *newCtx,
*/
newCtx->NewState |= _NEW_
[Mesa-dev] intel_draw_buffers overhead reduction (with mesa core changes)
With some of our new platforms, CPU overhead is becoming a major issue, so I started poking around the profile of cairo-gl again. I noticed some comedy in the FBO statechange path, where i965 was recomputing state multiple times up front instead of delaying it until draw time. Most it originally came from the merge of FBO support to i965, where I flagged extra state because we didn't have all the required state flags sorted out at the time. In the process, I noticed some silly duplicated code between drivers and Mesa core, and ripped that out. Should you want to test it, the code is at the i965-drawbuffers-reduction branch of my Mesa tree. The end result for cairo-gl is a 2.2964% +/- 0.459116% improvement in test runtime (n=31/30). I didn't analyze which particular patches gave the biggest wins, though patch 10/11 was big on the profile. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] build: remove script compatibility symlinks
On Thu, Jun 20, 2013 at 08:32:03PM -0700, Kenneth Graunke wrote: > On 06/20/2013 06:45 PM, Jonathan Gray wrote: > >On Thu, Jun 20, 2013 at 04:00:04PM -0600, Brian Paul wrote: > >>On 06/20/2013 03:32 PM, Dave Airlie wrote: > >>>On Fri, Jun 21, 2013 at 2:28 AM, Jonathan Gray wrote: > The symlinks for compatibility with old scripts assumes > sysv shared library versioning and breaks other systems. > > For example OpenBSD uses sunos 4 style .so.major.minor > versioning so the targets with ln will fail. > > Fixes bug 63269. > > >>> > >>>totally nak. > >> > >>Yeah, I don't want to loose this feature either. > >> > >> > >>>My fix you mean avoids? > >>> > >>>A lot of developers use this feature, I do wonder if maybe we can move > >>>it behind a configure switch though as I think it also causes some > >>>rpaths to be emitted that I think distro packages would like to avoid. > >> > >>We could certainly be smarter about whether to make the links or how > >>they're made. I'd rather pursue that. > > > >Perhaps it is enough to glob the ln calls so the .patch part > >is never explicitly referenced. The additional symlinks to > >the library won't always make sense on non linux systems but > >at least mesa would actually build again then. > > We could almost do: > > for lib in .libs/foo.so*; do ln -f $lib > $(top_builddir)/$(LIB_DIR)/`basename $lib`; done > > This would create hardlinks for every library that actually got > built. Unfortunately, I think it means that the symlinks will point > to the original .libs/foo.so.1.0.0 file, which means that you can't > just copy 'lib' around anymore. Hm. > > Alternatively, what about simply having 'make' run 'make > DESTDIR=$(top_builddir)/$(LIB_DIR) install' or the like? I guess > that would put libraries in mesa/lib// and DRI > drivers in mesa/lib///dri, which is a little > annoying. And does rpath nonsense... The following is enough to avoid the specific problem on OpenBSD. There doesn't appear to be any easy way to get the name of the shared library from automake/libtool. diff --git src/egl/main/Makefile.am src/egl/main/Makefile.am index ca5257a..ebe15f6 100644 --- src/egl/main/Makefile.am +++ src/egl/main/Makefile.am @@ -120,7 +120,7 @@ endif # a while by putting a link to the driver into /lib of the build tree. all-local: libEGL.la $(MKDIR_P) $(top_builddir)/$(LIB_DIR); - ln -f .libs/libEGL.so.1.0.0 $(top_builddir)/$(LIB_DIR)/libEGL.so.1 + ln -f .libs/libEGL.so.1.0* $(top_builddir)/$(LIB_DIR)/libEGL.so.1 ln -sf libEGL.so.1 $(top_builddir)/$(LIB_DIR)/libEGL.so pkgconfigdir = $(libdir)/pkgconfig diff --git src/gbm/Makefile.am src/gbm/Makefile.am index e22c55c..cc4ba61 100644 --- src/gbm/Makefile.am +++ src/gbm/Makefile.am @@ -43,4 +43,4 @@ endif all-local: libgbm.la $(MKDIR_P) $(top_builddir)/$(LIB_DIR); - ln -f .libs/libgbm.so.1.0.0 $(top_builddir)/$(LIB_DIR)/libgbm.so + ln -f .libs/libgbm.so.1.0* $(top_builddir)/$(LIB_DIR)/libgbm.so diff --git src/glx/Makefile.am src/glx/Makefile.am index f01709b..faecfd6 100644 --- src/glx/Makefile.am +++ src/glx/Makefile.am @@ -112,5 +112,5 @@ lib@GL_LIB@_la_LDFLAGS = $(GL_LDFLAGS) # a while by putting a link to the driver into /lib of the build tree. all-local: lib@GL_LIB@.la $(MKDIR_P) $(top_builddir)/$(LIB_DIR); - ln -f .libs/lib@GL_LIB@.so.1.2.0 $(top_builddir)/$(LIB_DIR)/lib@GL_LIB@.so.1 + ln -f .libs/lib@GL_LIB@.so.1.2* $(top_builddir)/$(LIB_DIR)/lib@GL_LIB@.so.1 ln -sf lib@GL_LIB@.so.1 $(top_builddir)/$(LIB_DIR)/lib@GL_LIB@.so diff --git src/mapi/es1api/Makefile.am src/mapi/es1api/Makefile.am index eb98f16..f7bcce2 100644 --- src/mapi/es1api/Makefile.am +++ src/mapi/es1api/Makefile.am @@ -61,6 +61,4 @@ CLEANFILES = $(BUILT_SOURCES) # a while by putting a link to the driver into /lib of the build tree. all-local: libGLESv1_CM.la $(MKDIR_P) $(top_builddir)/$(LIB_DIR); - ln -f .libs/libGLESv1_CM.so $(top_builddir)/$(LIB_DIR)/libGLESv1_CM.so - ln -f .libs/libGLESv1_CM.so.1 $(top_builddir)/$(LIB_DIR)/libGLESv1_CM.so.1 - ln -f .libs/libGLESv1_CM.so.1.1.0 $(top_builddir)/$(LIB_DIR)/libGLESv1_CM.so.1.1.0 + ln -f .libs/libGLESv1_CM.so* $(top_builddir)/$(LIB_DIR)/ diff --git src/mapi/es2api/Makefile.am src/mapi/es2api/Makefile.am index c6b0ca4..9e0419a 100644 --- src/mapi/es2api/Makefile.am +++ src/mapi/es2api/Makefile.am @@ -65,6 +65,4 @@ CLEANFILES = $(BUILT_SOURCES) # a while by putting a link to the driver into /lib of the build tree. all-local: libGLESv2.la $(MKDIR_P) $(top_builddir)/$(LIB_DIR); - ln -f .libs/libGLESv2.so $(top_builddir)/$(LIB_DIR)/libGLESv2.so - ln -f .libs/libGLESv2.so.2 $(top_builddir)/$(LIB_DIR)/libGLESv2.so.2 - ln -f .libs/libGLESv2.so.2.0.0 $(top_builddir)/$(LIB_DIR)/libGLESv2.so.2.0.0 + ln -f .libs/libGLESv2.so* $(top_builddir)/$(LIB_DIR)/ diff --git src/mapi/shared-glapi/Makefile.am src/mapi/shared-glapi/Makefi
Re: [Mesa-dev] [PATCH 2/2] mesa: Move the common _mesa_glsl_compile_shader() code to glsl/.
On 06/19/2013 04:19 PM, Eric Anholt wrote: This code had no relation to ir_to_mesa.cpp, since it was also used by intel and state_tracker, and most of it was duplicated with the standalone compiler (which has periodically drifted from the Mesa copy). v2: Split from the ir_to_mesa to shaderapi.c changes. Acked-by: Paul Berry (v1) Thank you. Having these separated makes it clear what code just moved between files and what code got coalesced together. Sorry for the trouble. Both patches are: Reviewed-by: Kenneth Graunke ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] build: remove script compatibility symlinks
On 06/20/2013 06:45 PM, Jonathan Gray wrote: On Thu, Jun 20, 2013 at 04:00:04PM -0600, Brian Paul wrote: On 06/20/2013 03:32 PM, Dave Airlie wrote: On Fri, Jun 21, 2013 at 2:28 AM, Jonathan Gray wrote: The symlinks for compatibility with old scripts assumes sysv shared library versioning and breaks other systems. For example OpenBSD uses sunos 4 style .so.major.minor versioning so the targets with ln will fail. Fixes bug 63269. totally nak. Yeah, I don't want to loose this feature either. My fix you mean avoids? A lot of developers use this feature, I do wonder if maybe we can move it behind a configure switch though as I think it also causes some rpaths to be emitted that I think distro packages would like to avoid. We could certainly be smarter about whether to make the links or how they're made. I'd rather pursue that. Perhaps it is enough to glob the ln calls so the .patch part is never explicitly referenced. The additional symlinks to the library won't always make sense on non linux systems but at least mesa would actually build again then. We could almost do: for lib in .libs/foo.so*; do ln -f $lib $(top_builddir)/$(LIB_DIR)/`basename $lib`; done This would create hardlinks for every library that actually got built. Unfortunately, I think it means that the symlinks will point to the original .libs/foo.so.1.0.0 file, which means that you can't just copy 'lib' around anymore. Hm. Alternatively, what about simply having 'make' run 'make DESTDIR=$(top_builddir)/$(LIB_DIR) install' or the like? I guess that would put libraries in mesa/lib// and DRI drivers in mesa/lib///dri, which is a little annoying. And does rpath nonsense... --Ken ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] build: remove script compatibility symlinks
On Thu, Jun 20, 2013 at 04:00:04PM -0600, Brian Paul wrote: > On 06/20/2013 03:32 PM, Dave Airlie wrote: > >On Fri, Jun 21, 2013 at 2:28 AM, Jonathan Gray wrote: > >>The symlinks for compatibility with old scripts assumes > >>sysv shared library versioning and breaks other systems. > >> > >>For example OpenBSD uses sunos 4 style .so.major.minor > >>versioning so the targets with ln will fail. > >> > >>Fixes bug 63269. > >> > > > >totally nak. > > Yeah, I don't want to loose this feature either. > > > >My fix you mean avoids? > > > >A lot of developers use this feature, I do wonder if maybe we can move > >it behind a configure switch though as I think it also causes some > >rpaths to be emitted that I think distro packages would like to avoid. > > We could certainly be smarter about whether to make the links or how > they're made. I'd rather pursue that. Perhaps it is enough to glob the ln calls so the .patch part is never explicitly referenced. The additional symlinks to the library won't always make sense on non linux systems but at least mesa would actually build again then. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] New Device Driver Help
Hello everyone, My name is Andy. I am a university student from Canada.I am currently working on a project which I am trying to port the mesa library to another device. (the Altera DE2)I am wondering if anyone can give me some suggestions to get started.Any information would be great! My email address is lilap...@gmail.com / lilapkiu@hotmail.comThank you for your time. Andy ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 12/12] R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI
By default, we expand these operations for both EG and SI. Move the
duplicated code into a common space for now. If the targets ever actually
implement these operations as instructions, we can override that in the relevant
target.
Signed-off-by: Aaron Watry
---
lib/Target/R600/AMDGPUISelLowering.cpp | 22 ++
lib/Target/R600/R600ISelLowering.cpp | 19 ---
lib/Target/R600/SIISelLowering.cpp | 30 --
3 files changed, 22 insertions(+), 49 deletions(-)
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp
b/lib/Target/R600/AMDGPUISelLowering.cpp
index 02d6fab..6d73590 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -70,6 +70,28 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine
&TM) :
setOperationAction(ISD::UDIV, MVT::i32, Expand);
setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
setOperationAction(ISD::UREM, MVT::i32, Expand);
+
+ int types[] = {
+(int)MVT::v2i32,
+(int)MVT::v4i32
+ };
+ size_t NumTypes = sizeof(types) / sizeof(*types);
+
+ for (unsigned int x = 0; x < NumTypes; ++x) {
+MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
+//Expand the following operations for the current type by default
+setOperationAction(ISD::ADD, VT, Expand);
+setOperationAction(ISD::AND, VT, Expand);
+setOperationAction(ISD::MUL, VT, Expand);
+setOperationAction(ISD::OR, VT, Expand);
+setOperationAction(ISD::SHL, VT, Expand);
+setOperationAction(ISD::SRL, VT, Expand);
+setOperationAction(ISD::SRA, VT, Expand);
+setOperationAction(ISD::SUB, VT, Expand);
+setOperationAction(ISD::UDIV, VT, Expand);
+setOperationAction(ISD::UREM, VT, Expand);
+setOperationAction(ISD::XOR, VT, Expand);
+ }
}
//===-===//
diff --git a/lib/Target/R600/R600ISelLowering.cpp
b/lib/Target/R600/R600ISelLowering.cpp
index cf349a8..18e83e8 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -38,30 +38,11 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
- setOperationAction(ISD::ADD, MVT::v4i32, Expand);
- setOperationAction(ISD::AND, MVT::v4i32, Expand);
setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
- setOperationAction(ISD::MUL, MVT::v2i32, Expand);
- setOperationAction(ISD::MUL, MVT::v4i32, Expand);
- setOperationAction(ISD::OR, MVT::v4i32, Expand);
- setOperationAction(ISD::OR, MVT::v2i32, Expand);
setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand);
- setOperationAction(ISD::SHL, MVT::v4i32, Expand);
- setOperationAction(ISD::SHL, MVT::v2i32, Expand);
- setOperationAction(ISD::SRL, MVT::v4i32, Expand);
- setOperationAction(ISD::SRL, MVT::v2i32, Expand);
- setOperationAction(ISD::SRA, MVT::v4i32, Expand);
- setOperationAction(ISD::SRA, MVT::v2i32, Expand);
- setOperationAction(ISD::SUB, MVT::v4i32, Expand);
- setOperationAction(ISD::SUB, MVT::v2i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
- setOperationAction(ISD::UDIV, MVT::v2i32, Expand);
- setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
- setOperationAction(ISD::UREM, MVT::v4i32, Expand);
setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
- setOperationAction(ISD::XOR, MVT::v4i32, Expand);
- setOperationAction(ISD::XOR, MVT::v2i32, Expand);
setOperationAction(ISD::BR_CC, MVT::i32, Expand);
setOperationAction(ISD::BR_CC, MVT::f32, Expand);
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index e70c7de..9d4cfef 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -65,36 +65,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::ADD, MVT::i64, Legal);
setOperationAction(ISD::ADD, MVT::i32, Legal);
- setOperationAction(ISD::ADD, MVT::v4i32, Expand);
- setOperationAction(ISD::ADD, MVT::v2i32, Expand);
-
- setOperationAction(ISD::AND, MVT::v2i32, Expand);
- setOperationAction(ISD::AND, MVT::v4i32, Expand);
-
- setOperationAction(ISD::MUL, MVT::v2i32, Expand);
- setOperationAction(ISD::MUL, MVT::v4i32, Expand);
-
- setOperationAction(ISD::OR, MVT::v2i32, Expand);
- setOperationAction(ISD::OR, MVT::v4i32, Expand);
-
- setOperationAction(ISD::SHL, MVT::v2i32, Expand);
- setOperationAction(ISD::SHL, MVT::v4i32, Expand);
- setOperationAction(ISD::SRL, MVT::v4i32, Expand);
- setOperationAction(ISD::SRL, MVT::v2i32, Expand);
- setOperationAction(ISD::SRA, MVT::v4i32, Expand);
- setOperationAction(ISD::SRA, MVT::v2i32, Expand);
-
- setOperationAction(ISD::SUB, MVT::v2i32, Expand);
- setOperationAction(ISD::SUB, MVT::v4i32, Expand);
-
- setOperationAction(ISD::UDIV, MVT::v2i32,
[Mesa-dev] [PATCH 11/12] R600: Add v2i32 test for vselect
Note: Only adding test for evergreen, not SI yet.
When I attempted to expand vselect for SI, I got the following:
llc:
/home/awatry/src/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:522:
llvm::SDValue llvm::DAGTypeLegalizer::PromoteIntRes_SETCC(llvm::SDNode*):
Assertion `SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
"Vector compare must return a vector result!"' failed.
Signed-off-by: Aaron Watry
---
test/CodeGen/R600/vselect.ll | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll
index edd7ba0..3f08cec 100644
--- a/test/CodeGen/R600/vselect.ll
+++ b/test/CodeGen/R600/vselect.ll
@@ -1,10 +1,24 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
-; CHECK: @test_select_v4i32
-; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
-; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
-; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
-; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: @test_select_v2i32
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+
+define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32>
addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
+entry:
+ %0 = load <2 x i32> addrspace(1)* %in0
+ %1 = load <2 x i32> addrspace(1)* %in1
+ %cmp = icmp ne <2 x i32> %0, %1
+ %result = select <2 x i1> %cmp, <2 x i32> %0, <2 x i32> %1
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @test_select_v4i32
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32>
addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
entry:
--
1.8.1.2
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[Mesa-dev] [PATCH 10/12] R600/SI: Expand xor v2i32/v4i32
Add test cases for both vector sizes on SI and also add v2i32 test for EG.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 3 +++
test/CodeGen/R600/xor.ll | 40 +++---
2 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index a784667..e70c7de 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -93,6 +93,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::UREM, MVT::v2i32, Expand);
setOperationAction(ISD::UREM, MVT::v4i32, Expand);
+ setOperationAction(ISD::XOR, MVT::v2i32, Expand);
+ setOperationAction(ISD::XOR, MVT::v4i32, Expand);
+
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
diff --git a/test/CodeGen/R600/xor.ll b/test/CodeGen/R600/xor.ll
index cf612e0..f52729d 100644
--- a/test/CodeGen/R600/xor.ll
+++ b/test/CodeGen/R600/xor.ll
@@ -1,12 +1,38 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
-; CHECK: @xor_v4i32
-; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @xor_v2i32
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
-define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32>
%b) {
+;SI-CHECK: @xor_v2i32
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+
+define void @xor_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)*
%in0, <2 x i32> addrspace(1)* %in1) {
+ %a = load <2 x i32> addrspace(1) * %in0
+ %b = load <2 x i32> addrspace(1) * %in1
+ %result = xor <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @xor_v4i32
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @xor_v4i32
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)*
%in0, <4 x i32> addrspace(1)* %in1) {
+ %a = load <4 x i32> addrspace(1) * %in0
+ %b = load <4 x i32> addrspace(1) * %in1
%result = xor <4 x i32> %a, %b
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
ret void
--
1.8.1.2
___
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[Mesa-dev] [PATCH 09/12] R600: Add v2i32 test for setcc on evergreen
No test/expansion for SI has been added yet. Attempts to expand this
operation for SI resulted in a stacktrace in (IIRC) LegalizeIntegerTypes
which was complaining about vector comparisons being required to return
a vector type.
Signed-off-by: Aaron Watry
---
test/CodeGen/R600/setcc.ll | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/test/CodeGen/R600/setcc.ll b/test/CodeGen/R600/setcc.ll
index 0752f2e..e3f77b1 100644
--- a/test/CodeGen/R600/setcc.ll
+++ b/test/CodeGen/R600/setcc.ll
@@ -1,7 +1,26 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: SETE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;EG-CHECK: @test2
+;EG-CHECK: SETE_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: SETE_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = icmp eq <2 x i32> %a, %b
+ %sext = sext <2 x i1> %result to <2 x i32>
+ store <2 x i32> %sext, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: SETE_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: SETE_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: SETE_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: SETE_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
%a = load <4 x i32> addrspace(1) * %in
%b = load <4 x i32> addrspace(1) * %b_ptr
--
1.8.1.2
___
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[Mesa-dev] [PATCH 07/12] R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG
Also add lit test for both cases on SI, and v2i32 for evergreen.
Note: I followed the guidance of the v4i32 EG check... UDIV produces really
complex code, so let's just check that the instruction was lowered
successfully.
Signed-off-by: Aaron Watry
---
lib/Target/R600/R600ISelLowering.cpp | 1 +
lib/Target/R600/SIISelLowering.cpp | 3 +++
test/CodeGen/R600/udiv.ll| 25 ++---
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/lib/Target/R600/R600ISelLowering.cpp
b/lib/Target/R600/R600ISelLowering.cpp
index 812df83..cf349a8 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -56,6 +56,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SUB, MVT::v4i32, Expand);
setOperationAction(ISD::SUB, MVT::v2i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::v2i32, Expand);
setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
setOperationAction(ISD::UREM, MVT::v4i32, Expand);
setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index 5f44d3a..1fb28fa 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -87,6 +87,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SUB, MVT::v2i32, Expand);
setOperationAction(ISD::SUB, MVT::v4i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::v2i32, Expand);
+ setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
+
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
diff --git a/test/CodeGen/R600/udiv.ll b/test/CodeGen/R600/udiv.ll
index b81e366..08fe2ef 100644
--- a/test/CodeGen/R600/udiv.ll
+++ b/test/CodeGen/R600/udiv.ll
@@ -1,11 +1,30 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
;The code generated by udiv is long and complex and may frequently change.
;The goal of this test is to make sure the ISel doesn't fail when it gets
;a v4i32 udiv
-;CHECK: CF_END
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;EG-CHECK: @test2
+;EG-CHECK: CF_END
+;SI-CHECK: @test2
+;SI-CHECK: S_ENDPGM
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = udiv <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: CF_END
+;SI-CHECK: @test4
+;SI-CHECK: S_ENDPGM
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
%a = load <4 x i32> addrspace(1) * %in
%b = load <4 x i32> addrspace(1) * %b_ptr
--
1.8.1.2
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[Mesa-dev] [PATCH 08/12] R600/SI: Expand urem of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Note: I followed the guidance of the v4i32 EG check... UREM produces really
complex code, so let's just check that the instruction was lowered
successfully.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 3 +++
test/CodeGen/R600/urem.ll | 27 +++
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index 1fb28fa..a784667 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -90,6 +90,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::UDIV, MVT::v2i32, Expand);
setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
+ setOperationAction(ISD::UREM, MVT::v2i32, Expand);
+ setOperationAction(ISD::UREM, MVT::v4i32, Expand);
+
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
diff --git a/test/CodeGen/R600/urem.ll b/test/CodeGen/R600/urem.ll
index a2cc0bd..cf3474c 100644
--- a/test/CodeGen/R600/urem.ll
+++ b/test/CodeGen/R600/urem.ll
@@ -1,11 +1,30 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
;The code generated by urem is long and complex and may frequently change.
;The goal of this test is to make sure the ISel doesn't fail when it gets
-;a v4i32 urem
-;CHECK: CF_END
+;a v2i32/v4i32 urem
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;EG-CHECK: @test2
+;EG-CHECK: CF_END
+;SI-CHECK: @test2
+;SI-CHECK: S_ENDPGM
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = urem <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: CF_END
+;SI-CHECK: @test4
+;SI-CHECK: S_ENDPGM
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
%a = load <4 x i32> addrspace(1) * %in
%b = load <4 x i32> addrspace(1) * %b_ptr
--
1.8.1.2
___
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[Mesa-dev] [PATCH 06/12] R600/SI: Expand ashr of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 2 ++
test/CodeGen/R600/sra.ll | 41 +++---
2 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index 4219825..5f44d3a 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -81,6 +81,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SHL, MVT::v4i32, Expand);
setOperationAction(ISD::SRL, MVT::v4i32, Expand);
setOperationAction(ISD::SRL, MVT::v2i32, Expand);
+ setOperationAction(ISD::SRA, MVT::v4i32, Expand);
+ setOperationAction(ISD::SRA, MVT::v2i32, Expand);
setOperationAction(ISD::SUB, MVT::v2i32, Expand);
setOperationAction(ISD::SUB, MVT::v4i32, Expand);
diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll
index 972542d..7c5cc75 100644
--- a/test/CodeGen/R600/sra.ll
+++ b/test/CodeGen/R600/sra.ll
@@ -1,12 +1,39 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
-; CHECK: @ashr_v4i32
-; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @ashr_v2i32
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32>
%b) {
+;SI-CHECK: @ashr_v2i32
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)*
%in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = ashr <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @ashr_v4i32
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @ashr_v4i32
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)*
%in) {
+ %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+ %a = load <4 x i32> addrspace(1) * %in
+ %b = load <4 x i32> addrspace(1) * %b_ptr
%result = ashr <4 x i32> %a, %b
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
ret void
--
1.8.1.2
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[Mesa-dev] [PATCH 05/12] R600/SI: Expand srl of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 2 ++
test/CodeGen/R600/srl.ll | 42 +++---
2 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index 515c7a4..4219825 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -79,6 +79,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SHL, MVT::v2i32, Expand);
setOperationAction(ISD::SHL, MVT::v4i32, Expand);
+ setOperationAction(ISD::SRL, MVT::v4i32, Expand);
+ setOperationAction(ISD::SRL, MVT::v2i32, Expand);
setOperationAction(ISD::SUB, MVT::v2i32, Expand);
setOperationAction(ISD::SUB, MVT::v4i32, Expand);
diff --git a/test/CodeGen/R600/srl.ll b/test/CodeGen/R600/srl.ll
index 5f63600..d1dcd7f 100644
--- a/test/CodeGen/R600/srl.ll
+++ b/test/CodeGen/R600/srl.ll
@@ -1,12 +1,40 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
-; CHECK: @lshr_v4i32
-; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @lshr_v2i32
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32>
%b) {
+;SI-CHECK: @lshr_v2i32
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)*
%in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = lshr <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+
+;EG-CHECK: @lshr_v4i32
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @lshr_v4i32
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)*
%in) {
+ %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+ %a = load <4 x i32> addrspace(1) * %in
+ %b = load <4 x i32> addrspace(1) * %b_ptr
%result = lshr <4 x i32> %a, %b
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
ret void
--
1.8.1.2
___
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[Mesa-dev] [PATCH 04/12] R600/SI: Expand shl of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 3 +++
test/CodeGen/R600/shl.ll | 47 ++
2 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index 30a7de5..515c7a4 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -77,6 +77,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::OR, MVT::v2i32, Expand);
setOperationAction(ISD::OR, MVT::v4i32, Expand);
+ setOperationAction(ISD::SHL, MVT::v2i32, Expand);
+ setOperationAction(ISD::SHL, MVT::v4i32, Expand);
+
setOperationAction(ISD::SUB, MVT::v2i32, Expand);
setOperationAction(ISD::SUB, MVT::v4i32, Expand);
diff --git a/test/CodeGen/R600/shl.ll b/test/CodeGen/R600/shl.ll
index db970e9..d68730a 100644
--- a/test/CodeGen/R600/shl.ll
+++ b/test/CodeGen/R600/shl.ll
@@ -1,16 +1,43 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
-; CHECK: @shl_v4i32
-; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; XXX: Add SI test for i64 shl once i64 stores and i64 function arguments are
+; supported.
+
+;EG-CHECK: @shl_v2i32
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @shl_v2i32
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)*
%in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = shl <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @shl_v4i32
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @shl_v4i32
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
-define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32>
%b) {
+define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)*
%in) {
+ %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+ %a = load <4 x i32> addrspace(1) * %in
+ %b = load <4 x i32> addrspace(1) * %b_ptr
%result = shl <4 x i32> %a, %b
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
ret void
}
-
-; XXX: Add SI test for i64 shl once i64 stores and i64 function arguments are
-; supported.
--
1.8.1.2
___
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[Mesa-dev] [PATCH 03/12] R600/SI: Expand or of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 3 +++
test/CodeGen/R600/or.ll| 41 +++---
2 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index cb80e5e..30a7de5 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -74,6 +74,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::MUL, MVT::v2i32, Expand);
setOperationAction(ISD::MUL, MVT::v4i32, Expand);
+ setOperationAction(ISD::OR, MVT::v2i32, Expand);
+ setOperationAction(ISD::OR, MVT::v4i32, Expand);
+
setOperationAction(ISD::SUB, MVT::v2i32, Expand);
setOperationAction(ISD::SUB, MVT::v4i32, Expand);
diff --git a/test/CodeGen/R600/or.ll b/test/CodeGen/R600/or.ll
index b0dbb02..4a4e892 100644
--- a/test/CodeGen/R600/or.ll
+++ b/test/CodeGen/R600/or.ll
@@ -1,12 +1,39 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
-; CHECK: @or_v4i32
-; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; EG-CHECK: @or_v2i32
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
-define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32>
%b) {
+;SI-CHECK: @or_v2i32
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)*
%in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = or <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+; EG-CHECK: @or_v4i32
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @or_v4i32
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)*
%in) {
+ %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+ %a = load <4 x i32> addrspace(1) * %in
+ %b = load <4 x i32> addrspace(1) * %b_ptr
%result = or <4 x i32> %a, %b
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
ret void
--
1.8.1.2
___
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[Mesa-dev] [PATCH 02/12] R600/SI: Expand mul of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 3 +++
test/CodeGen/R600/mul.ll | 38 --
2 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index bf2e7d3..cb80e5e 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -71,6 +71,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::AND, MVT::v2i32, Expand);
setOperationAction(ISD::AND, MVT::v4i32, Expand);
+ setOperationAction(ISD::MUL, MVT::v2i32, Expand);
+ setOperationAction(ISD::MUL, MVT::v4i32, Expand);
+
setOperationAction(ISD::SUB, MVT::v2i32, Expand);
setOperationAction(ISD::SUB, MVT::v4i32, Expand);
diff --git a/test/CodeGen/R600/mul.ll b/test/CodeGen/R600/mul.ll
index 7278e90..18a17b6 100644
--- a/test/CodeGen/R600/mul.ll
+++ b/test/CodeGen/R600/mul.ll
@@ -1,12 +1,38 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK
%s
+; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
; mul24 and mad24 are affected
-;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;EG-CHECK: @test2
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test2
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = mul <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test4
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
%a = load <4 x i32> addrspace(1) * %in
%b = load <4 x i32> addrspace(1) * %b_ptr
--
1.8.1.2
___
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[Mesa-dev] [PATCH 01/12] R600/SI: Expand and of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Signed-off-by: Aaron Watry
---
lib/Target/R600/SIISelLowering.cpp | 3 +++
test/CodeGen/R600/and.ll | 37 +++--
2 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index 776eb86..bf2e7d3 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -68,6 +68,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
setOperationAction(ISD::ADD, MVT::v4i32, Expand);
setOperationAction(ISD::ADD, MVT::v2i32, Expand);
+ setOperationAction(ISD::AND, MVT::v2i32, Expand);
+ setOperationAction(ISD::AND, MVT::v4i32, Expand);
+
setOperationAction(ISD::SUB, MVT::v2i32, Expand);
setOperationAction(ISD::SUB, MVT::v4i32, Expand);
diff --git a/test/CodeGen/R600/and.ll b/test/CodeGen/R600/and.ll
index 166af2d..44c21bd 100644
--- a/test/CodeGen/R600/and.ll
+++ b/test/CodeGen/R600/and.ll
@@ -1,11 +1,36 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
-;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @test2
+;EG-CHECK: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
+;EG-CHECK: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW],
T[0-9]+\.[XYZW]}}
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;SI-CHECK: @test2
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+ %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+ %a = load <2 x i32> addrspace(1) * %in
+ %b = load <2 x i32> addrspace(1) * %b_ptr
+ %result = and <2 x i32> %a, %b
+ store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+ ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test4
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
%a = load <4 x i32> addrspace(1) * %in
%b = load <4 x i32> addrspace(1) * %b_ptr
--
1.8.1.2
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[Mesa-dev] R600: Expand integer operations for SI and consolidate code with EG
This series is intended to bring SI closer to evergreen when it comes to support for v2i32/v4i32 integer operations. It adds support for expanding the following v2i32/v4i32 operations on SI: AND, MUL, OR, SHL, SRL, ASHR, UDIV, UREM, XOR Once that's done, the setOperationAction(op,type,Expand) calls that appear in both R600ISelLowering.cpp and SIISelLowering.cpp are all moved to AMDGPUISelLowering.cpp. If we decide to implement these ops through native instructions for either target in the future, we can override that in the individual targets. Signed-off-by: Aaron Watry R600/SI: Expand and of v2i32/v4i32 for SI R600/SI: Expand mul of v2i32/v4i32 for SI R600/SI: Expand or of v2i32/v4i32 for SI R600/SI: Expand shl of v2i32/v4i32 for SI R600/SI: Expand srl of v2i32/v4i32 for SI R600/SI: Expand ashr of v2i32/v4i32 for SI R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG R600/SI: Expand urem of v2i32/v4i32 for SI R600: Add v2i32 test for setcc on evergreen R600/SI: Expand xor v2i32/v4i32 R600: Add v2i32 test for vselect R600: Consolidate expansion of v2i32/v4i32 ops for SI/EG lib/Target/R600/AMDGPUISelLowering.cpp | 22 lib/Target/R600/R600ISelLowering.cpp | 18 - lib/Target/R600/SIISelLowering.cpp | 5 test/CodeGen/R600/and.ll | 37 +- test/CodeGen/R600/mul.ll | 38 ++- test/CodeGen/R600/or.ll| 41 - test/CodeGen/R600/setcc.ll | 25 +++--- test/CodeGen/R600/shl.ll | 47 ++ test/CodeGen/R600/sra.ll | 41 - test/CodeGen/R600/srl.ll | 42 +- test/CodeGen/R600/udiv.ll | 25 +++--- test/CodeGen/R600/urem.ll | 27 --- test/CodeGen/R600/vselect.ll | 26 ++- test/CodeGen/R600/xor.ll | 40 - 14 files changed, 345 insertions(+), 89 deletions(-) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] build: remove script compatibility symlinks
On 06/20/2013 03:32 PM, Dave Airlie wrote: On Fri, Jun 21, 2013 at 2:28 AM, Jonathan Gray wrote: The symlinks for compatibility with old scripts assumes sysv shared library versioning and breaks other systems. For example OpenBSD uses sunos 4 style .so.major.minor versioning so the targets with ln will fail. Fixes bug 63269. totally nak. Yeah, I don't want to loose this feature either. My fix you mean avoids? A lot of developers use this feature, I do wonder if maybe we can move it behind a configure switch though as I think it also causes some rpaths to be emitted that I think distro packages would like to avoid. We could certainly be smarter about whether to make the links or how they're made. I'd rather pursue that. -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/3] R600: Expand v2i32 load/store instead of custom lowering
Thanks Tom.
Also as discussed on IRC, I checked the v2i32 expand change against
piglits cl/program/execute/*stack*.cl test cases, as well as the v2i32
test that just sent to the piglit list. The tests were run on a Radeon
5400, and all of them passed with the Expand'ed v2i32 loads/stores.
--Aaron
On Thu, Jun 20, 2013 at 4:30 PM, Tom Stellard wrote:
> On Wed, Jun 19, 2013 at 08:51:01AM -0700, Tom Stellard wrote:
>> On Mon, Jun 17, 2013 at 04:11:38PM -0500, Aaron Watry wrote:
>> > The custom lowering causes llc to crash with a segfault.
>> >
>> > Ideally, the custom lowering can be fixed, but this allows
>> > programs which load/store v2i32 to work without crashing.
>> >
>> > Signed-off-by: Aaron Watry
>> > ---
>> > lib/Target/R600/R600ISelLowering.cpp | 4 ++--
>> > test/CodeGen/R600/load.vec.ll| 6 ++
>> > 2 files changed, 8 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/lib/Target/R600/R600ISelLowering.cpp
>> > b/lib/Target/R600/R600ISelLowering.cpp
>> > index 9cedadb..812df83 100644
>> > --- a/lib/Target/R600/R600ISelLowering.cpp
>> > +++ b/lib/Target/R600/R600ISelLowering.cpp
>> > @@ -86,7 +86,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine
>> > &TM) :
>> >
>> >// Legalize loads and stores to the private address space.
>> >setOperationAction(ISD::LOAD, MVT::i32, Custom);
>> > - setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
>> > + setOperationAction(ISD::LOAD, MVT::v2i32, Expand);
>> >setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
>> >setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
>> >setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
>> > @@ -94,7 +94,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine
>> > &TM) :
>> >setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom);
>> >setOperationAction(ISD::STORE, MVT::i8, Custom);
>> >setOperationAction(ISD::STORE, MVT::i32, Custom);
>> > - setOperationAction(ISD::STORE, MVT::v2i32, Custom);
>> > + setOperationAction(ISD::STORE, MVT::v2i32, Expand);
>>
>> We have to use custom lowering in order for things like constant loads
>> and global stores to work, so I think we need to fix whatever crash is
>> happening with custom lowering.
>>
>
> As you pointed out on IRC, since v2[if]32 loads are expanded to [if]32
> loads and we custom lower those, this patch should work fine. I will
> push this series.
>
> Thanks,
> Tom
>> >setOperationAction(ISD::STORE, MVT::v4i32, Custom);
>> >
>> >setOperationAction(ISD::LOAD, MVT::i32, Custom);
>> > diff --git a/test/CodeGen/R600/load.vec.ll b/test/CodeGen/R600/load.vec.ll
>> > index 08e034e..da1149a 100644
>> > --- a/test/CodeGen/R600/load.vec.ll
>> > +++ b/test/CodeGen/R600/load.vec.ll
>> > @@ -1,6 +1,10 @@
>> > +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck
>> > --check-prefix=EG-CHECK %s
>> > ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK
>> > %s
>> >
>> > ; load a v2i32 value from the global address space.
>> > +; EG-CHECK: @load_v2i32
>> > +; EG-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4
>> > +; EG-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
>> > ; SI-CHECK: @load_v2i32
>> > ; SI-CHECK: BUFFER_LOAD_DWORDX2 VGPR{{[0-9]+}}
>> > define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32>
>> > addrspace(1)* %in) {
>> > @@ -10,6 +14,8 @@ define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2
>> > x i32> addrspace(1)* %i
>> > }
>> >
>> > ; load a v4i32 value from the global address space.
>> > +; EG-CHECK: @load_v4i32
>> > +; EG-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0
>> > ; SI-CHECK: @load_v4i32
>> > ; SI-CHECK: BUFFER_LOAD_DWORDX4 VGPR{{[0-9]+}}
>> > define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32>
>> > addrspace(1)* %in) {
>> > --
>> > 1.8.1.2
>> >
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v2i32-stack.cl
Description: Binary data
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Re: [Mesa-dev] Mesa driver for VirtualBox
On Fri, Jun 21, 2013 at 12:47 AM, Michael Thayer wrote: > Hello, > > I am looking at the possibility of writing a driver for VirtualBox (ahem, > yes) which could partly live inside of the Mesa tree. My initial idea was > to have the driver in two parts, a driver/client part in the Mesa tree and a > server part in the VirtualBox tree which would communicate using an > agreed-on protocol through a local socket. The reasons for wanting to split > the driver this way are on the one hand that we still don't feel quite ready > to commit our host-guest 3D interface to eternity, and on the other that the > driver part on the Mesa side might well be useful in other contexts - > controlled 3D access (insofar as such a thing is possible) out of a sand box > comes to mind. > > I was considering a textual protocol between client and server which would > more or less model the Gallium3D API, with (texture and other) buffers > passed using shared memory via file descriptors. Gallium3D would have the > advantage that it is a much smaller target surface (if I may use that word) > than OpenGL. It has the disadvantage that it is closer to D3D than to > OpenGL, which may be better for modelling hardware, but perhaps less so for > proxying OpenGL APIs on a guest to OpenGL APIs on a host. In particular the > fact that we can't directly access the GLSL shader source which applications > on a guest system are presumably trying to send us, and which we need to > pass through to the host, disturbs me somewhat. Of course, I realise that > on the other hand this potentially gives us access to shaders in different > formats, but our main target will still be OpenGL on OpenGL for the > immediately forseeable future. I understand that Gallium3D receives shaders > in a format close to compiled D3D shaders, which suggests that WineD3D might > be of use. An alternative is to go straight for a DRI driver rather than a > Gallium3D one. I would be interested in any thoughts and suggestions! > > For background, I have some knowledge of 3D programming but am certainly no > expert. I can browse the Mesa source code and the drivers in it without > getting too worried, but need to use a search engine as I do so to feel > confident that I understand what is happening in the code. > I can't really speak to how good an idea or not this is, however I have written some code to do something similiar, pushing all the internal gallium API over a pipe to a GL renderer on the other side of the pipe. It isn't complete, it was only a stepping stone on my research to qemu 3D work. The biggest issue I see with doing something like that is how to make final display of things to the X server and making things like texture from pixmap work efficiently. The stuff I've done is on the renderer-1 branch of my mesa repo http://cgit.freedesktop.org/~airlied/mesa/log/?h=renderer-1 but its moved on a lot from that point, and I doubt the pipe code I wrote even builds anymore, since I've mostly moved to testing it as part of qemu now. But it currently just passes TGSI shaders through and converts them into GLSL using an assembler that will look something like the one in wine I suspect. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] build: remove script compatibility symlinks
On Fri, Jun 21, 2013 at 2:28 AM, Jonathan Gray wrote: > The symlinks for compatibility with old scripts assumes > sysv shared library versioning and breaks other systems. > > For example OpenBSD uses sunos 4 style .so.major.minor > versioning so the targets with ln will fail. > > Fixes bug 63269. > totally nak. My fix you mean avoids? A lot of developers use this feature, I do wonder if maybe we can move it behind a configure switch though as I think it also causes some rpaths to be emitted that I think distro packages would like to avoid. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/3] R600: Expand v2i32 load/store instead of custom lowering
On Wed, Jun 19, 2013 at 08:51:01AM -0700, Tom Stellard wrote:
> On Mon, Jun 17, 2013 at 04:11:38PM -0500, Aaron Watry wrote:
> > The custom lowering causes llc to crash with a segfault.
> >
> > Ideally, the custom lowering can be fixed, but this allows
> > programs which load/store v2i32 to work without crashing.
> >
> > Signed-off-by: Aaron Watry
> > ---
> > lib/Target/R600/R600ISelLowering.cpp | 4 ++--
> > test/CodeGen/R600/load.vec.ll| 6 ++
> > 2 files changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/lib/Target/R600/R600ISelLowering.cpp
> > b/lib/Target/R600/R600ISelLowering.cpp
> > index 9cedadb..812df83 100644
> > --- a/lib/Target/R600/R600ISelLowering.cpp
> > +++ b/lib/Target/R600/R600ISelLowering.cpp
> > @@ -86,7 +86,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM)
> > :
> >
> >// Legalize loads and stores to the private address space.
> >setOperationAction(ISD::LOAD, MVT::i32, Custom);
> > - setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
> > + setOperationAction(ISD::LOAD, MVT::v2i32, Expand);
> >setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
> >setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
> >setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
> > @@ -94,7 +94,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM)
> > :
> >setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Custom);
> >setOperationAction(ISD::STORE, MVT::i8, Custom);
> >setOperationAction(ISD::STORE, MVT::i32, Custom);
> > - setOperationAction(ISD::STORE, MVT::v2i32, Custom);
> > + setOperationAction(ISD::STORE, MVT::v2i32, Expand);
>
> We have to use custom lowering in order for things like constant loads
> and global stores to work, so I think we need to fix whatever crash is
> happening with custom lowering.
>
As you pointed out on IRC, since v2[if]32 loads are expanded to [if]32
loads and we custom lower those, this patch should work fine. I will
push this series.
Thanks,
Tom
> >setOperationAction(ISD::STORE, MVT::v4i32, Custom);
> >
> >setOperationAction(ISD::LOAD, MVT::i32, Custom);
> > diff --git a/test/CodeGen/R600/load.vec.ll b/test/CodeGen/R600/load.vec.ll
> > index 08e034e..da1149a 100644
> > --- a/test/CodeGen/R600/load.vec.ll
> > +++ b/test/CodeGen/R600/load.vec.ll
> > @@ -1,6 +1,10 @@
> > +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck
> > --check-prefix=EG-CHECK %s
> > ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK
> > %s
> >
> > ; load a v2i32 value from the global address space.
> > +; EG-CHECK: @load_v2i32
> > +; EG-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4
> > +; EG-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
> > ; SI-CHECK: @load_v2i32
> > ; SI-CHECK: BUFFER_LOAD_DWORDX2 VGPR{{[0-9]+}}
> > define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32>
> > addrspace(1)* %in) {
> > @@ -10,6 +14,8 @@ define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2
> > x i32> addrspace(1)* %i
> > }
> >
> > ; load a v4i32 value from the global address space.
> > +; EG-CHECK: @load_v4i32
> > +; EG-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0
> > ; SI-CHECK: @load_v4i32
> > ; SI-CHECK: BUFFER_LOAD_DWORDX4 VGPR{{[0-9]+}}
> > define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32>
> > addrspace(1)* %in) {
> > --
> > 1.8.1.2
> >
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[Mesa-dev] [PATCH] llvmpipe: fix wrong results for queries not in a scene
From: Roland Scheidegger
The result isn't always 0 in this case (depends on query type),
so instead of special casing this just use the ordinary path (should result
in correct values thanks to initialization in query_begin/end), just
skipping the fence wait.
---
src/gallium/drivers/llvmpipe/lp_query.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/llvmpipe/lp_query.c
b/src/gallium/drivers/llvmpipe/lp_query.c
index 386639e..1d3edff 100644
--- a/src/gallium/drivers/llvmpipe/lp_query.c
+++ b/src/gallium/drivers/llvmpipe/lp_query.c
@@ -100,20 +100,17 @@ llvmpipe_get_query_result(struct pipe_context *pipe,
uint64_t *result = (uint64_t *)vresult;
int i;
- if (!pq->fence) {
- /* no fence because there was no scene, so results is zero */
- *result = 0;
- return TRUE;
- }
-
- if (!lp_fence_signalled(pq->fence)) {
- if (!lp_fence_issued(pq->fence))
- llvmpipe_flush(pipe, NULL, __FUNCTION__);
+ if (pq->fence) {
+ /* only have a fence if there was a scene */
+ if (!lp_fence_signalled(pq->fence)) {
+ if (!lp_fence_issued(pq->fence))
+llvmpipe_flush(pipe, NULL, __FUNCTION__);
- if (!wait)
- return FALSE;
+ if (!wait)
+return FALSE;
- lp_fence_wait(pq->fence);
+ lp_fence_wait(pq->fence);
+ }
}
/* Sum the results from each of the threads:
--
1.7.9.5
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[Mesa-dev] [Bug 56710] src/mapi/glapi/glapitemp.h:1640:1: warning: no previous prototype for ‘glReadBufferNV’ [-Wmissing-prototypes]
https://bugs.freedesktop.org/show_bug.cgi?id=56710 Andreas Boll changed: What|Removed |Added QA Contact||mesa-dev@lists.freedesktop. ||org --- Comment #13 from Andreas Boll --- Could you still reproduce this bug? It should be fixed/worked around with this commit: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ea43e65498505fc5d11d63668cda165146eb55b -- You are receiving this mail because: You are the QA Contact for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] i965: Remove broken source type assertions from brw_alu3().
On Thu, Jun 13, 2013 at 2:55 PM, Kenneth Graunke wrote:
> Commit 526ffdfc033ab01cf133cb7e8290c65d12ccc9be attempted to generalize
> the source register type assertions to allow D and UD. However, the
> src1 and src2 assertions actually checked src0.type against D and UD due
> to a copy and paste bug.
>
> It also began setting the source and destination register types based on
> dest.type, ignoring src0/src1/src2.type completely. BFE and BFI2 may
> actually pass mixed D/UD types and expect them to be ignored, which is
> arguably a bit sloppy, but not too crazy either.
>
> This patch simply removes the source register assertions as those values
> aren't used anyway. It also clarifies the comment above the block that
> sets the register types.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 19 +--
> 1 file changed, 5 insertions(+), 14 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index 3d0db1b..f2cacd1 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -811,9 +811,6 @@ static struct brw_instruction *brw_alu3(struct
> brw_compile *p,
> assert(src0.file == BRW_GENERAL_REGISTER_FILE);
> assert(src0.address_mode == BRW_ADDRESS_DIRECT);
> assert(src0.nr < 128);
> - assert(src0.type == BRW_REGISTER_TYPE_F ||
> - src0.type == BRW_REGISTER_TYPE_D ||
> - src0.type == BRW_REGISTER_TYPE_UD);
> insn->bits2.da3src.src0_swizzle = src0.dw1.bits.swizzle;
> insn->bits2.da3src.src0_subreg_nr = get_3src_subreg_nr(src0);
> insn->bits2.da3src.src0_reg_nr = src0.nr;
> @@ -824,9 +821,6 @@ static struct brw_instruction *brw_alu3(struct
> brw_compile *p,
> assert(src1.file == BRW_GENERAL_REGISTER_FILE);
> assert(src1.address_mode == BRW_ADDRESS_DIRECT);
> assert(src1.nr < 128);
> - assert(src1.type == BRW_REGISTER_TYPE_F ||
> - src0.type == BRW_REGISTER_TYPE_D ||
> - src0.type == BRW_REGISTER_TYPE_UD);
> insn->bits2.da3src.src1_swizzle = src1.dw1.bits.swizzle;
> insn->bits2.da3src.src1_subreg_nr_low = get_3src_subreg_nr(src1) & 0x3;
> insn->bits3.da3src.src1_subreg_nr_high = get_3src_subreg_nr(src1) >> 2;
> @@ -838,9 +832,6 @@ static struct brw_instruction *brw_alu3(struct
> brw_compile *p,
> assert(src2.file == BRW_GENERAL_REGISTER_FILE);
> assert(src2.address_mode == BRW_ADDRESS_DIRECT);
> assert(src2.nr < 128);
> - assert(src2.type == BRW_REGISTER_TYPE_F ||
> - src0.type == BRW_REGISTER_TYPE_D ||
> - src0.type == BRW_REGISTER_TYPE_UD);
> insn->bits3.da3src.src2_swizzle = src2.dw1.bits.swizzle;
> insn->bits3.da3src.src2_subreg_nr = get_3src_subreg_nr(src2);
> insn->bits3.da3src.src2_rep_ctrl = src2.vstride == BRW_VERTICAL_STRIDE_0;
> @@ -849,12 +840,12 @@ static struct brw_instruction *brw_alu3(struct
> brw_compile *p,
> insn->bits1.da3src.src2_negate = src2.negate;
>
> if (intel->gen >= 7) {
> - /* For MAD and LRP, all incoming src types are float, but for BFE and
> - * BFI2, the three source types might not all be the same. src2, the
> - * primary argument, should match the type of the destination.
> + /* Set both the source and destination types based on dest.type,
> + * ignoring the source register types. The MAD and LRP emitters ensure
> + * that all four types are float. The BFE and BFI2 emitters, however,
> + * may send us mixed D and UD types and want us to ignore that and use
> + * the destination type.
> */
> - assert(dest.type == src2.type);
> -
>switch (dest.type) {
>case BRW_REGISTER_TYPE_F:
> insn->bits1.da3src.src_type = BRW_3SRC_TYPE_F;
> --
> 1.8.3
>
> ___
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Changes look good to me.
Both patches are: Reviewed-by: Anuj Phogat
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[Mesa-dev] [PATCH] build: remove script compatibility symlinks
The symlinks for compatibility with old scripts assumes sysv shared library versioning and breaks other systems. For example OpenBSD uses sunos 4 style .so.major.minor versioning so the targets with ln will fail. Fixes bug 63269. Signed-off-by: Jonathan Gray --- src/egl/main/Makefile.am | 7 --- src/gallium/targets/dri-freedreno/Makefile.am | 6 -- src/gallium/targets/dri-i915/Makefile.am | 6 -- src/gallium/targets/dri-ilo/Makefile.am| 7 --- src/gallium/targets/dri-nouveau/Makefile.am| 6 -- src/gallium/targets/dri-r300/Makefile.am | 6 -- src/gallium/targets/dri-r600/Makefile.am | 6 -- src/gallium/targets/dri-radeonsi/Makefile.am | 6 -- src/gallium/targets/dri-swrast/Makefile.am | 6 -- src/gallium/targets/dri-vmwgfx/Makefile.am | 6 -- src/gallium/targets/egl-static/Makefile.am | 20 src/gallium/targets/libgl-xlib/Makefile.am | 6 -- src/gallium/targets/opencl/Makefile.am | 6 -- src/gallium/targets/osmesa/Makefile.am | 11 --- src/gallium/targets/vdpau-nouveau/Makefile.am | 6 -- src/gallium/targets/vdpau-r300/Makefile.am | 6 -- src/gallium/targets/vdpau-r600/Makefile.am | 6 -- src/gallium/targets/vdpau-radeonsi/Makefile.am | 6 -- src/gallium/targets/vdpau-softpipe/Makefile.am | 6 -- src/gallium/targets/xa-vmwgfx/Makefile.am | 6 -- src/gallium/targets/xorg-i915/Makefile.am | 6 -- src/gallium/targets/xorg-nouveau/Makefile.am | 6 -- src/gallium/targets/xorg-r600/Makefile.am | 6 -- src/gallium/targets/xorg-radeonsi/Makefile.am | 6 -- src/gallium/targets/xvmc-nouveau/Makefile.am | 6 -- src/gallium/targets/xvmc-r300/Makefile.am | 6 -- src/gallium/targets/xvmc-r600/Makefile.am | 6 -- src/gallium/targets/xvmc-softpipe/Makefile.am | 6 -- src/gbm/Makefile.am| 4 src/glx/Makefile.am| 7 --- src/mapi/es1api/Makefile.am| 8 src/mapi/es2api/Makefile.am| 8 src/mapi/shared-glapi/Makefile.am | 6 -- src/mapi/vgapi/Makefile.am | 8 src/mesa/drivers/dri/i915/Makefile.am | 6 -- src/mesa/drivers/dri/i965/Makefile.am | 6 -- src/mesa/drivers/dri/nouveau/Makefile.am | 6 -- src/mesa/drivers/dri/r200/Makefile.am | 6 -- src/mesa/drivers/dri/radeon/Makefile.am| 6 -- src/mesa/drivers/dri/swrast/Makefile.am| 6 -- src/mesa/drivers/osmesa/Makefile.am| 9 - src/mesa/drivers/x11/Makefile.am | 9 - src/mesa/libdricore/Makefile.am| 7 --- 43 files changed, 291 deletions(-) diff --git src/egl/main/Makefile.am src/egl/main/Makefile.am index ca5257a..61192d6 100644 --- src/egl/main/Makefile.am +++ src/egl/main/Makefile.am @@ -116,13 +116,6 @@ libEGL_la_LIBADD += ../drivers/dri2/libegl_dri2.la libEGL_la_LIBADD += $(LIBUDEV_LIBS) $(DLOPEN_LIBS) $(LIBDRM_LIBS) endif -# Provide compatibility with scripts for the old Mesa build system for -# a while by putting a link to the driver into /lib of the build tree. -all-local: libEGL.la - $(MKDIR_P) $(top_builddir)/$(LIB_DIR); - ln -f .libs/libEGL.so.1.0.0 $(top_builddir)/$(LIB_DIR)/libEGL.so.1 - ln -sf libEGL.so.1 $(top_builddir)/$(LIB_DIR)/libEGL.so - pkgconfigdir = $(libdir)/pkgconfig pkgconfig_DATA = egl.pc diff --git src/gallium/targets/dri-freedreno/Makefile.am src/gallium/targets/dri-freedreno/Makefile.am index cfa1f37..b39723e 100644 --- src/gallium/targets/dri-freedreno/Makefile.am +++ src/gallium/targets/dri-freedreno/Makefile.am @@ -65,9 +65,3 @@ if HAVE_MESA_LLVM kgsl_dri_la_LDFLAGS += $(LLVM_LDFLAGS) kgsl_dri_la_LIBADD += $(LLVM_LIBS) endif - -# Provide compatibility with scripts for the old Mesa build system for -# a while by putting a link to the driver into /lib of the build tree. -all-local: kgsl_dri.la - $(MKDIR_P) $(top_builddir)/$(LIB_DIR)/gallium - ln -f .libs/kgsl_dri.so $(top_builddir)/$(LIB_DIR)/gallium/kgsl_dri.so diff --git src/gallium/targets/dri-i915/Makefile.am src/gallium/targets/dri-i915/Makefile.am index ce6be78..818d340 100644 --- src/gallium/targets/dri-i915/Makefile.am +++ src/gallium/targets/dri-i915/Makefile.am @@ -68,9 +68,3 @@ if HAVE_MESA_LLVM AM_CPPFLAGS += -DGALLIUM_LLVMPIPE i915_dri_la_LIBADD += $(top_builddir)/src/gallium/drivers/llvmpipe/libllvmpipe.la $(LLVM_LIBS) endif - -# Provide compatibility with scripts for the old Mesa build system for -# a while by putting a link to the driver into /lib of the build tree. -all-local: i915_dri.la - $(MKDIR_P) $(top_builddir)/$(LIB_DIR)/gallium - ln -f .libs/i915_dri.so $(top_builddir)/$(LIB_DIR)/gallium/i915_dri.so diff --git src/galli
Re: [Mesa-dev] [PATCH 0/6] Eliminating unused built-in varyings
Hi, Am 19.06.2013 um 13:22 schrieb Marek Olšák : > Could somebody please review this series? I don't really know the code well enough to give a meaningful review, but I've tested the patches with Wine on r300g and they work as advertised :-) . Rendering is OK, and 3DMark2000 performance is improved from 4000 3dmarks to 7200. (The GL fixed function pipeline gets 8000, but that may be our bug) Cheers, Stefan ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] Mesa driver for VirtualBox
Hello, I am looking at the possibility of writing a driver for VirtualBox (ahem, yes) which could partly live inside of the Mesa tree. My initial idea was to have the driver in two parts, a driver/client part in the Mesa tree and a server part in the VirtualBox tree which would communicate using an agreed-on protocol through a local socket. The reasons for wanting to split the driver this way are on the one hand that we still don't feel quite ready to commit our host-guest 3D interface to eternity, and on the other that the driver part on the Mesa side might well be useful in other contexts - controlled 3D access (insofar as such a thing is possible) out of a sand box comes to mind. I was considering a textual protocol between client and server which would more or less model the Gallium3D API, with (texture and other) buffers passed using shared memory via file descriptors. Gallium3D would have the advantage that it is a much smaller target surface (if I may use that word) than OpenGL. It has the disadvantage that it is closer to D3D than to OpenGL, which may be better for modelling hardware, but perhaps less so for proxying OpenGL APIs on a guest to OpenGL APIs on a host. In particular the fact that we can't directly access the GLSL shader source which applications on a guest system are presumably trying to send us, and which we need to pass through to the host, disturbs me somewhat. Of course, I realise that on the other hand this potentially gives us access to shaders in different formats, but our main target will still be OpenGL on OpenGL for the immediately forseeable future. I understand that Gallium3D receives shaders in a format close to compiled D3D shaders, which suggests that WineD3D might be of use. An alternative is to go straight for a DRI driver rather than a Gallium3D one. I would be interested in any thoughts and suggestions! For background, I have some knowledge of 3D programming but am certainly no expert. I can browse the Mesa source code and the drivers in it without getting too worried, but need to use a search engine as I do so to feel confident that I understand what is happening in the code. I look forward to reading any answers. Thanks in advance! Michael -- ORACLE Deutschland B.V. & Co. KG Michael Thayer Werkstrasse 24 VirtualBox engineering 71384 Weinstadt, Germany mailto:michael.tha...@oracle.com Hauptverwaltung: Riesstr. 25, D-80992 München Registergericht: Amtsgericht München, HRA 95603 Geschäftsführer: Jürgen Kunz Komplementärin: ORACLE Deutschland Verwaltung B.V. Hertogswetering 163/167, 3543 AS Utrecht, Niederlande Handelsregister der Handelskammer Midden-Niederlande, Nr. 30143697 Geschäftsführer: Alexander van der Ven, Astrid Kepper, Val Maher ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 5/6] mesa: Fix missing setting of shader->IsES.
On 06/19/2013 03:57 PM, Eric Anholt wrote: Kenneth Graunke writes: On 06/17/2013 04:10 PM, Eric Anholt wrote: I noticed this while trying to merge code with the builtin compiler, which does set it. Note that this causes two regressions in piglit in default-precision-sampler.* which try to link without a vertex or fragment shader, due to being run under the desktop glslparsertest binary (using ARB_ES3_compatibility) that doesn't know about this requirement. That seems quite odd. There are ifdefs in glslparsertest for adding appropriate stub shaders for ES in an ES build, but if you run in ES3 compat on a desktop build, it doesn't happen. We should just be running these tests in the ES build. I don't think that's true - glslparsertest in master only appears to add stub shaders if the requested language version is 100. Presumably it ought to do the same for 300 es. Only running the tests on the actual ES3 api seems reasonable too, but I'm not sure it would fix the problem. --Ken ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] configure.ac: make grep tests more portable
Use grep -w instead of the empty string escape sequences
which are less portable. Makes the grep tests
function as intended on OpenBSD.
Signed-off-by: Jonathan Gray
---
configure.ac | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git configure.ac configure.ac
index 6832b0d..45d9b1c 100644
--- configure.ac
+++ configure.ac
@@ -1580,14 +1580,14 @@ if test "x$enable_gallium_llvm" = xyes; then
LLVM_VERSION=`$LLVM_CONFIG --version | sed 's/svn.*//g'`
LLVM_VERSION_INT=`echo $LLVM_VERSION | sed -e
's/\([[0-9]]\)\.\([[0-9]]\)/\10\2/g'`
LLVM_COMPONENTS="engine bitwriter"
-if $LLVM_CONFIG --components | grep -q '\'; then
+if $LLVM_CONFIG --components | grep -qw 'mcjit'; then
LLVM_COMPONENTS="${LLVM_COMPONENTS} mcjit"
fi
if test "x$enable_opencl" = xyes; then
LLVM_COMPONENTS="${LLVM_COMPONENTS} ipo linker instrumentation"
# LLVM 3.3 >= 177971 requires IRReader
-if $LLVM_CONFIG --components | grep -q '\'; then
+if $LLVM_CONFIG --components | grep -qw 'irreader'; then
LLVM_COMPONENTS="${LLVM_COMPONENTS} irreader"
fi
fi
@@ -1709,7 +1709,7 @@ radeon_llvm_check() {
if test "$LLVM_VERSION_INT" -lt
"${LLVM_REQUIRED_VERSION_MAJOR}0${LLVM_REQUIRED_VERSION_MINOR}"; then
AC_MSG_ERROR([LLVM
$LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR or newer is required
for r600g and radeonsi.])
fi
-if test true && $LLVM_CONFIG --targets-built | grep -qv '\' ; then
+if test true && $LLVM_CONFIG --targets-built | grep -qvw 'R600' ; then
AC_MSG_ERROR([LLVM R600 Target not enabled. You can enable it when
building the LLVM
sources with the --enable-experimental-targets=R600
configure flag])
--
1.8.3.1
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[Mesa-dev] [PATCH] nvc0: Display an error when DRM version is too old to use performance counters
From: Samuel
---
src/gallium/drivers/nvc0/nvc0_query.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_query.c
b/src/gallium/drivers/nvc0/nvc0_query.c
index 75c515a..7fc1ca9 100644
--- a/src/gallium/drivers/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nvc0/nvc0_query.c
@@ -1141,8 +1141,12 @@ nvc0_screen_get_driver_query_info(struct pipe_screen
*pscreen,
count += NVC0_QUERY_DRV_STAT_COUNT;
if (screen->base.class_3d >= NVE4_3D_CLASS) {
- if (screen->base.device->drm_version >= 0x01000101)
+ if (screen->base.device->drm_version >= 0x01000101) {
count += NVE4_PM_QUERY_COUNT;
+ } else {
+ NOUVEAU_ERR("DRM version is too old to use performance counters!\n");
+ return count;
+ }
}
if (!info)
return count;
--
1.8.3.1
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