Re: [Mesa-dev] OpenGL ES only configuration (without desktop OpenGL support)
On Tue, 6 Aug 2013 21:49:52 -0700 Matt Turner matts...@gmail.com wrote: On Tue, Aug 6, 2013 at 9:44 PM, Siarhei Siamashka siarhei.siamas...@gmail.com wrote: Based on a quick test, the current Mesa git master also can work in ES-only mode if the following commits are reverted: http://cgit.freedesktop.org/mesa/mesa/commit/?id=afa33a001a39c44238ba8fd76f8eeabad041459e This commit should be (should have been?) a no-op. Did it actually cause a problem? Yes, it somehow causes the following compilation error: egl_st.c:32:37: fatal error: state_tracker/st_gl_api.h: No such file or directory #include state_tracker/st_gl_api.h ^ I just used bisecting to identify the culprit and verified that reverting afa33a001a39c44238ba8fd76f8eeabad041459e makes this problem disappear. -- Best regards, Siarhei Siamashka ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] PATCH: R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE
On Die, 2013-08-06 at 16:12 -0700, Tom Stellard wrote: The attached patches teach the SI backend to lower BUILD_VECTOR to REG_SEQUENCE, which should help the register allocator produce better code. This also fixes 364 array indexing piglit tests. Actually, at least on SI, I think some tests were recently regressed and fixed again by other changes. I got this warning when importing the first patch with StGit: Importing patch 0001-R600-SI-Assign-a-register-class-to-the-vaddr-operand.patch ... stdin:404: new blank line at EOF. Other than that, the patches look good to me. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Debian, X and DRI developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] OSMesa (version 9.0) compile error
On 08/06/2013 11:02 AM, ZhiLi wrote: Hello everyone, I am trying to compile Mesa and OSMesa (version 9.0) on linux ubuntu 12.04. The compiled libGL.so works well, however, libOSMesa.so does not work. I check the properties of libOSMesa.so, it says: Name: libOSMesa.so Type: link(broken) (inode/symlink) Link target:libSOMesa.so.8.0.0 Size: 18 bytes Does anyone happen to have the same problem? How can I fix this problem? What was your ./configure command (or scons command)? What's the output of 'ls -l lib' (in the mesa directory)? -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] gallivm: propagate scalar_lod to emit_size_query too
From: Roland Scheidegger srol...@vmware.com
Clearly the returned values need to be per-element if the lod is per element.
Does not actually change behavior yet.
---
src/gallium/auxiliary/draw/draw_llvm_sample.c |2 ++
src/gallium/auxiliary/gallivm/lp_bld_sample.h |1 +
src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c |1 +
src/gallium/auxiliary/gallivm/lp_bld_tgsi.h |1 +
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c |5 +
src/gallium/drivers/llvmpipe/lp_tex_sample.c |2 ++
6 files changed, 12 insertions(+)
diff --git a/src/gallium/auxiliary/draw/draw_llvm_sample.c
b/src/gallium/auxiliary/draw/draw_llvm_sample.c
index 0cb5c21..3016d7c 100644
--- a/src/gallium/auxiliary/draw/draw_llvm_sample.c
+++ b/src/gallium/auxiliary/draw/draw_llvm_sample.c
@@ -271,6 +271,7 @@ draw_llvm_sampler_soa_emit_size_query(const struct
lp_build_sampler_soa *base,
struct lp_type type,
unsigned texture_unit,
boolean need_nr_mips,
+ boolean scalar_lod,
LLVMValueRef explicit_lod, /* optional */
LLVMValueRef *sizes_out)
{
@@ -284,6 +285,7 @@ draw_llvm_sampler_soa_emit_size_query(const struct
lp_build_sampler_soa *base,
type,
texture_unit,
need_nr_mips,
+ scalar_lod,
explicit_lod,
sizes_out);
}
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.h
b/src/gallium/auxiliary/gallivm/lp_bld_sample.h
index f9a2b3f..dff8be2 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.h
@@ -498,6 +498,7 @@ lp_build_size_query_soa(struct gallivm_state *gallivm,
struct lp_type int_type,
unsigned texture_unit,
boolean need_nr_mips,
+boolean scalar_lod,
LLVMValueRef explicit_lod,
LLVMValueRef *sizes_out);
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
index 122ec4f..6780d3e 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
@@ -1917,6 +1917,7 @@ lp_build_size_query_soa(struct gallivm_state *gallivm,
struct lp_type int_type,
unsigned texture_unit,
boolean need_nr_mips,
+boolean scalar_lod,
LLVMValueRef explicit_lod,
LLVMValueRef *sizes_out)
{
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
index 0b48450..aec019a 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.h
@@ -193,6 +193,7 @@ struct lp_build_sampler_soa
struct lp_type type,
unsigned unit,
boolean need_nr_mips,
+ boolean scalar_lod,
LLVMValueRef explicit_lod, /* optional */
LLVMValueRef *sizes_out);
};
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index c199385..02d804a 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -1990,6 +1990,7 @@ emit_size_query( struct lp_build_tgsi_soa_context *bld,
boolean is_sviewinfo)
{
LLVMValueRef explicit_lod;
+ boolean scalar_lod;
unsigned has_lod;
unsigned i;
unsigned unit = inst-Src[1].Register.Index;
@@ -2024,11 +2025,15 @@ emit_size_query( struct lp_build_tgsi_soa_context *bld,
else
explicit_lod = NULL;
+ /* TODO: use scalar lod if explicit_lod is broadcasted scalar */
+ scalar_lod = bld-bld_base.info-processor == TGSI_PROCESSOR_FRAGMENT;
+
bld-sampler-emit_size_query(bld-sampler,
bld-bld_base.base.gallivm,
bld-bld_base.int_bld.type,
unit,
is_sviewinfo,
+ scalar_lod,
explicit_lod,
sizes_out);
}
diff --git a/src/gallium/drivers/llvmpipe/lp_tex_sample.c
b/src/gallium/drivers/llvmpipe/lp_tex_sample.c
index 2fb6f5b..2aec6ea 100644
--- a/src/gallium/drivers/llvmpipe/lp_tex_sample.c
+++ b/src/gallium/drivers/llvmpipe/lp_tex_sample.c
@@ -281,6 +281,7 @@ lp_llvm_sampler_soa_emit_size_query(const struct
lp_build_sampler_soa *base,
[Mesa-dev] [PATCH 1/2] gallium: clarify SVIEWINFO opcode
From: Roland Scheidegger srol...@vmware.com This opcode is quite problematic in tgsi, while it tries to mirror d3d10 resinfo it can't really do what's stated there due to missing the crazy return type modifiers. Hence specify this is ignored along with the swizzle. (Other options would be to have multiple opcodes or specify the ret type modifier maybe in dst_reg as there's padding bits left there but it is the only instruction allowing this.) --- src/gallium/docs/source/tgsi.rst | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index 8506b7e..949ad89 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -1868,7 +1868,15 @@ after lookup. the mipmap level selected by the src_mip_level and are in the number of texels. For 1d texture array width is in dst.x, array size - is in dst.y and dst.zw are always 0. + is in dst.y and dst.z is 0. The number of mipmaps + is still in dst.w. + In contrast to d3d10 resinfo, there's no way in the + tgsi instruction encoding to specify the return type + (float/rcpfloat/uint), hence always using uint. Also, + unlike the SAMPLE instructions, the swizzle on src1 + resinfo allowing swizzling dst values is ignored (due + to the interaction with rcpfloat modifier which requires + some swizzle handling in the state tracker anyway). .. opcode:: SAMPLE_POS - query the position of a given sample. dst receives float4 (x, y, 0, 0) indicated where the -- 1.7.9.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] R300 'make check' build failure on master and 9.2
On Tue, Aug 06, 2013 at 10:12:19AM -0700, Ian Romanick wrote: We should set a goal for the 9.3 release: all drivers should just build and 'make check' without having to add a bunch of magic incantations to the configure line. We also need a build bot that will build and 'make check' every commit. Ugh. :( +1 for the buildbot I'm having trouble reproducing this, what configure flags are you using? -Tom CCLD r300_compiler_tests ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_format_s3tc.o): In function `util_format_linear_float_to_srgb_8unorm': /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_format_srgb.h:66: undefined reference to `powf' ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_format_table.o): In function `util_format_linear_float_to_srgb_8unorm': /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_format_srgb.h:66: undefined reference to `powf' ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_dl.o): In function `util_dl_open': /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_dl.c:48: undefined reference to `dlopen' ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_dl.o): In function `util_dl_get_proc_address': /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_dl.c:62: undefined reference to `dlsym' ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_dl.o): In function `util_dl_close': /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_dl.c:75: undefined reference to `dlclose' ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_dl.o): In function `util_dl_error': /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_dl.c:88: undefined reference to `dlerror' ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_format_other.o): In function `float3_to_rgb9e5': /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_format_rgb9e5.h:119: undefined reference to `pow' /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_format_rgb9e5.h:121: undefined reference to `floor' /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_format_rgb9e5.h:130: undefined reference to `floor' /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_format_rgb9e5.h:131: undefined reference to `floor' /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_format_rgb9e5.h:132: undefined reference to `floor' ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_format_other.o): In function `rgb9e5_to_float3': /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_format_rgb9e5.h:157: undefined reference to `pow' ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_format_other.o): In function `r8g8bx_derive': /home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/auxiliary/util/u_format_other.c:327: undefined reference to `sqrtf' collect2: error: ld returned 1 exit status gmake[4]: *** [r300_compiler_tests] Error 1 gmake[4]: Leaving directory `/home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/drivers/r300' gmake[3]: *** [check-am] Error 2 gmake[3]: Leaving directory `/home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/drivers/r300' gmake[2]: *** [check-recursive] Error 1 gmake[2]: Leaving directory `/home/idr/devel/graphics/Mesa/BUILD/master-64/src/gallium/drivers' gmake[1]: *** [check-recursive] Error 1 gmake[1]: Leaving directory `/home/idr/devel/graphics/Mesa/BUILD/master-64/src' make: *** [check-recursive] Error 1 make: Leaving directory `/home/idr/devel/graphics/Mesa/BUILD/master-64' ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] clover: Fix linkage of libOpenCL
Clover needs the option component of llvm.
Signed-off-by: Niels Ole Salscheider niels_...@salscheider-online.de
---
configure.ac | 4
1 Datei geändert, 4 Zeilen hinzugefügt(+)
diff --git a/configure.ac b/configure.ac
index 62d06e0..0dcd2a5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1617,6 +1617,10 @@ if test x$enable_gallium_llvm = xyes; then
if $LLVM_CONFIG --components | grep -qw 'irreader'; then
LLVM_COMPONENTS=${LLVM_COMPONENTS} irreader
fi
+# LLVM 3.4 requires Option
+if $LLVM_CONFIG --components | grep -qw 'option'; then
+LLVM_COMPONENTS=${LLVM_COMPONENTS} option
+fi
fi
DEFINES=${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT
MESA_LLVM=1
--
1.7.11.7
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[Mesa-dev] [PATCH 1/2] R600/SI: Implement sint-fp64 conversions
---
lib/Target/R600/SIInstrInfo.td| 6 ++
lib/Target/R600/SIInstructions.td | 8 ++--
test/CodeGen/R600/fp64_to_sint.ll | 9 +
test/CodeGen/R600/sint_to_fp64.ll | 9 +
4 Dateien geändert, 30 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)
create mode 100644 test/CodeGen/R600/fp64_to_sint.ll
create mode 100644 test/CodeGen/R600/sint_to_fp64.ll
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 52af79c..302fa24 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -184,6 +184,12 @@ multiclass VOP1_32 bits8 op, string opName, listdag
pattern
multiclass VOP1_64 bits8 op, string opName, listdag pattern
: VOP1_Helper op, VReg_64, VSrc_64, opName, pattern;
+multiclass VOP1_32_64 bits8 op, string opName, listdag pattern
+ : VOP1_Helper op, VReg_32, VSrc_64, opName, pattern;
+
+multiclass VOP1_64_32 bits8 op, string opName, listdag pattern
+ : VOP1_Helper op, VReg_64, VSrc_32, opName, pattern;
+
multiclass VOP2_Helper bits6 op, RegisterClass vrc, RegisterClass arc,
string opName, listdag pattern, string revOp {
def _e32 : VOP2
diff --git a/lib/Target/R600/SIInstructions.td
b/lib/Target/R600/SIInstructions.td
index 500d15e..efe7a3e 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -603,8 +603,12 @@ defm V_MOV_B32 : VOP1_32 0x0001, V_MOV_B32, [];
} // End neverHasSideEffects = 1, isMoveImm = 1
defm V_READFIRSTLANE_B32 : VOP1_32 0x0002, V_READFIRSTLANE_B32, [];
-//defm V_CVT_I32_F64 : VOP1_32 0x0003, V_CVT_I32_F64, [];
-//defm V_CVT_F64_I32 : VOP1_64 0x0004, V_CVT_F64_I32, [];
+defm V_CVT_I32_F64 : VOP1_32_64 0x0003, V_CVT_I32_F64,
+ [(set i32:$dst, (fp_to_sint f64:$src0))]
+;
+defm V_CVT_F64_I32 : VOP1_64_32 0x0004, V_CVT_F64_I32,
+ [(set f64:$dst, (sint_to_fp i32:$src0))]
+;
defm V_CVT_F32_I32 : VOP1_32 0x0005, V_CVT_F32_I32,
[(set f32:$dst, (sint_to_fp i32:$src0))]
;
diff --git a/test/CodeGen/R600/fp64_to_sint.ll
b/test/CodeGen/R600/fp64_to_sint.ll
new file mode 100644
index 000..42f9f34
--- /dev/null
+++ b/test/CodeGen/R600/fp64_to_sint.ll
@@ -0,0 +1,9 @@
+; RUN: llc %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK
+
+; CHECK: @fp64_to_sint
+; CHECK: V_CVT_I32_F64_e32
+define void @fp64_to_sint(i32 addrspace(1)* %out, double %in) {
+ %result = fptosi double %in to i32
+ store i32 %result, i32 addrspace(1)* %out
+ ret void
+}
diff --git a/test/CodeGen/R600/sint_to_fp64.ll
b/test/CodeGen/R600/sint_to_fp64.ll
new file mode 100644
index 000..37f67c9
--- /dev/null
+++ b/test/CodeGen/R600/sint_to_fp64.ll
@@ -0,0 +1,9 @@
+; RUN: llc %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK
+
+; CHECK: @sint_to_fp64
+; CHECK: V_CVT_F64_I32_e32
+define void @sint_to_fp64(double addrspace(1)* %out, i32 %in) {
+ %result = sitofp i32 %in to double
+ store double %result, double addrspace(1)* %out
+ ret void
+}
--
1.7.11.7
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[Mesa-dev] [PATCH 2/2] R600/SI: Implement fp32-fp64 conversions
---
lib/Target/R600/SIISelLowering.cpp | 3 +++
lib/Target/R600/SIInstructions.td | 8 ++--
test/CodeGen/R600/fpext.ll | 9 +
test/CodeGen/R600/fptrunc.ll | 9 +
4 Dateien geändert, 27 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)
create mode 100644 test/CodeGen/R600/fpext.ll
create mode 100644 test/CodeGen/R600/fptrunc.ll
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index c64027f..b714fc1 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -85,6 +85,9 @@ SITargetLowering::SITargetLowering(TargetMachine TM) :
setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
+ setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setTargetDAGCombine(ISD::SELECT_CC);
diff --git a/lib/Target/R600/SIInstructions.td
b/lib/Target/R600/SIInstructions.td
index efe7a3e..dc41885 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -625,8 +625,12 @@ defm V_MOV_FED_B32 : VOP1_32 0x0009, V_MOV_FED_B32,
[];
//defm V_CVT_RPI_I32_F32 : VOP1_32 0x000c, V_CVT_RPI_I32_F32, [];
//defm V_CVT_FLR_I32_F32 : VOP1_32 0x000d, V_CVT_FLR_I32_F32, [];
//defm V_CVT_OFF_F32_I4 : VOP1_32 0x000e, V_CVT_OFF_F32_I4, [];
-//defm V_CVT_F32_F64 : VOP1_32 0x000f, V_CVT_F32_F64, [];
-//defm V_CVT_F64_F32 : VOP1_64 0x0010, V_CVT_F64_F32, [];
+defm V_CVT_F32_F64 : VOP1_32_64 0x000f, V_CVT_F32_F64,
+ [(set f32:$dst, (fround f64:$src0))]
+;
+defm V_CVT_F64_F32 : VOP1_64_32 0x0010, V_CVT_F64_F32,
+ [(set f64:$dst, (fextend f32:$src0))]
+;
//defm V_CVT_F32_UBYTE0 : VOP1_32 0x0011, V_CVT_F32_UBYTE0, [];
//defm V_CVT_F32_UBYTE1 : VOP1_32 0x0012, V_CVT_F32_UBYTE1, [];
//defm V_CVT_F32_UBYTE2 : VOP1_32 0x0013, V_CVT_F32_UBYTE2, [];
diff --git a/test/CodeGen/R600/fpext.ll b/test/CodeGen/R600/fpext.ll
new file mode 100644
index 000..e02c19c
--- /dev/null
+++ b/test/CodeGen/R600/fpext.ll
@@ -0,0 +1,9 @@
+; RUN: llc %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK
+
+; CHECK: @fpext
+; CHECK: V_CVT_F64_F32_e32
+define void @fpext(double addrspace(1)* %out, float %in) {
+ %result = fpext float %in to double
+ store double %result, double addrspace(1)* %out
+ ret void
+}
diff --git a/test/CodeGen/R600/fptrunc.ll b/test/CodeGen/R600/fptrunc.ll
new file mode 100644
index 000..2a10f63
--- /dev/null
+++ b/test/CodeGen/R600/fptrunc.ll
@@ -0,0 +1,9 @@
+; RUN: llc %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK
+
+; CHECK: @fptrunc
+; CHECK: V_CVT_F32_F64_e32
+define void @fptrunc(float addrspace(1)* %out, double %in) {
+ %result = fptrunc double %in to float
+ store float %result, float addrspace(1)* %out
+ ret void
+}
--
1.7.11.7
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Re: [Mesa-dev] [PATCH 3/3] i965/blorp: Add support for single sample scaled blit with bilinear filter
On Tue, Aug 6, 2013 at 3:05 PM, Paul Berry stereotype...@gmail.com wrote:
On 5 August 2013 15:37, Anuj Phogat anuj.pho...@gmail.com wrote:
Currently single sample scaled blits with GL_LINEAR filter falls
back to meta path. Patch removes this limitation in BLORP engine
and implements single sample scaled blit with bilinear filter.
No piglit, gles3 regressions are obeserved with this patch. Piglit
test case patches to verify this implementation are out on piglit
mailing list.
I'm uncomfortable with the approach taken in this patch, because it
doesn't make use of the bilinear filtering capability built into the
sampling hardware.
Back when you were implementing EXT_framebuffer_multisample_blit_scaled,
there was good reason not to use the sampler's bilinear filtering
capability--because it doesn't work properly for multisampled textures.
But for scaled blitting of single-sampled textures it should work fine, and
in all likelihood it will be faster than doing manual bilinear filtering in
the shader. Also, there's a higher risk of making mistakes if we manually
implement bilinear filtering in the shader.
I'd recommend instead using the sample message to read from the surface
when doing GL_LINEAR filtering.
Yes, It'll be more efficient to use inbuilt support for bilinear filtering
in hardware. I'll modify my patch
to use sample message.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_blorp.h | 7 +-
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 157
--
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +-
3 files changed, 132 insertions(+), 36 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 49862b8..be40625 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -44,7 +44,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
float src_x1, float src_y1,
float dst_x0, float dst_y0,
float dst_x1, float dst_y1,
-bool mirror_x, bool mirror_y);
+GLenum filter, bool mirror_x, bool mirror_y);
bool
brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
@@ -333,6 +333,9 @@ struct brw_blorp_blit_prog_key
*/
float x_scale;
float y_scale;
+
+ /* True for single sample scaled blits with linear filter. */
+ bool bilinear_filter;
};
class brw_blorp_blit_params : public brw_blorp_params
@@ -347,7 +350,7 @@ public:
GLfloat src_x1, GLfloat src_y1,
GLfloat dst_x0, GLfloat dst_y0,
GLfloat dst_x1, GLfloat dst_y1,
- bool mirror_x, bool mirror_y);
+ GLenum filter, bool mirror_x, bool mirror_y);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 8c0db48..0a28026 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -133,7 +133,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
float src_x1, float src_y1,
float dst_x0, float dst_y0,
float dst_x1, float dst_y1,
-bool mirror_x, bool mirror_y)
+GLenum filter, bool mirror_x, bool mirror_y)
{
/* Get ready to blit. This includes depth resolving the src and dst
* buffers if necessary. Note: it's not necessary to do a color
resolve on
@@ -161,7 +161,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
src_x1, src_y1,
dst_x0, dst_y0,
dst_x1, dst_y1,
-mirror_x, mirror_y);
+filter, mirror_x, mirror_y);
brw_blorp_exec(brw, params);
intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level,
dst_layer);
@@ -173,7 +173,7 @@ do_blorp_blit(struct brw_context *brw, GLbitfield
buffer_bit,
struct intel_renderbuffer *dst_irb,
GLfloat srcX0, GLfloat srcY0, GLfloat srcX1, GLfloat srcY1,
GLfloat dstX0, GLfloat dstY0, GLfloat dstX1, GLfloat dstY1,
- bool mirror_x, bool mirror_y)
+ GLenum filter, bool mirror_x, bool mirror_y)
{
/* Find source/dst miptrees */
struct intel_mipmap_tree *src_mt = find_miptree(buffer_bit, src_irb);
@@ -185,7 +185,7 @@ do_blorp_blit(struct brw_context *brw, GLbitfield
buffer_bit,
dst_mt, dst_irb-mt_level, dst_irb-mt_layer,
srcX0,
[Mesa-dev] [PATCH] main: Fix deprecation of glLineWidth()
From section E.1 (Profiles and Deprecated Features of OpenGL 3.0)
of the OpenGL 3.0 spec:
LineWidth is not deprecated, but values greater than 1.0
will generate an INVALID VALUE error
From context it is clear that values greater than 1.0 should only
generate an INVALID VALUE error in a forward-compatible context.
The code was correctly quoting this spec text, but it was disallowing
all line widths in forward-compatible contexts, instead of just widths
greater than 1.0.
This patch introduces the correct check, so that setting a line width
of 1.0 or less is permitted.
---
src/mesa/main/lines.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/lines.c b/src/mesa/main/lines.c
index 0df9d66..3c08ed2 100644
--- a/src/mesa/main/lines.c
+++ b/src/mesa/main/lines.c
@@ -56,19 +56,20 @@ _mesa_LineWidth( GLfloat width )
* Wide lines and line stipple - LineWidth is not deprecated, but
* values greater than 1.0 will generate an INVALID_VALUE error;
*
* This is one of the very few cases where functionality was deprecated but
* *NOT* removed in a later spec. Therefore, we only disallow this in a
* forward compatible context.
*/
if (ctx-API == API_OPENGL_CORE
((ctx-Const.ContextFlags GL_CONTEXT_FLAG_FORWARD_COMPATIBLE_BIT)
- != 0)) {
+ != 0)
+width 1.0) {
_mesa_error( ctx, GL_INVALID_VALUE, glLineWidth );
return;
}
if (ctx-Line.Width == width)
return;
FLUSH_VERTICES(ctx, _NEW_LINE);
ctx-Line.Width = width;
--
1.8.3.4
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[Mesa-dev] [PATCH] glsl: Enable ARB_fragment_coord_conventions functionality in GLSL 1.50.
GLSL 1.50 incorporates the functionality of the
ARB_fragment_coord_conventions extension, so we need to make this
functionality available even if the extension isn't enabled.
---
src/glsl/ast_to_hir.cpp | 3 ++-
src/glsl/glsl_parser.yy | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 482ab3c..bfdf8e3 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2332,7 +2332,8 @@ get_variable_being_redeclared(ir_variable *var,
ast_declaration *decl,
earlier-type = var-type;
delete var;
var = NULL;
- } else if (state-ARB_fragment_coord_conventions_enable
+ } else if ((state-ARB_fragment_coord_conventions_enable ||
+ state-is_version(150, 0))
strcmp(var-name, gl_FragCoord) == 0
earlier-type == var-type
earlier-mode == var-mode) {
diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy
index a847d2a..e3a57ea 100644
--- a/src/glsl/glsl_parser.yy
+++ b/src/glsl/glsl_parser.yy
@@ -1158,7 +1158,8 @@ layout_qualifier_id:
memset( $$, 0, sizeof($$));
/* Layout qualifiers for ARB_fragment_coord_conventions. */
- if (!$$.flags.i state-ARB_fragment_coord_conventions_enable) {
+ if (!$$.flags.i (state-ARB_fragment_coord_conventions_enable ||
+ state-is_version(150, 0))) {
if (strcmp($1, origin_upper_left) == 0) {
$$.flags.q.origin_upper_left = 1;
} else if (strcmp($1, pixel_center_integer) == 0) {
--
1.8.3.4
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Re: [Mesa-dev] [PATCH mesa 3/3] egl: Update to Wayland 1.2 server API
On Thu, Jul 18, 2013 at 03:11:25PM +0300, Ander Conselvan de Oliveira wrote:
Since Wayland 1.2, struct wl_buffer and a few functions are deprecated.
References to wl_buffer are replaced with wl_resource and some getter
functions and calls to deprecated functions are replaced with the proper
new API. The latter changes are related to resource versioning.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
Thanks Ander, this and the two previous patches pushed.
Kristian
---
docs/specs/WL_bind_wayland_display.spec| 8 ++-
include/EGL/eglmesaext.h | 6 +-
src/egl/drivers/dri2/egl_dri2.c| 28 +
src/egl/drivers/dri2/egl_dri2.h| 1 -
src/egl/main/eglapi.c | 2 +-
src/egl/main/eglapi.h | 2 +-
src/egl/wayland/wayland-drm/wayland-drm.c | 66
+-
src/egl/wayland/wayland-drm/wayland-drm.h | 13 +++--
.../state_trackers/egl/common/egl_g3d_api.c| 2 +-
.../state_trackers/egl/common/egl_g3d_image.c | 4 +-
.../egl/common/native_wayland_bufmgr.h | 6 +-
.../egl/common/native_wayland_drm_bufmgr.c | 25 +---
src/gbm/backends/dri/gbm_dri.c | 5 +-
13 files changed, 99 insertions(+), 69 deletions(-)
diff --git a/docs/specs/WL_bind_wayland_display.spec
b/docs/specs/WL_bind_wayland_display.spec
index 02bd6ea..8f0083c 100644
--- a/docs/specs/WL_bind_wayland_display.spec
+++ b/docs/specs/WL_bind_wayland_display.spec
@@ -17,7 +17,7 @@ Status
Version
-Version 1, March 1, 2011
+Version 5, July 16, 2013
Number
@@ -57,7 +57,7 @@ New Procedures and Functions
struct wl_display *display);
EGLBoolean eglQueryWaylandBufferWL(EGLDisplay dpy,
- struct wl_buffer *buffer,
+ struct wl_resource *buffer,
EGLint attribute, EGLint *value);
New Tokens
@@ -173,3 +173,7 @@ Revision History
Use EGL_TEXTURE_FORMAT, EGL_TEXTURE_RGB, and EGL_TEXTURE_RGBA,
and just define the new YUV texture formats. Add support for
EGL_WIDTH and EGL_HEIGHT in the query attributes (Kristian Høgsberg)
+Version 5, July 16, 2013
+Change eglQueryWaylandBufferWL to take a resource pointer to the
+buffer instead of a pointer to a struct wl_buffer, as the latter has
+been deprecated. (Ander Conselvan de Oliveira)
diff --git a/include/EGL/eglmesaext.h b/include/EGL/eglmesaext.h
index d476d18..e0eae28 100644
--- a/include/EGL/eglmesaext.h
+++ b/include/EGL/eglmesaext.h
@@ -120,15 +120,15 @@ typedef EGLDisplay (EGLAPIENTRYP
PFNEGLGETDRMDISPLAYMESA) (int fd);
#define EGL_TEXTURE_Y_XUXV_WL 0x31D9
struct wl_display;
-struct wl_buffer;
+struct wl_resource;
#ifdef EGL_EGLEXT_PROTOTYPES
EGLAPI EGLBoolean EGLAPIENTRY eglBindWaylandDisplayWL(EGLDisplay dpy, struct
wl_display *display);
EGLAPI EGLBoolean EGLAPIENTRY eglUnbindWaylandDisplayWL(EGLDisplay dpy,
struct wl_display *display);
-EGLAPI EGLBoolean EGLAPIENTRY eglQueryWaylandBufferWL(EGLDisplay dpy, struct
wl_buffer *buffer, EGLint attribute, EGLint *value);
+EGLAPI EGLBoolean EGLAPIENTRY eglQueryWaylandBufferWL(EGLDisplay dpy, struct
wl_resource *buffer, EGLint attribute, EGLint *value);
#endif
typedef EGLBoolean (EGLAPIENTRYP PFNEGLBINDWAYLANDDISPLAYWL) (EGLDisplay
dpy, struct wl_display *display);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLUNBINDWAYLANDDISPLAYWL) (EGLDisplay
dpy, struct wl_display *display);
-typedef EGLBoolean (EGLAPIENTRYP PFNEGLQUERYWAYLANDBUFFERWL) (EGLDisplay
dpy, struct wl_buffer *buffer, EGLint attribute, EGLint *value);
+typedef EGLBoolean (EGLAPIENTRYP PFNEGLQUERYWAYLANDBUFFERWL) (EGLDisplay
dpy, struct wl_resource *buffer, EGLint attribute, EGLint *value);
#endif
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 1bce314..44fd8a8 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -41,6 +41,10 @@
#include egl_dri2.h
+#ifdef HAVE_WAYLAND_PLATFORM
+#include wayland-drm.h
+#endif
+
const __DRIuseInvalidateExtension use_invalidate = {
{ __DRI_USE_INVALIDATE, 1 }
};
@@ -1195,7 +1199,7 @@ dri2_create_image_wayland_wl_buffer(_EGLDisplay *disp,
_EGLContext *ctx,
EGLClientBuffer _buffer,
const EGLint *attr_list)
{
- struct wl_drm_buffer *buffer = (struct wl_drm_buffer *) _buffer;
+ struct wl_drm_buffer *buffer;
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
const struct wl_drm_components_descriptor *f;
__DRIimage *dri_image;
@@ -1203,7 +1207,8 @@
Re: [Mesa-dev] [PATCH] glsl: Enable ARB_fragment_coord_conventions functionality in GLSL 1.50.
On 08/07/2013 10:31 AM, Paul Berry wrote: GLSL 1.50 incorporates the functionality of the ARB_fragment_coord_conventions extension, so we need to make this functionality available even if the extension isn't enabled. --- src/glsl/ast_to_hir.cpp | 3 ++- src/glsl/glsl_parser.yy | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Kenneth Graunke kenn...@whitecape.org ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] segfault in pstip_bind_sampler_states
One of the VTK tests (vtkFiltersHybridPython-largeImageOffset) makes OSMesa segfault. This is the top of the gdb backtrace : #0 pstip_bind_sampler_states (pipe=optimized out, num=0, sampler=0x0) at draw/draw_pipe_pstipple.c:713 #1 0x7fffdf7580fc in cso_release_all (ctx=ctx@entry=0x15f1540) at cso_cache/cso_context.c:307 #2 0x7fffdf6aebad in st_destroy_context (st=0x15da330) at ../../src/mesa/state_tracker/st_context.c:287 #3 0x7fffdf888022 in OSMesaDestroyContext (osmesa=0x13622d0) at osmesa.c:583 #4 0x7fffdcc02c13 in vtkOSOpenGLRenderWindow::DestroyOffScreenWindow (this=0xec6770) at /home/kevin/kitware/VTK/Rendering/OpenGL/vtkOSOpenGLRenderWindow.cxx:226 Do I interpret that as pstip_bind_sampler_states was sent a null pointer sampler? signature.asc Description: OpenPGP digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] gallivm: don't clamp reference value for shadow comparison for float formats
From: Roland Scheidegger srol...@vmware.com
This is wrong both for OpenGL and d3d. (In fact clamping is a side effect
of converting to depth format, so this should really do quantization too
at least in d3d10 for the comparisons to be truly correct.)
---
src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
index 6780d3e..337b6f7 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
@@ -1445,6 +1445,8 @@ lp_build_sample_compare(struct lp_build_sample_context
*bld,
LLVMBuilderRef builder = bld-gallivm-builder;
LLVMValueRef res, p;
const unsigned chan = 0;
+ unsigned chan_type;
+ const struct util_format_description *format_desc;
if (bld-static_sampler_state-compare_mode == PIPE_TEX_COMPARE_NONE)
return;
@@ -1466,11 +1468,22 @@ lp_build_sample_compare(struct lp_build_sample_context
*bld,
coord, tex);
}
- /* Clamp p coords to [0,1] */
- p = lp_build_clamp(bld-coord_bld, p,
- bld-coord_bld.zero,
- bld-coord_bld.one);
+ /* Clamp p coords to [0,1] for fixed function depth texture format */
+ format_desc = util_format_description(bld-static_texture_state-format);
+ /* not entirely sure we couldn't end up with non-valid swizzle here */
+ chan_type = format_desc-swizzle[0] = UTIL_FORMAT_SWIZZLE_W ?
+ format_desc-channel[format_desc-swizzle[0]].type :
+ UTIL_FORMAT_TYPE_FLOAT;
+ if (chan_type != UTIL_FORMAT_TYPE_FLOAT) {
+ p = lp_build_clamp(bld-coord_bld, p,
+ bld-coord_bld.zero, bld-coord_bld.one);
+ }
+ /*
+* technically this is not entirely correct for unorm depth as the ref value
+* should be converted to the depth format (quantization!) and comparison
+* then done in texture format.
+*/
/* result = (p FUNC texel) ? 1 : 0 */
res = lp_build_cmp(texel_bld, bld-static_sampler_state-compare_func,
p, texel[chan]);
--
1.7.9.5
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[Mesa-dev] [PATCH 2/2] softpipe: don't clamp reference value for shadow comparison for float formats
From: Roland Scheidegger srol...@vmware.com
Clamping is only done for fixed-point formats as part of conversion to
texture format.
---
src/gallium/drivers/softpipe/sp_tex_sample.c | 44 +++---
1 file changed, 32 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c
b/src/gallium/drivers/softpipe/sp_tex_sample.c
index 8de2712..4121857 100644
--- a/src/gallium/drivers/softpipe/sp_tex_sample.c
+++ b/src/gallium/drivers/softpipe/sp_tex_sample.c
@@ -2294,6 +2294,8 @@ sample_compare(struct sp_sampler_view *sp_sview,
int j, k0, k1, k2, k3;
float val;
float pc0, pc1, pc2, pc3;
+ const struct util_format_description *format_desc;
+ unsigned chan_type;
/**
* Compare texcoord 'p' (aka R) against texture value 'rgba[0]'
@@ -2304,21 +2306,39 @@ sample_compare(struct sp_sampler_view *sp_sview,
if (sp_sview-base.texture-target == PIPE_TEXTURE_2D_ARRAY ||
sp_sview-base.texture-target == PIPE_TEXTURE_CUBE) {
- pc0 = CLAMP(c0[0], 0.0F, 1.0F);
- pc1 = CLAMP(c0[1], 0.0F, 1.0F);
- pc2 = CLAMP(c0[2], 0.0F, 1.0F);
- pc3 = CLAMP(c0[3], 0.0F, 1.0F);
+ pc0 = c0[0];
+ pc1 = c0[1];
+ pc2 = c0[2];
+ pc3 = c0[3];
} else if (sp_sview-base.texture-target == PIPE_TEXTURE_CUBE_ARRAY) {
- pc0 = CLAMP(c1[0], 0.0F, 1.0F);
- pc1 = CLAMP(c1[1], 0.0F, 1.0F);
- pc2 = CLAMP(c1[2], 0.0F, 1.0F);
- pc3 = CLAMP(c1[3], 0.0F, 1.0F);
+ pc0 = c1[0];
+ pc1 = c1[1];
+ pc2 = c1[2];
+ pc3 = c1[3];
} else {
- pc0 = CLAMP(p[0], 0.0F, 1.0F);
- pc1 = CLAMP(p[1], 0.0F, 1.0F);
- pc2 = CLAMP(p[2], 0.0F, 1.0F);
- pc3 = CLAMP(p[3], 0.0F, 1.0F);
+ pc0 = p[0];
+ pc1 = p[1];
+ pc2 = p[2];
+ pc3 = p[3];
+ }
+
+ format_desc = util_format_description(sp_sview-base.format);
+ /* not entirely sure we couldn't end up with non-valid swizzle here */
+ chan_type = format_desc-swizzle[0] = UTIL_FORMAT_SWIZZLE_W ?
+ format_desc-channel[format_desc-swizzle[0]].type :
+ UTIL_FORMAT_TYPE_FLOAT;
+ if (chan_type != UTIL_FORMAT_TYPE_FLOAT) {
+ /*
+ * clamping is a result of conversion to texture format, hence
+ * doesn't happen with floats. Technically also should do comparison
+ * in texture format (quantization!).
+ */
+ pc0 = CLAMP(pc0, 0.0F, 1.0F);
+ pc1 = CLAMP(pc1, 0.0F, 1.0F);
+ pc2 = CLAMP(pc2, 0.0F, 1.0F);
+ pc3 = CLAMP(pc3, 0.0F, 1.0F);
}
+
/* compare four texcoords vs. four texture samples */
switch (sampler-compare_func) {
case PIPE_FUNC_LESS:
--
1.7.9.5
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[Mesa-dev] [PATCH] gallivm: honor d3d10 floating point rules for shadow comparisons
From: Roland Scheidegger srol...@vmware.com
d3d10 specifies ordered comparisons for everything but not_equal which is
unordered
(http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx).
OpenGL probably doesn't care.
---
src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
index 337b6f7..4305c49 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
@@ -1484,12 +1484,26 @@ lp_build_sample_compare(struct lp_build_sample_context
*bld,
* should be converted to the depth format (quantization!) and comparison
* then done in texture format.
*/
+
/* result = (p FUNC texel) ? 1 : 0 */
- res = lp_build_cmp(texel_bld, bld-static_sampler_state-compare_func,
- p, texel[chan]);
+ /*
+* honor d3d10 floating point rules here, which state that comparisons
+* are ordered except NOT_EQUAL which is unordered.
+*/
+ if (bld-static_sampler_state-compare_func != PIPE_FUNC_NOTEQUAL) {
+ res = lp_build_cmp_ordered(texel_bld,
bld-static_sampler_state-compare_func,
+ p, texel[chan]);
+ }
+ else {
+ res = lp_build_cmp(texel_bld, bld-static_sampler_state-compare_func,
+ p, texel[chan]);
+ }
res = lp_build_select(texel_bld, res, texel_bld-one, texel_bld-zero);
- /* XXX returning result for default GL_DEPTH_TEXTURE_MODE = GL_LUMINANCE */
+ /*
+* returning result for default GL_DEPTH_TEXTURE_MODE = GL_LUMINANCE.
+* This should be ok because sampler swizzle is applied on top of it.
+*/
texel[0] =
texel[1] =
texel[2] = res;
--
1.7.9.5
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Re: [Mesa-dev] [PATCH] main: Fix deprecation of glLineWidth()
On Wed, Aug 7, 2013 at 10:28 AM, Paul Berry stereotype...@gmail.com wrote:
From section E.1 (Profiles and Deprecated Features of OpenGL 3.0)
of the OpenGL 3.0 spec:
LineWidth is not deprecated, but values greater than 1.0
will generate an INVALID VALUE error
From context it is clear that values greater than 1.0 should only
generate an INVALID VALUE error in a forward-compatible context.
The code was correctly quoting this spec text, but it was disallowing
all line widths in forward-compatible contexts, instead of just widths
greater than 1.0.
This patch introduces the correct check, so that setting a line width
of 1.0 or less is permitted.
---
src/mesa/main/lines.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/lines.c b/src/mesa/main/lines.c
index 0df9d66..3c08ed2 100644
--- a/src/mesa/main/lines.c
+++ b/src/mesa/main/lines.c
@@ -56,19 +56,20 @@ _mesa_LineWidth( GLfloat width )
* Wide lines and line stipple - LineWidth is not deprecated, but
* values greater than 1.0 will generate an INVALID_VALUE error;
*
* This is one of the very few cases where functionality was deprecated
but
* *NOT* removed in a later spec. Therefore, we only disallow this in a
* forward compatible context.
*/
if (ctx-API == API_OPENGL_CORE
((ctx-Const.ContextFlags GL_CONTEXT_FLAG_FORWARD_COMPATIBLE_BIT)
- != 0)) {
+ != 0)
+width 1.0) {
_mesa_error( ctx, GL_INVALID_VALUE, glLineWidth );
return;
}
if (ctx-Line.Width == width)
return;
FLUSH_VERTICES(ctx, _NEW_LINE);
ctx-Line.Width = width;
--
1.8.3.4
Reviewed-by: Matt Turner matts...@gmail.com
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Re: [Mesa-dev] [PATCH] glsl: Enable ARB_fragment_coord_conventions functionality in GLSL 1.50.
On Wed, Aug 7, 2013 at 10:31 AM, Paul Berry stereotype...@gmail.com wrote:
GLSL 1.50 incorporates the functionality of the
ARB_fragment_coord_conventions extension, so we need to make this
functionality available even if the extension isn't enabled.
---
src/glsl/ast_to_hir.cpp | 3 ++-
src/glsl/glsl_parser.yy | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 482ab3c..bfdf8e3 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2332,7 +2332,8 @@ get_variable_being_redeclared(ir_variable *var,
ast_declaration *decl,
earlier-type = var-type;
delete var;
var = NULL;
- } else if (state-ARB_fragment_coord_conventions_enable
+ } else if ((state-ARB_fragment_coord_conventions_enable ||
+ state-is_version(150, 0))
strcmp(var-name, gl_FragCoord) == 0
earlier-type == var-type
earlier-mode == var-mode) {
diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy
index a847d2a..e3a57ea 100644
--- a/src/glsl/glsl_parser.yy
+++ b/src/glsl/glsl_parser.yy
@@ -1158,7 +1158,8 @@ layout_qualifier_id:
memset( $$, 0, sizeof($$));
/* Layout qualifiers for ARB_fragment_coord_conventions. */
- if (!$$.flags.i state-ARB_fragment_coord_conventions_enable) {
+ if (!$$.flags.i (state-ARB_fragment_coord_conventions_enable ||
+ state-is_version(150, 0))) {
if (strcmp($1, origin_upper_left) == 0) {
$$.flags.q.origin_upper_left = 1;
} else if (strcmp($1, pixel_center_integer) == 0) {
--
1.8.3.4
I looked through the other uses of
ARB_fragment_coord_conventions_enable and no others looked like they
needed to be updated.
Reviewed-by: Matt Turner matts...@gmail.com
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Re: [Mesa-dev] [PATCH 2/2] gallivm: propagate scalar_lod to emit_size_query too
- Original Message - From: Roland Scheidegger srol...@vmware.com Clearly the returned values need to be per-element if the lod is per element. Does not actually change behavior yet. Looks good. For the entire series: Reviewed-by: Zack Rusin za...@vmware.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa/vbo: Fix handling of attribute 0 in non-compatibilty contexts
From: Ian Romanick ian.d.roman...@intel.com
It is only in OpenGL compatibility-style contexts where generic
attribute 0 and GL_VERTEX_ARRAY have a bizzare, aliasing relationship.
Moreover, it is only in OpenGL compatibility-style contexts and OpenGL
ES 1.x where one of these attributes provokes the vertex. In all other
APIs each implicit call to glArrayElement provokes a vertex regardless
of which attributes are enabled.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Cc: Robert Bragg rob...@sixbynine.org
Cc: 9.0 9.1 9.2 mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55503
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66292
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67548
---
This patch is probably easier to review after applying. Otherwise, it's
a little non-obvious what has changed. The removed code in the last
hunk was moved, line-wrapped, and slightly modified too.
src/mesa/vbo/vbo_exec_array.c | 82 +++
1 file changed, 59 insertions(+), 23 deletions(-)
diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
index 75831fa..bd05cd0 100644
--- a/src/mesa/vbo/vbo_exec_array.c
+++ b/src/mesa/vbo/vbo_exec_array.c
@@ -442,41 +442,77 @@ recalculate_input_bindings(struct gl_context *ctx)
break;
case VP_ARB:
- /* GL_ARB_vertex_program or GLSL vertex shader - Only the generic[0]
+ /* There are no shaders in OpenGL ES 1.x, so this code path should be
+ * impossible to reach. The meta code is careful to not use shaders in
+ * ES1.
+ */
+ assert(ctx-API != API_OPENGLES);
+
+ /* In the compatibility profile of desktop OpenGL, the generic[0]
* attribute array aliases and overrides the legacy position array.
- *
* Otherwise, legacy attributes available in the legacy slots,
* generic attributes in the generic slots and materials are not
* available as per-vertex attributes.
+ *
+ * In all other APIs, only the generic attributes exist, and none of the
+ * slots are considered magic.
*/
- if (vertexAttrib[VERT_ATTRIB_GENERIC0].Enabled)
-inputs[0] = vertexAttrib[VERT_ATTRIB_GENERIC0];
- else if (vertexAttrib[VERT_ATTRIB_POS].Enabled)
-inputs[0] = vertexAttrib[VERT_ATTRIB_POS];
- else {
-inputs[0] = vbo-currval[VBO_ATTRIB_POS];
- const_inputs |= VERT_BIT_POS;
- }
+ if (ctx-API == API_OPENGL_COMPAT) {
+ if (vertexAttrib[VERT_ATTRIB_GENERIC0].Enabled)
+inputs[0] = vertexAttrib[VERT_ATTRIB_GENERIC0];
+ else if (vertexAttrib[VERT_ATTRIB_POS].Enabled)
+inputs[0] = vertexAttrib[VERT_ATTRIB_POS];
+ else {
+inputs[0] = vbo-currval[VBO_ATTRIB_POS];
+const_inputs |= VERT_BIT_POS;
+ }
- for (i = 1; i VERT_ATTRIB_FF_MAX; i++) {
-if (vertexAttrib[VERT_ATTRIB_FF(i)].Enabled)
- inputs[i] = vertexAttrib[VERT_ATTRIB_FF(i)];
-else {
- inputs[i] = vbo-currval[VBO_ATTRIB_POS+i];
+ for (i = 1; i VERT_ATTRIB_FF_MAX; i++) {
+if (vertexAttrib[VERT_ATTRIB_FF(i)].Enabled)
+ inputs[i] = vertexAttrib[VERT_ATTRIB_FF(i)];
+else {
+ inputs[i] = vbo-currval[VBO_ATTRIB_POS+i];
+ const_inputs |= VERT_BIT_FF(i);
+}
+ }
+
+ for (i = 1; i VERT_ATTRIB_GENERIC_MAX; i++) {
+if (vertexAttrib[VERT_ATTRIB_GENERIC(i)].Enabled)
+ inputs[VERT_ATTRIB_GENERIC(i)] =
+ vertexAttrib[VERT_ATTRIB_GENERIC(i)];
+else {
+ inputs[VERT_ATTRIB_GENERIC(i)] =
+ vbo-currval[VBO_ATTRIB_GENERIC0+i];
+ const_inputs |= VERT_BIT_GENERIC(i);
+}
+ }
+
+ inputs[VERT_ATTRIB_GENERIC0] = inputs[0];
+ } else {
+ /* Other parts of the code assume that inputs[0] through
+ * inputs[VERT_ATTRIB_FF_MAX] will be non-NULL. However, in OpenGL
+ * ES 2.0+ or OpenGL core profile, none of these arrays should ever
+ * be enabled.
+ */
+ for (i = 0; i VERT_ATTRIB_FF_MAX; i++) {
+assert(!vertexAttrib[VERT_ATTRIB_FF(i)].Enabled);
+
+inputs[i] = vbo-currval[VBO_ATTRIB_POS+i];
const_inputs |= VERT_BIT_FF(i);
}
- }
- for (i = 1; i VERT_ATTRIB_GENERIC_MAX; i++) {
-if (vertexAttrib[VERT_ATTRIB_GENERIC(i)].Enabled)
- inputs[VERT_ATTRIB_GENERIC(i)] =
vertexAttrib[VERT_ATTRIB_GENERIC(i)];
-else {
- inputs[VERT_ATTRIB_GENERIC(i)] =
vbo-currval[VBO_ATTRIB_GENERIC0+i];
-const_inputs |= VERT_BIT_GENERIC(i);
+ for (i = 0; i VERT_ATTRIB_GENERIC_MAX; i++) {
+if (vertexAttrib[VERT_ATTRIB_GENERIC(i)].Enabled)
+ inputs[VERT_ATTRIB_GENERIC(i)] =
+
[Mesa-dev] [Bug 55503] Constant vertex attributes broken
https://bugs.freedesktop.org/show_bug.cgi?id=55503 --- Comment #4 from Ian Romanick i...@freedesktop.org --- I have posted a somewhat different patch to the mesa-dev mailing list for review: http://lists.freedesktop.org/archives/mesa-dev/2013-August/042881.html -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 55503] Constant vertex attributes broken
https://bugs.freedesktop.org/show_bug.cgi?id=55503 Ian Romanick i...@freedesktop.org changed: What|Removed |Added Blocks||67224 -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] main: Fix deprecation of glLineWidth()
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
I believe we have someone writing a piglit test for this?
On 08/07/2013 10:28 AM, Paul Berry wrote:
From section E.1 (Profiles and Deprecated Features of OpenGL 3.0)
of the OpenGL 3.0 spec:
LineWidth is not deprecated, but values greater than 1.0
will generate an INVALID VALUE error
From context it is clear that values greater than 1.0 should only
generate an INVALID VALUE error in a forward-compatible context.
The code was correctly quoting this spec text, but it was disallowing
all line widths in forward-compatible contexts, instead of just widths
greater than 1.0.
This patch introduces the correct check, so that setting a line width
of 1.0 or less is permitted.
---
src/mesa/main/lines.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/lines.c b/src/mesa/main/lines.c
index 0df9d66..3c08ed2 100644
--- a/src/mesa/main/lines.c
+++ b/src/mesa/main/lines.c
@@ -56,19 +56,20 @@ _mesa_LineWidth( GLfloat width )
* Wide lines and line stipple - LineWidth is not deprecated, but
* values greater than 1.0 will generate an INVALID_VALUE error;
*
* This is one of the very few cases where functionality was deprecated but
* *NOT* removed in a later spec. Therefore, we only disallow this in a
* forward compatible context.
*/
if (ctx-API == API_OPENGL_CORE
((ctx-Const.ContextFlags GL_CONTEXT_FLAG_FORWARD_COMPATIBLE_BIT)
- != 0)) {
+ != 0)
+width 1.0) {
_mesa_error( ctx, GL_INVALID_VALUE, glLineWidth );
return;
}
if (ctx-Line.Width == width)
return;
FLUSH_VERTICES(ctx, _NEW_LINE);
ctx-Line.Width = width;
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[Mesa-dev] [PATCH] mesa: Specify a better GL_MAX_SERVER_WAIT_TIMEOUT limit.
The previous value of (GLuint64) ~0 has some problems: GL_MAX_SERVER_WAIT_TIMEOUT is supposed to be a GLuint64 value, but has to be queried via GetInteger64v(), which returns a GLint64. This means that some applications are likely to treat it as a signed integer, where ~0 means -1. Negative values are nonsensical and problematic. When interpreted correctly, ~0 translates to about 0.58 million years, which seems rather excessive. This patch changes it to 0x1fff7fff, which is about 1.11 years. This is still plenty long, and is the same as both an int64 and uint64. Applications that accidentally store it in a 32-bit int/unsigned also get a non-zero value, which is again the same as both int and unsigned. Cc: Ian Romanick i...@freedesktop.org Cc: Nicholas Mack nichm...@gmail.com Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/main/context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index d687fb7..582b3d4 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -622,7 +622,7 @@ _mesa_init_constants(struct gl_context *ctx) ctx-Const.MaxSamples = 0; /* GL_ARB_sync */ - ctx-Const.MaxServerWaitTimeout = (GLuint64) ~0; + ctx-Const.MaxServerWaitTimeout = 0x1fff7fff; /* GL_ATI_envmap_bumpmap */ ctx-Const.SupportedBumpUnits = SUPPORTED_ATI_BUMP_UNITS; -- 1.8.3.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallivm: honor d3d10 floating point rules for shadow comparisons
- Original Message - From: Roland Scheidegger srol...@vmware.com d3d10 specifies ordered comparisons for everything but not_equal which is unordered (http://msdn.microsoft.com/en-us/library/windows/desktop/cc308050.aspx). OpenGL probably doesn't care. This series looks good too. For all three: Reviewed-by: Zack Rusin za...@vmware.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] main: Fix deprecation of glLineWidth()
On 7 August 2013 12:34, Ian Romanick i...@freedesktop.org wrote:
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
I believe we have someone writing a piglit test for this?
Yes, I believe Nick is writing a test for it.
On 08/07/2013 10:28 AM, Paul Berry wrote:
From section E.1 (Profiles and Deprecated Features of OpenGL 3.0)
of the OpenGL 3.0 spec:
LineWidth is not deprecated, but values greater than 1.0
will generate an INVALID VALUE error
From context it is clear that values greater than 1.0 should only
generate an INVALID VALUE error in a forward-compatible context.
The code was correctly quoting this spec text, but it was disallowing
all line widths in forward-compatible contexts, instead of just widths
greater than 1.0.
This patch introduces the correct check, so that setting a line width
of 1.0 or less is permitted.
---
src/mesa/main/lines.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/lines.c b/src/mesa/main/lines.c
index 0df9d66..3c08ed2 100644
--- a/src/mesa/main/lines.c
+++ b/src/mesa/main/lines.c
@@ -56,19 +56,20 @@ _mesa_LineWidth( GLfloat width )
* Wide lines and line stipple - LineWidth is not deprecated,
but
* values greater than 1.0 will generate an INVALID_VALUE error;
*
* This is one of the very few cases where functionality was
deprecated but
* *NOT* removed in a later spec. Therefore, we only disallow this
in a
* forward compatible context.
*/
if (ctx-API == API_OPENGL_CORE
((ctx-Const.ContextFlags GL_CONTEXT_FLAG_FORWARD_**
COMPATIBLE_BIT)
- != 0)) {
+ != 0)
+width 1.0) {
_mesa_error( ctx, GL_INVALID_VALUE, glLineWidth );
return;
}
if (ctx-Line.Width == width)
return;
FLUSH_VERTICES(ctx, _NEW_LINE);
ctx-Line.Width = width;
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Re: [Mesa-dev] [PATCH mesa 3/3] egl: Update to Wayland 1.2 server API
On 08/07/2013 10:39 AM, Kristian Høgsberg wrote:
On Thu, Jul 18, 2013 at 03:11:25PM +0300, Ander Conselvan de Oliveira wrote:
Since Wayland 1.2, struct wl_buffer and a few functions are deprecated.
References to wl_buffer are replaced with wl_resource and some getter
functions and calls to deprecated functions are replaced with the proper
new API. The latter changes are related to resource versioning.
Signed-off-by: Ander Conselvan de Oliveira
ander.conselvan.de.olive...@intel.com
Thanks Ander, this and the two previous patches pushed.
If any patches need to be picked back to the 9.2 branch (or 9.1 branch),
please send them to mesa-stable. I don't follow the Wayland work very
closely, so I defer to Kristian's guidance.
Kristian
---
docs/specs/WL_bind_wayland_display.spec| 8 ++-
include/EGL/eglmesaext.h | 6 +-
src/egl/drivers/dri2/egl_dri2.c| 28 +
src/egl/drivers/dri2/egl_dri2.h| 1 -
src/egl/main/eglapi.c | 2 +-
src/egl/main/eglapi.h | 2 +-
src/egl/wayland/wayland-drm/wayland-drm.c | 66 +-
src/egl/wayland/wayland-drm/wayland-drm.h | 13 +++--
.../state_trackers/egl/common/egl_g3d_api.c| 2 +-
.../state_trackers/egl/common/egl_g3d_image.c | 4 +-
.../egl/common/native_wayland_bufmgr.h | 6 +-
.../egl/common/native_wayland_drm_bufmgr.c | 25 +---
src/gbm/backends/dri/gbm_dri.c | 5 +-
13 files changed, 99 insertions(+), 69 deletions(-)
diff --git a/docs/specs/WL_bind_wayland_display.spec
b/docs/specs/WL_bind_wayland_display.spec
index 02bd6ea..8f0083c 100644
--- a/docs/specs/WL_bind_wayland_display.spec
+++ b/docs/specs/WL_bind_wayland_display.spec
@@ -17,7 +17,7 @@ Status
Version
-Version 1, March 1, 2011
+Version 5, July 16, 2013
Number
@@ -57,7 +57,7 @@ New Procedures and Functions
struct wl_display *display);
EGLBoolean eglQueryWaylandBufferWL(EGLDisplay dpy,
- struct wl_buffer *buffer,
+ struct wl_resource *buffer,
EGLint attribute, EGLint *value);
New Tokens
@@ -173,3 +173,7 @@ Revision History
Use EGL_TEXTURE_FORMAT, EGL_TEXTURE_RGB, and EGL_TEXTURE_RGBA,
and just define the new YUV texture formats. Add support for
EGL_WIDTH and EGL_HEIGHT in the query attributes (Kristian Høgsberg)
+Version 5, July 16, 2013
+Change eglQueryWaylandBufferWL to take a resource pointer to the
+buffer instead of a pointer to a struct wl_buffer, as the latter has
+been deprecated. (Ander Conselvan de Oliveira)
diff --git a/include/EGL/eglmesaext.h b/include/EGL/eglmesaext.h
index d476d18..e0eae28 100644
--- a/include/EGL/eglmesaext.h
+++ b/include/EGL/eglmesaext.h
@@ -120,15 +120,15 @@ typedef EGLDisplay (EGLAPIENTRYP PFNEGLGETDRMDISPLAYMESA)
(int fd);
#define EGL_TEXTURE_Y_XUXV_WL 0x31D9
struct wl_display;
-struct wl_buffer;
+struct wl_resource;
#ifdef EGL_EGLEXT_PROTOTYPES
EGLAPI EGLBoolean EGLAPIENTRY eglBindWaylandDisplayWL(EGLDisplay dpy, struct
wl_display *display);
EGLAPI EGLBoolean EGLAPIENTRY eglUnbindWaylandDisplayWL(EGLDisplay dpy,
struct wl_display *display);
-EGLAPI EGLBoolean EGLAPIENTRY eglQueryWaylandBufferWL(EGLDisplay dpy, struct
wl_buffer *buffer, EGLint attribute, EGLint *value);
+EGLAPI EGLBoolean EGLAPIENTRY eglQueryWaylandBufferWL(EGLDisplay dpy, struct
wl_resource *buffer, EGLint attribute, EGLint *value);
#endif
typedef EGLBoolean (EGLAPIENTRYP PFNEGLBINDWAYLANDDISPLAYWL) (EGLDisplay dpy,
struct wl_display *display);
typedef EGLBoolean (EGLAPIENTRYP PFNEGLUNBINDWAYLANDDISPLAYWL) (EGLDisplay
dpy, struct wl_display *display);
-typedef EGLBoolean (EGLAPIENTRYP PFNEGLQUERYWAYLANDBUFFERWL) (EGLDisplay dpy,
struct wl_buffer *buffer, EGLint attribute, EGLint *value);
+typedef EGLBoolean (EGLAPIENTRYP PFNEGLQUERYWAYLANDBUFFERWL) (EGLDisplay dpy,
struct wl_resource *buffer, EGLint attribute, EGLint *value);
#endif
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 1bce314..44fd8a8 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -41,6 +41,10 @@
#include egl_dri2.h
+#ifdef HAVE_WAYLAND_PLATFORM
+#include wayland-drm.h
+#endif
+
const __DRIuseInvalidateExtension use_invalidate = {
{ __DRI_USE_INVALIDATE, 1 }
};
@@ -1195,7 +1199,7 @@ dri2_create_image_wayland_wl_buffer(_EGLDisplay *disp,
_EGLContext *ctx,
EGLClientBuffer _buffer,
const EGLint *attr_list)
{
- struct wl_drm_buffer *buffer = (struct wl_drm_buffer *) _buffer;
+ struct wl_drm_buffer *buffer;
struct dri2_egl_display
Re: [Mesa-dev] Questions about arrays in GLSL 1.50 interface blocks
On 08/06/2013 01:34 PM, Matt Turner wrote: On Tue, Aug 6, 2013 at 12:11 PM, Paul Berry stereotype...@gmail.com wrote: Based on what we've seen with AMD and nVidia so far, it seems like the intended behaviour is probably: redeclarations of interface blocks are prohibited, with the exception of gl_PerVertex (which may only be redeclared once in a given compilation unit). Which means disallowing user-defined unsized arrays in interface blocks (other than gl_PerVertex)? Seems fine, just confirming. There's a specific example in the spec that shows unsized arrays in a uniform block that says implicitly sized in a comment. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] R300 'make check' build failure on master and 9.2
On 08/07/2013 01:33 PM, Ian Romanick wrote: On 08/07/2013 08:43 AM, Tom Stellard wrote: On Tue, Aug 06, 2013 at 10:12:19AM -0700, Ian Romanick wrote: We should set a goal for the 9.3 release: all drivers should just build and 'make check' without having to add a bunch of magic incantations to the configure line. We also need a build bot that will build and 'make check' every commit. Ugh. :( +1 for the buildbot I'm having trouble reproducing this, what configure flags are you using? I've attached my full build log. I don't see anything weird on my configure line. Thoughts? Okay... that was too big. Here's just the configure part. cleaning 64 ./autogen.sh --prefix=/opt/xorg-master-x86_64 --libdir=/opt/xorg-master-x86_64/lib64 --disable-glw --disable-glut --disable-glu --disable-xvmc --disable-vdpau --enable-xcb --enable-dri --enable-glx --enable-egl --with-dri-drivers=i965,i915,swrast --enable-64-bit --enable-debug --with-gallium-drivers --enable-gallium-llvm --with-llvm-shared-libs --disable-gallium-g3dvl --enable-glx-tls --enable-texture-float --enable-shared-glapi --enable-gles1 --enable-gles2 libtoolize: putting auxiliary files in AC_CONFIG_AUX_DIR, `bin'. libtoolize: copying file `bin/ltmain.sh' libtoolize: putting macros in AC_CONFIG_MACRO_DIR, `m4'. libtoolize: copying file `m4/libtool.m4' libtoolize: copying file `m4/ltoptions.m4' libtoolize: copying file `m4/ltsugar.m4' libtoolize: copying file `m4/ltversion.m4' libtoolize: copying file `m4/lt~obsolete.m4' checking build system type... x86_64-unknown-linux-gnu checking host system type... x86_64-unknown-linux-gnu checking target system type... x86_64-unknown-linux-gnu checking for a BSD-compatible install... /usr/bin/install -c checking whether build environment is sane... yes checking for a thread-safe mkdir -p... /usr/bin/mkdir -p checking for gawk... gawk checking whether make sets $(MAKE)... yes checking whether make supports nested variables... yes checking for style of include used by make... GNU checking for gcc... gcc checking whether the C compiler works... yes checking for C compiler default output file name... a.out checking for suffix of executables... checking whether we are cross compiling... no checking for suffix of object files... o checking whether we are using the GNU C compiler... yes checking whether gcc accepts -g... yes checking for gcc option to accept ISO C89... none needed checking dependency style of gcc... gcc3 checking for ar... ar checking the archiver (ar) interface... ar checking how to run the C preprocessor... gcc -E checking for gcc... (cached) gcc checking whether we are using the GNU C compiler... (cached) yes checking whether gcc accepts -g... (cached) yes checking for gcc option to accept ISO C89... (cached) none needed checking dependency style of gcc... (cached) gcc3 checking for gcc... gcc checking whether we are using the GNU C compiler... (cached) yes checking whether gcc accepts -g... yes checking for gcc option to accept ISO C89... (cached) none needed checking dependency style of gcc... (cached) gcc3 checking how to run the C preprocessor... gcc -E checking for g++... g++ checking whether we are using the GNU C++ compiler... yes checking whether g++ accepts -g... yes checking dependency style of g++... gcc3 checking how to run the C++ preprocessor... g++ -E checking for g++... g++ checking whether we are using the GNU C++ compiler... (cached) yes checking whether g++ accepts -g... yes checking dependency style of g++... (cached) gcc3 checking how to run the C++ preprocessor... g++ -E checking whether gcc and cc understand -c and -o together... yes checking dependency style of gcc... gcc3 checking for gmake... gmake checking for python2... python2 checking python2 module: libxml2... yes checking for a sed that does not truncate output... /usr/bin/sed checking how to print strings... printf checking for a sed that does not truncate output... (cached) /usr/bin/sed checking for grep that handles long lines and -e... /usr/bin/grep checking for egrep... /usr/bin/grep -E checking for fgrep... /usr/bin/grep -F checking for ld used by gcc... /usr/bin/ld checking if the linker (/usr/bin/ld) is GNU ld... yes checking for BSD- or MS-compatible name lister (nm)... /usr/bin/nm -B checking the name lister (/usr/bin/nm -B) interface... BSD nm checking whether ln -s works... yes checking the maximum length of command line arguments... 1572864 checking whether the shell understands some XSI constructs... yes checking whether the shell understands +=... yes checking how to convert x86_64-unknown-linux-gnu file names to x86_64-unknown-linux-gnu format... func_convert_file_noop checking how to convert x86_64-unknown-linux-gnu file names to toolchain format... func_convert_file_noop checking for /usr/bin/ld option to reload object files... -r checking for objdump... objdump checking how to recognize dependent libraries... pass_all checking for dlltool... no checking how to associate runtime and
Re: [Mesa-dev] [PATCH 4/6] i965/fs: Optimize IF/MOV/ELSE/MOV/ENDIF to SEL when possible.
On 08/06/2013 02:17 PM, Kenneth Graunke wrote: On 08/06/2013 04:14 AM, Christoph Bumiller wrote: On 06.08.2013 03:28, Kenneth Graunke wrote: Many GLSL shaders contain code of the form: x = condition ? foo : bar The compiler emits an ir_if tree for this, since each subexpression might be a complex tree that could have side-effects and short-circuit logic operations. However, the common case is to simply pick one of two constants or variable's values---which is exactly what SEL is for. Replacing IF/ELSE with SEL also simplifies the control flow graph, making optimization passes which work on basic blocks more effective. Don't you think something like that should be implemented in common code so that all drivers can profit ? It would be really nice to have more, useful device-independent optimizations or simplifications like this already done instead of requiring each driver to re-implement them (or use llvm). I agree - I'd love to have more optimizations in the common code. But it's rather awkward to implement them now due to our tree-like IR. For example, if I created an ir_triop_sel expression, it would take three ir_rvalues as operands. If I let those be arbitrary expresion trees, then ir_triop_sel couldn't map to SEL in basically any hardware, and so backends would need to codegen them as if-ladders. Awkward. Or, if I forced ir_triop_sel to only take constants and...dereferences of variables?...it might map to hardware SEL, but it wouldn't match any of the rest of the IR, so enforcing those restrictions would probably be awkward. I've thought a bit about this. I believe this could / should be handled in a couple ways... as should some of the constraints that we already have. 1. Formalize the notion of IR levels or languages. We started with this as the plan (having HIR and MIR), but, in our rush, quickly deviated from that plan. A big part of this is just documenting the concept and documenting which ir_instruction subclasses can occur in which languages. 2. Augment ir_validate to validate the constraints of different languages. If we have multiple languages that share the same data types but differing restrictions (e.g., in a low-level IR operands can only be ir_constant or ir_dereference), the validator should enforce that. 3. Implement specific passes to translate from one language to another. Use the validator at both ends to enforce the constraints. Create a large number of unit tests to exercise the conversions. The tree IR is actually pretty cumbersome to work with. I was going to implement CSE in the main GLSL compiler, but realized there's no sensible way to even compare two IR expression trees right now. My code started diverging pretty significantly from the algorithm in the textbook, and that seemed bad. My hope is to eventually create a 3-src style IR for the compiler which is SSA and doesn't have trees. SSA would mean use/def and liveness is trivial, and with use/def and 3-src, most compiler optimization passes should translate pretty easily. The idea would be to treat the current GLSL IR as HIR (a high level IR), and generate the new low-level IR (LIR). Then, we'd generate i965 assembly from LIR, and probably TGSI as well. If we start with a reasonable picture of where we'd like to end, I think we can do a lot of this incrementally. Borrowing from my steps above, we could write a tree flattening pass that would convert the existing IR to a flat IR using the same data types. But that's mostly in the wouldn't it be great file for now...in the meantime, it's just a lot easier to write optimizations in the backend. --Ken ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/6] i965/fs: Optimize IF/MOV/ELSE/MOV/ENDIF to SEL when possible.
On 08/05/2013 06:28 PM, Kenneth Graunke wrote:
Many GLSL shaders contain code of the form:
x = condition ? foo : bar
The compiler emits an ir_if tree for this, since each subexpression
might be a complex tree that could have side-effects and short-circuit
logic operations.
However, the common case is to simply pick one of two constants or
variable's values---which is exactly what SEL is for. Replacing IF/ELSE
with SEL also simplifies the control flow graph, making optimization
passes which work on basic blocks more effective.
The shader-db statistics:
total instructions in shared programs: 1655247 - 1503234 (-9.18%)
instructions in affected programs: 949188 - 797175 (-16.02%)
2,970 shaders were helped, none hurt. Gained 181 SIMD16 programs.
This helps Valve's Source Engine games (max -41.33%), The Cave
(max -33.33%), Serious Sam 3 (max -18.64%), Yo Frankie! (max -30.19%),
Zen Bound (max -22.22%), GStreamer (max -6.12%), and GLBenchmark 2.7
(max -1.94%).
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 78
2 files changed, 79 insertions(+)
The pattern matching stuff here might be useful to abstract for reuse in
other peephole type optimizations; ensuring that the right opcodes exist
without accidentally walking the list is tricky to get right.
Then again, I'm not sure how many useful peephole optimizations we'll have;
it may be more useful in many cases to walk a UD-chain rather than looking
at consecutive instructions.
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 370ab6c..7feb2b6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -369,6 +369,7 @@ public:
fs_reg src0, fs_reg src1);
bool try_emit_saturate(ir_expression *ir);
bool try_emit_mad(ir_expression *ir, int mul_arg);
+ void try_replace_with_sel();
void emit_bool_to_cond_code(ir_rvalue *condition);
void emit_if_gen6(ir_if *ir);
void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index ee7728c..a36c248 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1842,6 +1842,82 @@ fs_visitor::emit_if_gen6(ir_if *ir)
inst-predicate = BRW_PREDICATE_NORMAL;
}
+/**
+ * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
+ *
+ * Many GLSL shaders contain the following pattern:
+ *
+ *x = condition ? foo : bar
+ *
+ * The compiler emits an ir_if tree for this, since each subexpression might be
+ * a complex tree that could have side-effects or short-circuit logic.
+ *
+ * However, the common case is to simply select one of two constants or
+ * variable values---which is exactly what SEL is for. In this case, the
+ * assembly looks like:
+ *
+ *(+f0) IF
+ *MOV dst src0
+ *ELSE
+ *MOV dst src1
+ *ENDIF
Do we see many cases of
foo = batman;
if (condition)
foo = robin;
+ *
+ * which can be easily translated into:
+ *
+ *(+f0) SEL dst src0 src1
+ *
+ * If src0 is an immediate value, we promote it to a temporary GRF.
+ */
+void
+fs_visitor::try_replace_with_sel()
+{
+ fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
+ assert(endif_inst-opcode == BRW_OPCODE_ENDIF);
+
+ /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
Just curious about the decision to match in reverse...
+ int opcodes[] = {
+ BRW_OPCODE_IF, BRW_OPCODE_MOV, BRW_OPCODE_ELSE, BRW_OPCODE_MOV,
+ };
+
+ fs_inst *match = (fs_inst *) endif_inst-prev;
+ for (int i = 0; i 4; i++) {
+ if (match-is_head_sentinel() || match-opcode != opcodes[4-i-1])
+ return;
+ match = (fs_inst *) match-prev;
+ }
+
+ /* The opcodes match; it looks like the right sequence of instructions. */
+ fs_inst *else_mov = (fs_inst *) endif_inst-prev;
+ fs_inst *then_mov = (fs_inst *) else_mov-prev-prev;
+ fs_inst *if_inst = (fs_inst *) then_mov-prev;
+
+ /* Check that the MOVs are the right form. */
+ if (then_mov-dst.equals(else_mov-dst)
+ !then_mov-is_partial_write()
+ !else_mov-is_partial_write()) {
+
+ /* Remove the matched instructions; we'll emit a SEL to replace them. */
+ while (!if_inst-next-is_tail_sentinel())
+ if_inst-next-remove();
+ if_inst-remove();
+
+ /* Only the last source register can be a constant, so if the MOV in
+ * the then clause uses a constant, we need to put it in a temporary.
+ */
+ fs_reg src0(then_mov-src[0]);
+ if (src0.file == IMM) {
+ src0 = fs_reg(this, glsl_type::float_type);
+ src0.type = then_mov-src[0].type;
+ emit(MOV(src0, then_mov-src[0]));
+ }
+
+ fs_inst *sel = emit(BRW_OPCODE_SEL,
Re: [Mesa-dev] [PATCH] mesa: Specify a better GL_MAX_SERVER_WAIT_TIMEOUT limit.
On 08/07/2013 12:56 PM, Kenneth Graunke wrote: The previous value of (GLuint64) ~0 has some problems: GL_MAX_SERVER_WAIT_TIMEOUT is supposed to be a GLuint64 value, but has to be queried via GetInteger64v(), which returns a GLint64. This means that some applications are likely to treat it as a signed integer, where ~0 means -1. Negative values are nonsensical and problematic. When interpreted correctly, ~0 translates to about 0.58 million years, which seems rather excessive. This patch changes it to 0x1fff7fff, which is about 1.11 years. This is still plenty long, and is the same as both an int64 and uint64. Applications that accidentally store it in a 32-bit int/unsigned also get a non-zero value, which is again the same as both int and unsigned. and non-negative Cc: Ian Romanick i...@freedesktop.org Cc: Nicholas Mack nichm...@gmail.com Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/main/context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index d687fb7..582b3d4 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -622,7 +622,7 @@ _mesa_init_constants(struct gl_context *ctx) ctx-Const.MaxSamples = 0; /* GL_ARB_sync */ - ctx-Const.MaxServerWaitTimeout = (GLuint64) ~0; + ctx-Const.MaxServerWaitTimeout = 0x1fff7fff; Does this need any ULL decoration on the end to make other compilers happy? /* GL_ATI_envmap_bumpmap */ ctx-Const.SupportedBumpUnits = SUPPORTED_ATI_BUMP_UNITS; ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] R600/SI: Implement sint-fp64 conversions
On Wed, Aug 07, 2013 at 05:53:36PM +0200, Niels Ole Salscheider wrote:
---
lib/Target/R600/SIInstrInfo.td| 6 ++
lib/Target/R600/SIInstructions.td | 8 ++--
test/CodeGen/R600/fp64_to_sint.ll | 9 +
test/CodeGen/R600/sint_to_fp64.ll | 9 +
Both patches are:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Please request commit access from Chris, so you can commit these:
http://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access
Here are instructions for setting up git-svn:
http://llvm.org/docs/GettingStarted.html#for-developers-to-work-with-git-svn
-Tom
4 Dateien geändert, 30 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)
create mode 100644 test/CodeGen/R600/fp64_to_sint.ll
create mode 100644 test/CodeGen/R600/sint_to_fp64.ll
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 52af79c..302fa24 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -184,6 +184,12 @@ multiclass VOP1_32 bits8 op, string opName, listdag
pattern
multiclass VOP1_64 bits8 op, string opName, listdag pattern
: VOP1_Helper op, VReg_64, VSrc_64, opName, pattern;
+multiclass VOP1_32_64 bits8 op, string opName, listdag pattern
+ : VOP1_Helper op, VReg_32, VSrc_64, opName, pattern;
+
+multiclass VOP1_64_32 bits8 op, string opName, listdag pattern
+ : VOP1_Helper op, VReg_64, VSrc_32, opName, pattern;
+
multiclass VOP2_Helper bits6 op, RegisterClass vrc, RegisterClass arc,
string opName, listdag pattern, string revOp {
def _e32 : VOP2
diff --git a/lib/Target/R600/SIInstructions.td
b/lib/Target/R600/SIInstructions.td
index 500d15e..efe7a3e 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -603,8 +603,12 @@ defm V_MOV_B32 : VOP1_32 0x0001, V_MOV_B32, [];
} // End neverHasSideEffects = 1, isMoveImm = 1
defm V_READFIRSTLANE_B32 : VOP1_32 0x0002, V_READFIRSTLANE_B32, [];
-//defm V_CVT_I32_F64 : VOP1_32 0x0003, V_CVT_I32_F64, [];
-//defm V_CVT_F64_I32 : VOP1_64 0x0004, V_CVT_F64_I32, [];
+defm V_CVT_I32_F64 : VOP1_32_64 0x0003, V_CVT_I32_F64,
+ [(set i32:$dst, (fp_to_sint f64:$src0))]
+;
+defm V_CVT_F64_I32 : VOP1_64_32 0x0004, V_CVT_F64_I32,
+ [(set f64:$dst, (sint_to_fp i32:$src0))]
+;
defm V_CVT_F32_I32 : VOP1_32 0x0005, V_CVT_F32_I32,
[(set f32:$dst, (sint_to_fp i32:$src0))]
;
diff --git a/test/CodeGen/R600/fp64_to_sint.ll
b/test/CodeGen/R600/fp64_to_sint.ll
new file mode 100644
index 000..42f9f34
--- /dev/null
+++ b/test/CodeGen/R600/fp64_to_sint.ll
@@ -0,0 +1,9 @@
+; RUN: llc %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK
+
+; CHECK: @fp64_to_sint
+; CHECK: V_CVT_I32_F64_e32
+define void @fp64_to_sint(i32 addrspace(1)* %out, double %in) {
+ %result = fptosi double %in to i32
+ store i32 %result, i32 addrspace(1)* %out
+ ret void
+}
diff --git a/test/CodeGen/R600/sint_to_fp64.ll
b/test/CodeGen/R600/sint_to_fp64.ll
new file mode 100644
index 000..37f67c9
--- /dev/null
+++ b/test/CodeGen/R600/sint_to_fp64.ll
@@ -0,0 +1,9 @@
+; RUN: llc %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK
+
+; CHECK: @sint_to_fp64
+; CHECK: V_CVT_F64_I32_e32
+define void @sint_to_fp64(double addrspace(1)* %out, i32 %in) {
+ %result = sitofp i32 %in to double
+ store double %result, double addrspace(1)* %out
+ ret void
+}
--
1.7.11.7
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[Mesa-dev] [PATCH 01/20] tgsi: fix the location of sample index
The sample index is always in W. --- src/gallium/auxiliary/tgsi/tgsi_util.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c b/src/gallium/auxiliary/tgsi/tgsi_util.c index 98c1e6e..fed5f76 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_util.c +++ b/src/gallium/auxiliary/tgsi/tgsi_util.c @@ -418,9 +418,11 @@ tgsi_util_get_texture_coord_dim(int tgsi_tex, int *shadow_or_sample) case TGSI_TEXTURE_SHADOW1D_ARRAY: case TGSI_TEXTURE_SHADOW2D_ARRAY: case TGSI_TEXTURE_SHADOWCUBE_ARRAY: + *shadow_or_sample = dim; + break; case TGSI_TEXTURE_2D_MSAA: case TGSI_TEXTURE_2D_ARRAY_MSAA: - *shadow_or_sample = dim; + *shadow_or_sample = 3; break; default: /* no shadow nor sample */ -- 1.8.1.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 02/20] tgsi: add info about MSAA samplers to tgsi_shader_info
---
src/gallium/auxiliary/tgsi/tgsi_scan.c | 13 +
src/gallium/auxiliary/tgsi/tgsi_scan.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 1294a7a..05b7111 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -36,6 +36,7 @@
#include util/u_debug.h
#include util/u_math.h
+#include util/u_memory.h
#include util/u_prim.h
#include tgsi/tgsi_parse.h
#include tgsi/tgsi_util.h
@@ -128,6 +129,18 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
if (src-Register.Indirect) {
info-indirect_files |= (1 src-Register.File);
}
+
+ /* MSAA samplers */
+ if (src-Register.File == TGSI_FILE_SAMPLER) {
+ assert(fullinst-Instruction.Texture);
+ assert(src-Register.Index
Elements(info-is_msaa_sampler));
+
+ if (fullinst-Instruction.Texture
+ (fullinst-Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
+ fullinst-Texture.Texture ==
TGSI_TEXTURE_2D_ARRAY_MSAA)) {
+ info-is_msaa_sampler[src-Register.Index] = TRUE;
+ }
+ }
}
/* check for indirect register writes */
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.h
b/src/gallium/auxiliary/tgsi/tgsi_scan.h
index e2fa73a..d9147bd 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.h
@@ -80,6 +80,7 @@ struct tgsi_shader_info
boolean color0_writes_all_cbufs;
boolean writes_viewport_index;
boolean writes_layer;
+ boolean is_msaa_sampler[PIPE_MAX_SAMPLERS];
unsigned num_written_culldistance;
unsigned num_written_clipdistance;
--
1.8.1.2
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[Mesa-dev] [PATCH 03/20] radeonsi: rename r600_resource_texture to r600_texture
---
src/gallium/drivers/radeonsi/r600_blit.c | 22 +-
src/gallium/drivers/radeonsi/r600_resource.h | 6 ++---
src/gallium/drivers/radeonsi/r600_texture.c | 34 ++--
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 4 ++--
src/gallium/drivers/radeonsi/radeonsi_uvd.c | 12 +-
src/gallium/drivers/radeonsi/si_state.c | 16 ++---
src/gallium/drivers/radeonsi/si_state_draw.c | 2 +-
7 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/r600_blit.c
b/src/gallium/drivers/radeonsi/r600_blit.c
index 34f14ba..421aab3 100644
--- a/src/gallium/drivers/radeonsi/r600_blit.c
+++ b/src/gallium/drivers/radeonsi/r600_blit.c
@@ -101,8 +101,8 @@ static void r600_blitter_end(struct pipe_context *ctx)
}
void si_blit_uncompress_depth(struct pipe_context *ctx,
- struct r600_resource_texture *texture,
- struct r600_resource_texture *staging,
+ struct r600_texture *texture,
+ struct r600_texture *staging,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer)
{
@@ -111,7 +111,7 @@ void si_blit_uncompress_depth(struct pipe_context *ctx,
float depth = 1.0f;
const struct util_format_description *desc;
void *custom_dsa;
- struct r600_resource_texture *flushed_depth_texture = staging ?
+ struct r600_texture *flushed_depth_texture = staging ?
staging : texture-flushed_depth_texture;
if (!staging !texture-dirty_db_mask)
@@ -172,7 +172,7 @@ void si_blit_uncompress_depth(struct pipe_context *ctx,
}
static void si_blit_decompress_depth_in_place(struct r600_context *rctx,
- struct r600_resource_texture
*texture,
+ struct r600_texture *texture,
unsigned first_level, unsigned
last_level,
unsigned first_layer, unsigned
last_layer)
{
@@ -222,12 +222,12 @@ void si_flush_depth_textures(struct r600_context *rctx,
for (i = 0; i textures-n_views; ++i) {
struct pipe_sampler_view *view;
- struct r600_resource_texture *tex;
+ struct r600_texture *tex;
view = textures-views[i]-base;
if (!view) continue;
- tex = (struct r600_resource_texture *)view-texture;
+ tex = (struct r600_texture *)view-texture;
if (!tex-is_depth || tex-is_flushing_texture)
continue;
@@ -294,7 +294,7 @@ static void r600_compressed_to_blittable(struct
pipe_resource *tex,
unsigned level,
struct texture_orig_info *orig)
{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
+ struct r600_texture *rtex = (struct r600_texture*)tex;
unsigned pixsize = util_format_get_blocksize(rtex-real_format);
int new_format;
int new_height, new_width;
@@ -329,7 +329,7 @@ static void r600_change_format(struct pipe_resource *tex,
struct texture_orig_info *orig,
enum pipe_format format)
{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
+ struct r600_texture *rtex = (struct r600_texture*)tex;
orig-format = tex-format;
orig-width0 = tex-width0;
@@ -346,7 +346,7 @@ static void r600_reset_blittable_to_orig(struct
pipe_resource *tex,
unsigned level,
struct texture_orig_info *orig)
{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
+ struct r600_texture *rtex = (struct r600_texture*)tex;
tex-format = orig-format;
tex-width0 = orig-width0;
@@ -366,7 +366,7 @@ static void r600_resource_copy_region(struct pipe_context
*ctx,
const struct pipe_box *src_box)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_resource_texture *rsrc = (struct r600_resource_texture*)src;
+ struct r600_texture *rsrc = (struct r600_texture*)src;
struct texture_orig_info orig_info[2];
struct pipe_box sbox;
const struct pipe_box *psbox = src_box;
@@ -467,7 +467,7 @@ static void si_blit(struct pipe_context *ctx,
const struct pipe_blit_info *info)
{
struct r600_context *rctx = (struct r600_context*)ctx;
- struct r600_resource_texture *rsrc = (struct
r600_resource_texture*)info-src.resource;
+ struct r600_texture *rsrc = (struct r600_texture*)info-src.resource;
assert(util_blitter_is_blit_supported(rctx-blitter, info));
diff --git
[Mesa-dev] [PATCH 04/20] radeonsi: rename r600_texture::dirty_db_mask to dirty_level_mask
---
src/gallium/drivers/radeonsi/r600_blit.c | 10 +-
src/gallium/drivers/radeonsi/r600_resource.h | 2 +-
src/gallium/drivers/radeonsi/r600_texture.c | 2 +-
src/gallium/drivers/radeonsi/si_state_draw.c | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/r600_blit.c
b/src/gallium/drivers/radeonsi/r600_blit.c
index 421aab3..bab108e 100644
--- a/src/gallium/drivers/radeonsi/r600_blit.c
+++ b/src/gallium/drivers/radeonsi/r600_blit.c
@@ -114,7 +114,7 @@ void si_blit_uncompress_depth(struct pipe_context *ctx,
struct r600_texture *flushed_depth_texture = staging ?
staging : texture-flushed_depth_texture;
- if (!staging !texture-dirty_db_mask)
+ if (!staging !texture-dirty_level_mask)
return;
desc =
util_format_description(flushed_depth_texture-resource.b.b.format);
@@ -133,7 +133,7 @@ void si_blit_uncompress_depth(struct pipe_context *ctx,
}
for (level = first_level; level = last_level; level++) {
- if (!staging !(texture-dirty_db_mask (1 level)))
+ if (!staging !(texture-dirty_level_mask (1 level)))
continue;
/* The smaller the mipmap level, the less layers there are
@@ -166,7 +166,7 @@ void si_blit_uncompress_depth(struct pipe_context *ctx,
/* The texture will always be dirty if some layers aren't
flushed.
* I don't think this case can occur though. */
if (!staging first_layer == 0 last_layer == max_layer) {
- texture-dirty_db_mask = ~(1 level);
+ texture-dirty_level_mask = ~(1 level);
}
}
}
@@ -182,7 +182,7 @@ static void si_blit_decompress_depth_in_place(struct
r600_context *rctx,
surf_tmpl.format = texture-resource.b.b.format;
for (level = first_level; level = last_level; level++) {
- if (!(texture-dirty_db_mask (1 level)))
+ if (!(texture-dirty_level_mask (1 level)))
continue;
surf_tmpl.u.tex.level = level;
@@ -210,7 +210,7 @@ static void si_blit_decompress_depth_in_place(struct
r600_context *rctx,
/* The texture will always be dirty if some layers aren't
flushed.
* I don't think this case occurs often though. */
if (first_layer == 0 last_layer == max_layer) {
- texture-dirty_db_mask = ~(1 level);
+ texture-dirty_level_mask = ~(1 level);
}
}
}
diff --git a/src/gallium/drivers/radeonsi/r600_resource.h
b/src/gallium/drivers/radeonsi/r600_resource.h
index 19cc1d9..24db2a9 100644
--- a/src/gallium/drivers/radeonsi/r600_resource.h
+++ b/src/gallium/drivers/radeonsi/r600_resource.h
@@ -49,7 +49,7 @@ struct r600_texture {
unsignedpitch_override;
unsignedis_depth;
- unsigneddirty_db_mask; /* each bit says if that
miplevel is dirty */
+ unsigneddirty_level_mask; /* each bit says if
that miplevel is dirty */
struct r600_texture *flushed_depth_texture;
boolean is_flushing_texture;
struct radeon_surface surface;
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c
b/src/gallium/drivers/radeonsi/r600_texture.c
index 5b9cad1..8b0f6a4 100644
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -658,7 +658,7 @@ bool r600_init_flushed_depth_texture(struct pipe_context
*ctx,
if (staging)
resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
else
- rtex-dirty_db_mask = (1 (resource.last_level+1)) - 1;
+ rtex-dirty_level_mask = (1 (resource.last_level+1)) - 1;
*flushed_depth_texture = (struct r600_texture
*)ctx-screen-resource_create(ctx-screen, resource);
if (*flushed_depth_texture == NULL) {
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 45cfcc4..3363d46 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -726,7 +726,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
struct pipe_surface *surf = rctx-framebuffer.zsbuf;
struct r600_texture *rtex = (struct r600_texture
*)surf-texture;
- rtex-dirty_db_mask |= 1 surf-u.tex.level;
+ rtex-dirty_level_mask |= 1 surf-u.tex.level;
}
pipe_resource_reference(ib.buffer, NULL);
--
1.8.1.2
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[Mesa-dev] [PATCH 05/20] radeonsi: correct sampler function names
---
src/gallium/drivers/radeonsi/si_state.c | 46 -
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index be4db8b..1dd51a8 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2488,11 +2488,11 @@ static void *si_create_sampler_state(struct
pipe_context *ctx,
return rstate;
}
-static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx,
- unsigned count,
- struct pipe_sampler_view
**views,
- struct r600_textures_info
*samplers,
- unsigned user_data_reg)
+static struct si_pm4_state *si_set_sampler_views(struct r600_context *rctx,
+unsigned count,
+struct pipe_sampler_view
**views,
+struct r600_textures_info
*samplers,
+unsigned user_data_reg)
{
struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view
**)views;
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
@@ -2541,32 +2541,32 @@ out:
return pm4;
}
-static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
- struct pipe_sampler_view **views)
+static void si_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
+ struct pipe_sampler_view **views)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4;
- pm4 = si_set_sampler_view(rctx, count, views, rctx-vs_samplers,
+ pm4 = si_set_sampler_views(rctx, count, views, rctx-vs_samplers,
R_00B130_SPI_SHADER_USER_DATA_VS_0);
si_pm4_set_state(rctx, vs_sampler_views, pm4);
}
-static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
- struct pipe_sampler_view **views)
+static void si_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
+ struct pipe_sampler_view **views)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4;
- pm4 = si_set_sampler_view(rctx, count, views, rctx-ps_samplers,
+ pm4 = si_set_sampler_views(rctx, count, views, rctx-ps_samplers,
R_00B030_SPI_SHADER_USER_DATA_PS_0);
si_pm4_set_state(rctx, ps_sampler_views, pm4);
}
-static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx,
unsigned count,
- void **states,
- struct r600_textures_info *samplers,
- unsigned user_data_reg)
+static struct si_pm4_state *si_bind_sampler_states(struct r600_context *rctx,
unsigned count,
+ void **states,
+ struct r600_textures_info
*samplers,
+ unsigned user_data_reg)
{
struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state
**)states;
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
@@ -2637,22 +2637,22 @@ out:
return pm4;
}
-static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void
**states)
+static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned
count, void **states)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4;
- pm4 = si_bind_sampler(rctx, count, states, rctx-vs_samplers,
+ pm4 = si_bind_sampler_states(rctx, count, states, rctx-vs_samplers,
R_00B130_SPI_SHADER_USER_DATA_VS_0);
si_pm4_set_state(rctx, vs_sampler, pm4);
}
-static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void
**states)
+static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned
count, void **states)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4;
- pm4 = si_bind_sampler(rctx, count, states, rctx-ps_samplers,
+ pm4 = si_bind_sampler_states(rctx, count, states, rctx-ps_samplers,
R_00B030_SPI_SHADER_USER_DATA_PS_0);
si_pm4_set_state(rctx, ps_sampler, pm4);
}
@@ -2862,13 +2862,13 @@ void si_init_state_functions(struct r600_context *rctx)
rctx-context.delete_fs_state = si_delete_ps_shader;
rctx-context.create_sampler_state = si_create_sampler_state;
- rctx-context.bind_vertex_sampler_states =
[Mesa-dev] [PATCH 06/20] radeonsi: initialize the radeon_surface structure
this fixes valgrind warnings
---
src/gallium/drivers/radeonsi/r600_texture.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c
b/src/gallium/drivers/radeonsi/r600_texture.c
index 8b0f6a4..62a7518 100644
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -523,7 +523,7 @@ struct pipe_resource *si_texture_create(struct pipe_screen
*screen,
const struct pipe_resource *templ)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
- struct radeon_surface surface;
+ struct radeon_surface surface = {0};
unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
int r;
--
1.8.1.2
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[Mesa-dev] [PATCH 07/20] radeonsi: unduplicate code in create_context
---
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 69b9ca9..3ebed98 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -233,12 +233,6 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
switch (rctx-chip_class) {
case SI:
- si_init_state_functions(rctx);
- LIST_INITHEAD(rctx-active_query_list);
- rctx-cs = rctx-ws-cs_create(rctx-ws, RING_GFX, NULL);
- rctx-max_db = 8;
- si_init_config(rctx);
- break;
case CIK:
si_init_state_functions(rctx);
LIST_INITHEAD(rctx-active_query_list);
--
1.8.1.2
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[Mesa-dev] [PATCH 09/20] radeonsi: implement GL_SAMPLE_ALPHA_TO_ONE
---
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 1 +
src/gallium/drivers/radeonsi/radeonsi_shader.c | 14 ++
src/gallium/drivers/radeonsi/radeonsi_shader.h | 1 +
src/gallium/drivers/radeonsi/si_state.c| 12
src/gallium/drivers/radeonsi/si_state.h| 3 ++-
5 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
index fc02e38..d2e8831 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -146,6 +146,7 @@ struct r600_context {
struct si_vertex_element*vertex_elements;
struct pipe_framebuffer_state framebuffer;
unsignedfb_log_samples;
+ unsignedfb_cb0_is_integer;
unsignedpa_sc_line_stipple;
unsignedpa_su_sc_mode_cntl;
/* for saving when using blitter */
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index fee6262..18dde61 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -561,6 +561,17 @@ static void si_alpha_test(struct lp_build_tgsi_context
*bld_base,
}
}
+static void si_alpha_to_one(struct lp_build_tgsi_context *bld_base,
+ unsigned index)
+{
+ struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
+
+ /* set alpha to one */
+ LLVMBuildStore(bld_base-base.gallivm-builder,
+ bld_base-base.one,
+ si_shader_ctx-radeon_bld.soa.outputs[index][3]);
+}
+
static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
unsigned index)
{
@@ -703,6 +714,9 @@ handle_semantic:
param_count++;
} else {
target = V_008DFC_SQ_EXP_MRT +
color_count;
+ if
(si_shader_ctx-shader-key.ps.alpha_to_one) {
+ si_alpha_to_one(bld_base,
index);
+ }
if (color_count == 0
si_shader_ctx-shader-key.ps.alpha_func != PIPE_FUNC_ALWAYS)
si_alpha_test(bld_base, index);
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h
b/src/gallium/drivers/radeonsi/radeonsi_shader.h
index 60a48f4..051ef1f 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h
@@ -123,6 +123,7 @@ union si_shader_key {
unsignedcolor_two_side:1;
unsignedalpha_func:3;
unsignedflatshade:1;
+ unsignedalpha_to_one:1;
float alpha_ref;
} ps;
struct {
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 4036d07..90c31de 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -255,6 +255,8 @@ static void *si_create_blend_state_mode(struct pipe_context
*ctx,
if (blend == NULL)
return NULL;
+ blend-alpha_to_one = state-alpha_to_one;
+
color_control = S_028808_MODE(mode);
if (state-logicop_enable) {
color_control |= S_028808_ROP3(state-logicop_func |
(state-logicop_func 4));
@@ -520,6 +522,7 @@ static void *si_create_rs_state(struct pipe_context *ctx,
}
rs-two_side = state-light_twoside;
+ rs-multisample_enable = state-multisample;
rs-clip_plane_enable = state-clip_plane_enable;
polygon_dual_mode = (state-fill_front != PIPE_POLYGON_MODE_FILL ||
@@ -2247,6 +2250,8 @@ static void si_set_framebuffer_state(struct pipe_context
*ctx,
si_set_msaa_state(rctx, pm4, nr_samples);
rctx-fb_log_samples = util_logbase2(nr_samples);
+ rctx-fb_cb0_is_integer = state-nr_cbufs
+
util_format_is_pure_integer(state-cbufs[0]-format);
si_pm4_set_state(rctx, framebuffer, pm4);
si_update_fb_rs_state(rctx);
@@ -2277,9 +2282,16 @@ static INLINE void si_shader_selector_key(struct
pipe_context *ctx,
if (sel-fs_write_all)
key-ps.nr_cbufs = rctx-framebuffer.nr_cbufs;
key-ps.export_16bpc = rctx-export_16bpc;
+
if (rctx-queued.named.rasterizer) {
key-ps.color_two_side =
rctx-queued.named.rasterizer-two_side;
key-ps.flatshade =
rctx-queued.named.rasterizer-flatshade;
+
+ if
[Mesa-dev] [PATCH 10/20] radeonsi: disable alpha-to-coverage for integer colorbuffers
---
src/gallium/drivers/radeonsi/radeonsi_shader.h | 1 +
src/gallium/drivers/radeonsi/si_state_draw.c | 9 -
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h
b/src/gallium/drivers/radeonsi/radeonsi_shader.h
index 051ef1f..2ce34b9 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h
@@ -143,6 +143,7 @@ struct si_pipe_shader {
unsignedspi_ps_input_ena;
unsignedspi_shader_col_format;
unsignedcb_shader_mask;
+ boolcb0_is_integer;
unsignedsprite_coord_enable;
unsignedso_strides[4];
union si_shader_key key;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index e200ab1..7b8a522 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -135,7 +135,9 @@ static void si_pipe_shader_ps(struct pipe_context *ctx,
struct si_pipe_shader *s
si_pm4_inval_shader_cache(pm4);
- db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+ db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
+
S_02880C_ALPHA_TO_MASK_DISABLE(rctx-fb_cb0_is_integer);
+
for (i = 0; i shader-shader.ninput; i++) {
switch (shader-shader.input[i].name) {
case TGSI_SEMANTIC_POSITION:
@@ -254,6 +256,7 @@ static void si_pipe_shader_ps(struct pipe_context *ctx,
struct si_pipe_shader *s
si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
+ shader-cb0_is_integer = rctx-fb_cb0_is_integer;
shader-sprite_coord_enable = rctx-sprite_coord_enable;
si_pm4_bind_state(rctx, ps, shader-pm4);
}
@@ -444,6 +447,10 @@ static void si_update_derived_state(struct r600_context
*rctx)
ps_dirty = 0;
}
+ if (rctx-ps_shader-current-cb0_is_integer !=
rctx-fb_cb0_is_integer) {
+ si_pipe_shader_ps(ctx, rctx-ps_shader-current);
+ ps_dirty = 1;
+ }
if (ps_dirty) {
si_pm4_bind_state(rctx, ps, rctx-ps_shader-current-pm4);
--
1.8.1.2
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[Mesa-dev] [PATCH 11/20] radeonsi: implement uncompressed MSAA texturing
This is glBlitFramebuffer support for MSAA surfaces as required by GL 3.0
and texturing as required by GL 3.2 and GL_ARB_texture_multisample.
---
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 3 ++-
src/gallium/drivers/radeonsi/si_state.c | 17 +++--
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 18aebd2..53bf348 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -363,7 +363,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_COMPUTE:
+ case PIPE_CAP_TEXTURE_MULTISAMPLE:
return 1;
+
case PIPE_CAP_TGSI_TEXCOORD:
return 0;
@@ -385,7 +387,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_USER_VERTEX_BUFFERS:
- case PIPE_CAP_TEXTURE_MULTISAMPLE:
case PIPE_CAP_QUERY_TIMESTAMP:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
case PIPE_CAP_CUBE_MAP_ARRAY:
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 90c31de..108345c 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1555,7 +1555,7 @@ static unsigned si_tex_compare(unsigned compare)
}
}
-static unsigned si_tex_dim(unsigned dim)
+static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
{
switch (dim) {
default:
@@ -1565,9 +1565,11 @@ static unsigned si_tex_dim(unsigned dim)
return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
case PIPE_TEXTURE_2D:
case PIPE_TEXTURE_RECT:
- return V_008F1C_SQ_RSRC_IMG_2D;
+ return nr_samples 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
+ V_008F1C_SQ_RSRC_IMG_2D;
case PIPE_TEXTURE_2D_ARRAY:
- return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
+ return nr_samples 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
+ V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
case PIPE_TEXTURE_3D:
return V_008F1C_SQ_RSRC_IMG_3D;
case PIPE_TEXTURE_CUBE:
@@ -2649,11 +2651,14 @@ static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context *ctx
S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
- S_008F1C_BASE_LEVEL(state-u.tex.first_level) |
- S_008F1C_LAST_LEVEL(state-u.tex.last_level) |
+ S_008F1C_BASE_LEVEL(texture-nr_samples 1 ?
+ 0 :
state-u.tex.first_level) |
+ S_008F1C_LAST_LEVEL(texture-nr_samples 1 ?
+
util_logbase2(texture-nr_samples) :
+ state-u.tex.last_level) |
S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0,
false)) |
S_008F1C_POW2_PAD(texture-last_level 0) |
- S_008F1C_TYPE(si_tex_dim(texture-target)));
+ S_008F1C_TYPE(si_tex_dim(texture-target,
texture-nr_samples)));
view-state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch -
1));
view-state[5] = (S_008F24_BASE_ARRAY(state-u.tex.first_layer) |
S_008F24_LAST_ARRAY(state-u.tex.last_layer));
--
1.8.1.2
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 12/20] radeonsi: implement MSAA colorbuffer compression for rendering
---
src/gallium/drivers/radeonsi/r600_hw_context.c | 11 ++
src/gallium/drivers/radeonsi/r600_resource.h | 21
src/gallium/drivers/radeonsi/r600_texture.c| 133 -
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 2 +
src/gallium/drivers/radeonsi/si_commands.c | 9 ++
src/gallium/drivers/radeonsi/si_state.c| 28 ++
src/gallium/drivers/radeonsi/si_state.h| 2 +
src/gallium/drivers/radeonsi/si_state_draw.c | 11 ++
src/gallium/drivers/radeonsi/sid.h | 1 +
9 files changed, 216 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c
b/src/gallium/drivers/radeonsi/r600_hw_context.c
index 25c972b..382382b 100644
--- a/src/gallium/drivers/radeonsi/r600_hw_context.c
+++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
@@ -179,6 +179,17 @@ static void r600_flush_framebuffer(struct r600_context
*ctx)
si_pm4_emit(ctx, pm4);
si_pm4_free_state(ctx, pm4, ~0);
+ /* flush CB_META */
+ pm4 = si_pm4_alloc_state(ctx);
+
+ if (pm4 == NULL)
+ return;
+
+ si_cmd_flush_and_inv_cb_meta(pm4);
+ si_pm4_emit(ctx, pm4);
+ si_pm4_free_state(ctx, pm4, ~0);
+ ctx-flush_and_inv_cb_meta = false;
+
ctx-flags = ~R600_CONTEXT_DST_CACHES_DIRTY;
}
diff --git a/src/gallium/drivers/radeonsi/r600_resource.h
b/src/gallium/drivers/radeonsi/r600_resource.h
index ca8121f..e5dd36a 100644
--- a/src/gallium/drivers/radeonsi/r600_resource.h
+++ b/src/gallium/drivers/radeonsi/r600_resource.h
@@ -40,6 +40,22 @@ struct r600_transfer {
struct pipe_resource*staging;
};
+struct r600_fmask_info {
+ unsigned offset;
+ unsigned size;
+ unsigned alignment;
+ unsigned bank_height;
+ unsigned slice_tile_max;
+ unsigned tile_mode_index;
+};
+
+struct r600_cmask_info {
+ unsigned offset;
+ unsigned size;
+ unsigned alignment;
+ unsigned slice_tile_max;
+};
+
struct r600_texture {
struct si_resource resource;
@@ -48,12 +64,17 @@ struct r600_texture {
* for the stencil buffer below. */
enum pipe_formatreal_format;
+ unsignedsize;
unsignedpitch_override;
unsignedis_depth;
unsigneddirty_level_mask; /* each bit says if
that miplevel is dirty */
struct r600_texture *flushed_depth_texture;
boolean is_flushing_texture;
struct radeon_surface surface;
+
+ /* Colorbuffer compression and fast clear. */
+ struct r600_fmask_info fmask;
+ struct r600_cmask_info cmask;
};
struct r600_surface {
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c
b/src/gallium/drivers/radeonsi/r600_texture.c
index ed21bd1..cd3d1aa 100644
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -173,6 +173,9 @@ static int r600_setup_surface(struct pipe_screen *screen,
if (r) {
return r;
}
+
+ rtex-size = rtex-surface.bo_size;
+
if (pitch_in_bytes_override pitch_in_bytes_override !=
rtex-surface.level[0].pitch_bytes) {
/* old ddx on evergreen over estimate alignment for 1d, only 1
level
* for those
@@ -419,6 +422,116 @@ static const struct u_resource_vtbl r600_texture_vtbl =
DEBUG_GET_ONCE_BOOL_OPTION(print_texdepth, RADEON_PRINT_TEXDEPTH, FALSE);
+/* The number of samples can be specified independently of the texture. */
+static void r600_texture_get_fmask_info(struct r600_screen *rscreen,
+ struct r600_texture *rtex,
+ unsigned nr_samples,
+ struct r600_fmask_info *out)
+{
+ /* FMASK is allocated like an ordinary texture. */
+ struct radeon_surface fmask = rtex-surface;
+
+ memset(out, 0, sizeof(*out));
+
+ fmask.bo_alignment = 0;
+ fmask.bo_size = 0;
+ fmask.nsamples = 1;
+ fmask.flags |= RADEON_SURF_FMASK | RADEON_SURF_HAS_TILE_MODE_INDEX;
+
+ switch (nr_samples) {
+ case 2:
+ case 4:
+ fmask.bpe = 1;
+ break;
+ case 8:
+ fmask.bpe = 4;
+ break;
+ default:
+ R600_ERR(Invalid sample count for FMASK allocation.\n);
+ return;
+ }
+
+ if (rscreen-ws-surface_init(rscreen-ws, fmask)) {
+ R600_ERR(Got error in surface_init while allocating FMASK.\n);
+ return;
+ }
+
+ assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
+
+ out-slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) /
64;
+ if (out-slice_tile_max)
+ out-slice_tile_max -= 1;
+
[Mesa-dev] [PATCH 13/20] radeonsi: implement FMASK decompression for MSAA texturing
---
src/gallium/drivers/radeonsi/r600_blit.c | 114 +++
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 1 +
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 5 ++
src/gallium/drivers/radeonsi/si_state.c | 29 +--
src/gallium/drivers/radeonsi/si_state_draw.c | 19 +
5 files changed, 149 insertions(+), 19 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/r600_blit.c
b/src/gallium/drivers/radeonsi/r600_blit.c
index 3f9a184..2db952c 100644
--- a/src/gallium/drivers/radeonsi/r600_blit.c
+++ b/src/gallium/drivers/radeonsi/r600_blit.c
@@ -239,6 +239,75 @@ void si_flush_depth_textures(struct r600_context *rctx,
}
}
+static void r600_blit_decompress_color(struct pipe_context *ctx,
+ struct r600_texture *rtex,
+ unsigned first_level, unsigned last_level,
+ unsigned first_layer, unsigned last_layer)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ unsigned layer, level, checked_last_layer, max_layer;
+
+ if (!rtex-dirty_level_mask)
+ return;
+
+ for (level = first_level; level = last_level; level++) {
+ if (!(rtex-dirty_level_mask (1 level)))
+ continue;
+
+ /* The smaller the mipmap level, the less layers there are
+* as far as 3D textures are concerned. */
+ max_layer = util_max_layer(rtex-resource.b.b, level);
+ checked_last_layer = last_layer max_layer ? last_layer :
max_layer;
+
+ for (layer = first_layer; layer = checked_last_layer; layer++)
{
+ struct pipe_surface *cbsurf, surf_tmpl;
+
+ surf_tmpl.format = rtex-resource.b.b.format;
+ surf_tmpl.u.tex.level = level;
+ surf_tmpl.u.tex.first_layer = layer;
+ surf_tmpl.u.tex.last_layer = layer;
+ cbsurf = ctx-create_surface(ctx, rtex-resource.b.b,
surf_tmpl);
+
+ r600_blitter_begin(ctx, R600_DECOMPRESS);
+ util_blitter_custom_color(rctx-blitter, cbsurf,
+
rctx-custom_blend_decompress);
+ r600_blitter_end(ctx);
+
+ pipe_surface_reference(cbsurf, NULL);
+ }
+
+ /* The texture will always be dirty if some layers aren't
flushed.
+* I don't think this case occurs often though. */
+ if (first_layer == 0 last_layer == max_layer) {
+ rtex-dirty_level_mask = ~(1 level);
+ }
+ }
+}
+
+void r600_decompress_color_textures(struct r600_context *rctx,
+ struct r600_textures_info *textures)
+{
+ unsigned i;
+ unsigned mask = textures-compressed_colortex_mask;
+
+ while (mask) {
+ struct pipe_sampler_view *view;
+ struct r600_texture *tex;
+
+ i = u_bit_scan(mask);
+
+ view = textures-views[i]-base;
+ assert(view);
+
+ tex = (struct r600_texture *)view-texture;
+ assert(tex-cmask.size || tex-fmask.size);
+
+ r600_blit_decompress_color(rctx-context, tex,
+ view-u.tex.first_level,
view-u.tex.last_level,
+ 0,
util_max_layer(tex-resource.b.b, view-u.tex.first_level));
+ }
+}
+
static void r600_clear(struct pipe_context *ctx, unsigned buffers,
const union pipe_color_union *color,
double depth, unsigned stencil)
@@ -282,6 +351,28 @@ static void r600_clear_depth_stencil(struct pipe_context
*ctx,
r600_blitter_end(ctx);
}
+/* Helper for decompressing a portion of a color or depth resource before
+ * blitting if any decompression is needed.
+ * The driver doesn't decompress resources automatically while u_blitter is
+ * rendering. */
+static void r600_decompress_subresource(struct pipe_context *ctx,
+ struct pipe_resource *tex,
+ unsigned level,
+ unsigned first_layer, unsigned
last_layer)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_texture *rtex = (struct r600_texture*)tex;
+
+ if (rtex-is_depth !rtex-is_flushing_texture) {
+ si_blit_decompress_depth_in_place(rctx, rtex,
+ level, level,
+ first_layer, last_layer);
+ } else if (rtex-fmask.size || rtex-cmask.size) {
+ r600_blit_decompress_color(ctx, rtex, level, level,
+ first_layer, last_layer);
+ }
+}
+
struct texture_orig_info {
unsigned format;
[Mesa-dev] [PATCH 14/20] radeonsi: reserve a parameter slot for FMASK resources in shaders
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 7 ++--
src/gallium/drivers/radeonsi/radeonsi_shader.h | 58 ++
src/gallium/drivers/radeonsi/si_state_draw.c | 1 +
3 files changed, 36 insertions(+), 30 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 18dde61..2806045 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -1209,7 +1209,7 @@ static void create_function(struct si_shader_context
*si_shader_ctx)
{
struct lp_build_tgsi_context *bld_base =
si_shader_ctx-radeon_bld.soa.bld_base;
struct gallivm_state *gallivm = bld_base-base.gallivm;
- LLVMTypeRef params[20], f32, i8, i32, v2i32, v3i32;
+ LLVMTypeRef params[SI_MAX_PARAMS], f32, i8, i32, v2i32, v3i32;
unsigned i;
i8 = LLVMInt8TypeInContext(gallivm-context);
@@ -1221,6 +1221,7 @@ static void create_function(struct si_shader_context
*si_shader_ctx)
params[SI_PARAM_CONST] = LLVMPointerType(LLVMVectorType(i8, 16),
CONST_ADDR_SPACE);
params[SI_PARAM_SAMPLER] = params[SI_PARAM_CONST];
params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32),
CONST_ADDR_SPACE);
+ params[SI_PARAM_FMASK_RESOURCE] = params[SI_PARAM_RESOURCE];
if (si_shader_ctx-type == TGSI_PROCESSOR_VERTEX) {
params[SI_PARAM_VERTEX_BUFFER] = params[SI_PARAM_SAMPLER];
@@ -1229,7 +1230,7 @@ static void create_function(struct si_shader_context
*si_shader_ctx)
params[SI_PARAM_DUMMY_0] = i32;
params[SI_PARAM_DUMMY_1] = i32;
params[SI_PARAM_INSTANCE_ID] = i32;
- radeon_llvm_create_func(si_shader_ctx-radeon_bld, params, 9);
+ radeon_llvm_create_func(si_shader_ctx-radeon_bld, params, 10);
} else {
params[SI_PARAM_PRIM_MASK] = i32;
@@ -1249,7 +1250,7 @@ static void create_function(struct si_shader_context
*si_shader_ctx)
params[SI_PARAM_ANCILLARY] = f32;
params[SI_PARAM_SAMPLE_COVERAGE] = f32;
params[SI_PARAM_POS_FIXED_PT] = f32;
- radeon_llvm_create_func(si_shader_ctx-radeon_bld, params, 20);
+ radeon_llvm_create_func(si_shader_ctx-radeon_bld, params, 21);
}
radeon_llvm_shader_type(si_shader_ctx-radeon_bld.main_fn,
si_shader_ctx-type);
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h
b/src/gallium/drivers/radeonsi/radeonsi_shader.h
index 2ce34b9..836b144 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h
@@ -34,43 +34,47 @@
#define SI_SGPR_CONST 0
#define SI_SGPR_SAMPLER2
#define SI_SGPR_RESOURCE 4
-#define SI_SGPR_VERTEX_BUFFER 6
-#define SI_SGPR_START_INSTANCE 8
+#define SI_SGPR_FMASK_RESOURCE 6
+#define SI_SGPR_VERTEX_BUFFER 8
+#define SI_SGPR_START_INSTANCE 10
-#define SI_VS_NUM_USER_SGPR9
-#define SI_PS_NUM_USER_SGPR6
+#define SI_VS_NUM_USER_SGPR11
+#define SI_PS_NUM_USER_SGPR8
/* LLVM function parameter indices */
#define SI_PARAM_CONST 0
#define SI_PARAM_SAMPLER 1
#define SI_PARAM_RESOURCE 2
+#define SI_PARAM_FMASK_RESOURCE3
/* VS only parameters */
-#define SI_PARAM_VERTEX_BUFFER 3
-#define SI_PARAM_START_INSTANCE4
-#define SI_PARAM_VERTEX_ID 5
-#define SI_PARAM_DUMMY_0 6
-#define SI_PARAM_DUMMY_1 7
-#define SI_PARAM_INSTANCE_ID 8
+#define SI_PARAM_VERTEX_BUFFER 4
+#define SI_PARAM_START_INSTANCE5
+#define SI_PARAM_VERTEX_ID 6
+#define SI_PARAM_DUMMY_0 7
+#define SI_PARAM_DUMMY_1 8
+#define SI_PARAM_INSTANCE_ID 9
/* PS only parameters */
-#define SI_PARAM_PRIM_MASK 3
-#define SI_PARAM_PERSP_SAMPLE 4
-#define SI_PARAM_PERSP_CENTER 5
-#define SI_PARAM_PERSP_CENTROID6
-#define SI_PARAM_PERSP_PULL_MODEL 7
-#define SI_PARAM_LINEAR_SAMPLE 8
-#define SI_PARAM_LINEAR_CENTER 9
-#define SI_PARAM_LINEAR_CENTROID 10
-#define SI_PARAM_LINE_STIPPLE_TEX 11
-#define SI_PARAM_POS_X_FLOAT 12
-#define SI_PARAM_POS_Y_FLOAT 13
-#define SI_PARAM_POS_Z_FLOAT 14
-#define SI_PARAM_POS_W_FLOAT 15
-#define SI_PARAM_FRONT_FACE16
-#define SI_PARAM_ANCILLARY 17
-#define SI_PARAM_SAMPLE_COVERAGE 18
-#define SI_PARAM_POS_FIXED_PT 19
+#define SI_PARAM_PRIM_MASK 4
+#define SI_PARAM_PERSP_SAMPLE 5
+#define SI_PARAM_PERSP_CENTER 6
+#define SI_PARAM_PERSP_CENTROID7
+#define SI_PARAM_PERSP_PULL_MODEL 8
+#define SI_PARAM_LINEAR_SAMPLE 9
+#define SI_PARAM_LINEAR_CENTER 10
+#define SI_PARAM_LINEAR_CENTROID 11
+#define SI_PARAM_LINE_STIPPLE_TEX 12
+#define SI_PARAM_POS_X_FLOAT 13
+#define
[Mesa-dev] [PATCH 15/20] radeonsi: add basic infrastructure for atom-based states
It's the same as in r600g. Look how simple it is.
---
src/gallium/drivers/radeonsi/r600_hw_context.c | 8
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 9 +
src/gallium/drivers/radeonsi/si_state.h| 10 ++
src/gallium/drivers/radeonsi/si_state_draw.c | 8 +++-
4 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c
b/src/gallium/drivers/radeonsi/r600_hw_context.c
index 382382b..7ed7496 100644
--- a/src/gallium/drivers/radeonsi/r600_hw_context.c
+++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
@@ -114,9 +114,17 @@ err:
void si_need_cs_space(struct r600_context *ctx, unsigned num_dw,
boolean count_draw_in)
{
+ int i;
+
/* The number of dwords we already used in the CS so far. */
num_dw += ctx-cs-cdw;
+ for (i = 0; i ctx-num_atoms; i++) {
+ if (ctx-atoms[i]-dirty) {
+ num_dw += ctx-atoms[i]-num_dw;
+ }
+ }
+
if (count_draw_in) {
/* The number of dwords all the dirty states would take. */
num_dw += ctx-pm4_dirty_cdwords;
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
index e370149..5fa9bdc 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -145,6 +145,10 @@ struct r600_context {
void*custom_blend_decompress;
struct r600_screen *screen;
struct radeon_winsys*ws;
+
+ struct si_atom *atoms[SI_MAX_ATOMS];
+ unsignednum_atoms;
+
struct si_vertex_element*vertex_elements;
struct pipe_framebuffer_state framebuffer;
unsignedfb_log_samples;
@@ -329,4 +333,9 @@ static INLINE uint64_t r600_resource_va(struct pipe_screen
*screen, struct pipe_
return rscreen-ws-buffer_get_virtual_address(rresource-cs_buf);
}
+static INLINE void si_add_atom(struct r600_context *rctx, struct si_atom *atom)
+{
+ rctx-atoms[rctx-num_atoms++] = atom;
+}
+
#endif
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index b01fbf2..4aabdef 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -29,6 +29,16 @@
#include radeonsi_pm4.h
+#define SI_MAX_ATOMS 2
+
+/* This encapsulates a state or an operation which can emitted into the GPU
+ * command stream. */
+struct si_atom {
+ void (*emit)(struct r600_context *ctx, struct si_atom *state);
+ unsignednum_dw;
+ booldirty;
+};
+
struct si_state_blend {
struct si_pm4_state pm4;
uint32_tcb_target_mask;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 4208fa7..bcae778 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -664,7 +664,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct pipe_index_buffer ib = {};
- uint32_t cp_coher_cntl;
+ uint32_t cp_coher_cntl, i;
if (!info-count (info-indexed || !info-count_from_stream_output))
return;
@@ -728,6 +728,12 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
si_need_cs_space(rctx, 0, TRUE);
+ for (i = 0; i rctx-num_atoms; i++) {
+ if (rctx-atoms[i]-dirty) {
+ rctx-atoms[i]-emit(rctx, rctx-atoms[i]);
+ }
+ }
+
si_pm4_emit_dirty(rctx);
rctx-pm4_dirty_cdwords = 0;
--
1.8.1.2
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[Mesa-dev] [PATCH 16/20] radeonsi: add FMASK texture binding slots and resource setup
FMASK is bound as a separate texture. For every texture, there can be
an FMASK. Therefore a separate array of resource slots has to be added.
This adds a new mechanism for emitting resource descriptors, its features are:
- resource descriptors are stored in an ordinary buffer (not in a CS)
- descriptors of disabled resources are set to zeros
- fine-grained resource updates (it can update one resource slot while not
touching the other slots)
- updates are done with the WRITE_DATA packet
- it implements the si_atom interface for packet emission
- only used for FMASK textures right now
The primary motivation for this is that FMASK textures naturally need
fine-grained resource updates and I also need to query in the shader
if a resource is NULL.
---
src/gallium/drivers/radeonsi/Makefile.sources | 1 +
src/gallium/drivers/radeonsi/r600_hw_context.c | 3 +
src/gallium/drivers/radeonsi/r600_resource.h | 1 +
src/gallium/drivers/radeonsi/r600_texture.c| 1 +
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 9 +-
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 6 +-
src/gallium/drivers/radeonsi/radeonsi_pm4.c| 7 +
src/gallium/drivers/radeonsi/radeonsi_pm4.h| 2 +
src/gallium/drivers/radeonsi/si_descriptors.c | 188 +
src/gallium/drivers/radeonsi/si_state.c| 58 +++-
src/gallium/drivers/radeonsi/si_state.h| 36 +
11 files changed, 305 insertions(+), 7 deletions(-)
create mode 100644 src/gallium/drivers/radeonsi/si_descriptors.c
diff --git a/src/gallium/drivers/radeonsi/Makefile.sources
b/src/gallium/drivers/radeonsi/Makefile.sources
index b3ffa72..68c8282 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -10,6 +10,7 @@ C_SOURCES := \
r600_translate.c \
radeonsi_pm4.c \
radeonsi_compute.c \
+ si_descriptors.c \
si_state.c \
si_state_streamout.c \
si_state_draw.c \
diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c
b/src/gallium/drivers/radeonsi/r600_hw_context.c
index 7ed7496..b595477 100644
--- a/src/gallium/drivers/radeonsi/r600_hw_context.c
+++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
@@ -289,6 +289,9 @@ void si_context_flush(struct r600_context *ctx, unsigned
flags)
* next draw command
*/
si_pm4_reset_emitted(ctx);
+
+ si_sampler_views_begin_new_cs(ctx,
ctx-fmask_sampler_views[PIPE_SHADER_VERTEX]);
+ si_sampler_views_begin_new_cs(ctx,
ctx-fmask_sampler_views[PIPE_SHADER_FRAGMENT]);
}
void si_context_emit_fence(struct r600_context *ctx, struct si_resource
*fence_bo, unsigned offset, unsigned value)
diff --git a/src/gallium/drivers/radeonsi/r600_resource.h
b/src/gallium/drivers/radeonsi/r600_resource.h
index e5dd36a..ab5c7b7 100644
--- a/src/gallium/drivers/radeonsi/r600_resource.h
+++ b/src/gallium/drivers/radeonsi/r600_resource.h
@@ -44,6 +44,7 @@ struct r600_fmask_info {
unsigned offset;
unsigned size;
unsigned alignment;
+ unsigned pitch;
unsigned bank_height;
unsigned slice_tile_max;
unsigned tile_mode_index;
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c
b/src/gallium/drivers/radeonsi/r600_texture.c
index cd3d1aa..b613564 100644
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -463,6 +463,7 @@ static void r600_texture_get_fmask_info(struct r600_screen
*rscreen,
out-slice_tile_max -= 1;
out-tile_mode_index = fmask.tiling_index[0];
+ out-pitch = fmask.level[0].nblk_x;
out-bank_height = fmask.bankh;
out-alignment = MAX2(256, fmask.bo_alignment);
out-size = fmask.bo_size;
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index ad955e3..3112124 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -178,6 +178,9 @@ static void r600_destroy_context(struct pipe_context
*context)
{
struct r600_context *rctx = (struct r600_context *)context;
+
si_release_sampler_views(rctx-fmask_sampler_views[PIPE_SHADER_VERTEX]);
+
si_release_sampler_views(rctx-fmask_sampler_views[PIPE_SHADER_FRAGMENT]);
+
si_resource_reference(rctx-border_color_table, NULL);
if (rctx-dummy_pixel_shader) {
@@ -233,12 +236,16 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
rctx-context.create_video_buffer = vl_video_buffer_create;
}
+ rctx-cs = rctx-ws-cs_create(rctx-ws, RING_GFX, NULL);
+
+ si_init_sampler_views(rctx,
rctx-fmask_sampler_views[PIPE_SHADER_VERTEX]);
+ si_init_sampler_views(rctx,
rctx-fmask_sampler_views[PIPE_SHADER_FRAGMENT]);
+
switch (rctx-chip_class) {
case SI:
case CIK:
si_init_state_functions(rctx);
[Mesa-dev] [PATCH 17/20] radeonsi: implement texture fetching for compressed MSAA textures
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 125 -
1 file changed, 120 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 2806045..9ca7a0e 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -67,6 +67,7 @@ struct si_shader_context
LLVMValueRef *constants;
LLVMValueRef *resources;
LLVMValueRef *samplers;
+ LLVMValueRef *fmask_resources;
};
static struct si_shader_context * si_shader_context(
@@ -884,6 +885,12 @@ handle_semantic:
/* ctx-shader-output[i].spi_sid =
r600_spi_sid(ctx-shader-output[i]);*/
}
+static const struct lp_build_tgsi_action txf_action;
+
+static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
+ struct lp_build_tgsi_context * bld_base,
+ struct lp_build_emit_data * emit_data);
+
static void tex_fetch_args(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
@@ -893,9 +900,11 @@ static void tex_fetch_args(
const struct tgsi_full_instruction * inst = emit_data-inst;
unsigned opcode = inst-Instruction.Opcode;
unsigned target = inst-Texture.Texture;
- unsigned sampler_src;
+ unsigned sampler_src, sampler_index;
LLVMValueRef coords[4];
LLVMValueRef address[16];
+ LLVMValueRef sample_index_rewrite = NULL;
+ LLVMValueRef sample_chan = NULL;
int ref_pos;
unsigned num_coords = tgsi_util_get_texture_coord_dim(target, ref_pos);
unsigned count = 0;
@@ -990,9 +999,99 @@ static void tex_fetch_args(
}
sampler_src = emit_data-inst-Instruction.NumSrcRegs - 1;
+ sampler_index = emit_data-inst-Src[sampler_src].Register.Index;
+
+ /* Adjust the sample index according to FMASK.
+*
+* For uncompressed MSAA surfaces, FMASK should return 0x76543210,
+* which is the identity mapping. Each nibble says which physical sample
+* should be fetched to get that sample.
+*
+* For example, 0x1100 means there are only 2 samples stored and
+* the second sample covers 3/4 of the pixel. When reading samples 0
+* and 1, return physical sample 0 (determined by the first two 0s
+* in FMASK), otherwise return physical sample 1.
+*
+* The sample index should be adjusted as follows:
+* sample_index = (fmask (sample_index * 4)) 0xF;
+*/
+ if (target == TGSI_TEXTURE_2D_MSAA ||
+ target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
+ struct lp_build_context *uint_bld = bld_base-uint_bld;
+ struct lp_build_emit_data txf_emit_data = *emit_data;
+ LLVMValueRef txf_address[16];
+ unsigned txf_count = count;
+
+ memcpy(txf_address, address, sizeof(address));
+
+ /* Pad to a power-of-two size. */
+ while (txf_count util_next_power_of_two(txf_count))
+ txf_address[txf_count++] =
LLVMGetUndef(LLVMInt32TypeInContext(gallivm-context));
+
+ /* Read FMASK using TXF. */
+ txf_emit_data.chan = 0;
+ txf_emit_data.dst_type = LLVMVectorType(
+
LLVMInt32TypeInContext(bld_base-base.gallivm-context), 4);
+ txf_emit_data.args[0] = lp_build_gather_values(gallivm,
txf_address, txf_count);
+ txf_emit_data.args[1] =
si_shader_ctx-fmask_resources[sampler_index];
+ txf_emit_data.args[2] =
lp_build_const_int32(bld_base-base.gallivm, target);
+ txf_emit_data.arg_count = 3;
+
+ build_tex_intrinsic(txf_action, bld_base, txf_emit_data);
+
+ /* Initialize some constants. */
+ if (target == TGSI_TEXTURE_2D_MSAA) {
+ sample_chan = LLVMConstInt(uint_bld-elem_type, 2, 0);
+ } else {
+ sample_chan = LLVMConstInt(uint_bld-elem_type, 3, 0);
+ }
+
+ LLVMValueRef four = LLVMConstInt(uint_bld-elem_type, 4, 0);
+ LLVMValueRef F = LLVMConstInt(uint_bld-elem_type, 0xF, 0);
+
+ /* Apply the formula. */
+ LLVMValueRef fmask =
+ LLVMBuildExtractElement(gallivm-builder,
+ txf_emit_data.output[0],
+ uint_bld-zero, );
+
+ LLVMValueRef sample_index =
+ LLVMBuildExtractElement(gallivm-builder,
+ txf_emit_data.args[0],
+ sample_chan, );
+
+ LLVMValueRef sample_index4 =
+ LLVMBuildMul(gallivm-builder, sample_index,
[Mesa-dev] [PATCH 19/20] radeonsi: disable unbound colorbuffers
---
src/gallium/drivers/radeonsi/si_state.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index a09afb2..861f6b9 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2232,7 +2232,7 @@ static void si_set_framebuffer_state(struct pipe_context
*ctx,
struct r600_context *rctx = (struct r600_context *)ctx;
struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
uint32_t tl, br;
- int tl_x, tl_y, br_x, br_y, nr_samples;
+ int tl_x, tl_y, br_x, br_y, nr_samples, i;
if (pm4 == NULL)
return;
@@ -2248,7 +2248,7 @@ static void si_set_framebuffer_state(struct pipe_context
*ctx,
/* build states */
rctx-export_16bpc = 0;
rctx-fb_compressed_cb_mask = 0;
- for (int i = 0; i state-nr_cbufs; i++) {
+ for (i = 0; i state-nr_cbufs; i++) {
struct r600_texture *rtex =
(struct r600_texture*)state-cbufs[i]-texture;
@@ -2258,6 +2258,11 @@ static void si_set_framebuffer_state(struct pipe_context
*ctx,
rctx-fb_compressed_cb_mask |= 1 i;
}
}
+ for (; i 8; i++) {
+ si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
+ S_028C70_FORMAT(V_028C70_COLOR_INVALID));
+ }
+
assert(!(rctx-export_16bpc ~0xff));
si_db(rctx, pm4, state);
--
1.8.1.2
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[Mesa-dev] [PATCH 18/20] radeonsi: port texture improvements from r600g
This started as an attempt to add support for MSAA texture transfers and
MSAA depth-stencil decompression for the DB-CB copy path.
It has gotten a bit out of control, but it's for the greater good.
Some changes do not make much sense, they are there just to make it look
like the other driver.
With a few cosmetic modifications, r600_texture.c can be shared with
a symlink.
---
src/gallium/drivers/r600/r600_blit.c | 3 -
src/gallium/drivers/r600/r600_texture.c | 3 +-
src/gallium/drivers/radeonsi/r600_blit.c | 53 ++-
src/gallium/drivers/radeonsi/r600_resource.h | 7 +-
src/gallium/drivers/radeonsi/r600_texture.c | 528 ---
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 8 +-
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 11 +-
src/gallium/drivers/radeonsi/si_state.c | 21 +-
8 files changed, 365 insertions(+), 269 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_blit.c
b/src/gallium/drivers/r600/r600_blit.c
index 2230e7b..1c22a75 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -171,9 +171,6 @@ void r600_blit_decompress_depth(struct pipe_context *ctx,
zsurf = ctx-create_surface(ctx,
texture-resource.b.b, surf_tmpl);
surf_tmpl.format =
flushed_depth_texture-resource.b.b.format;
- surf_tmpl.u.tex.level = level;
- surf_tmpl.u.tex.first_layer = layer;
- surf_tmpl.u.tex.last_layer = layer;
cbsurf = ctx-create_surface(ctx,
flushed_depth_texture-resource.b.b, surf_tmpl);
diff --git a/src/gallium/drivers/r600/r600_texture.c
b/src/gallium/drivers/r600/r600_texture.c
index 36cca17..742e982 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -458,8 +458,7 @@ r600_texture_create_object(struct pipe_screen *screen,
rtex-is_depth =
util_format_has_depth(util_format_description(rtex-resource.b.b.format));
rtex-surface = *surface;
- r = r600_setup_surface(screen, rtex,
- pitch_in_bytes_override);
+ r = r600_setup_surface(screen, rtex, pitch_in_bytes_override);
if (r) {
FREE(rtex);
return NULL;
diff --git a/src/gallium/drivers/radeonsi/r600_blit.c
b/src/gallium/drivers/radeonsi/r600_blit.c
index 2db952c..d5ed87a 100644
--- a/src/gallium/drivers/radeonsi/r600_blit.c
+++ b/src/gallium/drivers/radeonsi/r600_blit.c
@@ -102,23 +102,31 @@ static void r600_blitter_end(struct pipe_context *ctx)
r600_context_queries_resume(rctx);
}
-void si_blit_uncompress_depth(struct pipe_context *ctx,
+static unsigned u_max_sample(struct pipe_resource *r)
+{
+ return r-nr_samples ? r-nr_samples - 1 : 0;
+}
+
+void r600_blit_decompress_depth(struct pipe_context *ctx,
struct r600_texture *texture,
struct r600_texture *staging,
unsigned first_level, unsigned last_level,
- unsigned first_layer, unsigned last_layer)
+ unsigned first_layer, unsigned last_layer,
+ unsigned first_sample, unsigned last_sample)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- unsigned layer, level, checked_last_layer, max_layer;
+ unsigned layer, level, sample, checked_last_layer, max_layer,
max_sample;
float depth = 1.0f;
const struct util_format_description *desc;
- void *custom_dsa;
+ void **custom_dsa;
struct r600_texture *flushed_depth_texture = staging ?
staging : texture-flushed_depth_texture;
if (!staging !texture-dirty_level_mask)
return;
+ max_sample = u_max_sample(texture-resource.b.b);
+
desc =
util_format_description(flushed_depth_texture-resource.b.b.format);
switch (util_format_has_depth(desc) | util_format_has_stencil(desc)
1) {
default:
@@ -144,30 +152,35 @@ void si_blit_uncompress_depth(struct pipe_context *ctx,
checked_last_layer = last_layer max_layer ? last_layer :
max_layer;
for (layer = first_layer; layer = checked_last_layer; layer++)
{
- struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
+ for (sample = first_sample; sample = last_sample;
sample++) {
+ struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
- surf_tmpl.format = texture-real_format;
- surf_tmpl.u.tex.level = level;
- surf_tmpl.u.tex.first_layer = layer;
- surf_tmpl.u.tex.last_layer = layer;
+ surf_tmpl.format = texture-resource.b.b.format;
+ surf_tmpl.u.tex.level = level;
+
[Mesa-dev] [PATCH 20/20] radeonsi: remove useless code in tex_fetch_args
The array slice has already been added to address.
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 9ca7a0e..d695c9e 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -964,24 +964,6 @@ static void tex_fetch_args(
if (num_coords 2)
address[count++] = coords[2];
- /* Pack array slice */
- switch (target) {
- case TGSI_TEXTURE_1D_ARRAY:
- address[count++] = coords[1];
- }
- switch (target) {
- case TGSI_TEXTURE_2D_ARRAY:
- case TGSI_TEXTURE_2D_ARRAY_MSAA:
- case TGSI_TEXTURE_SHADOW2D_ARRAY:
- address[count++] = coords[2];
- }
- switch (target) {
- case TGSI_TEXTURE_CUBE_ARRAY:
- case TGSI_TEXTURE_SHADOW1D_ARRAY:
- case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
- address[count++] = coords[3];
- }
-
/* Pack LOD */
if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
address[count++] = coords[3];
--
1.8.1.2
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[Mesa-dev] [PATCH 00/20] MSAA support for Radeon SI and more
Hi everyone, This is MSAA support for the radeonsi driver. It implements MSAA rendering, texturing, and colorbuffer compression. The only missing feature is the MSAA fast color clear; other than that, it operates at maximum performance the hardware is capable of. I have some patches for the LLVM shader backend this work depends on. I'll send them soon. In order to support texturing with compressed colorbuffers on SI, a special FMASK texture which holds colorbuffer compression data has to be bound to a shader, which means shaders must support 16 FMASK textures in addition to 16 textures exposed to OpenGL. I came up with a new mechanism for setting up shader resource descriptors specifically for FMASK, because the current mechanism doesn't allow fine-grained resource updates. The descriptors are stored in a buffer and updated using the WRITE_DATA packet, and the state management is pretty much the same as in r600g - it's based on r600_atom. There's more info about why this is a lot better in the commit that adds it. I think we could eventually use it for all shader resources and sampler states. There are also some minor changes which are not related to MSAA. Also the whole r600_texture.c file from r600g is ported to radeonsi. Patches 1-2: One fix for TGSI and a small addition to tgsi_shader_info. Patches 3-7: Small cleanups of the radeonsi driver. Patches 8-18: These are the MSAA patches. Patches 19-20: Small unrelated radeonsi fixes. src/gallium/auxiliary/tgsi/tgsi_scan.c | 13 ++ src/gallium/auxiliary/tgsi/tgsi_scan.h | 1 + src/gallium/auxiliary/tgsi/tgsi_util.c | 4 +- src/gallium/drivers/r600/r600_blit.c | 3 - src/gallium/drivers/r600/r600_texture.c| 3 +- src/gallium/drivers/radeonsi/Makefile.sources | 1 + src/gallium/drivers/radeonsi/r600_blit.c | 327 +- src/gallium/drivers/radeonsi/r600_hw_context.c | 22 +++ src/gallium/drivers/radeonsi/r600_resource.h | 38 +++- src/gallium/drivers/radeonsi/r600_texture.c| 649 src/gallium/drivers/radeonsi/radeonsi_pipe.c | 28 +-- src/gallium/drivers/radeonsi/radeonsi_pipe.h | 40 +++- src/gallium/drivers/radeonsi/radeonsi_pm4.c| 7 + src/gallium/drivers/radeonsi/radeonsi_pm4.h| 2 + src/gallium/drivers/radeonsi/radeonsi_shader.c | 164 --- src/gallium/drivers/radeonsi/radeonsi_shader.h | 60 +++--- src/gallium/drivers/radeonsi/radeonsi_uvd.c| 12 +- src/gallium/drivers/radeonsi/si_commands.c | 9 + src/gallium/drivers/radeonsi/si_descriptors.c | 188 ++ src/gallium/drivers/radeonsi/si_state.c| 511 +-- src/gallium/drivers/radeonsi/si_state.h| 52 - src/gallium/drivers/radeonsi/si_state_draw.c | 55 +- src/gallium/drivers/radeonsi/sid.h | 11 ++ 23 files changed, 1766 insertions(+), 434 deletions(-) Please review. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] R300 'make check' build failure on master and 9.2
On Wed, Aug 07, 2013 at 03:25:48PM -0700, Ian Romanick wrote: On 08/07/2013 01:33 PM, Ian Romanick wrote: On 08/07/2013 08:43 AM, Tom Stellard wrote: On Tue, Aug 06, 2013 at 10:12:19AM -0700, Ian Romanick wrote: We should set a goal for the 9.3 release: all drivers should just build and 'make check' without having to add a bunch of magic incantations to the configure line. We also need a build bot that will build and 'make check' every commit. Ugh. :( +1 for the buildbot I'm having trouble reproducing this, what configure flags are you using? I've attached my full build log. I don't see anything weird on my configure line. Thoughts? Okay... that was too big. Here's just the configure part. cleaning 64 ./autogen.sh --prefix=/opt/xorg-master-x86_64 --libdir=/opt/xorg-master-x86_64/lib64 --disable-glw --disable-glut --disable-glu --disable-xvmc --disable-vdpau --enable-xcb --enable-dri --enable-glx --enable-egl --with-dri-drivers=i965,i915,swrast --enable-64-bit --enable-debug --with-gallium-drivers --enable-gallium-llvm --with-llvm-shared-libs --disable-gallium-g3dvl --enable-glx-tls --enable-texture-float --enable-shared-glapi --enable-gles1 --enable-gles2 Thanks, Ian. I've fixed this failure in master and sent the patches to the stable list for 9.2. Sorry for the inconvenience. -Tom ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 54805] gl_ClipVertex support horribly broken with software TNL
https://bugs.freedesktop.org/show_bug.cgi?id=54805 Ian Romanick i...@freedesktop.org changed: What|Removed |Added Assignee|kenn...@whitecape.org |mesa-dev@lists.freedesktop. ||org CC||bri...@vmware.com Summary|[Bisected regression|gl_ClipVertex support |i915]Piglit |horribly broken with |spec_glsl-1.20_execution_cl |software TNL |ipping_vs-clip-vertex-const | |-reject fails | Component|Drivers/DRI/i915|Mesa core Blocks|67224 | --- Comment #9 from Ian Romanick i...@freedesktop.org --- All the DIFFERING_SIGN business is just a red herring, and this isn't a real regression. It was just dumb luck that vs-clip-vertex-const-reject.shader_test ever passed. I tried several of the other vs-clip-vertex-* tests pass. None of them pass because the clip code always uses gl_Position for clipping instead of gl_ClipVertex. I'm removing this from the blocker list and updating the summary. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] gallivm: honor d3d10's wishes of out-of-bounds behavior for texture size query
From: Roland Scheidegger srol...@vmware.com
Specifically, must return 0 for non-existent mip levels (and non-existent
textures which is an unsolved problem) for everything but total mip count.
---
src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 35 -
1 file changed, 27 insertions(+), 8 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
index 4305c49..b0bb58b 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
@@ -1948,11 +1948,11 @@ lp_build_size_query_soa(struct gallivm_state *gallivm,
LLVMValueRef explicit_lod,
LLVMValueRef *sizes_out)
{
- LLVMValueRef lod;
- LLVMValueRef size;
+ LLVMValueRef lod, level, size;
LLVMValueRef first_level = NULL;
int dims, i;
boolean has_array;
+ unsigned num_lods = 1;
struct lp_build_context bld_int_vec;
dims = texture_dims(static_state-target);
@@ -1975,9 +1975,8 @@ lp_build_size_query_soa(struct gallivm_state *gallivm,
/* FIXME: this needs to honor per-element lod */
lod = LLVMBuildExtractElement(gallivm-builder, explicit_lod,
lp_build_const_int32(gallivm, 0), );
first_level = dynamic_state-first_level(dynamic_state, gallivm,
texture_unit);
- lod = lp_build_broadcast_scalar(bld_int_vec,
- LLVMBuildAdd(gallivm-builder, lod,
first_level, lod));
-
+ level = LLVMBuildAdd(gallivm-builder, lod, first_level, level);
+ lod = lp_build_broadcast_scalar(bld_int_vec, level);
} else {
lod = bld_int_vec.zero;
}
@@ -2013,10 +2012,30 @@ lp_build_size_query_soa(struct gallivm_state *gallivm,
lp_build_const_int32(gallivm, dims), );
/*
-* XXX for out-of-bounds lod, should set size to zero vector here
-* (for dx10-style only, i.e. need_nr_mips)
+* d3d10 requires zero for x/y/z values (but not w, i.e. mip levels)
+* if level is out of bounds (note this can't cover unbound texture
+* here, which also requires returning zero).
*/
-
+ if (explicit_lod need_nr_mips) {
+ LLVMValueRef last_level, out, out1;
+ struct lp_build_context leveli_bld;
+
+ /* everything is scalar for now */
+ lp_build_context_init(leveli_bld, gallivm, lp_type_int_vec(32, 32));
+ last_level = dynamic_state-last_level(dynamic_state, gallivm,
texture_unit);
+
+ out = lp_build_cmp(leveli_bld, PIPE_FUNC_LESS, level, first_level);
+ out1 = lp_build_cmp(leveli_bld, PIPE_FUNC_GREATER, level, last_level);
+ out = lp_build_or(leveli_bld, out, out1);
+ if (num_lods == 1) {
+ out = lp_build_broadcast_scalar(bld_int_vec, out);
+ }
+ else {
+ /* TODO */
+ assert(0);
+ }
+ size = lp_build_andnot(bld_int_vec, size, out);
+ }
for (i = 0; i dims + (has_array ? 1 : 0); i++) {
sizes_out[i] = lp_build_extract_broadcast(gallivm, bld_int_vec.type,
int_type,
size,
--
1.7.9.5
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[Mesa-dev] [PATCH 2/2] gallivm: use texture target from shader instead of static state for size query
From: Roland Scheidegger srol...@vmware.com
d3d10 has no notion of distinct array resources neither at the resource nor
sampler view level. However, shader dcl of resources certainly has, and
d3d10 expects resinfo to return the values according to that - in particular
a resource might have been a 1d texture with some array layers, then the
sampler view might have only used 1 layer so it can be accessed both as 1d
or 1d array texture (I think - the former definitely works). resinfo of a
resource decleared as array needs to return number of array layers but
non-array resource needs to return 0 (and not 1). Hence fix this by passing
the target from the shader decl to emit_size_query and use that (in case of
OpenGL the target will come from the instruction itself).
Could probably do the same for actual sampling, though it may not matter there
(as the bogus components will essentially get clamped away), possibly could
wreak havoc though if it REALLY doesn't match (which is of course an error
but still).
---
src/gallium/auxiliary/draw/draw_llvm_sample.c |2 +
src/gallium/auxiliary/gallivm/lp_bld_sample.h |1 +
src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 32 ++-
src/gallium/auxiliary/gallivm/lp_bld_tgsi.h |1 +
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 43 -
src/gallium/drivers/llvmpipe/lp_tex_sample.c |2 +
6 files changed, 77 insertions(+), 4 deletions(-)
diff --git a/src/gallium/auxiliary/draw/draw_llvm_sample.c
b/src/gallium/auxiliary/draw/draw_llvm_sample.c
index 3016d7c..f10cba3 100644
--- a/src/gallium/auxiliary/draw/draw_llvm_sample.c
+++ b/src/gallium/auxiliary/draw/draw_llvm_sample.c
@@ -270,6 +270,7 @@ draw_llvm_sampler_soa_emit_size_query(const struct
lp_build_sampler_soa *base,
struct gallivm_state *gallivm,
struct lp_type type,
unsigned texture_unit,
+ unsigned target,
boolean need_nr_mips,
boolean scalar_lod,
LLVMValueRef explicit_lod, /* optional */
@@ -284,6 +285,7 @@ draw_llvm_sampler_soa_emit_size_query(const struct
lp_build_sampler_soa *base,
sampler-dynamic_state.base,
type,
texture_unit,
+ target,
need_nr_mips,
scalar_lod,
explicit_lod,
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.h
b/src/gallium/auxiliary/gallivm/lp_bld_sample.h
index dff8be2..db3ea1d 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.h
@@ -497,6 +497,7 @@ lp_build_size_query_soa(struct gallivm_state *gallivm,
struct lp_sampler_dynamic_state *dynamic_state,
struct lp_type int_type,
unsigned texture_unit,
+unsigned target,
boolean need_nr_mips,
boolean scalar_lod,
LLVMValueRef explicit_lod,
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
index b0bb58b..e403ac8 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
@@ -1943,6 +1943,7 @@ lp_build_size_query_soa(struct gallivm_state *gallivm,
struct lp_sampler_dynamic_state *dynamic_state,
struct lp_type int_type,
unsigned texture_unit,
+unsigned target,
boolean need_nr_mips,
boolean scalar_lod,
LLVMValueRef explicit_lod,
@@ -1955,9 +1956,36 @@ lp_build_size_query_soa(struct gallivm_state *gallivm,
unsigned num_lods = 1;
struct lp_build_context bld_int_vec;
- dims = texture_dims(static_state-target);
+ /*
+* Do some sanity verification about bound texture and shader dcl target.
+* Not entirely sure what's possible but assume array/non-array
+* always compatible (probably not ok for OpenGL but d3d10 has no
+* distinction of arrays at the resource level).
+* Everything else looks bogus (though not entirely sure about rect/2d).
+* Currently disabled because it causes assertion failures if there's
+* nothing bound (or rather a dummy texture, not that this case would
+* return the right values).
+*/
+ if (0 static_state-target != target) {
+ if (static_state-target == PIPE_TEXTURE_1D)
+ assert(target == PIPE_TEXTURE_1D_ARRAY);
+ else if (static_state-target == PIPE_TEXTURE_1D_ARRAY)
+ assert(target ==
[Mesa-dev] [Bug 55503] Constant vertex attributes broken
https://bugs.freedesktop.org/show_bug.cgi?id=55503 Ian Romanick i...@freedesktop.org changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|mesa-dev@lists.freedesktop. |i...@freedesktop.org |org | -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] R300 'make check' build failure on master and 9.2
On 08/07/2013 05:45 PM, Tom Stellard wrote: On Wed, Aug 07, 2013 at 03:25:48PM -0700, Ian Romanick wrote: On 08/07/2013 01:33 PM, Ian Romanick wrote: On 08/07/2013 08:43 AM, Tom Stellard wrote: On Tue, Aug 06, 2013 at 10:12:19AM -0700, Ian Romanick wrote: We should set a goal for the 9.3 release: all drivers should just build and 'make check' without having to add a bunch of magic incantations to the configure line. We also need a build bot that will build and 'make check' every commit. Ugh. :( +1 for the buildbot I'm having trouble reproducing this, what configure flags are you using? I've attached my full build log. I don't see anything weird on my configure line. Thoughts? Okay... that was too big. Here's just the configure part. cleaning 64 ./autogen.sh --prefix=/opt/xorg-master-x86_64 --libdir=/opt/xorg-master-x86_64/lib64 --disable-glw --disable-glut --disable-glu --disable-xvmc --disable-vdpau --enable-xcb --enable-dri --enable-glx --enable-egl --with-dri-drivers=i965,i915,swrast --enable-64-bit --enable-debug --with-gallium-drivers --enable-gallium-llvm --with-llvm-shared-libs --disable-gallium-g3dvl --enable-glx-tls --enable-texture-float --enable-shared-glapi --enable-gles1 --enable-gles2 Thanks, Ian. I've fixed this failure in master and sent the patches to the stable list for 9.2. Sorry for the inconvenience. Yay! Looking at the fix, I think that also tells us that the buildbot needs to have as goofy of a build environment as possible. :) Also... I picked the fixes to 9.2. -Tom ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
