[Mesa-dev] [Bug 74717] r600g: 'invalid read' linking geometry shader
https://bugs.freedesktop.org/show_bug.cgi?id=74717 Michel Dänzer changed: What|Removed |Added Assignee|dri-devel@lists.freedesktop |mesa-dev@lists.freedesktop. |.org|org Component|Drivers/Gallium/r600|Mesa core --- Comment #7 from Michel Dänzer --- Looks like a GLSL compiler issue. -- You are receiving this mail because: You are on the CC list for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74727] Mesa 10.1: doesn't build with DRI3 enabled
https://bugs.freedesktop.org/show_bug.cgi?id=74727 Michel Dänzer changed: What|Removed |Added Assignee|mesa-dev@lists.freedesktop. |x...@lists.freedesktop.org |org | QA Contact||x...@lists.freedesktop.org Product|Mesa|XCB Version|git |1.10 Component|GLX |Library --- Comment #4 from Michel Dänzer --- (In reply to comment #1) > You need the xcb randr.h, not the Xlib randr.h. That should be in a > libxcb-randr development package. On debian, that's libxcb-randr0-dev. This dependency should be reflected in xcb-present.pc. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965: Don't call abort() on an unknown device.
If we don't recognize the PCI ID, we can't reasonably load the driver. However, calling abort() is quite rude - it means the application that tried to initialize us (possibly the X server) can't continue via fallback paths. We already have a more polite mechanism - failing to create the context. So, just use that. While we're at it, improve the error message. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73024 Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_device_info.c | 4 ++-- src/mesa/drivers/dri/i965/intel_screen.c| 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c index eb1df79..d931091 100644 --- a/src/mesa/drivers/dri/i965/brw_device_info.c +++ b/src/mesa/drivers/dri/i965/brw_device_info.c @@ -229,7 +229,7 @@ brw_get_device_info(int devid) #define CHIPSET(id, family, name) case id: return &brw_device_info_##family; #include "pci_ids/i965_pci_ids.h" default: - fprintf(stderr, "Unknown Intel device."); - abort(); + fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid); + return NULL; } } diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 6ab3609..acdb5f3 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1328,6 +1328,8 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) intelScreen->deviceID = drm_intel_bufmgr_gem_get_devid(intelScreen->bufmgr); intelScreen->devinfo = brw_get_device_info(intelScreen->deviceID); + if (!intelScreen->devinfo) + return false; intelScreen->hw_must_use_separate_stencil = intelScreen->devinfo->gen >= 7; -- 1.8.5.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/3] glx/apple: Fixed glx context memory leak in case of failure.
---
src/glx/apple/apple_glx_context.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/glx/apple/apple_glx_context.c
b/src/glx/apple/apple_glx_context.c
index 0bb25b4..8a6ded2 100644
--- a/src/glx/apple/apple_glx_context.c
+++ b/src/glx/apple/apple_glx_context.c
@@ -142,6 +142,7 @@ apple_glx_create_context(void **ptr, Display * dpy, int
screen,
if (sharedac && !is_context_valid(sharedac)) {
*errorptr = GLXBadContext;
*x11errorptr = false;
+ free(ac);
return true;
}
--
1.8.5.4
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/3] gbm/dri: Fixed buffer object memory leak in case of failure.
--- src/gbm/backends/dri/gbm_dri.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c index e013980..db4e074 100644 --- a/src/gbm/backends/dri/gbm_dri.c +++ b/src/gbm/backends/dri/gbm_dri.c @@ -609,7 +609,7 @@ gbm_dri_bo_create(struct gbm_device *gbm, dri_format = __DRI_IMAGE_FORMAT_XRGB2101010; break; default: - return NULL; + goto failed; } if (usage & GBM_BO_USE_SCANOUT) @@ -626,7 +626,7 @@ gbm_dri_bo_create(struct gbm_device *gbm, dri_format, dri_use, bo); if (bo->image == NULL) - return NULL; + goto failed; dri->image->queryImage(bo->image, __DRI_IMAGE_ATTRIB_HANDLE, &bo->base.base.handle.s32); @@ -634,6 +634,10 @@ gbm_dri_bo_create(struct gbm_device *gbm, (int *) &bo->base.base.stride); return &bo->base.base; + +failed: + free(bo); + return NULL; } static struct gbm_surface * -- 1.8.5.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/3] r300g/tests: Added missing fclose for FILE resource.
---
src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c
b/src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c
index b4e30d8..239a762 100644
--- a/src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c
+++ b/src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c
@@ -557,6 +557,7 @@ unsigned load_program(
if (last_char && last_char != '\n') {
fprintf(stderr, "Error line cannot be longer than 100 "
"characters:\n%s\n", line);
+ fclose(file);
return 0;
}
@@ -605,5 +606,7 @@ unsigned load_program(
// XXX: Parse immediates from the file.
add_instruction(c, test->input[i]);
}
+
+ fclose(file);
return 1;
}
--
1.8.5.4
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] Texture from RenderBuffer for blitting
Hi,
I was looking over the _mesa_meta_BlitFramebuffer and in particular,
blitframebuffer_texture(). A few idea (feedback welcome and wanted):
Firstly, the check if src is a renderbuffer or not. I think it might be a good
idea to add an internal Mesa API to allow a driver to specify that a
renderbuffer can be used as a texture. I believe that atleast for i965, this
would make that blitframebuffer_texture() would likely always be used when i965
blitframebuffer implementation uses _mesa_meta_BlitFramebuffer.
Secondly, if a driver supports MRT, I think it would be better to use an MRT
fragment shader instead of a looping over each render target. Indeed, by doing
so, the read associated to the texture fetch would happen once instead of once
per color buffer.
Thirdly (and this is quite minor), rather than using a VBO to hold the vertex
data, I'd think it would be better if the vertex data was static values {
{0,1}, {1,0}, {1,1}, {0,1} } and the vertex shader would have uniforms that
takes the local normalized values and produces the texture coordinate (and clip
positional values). The reason being that since the same buffer object is used,
changing it and then using it means that if an application does several blits
in a row then an underlying driver will either stall or do "something" for the
buffer object (for i965 since it is small, this means copy it usually).
Lastly, in handling the case where the src and dest are the same buffers in the
case where the buffer can be viewed as a texture rather than using
CopyTex[Sub]Image to a temporary buffer, to instead use
blitframebuffer_texture() onto a temporary texture and then use
blitframebuffer_texture() onto the dest. The main benefit being that various
format conversion cases are then handled properly (since CopyTex[Sub]Image
requires the formats to match more closely than BlitFramebuffer requires).
-Kevin
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Texture from RenderBuffer for blitting
Hi,
Um, please ignore the 1st suggestion; it was already in Mesa and I was not
awake of enough. Sighs.
From: Rogovin, Kevin
Sent: Monday, February 10, 2014 12:06 PM
To: mesa-dev@lists.freedesktop.org
Cc: Romanick, Ian D
Subject: Texture from RenderBuffer for blitting
Hi,
I was looking over the _mesa_meta_BlitFramebuffer and in particular,
blitframebuffer_texture(). A few idea (feedback welcome and wanted):
Firstly, the check if src is a renderbuffer or not. I think it might be a good
idea to add an internal Mesa API to allow a driver to specify that a
renderbuffer can be used as a texture. I believe that atleast for i965, this
would make that blitframebuffer_texture() would likely always be used when i965
blitframebuffer implementation uses _mesa_meta_BlitFramebuffer.
Secondly, if a driver supports MRT, I think it would be better to use an MRT
fragment shader instead of a looping over each render target. Indeed, by doing
so, the read associated to the texture fetch would happen once instead of once
per color buffer.
Thirdly (and this is quite minor), rather than using a VBO to hold the vertex
data, I'd think it would be better if the vertex data was static values {
{0,1}, {1,0}, {1,1}, {0,1} } and the vertex shader would have uniforms that
takes the local normalized values and produces the texture coordinate (and clip
positional values). The reason being that since the same buffer object is used,
changing it and then using it means that if an application does several blits
in a row then an underlying driver will either stall or do "something" for the
buffer object (for i965 since it is small, this means copy it usually).
Lastly, in handling the case where the src and dest are the same buffers in the
case where the buffer can be viewed as a texture rather than using
CopyTex[Sub]Image to a temporary buffer, to instead use
blitframebuffer_texture() onto a temporary texture and then use
blitframebuffer_texture() onto the dest. The main benefit being that various
format conversion cases are then handled properly (since CopyTex[Sub]Image
requires the formats to match more closely than BlitFramebuffer requires).
-Kevin
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] meta_blitframebuffer integer format corrections
Corrects the format for the temp texture used in
for the case where source framebuffer is an integer
texture when blitframebuffer_texture() cannot be used.
Note: Does NOT correct the underling blits, rather only
corrects the format of the temporary texture to be
an integer format.
---
src/mesa/drivers/common/meta.c | 42 +++---
1 file changed, 39 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index f12bcaa..b446053 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -356,6 +356,34 @@ static void meta_glsl_clear_cleanup(struct clear_state
*clear);
static void meta_glsl_generate_mipmap_cleanup(struct gen_mipmap_state *mipmap);
static void meta_decompress_cleanup(struct decompress_state *decompress);
static void meta_drawpix_cleanup(struct drawpix_state *drawpix);
+static GLenum meta_integer_suffixed_format(GLenum base_format);
+
+/**
+ * returns the base_format value suffixed with _INTEGER
+ */
+static GLenum
+meta_integer_suffixed_format(GLenum base_format)
+{
+ switch(base_format) {
+ case GL_RED:
+ return GL_RED_INTEGER;
+ case GL_RG:
+ return GL_RG_INTEGER;
+ case GL_RGB:
+ return GL_RGB_INTEGER;
+ case GL_RGBA:
+ return GL_RGBA_INTEGER;
+ case GL_ALPHA:
+ return GL_ALPHA_INTEGER_EXT;
+ case GL_LUMINANCE:
+ return GL_LUMINANCE_INTEGER_EXT;
+ case GL_LUMINANCE_ALPHA:
+ return GL_LUMINANCE_ALPHA_INTEGER_EXT;
+ default:
+ return base_format;
+ }
+}
+
static GLuint
compile_shader_with_debug(struct gl_context *ctx, GLenum target, const
GLcharARB *source)
@@ -1902,15 +1930,23 @@ _mesa_meta_BlitFramebuffer(struct gl_context *ctx,
const struct gl_renderbuffer *colorReadRb = readFb->_ColorReadBuffer;
const GLenum rb_base_format =
_mesa_base_tex_format(ctx, colorReadRb->InternalFormat);
+ const GLenum rb_datatype =
+ _mesa_get_format_datatype(colorReadRb->Format);
+ const GLenum rb_format = (rb_datatype==GL_INT
+|| rb_datatype==GL_UNSIGNED_INT) ?
+ meta_integer_suffixed_format(rb_base_format):
+ rb_base_format;
+
+
- /* Using the exact source rectangle to create the texture does incorrect
+ /* Using the exact source rectangle to create the texture does incorrect
* linear filtering along the edges. So, allocate the texture extended
along
* edges by one pixel in x, y directions.
*/
- newTex = alloc_texture(tex, srcW + 2, srcH + 2, rb_base_format);
+ newTex = alloc_texture(tex, srcW + 2, srcH + 2,
colorReadRb->InternalFormat);
setup_copypix_texture(ctx, tex, newTex,
srcX - 1, srcY - 1, srcW + 2, srcH + 2,
-rb_base_format, filter);
+rb_format, filter);
/* texcoords (after texture allocation!) */
{
verts[0].s = 1.0F;
--
1.8.1.2
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74760] Anno 1701 colors of textures are corrupted using Intel GM45 Express chipset
https://bugs.freedesktop.org/show_bug.cgi?id=74760 --- Comment #4 from chefche...@gmx.de --- Created attachment 93763 --> https://bugs.freedesktop.org/attachment.cgi?id=93763&action=edit winedbg error log -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/3] st/xa: use pipe-loader to get screen
Hi Rob
On 08/02/14 22:41, Rob Clark wrote:
> From: Rob Clark
>
> This lets multiple gallium drivers use XA.
>
> Signed-off-by: Rob Clark
> ---
> configure.ac | 8 ++--
> src/gallium/state_trackers/xa/Makefile.am | 11 -
> src/gallium/state_trackers/xa/xa_priv.h | 1 +
> src/gallium/state_trackers/xa/xa_tracker.c| 6 ++-
> src/gallium/state_trackers/xa/xatracker.pc.in | 9
> src/gallium/targets/Makefile.am | 4 --
> src/gallium/targets/xa-vmwgfx/Makefile.am | 61
> ---
> src/gallium/targets/xa-vmwgfx/vmw_target.c| 26
> src/gallium/targets/xa-vmwgfx/xatracker.pc.in | 9
> 9 files changed, 29 insertions(+), 106 deletions(-)
> create mode 100644 src/gallium/state_trackers/xa/xatracker.pc.in
> delete mode 100644 src/gallium/targets/xa-vmwgfx/Makefile.am
> delete mode 100644 src/gallium/targets/xa-vmwgfx/vmw_target.c
> delete mode 100644 src/gallium/targets/xa-vmwgfx/xatracker.pc.in
>
> diff --git a/configure.ac b/configure.ac
> index 2424dde..6f490fc 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -1270,6 +1270,7 @@ dnl XA configuration
> dnl
> if test "x$enable_xa" = xyes; then
> GALLIUM_STATE_TRACKERS_DIRS="xa $GALLIUM_STATE_TRACKERS_DIRS"
> +enable_gallium_loader=yes
> fi
> AM_CONDITIONAL(HAVE_ST_XA, test "x$enable_xa" = xyes)
>
> @@ -1743,7 +1744,7 @@ if test "x$with_gallium_drivers" != x; then
> xsvga)
> HAVE_GALLIUM_SVGA=yes
> GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS svga softpipe"
> -gallium_check_st "svga/drm" "dri-vmwgfx" "xa-vmwgfx"
> +gallium_check_st "svga/drm" "dri-vmwgfx" ""
> ;;
> xi915)
> HAVE_GALLIUM_I915=yes
> @@ -1959,7 +1960,7 @@ AC_SUBST([XVMC_MAJOR], 1)
> AC_SUBST([XVMC_MINOR], 0)
>
> AC_SUBST([XA_MAJOR], 2)
> -AC_SUBST([XA_MINOR], 1)
> +AC_SUBST([XA_MINOR], 2)
> AC_SUBST([XA_TINY], 0)
> AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_TINY")
>
> @@ -2021,6 +2022,7 @@ AC_CONFIG_FILES([Makefile
> src/gallium/state_trackers/vdpau/Makefile
> src/gallium/state_trackers/vega/Makefile
> src/gallium/state_trackers/xa/Makefile
> + src/gallium/state_trackers/xa/xatracker.pc
> src/gallium/state_trackers/xvmc/Makefile
> src/gallium/targets/Makefile
> src/gallium/targets/dri-freedreno/Makefile
> @@ -2043,8 +2045,6 @@ AC_CONFIG_FILES([Makefile
> src/gallium/targets/r600/xvmc/Makefile
> src/gallium/targets/libgl-xlib/Makefile
> src/gallium/targets/vdpau-nouveau/Makefile
> - src/gallium/targets/xa-vmwgfx/Makefile
> - src/gallium/targets/xa-vmwgfx/xatracker.pc
> src/gallium/targets/xvmc-nouveau/Makefile
> src/gallium/tests/trivial/Makefile
> src/gallium/tests/unit/Makefile
> diff --git a/src/gallium/state_trackers/xa/Makefile.am
> b/src/gallium/state_trackers/xa/Makefile.am
> index 7d0b366..37ec0c4 100644
> --- a/src/gallium/state_trackers/xa/Makefile.am
> +++ b/src/gallium/state_trackers/xa/Makefile.am
> @@ -25,6 +25,8 @@ include $(top_srcdir)/src/gallium/Automake.inc
>
> AM_CFLAGS = \
> -Wall -pedantic \
> + $(GALLIUM_PIPE_LOADER_DEFINES) \
> + -DPIPE_SEARCH_DIR=\"$(libdir)/gallium-pipe\" \
> $(GALLIUM_CFLAGS) \
> $(VISIBILITY_CFLAGS)
>
> @@ -33,12 +35,19 @@ AM_CPPFLAGS = \
> -I$(top_srcdir)/src/gallium/winsys \
> -I$(top_srcdir)/src/gallium/drivers
>
> +pkgconfigdir = $(libdir)/pkgconfig
> +pkgconfig_DATA = xatracker.pc
> +
> xa_includedir = $(includedir)
> xa_include_HEADERS = \
> xa_composite.h \
> xa_context.h \
> xa_tracker.h
>
> -noinst_LTLIBRARIES = libxatracker.la
> +lib_LTLIBRARIES = libxatracker.la
>
> libxatracker_la_SOURCES = $(C_SOURCES)
> +libxatracker_la_LIBADD = \
> + $(GALLIUM_PIPE_LOADER_LIBS) \
> + $(top_builddir)/src/gallium/auxiliary/pipe-loader/libpipe_loader.la \
> + $(top_builddir)/src/gallium/auxiliary/libgallium.la
Can you please keep this as is, and add a xatracker target in the
targets folder. Similar to the way opencl and gbm are handled.
> diff --git a/src/gallium/state_trackers/xa/xa_priv.h
> b/src/gallium/state_trackers/xa/xa_priv.h
> index ee182e7..b99c214 100644
> --- a/src/gallium/state_trackers/xa/xa_priv.h
> +++ b/src/gallium/state_trackers/xa/xa_priv.h
> @@ -74,6 +74,7 @@ struct xa_tracker {
> unsigned int format_map[XA_LAST_SURFACE_TYPE][2];
> int d_depth_bits_last;
> int ds_depth_bits_last;
> +struct pipe_loader_device *dev;
> struct pipe_screen *screen;
> struct xa_context *default_ctx;
> };
> diff --git a/src/gallium/state_trackers/xa/xa_tracker.c
> b/src/gallium/state_trackers/xa/xa_tracker.c
> index cda6501..840c361 100644
> --- a/src/gallium/state_trackers/xa/xa_tracker.c
> +++ b/src/ga
[Mesa-dev] [Bug 74760] Anno 1701 colors of textures are corrupted using Intel GM45 Express chipset
https://bugs.freedesktop.org/show_bug.cgi?id=74760 --- Comment #6 from chefche...@gmx.de --- Created attachment 93768 --> https://bugs.freedesktop.org/attachment.cgi?id=93768&action=edit intel bios dump -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74760] Anno 1701 colors of textures are corrupted using Intel GM45 Express chipset
https://bugs.freedesktop.org/show_bug.cgi?id=74760 --- Comment #5 from chefche...@gmx.de --- Created attachment 93767 --> https://bugs.freedesktop.org/attachment.cgi?id=93767&action=edit intel reg dumper output -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74760] Anno 1701 colors of textures are corrupted using Intel GM45 Express chipset
https://bugs.freedesktop.org/show_bug.cgi?id=74760 --- Comment #7 from chefche...@gmx.de --- lspci 00:00.0 Host bridge: Intel Corporation Mobile 4 Series Chipset Memory Controller Hub (rev 07) 00:02.0 VGA compatible controller: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller (rev 07) 00:02.1 Display controller: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller (rev 07) uname -r 3.11.10-7-desktop uname -m x86_64 (however it's biarch) pkg-config --modversion libdrm 2.4.46 hope that's enough. If not would someone please tell me how to do an API trace (what debug libraries do I have to install and what commands to use) -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/3] pipe-loader: add pipe loader for freedreno/msm
On 08/02/14 22:41, Rob Clark wrote:
> From: Rob Clark
>
> Signed-off-by: Rob Clark
> ---
> src/gallium/targets/pipe-loader/Makefile.am | 16
> src/gallium/targets/pipe-loader/pipe_msm.c | 20
> 2 files changed, 36 insertions(+)
> create mode 100644 src/gallium/targets/pipe-loader/pipe_msm.c
>
> diff --git a/src/gallium/targets/pipe-loader/Makefile.am
> b/src/gallium/targets/pipe-loader/Makefile.am
> index 97733c1..8a0f254 100644
> --- a/src/gallium/targets/pipe-loader/Makefile.am
> +++ b/src/gallium/targets/pipe-loader/Makefile.am
> @@ -132,6 +132,22 @@ pipe_radeonsi_la_LDFLAGS += $(LLVM_LDFLAGS)
> endif
> endif
>
> +if HAVE_GALLIUM_FREEDRENO
> +pipe_LTLIBRARIES += pipe_msm.la
> +pipe_msm_la_SOURCES = pipe_msm.c
> +nodist_EXTRA_pipe_msm_la_SOURCES = dummy.cpp
> +pipe_msm_la_LIBADD = \
> + $(PIPE_LIBS) \
> + $(top_builddir)/src/gallium/winsys/freedreno/drm/libfreedrenodrm.la \
> + $(top_builddir)/src/gallium/drivers/freedreno/libfreedreno.la \
> + $(LIBDRM_LIBS)
> +pipe_msm_la_LDFLAGS = -no-undefined -avoid-version -module
> +if HAVE_MESA_LLVM
> +pipe_msm_la_LIBADD += $(LLVM_LIBS)
> +pipe_msm_la_LDFLAGS += $(LLVM_LDFLAGS)
> +endif
> +endif
> +
> if HAVE_GALLIUM_SVGA
> pipe_LTLIBRARIES += pipe_vmwgfx.la
> pipe_vmwgfx_la_SOURCES = pipe_vmwgfx.c
> diff --git a/src/gallium/targets/pipe-loader/pipe_msm.c
> b/src/gallium/targets/pipe-loader/pipe_msm.c
> new file mode 100644
> index 000..509e94c
> --- /dev/null
> +++ b/src/gallium/targets/pipe-loader/pipe_msm.c
> @@ -0,0 +1,20 @@
> +
> +#include "target-helpers/inline_debug_helper.h"
> +#include "state_tracker/drm_driver.h"
> +#include "freedreno/drm/freedreno_drm_public.h"
> +
> +static struct pipe_screen *
> +create_screen(int fd)
> +{
> + struct pipe_screen *screen;
> +
> + screen = fd_drm_screen_create(fd);
> + if (!screen)
> + return NULL;
> +
> + screen = debug_screen_wrap(screen);
> +
> + return screen;
> +}
> +
> +DRM_DRIVER_DESCRIPTOR("msm", "freedreno", create_screen, NULL)
>
The driver descriptor has to be marked as public. Otherwise the symbol
will not be exported when we add VISIBILITY_CFLAGS to
targets/pipe-loader/Makefile.am
-Emil
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74717] r600g: 'invalid read' linking geometry shader
https://bugs.freedesktop.org/show_bug.cgi?id=74717 --- Comment #8 from Dieter Nützel --- 3.13.2 + geom + UVD IRQ patch Mesa 10.2.0-devel (git-a487ef8) LLVM 3.4 stable RV730 AGP With R600_DEBUG=nollvm it sometimes runs without crash but empty (black) window and somtimes like this: /opt/ogl-samples> ./build/release/gl-320-primitive-shading OpenGL Version Needed 3.2 ( 3.3 Found ) Compiling shader gl-320/primitive-shading.vert... Compiling shader gl-320/primitive-shading.geom... Compiling shader gl-320/primitive-shading.frag... Linking program Running Test EE r600_shader.c:345 tgsi_is_supported - unsupported src 0 (dimension 1) EE r600_shader.c:157 r600_pipe_shader_create - translation from TGSI failed ! EE r600_state_common.c:745 r600_shader_select - Failed to build shader variant (type=2) -22 EE r600_shader.c:345 tgsi_is_supported - unsupported src 0 (dimension 1) EE r600_shader.c:157 r600_pipe_shader_create - translation from TGSI failed ! EE r600_state_common.c:745 r600_shader_select - Failed to build shader variant (type=2) -22 EE r600_shader.c:345 tgsi_is_supported - unsupported src 0 (dimension 1) EE r600_shader.c:157 r600_pipe_shader_create - translation from TGSI failed ! EE r600_state_common.c:745 r600_shader_select - Failed to build shader variant (type=2) -22 [-] Test Ended Test Began Correctly. -- You are receiving this mail because: You are on the CC list for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/3] st/xa: use pipe-loader to get screen
On Mon, Feb 10, 2014 at 7:37 AM, Emil Velikov wrote:
> Hi Rob
>
> On 08/02/14 22:41, Rob Clark wrote:
>> From: Rob Clark
>>
>> This lets multiple gallium drivers use XA.
>>
>> Signed-off-by: Rob Clark
>> ---
>> configure.ac | 8 ++--
>> src/gallium/state_trackers/xa/Makefile.am | 11 -
>> src/gallium/state_trackers/xa/xa_priv.h | 1 +
>> src/gallium/state_trackers/xa/xa_tracker.c| 6 ++-
>> src/gallium/state_trackers/xa/xatracker.pc.in | 9
>> src/gallium/targets/Makefile.am | 4 --
>> src/gallium/targets/xa-vmwgfx/Makefile.am | 61
>> ---
>> src/gallium/targets/xa-vmwgfx/vmw_target.c| 26
>> src/gallium/targets/xa-vmwgfx/xatracker.pc.in | 9
>> 9 files changed, 29 insertions(+), 106 deletions(-)
>> create mode 100644 src/gallium/state_trackers/xa/xatracker.pc.in
>> delete mode 100644 src/gallium/targets/xa-vmwgfx/Makefile.am
>> delete mode 100644 src/gallium/targets/xa-vmwgfx/vmw_target.c
>> delete mode 100644 src/gallium/targets/xa-vmwgfx/xatracker.pc.in
>>
>> diff --git a/configure.ac b/configure.ac
>> index 2424dde..6f490fc 100644
>> --- a/configure.ac
>> +++ b/configure.ac
>> @@ -1270,6 +1270,7 @@ dnl XA configuration
>> dnl
>> if test "x$enable_xa" = xyes; then
>> GALLIUM_STATE_TRACKERS_DIRS="xa $GALLIUM_STATE_TRACKERS_DIRS"
>> +enable_gallium_loader=yes
>> fi
>> AM_CONDITIONAL(HAVE_ST_XA, test "x$enable_xa" = xyes)
>>
>> @@ -1743,7 +1744,7 @@ if test "x$with_gallium_drivers" != x; then
>> xsvga)
>> HAVE_GALLIUM_SVGA=yes
>> GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS svga softpipe"
>> -gallium_check_st "svga/drm" "dri-vmwgfx" "xa-vmwgfx"
>> +gallium_check_st "svga/drm" "dri-vmwgfx" ""
>> ;;
>> xi915)
>> HAVE_GALLIUM_I915=yes
>> @@ -1959,7 +1960,7 @@ AC_SUBST([XVMC_MAJOR], 1)
>> AC_SUBST([XVMC_MINOR], 0)
>>
>> AC_SUBST([XA_MAJOR], 2)
>> -AC_SUBST([XA_MINOR], 1)
>> +AC_SUBST([XA_MINOR], 2)
>> AC_SUBST([XA_TINY], 0)
>> AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_TINY")
>>
>> @@ -2021,6 +2022,7 @@ AC_CONFIG_FILES([Makefile
>> src/gallium/state_trackers/vdpau/Makefile
>> src/gallium/state_trackers/vega/Makefile
>> src/gallium/state_trackers/xa/Makefile
>> + src/gallium/state_trackers/xa/xatracker.pc
>> src/gallium/state_trackers/xvmc/Makefile
>> src/gallium/targets/Makefile
>> src/gallium/targets/dri-freedreno/Makefile
>> @@ -2043,8 +2045,6 @@ AC_CONFIG_FILES([Makefile
>> src/gallium/targets/r600/xvmc/Makefile
>> src/gallium/targets/libgl-xlib/Makefile
>> src/gallium/targets/vdpau-nouveau/Makefile
>> - src/gallium/targets/xa-vmwgfx/Makefile
>> - src/gallium/targets/xa-vmwgfx/xatracker.pc
>> src/gallium/targets/xvmc-nouveau/Makefile
>> src/gallium/tests/trivial/Makefile
>> src/gallium/tests/unit/Makefile
>> diff --git a/src/gallium/state_trackers/xa/Makefile.am
>> b/src/gallium/state_trackers/xa/Makefile.am
>> index 7d0b366..37ec0c4 100644
>> --- a/src/gallium/state_trackers/xa/Makefile.am
>> +++ b/src/gallium/state_trackers/xa/Makefile.am
>> @@ -25,6 +25,8 @@ include $(top_srcdir)/src/gallium/Automake.inc
>>
>> AM_CFLAGS = \
>> -Wall -pedantic \
>> + $(GALLIUM_PIPE_LOADER_DEFINES) \
>> + -DPIPE_SEARCH_DIR=\"$(libdir)/gallium-pipe\" \
>> $(GALLIUM_CFLAGS) \
>> $(VISIBILITY_CFLAGS)
>>
>> @@ -33,12 +35,19 @@ AM_CPPFLAGS = \
>> -I$(top_srcdir)/src/gallium/winsys \
>> -I$(top_srcdir)/src/gallium/drivers
>>
>> +pkgconfigdir = $(libdir)/pkgconfig
>> +pkgconfig_DATA = xatracker.pc
>> +
>> xa_includedir = $(includedir)
>> xa_include_HEADERS = \
>> xa_composite.h \
>> xa_context.h \
>> xa_tracker.h
>>
>> -noinst_LTLIBRARIES = libxatracker.la
>> +lib_LTLIBRARIES = libxatracker.la
>>
>> libxatracker_la_SOURCES = $(C_SOURCES)
>> +libxatracker_la_LIBADD = \
>> + $(GALLIUM_PIPE_LOADER_LIBS) \
>> + $(top_builddir)/src/gallium/auxiliary/pipe-loader/libpipe_loader.la \
>> + $(top_builddir)/src/gallium/auxiliary/libgallium.la
> Can you please keep this as is, and add a xatracker target in the
> targets folder. Similar to the way opencl and gbm are handled.
I confess to not completely understanding the separation between
target vs state tracker.. I guess I'll have a closer look at gbm and
opencl.
>> diff --git a/src/gallium/state_trackers/xa/xa_priv.h
>> b/src/gallium/state_trackers/xa/xa_priv.h
>> index ee182e7..b99c214 100644
>> --- a/src/gallium/state_trackers/xa/xa_priv.h
>> +++ b/src/gallium/state_trackers/xa/xa_priv.h
>> @@ -74,6 +74,7 @@ struct xa_tracker {
>> unsigned int format_map[XA_LAST_SURFACE_TYPE][2];
>> int d_depth_bits_last;
>> int ds_depth_bits_last;
>> +struct pipe_lo
[Mesa-dev] [Bug 74760] Anno 1701 colors of textures are corrupted using Intel GM45 Express chipset
https://bugs.freedesktop.org/show_bug.cgi?id=74760 --- Comment #8 from chefche...@gmx.de --- Created attachment 93772 --> https://bugs.freedesktop.org/attachment.cgi?id=93772&action=edit strace extract -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/3] pipe-loader: split out "client" version
On 08/02/14 22:41, Rob Clark wrote: > From: Rob Clark > > Build two versions of pipe-loader, with only the client version linking > in x11 client side dependencies. This will allow the XA state tracker > to use pipe-loader. > AFAICS it's rather messy story * s/HAVE_WINSYS_XLIB/NEED_WINSYS_XLIB/ s/x11_sw_create/xlib_create_sw_winsys/ * Then we should add to make pipe_loader_have_xcb configurable (either explicitly or implicitly). * Set NEED_WINSYS_XLIB=yes whenever pipe_loader_have_xcb is enabled and check for all the configure mayhem. Add a separate xcb/xlib pipe-loader and drop the current "standalone" one. -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/3] pipe-loader: split out "client" version
On 08/02/14 22:41, Rob Clark wrote:
> From: Rob Clark
>
> Build two versions of pipe-loader, with only the client version linking
> in x11 client side dependencies. This will allow the XA state tracker
> to use pipe-loader.
>
> Signed-off-by: Rob Clark
> ---
> configure.ac | 11 +--
> src/gallium/auxiliary/pipe-loader/Makefile.am | 19 ---
> src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 2 ++
> src/gallium/targets/gbm/Makefile.am| 4 ++--
> src/gallium/targets/opencl/Makefile.am | 4 ++--
> src/gallium/tests/trivial/Makefile.am | 4 ++--
> 6 files changed, 33 insertions(+), 11 deletions(-)
>
> diff --git a/configure.ac b/configure.ac
> index ba158e8..2424dde 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -1895,6 +1895,11 @@ AM_CONDITIONAL(NEED_GALLIUM_LLVMPIPE_DRIVER, test
> "x$HAVE_GALLIUM_I915" = xyes -
>"x$HAVE_GALLIUM_SOFTPIPE"
> = xyes \
>&& test "x$MESA_LLVM" = x1)
>
> +# NOTE: anything using xcb or other client side libs ends up in separate
> +# _CLIENT variables. The pipe loader is built in two variants,
> +# one that is standalone and does not link any x client libs (for
> +# use by XA tracker in particular, but could be used in any case
> +# where communication with xserver is not desired).
> if test "x$enable_gallium_loader" = xyes; then
> GALLIUM_WINSYS_DIRS="$GALLIUM_WINSYS_DIRS sw/null"
>
> @@ -1903,13 +1908,15 @@ if test "x$enable_gallium_loader" = xyes; then
> PKG_CHECK_MODULES([GALLIUM_PIPE_LOADER_XCB], [xcb xcb-dri2],
>pipe_loader_have_xcb=yes, pipe_loader_have_xcb=no)
> if test "x$pipe_loader_have_xcb" = xyes; then
> -GALLIUM_PIPE_LOADER_DEFINES="$GALLIUM_PIPE_LOADER_DEFINES
> -DHAVE_PIPE_LOADER_XCB"
> -GALLIUM_PIPE_LOADER_LIBS="$GALLIUM_PIPE_LOADER_LIBS
> $GALLIUM_PIPE_LOADER_XCB_LIBS $LIBDRM_LIBS"
> +
> GALLIUM_PIPE_LOADER_CLIENT_DEFINES="$GALLIUM_PIPE_LOADER_CLIENT_DEFINES
> -DHAVE_PIPE_LOADER_XCB"
> +
> GALLIUM_PIPE_LOADER_CLIENT_LIBS="$GALLIUM_PIPE_LOADER_CLIENT_LIBS
> $GALLIUM_PIPE_LOADER_XCB_LIBS $LIBDRM_LIBS"
The previous comments on this patch were more of a general (follow on)
cleanup to get the sw thing working than anything else.
I'm assuming that you need to drop the CLIENT_ from the rhs for both
defines and libs. Like the following
GALLIUM_PIPE_LOADER_CLIENT_DEFINES="$GALLIUM_PIPE_LOADER_DEFINES
-DHAVE_PIPE_LOADER_XCB"
GALLIUM_PIPE_LOADER_CLIENT_LIBS="$GALLIUM_PIPE_LOADER_LIBS
$GALLIUM_PIPE_LOADER_XCB_LIBS $LIBDRM_LIBS"
With these addressed the series is
Reviewed-by: Emil Velikov
> fi
> fi
>
> AC_SUBST([GALLIUM_PIPE_LOADER_DEFINES])
> AC_SUBST([GALLIUM_PIPE_LOADER_LIBS])
> +AC_SUBST([GALLIUM_PIPE_LOADER_CLIENT_DEFINES])
> +AC_SUBST([GALLIUM_PIPE_LOADER_CLIENT_LIBS])
> fi
>
> AM_CONDITIONAL(HAVE_I915_DRI, test x$HAVE_I915_DRI = xyes)
> diff --git a/src/gallium/auxiliary/pipe-loader/Makefile.am
> b/src/gallium/auxiliary/pipe-loader/Makefile.am
> index 8e4d034..4d8e264 100644
> --- a/src/gallium/auxiliary/pipe-loader/Makefile.am
> +++ b/src/gallium/auxiliary/pipe-loader/Makefile.am
> @@ -12,8 +12,9 @@ noinst_LTLIBRARIES =
>
> if HAVE_LOADER_GALLIUM
> noinst_LTLIBRARIES += libpipe_loader.la
> +noinst_LTLIBRARIES += libpipe_loader_client.la
>
> -libpipe_loader_la_SOURCES = \
> +COMMON_SOURCES = \
> pipe_loader.h \
> pipe_loader_priv.h \
> pipe_loader.c \
> @@ -22,10 +23,22 @@ libpipe_loader_la_SOURCES = \
> if HAVE_DRM_LOADER_GALLIUM
> AM_CFLAGS = $(LIBDRM_CFLAGS)
>
> -libpipe_loader_la_SOURCES += pipe_loader_drm.c
> +COMMON_SOURCES += pipe_loader_drm.c
>
> -libpipe_loader_la_LIBADD = \
> +COMMON_LIBADD = \
> $(top_builddir)/src/loader/libloader.la
>
> endif
> +
> +libpipe_loader_la_CFLAGS = -DSTANDALONE_LOADER \
> + $(AM_CFLAGS) $(AM_CPPFLAGS)
> +libpipe_loader_la_SOURCES = $(COMMON_SOURCES)
> +libpipe_loader_la_LIBADD = $(COMMON_LIBADD)
> +
> +libpipe_loader_client_la_CFLAGS = $(GALLIUM_PIPE_LOADER_CLIENT_DEFINES) \
> + $(AM_CFLAGS) $(AM_CPPFLAGS)
> +libpipe_loader_client_la_SOURCES = $(COMMON_SOURCES)
> +libpipe_loader_client_la_LIBADD = $(COMMON_LIBADD) \
> + $(GALLIUM_PIPE_LOADER_CLIENT_LIBS)
> +
> endif
> diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
> b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
> index 95a4f84..e53e8af 100644
> --- a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
> +++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
> @@ -47,7 +47,9 @@ static struct sw_winsys *(*backends[])() = {
> #ifdef HAVE_WINSYS_XLIB
> x11_sw_create,
> #endif
> +#ifndef STANDALONE_LOADER
> null_sw_create
> +#endif
> };
>
> int
> diff --git a/src/gallium/targets/gbm/Makef
[Mesa-dev] [Bug 67676] Transparent windows no longer work
https://bugs.freedesktop.org/show_bug.cgi?id=67676 --- Comment #6 from Sjoerd Simons --- Created attachment 93777 --> https://bugs.freedesktop.org/attachment.cgi?id=93777&action=edit Proposed patch egl_dri2: Allow both 24 and 32 bit X visuals for RGBA configs When using RGBA EGLConfigs allow both RGB and RGBA X visuals, such that application can decide whether they want to use RGBA (and have the compositor blend their windows). On my system with this change EGLConfigs with a 24 bit visual comes up first, as such applications blindly picking the first EGLConfig will still get an RGB X visual. Note that with this patch dri2_match_config only considers EGLConfigs to match iff their NativeVisualID also matches. Which is imho correct for X11, but i'm not sure if this is a valid thing to compare on other display systems. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/3] glx/apple: Fixed glx context memory leak in case of failure.
Perhaps Jeremy can review this patch...
On 02/10/2014 01:58 AM, Siavash Eliasi wrote:
> ---
> src/glx/apple/apple_glx_context.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/glx/apple/apple_glx_context.c
> b/src/glx/apple/apple_glx_context.c
> index 0bb25b4..8a6ded2 100644
> --- a/src/glx/apple/apple_glx_context.c
> +++ b/src/glx/apple/apple_glx_context.c
> @@ -142,6 +142,7 @@ apple_glx_create_context(void **ptr, Display * dpy, int
> screen,
> if (sharedac && !is_context_valid(sharedac)) {
>*errorptr = GLXBadContext;
>*x11errorptr = false;
> + free(ac);
>return true;
> }
>
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] configure: error out when building radeonsi without gallium-llvm
On Sat, Feb 08, 2014 at 03:52:29PM +, Emil Velikov wrote:
> --enable-gallium-llvm is required by radeonsi. Currently we
> check only for LLVM_VERSION_INT which is 0, whenever gallium-llvm
> is disabled explicitly.
>
> ./configure --with-gallium-drivers=r600,radeonsi --disable-gallium-llvm
>
I think this flag was originally intended to enable/disable llvmpipe,
but I can see the value in having a flag that guarantees you won't
pick up an unwanted LLVM dependencies.
> Signed-off-by: Emil Velikov
> ---
> configure.ac | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/configure.ac b/configure.ac
> index 8bf9b94..56d5c8e 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -1731,10 +1731,13 @@ gallium_require_drm_loader() {
> }
>
> radeon_llvm_check() {
> +if test "x$enable_gallium_llvm" != "xyes"; then
> +AC_MSG_ERROR([--enable_gallium_llvm is required when building $1])
> +fi
Did you mean to use underscores '_' in the configure option? Shouldn't it be:
--enable-gallium-llvm
-Tom
> LLVM_REQUIRED_VERSION_MAJOR="3"
> LLVM_REQUIRED_VERSION_MINOR="3"
> if test "$LLVM_VERSION_INT" -lt
> "${LLVM_REQUIRED_VERSION_MAJOR}0${LLVM_REQUIRED_VERSION_MINOR}"; then
> -AC_MSG_ERROR([LLVM
> $LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR or newer is
> required for r600g and radeonsi.])
> +AC_MSG_ERROR([LLVM
> $LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR or newer is
> required for $1])
> fi
> if test true && $LLVM_CONFIG --targets-built | grep -qvw 'R600' ; then
> AC_MSG_ERROR([LLVM R600 Target not enabled. You can enable it when
> building the LLVM
> @@ -1744,7 +1747,7 @@ radeon_llvm_check() {
> LLVM_COMPONENTS="${LLVM_COMPONENTS} r600 bitreader ipo"
> NEED_RADEON_LLVM=yes
> AC_CHECK_LIB([elf], [elf_memory], [ELF_LIB=-lelf],
> - [AC_MSG_ERROR([radeonsi and r600g require
> libelf when using LLVM])])
> + [AC_MSG_ERROR([$1 requires libelf when
> using LLVM])])
> }
>
> dnl Gallium drivers
> @@ -1797,7 +1800,7 @@ if test "x$with_gallium_drivers" != x; then
> gallium_require_drm_loader
> GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS r600"
> if test "x$enable_r600_llvm" = xyes -o "x$enable_opencl" = xyes;
> then
> -radeon_llvm_check
> +radeon_llvm_check "r600g"
> LLVM_COMPONENTS="${LLVM_COMPONENTS} bitreader asmparser"
> fi
> if test "x$enable_r600_llvm" = xyes; then
> @@ -1814,7 +1817,7 @@ if test "x$with_gallium_drivers" != x; then
> PKG_CHECK_MODULES([RADEON], [libdrm_radeon >=
> $LIBDRM_RADEON_REQUIRED])
> gallium_require_drm_loader
> GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS radeonsi"
> -radeon_llvm_check
> +radeon_llvm_check "radeonsi"
> gallium_check_st "radeon/drm" "radeonsi/dri" "" ""
> "radeonsi/vdpau" "radeonsi/omx"
> DRICOMMON_NEED_LIBDRM=yes
> ;;
> --
> 1.8.5.2
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 02/22] targets/pipe-loader: automake: drop obsolete version-script
On Sat, Feb 08, 2014 at 08:13:48PM +, Emil Velikov wrote: > On 08/02/14 17:53, Matt Turner wrote: > > The purpose of this version script looks to be related to static > > builds, but in your cover letter you said you were building with > > shared LLVM libraries. Does this affect static builds? > > > Unfortunately it does. For static builds the version script prevents us > to export _all_ of llvm api. > > This rule applies to pretty much everything that is linked with llvm, > and it's not confined within part of mesa. Other projects are > experiencing the same problem when static linking. > > I'm assuming that your idea is to keep the version scripts until the > whole mess is resolved. I kind of which that we drop the build option > and always use shared libraries/build. > > > Tom, Francisco > Considering that you guys are the primary people working with > llvm<>mesa would you have any comments on dropping mesa support for > static linking against llvm ? > I would like to continue to support static linking against llvm. -Tom ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/3] r300g/tests: Added missing fclose for FILE resource.
Reviewed-by: Tom Stellard
On Mon, Feb 10, 2014 at 01:28:14PM +0330, Siavash Eliasi wrote:
> ---
> src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c
> b/src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c
> index b4e30d8..239a762 100644
> --- a/src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c
> +++ b/src/gallium/drivers/r300/compiler/tests/rc_test_helpers.c
> @@ -557,6 +557,7 @@ unsigned load_program(
> if (last_char && last_char != '\n') {
> fprintf(stderr, "Error line cannot be longer than 100 "
> "characters:\n%s\n", line);
> + fclose(file);
> return 0;
> }
>
> @@ -605,5 +606,7 @@ unsigned load_program(
> // XXX: Parse immediates from the file.
> add_instruction(c, test->input[i]);
> }
> +
> + fclose(file);
> return 1;
> }
> --
> 1.8.5.4
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] configure: error out when building radeonsi without gallium-llvm
--enable-gallium-llvm is required by radeonsi. Currently we
check only for LLVM_VERSION_INT which is 0, whenever gallium-llvm
is disabled explicitly.
./configure --with-gallium-drivers=r600,radeonsi --disable-gallium-llvm
v2: Correct typo in error message. Spotted by Tom Stellard
Signed-off-by: Emil Velikov
---
configure.ac | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/configure.ac b/configure.ac
index 8bf9b94..eeecfa7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1731,10 +1731,13 @@ gallium_require_drm_loader() {
}
radeon_llvm_check() {
+if test "x$enable_gallium_llvm" != "xyes"; then
+AC_MSG_ERROR([--enable-gallium-llvm is required when building $1])
+fi
LLVM_REQUIRED_VERSION_MAJOR="3"
LLVM_REQUIRED_VERSION_MINOR="3"
if test "$LLVM_VERSION_INT" -lt
"${LLVM_REQUIRED_VERSION_MAJOR}0${LLVM_REQUIRED_VERSION_MINOR}"; then
-AC_MSG_ERROR([LLVM
$LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR or newer is required
for r600g and radeonsi.])
+AC_MSG_ERROR([LLVM
$LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR or newer is required
for $1])
fi
if test true && $LLVM_CONFIG --targets-built | grep -qvw 'R600' ; then
AC_MSG_ERROR([LLVM R600 Target not enabled. You can enable it when
building the LLVM
@@ -1744,7 +1747,7 @@ radeon_llvm_check() {
LLVM_COMPONENTS="${LLVM_COMPONENTS} r600 bitreader ipo"
NEED_RADEON_LLVM=yes
AC_CHECK_LIB([elf], [elf_memory], [ELF_LIB=-lelf],
- [AC_MSG_ERROR([radeonsi and r600g require
libelf when using LLVM])])
+ [AC_MSG_ERROR([$1 requires libelf when using
LLVM])])
}
dnl Gallium drivers
@@ -1797,7 +1800,7 @@ if test "x$with_gallium_drivers" != x; then
gallium_require_drm_loader
GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS r600"
if test "x$enable_r600_llvm" = xyes -o "x$enable_opencl" = xyes;
then
-radeon_llvm_check
+radeon_llvm_check "r600g"
LLVM_COMPONENTS="${LLVM_COMPONENTS} bitreader asmparser"
fi
if test "x$enable_r600_llvm" = xyes; then
@@ -1814,7 +1817,7 @@ if test "x$with_gallium_drivers" != x; then
PKG_CHECK_MODULES([RADEON], [libdrm_radeon >=
$LIBDRM_RADEON_REQUIRED])
gallium_require_drm_loader
GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS radeonsi"
-radeon_llvm_check
+radeon_llvm_check "radeonsi"
gallium_check_st "radeon/drm" "radeonsi/dri" "" ""
"radeonsi/vdpau" "radeonsi/omx"
DRICOMMON_NEED_LIBDRM=yes
;;
--
1.8.5.4
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] configure: error out when building radeonsi without gallium-llvm
On Mon, Feb 10, 2014 at 04:37:31PM +, Emil Velikov wrote:
> --enable-gallium-llvm is required by radeonsi. Currently we
> check only for LLVM_VERSION_INT which is 0, whenever gallium-llvm
> is disabled explicitly.
>
> ./configure --with-gallium-drivers=r600,radeonsi --disable-gallium-llvm
>
> v2: Correct typo in error message. Spotted by Tom Stellard
>
> Signed-off-by: Emil Velikov
Reviewed-by: Tom Stellard
> ---
> configure.ac | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/configure.ac b/configure.ac
> index 8bf9b94..eeecfa7 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -1731,10 +1731,13 @@ gallium_require_drm_loader() {
> }
>
> radeon_llvm_check() {
> +if test "x$enable_gallium_llvm" != "xyes"; then
> +AC_MSG_ERROR([--enable-gallium-llvm is required when building $1])
> +fi
> LLVM_REQUIRED_VERSION_MAJOR="3"
> LLVM_REQUIRED_VERSION_MINOR="3"
> if test "$LLVM_VERSION_INT" -lt
> "${LLVM_REQUIRED_VERSION_MAJOR}0${LLVM_REQUIRED_VERSION_MINOR}"; then
> -AC_MSG_ERROR([LLVM
> $LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR or newer is
> required for r600g and radeonsi.])
> +AC_MSG_ERROR([LLVM
> $LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR or newer is
> required for $1])
> fi
> if test true && $LLVM_CONFIG --targets-built | grep -qvw 'R600' ; then
> AC_MSG_ERROR([LLVM R600 Target not enabled. You can enable it when
> building the LLVM
> @@ -1744,7 +1747,7 @@ radeon_llvm_check() {
> LLVM_COMPONENTS="${LLVM_COMPONENTS} r600 bitreader ipo"
> NEED_RADEON_LLVM=yes
> AC_CHECK_LIB([elf], [elf_memory], [ELF_LIB=-lelf],
> - [AC_MSG_ERROR([radeonsi and r600g require
> libelf when using LLVM])])
> + [AC_MSG_ERROR([$1 requires libelf when
> using LLVM])])
> }
>
> dnl Gallium drivers
> @@ -1797,7 +1800,7 @@ if test "x$with_gallium_drivers" != x; then
> gallium_require_drm_loader
> GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS r600"
> if test "x$enable_r600_llvm" = xyes -o "x$enable_opencl" = xyes;
> then
> -radeon_llvm_check
> +radeon_llvm_check "r600g"
> LLVM_COMPONENTS="${LLVM_COMPONENTS} bitreader asmparser"
> fi
> if test "x$enable_r600_llvm" = xyes; then
> @@ -1814,7 +1817,7 @@ if test "x$with_gallium_drivers" != x; then
> PKG_CHECK_MODULES([RADEON], [libdrm_radeon >=
> $LIBDRM_RADEON_REQUIRED])
> gallium_require_drm_loader
> GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS radeonsi"
> -radeon_llvm_check
> +radeon_llvm_check "radeonsi"
> gallium_check_st "radeon/drm" "radeonsi/dri" "" ""
> "radeonsi/vdpau" "radeonsi/omx"
> DRICOMMON_NEED_LIBDRM=yes
> ;;
> --
> 1.8.5.4
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/3] pipe-loader: add pipe loader for freedreno/msm
There should be one called pipe_freedreno and the pipe driver loader should support sth. like: if ((strcmp(dev->driver_name, "kgsl") == 0) || (strcmp(dev->driver_name, "msm") == 0)) dev->driver_name = "freedreno"; in pipe_loader_find_module ... ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74803] New: Cogs shadows are broken
https://bugs.freedesktop.org/show_bug.cgi?id=74803 Priority: medium Bug ID: 74803 Assignee: mesa-dev@lists.freedesktop.org Summary: Cogs shadows are broken Severity: normal Classification: Unclassified OS: Linux (All) Reporter: funkydud...@hotmail.co.uk Hardware: x86-64 (AMD64) Status: NEW Version: git Component: Mesa core Product: Mesa Created attachment 93791 --> https://bugs.freedesktop.org/attachment.cgi?id=93791&action=edit Cogs shadow corruption When enabling shadows on Cogs, the game looks like the attached screenshot, shadows become corrupt. Laptop Resolution: 1280x800 GPU: HD2600 Mobility OS: Ubuntu 13.10 Kernel: 3.13 Running the latest builds of Mesa thanks to the oibaf repository. Disabling shadows allows me to play the game fine. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74803] Cogs shadows are broken
https://bugs.freedesktop.org/show_bug.cgi?id=74803 funkydude changed: What|Removed |Added Attachment #93791|0 |1 is obsolete|| --- Comment #1 from funkydude --- Created attachment 93792 --> https://bugs.freedesktop.org/attachment.cgi?id=93792&action=edit Cogs shadow corruption Fixed screenshot. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Don't call abort() on an unknown device.
On 02/10/2014 01:54 AM, Kenneth Graunke wrote: > If we don't recognize the PCI ID, we can't reasonably load the driver. > However, calling abort() is quite rude - it means the application that > tried to initialize us (possibly the X server) can't continue via > fallback paths. We already have a more polite mechanism - failing to > create the context. So, just use that. > > While we're at it, improve the error message. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73024 > Signed-off-by: Kenneth Graunke Come on! "Hulk SMASH!" is a fine error path. :) Reviewed-by: Ian Romanick > --- > src/mesa/drivers/dri/i965/brw_device_info.c | 4 ++-- > src/mesa/drivers/dri/i965/intel_screen.c| 2 ++ > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c > b/src/mesa/drivers/dri/i965/brw_device_info.c > index eb1df79..d931091 100644 > --- a/src/mesa/drivers/dri/i965/brw_device_info.c > +++ b/src/mesa/drivers/dri/i965/brw_device_info.c > @@ -229,7 +229,7 @@ brw_get_device_info(int devid) > #define CHIPSET(id, family, name) case id: return &brw_device_info_##family; > #include "pci_ids/i965_pci_ids.h" > default: > - fprintf(stderr, "Unknown Intel device."); > - abort(); > + fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", > devid); > + return NULL; > } > } > diff --git a/src/mesa/drivers/dri/i965/intel_screen.c > b/src/mesa/drivers/dri/i965/intel_screen.c > index 6ab3609..acdb5f3 100644 > --- a/src/mesa/drivers/dri/i965/intel_screen.c > +++ b/src/mesa/drivers/dri/i965/intel_screen.c > @@ -1328,6 +1328,8 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) > > intelScreen->deviceID = > drm_intel_bufmgr_gem_get_devid(intelScreen->bufmgr); > intelScreen->devinfo = brw_get_device_info(intelScreen->deviceID); > + if (!intelScreen->devinfo) > + return false; > > intelScreen->hw_must_use_separate_stencil = intelScreen->devinfo->gen >= > 7; > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/3] pipe-loader: add pipe loader for freedreno/msm
On Mon, Feb 10, 2014 at 12:30 PM, Johannes Obermayr wrote: > There should be one called pipe_freedreno and the pipe driver loader should > support sth. like: > >if ((strcmp(dev->driver_name, "kgsl") == 0) || (strcmp(dev->driver_name, > "msm") == 0)) > dev->driver_name = "freedreno"; > > in pipe_loader_find_module ... *really*? That seems even more ugly.. fwiw, I don't expect kgsl to stick around forever.. it is mainly a temporary convenience for folks with tablets/phones, since drm/msm is missing some features (mainly dsi panel support). We don't control the kgsl kernel interface. Eventually qcom will break it badly enough, and drm/msm will have gained enough features, that we decide kgsl is not worth keeping. BR, -R > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74803] Cogs shadows are broken
https://bugs.freedesktop.org/show_bug.cgi?id=74803 --- Comment #2 from Alex Deucher --- Is this a regression? If so, can you bisect? Also, please attach your xorg log and glxinfo and dmesg output. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] R600/SI: Completely Disable TypeRewriter on compute
From: Tom Stellard
---
lib/Target/R600/SITypeRewriter.cpp | 6 +++---
test/CodeGen/R600/bitcast.ll | 9 +
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/lib/Target/R600/SITypeRewriter.cpp
b/lib/Target/R600/SITypeRewriter.cpp
index b01a443..7de7b1f 100644
--- a/lib/Target/R600/SITypeRewriter.cpp
+++ b/lib/Target/R600/SITypeRewriter.cpp
@@ -69,11 +69,11 @@ bool SITypeRewriter::runOnFunction(Function &F) {
StringRef Str = A.getValueAsString();
Str.getAsInteger(0, ShaderType);
}
- if (ShaderType != ShaderType::COMPUTE) {
-visit(F);
- }
+ if (ShaderType == ShaderType::COMPUTE)
+return false;
visit(F);
+ visit(F);
return false;
}
diff --git a/test/CodeGen/R600/bitcast.ll b/test/CodeGen/R600/bitcast.ll
index bccc416..5bfc008 100644
--- a/test/CodeGen/R600/bitcast.ll
+++ b/test/CodeGen/R600/bitcast.ll
@@ -19,3 +19,12 @@ declare void @llvm.SI.export(i32, i32, i32, i32, i32, float,
float, float, float
attributes #0 = { "ShaderType"="0" }
+; CHECK-LABEL: @i8ptr_v16i8ptr
+; CHECK: S_ENDPGM
+define void @i8ptr_v16i8ptr(<16 x i8> addrspace(1)* %out, i8 addrspace(1)*
%in) {
+entry:
+ %0 = bitcast i8 addrspace(1)* %in to <16 x i8> addrspace(1)*
+ %1 = load <16 x i8> addrspace(1)* %0
+ store <16 x i8> %1, <16 x i8> addrspace(1)* %out
+ ret void
+}
--
1.8.1.5
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCHv2 3/4] st/xa: missing handle type
From: Rob Clark
DRM_API_HANDLE_TYPE_SHARED is zero, so doesn't actually fix anything.
But we shouldn't rely on SHARED handle type being zero.
Signed-off-by: Rob Clark
---
src/gallium/state_trackers/xa/xa_tracker.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/state_trackers/xa/xa_tracker.c
b/src/gallium/state_trackers/xa/xa_tracker.c
index 6943a29..01db945 100644
--- a/src/gallium/state_trackers/xa/xa_tracker.c
+++ b/src/gallium/state_trackers/xa/xa_tracker.c
@@ -370,6 +370,7 @@ xa_surface_from_handle(struct xa_tracker *xa,
{
struct winsys_handle whandle;
memset(&whandle, 0, sizeof(whandle));
+whandle.type = DRM_API_HANDLE_TYPE_SHARED;
whandle.handle = handle;
whandle.stride = stride;
return surface_create(xa, width, height, depth, stype, xa_format, flags,
&whandle);
--
1.8.5.3
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCHv2 4/4] pipe-loader: add pipe loader for freedreno/msm
From: Rob Clark
Signed-off-by: Rob Clark
---
src/gallium/targets/pipe-loader/Makefile.am | 16
src/gallium/targets/pipe-loader/pipe_msm.c | 21 +
2 files changed, 37 insertions(+)
create mode 100644 src/gallium/targets/pipe-loader/pipe_msm.c
diff --git a/src/gallium/targets/pipe-loader/Makefile.am
b/src/gallium/targets/pipe-loader/Makefile.am
index 97733c1..8a0f254 100644
--- a/src/gallium/targets/pipe-loader/Makefile.am
+++ b/src/gallium/targets/pipe-loader/Makefile.am
@@ -132,6 +132,22 @@ pipe_radeonsi_la_LDFLAGS += $(LLVM_LDFLAGS)
endif
endif
+if HAVE_GALLIUM_FREEDRENO
+pipe_LTLIBRARIES += pipe_msm.la
+pipe_msm_la_SOURCES = pipe_msm.c
+nodist_EXTRA_pipe_msm_la_SOURCES = dummy.cpp
+pipe_msm_la_LIBADD = \
+ $(PIPE_LIBS) \
+ $(top_builddir)/src/gallium/winsys/freedreno/drm/libfreedrenodrm.la \
+ $(top_builddir)/src/gallium/drivers/freedreno/libfreedreno.la \
+ $(LIBDRM_LIBS)
+pipe_msm_la_LDFLAGS = -no-undefined -avoid-version -module
+if HAVE_MESA_LLVM
+pipe_msm_la_LIBADD += $(LLVM_LIBS)
+pipe_msm_la_LDFLAGS += $(LLVM_LDFLAGS)
+endif
+endif
+
if HAVE_GALLIUM_SVGA
pipe_LTLIBRARIES += pipe_vmwgfx.la
pipe_vmwgfx_la_SOURCES = pipe_vmwgfx.c
diff --git a/src/gallium/targets/pipe-loader/pipe_msm.c
b/src/gallium/targets/pipe-loader/pipe_msm.c
new file mode 100644
index 000..76e4023
--- /dev/null
+++ b/src/gallium/targets/pipe-loader/pipe_msm.c
@@ -0,0 +1,21 @@
+
+#include "target-helpers/inline_debug_helper.h"
+#include "state_tracker/drm_driver.h"
+#include "freedreno/drm/freedreno_drm_public.h"
+
+static struct pipe_screen *
+create_screen(int fd)
+{
+ struct pipe_screen *screen;
+
+ screen = fd_drm_screen_create(fd);
+ if (!screen)
+ return NULL;
+
+ screen = debug_screen_wrap(screen);
+
+ return screen;
+}
+
+PUBLIC
+DRM_DRIVER_DESCRIPTOR("msm", "freedreno", create_screen, NULL)
--
1.8.5.3
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCHv2 0/4] enable XA for freedreno
From: Rob Clark Original patchset: http://lists.freedesktop.org/archives/mesa-dev/2014-February/053632.html v1: original v2: moves xa target into targets/xa, and fixes various issues spotted by Emil Rob Clark (4): pipe-loader: split out "client" version st/xa: use pipe-loader to get screen st/xa: missing handle type pipe-loader: add pipe loader for freedreno/msm configure.ac | 23 ++-- src/gallium/auxiliary/pipe-loader/Makefile.am | 24 ++-- src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 2 + src/gallium/state_trackers/xa/Makefile.am | 1 + src/gallium/state_trackers/xa/xa_priv.h| 1 + src/gallium/state_trackers/xa/xa_tracker.c | 10 +++- src/gallium/targets/Makefile.am| 8 +-- src/gallium/targets/gbm/Makefile.am| 4 +- src/gallium/targets/opencl/Makefile.am | 4 +- src/gallium/targets/pipe-loader/Makefile.am| 16 + src/gallium/targets/pipe-loader/pipe_msm.c | 21 +++ src/gallium/targets/xa-vmwgfx/Makefile.am | 61 --- src/gallium/targets/xa-vmwgfx/vmw_target.c | 26 - src/gallium/targets/xa-vmwgfx/xatracker.pc.in | 9 --- src/gallium/targets/xa/Makefile.am | 68 ++ src/gallium/targets/xa/xa.c| 49 src/gallium/targets/xa/xa.h| 37 src/gallium/targets/xa/xatracker.pc.in | 9 +++ src/gallium/tests/trivial/Makefile.am | 4 +- 19 files changed, 260 insertions(+), 117 deletions(-) create mode 100644 src/gallium/targets/pipe-loader/pipe_msm.c delete mode 100644 src/gallium/targets/xa-vmwgfx/Makefile.am delete mode 100644 src/gallium/targets/xa-vmwgfx/vmw_target.c delete mode 100644 src/gallium/targets/xa-vmwgfx/xatracker.pc.in create mode 100644 src/gallium/targets/xa/Makefile.am create mode 100644 src/gallium/targets/xa/xa.c create mode 100644 src/gallium/targets/xa/xa.h create mode 100644 src/gallium/targets/xa/xatracker.pc.in -- 1.8.5.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCHv2 2/4] st/xa: use pipe-loader to get screen
From: Rob Clark
This lets multiple gallium drivers use XA.
Signed-off-by: Rob Clark
---
configure.ac | 9 ++--
src/gallium/state_trackers/xa/Makefile.am | 1 +
src/gallium/state_trackers/xa/xa_priv.h | 1 +
src/gallium/state_trackers/xa/xa_tracker.c| 9 +++-
src/gallium/targets/Makefile.am | 8 ++--
src/gallium/targets/xa-vmwgfx/Makefile.am | 61
src/gallium/targets/xa-vmwgfx/vmw_target.c| 26 --
src/gallium/targets/xa-vmwgfx/xatracker.pc.in | 9
src/gallium/targets/xa/Makefile.am| 68 +++
src/gallium/targets/xa/xa.c | 49 +++
src/gallium/targets/xa/xa.h | 37 +++
src/gallium/targets/xa/xatracker.pc.in| 9
12 files changed, 182 insertions(+), 105 deletions(-)
delete mode 100644 src/gallium/targets/xa-vmwgfx/Makefile.am
delete mode 100644 src/gallium/targets/xa-vmwgfx/vmw_target.c
delete mode 100644 src/gallium/targets/xa-vmwgfx/xatracker.pc.in
create mode 100644 src/gallium/targets/xa/Makefile.am
create mode 100644 src/gallium/targets/xa/xa.c
create mode 100644 src/gallium/targets/xa/xa.h
create mode 100644 src/gallium/targets/xa/xatracker.pc.in
diff --git a/configure.ac b/configure.ac
index cba6301..29ca954 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1270,6 +1270,7 @@ dnl XA configuration
dnl
if test "x$enable_xa" = xyes; then
GALLIUM_STATE_TRACKERS_DIRS="xa $GALLIUM_STATE_TRACKERS_DIRS"
+enable_gallium_loader=yes
fi
AM_CONDITIONAL(HAVE_ST_XA, test "x$enable_xa" = xyes)
@@ -1743,7 +1744,7 @@ if test "x$with_gallium_drivers" != x; then
xsvga)
HAVE_GALLIUM_SVGA=yes
GALLIUM_DRIVERS_DIRS="$GALLIUM_DRIVERS_DIRS svga softpipe"
-gallium_check_st "svga/drm" "dri-vmwgfx" "xa-vmwgfx"
+gallium_check_st "svga/drm" "dri-vmwgfx" ""
;;
xi915)
HAVE_GALLIUM_I915=yes
@@ -1962,7 +1963,7 @@ AC_SUBST([XVMC_MAJOR], 1)
AC_SUBST([XVMC_MINOR], 0)
AC_SUBST([XA_MAJOR], 2)
-AC_SUBST([XA_MINOR], 1)
+AC_SUBST([XA_MINOR], 2)
AC_SUBST([XA_TINY], 0)
AC_SUBST([XA_VERSION], "$XA_MAJOR.$XA_MINOR.$XA_TINY")
@@ -2035,6 +2036,8 @@ AC_CONFIG_FILES([Makefile
src/gallium/targets/egl-static/Makefile
src/gallium/targets/gbm/Makefile
src/gallium/targets/opencl/Makefile
+ src/gallium/targets/xa/Makefile
+ src/gallium/targets/xa/xatracker.pc
src/gallium/targets/osmesa/Makefile
src/gallium/targets/osmesa/osmesa.pc
src/gallium/targets/pipe-loader/Makefile
@@ -2046,8 +2049,6 @@ AC_CONFIG_FILES([Makefile
src/gallium/targets/r600/xvmc/Makefile
src/gallium/targets/libgl-xlib/Makefile
src/gallium/targets/vdpau-nouveau/Makefile
- src/gallium/targets/xa-vmwgfx/Makefile
- src/gallium/targets/xa-vmwgfx/xatracker.pc
src/gallium/targets/xvmc-nouveau/Makefile
src/gallium/tests/trivial/Makefile
src/gallium/tests/unit/Makefile
diff --git a/src/gallium/state_trackers/xa/Makefile.am
b/src/gallium/state_trackers/xa/Makefile.am
index 7d0b366..af79ccd 100644
--- a/src/gallium/state_trackers/xa/Makefile.am
+++ b/src/gallium/state_trackers/xa/Makefile.am
@@ -29,6 +29,7 @@ AM_CFLAGS = \
$(VISIBILITY_CFLAGS)
AM_CPPFLAGS = \
+ -I$(top_srcdir)/src/gallium/targets/xa \
-I$(top_srcdir)/src/gallium/ \
-I$(top_srcdir)/src/gallium/winsys \
-I$(top_srcdir)/src/gallium/drivers
diff --git a/src/gallium/state_trackers/xa/xa_priv.h
b/src/gallium/state_trackers/xa/xa_priv.h
index ee182e7..b99c214 100644
--- a/src/gallium/state_trackers/xa/xa_priv.h
+++ b/src/gallium/state_trackers/xa/xa_priv.h
@@ -74,6 +74,7 @@ struct xa_tracker {
unsigned int format_map[XA_LAST_SURFACE_TYPE][2];
int d_depth_bits_last;
int ds_depth_bits_last;
+struct pipe_loader_device *dev;
struct pipe_screen *screen;
struct xa_context *default_ctx;
};
diff --git a/src/gallium/state_trackers/xa/xa_tracker.c
b/src/gallium/state_trackers/xa/xa_tracker.c
index cda6501..6943a29 100644
--- a/src/gallium/state_trackers/xa/xa_tracker.c
+++ b/src/gallium/state_trackers/xa/xa_tracker.c
@@ -28,8 +28,10 @@
#include "xa_tracker.h"
#include "xa_priv.h"
+#include "xa.h"
#include "pipe/p_state.h"
#include "pipe/p_format.h"
+#include "pipe-loader/pipe_loader.h"
#include "state_tracker/drm_driver.h"
#include "util/u_inlines.h"
@@ -143,7 +145,9 @@ xa_tracker_create(int drm_fd)
if (!xa)
return NULL;
-xa->screen = driver_descriptor.create_screen(drm_fd);
+xa->dev = xa_pipe_probe(drm_fd);
+if (xa->dev)
+ xa->screen = xa_pipe_create_screen(xa->dev);
if (!xa->screen)
goto out_no_screen;
@@ -190,6 +194,8 @@ xa_tracke
[Mesa-dev] [PATCHv2 1/4] pipe-loader: split out "client" version
From: Rob Clark
Build two versions of pipe-loader, with only the client version linking
in x11 client side dependencies. This will allow the XA state tracker
to use pipe-loader.
Signed-off-by: Rob Clark
---
configure.ac | 14 +++--
src/gallium/auxiliary/pipe-loader/Makefile.am | 24 ++
src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 2 ++
src/gallium/targets/gbm/Makefile.am| 4 ++--
src/gallium/targets/opencl/Makefile.am | 4 ++--
src/gallium/tests/trivial/Makefile.am | 4 ++--
6 files changed, 40 insertions(+), 12 deletions(-)
diff --git a/configure.ac b/configure.ac
index ba158e8..cba6301 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1895,6 +1895,11 @@ AM_CONDITIONAL(NEED_GALLIUM_LLVMPIPE_DRIVER, test
"x$HAVE_GALLIUM_I915" = xyes -
"x$HAVE_GALLIUM_SOFTPIPE" =
xyes \
&& test "x$MESA_LLVM" = x1)
+# NOTE: anything using xcb or other client side libs ends up in separate
+# _CLIENT variables. The pipe loader is built in two variants,
+# one that is standalone and does not link any x client libs (for
+# use by XA tracker in particular, but could be used in any case
+# where communication with xserver is not desired).
if test "x$enable_gallium_loader" = xyes; then
GALLIUM_WINSYS_DIRS="$GALLIUM_WINSYS_DIRS sw/null"
@@ -1903,13 +1908,18 @@ if test "x$enable_gallium_loader" = xyes; then
PKG_CHECK_MODULES([GALLIUM_PIPE_LOADER_XCB], [xcb xcb-dri2],
pipe_loader_have_xcb=yes, pipe_loader_have_xcb=no)
if test "x$pipe_loader_have_xcb" = xyes; then
-GALLIUM_PIPE_LOADER_DEFINES="$GALLIUM_PIPE_LOADER_DEFINES
-DHAVE_PIPE_LOADER_XCB"
-GALLIUM_PIPE_LOADER_LIBS="$GALLIUM_PIPE_LOADER_LIBS
$GALLIUM_PIPE_LOADER_XCB_LIBS $LIBDRM_LIBS"
+
GALLIUM_PIPE_LOADER_CLIENT_DEFINES="$GALLIUM_PIPE_LOADER_CLIENT_DEFINES
-DHAVE_PIPE_LOADER_XCB"
+GALLIUM_PIPE_LOADER_CLIENT_LIBS="$GALLIUM_PIPE_LOADER_CLIENT_LIBS
$GALLIUM_PIPE_LOADER_XCB_LIBS $LIBDRM_LIBS"
fi
fi
+GALLIUM_PIPE_LOADER_CLIENT_DEFINES="$GALLIUM_PIPE_LOADER_CLIENT_DEFINES
$GALLIUM_PIPE_LOADER_DEFINES"
+GALLIUM_PIPE_LOADER_CLIENT_LIBS="$GALLIUM_PIPE_LOADER_CLIENT_LIBS
$GALLIUM_PIPE_LOADER_LIBS"
+
AC_SUBST([GALLIUM_PIPE_LOADER_DEFINES])
AC_SUBST([GALLIUM_PIPE_LOADER_LIBS])
+AC_SUBST([GALLIUM_PIPE_LOADER_CLIENT_DEFINES])
+AC_SUBST([GALLIUM_PIPE_LOADER_CLIENT_LIBS])
fi
AM_CONDITIONAL(HAVE_I915_DRI, test x$HAVE_I915_DRI = xyes)
diff --git a/src/gallium/auxiliary/pipe-loader/Makefile.am
b/src/gallium/auxiliary/pipe-loader/Makefile.am
index 8e4d034..72b4798 100644
--- a/src/gallium/auxiliary/pipe-loader/Makefile.am
+++ b/src/gallium/auxiliary/pipe-loader/Makefile.am
@@ -1,7 +1,6 @@
AUTOMAKE_OPTIONS = subdir-objects
AM_CPPFLAGS = $(DEFINES) \
- $(GALLIUM_PIPE_LOADER_DEFINES) \
-I$(top_srcdir)/include \
-I$(top_srcdir)/src/loader \
-I$(top_srcdir)/src/gallium/include \
@@ -12,8 +11,9 @@ noinst_LTLIBRARIES =
if HAVE_LOADER_GALLIUM
noinst_LTLIBRARIES += libpipe_loader.la
+noinst_LTLIBRARIES += libpipe_loader_client.la
-libpipe_loader_la_SOURCES = \
+COMMON_SOURCES = \
pipe_loader.h \
pipe_loader_priv.h \
pipe_loader.c \
@@ -22,10 +22,26 @@ libpipe_loader_la_SOURCES = \
if HAVE_DRM_LOADER_GALLIUM
AM_CFLAGS = $(LIBDRM_CFLAGS)
-libpipe_loader_la_SOURCES += pipe_loader_drm.c
+COMMON_SOURCES += pipe_loader_drm.c
-libpipe_loader_la_LIBADD = \
+COMMON_LIBADD = \
$(top_builddir)/src/loader/libloader.la
endif
+
+libpipe_loader_la_CFLAGS = \
+ -DSTANDALONE_LOADER \
+ $(GALLIUM_PIPE_LOADER_DEFINES) \
+ $(AM_CFLAGS) $(AM_CPPFLAGS)
+libpipe_loader_la_SOURCES = $(COMMON_SOURCES)
+libpipe_loader_la_LIBADD = $(COMMON_LIBADD) \
+ $(GALLIUM_PIPE_LOADER_LIBS)
+
+libpipe_loader_client_la_CFLAGS = \
+ $(GALLIUM_PIPE_LOADER_CLIENT_DEFINES) \
+ $(AM_CFLAGS) $(AM_CPPFLAGS)
+libpipe_loader_client_la_SOURCES = $(COMMON_SOURCES)
+libpipe_loader_client_la_LIBADD = $(COMMON_LIBADD) \
+ $(GALLIUM_PIPE_LOADER_CLIENT_LIBS)
+
endif
diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
index 95a4f84..e53e8af 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
@@ -47,7 +47,9 @@ static struct sw_winsys *(*backends[])() = {
#ifdef HAVE_WINSYS_XLIB
x11_sw_create,
#endif
+#ifndef STANDALONE_LOADER
null_sw_create
+#endif
};
int
diff --git a/src/gallium/targets/gbm/Makefile.am
b/src/gallium/targets/gbm/Makefile.am
index 4299d07..30a3427 100644
--- a/src/gallium/targets/gbm/Makefile.am
+++ b/src/gallium/targets/gbm/Makefile.am
@@ -42,8 +42,8 @@ gbm_LTLIBRARIE
[Mesa-dev] [Bug 74803] Cogs shadows are broken
https://bugs.freedesktop.org/show_bug.cgi?id=74803 --- Comment #3 from funkydude --- No idea if it's a regression. The first time I played this game on Linux was ~2 weeks ago and the issue has been there since that time. Shadows are on by default, and this is a pretty old game. My guess is it is a regression or it would have been noticed previously. I'm not sure what bisect is or how to perform one. I'm also not sure where the xorg log is. Is that constantly logging? Should I delete the file and launch the game to create a small one if so? glxinfo and dmesg are too large, how do I dump them to a file? -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74803] Cogs shadows are broken
https://bugs.freedesktop.org/show_bug.cgi?id=74803 --- Comment #4 from Alex Deucher --- Just redirect the output to a file: glxinfo > glxinfo.txt dmesg > dmesg.txt The xorg log location is usually /var/log/Xorg.0.log. Don't worry about deleting it. It gets overwritten each time you start X. Google for "git bisect howto" to see how to use git to bisect a regression. If you are not comfortable with that, can you try older driver releases and see if you can narrow down which one caused the problem? -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/7] i965/blorp: refactor assertions for tile offset alignments
There are only two callers for compute_tile_offsets() and both require the exact same constraints for the tile offsets. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 6 ++ src/mesa/drivers/dri/i965/gen6_blorp.cpp | 5 - src/mesa/drivers/dri/i965/gen7_blorp.cpp | 5 - 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 76537c8..7bdf83a 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -148,6 +148,12 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, *tile_x = x_offset & mask_x; *tile_y = y_offset & mask_y; + /* Note that the low bits of these fields are missing, so +* there's the possibility of getting in trouble. +*/ + assert(*tile_x % 4 == 0); + assert(*tile_y % 2 == 0); + return intel_region_get_aligned_offset(region, x_offset & ~mask_x, y_offset & ~mask_y, map_stencil_as_y_tiled); diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 4222fa8..8d45d57 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -399,11 +399,6 @@ gen6_blorp_emit_surface_state(struct brw_context *brw, surf[4] = brw_get_surface_num_multisamples(surface->num_samples); - /* Note that the low bits of these fields are missing, so -* there's the possibility of getting in trouble. -*/ - assert(tile_x % 4 == 0); - assert(tile_y % 2 == 0); surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | (surface->mt->align_h == 4 ? diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 4bf9396..f067b0b 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -178,11 +178,6 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, surf[1] = surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset64; - /* Note that the low bits of these fields are missing, so -* there's the possibility of getting in trouble. -*/ - assert(tile_x % 4 == 0); - assert(tile_y % 2 == 0); surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) | SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) | SET_FIELD(mocs, GEN7_SURFACE_MOCS); -- 1.8.3.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/7] i965/blorp: split calculations of page and tile offsets
These will be handled separately in the coming patches.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 21 +
src/mesa/drivers/dri/i965/brw_blorp.h| 3 ++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 4 ++--
4 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 7bdf83a..6fc215f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -135,14 +135,13 @@ brw_blorp_surface_info::set(struct brw_context *brw,
* adjusted to account for Y vs. W tiling differences. So we compute it
* directly from the adjusted offsets.
*/
-uint32_t
+void
brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
uint32_t *tile_y) const
{
- struct intel_region *region = mt->region;
uint32_t mask_x, mask_y;
- intel_region_get_tile_masks(region, &mask_x, &mask_y,
+ intel_region_get_tile_masks(mt->region, &mask_x, &mask_y,
map_stencil_as_y_tiled);
*tile_x = x_offset & mask_x;
@@ -153,8 +152,22 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
*tile_x,
*/
assert(*tile_x % 4 == 0);
assert(*tile_y % 2 == 0);
+}
+
+
+/**
+ * Resolve the page aligned offset from the base address excluding the
+ * remaining part within the tile.
+ */
+uint32_t
+brw_blorp_surface_info::compute_page_offset() const
+{
+ uint32_t mask_x, mask_y;
+
+ intel_region_get_tile_masks(mt->region, &mask_x, &mask_y,
+ map_stencil_as_y_tiled);
- return intel_region_get_aligned_offset(region, x_offset & ~mask_x,
+ return intel_region_get_aligned_offset(mt->region, x_offset & ~mask_x,
y_offset & ~mask_y,
map_stencil_as_y_tiled);
}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index db41497..bbd6481 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -130,7 +130,8 @@ public:
unsigned int level, unsigned int layer,
bool is_render_target);
- uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
+ uint32_t compute_page_offset() const;
+ void compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
/* Setting this flag indicates that the buffer's contents are W-tiled
* stencil data, but the surface state should be set up for Y tiled
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 8d45d57..75900b8 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -380,8 +380,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT);
/* reloc */
- surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) +
- region->bo->offset64);
+ surf[1] = surface->compute_page_offset() + region->bo->offset64;
surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
(width - 1) << BRW_SURFACE_WIDTH_SHIFT |
@@ -399,6 +398,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
surf[4] = brw_get_surface_num_multisamples(surface->num_samples);
+ surface->compute_tile_offsets(&tile_x, &tile_y);
surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
(tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
(surface->mt->align_h == 4 ?
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index f067b0b..f6afab2 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -175,9 +175,9 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
/* reloc */
- surf[1] =
- surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset64;
+ surf[1] = surface->compute_page_offset() + region->bo->offset64;
+ surface->compute_tile_offsets(&tile_x, &tile_y);
surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
SET_FIELD(mocs, GEN7_SURFACE_MOCS);
--
1.8.3.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] Blorp without surface state xy-offsets
Surface state for blorp handles miplevel (and layer) offsets by adding full pages to the base address and the remaining offset within a tile (page) using special tile_xy-fields in the surface state config. This series moves the intra-tile offset handling to the blorp program. Vertices provided to the hardware are adjusted along with the drawing rectangle, and sampling offsets are shifted to compensate for the destination shift as well as to any offset in the source surface itself. This is all Paul's idea - I just tried to it implement accordingly. Originally the idea was to use hardware support for miplevel and layer access. This is proved to be very difficult due to the need for treating w-tiled stencil as y-tiled. Once miplevels become small enough, the aspect ratio changes between Y and W requiring special adjusting in the blorp program. The chosen approach should be a lot safer. I haven't tried yet but I cannot see any reason why the hardware layer support couldn't be enabled on top of this. Topi Pohjolainen (7): i965/blorp: refactor assertions for tile offset alignments i965/blorp: split calculations of page and tile offsets i965/blorp: add intra-tile offset support without surface config i965/blorp: handle destination tile offsets for w-tiled in the program i965/blorp: handle source tile offsets for w-tiled in the program i965/blorp: handle tile offsets for all destinations in the program i965/blorp: handle tile offsets for all sources in the program src/mesa/drivers/dri/i965/brw_blorp.cpp | 87 +-- src/mesa/drivers/dri/i965/brw_blorp.h | 21 ++- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 5 ++ src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 + src/mesa/drivers/dri/i965/gen6_blorp.cpp | 45 -- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 18 +++--- 6 files changed, 143 insertions(+), 35 deletions(-) -- 1.8.3.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/7] i965/blorp: add intra-tile offset support without surface config
In gen6/7 the surface state can be adjusted with these directly but
starting from gen8 there isn't that option anymore.
In this patch these are still just zero and have no effect.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 42 +++-
src/mesa/drivers/dri/i965/brw_blorp.h| 18
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 5
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 24
4 files changed, 83 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 6fc215f..0b749a9 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -46,7 +46,9 @@ brw_blorp_mip_info::brw_blorp_mip_info()
brw_blorp_surface_info::brw_blorp_surface_info()
: map_stencil_as_y_tiled(false),
- num_samples(0)
+ num_samples(0),
+ tile_x(0),
+ tile_y(0)
{
}
@@ -173,6 +175,44 @@ brw_blorp_surface_info::compute_page_offset() const
}
+/**
+ * Setup surface offsets needed for a shift from the base address of the
+ * surface to the beginning of the miplevel of interest. Destination offsets
+ * are configured for the pipeline (vertices, drawing rectangle) and their
+ * effect needs to be compensated when considering sampling coordinates for
+ * the source.
+ * It should be noted that there is need for the same offsets in two different
+ * spaces. In native X and Y-tiling cases these offsets are equal but when
+ * originally W-tiled surfaces are pretended to be Y-tiled the offsets given
+ * for the surface configuration differ from the ones used within the blorp
+ * program itself.
+ */
+void
+brw_blorp_params::configure_miplevel_offsets()
+{
+ uint32_t src_tile_orig_space_x = 0;
+ uint32_t src_tile_orig_space_y = 0;
+ uint32_t dst_tile_orig_space_x = 0;
+ uint32_t dst_tile_orig_space_y = 0;
+
+ /* Compensate for the adjusted destination offsets when calculating the
+* corresponding sampling coordinates for the source.
+*/
+ wm_push_consts.x_transform.offset -= dst_tile_orig_space_x;
+ wm_push_consts.y_transform.offset -= dst_tile_orig_space_y;
+
+ /* Shift the source itself according to its offsets. */
+ wm_push_consts.x_transform.offset += src_tile_orig_space_x;
+ wm_push_consts.y_transform.offset += src_tile_orig_space_y;
+
+ /* Also adjust the destination clipping rectangle (pixel killing). */
+ wm_push_consts.dst_x0 += dst_tile_orig_space_x;
+ wm_push_consts.dst_x1 += dst_tile_orig_space_x;
+ wm_push_consts.dst_y0 += dst_tile_orig_space_y;
+ wm_push_consts.dst_y1 += dst_tile_orig_space_y;
+}
+
+
brw_blorp_params::brw_blorp_params()
: x0(0),
y0(0),
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index bbd6481..0820e9d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -166,6 +166,23 @@ public:
* surface state for this surface.
*/
intel_msaa_layout msaa_layout;
+
+ /* Offsets within tile indicating the beginning of the mipmap level. The
+* buffer object base address can be adjusted in the surface state taking
+* into account full tiles (pages) but the remaining offset within the
+* page needs to be handled separately.
+* Offset in the destination is taken into account when setting up the
+* vertices for the pipeline. It is also considered within the shader
+* when resolving the sampling coordinates for the source surface and
+* setting up the clipping boundaries for the destination itself.
+* Source offset in turn is handled fully in the shader as part of the
+* sampling coordinate calculation.
+* Both source and destination offsets are also used in the surface state
+* setup phase to adjust the surface dimensions allowing for the shift in
+* the beginning of the read/write.
+*/
+ uint32_t tile_x;
+ uint32_t tile_y;
};
@@ -224,6 +241,7 @@ public:
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const = 0;
+ void configure_miplevel_offsets();
uint32_t x0;
uint32_t y0;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index c23504f..c5456a0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -2242,6 +2242,11 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
src.x_offset *= 2;
src.y_offset /= 2;
}
+
+ /* Now that possible compensation for W-tiling is done it is possible to
+* calculate any offsets needed for accessing miplevels other than zero.
+*/
+ configure_miplevel_offsets();
}
uint32_t
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 75900b8..8f257a7 100644
---
[Mesa-dev] [PATCH 4/7] i965/blorp: handle destination tile offsets for w-tiled in the program
instead of using the surface state x/y-offsets. These are not
available in the gen8 anymore.
No regressions on IVB and SNB.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 7 +++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 22 --
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 20 +++-
3 files changed, 38 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 0b749a9..ff590b5 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -195,6 +195,13 @@ brw_blorp_params::configure_miplevel_offsets()
uint32_t dst_tile_orig_space_x = 0;
uint32_t dst_tile_orig_space_y = 0;
+ if (dst.map_stencil_as_y_tiled) {
+ dst.compute_tile_offsets(&dst.tile_x, &dst.tile_y);
+
+ dst_tile_orig_space_x = dst.tile_x / 2;
+ dst_tile_orig_space_y = dst.tile_y * 2;
+ }
+
/* Compensate for the adjusted destination offsets when calculating the
* corresponding sampling coordinates for the source.
*/
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 8f257a7..5cd947b 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -378,7 +378,6 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
height /= 2;
}
struct intel_region *region = surface->mt->region;
- uint32_t tile_x, tile_y;
uint32_t *surf = (uint32_t *)
brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
@@ -392,6 +391,13 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
/* reloc */
surf[1] = surface->compute_page_offset() + region->bo->offset64;
+ /* When the tile offsets are handled by the blorp program directly the
+* dimensions of the surface need to be updated to allow full access.
+*/
+ if (surface->map_stencil_as_y_tiled && ¶ms->dst == surface) {
+ width += surface->tile_x;
+ height += surface->tile_y;
+ }
surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
(width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -407,12 +413,16 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
(pitch_bytes - 1) << BRW_SURFACE_PITCH_SHIFT);
surf[4] = brw_get_surface_num_multisamples(surface->num_samples);
+ surf[5] = (surface->mt->align_h == 4 ?
+ BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
- surface->compute_tile_offsets(&tile_x, &tile_y);
- surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
- (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
- (surface->mt->align_h == 4 ?
- BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
+ if (!surface->map_stencil_as_y_tiled || ¶ms->dst != surface) {
+ uint32_t tile_x, tile_y;
+
+ surface->compute_tile_offsets(&tile_x, &tile_y);
+ surf[5] |= (SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
+ SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET));
+ }
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->batch.bo,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index f6afab2..9e51b03 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -150,7 +150,6 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
* gen6_blorp_emit_surface_state).
*/
struct intel_region *region = surface->mt->region;
- uint32_t tile_x, tile_y;
const uint8_t mocs = GEN7_MOCS_L3;
uint32_t tiling = surface->map_stencil_as_y_tiled
@@ -177,10 +176,21 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
/* reloc */
surf[1] = surface->compute_page_offset() + region->bo->offset64;
- surface->compute_tile_offsets(&tile_x, &tile_y);
- surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
- SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
- SET_FIELD(mocs, GEN7_SURFACE_MOCS);
+ surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);
+
+ /* When the tile offsets are handled by the blorp program directly the
+* dimensions of the surface need to be updated to allow full access.
+*/
+ if (surface->map_stencil_as_y_tiled && is_render_target) {
+ width += surface->tile_x;
+ height += surface->tile_y;
+ } else {
+ uint32_t tile_x, tile_y;
+
+ surface->compute_tile_offsets(&tile_x, &tile_y);
+ surf[5] |= (SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
+ SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET));
+ }
surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
--
1.8.3.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 6/7] i965/blorp: handle tile offsets for all destinations in the program
Note that tile offset calculation is unnecessary for hiz as it does
not have a shader that would use them nor does the hiz execution
update the surface state table for destination - it configures only
the depth surface which is handled separately.
No regressions on IVB and SNB.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 10 ++
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 ++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +-
4 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 5cff9b4..32d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -192,14 +192,16 @@ brw_blorp_params::configure_miplevel_offsets()
{
uint32_t src_tile_orig_space_x = 0;
uint32_t src_tile_orig_space_y = 0;
- uint32_t dst_tile_orig_space_x = 0;
- uint32_t dst_tile_orig_space_y = 0;
+ uint32_t dst_tile_orig_space_x;
+ uint32_t dst_tile_orig_space_y;
+ dst.compute_tile_offsets(&dst.tile_x, &dst.tile_y);
if (dst.map_stencil_as_y_tiled) {
- dst.compute_tile_offsets(&dst.tile_x, &dst.tile_y);
-
dst_tile_orig_space_x = dst.tile_x / 2;
dst_tile_orig_space_y = dst.tile_y * 2;
+ } else {
+ dst_tile_orig_space_x = dst.tile_x;
+ dst_tile_orig_space_y = dst.tile_y;
}
if (src.map_stencil_as_y_tiled) {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 94672e0..701561b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -191,6 +191,7 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct
brw_context *brw,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
dst.set(brw, irb->mt, irb->mt_level, layer, true);
+ dst.compute_tile_offsets(&dst.tile_x, &dst.tile_y);
/* Override the surface format according to the context's sRGB rules. */
mesa_format format = _mesa_get_render_format(ctx, irb->mt->format);
@@ -362,6 +363,7 @@ brw_blorp_rt_resolve_params::brw_blorp_rt_resolve_params(
struct intel_mipmap_tree *mt)
{
dst.set(brw, mt, 0 /* level */, 0 /* layer */, true);
+ dst.compute_tile_offsets(&dst.tile_x, &dst.tile_y);
/* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
*
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index e5b3d3c..c89ec86 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -394,7 +394,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
/* When the tile offsets are handled by the blorp program directly the
* dimensions of the surface need to be updated to allow full access.
*/
- if (surface->map_stencil_as_y_tiled) {
+ if (surface->map_stencil_as_y_tiled || ¶ms->dst == surface) {
width += surface->tile_x;
height += surface->tile_y;
}
@@ -416,7 +416,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
surf[5] = (surface->mt->align_h == 4 ?
BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
- if (!surface->map_stencil_as_y_tiled) {
+ if (!surface->map_stencil_as_y_tiled && ¶ms->dst != surface) {
uint32_t tile_x, tile_y;
surface->compute_tile_offsets(&tile_x, &tile_y);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 337b7b9..8488e26 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -181,7 +181,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
/* When the tile offsets are handled by the blorp program directly the
* dimensions of the surface need to be updated to allow full access.
*/
- if (surface->map_stencil_as_y_tiled) {
+ if (surface->map_stencil_as_y_tiled || is_render_target) {
width += surface->tile_x;
height += surface->tile_y;
} else {
--
1.8.3.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 7/7] i965/blorp: handle tile offsets for all sources in the program
Note that hiz and clear programs need no consideration here as
they do not use any source surfaces.
No regressions on IVB and SNB.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 10 ++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 18 --
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 17 -
3 files changed, 14 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 32d..92bb037 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -190,8 +190,8 @@ brw_blorp_surface_info::compute_page_offset() const
void
brw_blorp_params::configure_miplevel_offsets()
{
- uint32_t src_tile_orig_space_x = 0;
- uint32_t src_tile_orig_space_y = 0;
+ uint32_t src_tile_orig_space_x;
+ uint32_t src_tile_orig_space_y;
uint32_t dst_tile_orig_space_x;
uint32_t dst_tile_orig_space_y;
@@ -204,11 +204,13 @@ brw_blorp_params::configure_miplevel_offsets()
dst_tile_orig_space_y = dst.tile_y;
}
+ src.compute_tile_offsets(&src.tile_x, &src.tile_y);
if (src.map_stencil_as_y_tiled) {
- src.compute_tile_offsets(&src.tile_x, &src.tile_y);
-
src_tile_orig_space_x = src.tile_x / 2;
src_tile_orig_space_y = src.tile_y * 2;
+ } else {
+ src_tile_orig_space_x = src.tile_x;
+ src_tile_orig_space_y = src.tile_y;
}
/* Compensate for the adjusted destination offsets when calculating the
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index c89ec86..4614e7f 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -391,13 +391,11 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
/* reloc */
surf[1] = surface->compute_page_offset() + region->bo->offset64;
- /* When the tile offsets are handled by the blorp program directly the
-* dimensions of the surface need to be updated to allow full access.
+ /* Tile offsets are handled by the blorp program directly and therefore
+* the dimensions of the surface need to be updated to allow full access.
*/
- if (surface->map_stencil_as_y_tiled || ¶ms->dst == surface) {
- width += surface->tile_x;
- height += surface->tile_y;
- }
+ width += surface->tile_x;
+ height += surface->tile_y;
surf[2] = (0 << BRW_SURFACE_LOD_SHIFT |
(width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
@@ -416,14 +414,6 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
surf[5] = (surface->mt->align_h == 4 ?
BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
- if (!surface->map_stencil_as_y_tiled && ¶ms->dst != surface) {
- uint32_t tile_x, tile_y;
-
- surface->compute_tile_offsets(&tile_x, &tile_y);
- surf[5] |= (SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
- SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET));
- }
-
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw->batch.bo,
wm_surf_offset + 4,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 8488e26..53c0e15 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -178,20 +178,11 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);
- /* When the tile offsets are handled by the blorp program directly the
-* dimensions of the surface need to be updated to allow full access.
+ /* Tile offsets are handled by the blorp program directly and therefore
+* the dimensions of the surface need to be updated to allow full access.
*/
- if (surface->map_stencil_as_y_tiled || is_render_target) {
- width += surface->tile_x;
- height += surface->tile_y;
- } else {
- uint32_t tile_x, tile_y;
-
- surface->compute_tile_offsets(&tile_x, &tile_y);
- surf[5] |= (SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
- SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET));
- }
-
+ width += surface->tile_x;
+ height += surface->tile_y;
surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
--
1.8.3.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/7] i965/blorp: handle source tile offsets for w-tiled in the program
instead of using the surface state x/y-offsets. These are not
available in the gen8 anymore.
No regressions on IVB and SNB.
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 7 +++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +-
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index ff590b5..5cff9b4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -202,6 +202,13 @@ brw_blorp_params::configure_miplevel_offsets()
dst_tile_orig_space_y = dst.tile_y * 2;
}
+ if (src.map_stencil_as_y_tiled) {
+ src.compute_tile_offsets(&src.tile_x, &src.tile_y);
+
+ src_tile_orig_space_x = src.tile_x / 2;
+ src_tile_orig_space_y = src.tile_y * 2;
+ }
+
/* Compensate for the adjusted destination offsets when calculating the
* corresponding sampling coordinates for the source.
*/
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 5cd947b..e5b3d3c 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -394,7 +394,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
/* When the tile offsets are handled by the blorp program directly the
* dimensions of the surface need to be updated to allow full access.
*/
- if (surface->map_stencil_as_y_tiled && ¶ms->dst == surface) {
+ if (surface->map_stencil_as_y_tiled) {
width += surface->tile_x;
height += surface->tile_y;
}
@@ -416,7 +416,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
surf[5] = (surface->mt->align_h == 4 ?
BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0);
- if (!surface->map_stencil_as_y_tiled || ¶ms->dst != surface) {
+ if (!surface->map_stencil_as_y_tiled) {
uint32_t tile_x, tile_y;
surface->compute_tile_offsets(&tile_x, &tile_y);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 9e51b03..337b7b9 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -181,7 +181,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
/* When the tile offsets are handled by the blorp program directly the
* dimensions of the surface need to be updated to allow full access.
*/
- if (surface->map_stencil_as_y_tiled && is_render_target) {
+ if (surface->map_stencil_as_y_tiled) {
width += surface->tile_x;
height += surface->tile_y;
} else {
--
1.8.3.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74803] Cogs shadows are broken
https://bugs.freedesktop.org/show_bug.cgi?id=74803 --- Comment #5 from funkydude --- Created attachment 93797 --> https://bugs.freedesktop.org/attachment.cgi?id=93797&action=edit glxinfo -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74803] Cogs shadows are broken
https://bugs.freedesktop.org/show_bug.cgi?id=74803 --- Comment #6 from funkydude --- Created attachment 93798 --> https://bugs.freedesktop.org/attachment.cgi?id=93798&action=edit xorg log -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74803] Cogs shadows are broken
https://bugs.freedesktop.org/show_bug.cgi?id=74803 --- Comment #7 from funkydude --- I purged the PPA which downgraded me to mesa 9.2.1 (I think). The issue is still there. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] glsl: Do not vectorize vector array dereferences.
Array dereferences must have scalar indices, so we cannot vectorize
them.
Reported-by: Andrew Guertin
---
src/glsl/opt_vectorize.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/glsl/opt_vectorize.cpp b/src/glsl/opt_vectorize.cpp
index 8ee81f1..dba303d 100644
--- a/src/glsl/opt_vectorize.cpp
+++ b/src/glsl/opt_vectorize.cpp
@@ -82,6 +82,7 @@ public:
virtual ir_visitor_status visit_enter(ir_assignment *);
virtual ir_visitor_status visit_enter(ir_swizzle *);
+ virtual ir_visitor_status visit_enter(ir_dereference_array *);
virtual ir_visitor_status visit_enter(ir_if *);
virtual ir_visitor_status visit_enter(ir_loop *);
@@ -289,6 +290,19 @@ ir_vectorize_visitor::visit_enter(ir_swizzle *ir)
return visit_continue;
}
+/* Upon entering an ir_array_dereference, remove the current assignment from
+ * further consideration. Since the index of an array dereference must scalar,
+ * we are not able to vectorize it.
+ *
+ * FINISHME: If all of scalar indices are identical we could vectorize.
+ */
+ir_visitor_status
+ir_vectorize_visitor::visit_enter(ir_dereference_array *ir)
+{
+ this->current_assignment = NULL;
+ return visit_continue_with_parent;
+}
+
/* Since there is no statement to visit between the "then" and "else"
* instructions try to vectorize before, in between, and after them to avoid
* combining statements from different basic blocks.
--
1.8.3.2
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] "glsl: Vectorize multiple scalar assignments" (mesa 4bd6e0d) breaks League of Legends on wine
On Mon, Feb 10, 2014 at 11:08 AM, Andrew Guertin wrote: > On 02/10/2014 12:11 AM, Matt Turner wrote: >> >> On Sat, Feb 8, 2014 at 5:29 AM, Andrew Guertin >> wrote: >>> >>> On 02/08/2014 02:41 AM, Matt Turner wrote: On Fri, Feb 7, 2014 at 10:22 PM, Andrew Guertin wrote: > > > Hi, > > I updated mesa and started getting some bad behavior in League of > Legends > (played through wine). After starting a game, upon hovering any of the > skill > buttons, instead of an info tooltip appearing, the whole screen is > covered > in grey. Some other problems are visible too, like the options menu > missing > most of its text. > > I bisected down to > > 4bd6e0d7c69b304be88996a6c2b96ce7d996e627 is the first bad commit > commit 4bd6e0d7c69b304be88996a6c2b96ce7d996e627 > Author: Matt Turner > Date: Sat Dec 21 11:28:05 2013 -0800 > > glsl: Vectorize multiple scalar assignments > > Reduces vertex shader instruction counts in DOTA2 by 6.42%, L4D2 > by > 4.61%, and CS:GO by 5.71%. > > total instructions in shared programs: 1500153 -> 1498191 > (-0.13%) > instructions in affected programs: 59919 -> 57957 (-3.27%) > > Reviewed-by: Ian Romanick > > > System info: > CPU: i7-3770 > GPU: HD 4000 > Kernel: 3.12 > > I am not subscribed to this mailing list, so please keep me cc'd. > > Thanks, > --Andrew Presumably you have the following commits on top of that, and none of them affect it? 8e2b8bd0 37f1903e 60654421 >>> >>> >>> >>> Yes, I was up to date with master when I first noticed this, probably >>> 882e98e5, so all of those were included. >>> >>> Could you send me (privately) or file a bug report with the output of the game running with MESA_GLSL=dump ? >>> >>> >>> >>> I've just spent about an hour trying to do this and failing. I get none >>> of >>> the output when running League of Legends. I get output when running >>> glxgears, and when running FurMark through wine, but none with LoL. I >>> also >>> tried MESA_GLSL=log, which again worked with FurMark but had no result >>> with >>> LoL. >>> >>> --Andrew >> >> >> Okay. Maybe you can capture an apitrace that shows the problem? I'd be >> able to extract the shaders from it. >> >> Thanks, >> Matt > > > I got this working, and I've uploaded the trace at > http://www.uvm.edu/~aguertin/personal/wine-preloader.trace.tar.xz . This is > with mesa a21552a96b (HEAD as of this morning), and wine 1.7.12. Thanks, that helped a lot. The problem was that the vectorization pass would combine multiple array dereference (which must have scalar indicies) into something with an illegal vector index. Running your trace against Mesa built with assertions caught the problem. I've sent a patch that fixes it and Cc'd you. If it works for you, feel free to give a Tested-by tag that I'll add to the commit message. Thanks again! Matt ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/3] glx/apple: Fixed glx context memory leak in case of failure.
Yep, looks right to me.
Reviewed-by: Jeremy Huddleston Sequoia:
On Feb 10, 2014, at 07:57, Ian Romanick wrote:
> Perhaps Jeremy can review this patch...
>
> On 02/10/2014 01:58 AM, Siavash Eliasi wrote:
>> ---
>> src/glx/apple/apple_glx_context.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/src/glx/apple/apple_glx_context.c
>> b/src/glx/apple/apple_glx_context.c
>> index 0bb25b4..8a6ded2 100644
>> --- a/src/glx/apple/apple_glx_context.c
>> +++ b/src/glx/apple/apple_glx_context.c
>> @@ -142,6 +142,7 @@ apple_glx_create_context(void **ptr, Display * dpy, int
>> screen,
>>if (sharedac && !is_context_valid(sharedac)) {
>> *errorptr = GLXBadContext;
>> *x11errorptr = false;
>> + free(ac);
>> return true;
>>}
>>
>>
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] R600/SI: Add a pattern for i32 anyext
From: Tom Stellard
---
lib/Target/R600/SIInstructions.td | 7 +--
test/CodeGen/R600/anyext.ll | 14 ++
2 files changed, 19 insertions(+), 2 deletions(-)
create mode 100644 test/CodeGen/R600/anyext.ll
diff --git a/lib/Target/R600/SIInstructions.td
b/lib/Target/R600/SIInstructions.td
index ac9b073..9da05c3 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -1840,11 +1840,14 @@ def : Pat <
(V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
>;
-def : Pat <
- (i32 (zext i1:$src0)),
+class Ext32Pat : Pat <
+ (i32 (ext i1:$src0)),
(V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
>;
+def : Ext32Pat ;
+def : Ext32Pat ;
+
// 1. Offset as 8bit DWORD immediate
def : Pat <
(SIload_constant i128:$sbase, IMM8bitDWORD:$offset),
diff --git a/test/CodeGen/R600/anyext.ll b/test/CodeGen/R600/anyext.ll
new file mode 100644
index 000..bbe5d0a
--- /dev/null
+++ b/test/CodeGen/R600/anyext.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
+
+; CHECK-LABEL: @anyext_i1_i32
+; CHECK: V_CNDMASK_B32_e64
+define void @anyext_i1_i32(i32 addrspace(1)* %out, i32 %cond) {
+entry:
+ %0 = icmp eq i32 %cond, 0
+ %1 = zext i1 %0 to i8
+ %2 = xor i8 %1, -1
+ %3 = and i8 %2, 1
+ %4 = zext i8 %3 to i32
+ store i32 %4, i32 addrspace(1)* %out
+ ret void
+}
--
1.8.1.5
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] R600/SI: Split global vector loads with more than 4 elements
From: Tom Stellard
---
lib/Target/R600/SIISelLowering.cpp | 8 +-
test/CodeGen/R600/load.ll | 178 +++--
2 files changed, 98 insertions(+), 88 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index 9537405..eb08a13 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -478,9 +478,11 @@ SDValue SITargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
case ISD::LOAD: {
LoadSDNode *Load = dyn_cast(Op);
-if ((Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
- Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
-Op.getValueType().isVector()) {
+if (Op.getValueType().isVector() &&
+(Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
+ Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
+ (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
+ Op.getValueType().getVectorNumElements() > 4))) {
SDValue MergedValues[2] = {
SplitVectorLoad(Op, DAG),
Load->getChain()
diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll
index 0153524..1486c4d 100644
--- a/test/CodeGen/R600/load.ll
+++ b/test/CodeGen/R600/load.ll
@@ -1,16 +1,15 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck
--check-prefix=R600-CHECK %s
-; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK
%s
-; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck
--check-prefix=SI-CHECK %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck
--check-prefix=R600-CHECK --check-prefix=FUNC %s
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK
--check-prefix=FUNC %s
+; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck
--check-prefix=SI-CHECK --check-prefix=FUNC %s
;======;
; GLOBAL ADDRESS SPACE
;======;
; Load an i8 value from the global address space.
-; R600-CHECK-LABEL: @load_i8
+; FUNC-LABEL: @load_i8
; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
-; SI-CHECK-LABEL: @load_i8
; SI-CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}},
define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
%1 = load i8 addrspace(1)* %in
@@ -19,13 +18,12 @@ define void @load_i8(i32 addrspace(1)* %out, i8
addrspace(1)* %in) {
ret void
}
-; R600-CHECK-LABEL: @load_i8_sext
+; FUNC-LABEL: @load_i8_sext
; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
; R600-CHECK: 24
; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
; R600-CHECK: 24
-; SI-CHECK-LABEL: @load_i8_sext
; SI-CHECK: BUFFER_LOAD_SBYTE
define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
entry:
@@ -35,10 +33,9 @@ entry:
ret void
}
-; R600-CHECK-LABEL: @load_v2i8
+; FUNC-LABEL: @load_v2i8
; R600-CHECK: VTX_READ_8
; R600-CHECK: VTX_READ_8
-; SI-CHECK-LABEL: @load_v2i8
; SI-CHECK: BUFFER_LOAD_UBYTE
; SI-CHECK: BUFFER_LOAD_UBYTE
define void @load_v2i8(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)*
%in) {
@@ -49,7 +46,7 @@ entry:
ret void
}
-; R600-CHECK-LABEL: @load_v2i8_sext
+; FUNC-LABEL: @load_v2i8_sext
; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
@@ -60,7 +57,6 @@ entry:
; R600-CHECK-DAG: 24
; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
; R600-CHECK-DAG: 24
-; SI-CHECK-LABEL: @load_v2i8_sext
; SI-CHECK: BUFFER_LOAD_SBYTE
; SI-CHECK: BUFFER_LOAD_SBYTE
define void @load_v2i8_sext(<2 x i32> addrspace(1)* %out, <2 x i8>
addrspace(1)* %in) {
@@ -71,12 +67,11 @@ entry:
ret void
}
-; R600-CHECK-LABEL: @load_v4i8
+; FUNC-LABEL: @load_v4i8
; R600-CHECK: VTX_READ_8
; R600-CHECK: VTX_READ_8
; R600-CHECK: VTX_READ_8
; R600-CHECK: VTX_READ_8
-; SI-CHECK-LABEL: @load_v4i8
; SI-CHECK: BUFFER_LOAD_UBYTE
; SI-CHECK: BUFFER_LOAD_UBYTE
; SI-CHECK: BUFFER_LOAD_UBYTE
@@ -89,7 +84,7 @@ entry:
ret void
}
-; R600-CHECK-LABEL: @load_v4i8_sext
+; FUNC-LABEL: @load_v4i8_sext
; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
; R600-CHECK-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]]
@@ -110,7 +105,6 @@ entry:
; R600-CHECK-DAG: 24
; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]]
; R600-CHECK-DAG: 24
-; SI-CHECK-LABEL: @load_v4i8_sext
; SI-CHECK: BUFFER_LOAD_SBYTE
; SI-CHECK: BUFFER_LOAD_SBYTE
; SI-CHECK: BUFFER_LOAD_SBYTE
@@ -124,9 +118,8 @@ entry:
}
; Load an i16 value from the global address sp
Re: [Mesa-dev] Mesa (master): nv30: report 8 maximum inputs
On 02/08/2014 04:18 PM, Ilia Mirkin wrote: > Module: Mesa > Branch: master > Commit: 356aff3a5c08be055d6befff99a72f5551b3ac2d > URL: > http://cgit.freedesktop.org/mesa/mesa/commit/?id=356aff3a5c08be055d6befff99a72f5551b3ac2d > > Author: Ilia Mirkin > Date: Wed Jan 29 12:36:13 2014 -0500 > > nv30: report 8 maximum inputs > > nvfx_fragprog_assign_generic only allows for up to 10/8 texcoords for > nv40/nv30. This fixes compilation of the varying-packing tests. > Furthermore it appears that the last 2 inputs on nv4x don't seem to > work in those tests, so just report 8 everywhere for now. Is it possible that the last two inputs are supposed to be used for gl_Color and gl_SecondaryColor? In that case, they may have clamping enabled by default (or always enabled, if the hardware cannot disable GL_CLAMP_VERTEX_COLOR). Does that match the behavior that you saw? > Tested on NV42, NV44. NV4B appears to have additional problems. > > Signed-off-by: Ilia Mirkin > Cc: 9.1 9.2 10.0 10.1 > > --- > > src/gallium/drivers/nouveau/nv30/nv30_screen.c |2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c > b/src/gallium/drivers/nouveau/nv30/nv30_screen.c > index 787802d..4045fdc 100644 > --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c > +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c > @@ -217,7 +217,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen, > unsigned shader, >case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: > return 0; >case PIPE_SHADER_CAP_MAX_INPUTS: > - return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10; > + return 8; /* should be possible to do 10 with nv4x */ >case PIPE_SHADER_CAP_MAX_CONSTS: > return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32; >case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: > > ___ > mesa-commit mailing list > mesa-com...@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-commit > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Mesa (master): nv30: report 8 maximum inputs
On Mon, Feb 10, 2014 at 4:43 PM, Ian Romanick wrote:
> On 02/08/2014 04:18 PM, Ilia Mirkin wrote:
>> Module: Mesa
>> Branch: master
>> Commit: 356aff3a5c08be055d6befff99a72f5551b3ac2d
>> URL:
>> http://cgit.freedesktop.org/mesa/mesa/commit/?id=356aff3a5c08be055d6befff99a72f5551b3ac2d
>>
>> Author: Ilia Mirkin
>> Date: Wed Jan 29 12:36:13 2014 -0500
>>
>> nv30: report 8 maximum inputs
>>
>> nvfx_fragprog_assign_generic only allows for up to 10/8 texcoords for
>> nv40/nv30. This fixes compilation of the varying-packing tests.
>> Furthermore it appears that the last 2 inputs on nv4x don't seem to
>> work in those tests, so just report 8 everywhere for now.
>
> Is it possible that the last two inputs are supposed to be used for
> gl_Color and gl_SecondaryColor? In that case, they may have clamping
> enabled by default (or always enabled, if the hardware cannot disable
> GL_CLAMP_VERTEX_COLOR). Does that match the behavior that you saw?
I'm definitely out of my depth here. What I saw were piglit tests
failing and hard-to-understand code with little additional
documentation.
There's a mask that enables passing of outputs from VP -> FP. This
mask has separate entries for colors, fog, psize, and clipping. The
texcoord's, as they are called, are in a different part of the mask.
The last 2 are in a different-yet part of the mask from the first 8.
This of course does not preclude them getting clamped/modified in some
way. Ideally those varying-packing tests would be rewritten in a way
that better exposes what actually went wrong, but I realize it's not
easy to add printf("interesting values: %f %f") into a shader.
It's also entirely possible that the issue is that the way you address
those last 2 texcoord's in the FP has to be done in some different way
than the first 8. Ideally I (or someone) would trace the blob and
analyze the bytecode/engine setup to see what the difference is. I
haven't gotten around to that (and unfortunately envydis doesn't
support the nv30/nv40 shader ISA).
However I was trying to make a dent in the nv4x failures and crashes.
This is the latest state, btw:
http://people.freedesktop.org/~imirkin/nv40-comparison/problems.html
-- I think actually a bunch of the test failures are due to incorrect
piglit tests (e.g. "shader uses too many input components (48 > 32)"),
so it's not _quite_ as bad as it looks. But before all of those were
"assertion failure trying to parse the TGSI because it had too many
inputs".
>
>> Tested on NV42, NV44. NV4B appears to have additional problems.
>>
>> Signed-off-by: Ilia Mirkin
>> Cc: 9.1 9.2 10.0 10.1
>>
>> ---
>>
>> src/gallium/drivers/nouveau/nv30/nv30_screen.c |2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
>> b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
>> index 787802d..4045fdc 100644
>> --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
>> +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
>> @@ -217,7 +217,7 @@ nv30_screen_get_shader_param(struct pipe_screen
>> *pscreen, unsigned shader,
>>case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
>> return 0;
>>case PIPE_SHADER_CAP_MAX_INPUTS:
>> - return (eng3d->oclass >= NV40_3D_CLASS) ? 12 : 10;
>> + return 8; /* should be possible to do 10 with nv4x */
>>case PIPE_SHADER_CAP_MAX_CONSTS:
>> return (eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32;
>>case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
>>
>> ___
>> mesa-commit mailing list
>> mesa-com...@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/mesa-commit
>>
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74471] [swrast] piglit ext_texture_array-gen-mipmap regression
https://bugs.freedesktop.org/show_bug.cgi?id=74471 Ian Romanick changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |DUPLICATE --- Comment #1 from Ian Romanick --- Bug #74769 has some more details. *** This bug has been marked as a duplicate of bug 74769 *** -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 73946] scanout broken on radeon SI (OLAND)
https://bugs.freedesktop.org/show_bug.cgi?id=73946 --- Comment #11 from Alex Deucher --- Also for oland, make sure your kernel has this patch: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/radeon/atombios_crtc.c?id=227ae10f17a5f2fd1307b7e582b603ef7bbb7e97 -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: Do not vectorize vector array dereferences.
Tested-by: Andrew Guertin
On 02/10/2014 04:09 PM, Matt Turner wrote:
Array dereferences must have scalar indices, so we cannot vectorize
them.
Reported-by: Andrew Guertin
---
src/glsl/opt_vectorize.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/glsl/opt_vectorize.cpp b/src/glsl/opt_vectorize.cpp
index 8ee81f1..dba303d 100644
--- a/src/glsl/opt_vectorize.cpp
+++ b/src/glsl/opt_vectorize.cpp
@@ -82,6 +82,7 @@ public:
virtual ir_visitor_status visit_enter(ir_assignment *);
virtual ir_visitor_status visit_enter(ir_swizzle *);
+ virtual ir_visitor_status visit_enter(ir_dereference_array *);
virtual ir_visitor_status visit_enter(ir_if *);
virtual ir_visitor_status visit_enter(ir_loop *);
@@ -289,6 +290,19 @@ ir_vectorize_visitor::visit_enter(ir_swizzle *ir)
return visit_continue;
}
+/* Upon entering an ir_array_dereference, remove the current assignment from
+ * further consideration. Since the index of an array dereference must scalar,
+ * we are not able to vectorize it.
+ *
+ * FINISHME: If all of scalar indices are identical we could vectorize.
+ */
+ir_visitor_status
+ir_vectorize_visitor::visit_enter(ir_dereference_array *ir)
+{
+ this->current_assignment = NULL;
+ return visit_continue_with_parent;
+}
+
/* Since there is no statement to visit between the "then" and "else"
* instructions try to vectorize before, in between, and after them to avoid
* combining statements from different basic blocks.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] "glsl: Vectorize multiple scalar assignments" (mesa 4bd6e0d) breaks League of Legends on wine
On 02/10/2014 12:11 AM, Matt Turner wrote: On Sat, Feb 8, 2014 at 5:29 AM, Andrew Guertin wrote: On 02/08/2014 02:41 AM, Matt Turner wrote: On Fri, Feb 7, 2014 at 10:22 PM, Andrew Guertin wrote: Hi, I updated mesa and started getting some bad behavior in League of Legends (played through wine). After starting a game, upon hovering any of the skill buttons, instead of an info tooltip appearing, the whole screen is covered in grey. Some other problems are visible too, like the options menu missing most of its text. I bisected down to 4bd6e0d7c69b304be88996a6c2b96ce7d996e627 is the first bad commit commit 4bd6e0d7c69b304be88996a6c2b96ce7d996e627 Author: Matt Turner Date: Sat Dec 21 11:28:05 2013 -0800 glsl: Vectorize multiple scalar assignments Reduces vertex shader instruction counts in DOTA2 by 6.42%, L4D2 by 4.61%, and CS:GO by 5.71%. total instructions in shared programs: 1500153 -> 1498191 (-0.13%) instructions in affected programs: 59919 -> 57957 (-3.27%) Reviewed-by: Ian Romanick System info: CPU: i7-3770 GPU: HD 4000 Kernel: 3.12 I am not subscribed to this mailing list, so please keep me cc'd. Thanks, --Andrew Presumably you have the following commits on top of that, and none of them affect it? 8e2b8bd0 37f1903e 60654421 Yes, I was up to date with master when I first noticed this, probably 882e98e5, so all of those were included. Could you send me (privately) or file a bug report with the output of the game running with MESA_GLSL=dump ? I've just spent about an hour trying to do this and failing. I get none of the output when running League of Legends. I get output when running glxgears, and when running FurMark through wine, but none with LoL. I also tried MESA_GLSL=log, which again worked with FurMark but had no result with LoL. --Andrew Okay. Maybe you can capture an apitrace that shows the problem? I'd be able to extract the shaders from it. Thanks, Matt I got this working, and I've uploaded the trace at http://www.uvm.edu/~aguertin/personal/wine-preloader.trace.tar.xz . This is with mesa a21552a96b (HEAD as of this morning), and wine 1.7.12. Also, while doing this I found that MESA_GLSL=log *did* work, it just put the results in an unexpected place. I haven't uploaded those, but let me know if you want them. Also let me know if you want output from a pre-regression mesa. --Andrew ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] R600/SI: Split global vector loads with more than 4 elements
Why would you want to do this for the small types? You should be able to
load those in fewer loads and then promote them.
On 02/10/2014 01:32 PM, Tom Stellard wrote:
From: Tom Stellard
---
lib/Target/R600/SIISelLowering.cpp | 8 +-
test/CodeGen/R600/load.ll | 178 +++--
2 files changed, 98 insertions(+), 88 deletions(-)
diff --git a/lib/Target/R600/SIISelLowering.cpp
b/lib/Target/R600/SIISelLowering.cpp
index 9537405..eb08a13 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -478,9 +478,11 @@ SDValue SITargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
case ISD::LOAD: {
LoadSDNode *Load = dyn_cast(Op);
-if ((Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
- Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
-Op.getValueType().isVector()) {
+if (Op.getValueType().isVector() &&
+(Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
+ Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
+ (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
+ Op.getValueType().getVectorNumElements() > 4))) {
SDValue MergedValues[2] = {
SplitVectorLoad(Op, DAG),
Load->getChain()
diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll
index 0153524..1486c4d 100644
--- a/test/CodeGen/R600/load.ll
+++ b/test/CodeGen/R600/load.ll
@@ -1,16 +1,15 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck
--check-prefix=R600-CHECK %s
-; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK
%s
-; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck
--check-prefix=SI-CHECK %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck
--check-prefix=R600-CHECK --check-prefix=FUNC %s
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK
--check-prefix=FUNC %s
+; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck
--check-prefix=SI-CHECK --check-prefix=FUNC %s
;======;
; GLOBAL ADDRESS SPACE
;======;
; Load an i8 value from the global address space.
-; R600-CHECK-LABEL: @load_i8
+; FUNC-LABEL: @load_i8
; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
-; SI-CHECK-LABEL: @load_i8
; SI-CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}},
define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
%1 = load i8 addrspace(1)* %in
@@ -19,13 +18,12 @@ define void @load_i8(i32 addrspace(1)* %out, i8
addrspace(1)* %in) {
ret void
}
-; R600-CHECK-LABEL: @load_i8_sext
+; FUNC-LABEL: @load_i8_sext
; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
; R600-CHECK: 24
; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
; R600-CHECK: 24
-; SI-CHECK-LABEL: @load_i8_sext
; SI-CHECK: BUFFER_LOAD_SBYTE
define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
entry:
@@ -35,10 +33,9 @@ entry:
ret void
}
-; R600-CHECK-LABEL: @load_v2i8
+; FUNC-LABEL: @load_v2i8
; R600-CHECK: VTX_READ_8
; R600-CHECK: VTX_READ_8
-; SI-CHECK-LABEL: @load_v2i8
; SI-CHECK: BUFFER_LOAD_UBYTE
; SI-CHECK: BUFFER_LOAD_UBYTE
define void @load_v2i8(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)*
%in) {
@@ -49,7 +46,7 @@ entry:
ret void
}
-; R600-CHECK-LABEL: @load_v2i8_sext
+; FUNC-LABEL: @load_v2i8_sext
; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
@@ -60,7 +57,6 @@ entry:
; R600-CHECK-DAG: 24
; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
; R600-CHECK-DAG: 24
-; SI-CHECK-LABEL: @load_v2i8_sext
; SI-CHECK: BUFFER_LOAD_SBYTE
; SI-CHECK: BUFFER_LOAD_SBYTE
define void @load_v2i8_sext(<2 x i32> addrspace(1)* %out, <2 x i8>
addrspace(1)* %in) {
@@ -71,12 +67,11 @@ entry:
ret void
}
-; R600-CHECK-LABEL: @load_v4i8
+; FUNC-LABEL: @load_v4i8
; R600-CHECK: VTX_READ_8
; R600-CHECK: VTX_READ_8
; R600-CHECK: VTX_READ_8
; R600-CHECK: VTX_READ_8
-; SI-CHECK-LABEL: @load_v4i8
; SI-CHECK: BUFFER_LOAD_UBYTE
; SI-CHECK: BUFFER_LOAD_UBYTE
; SI-CHECK: BUFFER_LOAD_UBYTE
@@ -89,7 +84,7 @@ entry:
ret void
}
-; R600-CHECK-LABEL: @load_v4i8_sext
+; FUNC-LABEL: @load_v4i8_sext
; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
; R600-CHECK-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]]
@@ -110,7 +105,6 @@ entry:
; R600-CHECK-DAG: 24
; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV
[Mesa-dev] [PATCH] mesa: assorted clean-ups in detach_shader()
Fix formatting, add new comments, get rid of extraneous indentation.
Suggested by Ian in bug 74723.
---
src/mesa/main/shaderapi.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 97a57a4..44b4c3a 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -383,31 +383,31 @@ detach_shader(struct gl_context *ctx, GLuint program,
GLuint shader)
_mesa_reference_shader(ctx, &shProg->Shaders[i], NULL);
/* alloc new, smaller array */
- newList =
-malloc((n - 1) * sizeof(struct gl_shader *));
+ newList = malloc((n - 1) * sizeof(struct gl_shader *));
if (!newList) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glDetachShader");
return;
}
+ /* Copy old list entries to new list, skipping removed entry at [i] */
for (j = 0; j < i; j++) {
newList[j] = shProg->Shaders[j];
}
- while (++i < n)
+ while (++i < n) {
newList[j++] = shProg->Shaders[i];
- free(shProg->Shaders);
+ }
+ /* Free old list and install new one */
+ free(shProg->Shaders);
shProg->Shaders = newList;
shProg->NumShaders = n - 1;
#ifdef DEBUG
- /* sanity check */
- {
-for (j = 0; j < shProg->NumShaders; j++) {
- assert(shProg->Shaders[j]->Type == GL_VERTEX_SHADER ||
- shProg->Shaders[j]->Type == GL_GEOMETRY_SHADER ||
- shProg->Shaders[j]->Type == GL_FRAGMENT_SHADER);
- assert(shProg->Shaders[j]->RefCount > 0);
-}
+ /* sanity check - make sure the new list's entries are sensible */
+ for (j = 0; j < shProg->NumShaders; j++) {
+assert(shProg->Shaders[j]->Type == GL_VERTEX_SHADER ||
+ shProg->Shaders[j]->Type == GL_GEOMETRY_SHADER ||
+ shProg->Shaders[j]->Type == GL_FRAGMENT_SHADER);
+assert(shProg->Shaders[j]->RefCount > 0);
}
#endif
--
1.7.10.4
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] i965/fs: Simplify FS_OPCODE_SET_SAMPLE_ID stride mashing a bit.
stride(brw_vec1_reg(...) ...) takes some register, changes the strides, then changes the strides again. Let's do it once. Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 6d211e1..26913d2 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1156,8 +1156,7 @@ fs_generator::generate_set_sample_id(fs_inst *inst, brw_push_insn_state(p); brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_set_mask_control(p, BRW_MASK_DISABLE); - struct brw_reg reg = stride(retype(brw_vec1_reg(src1.file, src1.nr, 0), - BRW_REGISTER_TYPE_UW), 1, 4, 0); + struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW); brw_ADD(p, dst, src0, reg); if (dispatch_width == 16) brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2)); -- 1.8.5.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] i965/fs: Simplify FS_OPCODE_SET_OMASK stride mashing a bit.
In the first case, we can simply call stride(mask, 16, 8, 2) rather than
creating a new register with a different stride, then immediately
changing it a second time.
In the second case, the stride was already what we wanted, so we can
just use mask without any changes at all.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 26913d2..4820b04 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1130,11 +1130,9 @@ fs_generator::generate_set_omask(fs_inst *inst,
brw_set_mask_control(p, BRW_MASK_DISABLE);
if (stride_8_8_1) {
- brw_MOV(p, dst, stride(retype(brw_vec1_reg(mask.file, mask.nr, 0),
-dst.type), 16, 8, 2));
+ brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
} else if (stride_0_1_0) {
- brw_MOV(p, dst, stride(retype(brw_vec1_reg(mask.file, mask.nr, 0),
-dst.type), 0, 1, 0));
+ brw_MOV(p, dst, retype(mask, dst.type));
}
brw_pop_insn_state(p);
}
--
1.8.5.2
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Mesa (master): nv30: report 8 maximum inputs
On 02/10/2014 02:04 PM, Ilia Mirkin wrote:
> On Mon, Feb 10, 2014 at 4:43 PM, Ian Romanick wrote:
>> On 02/08/2014 04:18 PM, Ilia Mirkin wrote:
>>> Module: Mesa
>>> Branch: master
>>> Commit: 356aff3a5c08be055d6befff99a72f5551b3ac2d
>>> URL:
>>> http://cgit.freedesktop.org/mesa/mesa/commit/?id=356aff3a5c08be055d6befff99a72f5551b3ac2d
>>>
>>> Author: Ilia Mirkin
>>> Date: Wed Jan 29 12:36:13 2014 -0500
>>>
>>> nv30: report 8 maximum inputs
>>>
>>> nvfx_fragprog_assign_generic only allows for up to 10/8 texcoords for
>>> nv40/nv30. This fixes compilation of the varying-packing tests.
>>> Furthermore it appears that the last 2 inputs on nv4x don't seem to
>>> work in those tests, so just report 8 everywhere for now.
>>
>> Is it possible that the last two inputs are supposed to be used for
>> gl_Color and gl_SecondaryColor? In that case, they may have clamping
>> enabled by default (or always enabled, if the hardware cannot disable
>> GL_CLAMP_VERTEX_COLOR). Does that match the behavior that you saw?
>
> I'm definitely out of my depth here. What I saw were piglit tests
> failing and hard-to-understand code with little additional
> documentation.
>
> There's a mask that enables passing of outputs from VP -> FP. This
> mask has separate entries for colors, fog, psize, and clipping. The
> texcoord's, as they are called, are in a different part of the mask.
> The last 2 are in a different-yet part of the mask from the first 8.
Hm... that does sound like something different.
> This of course does not preclude them getting clamped/modified in some
> way. Ideally those varying-packing tests would be rewritten in a way
> that better exposes what actually went wrong, but I realize it's not
> easy to add printf("interesting values: %f %f") into a shader.
Can that hardware render to floating point? You could try rendering to
a fp FBO, doing glReadPixels, the printf the data. It's messy, but it
works.
> It's also entirely possible that the issue is that the way you address
> those last 2 texcoord's in the FP has to be done in some different way
> than the first 8. Ideally I (or someone) would trace the blob and
> analyze the bytecode/engine setup to see what the difference is. I
> haven't gotten around to that (and unfortunately envydis doesn't
> support the nv30/nv40 shader ISA).
>
> However I was trying to make a dent in the nv4x failures and crashes.
> This is the latest state, btw:
> http://people.freedesktop.org/~imirkin/nv40-comparison/problems.html
> -- I think actually a bunch of the test failures are due to incorrect
> piglit tests (e.g. "shader uses too many input components (48 > 32)"),
Is that just the variable indexing tests? Hm... in at least
vs-varying-array-mat4-col-rd.shader_test, it looks like the varying
array is too big. OpenGL 2.1 only requires 32 varying components, and
that test clearly uses 16*3+4 = 52. It seems like the linker should
chop off the last element, but that still only reduces the usage to 36.
A few of those tests could be made to work with 32 varying floats by
reducing the array size from 3 to 2.
There are a couple that can't be fixed that way because you'd have to
reduce the array size to 1. For those tests, you'll have to add a
MAX_VARYING_COMPONENTS requirement that behaves like the existing
MAX_FRAGMENT_UNIFORM_VECTORS requirement.
> so it's not _quite_ as bad as it looks. But before all of those were
> "assertion failure trying to parse the TGSI because it had too many
> inputs".
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: assorted clean-ups in detach_shader()
On 02/10/2014 03:43 PM, Brian Paul wrote:
> Fix formatting, add new comments, get rid of extraneous indentation.
> Suggested by Ian in bug 74723.
> ---
> src/mesa/main/shaderapi.c | 24
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
> index 97a57a4..44b4c3a 100644
> --- a/src/mesa/main/shaderapi.c
> +++ b/src/mesa/main/shaderapi.c
> @@ -383,31 +383,31 @@ detach_shader(struct gl_context *ctx, GLuint program,
> GLuint shader)
> _mesa_reference_shader(ctx, &shProg->Shaders[i], NULL);
>
> /* alloc new, smaller array */
I was looking at this code earlier today. Would this be better?
/* Move the "tail" of the list of shaders up by one element.
*/
memmove(&shProg->Shaders[j], &shProg->Shaders[j + 1],
sizeof(shProg->Shaders[0]) * (n - (j + 1)));
/* Compact the array. Not worried about compacting realloc failures.
*/
newList = realloc(shProg->Shaders,
sizeof(shProg->Shaders[0]) * (n - 1));
if (!newList) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "glDetachShader");
return;
}
shProg->Shaders = newList;
shProg->NumShaders = n - 1;
For that matter, do we even need to compact the allocation?
/* Move the "tail" of the list of shaders up by one element.
*/
memmove(&shProg->Shaders[j], &shProg->Shaders[j + 1],
sizeof(shProg->Shaders[0]) * (n - (j + 1)));
shProg->Shaders[n - 1] = 0;
shProg->NumShaders = n - 1;
Whichever way you feel like doing it, they're all improvements.
Reviewed-by: Ian Romanick
> - newList =
> -malloc((n - 1) * sizeof(struct gl_shader *));
> + newList = malloc((n - 1) * sizeof(struct gl_shader *));
> if (!newList) {
> _mesa_error(ctx, GL_OUT_OF_MEMORY, "glDetachShader");
> return;
> }
> + /* Copy old list entries to new list, skipping removed entry at [i]
> */
> for (j = 0; j < i; j++) {
> newList[j] = shProg->Shaders[j];
> }
> - while (++i < n)
> + while (++i < n) {
> newList[j++] = shProg->Shaders[i];
> - free(shProg->Shaders);
> + }
>
> + /* Free old list and install new one */
> + free(shProg->Shaders);
> shProg->Shaders = newList;
> shProg->NumShaders = n - 1;
>
> #ifdef DEBUG
> - /* sanity check */
> - {
> -for (j = 0; j < shProg->NumShaders; j++) {
> - assert(shProg->Shaders[j]->Type == GL_VERTEX_SHADER ||
> - shProg->Shaders[j]->Type == GL_GEOMETRY_SHADER ||
> - shProg->Shaders[j]->Type == GL_FRAGMENT_SHADER);
> - assert(shProg->Shaders[j]->RefCount > 0);
> -}
> + /* sanity check - make sure the new list's entries are sensible */
> + for (j = 0; j < shProg->NumShaders; j++) {
> +assert(shProg->Shaders[j]->Type == GL_VERTEX_SHADER ||
> + shProg->Shaders[j]->Type == GL_GEOMETRY_SHADER ||
> + shProg->Shaders[j]->Type == GL_FRAGMENT_SHADER);
> +assert(shProg->Shaders[j]->RefCount > 0);
> }
> #endif
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: Do not vectorize vector array dereferences.
On 02/10/2014 01:09 PM, Matt Turner wrote:
> Array dereferences must have scalar indices, so we cannot vectorize
> them.
>
> Reported-by: Andrew Guertin
Seems like the easy fix.
Reviewed-by: Ian Romanick
Candidate for 10.1?
> ---
> src/glsl/opt_vectorize.cpp | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/src/glsl/opt_vectorize.cpp b/src/glsl/opt_vectorize.cpp
> index 8ee81f1..dba303d 100644
> --- a/src/glsl/opt_vectorize.cpp
> +++ b/src/glsl/opt_vectorize.cpp
> @@ -82,6 +82,7 @@ public:
>
> virtual ir_visitor_status visit_enter(ir_assignment *);
> virtual ir_visitor_status visit_enter(ir_swizzle *);
> + virtual ir_visitor_status visit_enter(ir_dereference_array *);
> virtual ir_visitor_status visit_enter(ir_if *);
> virtual ir_visitor_status visit_enter(ir_loop *);
>
> @@ -289,6 +290,19 @@ ir_vectorize_visitor::visit_enter(ir_swizzle *ir)
> return visit_continue;
> }
>
> +/* Upon entering an ir_array_dereference, remove the current assignment from
> + * further consideration. Since the index of an array dereference must
> scalar,
> + * we are not able to vectorize it.
> + *
> + * FINISHME: If all of scalar indices are identical we could vectorize.
> + */
> +ir_visitor_status
> +ir_vectorize_visitor::visit_enter(ir_dereference_array *ir)
> +{
> + this->current_assignment = NULL;
> + return visit_continue_with_parent;
> +}
> +
> /* Since there is no statement to visit between the "then" and "else"
> * instructions try to vectorize before, in between, and after them to avoid
> * combining statements from different basic blocks.
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] i965/fs: Simplify FS_OPCODE_SET_SAMPLE_ID stride mashing a bit.
Series is Reviewed-by: Ian Romanick On 02/10/2014 03:46 PM, Kenneth Graunke wrote: > stride(brw_vec1_reg(...) ...) takes some register, changes the strides, > then changes the strides again. Let's do it once. > > Signed-off-by: Kenneth Graunke > --- > src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp > b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp > index 6d211e1..26913d2 100644 > --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp > +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp > @@ -1156,8 +1156,7 @@ fs_generator::generate_set_sample_id(fs_inst *inst, > brw_push_insn_state(p); > brw_set_compression_control(p, BRW_COMPRESSION_NONE); > brw_set_mask_control(p, BRW_MASK_DISABLE); > - struct brw_reg reg = stride(retype(brw_vec1_reg(src1.file, src1.nr, 0), > - BRW_REGISTER_TYPE_UW), 1, 4, 0); > + struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW); > brw_ADD(p, dst, src0, reg); > if (dispatch_width == 16) >brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2)); > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: Do not vectorize vector array dereferences.
On Mon, Feb 10, 2014 at 4:32 PM, Ian Romanick wrote: > On 02/10/2014 01:09 PM, Matt Turner wrote: >> Array dereferences must have scalar indices, so we cannot vectorize >> them. >> >> Reported-by: Andrew Guertin > > Seems like the easy fix. > > Reviewed-by: Ian Romanick > > Candidate for 10.1? Yep, will mark as such. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/3] glsl: Compile error if fs defines conflicting qualifiers for gl_FragCoord
GLSL 1.50 spec says:
"If gl_FragCoord is redeclared in any fragment shader in a program,
it must be redeclared in all the fragment shaders in that
program that have a static use gl_FragCoord. All redeclarations of
gl_FragCoord in all fragment shaders in a single program must
have the same set of qualifiers."
This patch makes the glsl compiler to generate an error if we have a
fragment shader defined with conflicting layout qualifier declarations
for gl_FragCoord. For example:
layout(origin_upper_left, pixel_center_integer) in vec4 gl_FragCoord;
layout(pixel_center_integer) in vec4 gl_FragCoord;
void main()
{
gl_FragColor = gl_FragCoord.xyzz;
}
Cc:
Signed-off-by: Anuj Phogat
---
src/glsl/ast_to_hir.cpp | 39 +++
src/glsl/glsl_parser_extras.cpp | 3 +++
src/glsl/glsl_parser_extras.h | 10 ++
3 files changed, 52 insertions(+)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index c89a26b..7d7d89b 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2374,6 +2374,45 @@ apply_type_qualifier_to_variable(const struct
ast_type_qualifier *qual,
qual_string);
}
+ /* Make sure all gl_FragCoord redeclarations specify the same layout
+* qualifier type.
+*/
+ bool conflicting_pixel_center_integer =
+ state->fs_pixel_center_integer &&
+ !qual->flags.q.pixel_center_integer;
+
+ bool conflicting_origin_upper_left =
+ state->fs_origin_upper_left &&
+ !qual->flags.q.origin_upper_left;
+
+ if (conflicting_pixel_center_integer || conflicting_origin_upper_left) {
+ const char *const qual_string =
+ (conflicting_pixel_center_integer && conflicting_origin_upper_left) ?
+ "pixel_center_integer, origin_upper_left" :
+ (conflicting_pixel_center_integer ?
+ "origin_upper_left" : "pixel_center_integer");
+
+ const char *const state_string =
+ (state->fs_pixel_center_integer &&
+ state->fs_origin_upper_left) ?
+ "pixel_center_integer, origin_upper_left" :
+ (state->fs_origin_upper_left ?
+ "origin_upper_left" : "pixel_center_integer");
+
+ _mesa_glsl_error(loc, state,
+ "different layout qualifiers were specified with "
+ "`gl_FragCoord' (%s) and (%s) "
+ "redeclare fragment shader input `gl_FragCoord'",
+ state_string,
+ qual_string);
+ }
+
+ if (qual->flags.q.pixel_center_integer)
+ state->fs_pixel_center_integer = true;
+
+ if (qual->flags.q.origin_upper_left)
+ state->fs_origin_upper_left = true;
+
if (qual->flags.q.explicit_location) {
validate_explicit_location(qual, var, state, loc);
} else if (qual->flags.q.explicit_index) {
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index b822d22..b06337e 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -193,6 +193,9 @@ _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct
gl_context *_ctx,
this->default_uniform_qualifier->flags.q.shared = 1;
this->default_uniform_qualifier->flags.q.column_major = 1;
+ this->fs_origin_upper_left = false;
+ this->fs_pixel_center_integer = false;
+
this->gs_input_prim_type_specified = false;
this->gs_input_prim_type = GL_POINTS;
this->gs_input_size = 0;
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 7d66147..674dae5 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -182,6 +182,16 @@ struct _mesa_glsl_parse_state {
struct ast_type_qualifier *default_uniform_qualifier;
/**
+* True if a fragment shader has an input layout for redeclaring the
+* built-in variable gl_FragCoord.
+*
+* Note: this value is computed at ast_to_hir time rather than at parse
+* time.
+*/
+ bool fs_origin_upper_left;
+ bool fs_pixel_center_integer;
+
+ /**
* True if a geometry shader input primitive type was specified using a
* layout directive.
*
--
1.8.3.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/3] glsl: Link error if fs defines conflicting qualifiers for gl_FragCoord
GLSL 1.50 spec says:
"If gl_FragCoord is redeclared in any fragment shader in a program,
it must be redeclared in all the fragment shaders in that
program that have a static use gl_FragCoord. All redeclarations of
gl_FragCoord in all fragment shaders in a single program must
have the same set of qualifiers."
This patch causes the shader link to fail if we have multiple fragment
shaders with conflicting layout qualifiers for gl_FragCoord. For example:
fragment shader 1:
layout(origin_upper_left, pixel_center_integer) in vec4 gl_FragCoord;
void foo();
void main()
{
gl_FragColor = vec4(gl_FragCoord.xyz, 1.0);
foo();
}
fragment shader 2:
layout(origin_upper_left) in vec4 gl_FragCoord;
void foo()
{
gl_FragColor.a = gl_FragCoord.z;
}
Cc:
Signed-off-by: Anuj Phogat
---
src/glsl/ast_to_hir.cpp | 5
src/glsl/glsl_parser_extras.cpp | 14 +
src/glsl/glsl_parser_extras.h | 1 +
src/glsl/linker.cpp | 63 +
src/mesa/main/mtypes.h | 7 +
5 files changed, 90 insertions(+)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 7d7d89b..3b2e05a 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -120,6 +120,11 @@ _mesa_ast_to_hir(exec_list *instructions, struct
_mesa_glsl_parse_state *state)
instructions->push_head(var);
}
+ /* Figure out if gl_FragCoord is actually used in fragment shader */
+ ir_variable *const var = state->symbols->get_variable("gl_FragCoord");
+ if (var != NULL)
+ state->uses_gl_fragcoord = var->data.used;
+
/* From section 7.1 (Built-In Language Variables) of the GLSL 4.10 spec:
*
* If multiple shaders using members of a built-in block belonging to
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index b06337e..07fd1c7 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -193,6 +193,7 @@ _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct
gl_context *_ctx,
this->default_uniform_qualifier->flags.q.shared = 1;
this->default_uniform_qualifier->flags.q.column_major = 1;
+ this->uses_gl_fragcoord = false;
this->fs_origin_upper_left = false;
this->fs_pixel_center_integer = false;
@@ -1350,6 +1351,13 @@ set_shader_inout_layout(struct gl_shader *shader,
assert(!state->cs_input_local_size_specified);
}
+ if (shader->Stage != MESA_SHADER_FRAGMENT) {
+ /* Should have been prevented by the parser. */
+ assert(!state->uses_gl_fragcoord);
+ assert(!state->fs_pixel_center_integer);
+ assert(!state->fs_origin_upper_left);
+ }
+
switch (shader->Stage) {
case MESA_SHADER_GEOMETRY:
shader->Geom.VerticesOut = 0;
@@ -1379,6 +1387,12 @@ set_shader_inout_layout(struct gl_shader *shader,
}
break;
+ case MESA_SHADER_FRAGMENT:
+ shader->uses_gl_fragcoord = state->uses_gl_fragcoord;
+ shader->pixel_center_integer = state->fs_pixel_center_integer;
+ shader->origin_upper_left = state->fs_origin_upper_left;
+ break;
+
default:
/* Nothing to do. */
break;
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 674dae5..eddcf77 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -393,6 +393,7 @@ struct _mesa_glsl_parse_state {
const struct gl_extensions *extensions;
bool uses_builtin_functions;
+ bool uses_gl_fragcoord;
/**
* For geometry shaders, size of the most recently seen input declaration
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index bcd7394..f8564ca 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -1194,6 +1194,68 @@ private:
hash_table *unnamed_interfaces;
};
+static bool
+fs_uses_conflicting_layout_qualifiers(struct gl_shader *shader,
+ struct gl_shader *linked_shader)
+{
+ bool qual_absent_in_shader_but_present_in_linked_shader =
+ (!shader->origin_upper_left && linked_shader->origin_upper_left) ||
+ (!shader->pixel_center_integer && linked_shader->pixel_center_integer);
+
+ bool qual_present_in_shader_but_absent_in_linked_shader =
+ (shader->origin_upper_left && !linked_shader->origin_upper_left) ||
+ (shader->pixel_center_integer && !linked_shader->pixel_center_integer);
+
+ if ((qual_absent_in_shader_but_present_in_linked_shader &&
+shader->uses_gl_fragcoord) ||
+ (qual_present_in_shader_but_absent_in_linked_shader &&
+linked_shader->uses_gl_fragcoord))
+ return true;
+
+ return false;
+}
+
+/**
+ * Performs the cross-validation of layout qualifiers specified in
+ * redeclaration of gl_FragCoord for the attached fragment shaders,
+ * and propagates them to the linked FS and linked shader program.
+ */
+static void
+link_fs_input_layout_qualifiers(struct gl_shader_program *prog,
+ struct gl_shader *
[Mesa-dev] [PATCH 3/3] glsl: Apply the link error conditions to GL_ARB_fragment_coord_conventions
Link error conditions added in previous patch are equally applicable to GL_ARB_fragment_coord_conventions implementation. Extension's spec says: "If gl_FragCoord is redeclared in any fragment shader in a program, it must be redeclared in all the fragment shaders in that program that have a static use of gl_FragCoord. All redeclarations of gl_FragCoord in all fragment shaders in a single program must have the same set of qualifiers." Cc: Signed-off-by: Anuj Phogat --- src/glsl/glsl_parser_extras.cpp | 2 ++ src/glsl/linker.cpp | 7 ++- src/mesa/main/mtypes.h | 6 ++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp index 07fd1c7..89a8dbd 100644 --- a/src/glsl/glsl_parser_extras.cpp +++ b/src/glsl/glsl_parser_extras.cpp @@ -1391,6 +1391,8 @@ set_shader_inout_layout(struct gl_shader *shader, shader->uses_gl_fragcoord = state->uses_gl_fragcoord; shader->pixel_center_integer = state->fs_pixel_center_integer; shader->origin_upper_left = state->fs_origin_upper_left; + shader->ARB_fragment_coord_conventions_enable = + state->ARB_fragment_coord_conventions_enable; break; default: diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp index f8564ca..8f700ce 100644 --- a/src/glsl/linker.cpp +++ b/src/glsl/linker.cpp @@ -1230,7 +1230,8 @@ link_fs_input_layout_qualifiers(struct gl_shader_program *prog, linked_shader->origin_upper_left = false; linked_shader->pixel_center_integer = false; - if (linked_shader->Stage != MESA_SHADER_FRAGMENT || prog->Version < 150) + if (linked_shader->Stage != MESA_SHADER_FRAGMENT || + (prog->Version < 150 && !prog->ARB_fragment_coord_conventions_enable)) return; /* From the GLSL 1.50 spec, page 39: @@ -2120,6 +2121,7 @@ link_shaders(struct gl_context *ctx, struct gl_shader_program *prog) ralloc_free(prog->AtomicBuffers); prog->AtomicBuffers = NULL; prog->NumAtomicBuffers = 0; + prog->ARB_fragment_coord_conventions_enable = false; /* Separate the shaders into groups based on their type. */ @@ -2146,6 +2148,9 @@ link_shaders(struct gl_context *ctx, struct gl_shader_program *prog) goto done; } + prog->ARB_fragment_coord_conventions_enable |= + prog->Shaders[i]->ARB_fragment_coord_conventions_enable; + gl_shader_stage shader_type = prog->Shaders[i]->Stage; shader_list[shader_type][num_shaders[shader_type]] = prog->Shaders[i]; num_shaders[shader_type]++; diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index bbb6231..5e18faa 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -2413,6 +2413,7 @@ struct gl_shader bool uses_builtin_functions; bool uses_gl_fragcoord; + bool ARB_fragment_coord_conventions_enable; /** * Fragment shader state from GLSL 1.50 layout qualifiers. @@ -2736,6 +2737,11 @@ struct gl_shader_program * \c NULL. */ struct gl_shader *_LinkedShaders[MESA_SHADER_STAGES]; + + /* True if any of the fragment shaders attached to this program use: +* #extension ARB_fragment_coord_conventions: enable +*/ + GLboolean ARB_fragment_coord_conventions_enable; }; -- 1.8.3.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 74803] Cogs shadows are broken
https://bugs.freedesktop.org/show_bug.cgi?id=74803 --- Comment #8 from Marek Olšák --- Try to set this environment variable: R600_DEBUG=nohyperz -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/3] st/mesa: add texture gather support. (v2)
From: Dave Airlie
This adds support for GL_ARB_texture_gather, and one step of
support for GL_ARB_gpu_shader5.
This adds support for passing the TG4 instruction, along
with non-constant texture offsets, and tracking them for the
optimisation passes.
This doesn't support native textureGatherOffsets hw, to do that
you'd need to add a CAP and if set disable the lowering pass,
and bump the MAX offsets to 4, then do the i0,j0 sampling using
those.
Signed-off-by: Dave Airlie
---
src/mesa/state_tracker/st_extensions.c | 4 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 117 ++---
2 files changed, 94 insertions(+), 27 deletions(-)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index f9b7a44..e6d26a9 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -268,6 +268,7 @@ void st_init_limits(struct st_context *st)
c->MinProgramTexelOffset = screen->get_param(screen,
PIPE_CAP_MIN_TEXEL_OFFSET);
c->MaxProgramTexelOffset = screen->get_param(screen,
PIPE_CAP_MAX_TEXEL_OFFSET);
+ c->MaxProgramTextureGatherComponents = screen->get_param(screen,
PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS);
c->UniformBooleanTrue = ~0;
c->MaxTransformFeedbackBuffers =
@@ -779,4 +780,7 @@ void st_init_extensions(struct st_context *st)
if (!ctx->Extensions.EXT_transform_feedback)
ctx->Const.DisableVaryingPacking = GL_TRUE;
}
+
+ if (ctx->Const.MaxProgramTextureGatherComponents > 0)
+ ctx->Extensions.ARB_texture_gather = GL_TRUE;
}
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 610fc68..0db770e 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -87,7 +87,7 @@ extern "C" {
*/
#define MAX_ARRAYS256
-/* will be 4 for GLSL 4.00 */
+/* if we support a native gallium TG4 with the ability to take 4 texoffsets
then bump this */
#define MAX_GLSL_TEXTURE_OFFSET 1
class st_src_reg;
@@ -249,7 +249,8 @@ public:
int sampler; /**< sampler index */
int tex_target; /**< One of TEXTURE_*_INDEX */
GLboolean tex_shadow;
- struct tgsi_texture_offset tex_offsets[MAX_GLSL_TEXTURE_OFFSET];
+
+ st_src_reg tex_offsets[MAX_GLSL_TEXTURE_OFFSET];
unsigned tex_offset_num_offset;
int dead_mask; /**< Used in dead code elimination */
@@ -2685,7 +2686,7 @@ glsl_to_tgsi_visitor::visit(ir_call *ir)
void
glsl_to_tgsi_visitor::visit(ir_texture *ir)
{
- st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy, offset,
sample_index;
+ st_src_reg result_src, coord, cube_sc, lod_info, projector, dx, dy, offset,
sample_index, component;
st_dst_reg result_dst, coord_dst, cube_sc_dst;
glsl_to_tgsi_instruction *inst = NULL;
unsigned opcode = TGSI_OPCODE_NOP;
@@ -2779,12 +2780,20 @@ glsl_to_tgsi_visitor::visit(ir_texture *ir)
ir->lod_info.sample_index->accept(this);
sample_index = this->result;
break;
+ case ir_tg4:
+ opcode = TGSI_OPCODE_TG4;
+ ir->lod_info.component->accept(this);
+ component = this->result;
+ if (ir->offset) {
+ ir->offset->accept(this);
+ /* this should have been lowered */
+ assert(ir->offset->type->base_type != GLSL_TYPE_ARRAY);
+ offset = this->result;
+ }
+ break;
case ir_lod:
assert(!"Unexpected ir_lod opcode");
break;
- case ir_tg4:
- assert(!"Unexpected ir_tg4 opcode");
- break;
case ir_query_levels:
assert(!"Unexpected ir_query_levels opcode");
break;
@@ -2892,7 +2901,13 @@ glsl_to_tgsi_visitor::visit(ir_texture *ir)
inst = emit(ir, opcode, result_dst, coord, lod_info);
} else if (opcode == TGSI_OPCODE_TEX2) {
inst = emit(ir, opcode, result_dst, coord, cube_sc);
- } else
+ } else if (opcode == TGSI_OPCODE_TG4) {
+ if (is_cube_array && ir->shadow_comparitor) {
+ inst = emit(ir, opcode, result_dst, coord, cube_sc);
+ } else {
+ inst = emit(ir, opcode, result_dst, coord, component);
+ }
+ } else
inst = emit(ir, opcode, result_dst, coord);
if (ir->shadow_comparitor)
@@ -2903,12 +2918,8 @@ glsl_to_tgsi_visitor::visit(ir_texture *ir)
this->prog);
if (ir->offset) {
- inst->tex_offset_num_offset = 1;
- inst->tex_offsets[0].Index = offset.index;
- inst->tex_offsets[0].File = offset.file;
- inst->tex_offsets[0].SwizzleX = GET_SWZ(offset.swizzle, 0);
- inst->tex_offsets[0].SwizzleY = GET_SWZ(offset.swizzle, 1);
- inst->tex_offsets[0].SwizzleZ = GET_SWZ(offset.swizzle, 2);
+ inst->tex_offset_num_offset = 1;
+ inst->tex_offsets[0] = offset;
}
switch (sampler_type->sampler_dimensionality) {
@@ -3266,6 +3277,13 @@ glsl_to_tgsi_visitor::rename_temp_register(int index,
int new_index)
inst->
[Mesa-dev] [PATCH 2/3] gallium: add texture gather support to gallium (v3)
From: Dave Airlie
This adds support to gallium for a TG4 instruction,
and two CAPs. The first CAP is required for GL_ARB_texture_gather.
The second CAP is required to expose GL_ARB_gpu_shader5.
However so far we haven't found any hardware that natively
exposes the textureGatherOffsets feature from GL, so just
lower it for now. If hardware appears for this we can add
another CAP to allow TG4 to take 4 offsets.
v2: add component selection src and a cap to say
hw can do it. (st can use to help control
GL_ARB_gpu_shader5/GLSL 4.00). Add docs.
v3: rename to SM5, add docs.
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi/tgsi_info.c | 1 +
src/gallium/docs/source/screen.rst | 6
src/gallium/docs/source/tgsi.rst | 36
src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++
src/gallium/drivers/i915/i915_screen.c | 2 ++
src/gallium/drivers/ilo/ilo_screen.c | 2 ++
src/gallium/drivers/llvmpipe/lp_screen.c | 2 ++
src/gallium/drivers/nouveau/nv30/nv30_screen.c | 2 ++
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 ++
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++
src/gallium/drivers/r300/r300_screen.c | 2 ++
src/gallium/drivers/r600/r600_pipe.c | 2 ++
src/gallium/drivers/radeonsi/si_pipe.c | 2 ++
src/gallium/drivers/softpipe/sp_screen.c | 2 ++
src/gallium/drivers/svga/svga_screen.c | 2 ++
src/gallium/include/pipe/p_defines.h | 4 ++-
src/gallium/include/pipe/p_shader_tokens.h | 4 ++-
17 files changed, 73 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index f993600..565f274 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -221,6 +221,7 @@ static const struct tgsi_opcode_info
opcode_info[TGSI_OPCODE_LAST] =
{ 1, 3, 1, 0, 0, 0, OTHR, "TXL2", TGSI_OPCODE_TXL2 },
{ 1, 2, 0, 0, 0, 0, COMP, "IMUL_HI", TGSI_OPCODE_IMUL_HI },
{ 1, 2, 0, 0, 0, 0, COMP, "UMUL_HI", TGSI_OPCODE_UMUL_HI },
+ { 1, 3, 1, 0, 0, 0, OTHR, "TG4", TGSI_OPCODE_TG4 },
};
const struct tgsi_opcode_info *
diff --git a/src/gallium/docs/source/screen.rst
b/src/gallium/docs/source/screen.rst
index bd553f4..6b5a195 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -182,6 +182,12 @@ The integer capabilities:
vertex components output by a single invocation of a geometry shader.
This is the product of the number of attribute components per vertex and
the number of output vertices.
+* ``PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS``: Max number of components
+ in format that texture gather can operate on. 1 == RED, ALPHA etc,
+ 4 == All formats.
+* ``PIPE_CAP_TEXTURE_GATHER_SM5``: Whether the texture gather
+ hardware implements the SM5 features, component selection,
+ shadow comparison, and run-time offsets.
.. _pipe_capf:
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index be42572..03c5df8 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -986,6 +986,42 @@ XXX doesn't look like most of the opcodes really belong
here.
dst.z = texture_depth(unit, lod)
+.. opcode:: TG4 - Texture Gather (as per ARB_texture_gather)
+ Gathers the four texels to be used in a bi-linear
+ filtering operation and packs them into a single register.
+ Only works with 2D, 2D array, cubemaps, and cubemaps arrays.
+ For 2D textures, only the addressing modes of the sampler and
+ the top level of any mip pyramid are used. Set W to zero.
+ It behaves like the TEX instruction, but a filtered
+ sample is not generated. The four samples that contribute
+ to filtering are placed into xyzw in clockwise order,
+ starting with the (u,v) texture coordinate delta at the
+ following locations (-, +), (+, +), (+, -), (-, -), where
+ the magnitude of the deltas are half a texel.
+
+ PIPE_CAP_TEXTURE_SM5 enhances this instruction to support
+ shadow per-sample depth compares, single component selection,
+ and a non-constant offset. It doesn't allow support for the
+ GL independent offset to get i0,j0. This would require another
+ CAP is hw can do it natively. For now we lower that before
+ TGSI.
+
+.. math::
+
+ coord = src0
+
+ component = src1
+
+ dst = texture_gather4 (unit, coord, component)
+
+(with SM5 - cube array shadow)
+
+ coord = src0
+
+ compare = src1
+
+ dst = texture_gather (uint, coord, compare)
+
Integer ISA
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c
b/src/gallium/drivers/freedreno/freedreno_scr
[Mesa-dev] gallium/st: add texture gather support
This adds support to gallium, and also to the state tracker for ARB_texture_gather and also the gather features of ARB_gpu_shader5. It adds a single CAP for the ARB_texture_gather max components query, then another CAP to denote the GPU is capable of SM5 gather. This doesn't add native support for textureGatherOffsets yet, I don't have hw that can do this, so instead I just moved the i965 glsl lowering pass to a generic place and reused it. If you have native support for this feature, then you need to add another CAP + modify the state tracker at the appropriate places. I can help with it, if you are sure your hw can do it. You'd also need to modify the TG4 instruction under the new CAP to accept 4 offsets. I have r600g patches on top of this to add support to r600g, r600/700 can only do ARB_texture_gather, whereas evergreen->cayman can do the SM5 stuff, but not native tGOs. Dave. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/3] glsl/i965: move lower_offset_array up to GLSL compiler level.
From: Dave Airlie
This lowering pass will be useful for gallium drivers as well, in order to
support
the GL TG4 oddity that is textureGatherOffsets.
Signed-off-by: Dave Airlie
---
src/glsl/Makefile.sources | 1 +
src/glsl/ir_optimization.h | 1 +
src/glsl/lower_offset_array.cpp| 90 +
src/mesa/drivers/dri/i965/Makefile.sources | 1 -
src/mesa/drivers/dri/i965/brw_context.h| 1 -
.../drivers/dri/i965/brw_lower_offset_array.cpp| 93 --
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +-
7 files changed, 93 insertions(+), 96 deletions(-)
create mode 100644 src/glsl/lower_offset_array.cpp
delete mode 100644 src/mesa/drivers/dri/i965/brw_lower_offset_array.cpp
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index e69c1ac..5945590 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -67,6 +67,7 @@ LIBGLSL_FILES = \
$(GLSL_SRCDIR)/lower_jumps.cpp \
$(GLSL_SRCDIR)/lower_mat_op_to_vec.cpp \
$(GLSL_SRCDIR)/lower_noise.cpp \
+ $(GLSL_SRCDIR)/lower_offset_array.cpp \
$(GLSL_SRCDIR)/lower_packed_varyings.cpp \
$(GLSL_SRCDIR)/lower_named_interface_blocks.cpp \
$(GLSL_SRCDIR)/lower_packing_builtins.cpp \
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 055d655..24d019b 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -120,6 +120,7 @@ bool lower_vector_insert(exec_list *instructions, bool
lower_nonconstant_index);
void lower_named_interface_blocks(void *mem_ctx, gl_shader *shader);
bool optimize_redundant_jumps(exec_list *instructions);
bool optimize_split_arrays(exec_list *instructions, bool linked);
+bool lower_offset_arrays(exec_list *instructions);
ir_rvalue *
compare_index_block(exec_list *instructions, ir_variable *index,
diff --git a/src/glsl/lower_offset_array.cpp b/src/glsl/lower_offset_array.cpp
new file mode 100644
index 000..0c235ed
--- /dev/null
+++ b/src/glsl/lower_offset_array.cpp
@@ -0,0 +1,90 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \file brw_lower_offset_array.cpp
+ *
+ * IR lower pass to decompose ir_texture ir_tg4 with an array of offsets
+ * into four ir_tg4s with a single ivec2 offset, select the .w component of
each,
+ * and return those four values packed into a gvec4.
+ *
+ * \author Chris Forbes
+ */
+
+#include "glsl_types.h"
+#include "ir.h"
+#include "ir_builder.h"
+#include "ir_optimization.h"
+#include "ir_rvalue_visitor.h"
+
+using namespace ir_builder;
+
+class brw_lower_offset_array_visitor : public ir_rvalue_visitor {
+public:
+ brw_lower_offset_array_visitor()
+ {
+ progress = false;
+ }
+
+ void handle_rvalue(ir_rvalue **rv);
+
+ bool progress;
+};
+
+void
+brw_lower_offset_array_visitor::handle_rvalue(ir_rvalue **rv)
+{
+ if (*rv == NULL || (*rv)->ir_type != ir_type_texture)
+ return;
+
+ ir_texture *ir = (ir_texture *) *rv;
+ if (ir->op != ir_tg4 || !ir->offset || !ir->offset->type->is_array())
+ return;
+
+ void *mem_ctx = ralloc_parent(ir);
+
+ ir_variable *var = new (mem_ctx) ir_variable(ir->type, "result",
ir_var_auto);
+ base_ir->insert_before(var);
+
+ for (int i = 0; i < 4; i++) {
+ ir_texture *tex = ir->clone(mem_ctx, NULL);
+ tex->offset = new (mem_ctx) ir_dereference_array(tex->offset,
+new (mem_ctx) ir_constant(i));
+
+ base_ir->insert_before(assign(var, swizzle_w(tex), 1 << i));
+ }
+
+ *rv = new (mem_ctx) ir_dereference_variable(var);
+
+ progress = true;
+}
+
+bool
+lower_offset_arrays(exec_list *instructions)
+{
+ brw_lower_offset_array_visitor v;
+
+ visit_list_elements(&v, instructions);
+
+ return v.progress;
+}
diff --git a/src/mesa/drivers/dri/i965/M
Re: [Mesa-dev] Mesa (master): nv30: report 8 maximum inputs
On Mon, Feb 10, 2014 at 7:12 PM, Ian Romanick wrote:
> On 02/10/2014 02:04 PM, Ilia Mirkin wrote:
>> On Mon, Feb 10, 2014 at 4:43 PM, Ian Romanick wrote:
>>> On 02/08/2014 04:18 PM, Ilia Mirkin wrote:
Module: Mesa
Branch: master
Commit: 356aff3a5c08be055d6befff99a72f5551b3ac2d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=356aff3a5c08be055d6befff99a72f5551b3ac2d
Author: Ilia Mirkin
Date: Wed Jan 29 12:36:13 2014 -0500
nv30: report 8 maximum inputs
nvfx_fragprog_assign_generic only allows for up to 10/8 texcoords for
nv40/nv30. This fixes compilation of the varying-packing tests.
Furthermore it appears that the last 2 inputs on nv4x don't seem to
work in those tests, so just report 8 everywhere for now.
>>>
>>> Is it possible that the last two inputs are supposed to be used for
>>> gl_Color and gl_SecondaryColor? In that case, they may have clamping
>>> enabled by default (or always enabled, if the hardware cannot disable
>>> GL_CLAMP_VERTEX_COLOR). Does that match the behavior that you saw?
>>
>> I'm definitely out of my depth here. What I saw were piglit tests
>> failing and hard-to-understand code with little additional
>> documentation.
>>
>> There's a mask that enables passing of outputs from VP -> FP. This
>> mask has separate entries for colors, fog, psize, and clipping. The
>> texcoord's, as they are called, are in a different part of the mask.
>> The last 2 are in a different-yet part of the mask from the first 8.
>
> Hm... that does sound like something different.
>
>> This of course does not preclude them getting clamped/modified in some
>> way. Ideally those varying-packing tests would be rewritten in a way
>> that better exposes what actually went wrong, but I realize it's not
>> easy to add printf("interesting values: %f %f") into a shader.
>
> Can that hardware render to floating point? You could try rendering to
> a fp FBO, doing glReadPixels, the printf the data. It's messy, but it
> works.
The hardware? Yes. But it's disabled in the software. I asked Ben why,
and he gave me a reasonable explanation. However that explanation has
since escaped my memory, but it's in the irc logs if it's really
important.
For those specific tests, assuming a reasonable number of varyings
(i.e. < 255), one could just set the color results to e.g.
varying_index/255 -- that way we'd know which varying was the first
bad one. But in general, it's hard :( Shader debugging does seem like
a prime target for some extension though -- nv30 will never get
support for it, but at least future hardware driver writers may be
spared...
>
>> It's also entirely possible that the issue is that the way you address
>> those last 2 texcoord's in the FP has to be done in some different way
>> than the first 8. Ideally I (or someone) would trace the blob and
>> analyze the bytecode/engine setup to see what the difference is. I
>> haven't gotten around to that (and unfortunately envydis doesn't
>> support the nv30/nv40 shader ISA).
>>
>> However I was trying to make a dent in the nv4x failures and crashes.
>> This is the latest state, btw:
>> http://people.freedesktop.org/~imirkin/nv40-comparison/problems.html
>> -- I think actually a bunch of the test failures are due to incorrect
>> piglit tests (e.g. "shader uses too many input components (48 > 32)"),
>
> Is that just the variable indexing tests? Hm... in at least
At least those, yes. I forget if there were others.
> vs-varying-array-mat4-col-rd.shader_test, it looks like the varying
> array is too big. OpenGL 2.1 only requires 32 varying components, and
> that test clearly uses 16*3+4 = 52. It seems like the linker should
> chop off the last element, but that still only reduces the usage to 36.
> A few of those tests could be made to work with 32 varying floats by
> reducing the array size from 3 to 2.
Also interestingly, some of those tests used to pass before I threw in
the restriction down to 32. So I guess something can work with those
last 2 texcoords, or perhaps it was just coincidence... (Compare nv42
vs nv44 -- the nv42 run had the limit down to 8, the nv44 run didn't.)
>
> There are a couple that can't be fixed that way because you'd have to
> reduce the array size to 1. For those tests, you'll have to add a
> MAX_VARYING_COMPONENTS requirement that behaves like the existing
> MAX_FRAGMENT_UNIFORM_VECTORS requirement.
Sounds reasonable, I'll look into it. I'm less interested in making
piglit tests run on nv30 than I am at making them not fail :)
-ilia
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 02/10] r600g,radeonsi: share r600_surface
From: Marek Olšák
I'm gonna use this in radeonsi.
---
src/gallium/drivers/r600/r600_resource.h | 44 --
src/gallium/drivers/radeon/r600_pipe_common.h | 45 +++
src/gallium/drivers/radeonsi/si_pipe.h| 4 ---
src/gallium/drivers/radeonsi/si_state.c | 10 +++---
src/gallium/drivers/radeonsi/si_state.h | 1 -
5 files changed, 50 insertions(+), 54 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_resource.h
b/src/gallium/drivers/r600/r600_resource.h
index db88c9a..ae0bd88 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -34,50 +34,6 @@ struct r600_resource_global {
struct compute_memory_item *chunk;
};
-struct r600_surface {
- struct pipe_surface base;
-
- bool color_initialized;
- bool depth_initialized;
-
- /* Misc. color flags. */
- bool alphatest_bypass;
- bool export_16bpc;
-
- /* Color registers. */
- unsigned cb_color_info;
- unsigned cb_color_base;
- unsigned cb_color_view;
- unsigned cb_color_size; /* R600 only */
- unsigned cb_color_dim; /* EG only */
- unsigned cb_color_pitch;/* EG only */
- unsigned cb_color_slice;/* EG only */
- unsigned cb_color_attrib; /* EG only */
- unsigned cb_color_fmask;/* CB_COLORn_FMASK (EG) or
CB_COLORn_FRAG (r600) */
- unsigned cb_color_fmask_slice; /* EG only */
- unsigned cb_color_cmask;/* CB_COLORn_CMASK (EG) or
CB_COLORn_TILE (r600) */
- unsigned cb_color_cmask_slice; /* EG only */
- unsigned cb_color_mask; /* R600 only */
- struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations.
R600 only */
- struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations.
R600 only */
-
- /* DB registers. */
- unsigned db_depth_info; /* DB_Z_INFO (EG) or DB_DEPTH_INFO
(r600) */
- unsigned db_depth_base; /* DB_Z_READ/WRITE_BASE (EG) or
DB_DEPTH_BASE (r600) */
- unsigned db_depth_view;
- unsigned db_depth_size;
- unsigned db_depth_slice;/* EG only */
- unsigned db_stencil_base; /* EG only */
- unsigned db_stencil_info; /* EG only */
- unsigned db_prefetch_limit; /* R600 only */
- unsigned pa_su_poly_offset_db_fmt_cntl;
-
- unsignedhtile_enabled;
- unsigneddb_htile_surface;
- unsigneddb_htile_data_base;
- unsigneddb_preload_control;
-};
-
/* Return if the depth format can be read without the DB->CB copy on
r6xx-r7xx. */
static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
{
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 7193a0f..38c784a 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -160,6 +160,51 @@ struct r600_texture {
unsignedmipmap_shift;
};
+struct r600_surface {
+ struct pipe_surface base;
+
+ bool color_initialized;
+ bool depth_initialized;
+
+ /* Misc. color flags. */
+ bool alphatest_bypass;
+ bool export_16bpc;
+
+ /* Color registers. */
+ unsigned cb_color_info;
+ unsigned cb_color_base;
+ unsigned cb_color_view;
+ unsigned cb_color_size; /* R600 only */
+ unsigned cb_color_dim; /* EG only */
+ unsigned cb_color_pitch;/* EG and later */
+ unsigned cb_color_slice;/* EG and later */
+ unsigned cb_color_attrib; /* EG and later */
+ unsigned cb_color_fmask;/* CB_COLORn_FMASK (EG and later) or
CB_COLORn_FRAG (r600) */
+ unsigned cb_color_fmask_slice; /* EG and later */
+ unsigned cb_color_cmask;/* CB_COLORn_CMASK (EG and later) or
CB_COLORn_TILE (r600) */
+ unsigned cb_color_cmask_slice; /* EG and later */
+ unsigned cb_color_mask; /* R600 only */
+ struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations.
R600 only */
+ struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations.
R600 only */
+
+ /* DB registers. */
+ unsigned db_depth_info; /* R600 only, then SI and later */
+ unsigned db_z_info; /* EG and later */
+ unsigned db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later)
or DB_DEPTH_BASE (r600) */
+ unsigned db_depth_view;
+ unsigned db_depth_size;
+ unsigned db_depth_slice;/* EG and later */
+ unsigned db_stencil_base; /* EG and later */
+ unsigned db_stencil_info; /* EG and later */
+ unsigned db_prefetch_limit; /* R600 only */
+ unsigned db
[Mesa-dev] [PATCH 01/10] radeonsi: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to framebuffer state
From: Marek Olšák
It doesn't depend on anything else.
---
src/gallium/drivers/radeonsi/si_state.c | 29 +
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 5020547..f288652 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -484,7 +484,6 @@ static void si_update_fb_rs_state(struct si_context *sctx)
{
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
struct si_pm4_state *pm4;
- unsigned offset_db_fmt_cntl = 0, depth;
float offset_units;
if (!rs || !sctx->framebuffer.zsbuf)
@@ -496,17 +495,13 @@ static void si_update_fb_rs_state(struct si_context *sctx)
case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- depth = -24;
offset_units *= 2.0f;
break;
case PIPE_FORMAT_Z32_FLOAT:
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- depth = -23;
offset_units *= 1.0f;
- offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
break;
case PIPE_FORMAT_Z16_UNORM:
- depth = -16;
offset_units *= 4.0f;
break;
default:
@@ -519,14 +514,12 @@ static void si_update_fb_rs_state(struct si_context *sctx)
return;
/* FIXME some of those reg can be computed with cso */
- offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
fui(sctx->queued.named.rasterizer->offset_scale));
si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
fui(offset_units));
si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
fui(sctx->queued.named.rasterizer->offset_scale));
si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
fui(offset_units));
- si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
offset_db_fmt_cntl);
si_pm4_set_state(sctx, fb_rs, pm4);
}
@@ -1767,7 +1760,7 @@ static void si_db(struct si_context *sctx, struct
si_pm4_state *pm4,
unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks,
pipe_config;
uint32_t z_info, s_info, db_depth_info;
uint64_t z_offs, s_offs;
- uint32_t db_htile_data_base, db_htile_surface;
+ uint32_t db_htile_data_base, db_htile_surface,
pa_su_poly_offset_db_fmt_cntl;
if (state->zsbuf == NULL) {
si_pm4_set_reg(pm4, R_028040_DB_Z_INFO,
S_028040_FORMAT(V_028040_Z_INVALID));
@@ -1781,6 +1774,25 @@ static void si_db(struct si_context *sctx, struct
si_pm4_state *pm4,
format = si_translate_dbformat(rtex->resource.b.b.format);
+ switch (sctx->framebuffer.zsbuf->texture->format) {
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ case PIPE_FORMAT_X8Z24_UNORM:
+ case PIPE_FORMAT_Z24X8_UNORM:
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
+ break;
+ case PIPE_FORMAT_Z32_FLOAT:
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+ pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
+
S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+ break;
+ case PIPE_FORMAT_Z16_UNORM:
+ pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
+ break;
+ default:
+ assert(0);
+ }
+
if (format == V_028040_Z_INVALID) {
R600_ERR("Invalid DB format: %d, disabling DB.\n",
rtex->resource.b.b.format);
}
@@ -1900,6 +1912,7 @@ static void si_db(struct si_context *sctx, struct
si_pm4_state *pm4,
si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE,
S_02805C_SLICE_TILE_MAX(slice));
si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
+ si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
pa_su_poly_offset_db_fmt_cntl);
}
#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
--
1.8.3.2
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 07/10] radeonsi: compute depth surface registers only once
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_state.c | 98 ++---
1 file changed, 54 insertions(+), 44 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 89b4242..6642c7b 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1731,30 +1731,18 @@ static void si_initialize_color_surface(struct
si_context *sctx,
surf->color_initialized = true;
}
-static void si_db(struct si_context *sctx, struct si_pm4_state *pm4,
- const struct pipe_framebuffer_state *state)
+static void si_init_depth_surface(struct si_context *sctx,
+ struct r600_surface *surf)
{
struct si_screen *sscreen = sctx->screen;
- struct r600_texture *rtex;
- struct r600_surface *surf;
- unsigned level, pitch, slice, format, tile_mode_index, array_mode;
+ struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
+ unsigned level = surf->base.u.tex.level;
+ unsigned pitch, slice, format, tile_mode_index, array_mode;
unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks,
pipe_config;
uint32_t z_info, s_info, db_depth_info;
uint64_t z_offs, s_offs;
uint32_t db_htile_data_base, db_htile_surface,
pa_su_poly_offset_db_fmt_cntl;
- if (state->zsbuf == NULL) {
- si_pm4_set_reg(pm4, R_028040_DB_Z_INFO,
S_028040_FORMAT(V_028040_Z_INVALID));
- si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO,
S_028044_FORMAT(V_028044_STENCIL_INVALID));
- return;
- }
-
- surf = (struct r600_surface *)state->zsbuf;
- level = surf->base.u.tex.level;
- rtex = (struct r600_texture*)surf->base.texture;
-
- format = si_translate_dbformat(rtex->resource.b.b.format);
-
switch (sctx->framebuffer.zsbuf->texture->format) {
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
case PIPE_FORMAT_X8Z24_UNORM:
@@ -1774,6 +1762,8 @@ static void si_db(struct si_context *sctx, struct
si_pm4_state *pm4,
assert(0);
}
+ format = si_translate_dbformat(rtex->resource.b.b.format);
+
if (format == V_028040_Z_INVALID) {
R600_ERR("Invalid DB format: %d, disabling DB.\n",
rtex->resource.b.b.format);
}
@@ -1783,9 +1773,6 @@ static void si_db(struct si_context *sctx, struct
si_pm4_state *pm4,
z_offs += rtex->surface.level[level].offset;
s_offs += rtex->surface.stencil_level[level].offset;
- z_offs >>= 8;
- s_offs >>= 8;
-
pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
slice = (rtex->surface.level[level].nblk_x *
rtex->surface.level[level].nblk_y) / 64;
if (slice) {
@@ -1867,33 +1854,25 @@ static void si_db(struct si_context *sctx, struct
si_pm4_state *pm4,
uint64_t va = r600_resource_va(&sctx->screen->b.b,
&rtex->htile_buffer->b.b);
db_htile_data_base = va >> 8;
db_htile_surface = S_028ABC_FULL_CACHE(1);
-
- si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE);
} else {
db_htile_data_base = 0;
db_htile_surface = 0;
}
- si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
- S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
- S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
- si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
-
- si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
- si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
- si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
+ surf->db_depth_view =
S_028008_SLICE_START(surf->base.u.tex.first_layer) |
+ S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
+ surf->db_htile_data_base = db_htile_data_base;
+ surf->db_depth_info = db_depth_info;
+ surf->db_z_info = z_info;
+ surf->db_stencil_info = s_info;
+ surf->db_depth_base = z_offs >> 8;
+ surf->db_stencil_base = s_offs >> 8;
+ surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
+ surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
+ surf->db_htile_surface = db_htile_surface;
+ surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
- si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
- si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
- si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
- si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
- si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
-
- si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE,
S_028058_PITCH_TILE_MAX(pitch));
- si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE,
S_02805C_SLICE_TILE_MAX(slice));
-
- si_pm4_set_
[Mesa-dev] [PATCH 05/10] r600g: remove r600_resource.h
From: Marek Olšák
---
src/gallium/drivers/r600/compute_memory_pool.c | 1 -
src/gallium/drivers/r600/evergreen_compute.c | 1 -
src/gallium/drivers/r600/evergreen_compute.h | 7
src/gallium/drivers/r600/r600_pipe.h | 9 +-
src/gallium/drivers/r600/r600_resource.h | 45 --
5 files changed, 15 insertions(+), 48 deletions(-)
delete mode 100644 src/gallium/drivers/r600/r600_resource.h
diff --git a/src/gallium/drivers/r600/compute_memory_pool.c
b/src/gallium/drivers/r600/compute_memory_pool.c
index fd3a04c..90d5358 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.c
+++ b/src/gallium/drivers/r600/compute_memory_pool.c
@@ -33,7 +33,6 @@
#include "util/u_memory.h"
#include "util/u_inlines.h"
#include "util/u_framebuffer.h"
-#include "r600_resource.h"
#include "r600_shader.h"
#include "r600_pipe.h"
#include "r600_formats.h"
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 70efe5c..4a20405 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -39,7 +39,6 @@
#include "util/u_framebuffer.h"
#include "pipebuffer/pb_buffer.h"
#include "evergreend.h"
-#include "r600_resource.h"
#include "r600_shader.h"
#include "r600_pipe.h"
#include "r600_formats.h"
diff --git a/src/gallium/drivers/r600/evergreen_compute.h
b/src/gallium/drivers/r600/evergreen_compute.h
index e6c6d8f..e760790 100644
--- a/src/gallium/drivers/r600/evergreen_compute.h
+++ b/src/gallium/drivers/r600/evergreen_compute.h
@@ -26,10 +26,17 @@
#ifndef EVERGREEN_COMPUTE_H
#define EVERGREEN_COMPUTE_H
+
#include "r600_pipe.h"
struct r600_atom;
struct evergreen_compute_resource;
+struct compute_memory_item;
+
+struct r600_resource_global {
+ struct r600_resource base;
+ struct compute_memory_item *chunk;
+};
void *evergreen_create_compute_state(struct pipe_context *ctx, const struct
pipe_compute_state *cso);
void evergreen_delete_compute_state(struct pipe_context *ctx, void *state);
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 9f27a17..e732958 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -31,7 +31,6 @@
#include "r600_llvm.h"
#include "r600_public.h"
-#include "r600_resource.h"
#include "util/u_blitter.h"
#include "util/u_suballoc.h"
@@ -842,4 +841,12 @@ static INLINE unsigned r600_pack_float_12p4(float x)
x >= 4096 ? 0x : x * 16;
}
+/* Return if the depth format can be read without the DB->CB copy on
r6xx-r7xx. */
+static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
+{
+ return rtex->resource.b.b.nr_samples <= 1 &&
+ (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
+ rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
+}
+
#endif
diff --git a/src/gallium/drivers/r600/r600_resource.h
b/src/gallium/drivers/r600/r600_resource.h
deleted file mode 100644
index ae0bd88..000
--- a/src/gallium/drivers/r600/r600_resource.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright 2010 Marek Olšák CB copy on
r6xx-r7xx. */
-static INLINE bool r600_can_read_depth(struct r600_texture *rtex)
-{
- return rtex->resource.b.b.nr_samples <= 1 &&
- (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
- rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT);
-}
-
-#endif
--
1.8.3.2
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 03/10] r600g: use r600_surface::db_z_info
From: Marek Olšák
db_z_info was unused. This just renames the variable to match the register
name.
Now, db_depth_info is unused on Evergreen.
Both variables will be needed on SI though.
---
src/gallium/drivers/r600/evergreen_state.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index c86e812..82baa0f 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1636,15 +1636,15 @@ static void evergreen_init_depth_surface(struct
r600_context *rctx,
nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
offset >>= 8;
- surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
- S_028040_FORMAT(format) |
- S_028040_TILE_SPLIT(tile_split)|
- S_028040_NUM_BANKS(nbanks) |
- S_028040_BANK_WIDTH(bankw) |
- S_028040_BANK_HEIGHT(bankh) |
- S_028040_MACRO_TILE_ASPECT(macro_aspect);
+ surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
+ S_028040_FORMAT(format) |
+ S_028040_TILE_SPLIT(tile_split)|
+ S_028040_NUM_BANKS(nbanks) |
+ S_028040_BANK_WIDTH(bankw) |
+ S_028040_BANK_HEIGHT(bankh) |
+ S_028040_MACRO_TILE_ASPECT(macro_aspect);
if (rscreen->b.chip_class == CAYMAN && rtex->resource.b.b.nr_samples >
1) {
- surf->db_depth_info |=
S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
+ surf->db_z_info |=
S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
}
surf->db_depth_base = offset;
surf->db_depth_view =
S_028008_SLICE_START(surf->base.u.tex.first_layer) |
@@ -1704,7 +1704,7 @@ static void evergreen_init_depth_surface(struct
r600_context *rctx,
S_028ABC_HTILE_HEIGHT(1) |
S_028ABC_FULL_CACHE(1) |
S_028ABC_LINEAR(1);
- surf->db_depth_info |= S_028040_TILE_SURFACE_ENABLE(1);
+ surf->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
surf->db_preload_control = 0;
}
@@ -2274,7 +2274,7 @@ static void evergreen_emit_framebuffer_state(struct
r600_context *rctx, struct r
r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW,
zb->db_depth_view);
r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
- radeon_emit(cs, zb->db_depth_info); /* R_028040_DB_Z_INFO */
+ radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
radeon_emit(cs, zb->db_stencil_info); /*
R_028044_DB_STENCIL_INFO */
radeon_emit(cs, zb->db_depth_base); /*
R_028048_DB_Z_READ_BASE */
radeon_emit(cs, zb->db_stencil_base); /*
R_02804C_DB_STENCIL_READ_BASE */
--
1.8.3.2
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 04/10] r600g: remove r600_surface::htile_enabled
From: Marek Olšák
We can just use the base address register instead.
---
src/gallium/drivers/r600/evergreen_state.c| 6 ++
src/gallium/drivers/r600/r600_state.c | 6 ++
src/gallium/drivers/radeon/r600_pipe_common.h | 2 --
3 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 82baa0f..3dd576b 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1694,11 +1694,9 @@ static void evergreen_init_depth_surface(struct
r600_context *rctx,
S_028044_FORMAT(V_028044_STENCIL_8);
}
- surf->htile_enabled = 0;
/* use htile only for first level */
if (rtex->htile_buffer && !level) {
uint64_t va = r600_resource_va(&rctx->screen->b.b,
&rtex->htile_buffer->b.b);
- surf->htile_enabled = 1;
surf->db_htile_data_base = va >> 8;
surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
S_028ABC_HTILE_HEIGHT(1) |
@@ -2368,7 +2366,7 @@ static void evergreen_emit_db_state(struct r600_context
*rctx, struct r600_atom
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_db_state *a = (struct r600_db_state*)atom;
- if (a->rsurf && a->rsurf->htile_enabled) {
+ if (a->rsurf && a->rsurf->db_htile_data_base) {
struct r600_texture *rtex = (struct r600_texture
*)a->rsurf->base.texture;
unsigned reloc_idx;
@@ -2409,7 +2407,7 @@ static void evergreen_emit_db_misc_state(struct
r600_context *rctx, struct r600_
*
* Disable hyperz for now if not writing to zbuffer.
*/
- if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled &&
rctx->zwritemask) {
+ if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_data_base &&
rctx->zwritemask) {
/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL
*/
db_render_override |=
S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
/* This is to fix a lockup when hyperz and alpha test are
enabled at
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 0dfd426..815ed1f 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1530,11 +1530,9 @@ static void r600_init_depth_surface(struct r600_context
*rctx,
default:;
}
- surf->htile_enabled = 0;
/* use htile only for first level */
if (rtex->htile_buffer && !level) {
uint64_t va = r600_resource_va(&rctx->screen->b.b,
&rtex->htile_buffer->b.b);
- surf->htile_enabled = 1;
surf->db_htile_data_base = va >> 8;
surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
S_028D24_HTILE_HEIGHT(1) |
@@ -1993,7 +1991,7 @@ static void r600_emit_db_state(struct r600_context *rctx,
struct r600_atom *atom
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_db_state *a = (struct r600_db_state*)atom;
- if (a->rsurf && a->rsurf->htile_enabled) {
+ if (a->rsurf && a->rsurf->db_htile_data_base) {
struct r600_texture *rtex = (struct r600_texture
*)a->rsurf->base.texture;
unsigned reloc_idx;
@@ -2023,7 +2021,7 @@ static void r600_emit_db_misc_state(struct r600_context
*rctx, struct r600_atom
}
db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
}
- if (rctx->db_state.rsurf && rctx->db_state.rsurf->htile_enabled) {
+ if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_data_base) {
/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL
*/
db_render_override |=
S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
/* This is to fix a lockup when hyperz and alpha test are
enabled at
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 38c784a..9569c03 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -201,8 +201,6 @@ struct r600_surface {
unsigned db_htile_data_base;
unsigned db_preload_control;/* EG and later */
unsigned pa_su_poly_offset_db_fmt_cntl;
-
- unsigned htile_enabled; /* XXX remove */
};
struct r600_tiling_info {
--
1.8.3.2
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 10/10] r600g, radeonsi: consolidate create_surface and surface_destroy
From: Marek Olšák
---
src/gallium/drivers/r600/r600_state_common.c | 44 ---
src/gallium/drivers/radeon/r600_pipe_common.c | 3 +-
src/gallium/drivers/radeon/r600_pipe_common.h | 7 +++-
src/gallium/drivers/radeon/r600_texture.c | 52 ++-
src/gallium/drivers/radeonsi/si_blit.c| 5 ++-
src/gallium/drivers/radeonsi/si_state.c | 37 ---
6 files changed, 63 insertions(+), 85 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 22f2b06..7b0d772 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1722,48 +1722,6 @@ void r600_emit_shader(struct r600_context *rctx, struct
r600_atom *a)
radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
shader->bo, RADEON_USAGE_READ));
}
-struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
- struct pipe_resource *texture,
- const struct pipe_surface
*templ,
- unsigned width, unsigned height)
-{
- struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
-
-assert(templ->u.tex.first_layer <= util_max_layer(texture,
templ->u.tex.level));
-assert(templ->u.tex.last_layer <= util_max_layer(texture,
templ->u.tex.level));
- if (surface == NULL)
- return NULL;
- pipe_reference_init(&surface->base.reference, 1);
- pipe_resource_reference(&surface->base.texture, texture);
- surface->base.context = pipe;
- surface->base.format = templ->format;
- surface->base.width = width;
- surface->base.height = height;
- surface->base.u = templ->u;
- return &surface->base;
-}
-
-static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
- struct pipe_resource *tex,
- const struct pipe_surface
*templ)
-{
- unsigned level = templ->u.tex.level;
-
- return r600_create_surface_custom(pipe, tex, templ,
- u_minify(tex->width0, level),
- u_minify(tex->height0, level));
-}
-
-static void r600_surface_destroy(struct pipe_context *pipe,
-struct pipe_surface *surface)
-{
- struct r600_surface *surf = (struct r600_surface*)surface;
- pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
NULL);
- pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
NULL);
- pipe_resource_reference(&surface->texture, NULL);
- FREE(surface);
-}
-
unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
const unsigned char *swizzle_view,
boolean vtx)
@@ -2275,8 +2233,6 @@ void r600_init_common_state_functions(struct r600_context
*rctx)
rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
rctx->b.b.texture_barrier = r600_texture_barrier;
rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
- rctx->b.b.create_surface = r600_create_surface;
- rctx->b.b.surface_destroy = r600_surface_destroy;
rctx->b.b.draw_vbo = r600_draw_vbo;
rctx->b.invalidate_buffer = r600_invalidate_buffer;
rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 6fb3d38..05842aa 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -62,6 +62,7 @@ bool r600_common_context_init(struct r600_common_context
*rctx,
rctx->b.transfer_inline_write = u_default_transfer_inline_write;
rctx->b.memory_barrier = r600_memory_barrier;
+ r600_init_context_texture_functions(rctx);
r600_streamout_init(rctx);
r600_query_init(rctx);
@@ -613,7 +614,7 @@ bool r600_common_screen_init(struct r600_common_screen
*rscreen,
rscreen->b.is_video_format_supported =
vl_video_buffer_is_format_supported;
}
- r600_init_texture_functions(rscreen);
+ r600_init_screen_texture_functions(rscreen);
rscreen->ws = ws;
rscreen->family = rscreen->info.family;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 9569c03..e2ca18f 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -415,7 +415,12 @@ bool r600_init_flushed_depth_texture(struct pipe_context
*ctx,
struct r600_texture **staging);
struct pipe_resource *r600_tex
[Mesa-dev] [PATCH 09/10] radeonsi: inline util_blitter_copy_texture
From: Marek Olšák
This will be used for changing texture properties without modifying
pipe_resource like r600g, but not in this series. For now, this change
allows consolidation of pipe_surface functions.
---
src/gallium/drivers/radeonsi/si_blit.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 8bfa6ed..07396e7 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -483,8 +483,10 @@ static void si_resource_copy_region(struct pipe_context
*ctx,
const struct pipe_box *src_box)
{
struct si_context *sctx = (struct si_context *)ctx;
+ struct pipe_surface *dst_view, dst_templ;
+ struct pipe_sampler_view src_templ, *src_view;
struct texture_orig_info orig_info[2];
- struct pipe_box sbox;
+ struct pipe_box sbox, dstbox;
boolean restore_orig[2];
/* Fallback for buffers. */
@@ -562,11 +564,27 @@ static void si_resource_copy_region(struct pipe_context
*ctx,
restore_orig[1] = TRUE;
}
+ /* Initialize the surface. */
+ util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
+ dst_view = ctx->create_surface(ctx, dst, &dst_templ);
+
+ /* Initialize the sampler view. */
+ util_blitter_default_src_texture(&src_templ, src, src_level);
+ src_view = ctx->create_sampler_view(ctx, src, &src_templ);
+
+ u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
+abs(src_box->depth), &dstbox);
+
+ /* Copy. */
si_blitter_begin(ctx, SI_COPY);
- util_blitter_copy_texture(sctx->blitter, dst, dst_level, dstx, dsty,
dstz,
- src, src_level, src_box);
+ util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
+ src_view, src_box, src->width0, src->height0,
+ PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST,
NULL);
si_blitter_end(ctx);
+ pipe_surface_reference(&dst_view, NULL);
+ pipe_sampler_view_reference(&src_view, NULL);
+
if (restore_orig[0])
si_reset_blittable_to_orig(src, src_level, &orig_info[0]);
--
1.8.3.2
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 06/10] radeonsi: compute color surface registers only once
From: Marek Olšák
Same as r600g.
---
src/gallium/drivers/radeonsi/si_state.c | 99 ++---
1 file changed, 55 insertions(+), 44 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 0154e58..89b4242 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1572,37 +1572,31 @@ static unsigned si_tile_mode_index(struct r600_texture
*rtex, unsigned level, bo
* framebuffer handling
*/
-static void si_cb(struct si_context *sctx, struct si_pm4_state *pm4,
- const struct pipe_framebuffer_state *state, int cb)
+static void si_initialize_color_surface(struct si_context *sctx,
+ struct r600_surface *surf)
{
- struct r600_texture *rtex;
- struct r600_surface *surf;
- unsigned level = state->cbufs[cb]->u.tex.level;
+ struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
+ unsigned level = surf->base.u.tex.level;
+ uint64_t offset = rtex->surface.level[level].offset;
unsigned pitch, slice;
unsigned color_info, color_attrib, color_pitch, color_view;
unsigned tile_mode_index;
unsigned format, swap, ntype, endian;
- uint64_t offset;
const struct util_format_description *desc;
int i;
unsigned blend_clamp = 0, blend_bypass = 0;
unsigned max_comp_size;
- surf = (struct r600_surface *)state->cbufs[cb];
- rtex = (struct r600_texture*)state->cbufs[cb]->texture;
-
- offset = rtex->surface.level[level].offset;
-
/* Layered rendering doesn't work with LINEAR_GENERAL.
* (LINEAR_ALIGNED and others work) */
if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
- assert(state->cbufs[cb]->u.tex.first_layer ==
state->cbufs[cb]->u.tex.last_layer);
+ assert(surf->base.u.tex.first_layer ==
surf->base.u.tex.last_layer);
offset += rtex->surface.level[level].slice_size *
- state->cbufs[cb]->u.tex.first_layer;
+ surf->base.u.tex.first_layer;
color_view = 0;
} else {
- color_view =
S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
-
S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer);
+ color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer)
|
+S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
}
pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
@@ -1707,34 +1701,22 @@ static void si_cb(struct si_context *sctx, struct
si_pm4_state *pm4,
color_info |= S_028C70_FAST_CLEAR(1);
}
- offset += r600_resource_va(sctx->b.b.screen, state->cbufs[cb]->texture);
- offset >>= 8;
+ offset += r600_resource_va(sctx->b.b.screen, surf->base.texture);
- si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
- si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
- si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch);
- si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
S_028C68_TILE_MAX(slice));
- si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, color_view);
- si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
- si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
color_attrib);
+ surf->cb_color_base = offset >> 8;
+ surf->cb_color_pitch = color_pitch;
+ surf->cb_color_slice = S_028C68_TILE_MAX(slice);
+ surf->cb_color_view = color_view;
+ surf->cb_color_info = color_info;
+ surf->cb_color_attrib = color_attrib;
if (rtex->cmask.size) {
- si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
- offset + (rtex->cmask.offset >> 8));
- si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
- S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
+ surf->cb_color_cmask = (offset + rtex->cmask.offset) >> 8;
+ surf->cb_color_cmask_slice =
S_028C80_TILE_MAX(rtex->cmask.slice_tile_max);
}
if (rtex->fmask.size) {
- si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
- offset + (rtex->fmask.offset >> 8));
- si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
- S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
- }
-
- /* set CB_COLOR1_INFO for possible dual-src blending */
- if (state->nr_cbufs == 1) {
- assert(cb == 0);
- si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
color_info);
+ surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
+
[Mesa-dev] [PATCH 08/10] radeonsi: remove useless psbox variable from resource_copy_region
From: Marek Olšák --- src/gallium/drivers/radeonsi/si_blit.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index bf76ecf..8bfa6ed 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -485,7 +485,6 @@ static void si_resource_copy_region(struct pipe_context *ctx, struct si_context *sctx = (struct si_context *)ctx; struct texture_orig_info orig_info[2]; struct pipe_box sbox; - const struct pipe_box *psbox = src_box; boolean restore_orig[2]; /* Fallback for buffers. */ @@ -513,7 +512,7 @@ static void si_resource_copy_region(struct pipe_context *ctx, sbox.width = util_format_get_nblocksx(orig_info[0].format, src_box->width); sbox.height = util_format_get_nblocksy(orig_info[0].format, src_box->height); sbox.depth = src_box->depth; - psbox=&sbox; + src_box = &sbox; si_compressed_to_blittable(dst, dst_level, &orig_info[1]); restore_orig[1] = TRUE; @@ -565,7 +564,7 @@ static void si_resource_copy_region(struct pipe_context *ctx, si_blitter_begin(ctx, SI_COPY); util_blitter_copy_texture(sctx->blitter, dst, dst_level, dstx, dsty, dstz, - src, src_level, psbox); + src, src_level, src_box); si_blitter_end(ctx); if (restore_orig[0]) -- 1.8.3.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 01/10] radeonsi: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to framebuffer state
FORMAT_X8Z24_UNORM: > + case PIPE_FORMAT_Z24X8_UNORM: > + case PIPE_FORMAT_Z24_UNORM_S8_UINT: > + pa_su_poly_offset_db_fmt_cntl = > S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24); > + break; > + case PIPE_FORMAT_Z32_FLOAT: > + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: > + pa_su_poly_offset_db_fmt_cntl = > S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | > + > S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); > + break; I don't know much about SI, but this jumped out as weird -- shouldn't that be -32? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 01/10] radeonsi: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to framebuffer state
[Possibly ignore that, I guess it's the negated number of mantissa bits] On Tue, Feb 11, 2014 at 3:39 PM, Chris Forbes wrote: > FORMAT_X8Z24_UNORM: >> + case PIPE_FORMAT_Z24X8_UNORM: >> + case PIPE_FORMAT_Z24_UNORM_S8_UINT: >> + pa_su_poly_offset_db_fmt_cntl = >> S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24); >> + break; >> + case PIPE_FORMAT_Z32_FLOAT: >> + case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: >> + pa_su_poly_offset_db_fmt_cntl = >> S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | >> + >> S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); >> + break; > > I don't know much about SI, but this jumped out as weird -- shouldn't > that be -32? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] R600/SI: Split global vector loads with more than 4 elements
Hi Tom,
This definitely fixes some issues that I've been seeing with int8/16
vload8() and vload16() in CL. vstore8/vstore16 are still broken, but
at least the loads are working now (I've only tested int, but I can
give a full test run if you want/need).
For reference, the tests that failed before were in:
piglit/test/cl/program/execute/vload-int.cl
comment out the vload3 tests to get the rest to work. Previously int3,
int8, and int16 all failed, now just the int3 tests fail to build.
If you're curious, the vstore issues start like the following and can
be reproduced with the attached test case:
LLVM ERROR: Cannot select: 0x12fa1b0: v4i32 = extract_subvector
0x1c55240, 0x12f8ba0 [ORD=28] [ID=38]
0x1c55240: v8i32 = BUILD_VECTOR 0x1c55140, 0x12f7a90, 0x12f7f90,
0x12f8490, 0x12f8aa0, 0x12f8fa0, 0x12f94a0, 0x12f9ab0 [ORD=24] [ID=35]
--Aaron
On Mon, Feb 10, 2014 at 3:32 PM, Tom Stellard wrote:
> From: Tom Stellard
>
> ---
> lib/Target/R600/SIISelLowering.cpp | 8 +-
> test/CodeGen/R600/load.ll | 178
> +++--
> 2 files changed, 98 insertions(+), 88 deletions(-)
>
> diff --git a/lib/Target/R600/SIISelLowering.cpp
> b/lib/Target/R600/SIISelLowering.cpp
> index 9537405..eb08a13 100644
> --- a/lib/Target/R600/SIISelLowering.cpp
> +++ b/lib/Target/R600/SIISelLowering.cpp
> @@ -478,9 +478,11 @@ SDValue SITargetLowering::LowerOperation(SDValue Op,
> SelectionDAG &DAG) const {
>case ISD::BRCOND: return LowerBRCOND(Op, DAG);
>case ISD::LOAD: {
> LoadSDNode *Load = dyn_cast(Op);
> -if ((Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
> - Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
> -Op.getValueType().isVector()) {
> +if (Op.getValueType().isVector() &&
> +(Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
> + Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
> + (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
> + Op.getValueType().getVectorNumElements() > 4))) {
>SDValue MergedValues[2] = {
> SplitVectorLoad(Op, DAG),
> Load->getChain()
> diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll
> index 0153524..1486c4d 100644
> --- a/test/CodeGen/R600/load.ll
> +++ b/test/CodeGen/R600/load.ll
> @@ -1,16 +1,15 @@
> -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck
> --check-prefix=R600-CHECK %s
> -; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck
> --check-prefix=R600-CHECK %s
> -; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck
> --check-prefix=SI-CHECK %s
> +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck
> --check-prefix=R600-CHECK --check-prefix=FUNC %s
> +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck
> --check-prefix=R600-CHECK --check-prefix=FUNC %s
> +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck
> --check-prefix=SI-CHECK --check-prefix=FUNC %s
>
>
> ;======;
> ; GLOBAL ADDRESS SPACE
>
> ;======;
>
> ; Load an i8 value from the global address space.
> -; R600-CHECK-LABEL: @load_i8
> +; FUNC-LABEL: @load_i8
> ; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
>
> -; SI-CHECK-LABEL: @load_i8
> ; SI-CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}},
> define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
>%1 = load i8 addrspace(1)* %in
> @@ -19,13 +18,12 @@ define void @load_i8(i32 addrspace(1)* %out, i8
> addrspace(1)* %in) {
>ret void
> }
>
> -; R600-CHECK-LABEL: @load_i8_sext
> +; FUNC-LABEL: @load_i8_sext
> ; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
> ; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
> ; R600-CHECK: 24
> ; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
> ; R600-CHECK: 24
> -; SI-CHECK-LABEL: @load_i8_sext
> ; SI-CHECK: BUFFER_LOAD_SBYTE
> define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
> entry:
> @@ -35,10 +33,9 @@ entry:
>ret void
> }
>
> -; R600-CHECK-LABEL: @load_v2i8
> +; FUNC-LABEL: @load_v2i8
> ; R600-CHECK: VTX_READ_8
> ; R600-CHECK: VTX_READ_8
> -; SI-CHECK-LABEL: @load_v2i8
> ; SI-CHECK: BUFFER_LOAD_UBYTE
> ; SI-CHECK: BUFFER_LOAD_UBYTE
> define void @load_v2i8(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)*
> %in) {
> @@ -49,7 +46,7 @@ entry:
>ret void
> }
>
> -; R600-CHECK-LABEL: @load_v2i8_sext
> +; FUNC-LABEL: @load_v2i8_sext
> ; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]]
> ; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]]
> ; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]]
> @@ -60,7 +57,6 @@ entry:
> ; R600-CHECK-DAG: 24
> ; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]]
> ; R600-CHECK-DAG: 24
> -; SI-CHECK-LABEL: @load_v2i8_sext
> ; SI-CHECK: BUFFER_LOAD_SBYT
Re: [Mesa-dev] [PATCH 3/3] st/mesa: add texture gather support. (v2)
Just one (probably) trivial comment below:
On Mon, Feb 10, 2014 at 8:43 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This adds support for GL_ARB_texture_gather, and one step of
> support for GL_ARB_gpu_shader5.
>
> This adds support for passing the TG4 instruction, along
> with non-constant texture offsets, and tracking them for the
> optimisation passes.
>
> This doesn't support native textureGatherOffsets hw, to do that
> you'd need to add a CAP and if set disable the lowering pass,
> and bump the MAX offsets to 4, then do the i0,j0 sampling using
> those.
>
> Signed-off-by: Dave Airlie
> ---
> src/mesa/state_tracker/st_extensions.c | 4 +
> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 117
> ++---
> 2 files changed, 94 insertions(+), 27 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 610fc68..0db770e 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -4079,7 +4128,7 @@ struct st_translate {
> struct ureg_dst address[2];
> struct ureg_src samplers[PIPE_MAX_SAMPLERS];
> struct ureg_src systemValues[SYSTEM_VALUE_MAX];
> -
> + struct tgsi_texture_offset tex_offsets[MAX_GLSL_TEXTURE_OFFSET];
> unsigned array_sizes[MAX_ARRAYS];
>
> const GLuint *inputMapping;
> @@ -4379,22 +4428,34 @@ translate_src(struct st_translate *t, const
> st_src_reg *src_reg)
>
> static struct tgsi_texture_offset
> translate_tex_offset(struct st_translate *t,
> - const struct tgsi_texture_offset *in_offset)
> + const st_src_reg *in_offset, int idx)
idx does not appear to get used... did you mean to use it, or
left-over code change?
> {
> struct tgsi_texture_offset offset;
> struct ureg_src imm_src;
>
> - assert(in_offset->File == PROGRAM_IMMEDIATE);
> - imm_src = t->immediates[in_offset->Index];
> -
> - offset.File = imm_src.File;
> - offset.Index = imm_src.Index;
> - offset.SwizzleX = imm_src.SwizzleX;
> - offset.SwizzleY = imm_src.SwizzleY;
> - offset.SwizzleZ = imm_src.SwizzleZ;
> - offset.File = TGSI_FILE_IMMEDIATE;
> - offset.Padding = 0;
> -
> + switch (in_offset->file) {
> + case PROGRAM_IMMEDIATE:
> + imm_src = t->immediates[in_offset->index];
> +
> + offset.File = imm_src.File;
> + offset.Index = imm_src.Index;
> + offset.SwizzleX = imm_src.SwizzleX;
> + offset.SwizzleY = imm_src.SwizzleY;
> + offset.SwizzleZ = imm_src.SwizzleZ;
> + offset.Padding = 0;
> + break;
> + case PROGRAM_TEMPORARY:
> + imm_src = ureg_src(t->temps[in_offset->index]);
> + offset.File = imm_src.File;
> + offset.Index = imm_src.Index;
> + offset.SwizzleX = GET_SWZ(in_offset->swizzle, 0);
> + offset.SwizzleY = GET_SWZ(in_offset->swizzle, 1);
> + offset.SwizzleZ = GET_SWZ(in_offset->swizzle, 2);
> + offset.Padding = 0;
> + break;
> + default:
> + break;
> + }
> return offset;
> }
>
> @@ -4450,9 +4511,10 @@ compile_tgsi_instruction(struct st_translate *t,
> case TGSI_OPCODE_TEX2:
> case TGSI_OPCODE_TXB2:
> case TGSI_OPCODE_TXL2:
> + case TGSI_OPCODE_TG4:
>src[num_src++] = t->samplers[inst->sampler];
>for (i = 0; i < inst->tex_offset_num_offset; i++) {
> - texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
> + texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i], i);
and so this new parameter wouldn't be needed either.
-ilia
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/3] st/mesa: add texture gather support. (v2)
>> const GLuint *inputMapping;
>> @@ -4379,22 +4428,34 @@ translate_src(struct st_translate *t, const
>> st_src_reg *src_reg)
>>
>> static struct tgsi_texture_offset
>> translate_tex_offset(struct st_translate *t,
>> - const struct tgsi_texture_offset *in_offset)
>> + const st_src_reg *in_offset, int idx)
>
> idx does not appear to get used... did you mean to use it, or
> left-over code change?
Oh indeed that was for when I had array support here, which I ripped
out for the lowering pass.
>>src[num_src++] = t->samplers[inst->sampler];
>>for (i = 0; i < inst->tex_offset_num_offset; i++) {
>> - texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i]);
>> + texoffsets[i] = translate_tex_offset(t, &inst->tex_offsets[i], i);
>
> and so this new parameter wouldn't be needed either.
Good point.
Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 01/13] targets/pipe-loader: link pipe-nouveau against libdrm
Signed-off-by: Emil Velikov --- src/gallium/targets/pipe-loader/Makefile.am | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/targets/pipe-loader/Makefile.am b/src/gallium/targets/pipe-loader/Makefile.am index 97733c1..cb2eff7 100644 --- a/src/gallium/targets/pipe-loader/Makefile.am +++ b/src/gallium/targets/pipe-loader/Makefile.am @@ -72,6 +72,7 @@ pipe_nouveau_la_LIBADD = \ $(PIPE_LIBS) \ $(top_builddir)/src/gallium/winsys/nouveau/drm/libnouveaudrm.la \ $(top_builddir)/src/gallium/drivers/nouveau/libnouveau.la \ + $(LIBDRM_LIBS) \ $(NOUVEAU_LIBS) pipe_nouveau_la_LDFLAGS = -no-undefined -avoid-version -module if HAVE_MESA_LLVM -- 1.8.5.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] Convert vdpau and dri targets to the pipe-loader
Hello list, The recent patches from Rob gave me a nice kick to give another stab at integrating the pipe-loader into the vdpau/dri targets. What: - With these patches one library will be created for hardware and one for software driven backends - eg. libvdpau_gallium_dri, libvdpau_gallium_sw - Each library can use every possible pipe driver, determined at runtime. - To get the dri (galliumdrm_dri) or vdpau library working create hardlink (or symlink) to it (libvdpau_nouveau.so -> libvdpau_gallium_dri.so) Why: - Smaller overall size while having no extra exported symbols. This is a nice method of us to share most of gallium (read mesagallium and aux/gallium) without exporting every symbol either one to those two contain. - Drop the multiple duplicated - With those done, some additional symbol cleanup can be made using the linker. The stripped size of pipe_nouveau and pipe_swrast decreased by ~0.6MiB, downto 2.2, 1.2MiB accordingly. With similar results on other libaries. What has been tested: - (st/dri) nouveau and swrast were spinning glxgears and nouveau was glretrace-ing lol, dota2 and portal traces. - (st/vdpau) nouveau - tested using mplayer in benchmark mode. no significant changes were noticed. swrast was broken while using vdpau, as to why it was dropped a while back. What has not been tested/known to be broken: - (st/dri) currently the drm_configuration() and the driver options (__dri2ConfigOptions) are not wired up. - (st/vdpau) the driver specific create_winsys are not exported by the vdpau library, thus gl-vdpau interop is not tested and possibly broken. - Resolve all the linking between the library and all backends nouveau_dri.so -> galliumdrm_dri.so - Scons and drivers having multiple winsys (i915) In the weeks ahead: - Cleanup/resolve the above issues - Tackle the remaining two st (omx and xvmc), which should be trivial. - Compact the dri/drm and dri/sw state-trackers into a single library. Please let me know how you feel on the subject, and as ususal some testing including opencl, gbm, egl and gl-vdpau interop would be greatly appreciated. The complete patchset can be found in the pipe-loader-to-all branch over at https://github.com/evelikov/Mesa/ Note: the first 10 patches should be fine as is as. Cheers, Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 05/13] pipe-loader: handle memory allocation failure
Signed-off-by: Emil Velikov
---
src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c | 3 +++
src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
index 16f8a58..c5f191f 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
@@ -118,6 +118,9 @@ pipe_loader_drm_probe_fd(struct pipe_loader_device **dev,
int fd)
struct pipe_loader_drm_device *ddev = CALLOC_STRUCT(pipe_loader_drm_device);
int vendor_id, chip_id;
+ if (!ddev)
+ return FALSE;
+
if (loader_get_pci_id_for_fd(fd, &vendor_id, &chip_id)) {
ddev->base.type = PIPE_LOADER_DEVICE_PCI;
ddev->base.u.pci.vendor_id = vendor_id;
diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
index fd3d989..7f3f93b 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
@@ -58,6 +58,7 @@ pipe_loader_sw_probe(struct pipe_loader_device **devs, int
ndev)
for (i = 0; i < Elements(backends); i++) {
if (i < ndev) {
struct pipe_loader_sw_device *sdev =
CALLOC_STRUCT(pipe_loader_sw_device);
+/* TODO: handle CALLOC_STRUCT failure */
sdev->base.type = PIPE_LOADER_DEVICE_SOFTWARE;
sdev->base.driver_name = "swrast";
--
1.8.5.4
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 04/13] pipe-loader: build pipe_loader_drm_x_auth whenever HAVE_PIPE_LOADER_XCB is defined
Currently HAVE_PIPE_LOADER_XCB is defined, rather than being set to 1/0.
Signed-off-by: Emil Velikov
---
src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
index d6869fd..16f8a58 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
@@ -62,7 +62,7 @@ static struct pipe_loader_ops pipe_loader_drm_ops;
static void
pipe_loader_drm_x_auth(int fd)
{
-#if HAVE_PIPE_LOADER_XCB
+#ifdef HAVE_PIPE_LOADER_XCB
/* Try authenticate with the X server to give us access to devices that X
* is running on. */
xcb_connection_t *xcb_conn;
--
1.8.5.4
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
