Re: [Mesa-dev] [PATCH][RFC] dri3: Add support for the GLX_EXT_buffer_age extension
Am 20.02.2014 02:59, schrieb Ian Romanick:
On 02/19/2014 02:49 PM, Adel Gadllah wrote:
Hi,
The attached patch adds support for the GLX_EXT_buffer_age extension,
which is mostly used by compositors for efficient sub screen updates.
The extension should not be reported as supported when running DRI2 but
it seems to show up when I try to disable it with LIBGL_DRI3_DISABLE ...
not sure why suggestions welcome.
P.S: Please CC me when replying as I am not subscribed to the list.
You'll need to fix that. :)
Done.
You didn't send this patch with git-send-email. Whatever you used to
send it also mangled it, so it won't apply.
Yeah sorry for that git send-mail complained about the SSL cert so I just used
Thunderbird .. which didn't work well. I have fixed the SSL issue so next
version
will be sent using git send-mail.
+ * GLX_EXT_buffer_age
+ */
+#define GLX_BACK_BUFFER_AGE_EXT 0x20F4
+
typedef struct __GLXcontextRec *GLXContext;
typedef XID GLXPixmap;
diff --git a/include/GL/glxext.h b/include/GL/glxext.h
index 8c642f3..36e92dc 100644
--- a/include/GL/glxext.h
+++ b/include/GL/glxext.h
@@ -383,6 +383,11 @@ void glXReleaseTexImageEXT (Display *dpy,
GLXDrawable drawable, int buffer);
#define GLX_FLIP_COMPLETE_INTEL 0x8182
#endif /* GLX_INTEL_swap_event */
+#ifndef GLX_EXT_buffer_age
+#define GLX_EXT_buffer_age 1
+#define GLX_BACK_BUFFER_AGE_EXT 0x20F4
+#endif /* GLX_EXT_buffer_age */
+
We get glxext.h directly from Khronos, so it should not be modified...
Oh OK.
except to import new versions from upstream. It looks like the upstream
glxext.h has this, so the first patch in the series should be "glx:
Update glxext.h to revision 25407." And drop the change to glx.h.
Actually the version we ship seems to have it already. But probably worth
updating anyway.
#ifndef GLX_MESA_agp_offset
#define GLX_MESA_agp_offset 1
typedef unsigned int ( *PFNGLXGETAGPOFFSETMESAPROC) (const void *pointer);
diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
index 67fe9c1..007f449 100644
--- a/src/glx/dri2_glx.c
+++ b/src/glx/dri2_glx.c
@@ -1288,6 +1288,7 @@ dri2CreateScreen(int screen, struct glx_display *
priv)
psp->waitForSBC = NULL;
psp->setSwapInterval = NULL;
psp->getSwapInterval = NULL;
+ psp->queryBufferAge = NULL;
if (pdp->driMinor >= 2) {
psp->getDrawableMSC = dri2DrawableGetMSC;
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 70ec057..07120e1 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -1345,6 +1345,8 @@ dri3_swap_buffers(__GLXDRIdrawable *pdraw, int64_t
target_msc, int64_t divisor,
target_msc = priv->msc + priv->swap_interval * (priv->send_sbc
- priv->recv_sbc);
priv->buffers[buf_id]->busy = 1;
+ priv->buffers[buf_id]->last_swap = priv->swap_count;
+
xcb_present_pixmap(c,
priv->base.xDrawable,
priv->buffers[buf_id]->pixmap,
@@ -1379,11 +1381,23 @@ dri3_swap_buffers(__GLXDRIdrawable *pdraw,
int64_t target_msc, int64_t divisor,
xcb_flush(c);
if (priv->stamp)
++(*priv->stamp);
+
+ priv->swap_count++;
}
return ret;
}
+static int
+dri3_query_buffer_age(__GLXDRIdrawable *pdraw)
+{
+ struct dri3_drawable *priv = (struct dri3_drawable *) pdraw;
+ int buf_id = DRI3_BACK_ID(priv->cur_back);
Blank line here.
Also maybe use dri3_back_buffer instead?
const struct dri3_buffer *const back = dri3_back_buffer(priv);
if (back->last_swap != 0)
return 0;
else
return priv->swap_count - back->last_swap;
OK, you mean "== 0" right? Otherwise this does not make much sense ;)
...then check whether it's NULL. tsk tsk. :)
I think the declaration of pdraw (with the #ifdef stuff) should get
moved up to the previous else (just before calling _XRead). Then this
block could be 'if (pdraw != NULL) {" instead of just "{". Then you can
delete the other 'pdraw != NULL' checks (below). That refactor should
go in a separate patch.
I am not sure I understand this. The ifdefs will be needed anyway because
otherwise __GLXDRIdrawable is not defined. Or should I simply do something like:
#ifdef ...
__GLXDRIdrawable *pdraw = ...;
#else
void *pdraw = NULL;
#endif
...
if (pdraw != NULL)
?
+psc->driScreen->queryBufferAge != NULL) {
+
+*value = psc->driScreen->queryBufferAge (pdraw);
^
No space here.
OK.
+}
if (pdraw != NULL && !pdraw->textureTarget)
pdraw->textureTarget =
diff --git a/src/glx/glxclient.h b/src/glx/glxclient.h
index a7118af..9333bdf 100644
--- a/src/glx/glxclient.h
+++ b/src/glx/glxclient.h
@@ -125,6 +125,7 @@ struct __GLXDRIscreenRec {
int64_t *msc, int64_t *sbc);
int (*setSwapInterval)(__GLXDRIdrawable *pdraw, int interval);
int (*getSwapInterval)(__GLXDRIdrawable
[Mesa-dev] [Bug 75061] bug in clearing color buffer
https://bugs.freedesktop.org/show_bug.cgi?id=75061 --- Comment #6 from Maxim --- (In reply to comment #5) > Created attachment 94321 [details] [review] > Bail if rr->buf is NULL > > Does this patch help? > > (In reply to comment #3) > > valgrind + hellgrind > > Thanks, but the proper spelling is 'helgrind', so it was still using > memcheck as you can see. Just as a note for next time. SIGSEGV in evergreen_emit_vertex_buffers (evergreen_state.c:2479) -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 75061] bug in clearing color buffer
https://bugs.freedesktop.org/show_bug.cgi?id=75061 --- Comment #7 from Maxim --- Created attachment 94418 --> https://bugs.freedesktop.org/attachment.cgi?id=94418&action=edit gdb with patch -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 75061] bug in clearing color buffer
https://bugs.freedesktop.org/show_bug.cgi?id=75061 --- Comment #8 from Maxim --- Created attachment 94419 --> https://bugs.freedesktop.org/attachment.cgi?id=94419&action=edit valgrind only (with patch) -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 75061] bug in clearing color buffer
https://bugs.freedesktop.org/show_bug.cgi?id=75061 --- Comment #9 from Maxim --- Created attachment 94422 --> https://bugs.freedesktop.org/attachment.cgi?id=94422&action=edit valgrind + helgrind (with patch) -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 0/3] dri3: Add GLX_EXT_buffer_age support
Hi, OK here are updated patches based on the review comments. The first one simply updates the glxext.h header even though that turned out to not be required for this but it doesn't hurt doing it anyway. The second one refactors glx_pbuffer based on the review comments from Ian (assuming I got what he meant). Finally the third patch adds glx_ext_buffer_age support to dri3. Adel Gadllah (3): glx: Update glxext.h to revision 25407 glx_pbuffer: Refactor GetDrawableAttribute dri3: Add GLX_EXT_buffer_age support include/GL/glxext.h | 32 +--- src/glx/dri2_glx.c | 1 + src/glx/dri3_glx.c | 18 ++ src/glx/dri3_priv.h | 2 ++ src/glx/glx_pbuffer.c | 19 ++- src/glx/glxclient.h | 1 + src/glx/glxextensions.c | 1 + src/glx/glxextensions.h | 1 + 8 files changed, 67 insertions(+), 8 deletions(-) -- 1.8.5.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/3] dri3: Add GLX_EXT_buffer_age support
---
src/glx/dri2_glx.c | 1 +
src/glx/dri3_glx.c | 18 ++
src/glx/dri3_priv.h | 2 ++
src/glx/glx_pbuffer.c | 8
src/glx/glxclient.h | 1 +
src/glx/glxextensions.c | 1 +
src/glx/glxextensions.h | 1 +
7 files changed, 32 insertions(+)
diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
index 67fe9c1..146802a 100644
--- a/src/glx/dri2_glx.c
+++ b/src/glx/dri2_glx.c
@@ -1288,6 +1288,7 @@ dri2CreateScreen(int screen, struct glx_display * priv)
psp->waitForSBC = NULL;
psp->setSwapInterval = NULL;
psp->getSwapInterval = NULL;
+ psp->getBufferAge = NULL;
if (pdp->driMinor >= 2) {
psp->getDrawableMSC = dri2DrawableGetMSC;
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 70ec057..697d448 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -1345,6 +1345,7 @@ dri3_swap_buffers(__GLXDRIdrawable *pdraw, int64_t
target_msc, int64_t divisor,
target_msc = priv->msc + priv->swap_interval * (priv->send_sbc -
priv->recv_sbc);
priv->buffers[buf_id]->busy = 1;
+ priv->buffers[buf_id]->last_swap = priv->swap_count;
xcb_present_pixmap(c,
priv->base.xDrawable,
priv->buffers[buf_id]->pixmap,
@@ -1379,11 +1380,25 @@ dri3_swap_buffers(__GLXDRIdrawable *pdraw, int64_t
target_msc, int64_t divisor,
xcb_flush(c);
if (priv->stamp)
++(*priv->stamp);
+
+ priv->swap_count++;
}
return ret;
}
+static int
+dri3_get_buffer_age(__GLXDRIdrawable *pdraw)
+{
+ struct dri3_drawable *priv = (struct dri3_drawable *) pdraw;
+ const struct dri3_buffer *const back = dri3_back_buffer(priv);
+
+ if (back->last_swap != 0)
+ return priv->swap_count - back->last_swap;
+ else
+ return 0;
+}
+
/** dri3_open
*
* Wrapper around xcb_dri3_open
@@ -1742,6 +1757,9 @@ dri3_create_screen(int screen, struct glx_display * priv)
psp->copySubBuffer = dri3_copy_sub_buffer;
__glXEnableDirectExtension(&psc->base, "GLX_MESA_copy_sub_buffer");
+ psp->getBufferAge = dri3_get_buffer_age;
+ __glXEnableDirectExtension(&psc->base, "GLX_EXT_buffer_age");
+
free(driverName);
free(deviceName);
diff --git a/src/glx/dri3_priv.h b/src/glx/dri3_priv.h
index 1d124f8..d00440a 100644
--- a/src/glx/dri3_priv.h
+++ b/src/glx/dri3_priv.h
@@ -97,6 +97,7 @@ struct dri3_buffer {
uint32_t cpp;
uint32_t flags;
uint32_t width, height;
+ uint32_t last_swap;
enum dri3_buffer_typebuffer_type;
};
@@ -184,6 +185,7 @@ struct dri3_drawable {
struct dri3_buffer *buffers[DRI3_NUM_BUFFERS];
int cur_back;
int num_back;
+ uint32_t swap_count;
uint32_t *stamp;
diff --git a/src/glx/glx_pbuffer.c b/src/glx/glx_pbuffer.c
index 978730c..afb4206 100644
--- a/src/glx/glx_pbuffer.c
+++ b/src/glx/glx_pbuffer.c
@@ -373,6 +373,14 @@ GetDrawableAttribute(Display * dpy, GLXDrawable drawable,
if (!pdraw->textureFormat)
pdraw->textureFormat =
determineTextureFormat((const int *) data, num_attributes);
+
+if (attribute == GLX_BACK_BUFFER_AGE_EXT) {
+ struct glx_screen *psc = pdraw->psc;
+
+ if (psc->driScreen->getBufferAge != NULL)
+ *value = psc->driScreen->getBufferAge(pdraw);
+}
+
}
#endif
diff --git a/src/glx/glxclient.h b/src/glx/glxclient.h
index a7118af..74c19c4 100644
--- a/src/glx/glxclient.h
+++ b/src/glx/glxclient.h
@@ -125,6 +125,7 @@ struct __GLXDRIscreenRec {
int64_t *msc, int64_t *sbc);
int (*setSwapInterval)(__GLXDRIdrawable *pdraw, int interval);
int (*getSwapInterval)(__GLXDRIdrawable *pdraw);
+ int (*getBufferAge)(__GLXDRIdrawable *pdraw);
};
struct __GLXDRIdrawableRec
diff --git a/src/glx/glxextensions.c b/src/glx/glxextensions.c
index f186c13..ac1b4a7 100644
--- a/src/glx/glxextensions.c
+++ b/src/glx/glxextensions.c
@@ -103,6 +103,7 @@ static const struct extension_info known_glx_extensions[] =
{
{ GLX(SGIX_visual_select_group),VER(0,0), Y, Y, N, N },
{ GLX(EXT_texture_from_pixmap), VER(0,0), Y, N, N, N },
{ GLX(INTEL_swap_event),VER(0,0), Y, N, N, N },
+ { GLX(EXT_buffer_age), VER(0,0), Y, N, Y, Y },
{ NULL }
};
diff --git a/src/glx/glxextensions.h b/src/glx/glxextensions.h
index 8436a94..37e4ccc 100644
--- a/src/glx/glxextensions.h
+++ b/src/glx/glxextensions.h
@@ -66,6 +66,7 @@ enum
SGIX_visual_select_group_bit,
EXT_texture_from_pixmap_bit,
INTEL_swap_event_bit,
+ EXT_buffer_age_bit,
};
/* From the GLX perspective, the ARB and EXT extensions are identical. Use a
--
1.8.5.3
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[Mesa-dev] [PATCH 2/3] glx_pbuffer: Refactor GetDrawableAttribute
Move the pdraw != NULL check out so that they don't
have to be duplicated.
---
src/glx/glx_pbuffer.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/glx/glx_pbuffer.c b/src/glx/glx_pbuffer.c
index 411d6e5..978730c 100644
--- a/src/glx/glx_pbuffer.c
+++ b/src/glx/glx_pbuffer.c
@@ -350,6 +350,9 @@ GetDrawableAttribute(Display * dpy, GLXDrawable drawable,
_XEatData(dpy, length);
}
else {
+#if defined(GLX_DIRECT_RENDERING) && !defined(GLX_USE_APPLEGL)
+ __GLXDRIdrawable *pdraw = GetGLXDRIDrawable(dpy, drawable);
+#endif
_XRead(dpy, (char *) data, length * sizeof(CARD32));
/* Search the set of returned attributes for the attribute requested
by
@@ -363,13 +366,11 @@ GetDrawableAttribute(Display * dpy, GLXDrawable drawable,
}
#if defined(GLX_DIRECT_RENDERING) && !defined(GLX_USE_APPLEGL)
- {
-__GLXDRIdrawable *pdraw = GetGLXDRIDrawable(dpy, drawable);
-
-if (pdraw != NULL && !pdraw->textureTarget)
+ if (pdraw != NULL) {
+if (!pdraw->textureTarget)
pdraw->textureTarget =
determineTextureTarget((const int *) data, num_attributes);
-if (pdraw != NULL && !pdraw->textureFormat)
+if (!pdraw->textureFormat)
pdraw->textureFormat =
determineTextureFormat((const int *) data, num_attributes);
}
--
1.8.5.3
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[Mesa-dev] [PATCH 1/3] glx: Update glxext.h to revision 25407
---
include/GL/glxext.h | 32 +---
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/include/GL/glxext.h b/include/GL/glxext.h
index 8c642f3..826fda5 100644
--- a/include/GL/glxext.h
+++ b/include/GL/glxext.h
@@ -6,7 +6,7 @@ extern "C" {
#endif
/*
-** Copyright (c) 2013 The Khronos Group Inc.
+** Copyright (c) 2013-2014 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a
** copy of this software and/or associated documentation files (the
@@ -33,10 +33,10 @@ extern "C" {
** used to make the header, and the header can be found at
** http://www.opengl.org/registry/
**
-** Khronos $Revision: 24777 $ on $Date: 2014-01-14 14:02:32 -0800 (Tue, 14 Jan
2014) $
+** Khronos $Revision: 25407 $ on $Date: 2014-02-18 16:51:56 -0800 (Tue, 18 Feb
2014) $
*/
-#define GLX_GLXEXT_VERSION 20140114
+#define GLX_GLXEXT_VERSION 20140218
/* Generated C header for:
* API: glx
@@ -407,6 +407,32 @@ GLXPixmap glXCreateGLXPixmapMESA (Display *dpy,
XVisualInfo *visual, Pixmap pixm
#endif
#endif /* GLX_MESA_pixmap_colormap */
+#ifndef GLX_MESA_query_renderer
+#define GLX_MESA_query_renderer 1
+#define GLX_RENDERER_VENDOR_ID_MESA 0x8183
+#define GLX_RENDERER_DEVICE_ID_MESA 0x8184
+#define GLX_RENDERER_VERSION_MESA 0x8185
+#define GLX_RENDERER_ACCELERATED_MESA 0x8186
+#define GLX_RENDERER_VIDEO_MEMORY_MESA0x8187
+#define GLX_RENDERER_UNIFIED_MEMORY_ARCHITECTURE_MESA 0x8188
+#define GLX_RENDERER_PREFERRED_PROFILE_MESA 0x8189
+#define GLX_RENDERER_OPENGL_CORE_PROFILE_VERSION_MESA 0x818A
+#define GLX_RENDERER_OPENGL_COMPATIBILITY_PROFILE_VERSION_MESA 0x818B
+#define GLX_RENDERER_OPENGL_ES_PROFILE_VERSION_MESA 0x818C
+#define GLX_RENDERER_OPENGL_ES2_PROFILE_VERSION_MESA 0x818D
+#define GLX_RENDERER_ID_MESA 0x818E
+typedef Bool ( *PFNGLXQUERYCURRENTRENDERERINTEGERMESAPROC) (int attribute,
unsigned int *value);
+typedef const char *( *PFNGLXQUERYCURRENTRENDERERSTRINGMESAPROC) (int
attribute);
+typedef Bool ( *PFNGLXQUERYRENDERERINTEGERMESAPROC) (Display *dpy, int screen,
int renderer, int attribute, unsigned int *value);
+typedef const char *( *PFNGLXQUERYRENDERERSTRINGMESAPROC) (Display *dpy, int
screen, int renderer, int attribute);
+#ifdef GLX_GLXEXT_PROTOTYPES
+Bool glXQueryCurrentRendererIntegerMESA (int attribute, unsigned int *value);
+const char *glXQueryCurrentRendererStringMESA (int attribute);
+Bool glXQueryRendererIntegerMESA (Display *dpy, int screen, int renderer, int
attribute, unsigned int *value);
+const char *glXQueryRendererStringMESA (Display *dpy, int screen, int
renderer, int attribute);
+#endif
+#endif /* GLX_MESA_query_renderer */
+
#ifndef GLX_MESA_release_buffers
#define GLX_MESA_release_buffers 1
typedef Bool ( *PFNGLXRELEASEBUFFERSMESAPROC) (Display *dpy, GLXDrawable
drawable);
--
1.8.5.3
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Re: [Mesa-dev] [PATCH] st/omx/enc: add multi scaling buffers for performance improvement
Am 19.02.2014 18:17, schrieb Leo Liu:
From: Leo Liu
Signed-off-by: Leo Liu
Reviewed and pushed.
Thanks,
Christian.
---
src/gallium/state_trackers/omx/vid_enc.c | 38
src/gallium/state_trackers/omx/vid_enc.h | 7 --
2 files changed, 29 insertions(+), 16 deletions(-)
diff --git a/src/gallium/state_trackers/omx/vid_enc.c
b/src/gallium/state_trackers/omx/vid_enc.c
index 6e65274..3f1d01c 100644
--- a/src/gallium/state_trackers/omx/vid_enc.c
+++ b/src/gallium/state_trackers/omx/vid_enc.c
@@ -273,8 +273,9 @@ static OMX_ERRORTYPE vid_enc_Destructor(OMX_COMPONENTTYPE
*comp)
vl_compositor_cleanup_state(&priv->cstate);
vl_compositor_cleanup(&priv->compositor);
- if (priv->scale_buffer)
- priv->scale_buffer->destroy(priv->scale_buffer);
+ for (i = 0; i < OMX_VID_ENC_NUM_SCALING_BUFFERS; ++i)
+ if (priv->scale_buffer[i])
+ priv->scale_buffer[i]->destroy(priv->scale_buffer[i]);
if (priv->s_pipe)
priv->s_pipe->destroy(priv->s_pipe);
@@ -447,7 +448,8 @@ static OMX_ERRORTYPE vid_enc_SetConfig(OMX_HANDLETYPE
handle, OMX_INDEXTYPE idx,
OMX_COMPONENTTYPE *comp = handle;
vid_enc_PrivateType *priv = comp->pComponentPrivate;
OMX_ERRORTYPE r;
-
+ int i;
+
if (!config)
return OMX_ErrorBadParameter;
@@ -473,9 +475,11 @@ static OMX_ERRORTYPE vid_enc_SetConfig(OMX_HANDLETYPE handle, OMX_INDEXTYPE idx,
if (scale->xWidth < 176 || scale->xHeight < 144)
return OMX_ErrorBadParameter;
- if (priv->scale_buffer) {
- priv->scale_buffer->destroy(priv->scale_buffer);
- priv->scale_buffer = NULL;
+ for (i = 0; i < OMX_VID_ENC_NUM_SCALING_BUFFERS; ++i) {
+ if (priv->scale_buffer[i]) {
+priv->scale_buffer[i]->destroy(priv->scale_buffer[i]);
+priv->scale_buffer[i] = NULL;
+ }
}
priv->scale = *scale;
@@ -487,9 +491,11 @@ static OMX_ERRORTYPE vid_enc_SetConfig(OMX_HANDLETYPE
handle, OMX_INDEXTYPE idx,
templat.width = priv->scale.xWidth;
templat.height = priv->scale.xHeight;
templat.interlaced = false;
- priv->scale_buffer = priv->s_pipe->create_video_buffer(priv->s_pipe,
&templat);
- if (!priv->scale_buffer)
-return OMX_ErrorInsufficientResources;
+ for (i = 0; i < OMX_VID_ENC_NUM_SCALING_BUFFERS; ++i) {
+priv->scale_buffer[i] =
priv->s_pipe->create_video_buffer(priv->s_pipe, &templat);
+if (!priv->scale_buffer[i])
+ return OMX_ErrorInsufficientResources;
+ }
}
break;
@@ -545,8 +551,10 @@ static OMX_ERRORTYPE
vid_enc_MessageHandler(OMX_COMPONENTTYPE* comp, internalReq
templat.profile = PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE;
templat.entrypoint = PIPE_VIDEO_ENTRYPOINT_ENCODE;
templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
- templat.width = priv->scale_buffer ? priv->scale.xWidth :
port->sPortParam.format.video.nFrameWidth;
- templat.height = priv->scale_buffer ? priv->scale.xHeight :
port->sPortParam.format.video.nFrameHeight;
+ templat.width = priv->scale_buffer[priv->current_scale_buffer] ?
+priv->scale.xWidth :
port->sPortParam.format.video.nFrameWidth;
+ templat.height = priv->scale_buffer[priv->current_scale_buffer] ?
+priv->scale.xHeight :
port->sPortParam.format.video.nFrameHeight;
templat.max_references = 1;
priv->codec = priv->s_pipe->create_video_codec(priv->s_pipe, &templat);
@@ -736,7 +744,7 @@ static OMX_ERRORTYPE vid_enc_EncodeFrame(omx_base_PortType
*port, OMX_BUFFERHEAD
/* -- scale input image - */
- if (priv->scale_buffer) {
+ if (priv->scale_buffer[priv->current_scale_buffer]) {
struct vl_compositor *compositor = &priv->compositor;
struct vl_compositor_state *s = &priv->cstate;
struct pipe_sampler_view **views;
@@ -744,7 +752,8 @@ static OMX_ERRORTYPE vid_enc_EncodeFrame(omx_base_PortType
*port, OMX_BUFFERHEAD
unsigned i;
views = vbuf->get_sampler_view_planes(vbuf);
- dst_surface = priv->scale_buffer->get_surfaces(priv->scale_buffer);
+ dst_surface =
priv->scale_buffer[priv->current_scale_buffer]->get_surfaces
+ (priv->scale_buffer[priv->current_scale_buffer]);
vl_compositor_clear_layers(s);
for (i = 0; i < VL_MAX_SURFACES; ++i) {
@@ -768,7 +777,8 @@ static OMX_ERRORTYPE vid_enc_EncodeFrame(omx_base_PortType
*port, OMX_BUFFERHEAD
}
size = priv->scale.xWidth * priv->scale.xHeight * 2;
- vbuf = priv->scale_buffer;
+ vbuf = priv->scale_buffer[priv->current_scale_buffer++];
+ priv->current_scale_buffer %= OMX_VID_ENC_NUM_SCALING_BUFFERS;
}
priv->s_pipe->flush(priv->s_pipe, NULL, 0);
diff
Re: [Mesa-dev] [PATCH 5/9] glsl: Fix memcpy size in ir_constant
On Wed, Feb 19, 2014 at 4:35 AM, Ian Romanick wrote:
> On 02/09/2014 01:50 AM, Juha-Pekka Heikkilä wrote:
>> The place which cause Klocwork to highlight this is at
>> src/mesa/main/ff_fragment_shader.cpp around line 897 where it says:
>>
>> ...
>> float const_data[4] = {
>> float(1 << rgb_shift),
>> float(1 << rgb_shift),
>> float(1 << rgb_shift),
>> float(1 << alpha_shift)
>> };
>> shift = new(p->mem_ctx) ir_constant(glsl_type::vec4_type,
>> (ir_constant_data *)const_data);
>> ...
>>
>> I don't know if this is the only place for such usage but it looks
>> reasonable to me.
>>
>> If I fix this place instead of what my patch does Klocwork would tell
>> where is next similar usage for this ir_constant constructor, that is
>> if such exist.
>
> The ir_constant constructors are used in a lot of places. I'd rather
> not take the extra overhead to work around callers lying about the
> parameter type. If we have to keep fixing these one at a time, I'm okay
> with that. The error case is (most likely) that we read some garbage
> data from the stack. We should fix those, but it's not a cataclysmic
> error.
>
> Doing a quick check...
>
> egrep -r 'new[^ ]* ir_constant[(][^,)]*,[^)]*[)]' src/
>
> shows
>
> src/mesa/drivers/dri/i965/brw_fs_fp.cpp: ir->coordinate =
> new(mem_ctx) ir_constant(coordinate_type, &junk_data);
> src/glsl/builtin_functions.cpp: return new(mem_ctx) ir_constant(f,
> vector_elements);
> src/glsl/builtin_functions.cpp: return new(mem_ctx) ir_constant(i,
> vector_elements);
> src/glsl/builtin_functions.cpp: return new(mem_ctx) ir_constant(u,
> vector_elements);
> src/glsl/builtin_functions.cpp: return new(mem_ctx) ir_constant(type,
> &data);
> src/glsl/ir_clone.cpp: return new(mem_ctx) ir_constant(this->type,
> &this->value);
> src/glsl/opt_constant_propagation.cpp: *rvalue = new(ralloc_parent(deref))
> ir_constant(type, &data);
> src/glsl/ir_constant_expression.cpp: return new(ctx)
> ir_constant(this->type, &data);
> src/glsl/ir_constant_expression.cpp: return new(ctx)
> ir_constant(this->type, &data);
> src/glsl/ir_constant_expression.cpp: return new(ctx)
> ir_constant(column_type, &data);
> src/glsl/ir_constant_expression.cpp: return new(ctx) ir_constant(array,
> component);
> src/glsl/opt_algebraic.cpp: return new(mem_ctx) ir_constant(ir->type,
> &data);
> src/glsl/ast_to_hir.cpp: var->constant_value = new(var)
> ir_constant(glsl_type::ivec3_type, &data);
> src/glsl/ast_to_hir.cpp: new(var) ir_constant(glsl_type::ivec3_type,
> &data);
> src/glsl/lower_instructions.cpp: ir_constant *sign_mask = new(ir)
> ir_constant(0x8000u, vec_elem);
> src/glsl/lower_instructions.cpp: ir_constant *exp_shift = new(ir)
> ir_constant(23u, vec_elem);
> src/glsl/lower_instructions.cpp: ir_constant *exp_width = new(ir)
> ir_constant(8u, vec_elem);
> src/glsl/lower_instructions.cpp: new(ir)
> ir_constant(0x1, vec_elem;
> src/glsl/tests/uniform_initializer_utils.cpp: val = new(mem_ctx)
> ir_constant(type, &data);
> src/glsl/tests/uniform_initializer_utils.cpp: val = new(mem_ctx)
> ir_constant(array_type, &values_for_array);
> src/glsl/ast_function.cpp: return new(ctx) ir_constant(constant,
> component);
> src/glsl/ast_function.cpp: return new(ctx) ir_constant(constructor_type,
> &actual_parameters);
> src/glsl/ast_function.cpp: return new(ctx) ir_constant(constructor_type,
> &actual_parameters);
> src/glsl/ast_function.cpp: return new(mem_ctx)
> ir_constant(constructor_type, parameters);
> src/glsl/ast_function.cpp: ir_rvalue *rhs = new(ctx)
> ir_constant(rhs_type, &data);
> src/glsl/ast_function.cpp: new(ctx)
> ir_constant(rhs_var->type, &zero),
> src/glsl/ast_function.cpp: ir_rvalue *const rhs = new(ctx)
> ir_constant(col_type, &ident);
> src/glsl/ast_function.cpp: return new(ctx)
> ir_constant(constructor_type, &actual_parameters);
> src/glsl/ir_reader.cpp: return new(mem_ctx) ir_constant(type, &elements);
> src/glsl/ir_reader.cpp: return new(mem_ctx) ir_constant(type, &data);
> src/glsl/builtin_variables.cpp: var->constant_value = new(var)
> ir_constant(glsl_type::ivec3_type, &data);
> src/glsl/builtin_variables.cpp: new(var)
> ir_constant(glsl_type::ivec3_type, &data);
>
> Of those, I think we only need to audit:
>
> src/mesa/drivers/dri/i965/brw_fs_fp.cpp: ir->coordinate =
> new(mem_ctx) ir_constant(coordinate_type, &junk_data);
> src/glsl/builtin_functions.cpp: return new(mem_ctx) ir_constant(type,
> &data);
> src/glsl/opt_constant_propagation.cpp: *rvalue = new(ralloc_parent(deref))
> ir_constant(type, &data);
> src/glsl/ir_constant_expression.cpp: return new(ctx)
> ir_constant(this->type, &data);
> src/glsl/ir_constant_expression.cpp: return new(ctx)
> ir_constant(this->type, &data);
> src/glsl/ir_con
[Mesa-dev] classic dri driver cleanup broke --disable-dri
Hi Folks, Since commit ee55500c (configure: cleanup classic dri drivers handling, 2014-02-04) when I build from source using $ ./autogen.sh --disable-dri it fails with this error message: configure: error: classic DRI driver 'yes' does not exist I'm not sure whether it is related but I also get a lot of warnings from automake of the form: .../Makefile.am:#: warning: source file '...' is in a subdirectory, .../Makefile.am:#: but option 'subdir-objects' is disabled I'm using autoconf 2.69 and automake 1.14.1. Thanks, -Brad ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] classic dri driver cleanup broke --disable-dri
On 02/20/2014 05:38 PM, Brad King wrote: > Hi Folks, > > Since commit ee55500c (configure: cleanup classic dri drivers handling, > 2014-02-04) when I build from source using > > $ ./autogen.sh --disable-dri > > it fails with this error message: > > configure: error: classic DRI driver 'yes' does not exist > https://bugs.freedesktop.org/show_bug.cgi?id=75126 > I'm not sure whether it is related but I also get a lot of warnings > from automake of the form: > > .../Makefile.am:#: warning: source file '...' is in a subdirectory, > .../Makefile.am:#: but option 'subdir-objects' is disabled > > I'm using autoconf 2.69 and automake 1.14.1. > > Thanks, > -Brad > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev > -- Note: My last name is not Krejzi. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 75126] configure: error: classic DRI driver 'yes' does not exist
https://bugs.freedesktop.org/show_bug.cgi?id=75126 --- Comment #2 from Brad King --- I encountered the same issue and can confirm that 0001-configure-use-default-dri-drivers-whenever-opengl-an.patch fixes it for me. Thanks! -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] configure: use shared-glapi when more than one gl* API is used
Emil Velikov writes: > Current behaviour states that shared-glapi is usefull when building > with dri, which is not the case. Shared-glapi is used to dispatch > the gl* functions across the one or more gl api's which can be dri > based but do not need to be. > > Fixed the following build > > ./configure --enable-gles2 --disable-dri --enable-gallium-egl \ > --with-egl-platforms=fbdev --with-gallium-drivers=swrast > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75098 > Signed-off-by: Emil Velikov Reviewed-by: Eric Anholt pgpdgIPpzI17y.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/8] r600g: Use util_cpu_to_le32() instead of bswap32() on big-endian systems
---
src/gallium/drivers/r600/r600_asm.c | 2 +-
src/gallium/drivers/r600/r600_shader.c | 2 +-
src/gallium/drivers/r600/r600_state_common.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 3afe7b2..67df2f2 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2431,7 +2431,7 @@ void *r600_create_vertex_fetch_shader(struct pipe_context
*ctx,
if (R600_BIG_ENDIAN) {
for (i = 0; i < fs_size / 4; ++i) {
- bytecode[i] = util_bswap32(bc.bytecode[i]);
+ bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
}
} else {
memcpy(bytecode, bc.bytecode, fs_size);
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index baeef57..38c68e4 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -119,7 +119,7 @@ static int store_shader(struct pipe_context *ctx,
ptr = r600_buffer_map_sync_with_rings(&rctx->b, shader->bo,
PIPE_TRANSFER_WRITE);
if (R600_BIG_ENDIAN) {
for (i = 0; i < shader->shader.bc.ndw; ++i) {
- ptr[i] =
util_bswap32(shader->shader.bc.bytecode[i]);
+ ptr[i] =
util_cpu_to_le32(shader->shader.bc.bytecode[i]);
}
} else {
memcpy(ptr, shader->shader.bc.bytecode,
shader->shader.bc.ndw * sizeof(*ptr));
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index da4578a..5f9e8b7 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -936,7 +936,7 @@ static void r600_set_constant_buffer(struct pipe_context
*ctx, uint shader, uint
}
for (i = 0; i < size / 4; ++i) {
- tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
+ tmpPtr[i] = util_cpu_to_le32(((uint32_t
*)ptr)[i]);
}
u_upload_data(rctx->b.uploader, 0, size, tmpPtr,
&cb->buffer_offset, &cb->buffer);
--
1.8.1.4
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[Mesa-dev] [PATCH 4/8] radeonsi: Use util_cpu_to_le32() instead of bswap32() on big-endian systems
---
src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
src/gallium/drivers/radeonsi/si_shader.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index d45bc80..9b10d01 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -432,7 +432,7 @@ void si_upload_const_buffer(struct si_context *sctx, struct
r600_resource **rbuf
}
for (i = 0; i < size / 4; ++i) {
- tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
+ tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
}
u_upload_data(sctx->b.uploader, 0, size, tmpPtr, const_offset,
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 54270cd..9b04e6b 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2335,7 +2335,7 @@ int si_compile_llvm(struct si_context *sctx, struct
si_pipe_shader *shader,
ptr = (uint32_t*)sctx->b.ws->buffer_map(shader->bo->cs_buf,
sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
if (0 /*SI_BIG_ENDIAN*/) {
for (i = 0; i < binary.code_size / 4; ++i) {
- ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
+ ptr[i] = util_cpu_to_le32((*(uint32_t*)(binary.code +
i*4)));
}
} else {
memcpy(ptr, binary.code, binary.code_size);
--
1.8.1.4
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[Mesa-dev] [PATCH 8/8] clover: Pass buffer offsets to the driver in set_global_binding() v3
The offsets will be stored in the handles parameter. This makes
it possible to use sub-buffers.
v2:
- Style fixes
- Add support for constant sub-buffers
- Store handles in device byte order
v3:
- Use endian helpers
---
src/gallium/drivers/r600/evergreen_compute.c | 7 ++-
src/gallium/drivers/radeonsi/si_compute.c | 4
src/gallium/include/pipe/p_context.h | 13 -
src/gallium/state_trackers/clover/core/kernel.cpp | 18 ++
4 files changed, 32 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 70efe5c..5d090ad 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -662,10 +662,15 @@ static void evergreen_set_global_binding(
for (int i = 0; i < n; i++)
{
+ uint32_t buffer_offset;
+ uint32_t handle;
assert(resources[i]->target == PIPE_BUFFER);
assert(resources[i]->bind & PIPE_BIND_GLOBAL);
- *(handles[i]) = buffers[i]->chunk->start_in_dw * 4;
+ buffer_offset = util_le32_to_cpu(*(handles[i]));
+ handle = buffer_offset + buffers[i]->chunk->start_in_dw * 4;
+
+ *(handles[i]) = util_cpu_to_le32(handle);
}
evergreen_set_rat(ctx->cs_shader_state.shader, 0, pool->bo, 0,
pool->size_in_dw * 4);
diff --git a/src/gallium/drivers/radeonsi/si_compute.c
b/src/gallium/drivers/radeonsi/si_compute.c
index a7f49e7..ead5862 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -107,8 +107,12 @@ static void si_set_global_binding(
for (i = first; i < first + n; i++) {
uint64_t va;
+ uint32_t offset;
program->global_buffers[i] = resources[i];
va = r600_resource_va(ctx->screen, resources[i]);
+ offset = util_le32_to_cpu(*handles[i]);
+ va += offset;
+ va = util_cpu_to_le64(va);
memcpy(handles[i], &va, sizeof(va));
}
}
diff --git a/src/gallium/include/pipe/p_context.h
b/src/gallium/include/pipe/p_context.h
index 8ef6e27..209ec9e 100644
--- a/src/gallium/include/pipe/p_context.h
+++ b/src/gallium/include/pipe/p_context.h
@@ -460,11 +460,14 @@ struct pipe_context {
* unless it's NULL, in which case no new
* resources will be bound.
* \param handlesarray of pointers to the memory locations that
-* will be filled with the respective base
-* addresses each buffer will be mapped to. It
-* should contain at least \a count elements,
-* unless \a resources is NULL in which case \a
-* handles should be NULL as well.
+* will be updated with the address each buffer
+* will be mapped to. The base memory address of
+* each of the buffers will be added to the value
+* pointed to by its corresponding handle to form
+* the final address argument. It should contain
+* at least \a count elements, unless \a
+* resources is NULL in which case \a handles
+* should be NULL as well.
*
* Note that the driver isn't required to make any guarantees about
* the contents of the \a handles array being valid anytime except
diff --git a/src/gallium/state_trackers/clover/core/kernel.cpp
b/src/gallium/state_trackers/clover/core/kernel.cpp
index 6d894cd..3626a34 100644
--- a/src/gallium/state_trackers/clover/core/kernel.cpp
+++ b/src/gallium/state_trackers/clover/core/kernel.cpp
@@ -337,8 +337,17 @@ kernel::global_argument::bind(exec_context &ctx,
align(ctx.input, marg.target_align);
if (buf) {
- ctx.g_handles.push_back(allocate(ctx.input, marg.target_size));
- ctx.g_buffers.push_back(buf->resource(*ctx.q).pipe);
+ const resource &r = buf->resource(*ctx.q);
+ ctx.g_handles.push_back(ctx.input.size());
+ ctx.g_buffers.push_back(r.pipe);
+
+ // How to handle multi-demensional offsets?
+ // We don't need to. Buffer offsets are always
+ // one-dimensional.
+ auto v = bytes(r.offset[0]);
+ extend(v, marg.ext_type, marg.target_size);
+ byteswap(v, ctx.q->dev.endianness());
+ insert(ctx.input, v);
} else {
// Null pointer.
allocate(ctx.input, marg.target_size);
@@ -395,13 +404,14 @@ kernel::constant_argument::bind(exec_context &ctx,
align(ctx.input, marg.target_align);
if (buf) {
- auto v = bytes(ctx.resources.size() << 24);
+ const resource &r = buf->resource(*ctx.q);
+ auto v = bytes(ctx.resources.size() << 24 | r.offset[0]);
extend(v, mo
[Mesa-dev] [PATCH 3/8] util: Add util_cpu_to_le* helpers
--- src/gallium/auxiliary/util/u_math.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/auxiliary/util/u_math.h b/src/gallium/auxiliary/util/u_math.h index 0f498bc..ffbcc4c 100644 --- a/src/gallium/auxiliary/util/u_math.h +++ b/src/gallium/auxiliary/util/u_math.h @@ -726,6 +726,9 @@ util_bitcount(unsigned n) #define util_le16_to_cpu(x) (x) #endif +#define util_cpu_to_le64(x) util_le64_to_cpu(x) +#define util_cpu_to_le32(x) util_le32_to_cpu(x) +#define util_cpu_to_le16(x) util_le16_to_cpu(x) /** * Reverse byte order of a 32 bit word. -- 1.8.1.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/8] configure.ac: Use AX_GCC_BUILTIN to check availability of __builtin_bswap32
---
configure.ac| 6 ++
m4/ax_gcc_builtin.m4| 168
src/gallium/auxiliary/util/u_math.h | 3 +-
3 files changed, 176 insertions(+), 1 deletion(-)
create mode 100644 m4/ax_gcc_builtin.m4
diff --git a/configure.ac b/configure.ac
index 8390d27..75d345a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -119,6 +119,12 @@ if test "x$GCC" = xyes -a "x$acv_mesa_CLANG" = xno; then
GEN_ASM_OFFSETS=yes
fi
fi
+
+dnl Check for compiler builtins
+AX_GCC_BUILTIN([__builtin_bswap32])
+
+AC_SUBST(HAVE___BUILTIN_BSWAP32)
+
AM_CONDITIONAL([GEN_ASM_OFFSETS], test "x$GEN_ASM_OFFSETS" = xyes)
dnl Make sure the pkg-config macros are defined
diff --git a/m4/ax_gcc_builtin.m4 b/m4/ax_gcc_builtin.m4
new file mode 100644
index 000..b28a91b
--- /dev/null
+++ b/m4/ax_gcc_builtin.m4
@@ -0,0 +1,168 @@
+# ===
+# http://www.gnu.org/software/autoconf-archive/ax_gcc_builtin.html
+# ===
+#
+# SYNOPSIS
+#
+# AX_GCC_BUILTIN(BUILTIN)
+#
+# DESCRIPTION
+#
+# This macro checks if the compiler supports one of GCC's built-in
+# functions; many other compilers also provide those same built-ins.
+#
+# The BUILTIN parameter is the name of the built-in function.
+#
+# If BUILTIN is supported define HAVE_. Keep in mind that since
+# builtins usually start with two underscores they will be copied over
+# into the HAVE_ definition (e.g. HAVE___BUILTIN_EXPECT for
+# __builtin_expect()).
+#
+# The macro caches its result in the ax_cv_have_ variable (e.g.
+# ax_cv_have___builtin_expect).
+#
+# The macro currently supports the following built-in functions:
+#
+#__builtin_assume_aligned
+#__builtin_bswap32
+#__builtin_bswap64
+#__builtin_choose_expr
+#__builtin___clear_cache
+#__builtin_clrsb
+#__builtin_clrsbl
+#__builtin_clrsbll
+#__builtin_clz
+#__builtin_clzl
+#__builtin_clzll
+#__builtin_complex
+#__builtin_constant_p
+#__builtin_ctz
+#__builtin_ctzl
+#__builtin_ctzll
+#__builtin_expect
+#__builtin_ffs
+#__builtin_ffsl
+#__builtin_ffsll
+#__builtin_fpclassify
+#__builtin_huge_val
+#__builtin_huge_valf
+#__builtin_huge_vall
+#__builtin_inf
+#__builtin_infd128
+#__builtin_infd32
+#__builtin_infd64
+#__builtin_inff
+#__builtin_infl
+#__builtin_isinf_sign
+#__builtin_nan
+#__builtin_nand128
+#__builtin_nand32
+#__builtin_nand64
+#__builtin_nanf
+#__builtin_nanl
+#__builtin_nans
+#__builtin_nansf
+#__builtin_nansl
+#__builtin_object_size
+#__builtin_parity
+#__builtin_parityl
+#__builtin_parityll
+#__builtin_popcount
+#__builtin_popcountl
+#__builtin_popcountll
+#__builtin_powi
+#__builtin_powif
+#__builtin_powil
+#__builtin_prefetch
+#__builtin_trap
+#__builtin_types_compatible_p
+#__builtin_unreachable
+#
+# Unsuppored built-ins will be tested with an empty parameter set and the
+# result of the check might be wrong or meaningless so use with care.
+#
+# LICENSE
+#
+# Copyright (c) 2013 Gabriele Svelto
+#
+# Copying and distribution of this file, with or without modification, are
+# permitted in any medium without royalty provided the copyright notice
+# and this notice are preserved. This file is offered as-is, without any
+# warranty.
+
+#serial 2
+
+AC_DEFUN([AX_GCC_BUILTIN], [
+AS_VAR_PUSHDEF([ac_var], [ax_cv_have_$1])
+
+AC_CACHE_CHECK([for $1], [ac_var], [
+AC_LINK_IFELSE([AC_LANG_PROGRAM([], [
+m4_case([$1],
+[__builtin_assume_aligned], [$1("", 0)],
+[__builtin_bswap32], [$1(0)],
+[__builtin_bswap64], [$1(0)],
+[__builtin_choose_expr], [$1(0, 0, 0)],
+[__builtin___clear_cache], [$1("", "")],
+[__builtin_clrsb], [$1(0)],
+[__builtin_clrsbl], [$1(0)],
+[__builtin_clrsbll], [$1(0)],
+[__builtin_clz], [$1(0)],
+[__builtin_clzl], [$1(0)],
+[__builtin_clzll], [$1(0)],
+[__builtin_complex], [$1(0.0, 0.0)],
+[__builtin_constant_p], [$1(0)],
+[__builtin_ctz], [$1(0)],
+[__builtin_ctzl], [$1(0)],
+[__builtin_ctzll], [$1(0)],
+[__builtin_expect], [$1(0, 0)],
+[__builtin_ffs], [$1(0)],
+[__builtin_ffsl], [$1(0)],
+[__builtin_ffsll], [$1(0)],
+[__builtin_fpclassify], [$1(0, 1, 2, 3, 4, 0.0)],
+[__builtin_huge_val], [$1()],
+[__builtin_huge_valf], [$1()],
+[__builtin_huge_vall], [$1()],
+[__builtin_inf], [$1()],
+[__builtin_infd128]
[Mesa-dev] [PATCH 7/8] clover: Make resource::bind_surface() const
---
src/gallium/state_trackers/clover/core/resource.cpp | 2 +-
src/gallium/state_trackers/clover/core/resource.hpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/state_trackers/clover/core/resource.cpp
b/src/gallium/state_trackers/clover/core/resource.cpp
index 7e6b51f..f38573d 100644
--- a/src/gallium/state_trackers/clover/core/resource.cpp
+++ b/src/gallium/state_trackers/clover/core/resource.cpp
@@ -96,7 +96,7 @@ resource::unbind_sampler_view(command_queue &q,
}
pipe_surface *
-resource::bind_surface(command_queue &q, bool rw) {
+resource::bind_surface(command_queue &q, bool rw) const {
pipe_surface info {};
info.format = pipe->format;
diff --git a/src/gallium/state_trackers/clover/core/resource.hpp
b/src/gallium/state_trackers/clover/core/resource.hpp
index 7a6a3f1..b36fe36 100644
--- a/src/gallium/state_trackers/clover/core/resource.hpp
+++ b/src/gallium/state_trackers/clover/core/resource.hpp
@@ -68,7 +68,7 @@ namespace clover {
void unbind_sampler_view(command_queue &q,
pipe_sampler_view *st);
- pipe_surface *bind_surface(command_queue &q, bool rw);
+ pipe_surface *bind_surface(command_queue &q, bool rw) const;
void unbind_surface(command_queue &q, pipe_surface *st);
pipe_resource *pipe;
--
1.8.1.4
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[Mesa-dev] [PATCH 6/8] radeonsi: Use SI_BIG_ENDIAN now that it exists
---
src/gallium/drivers/radeonsi/si_shader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 9b04e6b..7776821 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2333,7 +2333,7 @@ int si_compile_llvm(struct si_context *sctx, struct
si_pipe_shader *shader,
}
ptr = (uint32_t*)sctx->b.ws->buffer_map(shader->bo->cs_buf,
sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
- if (0 /*SI_BIG_ENDIAN*/) {
+ if (SI_BIG_ENDIAN) {
for (i = 0; i < binary.code_size / 4; ++i) {
ptr[i] = util_cpu_to_le32((*(uint32_t*)(binary.code +
i*4)));
}
--
1.8.1.4
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[Mesa-dev] [PATCH 2/8] util: Add util_bswap64() v2
v2:
- Use __builtin_bswap64()
- Remove unnecessary mask
- Add util_le64_to_cpu() helper
---
configure.ac| 2 ++
src/gallium/auxiliary/util/u_math.h | 16
2 files changed, 18 insertions(+)
diff --git a/configure.ac b/configure.ac
index 75d345a..629f525 100644
--- a/configure.ac
+++ b/configure.ac
@@ -122,8 +122,10 @@ fi
dnl Check for compiler builtins
AX_GCC_BUILTIN([__builtin_bswap32])
+AX_GCC_BUILTIN([__builtin_bswap64])
AC_SUBST(HAVE___BUILTIN_BSWAP32)
+AC_SUBST(HAVE___BUILTIN_BSWAP64)
AM_CONDITIONAL([GEN_ASM_OFFSETS], test "x$GEN_ASM_OFFSETS" = xyes)
diff --git a/src/gallium/auxiliary/util/u_math.h
b/src/gallium/auxiliary/util/u_math.h
index b0f0e3d..0f498bc 100644
--- a/src/gallium/auxiliary/util/u_math.h
+++ b/src/gallium/auxiliary/util/u_math.h
@@ -717,9 +717,11 @@ util_bitcount(unsigned n)
*/
#ifdef PIPE_ARCH_BIG_ENDIAN
+#define util_le64_to_cpu(x) util_bswap64(x)
#define util_le32_to_cpu(x) util_bswap32(x)
#define util_le16_to_cpu(x) util_bswap16(x)
#else
+#define util_le64_to_cpu(x) (x)
#define util_le32_to_cpu(x) (x)
#define util_le16_to_cpu(x) (x)
#endif
@@ -742,6 +744,20 @@ util_bswap32(uint32_t n)
#endif
}
+/**
+ * Reverse byte order of a 64bit word.
+ */
+static INLINE uint64_t
+util_bswap64(uint64_t n)
+{
+#if defined(HAVE___BUILTIN_BSWAP64)
+ return __builtin_bswap64(n);
+#else
+ return ((uint64_t)util_bswap32(n) << 32) |
+ util_bswap32((n >> 32));
+#endif
+}
+
/**
* Reverse byte order of a 16 bit word.
--
1.8.1.4
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[Mesa-dev] [Bug 75278] New: st_program.c:1099: undefined reference to `ureg_property_gs_invocations'
https://bugs.freedesktop.org/show_bug.cgi?id=75278 Priority: medium Bug ID: 75278 Keywords: regression CC: anuj.pho...@gmail.com, jljus...@gmail.com, stereotype...@gmail.com Assignee: mesa-dev@lists.freedesktop.org Summary: st_program.c:1099: undefined reference to `ureg_property_gs_invocations' Severity: blocker Classification: Unclassified OS: All Reporter: v...@freedesktop.org Hardware: x86-64 (AMD64) Status: NEW Version: git Component: Mesa core Product: Mesa mesa: 741782b5948bb3d01d699f062a37513c2e73b076 (master) $ scons [...] build/linux-x86_64-debug/mesa/libmesa.a(st_program.os): In function `st_translate_geometry_program': src/mesa/state_tracker/st_program.c:1099: undefined reference to `ureg_property_gs_invocations' 86d6b5546b75ac7d5eedc26c14f579a4bfb40406 is the first bad commit commit 86d6b5546b75ac7d5eedc26c14f579a4bfb40406 Author: Jordan Justen Date: Sat Jan 25 12:34:24 2014 -0800 mesa: initialize gl_geometry_program Invocations field Signed-off-by: Jordan Justen Reviewed-by: Paul Berry Reviewed-by: Anuj Phogat :04 04 3b7acfca89e0b7e9f0d16ff43f04a2186504deaf da18d5749d12e284ee0ebf13908f719cb6657df4 Msrc bisect run success -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] dri3: Enable GLX_MESA_query_renderer on DRI3 too
From: Ian Romanick
This should have happend around the time of commit 4680d23, but Keith's
DRI3 patches and my GLX_MESA_query_renderer patches crossed in the mail.
I don't have a working DRI3 setup, so I haven't been able to actually
verify this. I'm hoping that someone can piglit this for me on DRI3...
It's also unfortunate the DRI2 and DRI3 can't share more code.
Signed-off-by: Ian Romanick
Cc: Keith Packard
Cc: "10.1"
---
src/glx/dri2.h| 8
src/glx/dri2_query_renderer.c | 39 +++
src/glx/dri3_glx.c| 10 +-
src/glx/dri3_priv.h | 1 +
4 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/src/glx/dri2.h b/src/glx/dri2.h
index 90efde8..7977d83 100644
--- a/src/glx/dri2.h
+++ b/src/glx/dri2.h
@@ -95,4 +95,12 @@ _X_HIDDEN int
dri2_query_renderer_string(struct glx_screen *base, int attribute,
const char **value);
+_X_HIDDEN int
+dri3_query_renderer_integer(struct glx_screen *base, int attribute,
+unsigned int *value);
+
+_X_HIDDEN int
+dri3_query_renderer_string(struct glx_screen *base, int attribute,
+ const char **value);
+
#endif
diff --git a/src/glx/dri2_query_renderer.c b/src/glx/dri2_query_renderer.c
index b50a202..e13024c 100644
--- a/src/glx/dri2_query_renderer.c
+++ b/src/glx/dri2_query_renderer.c
@@ -26,6 +26,7 @@
#include "dri2.h"
#include "dri_interface.h"
#include "dri2_priv.h"
+#include "dri3_priv.h"
static int
dri2_convert_glx_query_renderer_attribs(int attribute)
@@ -95,3 +96,41 @@ dri2_query_renderer_string(struct glx_screen *base, int
attribute,
return psc->rendererQuery->queryString(psc->driScreen, dri_attribute,
value);
}
+
+_X_HIDDEN int
+dri3_query_renderer_integer(struct glx_screen *base, int attribute,
+unsigned int *value)
+{
+ struct dri3_screen *const psc = (struct dri3_screen *) base;
+
+ /* Even though there are invalid values (and
+* dri2_convert_glx_query_renderer_attribs may return -1), the higher level
+* GLX code is required to perform the filtering. Assume that we got a
+* good value.
+*/
+ const int dri_attribute =
dri2_convert_glx_query_renderer_attribs(attribute);
+
+ if (psc->rendererQuery == NULL)
+ return -1;
+
+ return psc->rendererQuery->queryInteger(psc->driScreen, dri_attribute,
+ value);
+}
+
+_X_HIDDEN int
+dri3_query_renderer_string(struct glx_screen *base, int attribute,
+ const char **value)
+{
+ struct dri3_screen *const psc = (struct dri3_screen *) base;
+
+ /* Even though queryString only accepts a subset of the possible GLX
+* queries, the higher level GLX code is required to perform the filtering.
+* Assume that we got a good value.
+*/
+ const int dri_attribute =
dri2_convert_glx_query_renderer_attribs(attribute);
+
+ if (psc->rendererQuery == NULL)
+ return -1;
+
+ return psc->rendererQuery->queryString(psc->driScreen, dri_attribute,
value);
+}
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 70ec057..3b7ee1e 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -79,6 +79,7 @@
#include "dri_common.h"
#include "dri3_priv.h"
#include "loader.h"
+#include "dri2.h"
static const struct glx_context_vtable dri3_context_vtable;
@@ -1580,12 +1581,19 @@ dri3_bind_extensions(struct dri3_screen *psc, struct
glx_display * priv,
if (strcmp(extensions[i]->name, __DRI2_ROBUSTNESS) == 0)
__glXEnableDirectExtension(&psc->base,
"GLX_ARB_create_context_robustness");
+
+ if (strcmp(extensions[i]->name, __DRI2_RENDERER_QUERY) == 0) {
+ psc->rendererQuery = (__DRI2rendererQueryExtension *) extensions[i];
+ __glXEnableDirectExtension(&psc->base, "GLX_MESA_query_renderer");
+ }
}
}
static const struct glx_screen_vtable dri3_screen_vtable = {
dri3_create_context,
- dri3_create_context_attribs
+ dri3_create_context_attribs,
+ dri3_query_renderer_integer,
+ dri3_query_renderer_string,
};
/** dri3_create_screen
diff --git a/src/glx/dri3_priv.h b/src/glx/dri3_priv.h
index 1d124f8..3346a17 100644
--- a/src/glx/dri3_priv.h
+++ b/src/glx/dri3_priv.h
@@ -129,6 +129,7 @@ struct dri3_screen {
const __DRI2flushExtension *f;
const __DRI2configQueryExtension *config;
const __DRItexBufferExtension *texBuffer;
+ const __DRI2rendererQueryExtension *rendererQuery;
const __DRIconfig **driver_configs;
void *driver;
--
1.8.1.4
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[Mesa-dev] [PATCH 00/19] i965/fs clean ups
Matt Turner (19): i965: Reduce predicate field of backend_instruction to uint8_t. i965: Mark brw_reg_type and register_file enums as PACKED. i965/fs: Reduce the sizes of some fs_reg members. i965/fs: Make fs_reg's type an enum for better debugging. i965/fs: Reorder fs_reg for better packing. i965/fs: Reduce the sizes of some fs_inst members. i965/fs: Reorder fs_inst's fields for better packing. i965/fs: Use a bitfield for fs_inst's bool fields. These shrink the backend_instruction, fs_reg, and fs_inst classes by using appropriately sized types and reordering the fields for better packing. i965/fs: Use reg_undef instead of unset fs_reg constructor. i965/fs: Drop redundant zero assignments in fs_inst::init(). i965/fs: Move setting opcode = NOP to its one useful location. i965/fs: Pass fs_regs by constant reference where possible. i965/fs: Make fs_visitor::emit take a constant reference to an fs_inst. Some clean ups, and changes to pass fs_regs and fs_inst by reference. i965/fs: Add and use an fs_inst copy constructor. i965/fs: Disable fs_inst assignment operator. i965/fs: Combine fs_inst constructors using default parameters. i965/fs: ralloc fs_inst's fs_reg sources. i965/fs: Store the number of sources an fs_inst has. i965/fs: Add a function to resize fs_inst's sources array. Change's fs_inst's 3-element fs_reg src array to be a pointer that can be reallocated if necessary. No functional change, as three sources are always allocated. The last three patches will wait for users before being committed. src/mesa/drivers/dri/i965/brw_fs.cpp | 125 +-- src/mesa/drivers/dri/i965/brw_fs.h | 120 + src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 4 +- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 23 ++--- src/mesa/drivers/dri/i965/brw_reg.h | 3 +- src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +- src/mesa/drivers/dri/i965/brw_shader.h | 8 +- 7 files changed, 149 insertions(+), 136 deletions(-) -- 1.8.3.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 02/19] i965: Mark brw_reg_type and register_file enums as PACKED.
Will now take a byte, rather than four.
---
src/mesa/drivers/dri/i965/brw_reg.h| 3 ++-
src/mesa/drivers/dri/i965/brw_shader.h | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index 978dd3f..6f48b7d 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -43,6 +43,7 @@
#define BRW_REG_H
#include
+#include "main/compiler.h"
#include "program/prog_instruction.h"
#include "brw_defines.h"
@@ -88,7 +89,7 @@ brw_is_single_value_swizzle(int swiz)
swiz == BRW_SWIZZLE_);
}
-enum brw_reg_type {
+enum PACKED brw_reg_type {
BRW_REGISTER_TYPE_UD = 0,
BRW_REGISTER_TYPE_D,
BRW_REGISTER_TYPE_UW,
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index 4c79861..4d98cbc 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -23,11 +23,12 @@
#include
#include "brw_defines.h"
+#include "main/compiler.h"
#include "glsl/ir.h"
#pragma once
-enum register_file {
+enum PACKED register_file {
BAD_FILE,
GRF,
MRF,
--
1.8.3.2
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[Mesa-dev] [PATCH 05/19] i965/fs: Reorder fs_reg for better packing.
---
src/mesa/drivers/dri/i965/brw_fs.h | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index d3a5f85..a1f7222 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -85,9 +85,13 @@ public:
bool is_contiguous() const;
fs_reg retype(enum brw_reg_type type);
fs_reg &apply_stride(unsigned stride);
+ /** Smear a channel of the reg to all channels. */
+ fs_reg &set_smear(unsigned subreg);
/** Register file: GRF, MRF, IMM. */
enum register_file file;
+ /** Register type. BRW_REGISTER_TYPE_* */
+ enum brw_reg_type type;
/**
* Register number. For MRF, it's the hardware register. For
* GRF, it's a virtual register number until register allocation
@@ -101,14 +105,11 @@ public:
* For uniforms, this is in units of 1 float.
*/
int reg_offset;
- /** Register type. BRW_REGISTER_TYPE_* */
- enum brw_reg_type type;
- bool negate;
- bool abs;
- struct brw_reg fixed_hw_reg;
-
- /** Smear a channel of the reg to all channels. */
- fs_reg &set_smear(unsigned subreg);
+ /**
+* Offset in bytes from the start of the register. Values up to a
+* backend_reg::reg_offset unit are valid.
+*/
+ int subreg_offset;
/** Value for file == IMM */
union {
@@ -117,16 +118,15 @@ public:
float f;
} imm;
- /**
-* Offset in bytes from the start of the register. Values up to a
-* backend_reg::reg_offset unit are valid.
-*/
- int subreg_offset;
+ struct brw_reg fixed_hw_reg;
+
+ fs_reg *reladdr;
+
+ bool negate;
+ bool abs;
/** Register region horizontal stride */
uint8_t stride;
-
- fs_reg *reladdr;
};
static inline fs_reg
--
1.8.3.2
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[Mesa-dev] [PATCH 01/19] i965: Reduce predicate field of backend_instruction to uint8_t.
--- src/mesa/drivers/dri/i965/brw_shader.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index c76f33b..4c79861 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -56,7 +56,7 @@ public: enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */ - uint32_t predicate; + uint8_t predicate; bool predicate_inverse; }; -- 1.8.3.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 06/19] i965/fs: Reduce the sizes of some fs_inst members.
--- src/mesa/drivers/dri/i965/brw_fs.h | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index a1f7222..7da66ed 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -193,19 +193,19 @@ public: fs_reg dst; fs_reg src[3]; bool saturate; - int conditional_mod; /**< BRW_CONDITIONAL_* */ + uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */ /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional * mod and predication. */ uint8_t flag_subreg; - int mlen; /**< SEND message length */ - int regs_written; /**< Number of vgrfs written by a SEND message, or 1 */ - int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */ + uint8_t mlen; /**< SEND message length */ + uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */ + int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */ uint32_t texture_offset; /**< Texture offset bitfield */ - int sampler; - int target; /**< MRT target. */ + uint8_t sampler; + uint8_t target; /**< MRT target. */ bool eot; bool header_present; bool shadow_compare; -- 1.8.3.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 03/19] i965/fs: Reduce the sizes of some fs_reg members.
--- src/mesa/drivers/dri/i965/brw_fs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index c6f4ffb..38fa34b 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -92,7 +92,7 @@ public: * Register number. For MRF, it's the hardware register. For * GRF, it's a virtual register number until register allocation */ - int reg; + uint16_t reg; /** * Offset from the start of the contiguous register block. * @@ -102,7 +102,7 @@ public: */ int reg_offset; /** Register type. BRW_REGISTER_TYPE_* */ - int type; + uint8_t type; bool negate; bool abs; struct brw_reg fixed_hw_reg; @@ -124,7 +124,7 @@ public: int subreg_offset; /** Register region horizontal stride */ - int stride; + uint8_t stride; fs_reg *reladdr; }; -- 1.8.3.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 04/19] i965/fs: Make fs_reg's type an enum for better debugging.
Since the enum is marked as packed, it'll still take only one byte.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +++---
src/mesa/drivers/dri/i965/brw_fs.h | 6 +++---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_shader.h | 3 ++-
4 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 4f5558b..4940738 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -423,7 +423,7 @@ fs_reg::fs_reg(struct brw_reg fixed_hw_reg)
init();
this->file = HW_REG;
this->fixed_hw_reg = fixed_hw_reg;
- this->type = fixed_hw_reg.type;
+ this->type = (enum brw_reg_type)fixed_hw_reg.type;
}
bool
@@ -444,7 +444,7 @@ fs_reg::equals(const fs_reg &r) const
}
fs_reg
-fs_reg::retype(uint32_t type)
+fs_reg::retype(enum brw_reg_type type)
{
fs_reg result = *this;
result.type = type;
@@ -844,7 +844,7 @@ fs_reg::fs_reg(enum register_file file, int reg)
}
/** Fixed HW reg constructor. */
-fs_reg::fs_reg(enum register_file file, int reg, uint32_t type)
+fs_reg::fs_reg(enum register_file file, int reg, enum brw_reg_type type)
{
init();
this->file = file;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 38fa34b..d3a5f85 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -74,7 +74,7 @@ public:
fs_reg(uint32_t u);
fs_reg(struct brw_reg fixed_hw_reg);
fs_reg(enum register_file file, int reg);
- fs_reg(enum register_file file, int reg, uint32_t type);
+ fs_reg(enum register_file file, int reg, enum brw_reg_type type);
fs_reg(class fs_visitor *v, const struct glsl_type *type);
bool equals(const fs_reg &r) const;
@@ -83,7 +83,7 @@ public:
bool is_null() const;
bool is_valid_3src() const;
bool is_contiguous() const;
- fs_reg retype(uint32_t type);
+ fs_reg retype(enum brw_reg_type type);
fs_reg &apply_stride(unsigned stride);
/** Register file: GRF, MRF, IMM. */
@@ -102,7 +102,7 @@ public:
*/
int reg_offset;
/** Register type. BRW_REGISTER_TYPE_* */
- uint8_t type;
+ enum brw_reg_type type;
bool negate;
bool abs;
struct brw_reg fixed_hw_reg;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index d58c13d..1dcb583 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -282,7 +282,7 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
}
-int
+enum brw_reg_type
brw_type_for_base_type(const struct glsl_type *type)
{
switch (type->base_type) {
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
b/src/mesa/drivers/dri/i965/brw_shader.h
index 4d98cbc..bbbeb32 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -23,6 +23,7 @@
#include
#include "brw_defines.h"
+#include "brw_reg.h"
#include "main/compiler.h"
#include "glsl/ir.h"
@@ -99,7 +100,7 @@ uint32_t brw_texture_offset(struct gl_context *ctx,
ir_constant *offset);
#endif /* __cplusplus */
-int brw_type_for_base_type(const struct glsl_type *type);
+enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
uint32_t brw_conditional_for_comparison(unsigned int op);
uint32_t brw_math_function(enum opcode op);
const char *brw_instruction_name(enum opcode op);
--
1.8.3.2
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[Mesa-dev] [PATCH 07/19] i965/fs: Reorder fs_inst's fields for better packing.
---
src/mesa/drivers/dri/i965/brw_fs.h | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 7da66ed..b4e69ba 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -192,6 +192,17 @@ public:
fs_reg dst;
fs_reg src[3];
+
+ /** @{
+* Annotation for the generated IR. One of the two can be set.
+*/
+ const void *ir;
+ const char *annotation;
+ /** @} */
+
+ uint32_t texture_offset; /**< Texture offset bitfield */
+ uint32_t offset; /* spill/unspill offset */
+
bool saturate;
uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
@@ -203,7 +214,6 @@ public:
uint8_t mlen; /**< SEND message length */
uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1
*/
int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
- uint32_t texture_offset; /**< Texture offset bitfield */
uint8_t sampler;
uint8_t target; /**< MRT target. */
bool eot;
@@ -212,14 +222,6 @@ public:
bool force_uncompressed;
bool force_sechalf;
bool force_writemask_all;
- uint32_t offset; /* spill/unspill offset */
-
- /** @{
-* Annotation for the generated IR. One of the two can be set.
-*/
- const void *ir;
- const char *annotation;
- /** @} */
};
/**
--
1.8.3.2
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[Mesa-dev] [PATCH 13/19] i965/fs: Make fs_visitor::emit take a constant reference to an fs_inst.
It makes a copy internally, so making a second copy is unnecessary.
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index da4ef2a..fe063e6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -269,7 +269,7 @@ public:
bool can_do_source_mods(fs_inst *inst);
- fs_inst *emit(fs_inst inst);
+ fs_inst *emit(const fs_inst &inst);
fs_inst *emit(fs_inst *inst);
void emit(exec_list list);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 0c376a7..b28d7aa 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2439,7 +2439,7 @@ fs_visitor::emit_untyped_surface_read(unsigned
surf_index, fs_reg dst,
}
fs_inst *
-fs_visitor::emit(fs_inst inst)
+fs_visitor::emit(const fs_inst &inst)
{
fs_inst *list_inst = new(mem_ctx) fs_inst;
*list_inst = inst;
--
1.8.3.2
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[Mesa-dev] [PATCH 17/19] i965/fs: ralloc fs_inst's fs_reg sources.
Potentially we'll want more than three sources for Phi nodes.
To avoid passing a mem_ctx parameter into each fs_inst() constructor, we
add a static thread-local variable to fs_inst that we set in the
fs_visitor() constructor.
---
Is __thread good enough? What about multi-context GL?
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 ++
src/mesa/drivers/dri/i965/brw_fs.h | 4 +++-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 ++
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 77cdfa2..4d13446 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -51,10 +51,15 @@ extern "C" {
#include "brw_fs_live_variables.h"
#include "glsl/glsl_types.h"
+__thread void *fs_inst::mem_ctx;
+
void
fs_inst::init()
{
memset(this, 0, sizeof(*this));
+ assert(fs_inst::mem_ctx != NULL);
+
+ this->src = rzalloc_array(mem_ctx, fs_reg, 3);
/* This will be the case for almost all instructions. */
this->regs_written = 1;
@@ -111,6 +116,11 @@ dst:
fs_inst::fs_inst(const fs_inst &that)
{
memcpy(this, &that, sizeof(that));
+
+ this->src = ralloc_array(mem_ctx, fs_reg, 3);
+
+ for (int i = 0; i < 3; i++)
+ this->src[i] = that.src[i];
}
#define ALU1(op)\
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index f73f835..3623000 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -192,7 +192,7 @@ public:
bool writes_flag();
fs_reg dst;
- fs_reg src[3];
+ fs_reg *src;
/** @{
* Annotation for the generated IR. One of the two can be set.
@@ -223,6 +223,8 @@ public:
uint8_t force_uncompressed:1;
uint8_t force_sechalf:1;
uint8_t force_writemask_all:1;
+
+ static __thread void *mem_ctx;
};
/**
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 76f93c9..89f39a5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2947,6 +2947,7 @@ fs_visitor::fs_visitor(struct brw_context *brw,
this->stage_prog_data = &c->prog_data.base;
this->ctx = &brw->ctx;
this->mem_ctx = ralloc_context(NULL);
+ fs_inst::mem_ctx = this->mem_ctx;
if (shader_prog)
shader = (struct brw_shader *)
shader_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
@@ -2986,5 +2987,6 @@ fs_visitor::fs_visitor(struct brw_context *brw,
fs_visitor::~fs_visitor()
{
ralloc_free(this->mem_ctx);
+ fs_inst::mem_ctx = NULL;
hash_table_dtor(this->variable_ht);
}
--
1.8.3.2
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[Mesa-dev] [PATCH 15/19] i965/fs: Disable fs_inst assignment operator.
The fs_reg src array is going to turn into a pointer and we'd rather not
consider the implications of shallow copying fs_insts.
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 054008e..77df64b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -168,6 +168,8 @@ public:
};
class fs_inst : public backend_instruction {
+ fs_inst &operator=(const fs_inst &);
+
public:
DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
--
1.8.3.2
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[Mesa-dev] [PATCH 10/19] i965/fs: Drop redundant zero assignments in fs_inst::init().
Unfortunately the compiler isn't able to recognize that assigning
reg_undef is just zeroing the fs_reg, which was already done by the
above memset.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 --
1 file changed, 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index ae1237e..e51cdbd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -56,12 +56,6 @@ fs_inst::init()
{
memset(this, 0, sizeof(*this));
this->opcode = BRW_OPCODE_NOP;
- this->conditional_mod = BRW_CONDITIONAL_NONE;
-
- this->dst = reg_undef;
- this->src[0] = reg_undef;
- this->src[1] = reg_undef;
- this->src[2] = reg_undef;
/* This will be the case for almost all instructions. */
this->regs_written = 1;
--
1.8.3.2
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[Mesa-dev] [PATCH 19/19] i965/fs: Add a function to resize fs_inst's sources array.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +
src/mesa/drivers/dri/i965/brw_fs.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 997b411..ce50e8b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -124,6 +124,15 @@ fs_inst::fs_inst(const fs_inst &that)
this->src[i] = that.src[i];
}
+void
+fs_inst::resize_sources(uint8_t num_sources)
+{
+ if (this->sources != num_sources) {
+ this->src = reralloc(mem_ctx, this->src, fs_reg, num_sources);
+ this->sources = num_sources;
+ }
+}
+
#define ALU1(op)\
fs_inst *\
fs_visitor::op(fs_reg dst, fs_reg src0) \
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 6929a26..b086d5d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -182,6 +182,8 @@ public:
const fs_reg &src2 = reg_undef);
fs_inst(const fs_inst &that);
+ void resize_sources(uint8_t num_sources);
+
bool equals(fs_inst *inst);
bool overwrites_reg(const fs_reg ®);
bool is_send_from_grf();
--
1.8.3.2
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[Mesa-dev] [PATCH 12/19] i965/fs: Pass fs_regs by constant reference where possible.
These functions (modulo emit_lrp, necessitating the small fix-up) pass
these arguments by value unmodified to other functions. No point in
making an additional copy.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 7 ---
src/mesa/drivers/dri/i965/brw_fs.h | 14 --
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 12 +++-
3 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 37b5bb0..7dc83ad 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -238,8 +238,9 @@ fs_visitor::CMP(fs_reg dst, fs_reg src0, fs_reg src1,
uint32_t condition)
}
exec_list
-fs_visitor::VARYING_PULL_CONSTANT_LOAD(fs_reg dst, fs_reg surf_index,
- fs_reg varying_offset,
+fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
+ const fs_reg &surf_index,
+ const fs_reg &varying_offset,
uint32_t const_offset)
{
exec_list instructions;
@@ -3191,7 +3192,7 @@ fs_visitor::dump_instruction(backend_instruction *be_inst)
fs_inst *
fs_visitor::get_instruction_generating_reg(fs_inst *start,
fs_inst *end,
- fs_reg reg)
+ const fs_reg ®)
{
if (end == start ||
end->is_partial_write() ||
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index a1f33e7..da4ef2a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -317,10 +317,11 @@ public:
int type_size(const struct glsl_type *type);
fs_inst *get_instruction_generating_reg(fs_inst *start,
fs_inst *end,
- fs_reg reg);
+ const fs_reg ®);
- exec_list VARYING_PULL_CONSTANT_LOAD(fs_reg dst, fs_reg surf_index,
-fs_reg varying_offset,
+ exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
+const fs_reg &surf_index,
+const fs_reg &varying_offset,
uint32_t const_offset);
bool run();
@@ -399,9 +400,10 @@ public:
fs_reg fix_math_operand(fs_reg src);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
- void emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a);
- void emit_minmax(uint32_t conditionalmod, fs_reg dst,
-fs_reg src0, fs_reg src1);
+ void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
+ const fs_reg &a);
+ void emit_minmax(uint32_t conditionalmod, const fs_reg &dst,
+const fs_reg &src0, const fs_reg &src1);
bool try_emit_saturate(ir_expression *ir);
bool try_emit_mad(ir_expression *ir, int mul_arg);
void try_replace_with_sel();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 172ad6e..0c376a7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -212,7 +212,8 @@ fs_visitor::visit(ir_dereference_array *ir)
}
void
-fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a)
+fs_visitor::emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
+ const fs_reg &a)
{
if (brw->gen < 6 ||
!x.is_valid_3src() ||
@@ -225,8 +226,9 @@ fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg
a)
emit(MUL(y_times_a, y, a));
- a.negate = !a.negate;
- emit(ADD(one_minus_a, a, fs_reg(1.0f)));
+ fs_reg negative_a = a;
+ negative_a.negate = !a.negate;
+ emit(ADD(one_minus_a, negative_a, fs_reg(1.0f)));
emit(MUL(x_times_one_minus_a, x, one_minus_a));
emit(ADD(dst, x_times_one_minus_a, y_times_a));
@@ -239,8 +241,8 @@ fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg
a)
}
void
-fs_visitor::emit_minmax(uint32_t conditionalmod, fs_reg dst,
-fs_reg src0, fs_reg src1)
+fs_visitor::emit_minmax(uint32_t conditionalmod, const fs_reg &dst,
+const fs_reg &src0, const fs_reg &src1)
{
fs_inst *inst;
--
1.8.3.2
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[Mesa-dev] [PATCH 11/19] i965/fs: Move setting opcode = NOP to its one useful location.
All other callers of init() immediately set opcode to something else.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index e51cdbd..37b5bb0 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -55,7 +55,6 @@ void
fs_inst::init()
{
memset(this, 0, sizeof(*this));
- this->opcode = BRW_OPCODE_NOP;
/* This will be the case for almost all instructions. */
this->regs_written = 1;
@@ -64,6 +63,7 @@ fs_inst::init()
fs_inst::fs_inst()
{
init();
+ this->opcode = BRW_OPCODE_NOP;
}
fs_inst::fs_inst(enum opcode opcode)
--
1.8.3.2
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[Mesa-dev] [PATCH 08/19] i965/fs: Use a bitfield for fs_inst's bool fields.
--- src/mesa/drivers/dri/i965/brw_fs.h | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index b4e69ba..a1f33e7 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -203,7 +203,6 @@ public: uint32_t texture_offset; /**< Texture offset bitfield */ uint32_t offset; /* spill/unspill offset */ - bool saturate; uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */ /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional @@ -216,12 +215,13 @@ public: int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */ uint8_t sampler; uint8_t target; /**< MRT target. */ - bool eot; - bool header_present; - bool shadow_compare; - bool force_uncompressed; - bool force_sechalf; - bool force_writemask_all; + uint8_t saturate:1; + uint8_t eot:1; + uint8_t header_present:1; + uint8_t shadow_compare:1; + uint8_t force_uncompressed:1; + uint8_t force_sechalf:1; + uint8_t force_writemask_all:1; }; /** -- 1.8.3.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 18/19] i965/fs: Store the number of sources an fs_inst has.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 13 +++--
src/mesa/drivers/dri/i965/brw_fs.h | 3 ++-
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 4d13446..997b411 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -54,12 +54,13 @@ extern "C" {
__thread void *fs_inst::mem_ctx;
void
-fs_inst::init()
+fs_inst::init(int sources)
{
memset(this, 0, sizeof(*this));
assert(fs_inst::mem_ctx != NULL);
- this->src = rzalloc_array(mem_ctx, fs_reg, 3);
+ this->sources = sources;
+ this->src = rzalloc_array(mem_ctx, fs_reg, sources);
/* This will be the case for almost all instructions. */
this->regs_written = 1;
@@ -67,7 +68,7 @@ fs_inst::init()
fs_inst::fs_inst()
{
- init();
+ init(3);
this->opcode = BRW_OPCODE_NOP;
}
@@ -81,7 +82,7 @@ fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst,
if (&src1 == ®_undef)
assert(&src2 == ®_undef);
- init();
+ init(3);
if (&src2 != ®_undef) {
goto src2;
@@ -117,9 +118,9 @@ fs_inst::fs_inst(const fs_inst &that)
{
memcpy(this, &that, sizeof(that));
- this->src = ralloc_array(mem_ctx, fs_reg, 3);
+ this->src = ralloc_array(mem_ctx, fs_reg, that.sources);
- for (int i = 0; i < 3; i++)
+ for (int i = 0; i < that.sources; i++)
this->src[i] = that.src[i];
}
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 3623000..6929a26 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -173,7 +173,7 @@ class fs_inst : public backend_instruction {
public:
DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
- void init();
+ void init(int sources);
fs_inst();
fs_inst(enum opcode opcode, const fs_reg &dst = reg_undef,
@@ -204,6 +204,7 @@ public:
uint32_t texture_offset; /**< Texture offset bitfield */
uint32_t offset; /* spill/unspill offset */
+ uint8_t sources; /**< Number of fs_reg sources. */
uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
--
1.8.3.2
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[Mesa-dev] [PATCH 14/19] i965/fs: Add and use an fs_inst copy constructor.
Will get more complicated when fs_reg src becomes a pointer.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 5 +
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 +--
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 7dc83ad..77b9f57 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -131,6 +131,11 @@ fs_inst::fs_inst(enum opcode opcode, fs_reg dst,
assert(src[2].reg_offset >= 0);
}
+fs_inst::fs_inst(const fs_inst &that)
+{
+ memcpy(this, &that, sizeof(that));
+}
+
#define ALU1(op)\
fs_inst *\
fs_visitor::op(fs_reg dst, fs_reg src0) \
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index fe063e6..054008e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -180,6 +180,7 @@ public:
fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
fs_inst(enum opcode opcode, fs_reg dst,
fs_reg src0, fs_reg src1,fs_reg src2);
+ fs_inst(const fs_inst &that);
bool equals(fs_inst *inst);
bool overwrites_reg(const fs_reg ®);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index b28d7aa..76f93c9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2441,8 +2441,7 @@ fs_visitor::emit_untyped_surface_read(unsigned
surf_index, fs_reg dst,
fs_inst *
fs_visitor::emit(const fs_inst &inst)
{
- fs_inst *list_inst = new(mem_ctx) fs_inst;
- *list_inst = inst;
+ fs_inst *list_inst = new(mem_ctx) fs_inst(inst);
emit(list_inst);
return list_inst;
}
--
1.8.3.2
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[Mesa-dev] [PATCH 09/19] i965/fs: Use reg_undef instead of unset fs_reg constructor.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 4940738..ae1237e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -650,7 +650,7 @@ fs_visitor::emit_shader_time_write(enum
shader_time_shader_type type,
payload = fs_reg(this, glsl_type::uint_type);
emit(fs_inst(SHADER_OPCODE_SHADER_TIME_ADD,
-fs_reg(), payload, offset, value));
+reg_undef, payload, offset, value));
}
void
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 1d42f6b..b0c43af 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -675,7 +675,7 @@ fs_visitor::get_fp_dst_reg(const prog_dst_register *dst)
}
case PROGRAM_UNDEFINED:
- return fs_reg();
+ return reg_undef;
default:
_mesa_problem(ctx, "bad dst register file: %s\n",
@@ -695,7 +695,7 @@ fs_visitor::get_fp_src_reg(const prog_src_register *src)
switch (src->File) {
case PROGRAM_UNDEFINED:
- return fs_reg();
+ return reg_undef;
case PROGRAM_TEMPORARY:
result = fp_temp_regs[src->Index];
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 45b053d..172ad6e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2288,11 +2288,11 @@ fs_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
} else if (!strcmp("__intrinsic_atomic_increment", callee)) {
emit_untyped_atomic(BRW_AOP_INC, surf_index, dst, offset,
- fs_reg(), fs_reg());
+ reg_undef, reg_undef);
} else if (!strcmp("__intrinsic_atomic_predecrement", callee)) {
emit_untyped_atomic(BRW_AOP_PREDEC, surf_index, dst, offset,
- fs_reg(), fs_reg());
+ reg_undef, reg_undef);
}
}
--
1.8.3.2
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[Mesa-dev] [PATCH 16/19] i965/fs: Combine fs_inst constructors using default parameters.
Wouldn't it be nice if case labels could be non-constant expressions.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 77 +---
src/mesa/drivers/dri/i965/brw_fs.h | 10 ++---
2 files changed, 31 insertions(+), 56 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 77b9f57..77cdfa2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -66,69 +66,46 @@ fs_inst::fs_inst()
this->opcode = BRW_OPCODE_NOP;
}
-fs_inst::fs_inst(enum opcode opcode)
+fs_inst::fs_inst(enum opcode opcode, const fs_reg &dst,
+ const fs_reg &src0, const fs_reg &src1, const fs_reg &src2)
{
- init();
- this->opcode = opcode;
-}
+ if (&dst == ®_undef)
+ assert(&src0 == ®_undef);
+ if (&src0 == ®_undef)
+ assert(&src1 == ®_undef);
+ if (&src1 == ®_undef)
+ assert(&src2 == ®_undef);
-fs_inst::fs_inst(enum opcode opcode, fs_reg dst)
-{
init();
- this->opcode = opcode;
- this->dst = dst;
- if (dst.file == GRF)
- assert(dst.reg_offset >= 0);
-}
+ if (&src2 != ®_undef) {
+ goto src2;
+ } else if (&src1 != ®_undef) {
+ goto src1;
+ } else if (&src0 != ®_undef) {
+ goto src0;
+ } else if (&dst != ®_undef) {
+ goto dst;
+ }
-fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0)
-{
- init();
- this->opcode = opcode;
- this->dst = dst;
+src2:
+ this->src[2] = src2;
+ if (src[2].file == GRF)
+ assert(src[2].reg_offset >= 0);
+src1:
+ this->src[1] = src1;
+ if (src[1].file == GRF)
+ assert(src[1].reg_offset >= 0);
+src0:
this->src[0] = src0;
-
- if (dst.file == GRF)
- assert(dst.reg_offset >= 0);
if (src[0].file == GRF)
assert(src[0].reg_offset >= 0);
-}
-
-fs_inst::fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
-{
- init();
- this->opcode = opcode;
+dst:
this->dst = dst;
- this->src[0] = src0;
- this->src[1] = src1;
-
if (dst.file == GRF)
assert(dst.reg_offset >= 0);
- if (src[0].file == GRF)
- assert(src[0].reg_offset >= 0);
- if (src[1].file == GRF)
- assert(src[1].reg_offset >= 0);
-}
-fs_inst::fs_inst(enum opcode opcode, fs_reg dst,
-fs_reg src0, fs_reg src1, fs_reg src2)
-{
- init();
this->opcode = opcode;
- this->dst = dst;
- this->src[0] = src0;
- this->src[1] = src1;
- this->src[2] = src2;
-
- if (dst.file == GRF)
- assert(dst.reg_offset >= 0);
- if (src[0].file == GRF)
- assert(src[0].reg_offset >= 0);
- if (src[1].file == GRF)
- assert(src[1].reg_offset >= 0);
- if (src[2].file == GRF)
- assert(src[2].reg_offset >= 0);
}
fs_inst::fs_inst(const fs_inst &that)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 77df64b..f73f835 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -176,12 +176,10 @@ public:
void init();
fs_inst();
- fs_inst(enum opcode opcode);
- fs_inst(enum opcode opcode, fs_reg dst);
- fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
- fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
- fs_inst(enum opcode opcode, fs_reg dst,
- fs_reg src0, fs_reg src1,fs_reg src2);
+ fs_inst(enum opcode opcode, const fs_reg &dst = reg_undef,
+ const fs_reg &src0 = reg_undef,
+ const fs_reg &src1 = reg_undef,
+ const fs_reg &src2 = reg_undef);
fs_inst(const fs_inst &that);
bool equals(fs_inst *inst);
--
1.8.3.2
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[Mesa-dev] [Bug 71870] Metro: Last Light rendering issues
https://bugs.freedesktop.org/show_bug.cgi?id=71870 Thomas Rohloff changed: What|Removed |Added Status|VERIFIED|REOPENED Resolution|FIXED |--- --- Comment #47 from Thomas Rohloff --- (In reply to comment #40) > Bugzilla: Khronos #11702 https://www.khronos.org/bugzilla/show_bug.cgi?id=11702 gives me "Bug #11702 does not exist." -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 71870] Metro: Last Light rendering issues
https://bugs.freedesktop.org/show_bug.cgi?id=71870 Kenneth Graunke changed: What|Removed |Added Status|REOPENED|RESOLVED Resolution|--- |FIXED --- Comment #48 from Kenneth Graunke --- It's not in the public Khronos bug tracker. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 75286] New: make error with Gallium i915/DRM configuration
https://bugs.freedesktop.org/show_bug.cgi?id=75286
Priority: medium
Bug ID: 75286
Assignee: mesa-dev@lists.freedesktop.org
Summary: make error with Gallium i915/DRM configuration
Severity: normal
Classification: Unclassified
OS: All
Reporter: christian.procha...@genode-labs.com
Hardware: Other
Status: NEW
Version: git
Component: EGL
Product: Mesa
(git master 313402048fdad05d3401340129b9e412878d8957 with the patches from
Bugzilla entries 75098 and 75126)
When building with the following configuration:
./configure --enable-gles2 --disable-dri --enable-gallium-egl
--with-egl-platforms=drm --with-gallium-drivers=i915
the following error occurs:
...
Making all in gallium/targets
make[2]: Entering directory
`/home/christian/projects/mesa/mesa/src/gallium/targets'
Making all in egl-static
make[3]: Entering directory
`/home/christian/projects/mesa/mesa/src/gallium/targets/egl-static'
CC egl.lo
CC egl_pipe.lo
CC egl_st.lo
make[3]: *** No rule to make target
`../../../../src/gallium/winsys/i915/drm/libi915drm.la', needed by
`egl_gallium.la'. Stop.
Perhaps it has to do with the configuration output not having 'i915/drm' in the
'Winsys dirs' line?
---
prefix: /usr/local
exec_prefix: ${prefix}
libdir: ${exec_prefix}/lib
includedir: ${prefix}/include
OpenGL: yes (ES1: no ES2: yes)
OpenVG: no
OSMesa: no
GLX: no
EGL: yes
EGL platforms: drm
EGL drivers: egl_gallium
EGL Gallium STs: $(GL_LIB)
llvm:no
Gallium: yes
Target dirs: egl-static
Winsys dirs: i915/sw sw
Driver dirs: galahad i915 identity noop rbug softpipe trace
Trackers dirs: egl
Shared libs: yes
Static libs: no
Shared-glapi:yes
CFLAGS: -g -O2 -Wall -std=c99
-Werror=implicit-function-declaration -Werror=missing-prototypes
-fno-strict-aliasing -fno-builtin-memcmp
CXXFLAGS:-g -O2 -Wall -fno-strict-aliasing -fno-builtin-memcmp
Macros: -D_GNU_SOURCE -DHAVE_PTHREAD -DUSE_X86_ASM
-DUSE_MMX_ASM -DUSE_3DNOW_ASM -DUSE_SSE_ASM -DHAVE_DLOPEN -DHAVE_POSIX_MEMALIGN
-DHAVE_LIBDRM -DHAVE_LIBUDEV -DHAVE_MINCORE -DMESA_EGL_NO_X11_HEADERS
PYTHON2: python2
--
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[Mesa-dev] [PATCH] tgsi_ureg: add property_gs_invocations
Fixes a build break in state_tracker/st_program.c
Signed-off-by: Jordan Justen
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75278
Cc: Vinson Lee
---
src/gallium/auxiliary/tgsi/tgsi_ureg.c | 7 +++
src/gallium/auxiliary/tgsi/tgsi_ureg.h | 4
2 files changed, 11 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index f928f57..38cce58 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -168,6 +168,7 @@ struct ureg_program
unsigned property_gs_input_prim;
unsigned property_gs_output_prim;
unsigned property_gs_max_vertices;
+ unsigned property_gs_invocations;
unsigned char property_fs_coord_origin; /* = TGSI_FS_COORD_ORIGIN_* */
unsigned char property_fs_coord_pixel_center; /* =
TGSI_FS_COORD_PIXEL_CENTER_* */
unsigned char property_fs_color0_writes_all_cbufs; /* =
TGSI_FS_COLOR0_WRITES_ALL_CBUFS * */
@@ -295,6 +296,12 @@ ureg_property_gs_max_vertices(struct ureg_program *ureg,
{
ureg->property_gs_max_vertices = max_vertices;
}
+void
+ureg_property_gs_invocations(struct ureg_program *ureg,
+ unsigned invocations)
+{
+ ureg->property_gs_invocations = invocations;
+}
void
ureg_property_fs_coord_origin(struct ureg_program *ureg,
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
index e225984..a0a50b7 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
@@ -165,6 +165,10 @@ ureg_property_gs_max_vertices(struct ureg_program *ureg,
unsigned max_vertices);
void
+ureg_property_gs_invocations(struct ureg_program *ureg,
+ unsigned invocations);
+
+void
ureg_property_fs_coord_origin(struct ureg_program *ureg,
unsigned fs_coord_origin);
--
1.9.rc1
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[Mesa-dev] [Bug 75286] make error with Gallium i915/DRM configuration
https://bugs.freedesktop.org/show_bug.cgi?id=75286 --- Comment #1 from Emil Velikov --- The gallium i915 is a bit special, as it's the only driver to have both sw and drm based winsys. When you disable dri, you essentially state "there will be no drm winsys", thus the makefile should handle the libraries it tries to link. I highly suspect that the issue was present since day one, just that before you were not allowed to build such a config. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 75286] make error with Gallium i915/DRM configuration
https://bugs.freedesktop.org/show_bug.cgi?id=75286 --- Comment #2 from Stephane Marchesin --- I wonder if we should just remove the i915 sw winsys... I certainly don't use/test it and it's confusing (like in this case where people thing they're still getting acceleration). -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 75286] make error with Gallium i915/DRM configuration
https://bugs.freedesktop.org/show_bug.cgi?id=75286 --- Comment #3 from Christian Prochaska --- So, which configuration would be the one to use for accelerated rendering on i915 without X11? -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 75286] make error with Gallium i915/DRM configuration
https://bugs.freedesktop.org/show_bug.cgi?id=75286 --- Comment #4 from Emil Velikov --- (In reply to comment #2) > I wonder if we should just remove the i915 sw winsys... I certainly don't > use/test it and it's confusing (like in this case where people thing they're > still getting acceleration). While going through glx_mesa_query_renderer I asked myself - how much i915 is used/tested nowadays ? (In reply to comment #3) > So, which configuration would be the one to use for accelerated rendering on > i915 without X11? dri does not imply X11 in this case. You should be able to run i915/drm on a X-less system. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Avoid dependency hints on math opcodes
On 02/12/2014 04:24 PM, m...@lunarg.com wrote:
> From: Mike Stroyan
>
> Putting NoDDClr and NoDDChk dependency control on instruction
> sequences that include math opcodes can cause corruption of channels.
> Treat math opcodes like send opcodes and suppress dependency hinting.
Since you've analyised the failure in the real application, can you
produce a minimal shader_runner test case that exhibits the same
problem? Eric mentioned to me that he'd like to play with it to better
understand what's going on...
> Signed-off-by: Mike Stroyan
> Tested-by: Tony Bertapelli
> ---
> src/mesa/drivers/dri/i965/brw_vec4.cpp | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index dd23ed4..1c42ca8 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> @@ -717,6 +717,14 @@ vec4_visitor::opt_set_dependency_control()
> continue;
> }
>
> + /* Dependency control does not work well over math instructions.
> + */
> + if (inst->is_math()) {
> +memset(last_grf_write, 0, sizeof(last_grf_write));
> +memset(last_mrf_write, 0, sizeof(last_mrf_write));
> +continue;
> + }
> +
> /* Now, see if we can do dependency control for this instruction
>* against a previous one writing to its destination.
>*/
>
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[Mesa-dev] [Bug 75286] make error with Gallium i915/DRM configuration
https://bugs.freedesktop.org/show_bug.cgi?id=75286 --- Comment #5 from Stephane Marchesin --- (In reply to comment #4) > (In reply to comment #2) > > I wonder if we should just remove the i915 sw winsys... I certainly don't > > use/test it and it's confusing (like in this case where people thing they're > > still getting acceleration). > > While going through glx_mesa_query_renderer I asked myself - how much i915 > is used/tested nowadays ? I ship i915g on Chrome OS, so it is maintained. I don't encounter many issues with it, though, so there's not many commits. As for i915 + sw winsys, probably no one uses it. Maybe we should ask on the list. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/6] i965: Fix miptree matching for multisampled, non-interleaved miptrees.
On 02/19/2014 05:30 PM, Eric Anholt wrote: > We haven't been executing this code before the meta-blit case, because > we've been flagging the miptree as validated at texstorage time, and never > having to revalidate. > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 ++- > src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 ++ > 2 files changed, 16 insertions(+), 1 deletion(-) This series is: Reviewed-by: Kenneth Graunke For patch 1, I verified that physical_depth0 is scaled by mt->num_samples for UMS and CMS layouts, which trickles down to mt->level[level].depth. For patch 3, I believe the code matches the behavior we want. The rest I read carefully, including making sure the merging algorithms work. signature.asc Description: OpenPGP digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 75278] st_program.c:1099: undefined reference to `ureg_property_gs_invocations'
https://bugs.freedesktop.org/show_bug.cgi?id=75278 Jordan Justen changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #1 from Jordan Justen --- Fixed in c97763ca2d740bd44062a81def9a49a03dcc0424 -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 75286] make error with Gallium i915/DRM configuration
https://bugs.freedesktop.org/show_bug.cgi?id=75286 --- Comment #6 from Christian Prochaska --- (In reply to comment #4) > (In reply to comment #2) > > I wonder if we should just remove the i915 sw winsys... I certainly don't > > use/test it and it's confusing (like in this case where people thing they're > > still getting acceleration). > > While going through glx_mesa_query_renderer I asked myself - how much i915 > is used/tested nowadays ? As for my use case, I'm currently planning to upgrade our Mesa 7.8 port for the Genode OS Framework to Mesa 10. Back then, we had a spare IBM T60 notebook, so the i915 driver was the one which got ported (including the kernel part of the driver, since it is a non-Unix OS). I was not involved in the porting work then, so this topic is quite new to me and I'd like to stick with the i915 for now to limit the initial porting work to the Mesa part. The long-term goal is to support more recent hardware, though, so the i915 support is rather a temporary need. > > (In reply to comment #3) > > So, which configuration would be the one to use for accelerated rendering on > > i915 without X11? > > dri does not imply X11 in this case. You should be able to run i915/drm on a > X-less system. The latest configuration I tried was this one: ./configure --enable-gles2 --disable-glx --with-dri-drivers= --enable-gallium-egl --with-egl-platforms=drm --with-gallium-drivers=i915 but it depends on X11 headers: -- Making all in pipe-loader make[3]: Entering directory `/home/christian/projects/mesa/mesa/src/gallium/auxiliary/pipe-loader' CC libpipe_loader_la-pipe_loader.lo CC libpipe_loader_la-pipe_loader_sw.lo In file included from pipe_loader_sw.c:34:0: ../../../../src/gallium/include/state_tracker/xlib_sw_winsys.h:5:22: fatal error: X11/Xlib.h: No such file or directory -- Since I'm planning to derive the source files needed for the port from the make output, ideally there shouldn't appear any files which depend on anything X11-related. But in case there is no configuration which matches this constraint, I could also try to filter these files out later or try add such a configuration if this could be useful for others, too. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Avoid dependency hints on math opcodes
Ian,
Here is a shader_test version. It lacks the sparkling uncertainty of the
pixel values in the previous animated example program.
It just gets all vertices uniformly wrong when I run it.
On Thu, Feb 20, 2014 at 4:31 PM, Ian Romanick wrote:
> On 02/12/2014 04:24 PM, m...@lunarg.com wrote:
> > From: Mike Stroyan
> >
> > Putting NoDDClr and NoDDChk dependency control on instruction
> > sequences that include math opcodes can cause corruption of channels.
> > Treat math opcodes like send opcodes and suppress dependency hinting.
>
> Since you've analyised the failure in the real application, can you
> produce a minimal shader_runner test case that exhibits the same
> problem? Eric mentioned to me that he'd like to play with it to better
> understand what's going on...
>
> > Signed-off-by: Mike Stroyan
> > Tested-by: Tony Bertapelli
> > ---
> > src/mesa/drivers/dri/i965/brw_vec4.cpp | 8
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> > index dd23ed4..1c42ca8 100644
> > --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> > @@ -717,6 +717,14 @@ vec4_visitor::opt_set_dependency_control()
> > continue;
> > }
> >
> > + /* Dependency control does not work well over math
> instructions.
> > + */
> > + if (inst->is_math()) {
> > +memset(last_grf_write, 0, sizeof(last_grf_write));
> > +memset(last_mrf_write, 0, sizeof(last_mrf_write));
> > +continue;
> > + }
> > +
> > /* Now, see if we can do dependency control for this
> instruction
> >* against a previous one writing to its destination.
> >*/
> >
>
>
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LunarG, Inc. - The Graphics Experts
Cell: (970) 219-7905
Email: m...@lunarg.com
Website: http://www.lunarg.com
glsl-vs-math-dependency.shader_test
Description: Binary data
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[Mesa-dev] [Bug 75286] make error with Gallium i915/DRM configuration
https://bugs.freedesktop.org/show_bug.cgi?id=75286 --- Comment #7 from Emil Velikov --- (In reply to comment #5) [snip] > I ship i915g on Chrome OS, so it is maintained. I don't encounter many > issues with it, though, so there's not many commits. As for i915 + sw > winsys, probably no one uses it. Maybe we should ask on the list. AFAICS you are the primary developer of i915 so it's only fair that you give the good news :-) (In reply to comment #6) > > (In reply to comment #3) [snip] > > dri does not imply X11 in this case. You should be able to run i915/drm on a > > X-less system. > > The latest configuration I tried was this one: > > ./configure --enable-gles2 --disable-glx --with-dri-drivers= > --enable-gallium-egl --with-egl-platforms=drm --with-gallium-drivers=i915 > > but it depends on X11 headers: > > -- > Making all in pipe-loader > make[3]: Entering directory > `/home/christian/projects/mesa/mesa/src/gallium/auxiliary/pipe-loader' > CC libpipe_loader_la-pipe_loader.lo > CC libpipe_loader_la-pipe_loader_sw.lo > In file included from pipe_loader_sw.c:34:0: > ../../../../src/gallium/include/state_tracker/xlib_sw_winsys.h:5:22: fatal > error: X11/Xlib.h: No such file or directory > -- > > Since I'm planning to derive the source files needed for the port from the > make output, ideally there shouldn't appear any files which depend on > anything X11-related. But in case there is no configuration which matches > this constraint, I could also try to filter these files out later or try add > such a configuration if this could be useful for others, too. For compilation purposes you will need the headers but as far as runtime is concerned you should be fine. Here is a snippet from nouveau_dri.so $ ldd /usr/lib/xorg/modules/dri/nouveau_dri.so linux-vdso.so.1 (0x7fffb430a000) libexpat.so.1 => /usr/lib/libexpat.so.1 (0x7faaa5096000) libpthread.so.0 => /usr/lib/libpthread.so.0 (0x7faaa4e79000) libdl.so.2 => /usr/lib/libdl.so.2 (0x7faaa4c75000) libdrm_nouveau.so.2 => /usr/lib/libdrm_nouveau.so.2 (0x7faaa4a6d000) libdrm.so.2 => /usr/lib/libdrm.so.2 (0x7faaa4861000) libstdc++.so.6 => /usr/lib/libstdc++.so.6 (0x7faaa455d000) libm.so.6 => /usr/lib/libm.so.6 (0x7faaa425b000) libc.so.6 => /usr/lib/libc.so.6 (0x7faaa3eb3000) libgcc_s.so.1 => /usr/lib/libgcc_s.so.1 (0x7faaa3c9d000) /usr/lib64/ld-linux-x86-64.so.2 (0x7faaa5c74000) -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] dri3: Enable GLX_MESA_query_renderer on DRI3 too
On 20/02/14 19:47, Ian Romanick wrote:
> From: Ian Romanick
>
> This should have happend around the time of commit 4680d23, but Keith's
> DRI3 patches and my GLX_MESA_query_renderer patches crossed in the mail.
>
> I don't have a working DRI3 setup, so I haven't been able to actually
> verify this. I'm hoping that someone can piglit this for me on DRI3...
> It's also unfortunate the DRI2 and DRI3 can't share more code.
>
Hi Ian
I have some (tested) patches that add support for swrast, by ripping out
dri2_convert_glx_query_renderer_attribs to dri_common.c and managing it
from there. IMHO it seems a bit more appropriate place considering the
naming scheme of files/functions in the glx folder.
AFAICS your patches will work like a charm but I'm a bit short on a dri3
setup.
I will send out the lovely (20+) series tomorrow.
- Emil
> Signed-off-by: Ian Romanick
> Cc: Keith Packard
> Cc: "10.1"
> ---
> src/glx/dri2.h| 8
> src/glx/dri2_query_renderer.c | 39 +++
> src/glx/dri3_glx.c| 10 +-
> src/glx/dri3_priv.h | 1 +
> 4 files changed, 57 insertions(+), 1 deletion(-)
>
> diff --git a/src/glx/dri2.h b/src/glx/dri2.h
> index 90efde8..7977d83 100644
> --- a/src/glx/dri2.h
> +++ b/src/glx/dri2.h
> @@ -95,4 +95,12 @@ _X_HIDDEN int
> dri2_query_renderer_string(struct glx_screen *base, int attribute,
> const char **value);
>
> +_X_HIDDEN int
> +dri3_query_renderer_integer(struct glx_screen *base, int attribute,
> +unsigned int *value);
> +
> +_X_HIDDEN int
> +dri3_query_renderer_string(struct glx_screen *base, int attribute,
> + const char **value);
> +
> #endif
> diff --git a/src/glx/dri2_query_renderer.c b/src/glx/dri2_query_renderer.c
> index b50a202..e13024c 100644
> --- a/src/glx/dri2_query_renderer.c
> +++ b/src/glx/dri2_query_renderer.c
> @@ -26,6 +26,7 @@
> #include "dri2.h"
> #include "dri_interface.h"
> #include "dri2_priv.h"
> +#include "dri3_priv.h"
>
> static int
> dri2_convert_glx_query_renderer_attribs(int attribute)
> @@ -95,3 +96,41 @@ dri2_query_renderer_string(struct glx_screen *base, int
> attribute,
>
> return psc->rendererQuery->queryString(psc->driScreen, dri_attribute,
> value);
> }
> +
> +_X_HIDDEN int
> +dri3_query_renderer_integer(struct glx_screen *base, int attribute,
> +unsigned int *value)
> +{
> + struct dri3_screen *const psc = (struct dri3_screen *) base;
> +
> + /* Even though there are invalid values (and
> +* dri2_convert_glx_query_renderer_attribs may return -1), the higher
> level
> +* GLX code is required to perform the filtering. Assume that we got a
> +* good value.
> +*/
> + const int dri_attribute =
> dri2_convert_glx_query_renderer_attribs(attribute);
> +
> + if (psc->rendererQuery == NULL)
> + return -1;
> +
> + return psc->rendererQuery->queryInteger(psc->driScreen, dri_attribute,
> + value);
> +}
> +
> +_X_HIDDEN int
> +dri3_query_renderer_string(struct glx_screen *base, int attribute,
> + const char **value)
> +{
> + struct dri3_screen *const psc = (struct dri3_screen *) base;
> +
> + /* Even though queryString only accepts a subset of the possible GLX
> +* queries, the higher level GLX code is required to perform the
> filtering.
> +* Assume that we got a good value.
> +*/
> + const int dri_attribute =
> dri2_convert_glx_query_renderer_attribs(attribute);
> +
> + if (psc->rendererQuery == NULL)
> + return -1;
> +
> + return psc->rendererQuery->queryString(psc->driScreen, dri_attribute,
> value);
> +}
> diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
> index 70ec057..3b7ee1e 100644
> --- a/src/glx/dri3_glx.c
> +++ b/src/glx/dri3_glx.c
> @@ -79,6 +79,7 @@
> #include "dri_common.h"
> #include "dri3_priv.h"
> #include "loader.h"
> +#include "dri2.h"
>
> static const struct glx_context_vtable dri3_context_vtable;
>
> @@ -1580,12 +1581,19 @@ dri3_bind_extensions(struct dri3_screen *psc, struct
> glx_display * priv,
>if (strcmp(extensions[i]->name, __DRI2_ROBUSTNESS) == 0)
> __glXEnableDirectExtension(&psc->base,
> "GLX_ARB_create_context_robustness");
> +
> + if (strcmp(extensions[i]->name, __DRI2_RENDERER_QUERY) == 0) {
> + psc->rendererQuery = (__DRI2rendererQueryExtension *) extensions[i];
> + __glXEnableDirectExtension(&psc->base, "GLX_MESA_query_renderer");
> + }
> }
> }
>
> static const struct glx_screen_vtable dri3_screen_vtable = {
> dri3_create_context,
> - dri3_create_context_attribs
> + dri3_create_context_attribs,
> + dri3_query_renderer_integer,
> + dri3_query_renderer_string,
> };
>
> /** dri3_create_screen
> diff --git a/src/glx/dri3_priv.h b/src/glx/dri3_priv.h
> index 1d124f8..334
Re: [Mesa-dev] [PATCH 4/8] radeonsi: Use util_cpu_to_le32() instead of bswap32() on big-endian systems
On Don, 2014-02-20 at 10:21 -0800, Tom Stellard wrote:
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c
> b/src/gallium/drivers/radeonsi/si_shader.c
> index 54270cd..9b04e6b 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -2335,7 +2335,7 @@ int si_compile_llvm(struct si_context *sctx, struct
> si_pipe_shader *shader,
> ptr = (uint32_t*)sctx->b.ws->buffer_map(shader->bo->cs_buf,
> sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
> if (0 /*SI_BIG_ENDIAN*/) {
> for (i = 0; i < binary.code_size / 4; ++i) {
> - ptr[i] = util_bswap32(*(uint32_t*)(binary.code + i*4));
> + ptr[i] = util_cpu_to_le32((*(uint32_t*)(binary.code +
> i*4)));
> }
> } else {
> memcpy(ptr, binary.code, binary.code_size);
We could get rid of the separate *_ENDIAN paths using util_cpu_to_le*().
Either way, the non-clover patches are
Reviewed-by: Michel Dänzer
--
Earthling Michel Dänzer| http://www.amd.com
Libre software enthusiast |Mesa and X developer
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[Mesa-dev] [Bug 75286] make error with Gallium i915/DRM configuration
https://bugs.freedesktop.org/show_bug.cgi?id=75286 --- Comment #8 from Christian Prochaska --- (In reply to comment #7) > For compilation purposes you will need the headers but as far as runtime is > concerned you should be fine. > Seems to be only a missing #ifdef HAVE_WINSYS_XLIB around the X11 header inclusion in pipe_loader_sw.c. With that, it builds for me. I'll test later this day. Thanks for the hints so far. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Avoid dependency hints on math opcodes
On Thu, Feb 20, 2014 at 4:55 PM, Mike Stroyan wrote:
> Ian,
>
> Here is a shader_test version. It lacks the sparkling uncertainty of the
> pixel values in the previous animated example program.
> It just gets all vertices uniformly wrong when I run it.
Thanks for the test Mike. I reproduced it locally.
Comparing the vertex shader assembly before and after your patch, I
get the attached diff.
The good news is that it doesn't look like the math instructions'
dependency control flags are broken. The bad news is that our
dependency control optimization has a bug. :)
After three math exp instructions write to g8.{x,y,z}, we mov.sat
g8.xyz into g116.xyz which we use as a message register. The problem
is that we wrote a 1.0 into g116.w before the exp instructions, and
the dependency control optimization code recognized that the write to
g116.xyz would stall waiting for the write to g116.w and marked the
instructions with NoDDClr/NoDDChk. Unfortunately, marking the write to
g116.xyz with NoDDChk means that the instruction doesn't wait on the
writes to g8 to complete either!
--- pass2014-02-20 18:45:43.227973145 -0800
+++ fail2014-02-20 18:46:07.915975294 -0800
@@ -252,16 +252,16 @@
(assign (xyz) (var_ref R_1) (swiz xyz (expression vec4 * (swiz
(var_ref conditional_tmp) )(expression vec4 neg (var_ref R_1) ) ) ))
0x0550: mul(8) g7<1>.xyzF g70<4,4,1>.xF -g7<4,4,1>F {
align16 WE_normal 1Q };
(assign (w) (var_ref gl_FrontColor) (constant float (1.00)) )
-0x0560: mov.sat(8) g116<1>.wF 1F {
align16 WE_normal 1Q };
+0x0560: mov.sat(8) g116<1>.wF 1F {
align16 WE_normal NoDDClr 1Q };
(assign (x) (var_ref R_2) (swiz x (expression vec4 exp2 (swiz
(var_ref R_1) )) ))
-0x0570: math exp(8) g8<1>.xFg7<4,4,1>.xFnull{
align16 WE_normal 1Q };
+0x0570: math exp(8) g8<1>.xFg7<4,4,1>.xFnull{
align16 WE_normal NoDDClr 1Q };
(assign (y) (var_ref R_2) (swiz y (expression vec4 exp2 (expression vec4
+ (swiz (var_ref R_1) )(constant float (0x1.5798eep-27)) ) ) ))
0x0580: add(8) g80<1>F g7<4,4,1>.yF1e-08F {
align16 WE_normal 1Q };
-0x0590: math exp(8) g8<1>.yFg80<4,4,1>F null{
align16 WE_normal 1Q };
+0x0590: math exp(8) g8<1>.yFg80<4,4,1>F null{
align16 WE_normal NoDDClr,NoDDChk 1Q };
(assign (z) (var_ref R_2) (swiz z (expression vec4 exp2 (swiz
(var_ref R_1) )) ))
-0x05a0: math exp(8) g8<1>.zFg7<4,4,1>.zFnull{
align16 WE_normal 1Q };
+0x05a0: math exp(8) g8<1>.zFg7<4,4,1>.zFnull{
align16 WE_normal NoDDChk 1Q };
(assign (xyz) (var_ref gl_FrontColor) (swiz xyz (var_ref R_2) ))
-0x05b0: mov.sat(8) g116<1>.xyzFg8<4,4,1>.xyzxF {
align16 WE_normal 1Q };
+0x05b0: mov.sat(8) g116<1>.xyzFg8<4,4,1>.xyzxF {
align16 WE_normal NoDDChk 1Q };
indices, point width, clip flags
0x05c0: mov(8) g114<1>D0D {
align16 WE_normal 1Q };
gl_Position
@@ -272,4 +272,7 @@
0x0600: send(8) nullg113<4,4,1>F
urb 0 urb_write used complete mlen 5 rlen 0 { align16
WE_normal 1Q EOT };
-PIGLIT: {'result': 'pass' }
+Probe color at (1,1)
+ Expected: 0.00 0.00 0.00
+ Observed: 0.00 0.00 1.00
+PIGLIT: {'result': 'fail' }
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Re: [Mesa-dev] [PATCH 4/8] radeonsi: Use util_cpu_to_le32() instead of bswap32() on big-endian systems
FWIW, memcpy() vs a for() loop has different semantics with respect to
address alignment. I don't know how much it will matter, but last time I
was reading assembly output, copying int[] via for() loop didn't produce a
codepath for 16-byte aligned addresses (allowing for SSE streaming) while
memcpy() has a lot of such logic. This won't matter much unless you have
lots to copy, and of course, compiler optimizations can change, so maybe
this situation has changed.
Patrick
On Thu, Feb 20, 2014 at 8:11 PM, Michel Dänzer wrote:
> On Don, 2014-02-20 at 10:21 -0800, Tom Stellard wrote:
> >
> > diff --git a/src/gallium/drivers/radeonsi/si_shader.c
> b/src/gallium/drivers/radeonsi/si_shader.c
> > index 54270cd..9b04e6b 100644
> > --- a/src/gallium/drivers/radeonsi/si_shader.c
> > +++ b/src/gallium/drivers/radeonsi/si_shader.c
> > @@ -2335,7 +2335,7 @@ int si_compile_llvm(struct si_context *sctx,
> struct si_pipe_shader *shader,
> > ptr = (uint32_t*)sctx->b.ws->buffer_map(shader->bo->cs_buf,
> sctx->b.rings.gfx.cs, PIPE_TRANSFER_WRITE);
> > if (0 /*SI_BIG_ENDIAN*/) {
> > for (i = 0; i < binary.code_size / 4; ++i) {
> > - ptr[i] = util_bswap32(*(uint32_t*)(binary.code +
> i*4));
> > + ptr[i] =
> util_cpu_to_le32((*(uint32_t*)(binary.code + i*4)));
> > }
> > } else {
> > memcpy(ptr, binary.code, binary.code_size);
>
> We could get rid of the separate *_ENDIAN paths using util_cpu_to_le*().
>
> Either way, the non-clover patches are
>
> Reviewed-by: Michel Dänzer
>
>
> --
> Earthling Michel Dänzer| http://www.amd.com
> Libre software enthusiast |Mesa and X developer
>
> ___
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>
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Re: [Mesa-dev] [PATCH 1/8] configure.ac: Use AX_GCC_BUILTIN to check availability of __builtin_bswap32
On Thu, Feb 20, 2014 at 10:21 AM, Tom Stellard wrote:
> ---
> configure.ac| 6 ++
> m4/ax_gcc_builtin.m4| 168
>
> src/gallium/auxiliary/util/u_math.h | 3 +-
> 3 files changed, 176 insertions(+), 1 deletion(-)
> create mode 100644 m4/ax_gcc_builtin.m4
>
> diff --git a/configure.ac b/configure.ac
> index 8390d27..75d345a 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -119,6 +119,12 @@ if test "x$GCC" = xyes -a "x$acv_mesa_CLANG" = xno; then
> GEN_ASM_OFFSETS=yes
> fi
> fi
> +
> +dnl Check for compiler builtins
> +AX_GCC_BUILTIN([__builtin_bswap32])
> +
> +AC_SUBST(HAVE___BUILTIN_BSWAP32)
> +
> AM_CONDITIONAL([GEN_ASM_OFFSETS], test "x$GEN_ASM_OFFSETS" = xyes)
>
> dnl Make sure the pkg-config macros are defined
> diff --git a/src/gallium/auxiliary/util/u_math.h
> b/src/gallium/auxiliary/util/u_math.h
> index b5e0663..b0f0e3d 100644
> --- a/src/gallium/auxiliary/util/u_math.h
> +++ b/src/gallium/auxiliary/util/u_math.h
> @@ -731,7 +731,8 @@ util_bitcount(unsigned n)
> static INLINE uint32_t
> util_bswap32(uint32_t n)
> {
> -#if defined(PIPE_CC_GCC) && (PIPE_CC_GCC_VERSION >= 403)
> +/* We need the gcc version checks for non-autoconf build system */
> +#if defined(HAVE___BUILTIN_BSWAP32) || (defined(PIPE_CC_GCC) &&
> (PIPE_CC_GCC_VERSION >= 403))
> return __builtin_bswap32(n);
> #else
> return (n >> 24) |
I don't think this will work. AC_SUBST substitutes into the files
listed in AC_OUTPUT. I think what you want is to add something to
DEFINES. But I don't know what the point is of this patch, since the
existing preprocessor check should be sufficient?
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[Mesa-dev] [PATCH] nouveau: add a nouveau_compiler binary to compile TGSI into shader ISA
This makes it easy to compare output between different cards, especially
for ones that you don't have (and/or not in the current machine).
Signed-off-by: Ilia Mirkin
---
This currently only works for nv50+, but it'd probably be possible to split
the code paths and introduce nv30/40 support.
src/gallium/drivers/nouveau/.gitignore | 1 +
src/gallium/drivers/nouveau/Makefile.am| 12 +++
src/gallium/drivers/nouveau/nouveau_compiler.c | 133 +
3 files changed, 146 insertions(+)
create mode 100644 src/gallium/drivers/nouveau/.gitignore
create mode 100644 src/gallium/drivers/nouveau/nouveau_compiler.c
diff --git a/src/gallium/drivers/nouveau/.gitignore
b/src/gallium/drivers/nouveau/.gitignore
new file mode 100644
index 000..829f951
--- /dev/null
+++ b/src/gallium/drivers/nouveau/.gitignore
@@ -0,0 +1 @@
+nouveau_compiler
diff --git a/src/gallium/drivers/nouveau/Makefile.am
b/src/gallium/drivers/nouveau/Makefile.am
index 7c05223..ac4f9bb 100644
--- a/src/gallium/drivers/nouveau/Makefile.am
+++ b/src/gallium/drivers/nouveau/Makefile.am
@@ -39,3 +39,15 @@ libnouveau_la_SOURCES = \
$(NV50_C_SOURCES) \
$(NVC0_CODEGEN_SOURCES) \
$(NVC0_C_SOURCES)
+
+noinst_PROGRAMS = nouveau_compiler
+
+nouveau_compiler_SOURCES = \
+ nouveau_compiler.c
+
+nouveau_compiler_LDADD = \
+ libnouveau.la \
+ ../../auxiliary/libgallium.la \
+ -lstdc++ \
+ -lm \
+ -ldl
diff --git a/src/gallium/drivers/nouveau/nouveau_compiler.c
b/src/gallium/drivers/nouveau/nouveau_compiler.c
new file mode 100644
index 000..01d6b14
--- /dev/null
+++ b/src/gallium/drivers/nouveau/nouveau_compiler.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2014 Ilia Mirkin
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include
+
+#include "tgsi/tgsi_text.h"
+#include "util/u_debug.h"
+
+#include "codegen/nv50_ir_driver.h"
+#include "nv50/nv50_context.h"
+
+static int
+dummy_assign_slots(struct nv50_ir_prog_info *info)
+{
+ return 0;
+}
+
+int
+main(int argc, char *argv[])
+{
+ struct tgsi_token tokens[1024];
+ struct nv50_ir_prog_info info = {0};
+ int i, chipset = 0, type = -1;
+ const char *filename = NULL;
+ FILE *f;
+ char text[65536] = {0};
+
+ for (i = 1; i < argc; i++) {
+ if (!strcmp(argv[i], "-a"))
+ chipset = strtol(argv[++i], NULL, 16);
+ else
+ filename = argv[i];
+ }
+
+ if (!chipset) {
+ _debug_printf("Must specify a chipset (-a)\n");
+ return 1;
+ }
+
+ if (!filename) {
+ _debug_printf("Must specify a filename\n");
+ return 1;
+ }
+
+ if (!strcmp(filename, "-"))
+ f = stdin;
+ else
+ f = fopen(filename, "r");
+
+ if (f == NULL) {
+ _debug_printf("Error opening file '%s': %s\n", filename,
strerror(errno));
+ return 1;
+ }
+
+ fread(text, 1, sizeof(text), f);
+ if (ferror(f)) {
+ _debug_printf("Error reading file '%s'\n", filename);
+ return 1;
+ }
+ fclose(f);
+
+ _debug_printf("Compiling for NV%X\n", chipset);
+
+ if (!strncmp(text, "FRAG", 4))
+ type = PIPE_SHADER_FRAGMENT;
+ else if (!strncmp(text, "VERT", 4))
+ type = PIPE_SHADER_VERTEX;
+ else if (!strncmp(text, "GEOM", 4))
+ type = PIPE_SHADER_GEOMETRY;
+ else if (!strncmp(text, "COMP", 4))
+ type = PIPE_SHADER_COMPUTE;
+ else {
+ _debug_printf("Unrecognized TGSI header\n");
+ return 1;
+ }
+
+ if (!tgsi_text_translate(text, tokens, Elements(tokens)))
+ return 1;
+
+ info.type = type;
+ info.target = chipset;
+ info.bin.sourceRep = NV50_PROGRAM_IR_TGSI;
+ info.bin.source = tokens;
+
+ info.io.ucpCBSlot = 15;
+ info.io.ucpBase = NV50_CB_AUX_UCP_OFFSET;
+
+ info.io.resInfoCBSlot = 15;
+ info.io.suInfoBase = NV50_CB_AUX_TEX_MS_OFFSET;
+ info.io.msInfoCBSlot = 15;
+ info.io.msInfoBase = NV50_CB_AUX_MS_OFFSET;
+
+ info.assignSlots = dummy_assign_slots;
+
+ info.optLevel = d
[Mesa-dev] [PATCH 3/4] nv30: remove unused sprite flipping parameter
Signed-off-by: Ilia Mirkin
---
I assume this is some left-over from nvfx -> nv30? That flag certainly doesn't
do anything now...
src/gallium/drivers/nouveau/nv30/nv30_context.h | 3 +--
src/gallium/drivers/nouveau/nv30/nv30_fragprog.c | 2 +-
src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c | 3 +--
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.h
b/src/gallium/drivers/nouveau/nv30/nv30_context.h
index 864d97a..6dfab38 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_context.h
+++ b/src/gallium/drivers/nouveau/nv30/nv30_context.h
@@ -214,8 +214,7 @@ nv30_state_release(struct nv30_context *nv30);
//XXX: needed to make it build, clean this up!
void
-_nvfx_fragprog_translate(struct nv30_context *nvfx, struct nv30_fragprog *fp,
- boolean emulate_sprite_flipping);
+_nvfx_fragprog_translate(struct nv30_context *nvfx, struct nv30_fragprog *fp);
boolean
_nvfx_vertprog_translate(struct nv30_context *nv30, struct nv30_vertprog *vp);
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c
b/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c
index e8acdfe..3551645 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c
@@ -67,7 +67,7 @@ nv30_fragprog_validate(struct nv30_context *nv30)
int i;
if (!fp->translated) {
- _nvfx_fragprog_translate(nv30, fp, FALSE);
+ _nvfx_fragprog_translate(nv30, fp);
if (!fp->translated)
return;
diff --git a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
index ae4f789..bee23eb 100644
--- a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
+++ b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
@@ -1114,8 +1114,7 @@ out_err:
DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", FALSE)
void
-_nvfx_fragprog_translate(struct nv30_context *nvfx, struct nv30_fragprog *fp,
- boolean emulate_sprite_flipping)
+_nvfx_fragprog_translate(struct nv30_context *nvfx, struct nv30_fragprog *fp)
{
struct tgsi_parse_context parse;
struct nvfx_fpc *fpc = NULL;
--
1.8.3.2
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[Mesa-dev] [PATCH 1/4] nv30: remove use_nv4x, it is identical to is_nv4x
Signed-off-by: Ilia Mirkin
---
Perhaps there was a day when those were different, but that day is not today.
src/gallium/drivers/nouveau/nv30/nv30_context.c | 1 -
src/gallium/drivers/nouveau/nv30/nv30_context.h | 1 -
src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c | 20 ++--
src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c | 8
4 files changed, 14 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.c
b/src/gallium/drivers/nouveau/nv30/nv30_context.c
index 2146d27..4f68eee 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_context.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_context.c
@@ -235,7 +235,6 @@ nv30_context_create(struct pipe_screen *pscreen, void *priv)
/*XXX: nvfx... */
nv30->is_nv4x = (screen->eng3d->oclass >= NV40_3D_CLASS) ? ~0 : 0;
- nv30->use_nv4x = (screen->eng3d->oclass >= NV40_3D_CLASS) ? ~0 : 0;
nv30->render_mode = HW;
nv30->sample_mask = 0x;
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.h
b/src/gallium/drivers/nouveau/nv30/nv30_context.h
index 527614a..d0cb5f5 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_context.h
+++ b/src/gallium/drivers/nouveau/nv30/nv30_context.h
@@ -121,7 +121,6 @@ struct nv30_context {
/*XXX: nvfx state, DO NOT USE EVER OUTSIDE "STOLEN" NVFX code */
unsigned is_nv4x;
- unsigned use_nv4x;
bool hw_pointsprite_control;
enum {
HW,
diff --git a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
index 4751ec8..ae4f789 100644
--- a/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
+++ b/src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c
@@ -807,7 +807,7 @@ nvfx_fragprog_parse_instruction(struct nv30_context* nvfx,
struct nvfx_fpc *fpc,
case TGSI_OPCODE_IF:
// MOVRC0 R31 (TR0.xyzw), R:
// IF (NE.) ELSE END
- if(!nvfx->use_nv4x)
+ if(!nvfx->is_nv4x)
goto nv3x_cflow;
nv40_fp_if(fpc, src[0]);
break;
@@ -815,7 +815,7 @@ nvfx_fragprog_parse_instruction(struct nv30_context* nvfx,
struct nvfx_fpc *fpc,
case TGSI_OPCODE_ELSE:
{
uint32_t *hw;
- if(!nvfx->use_nv4x)
+ if(!nvfx->is_nv4x)
goto nv3x_cflow;
assert(util_dynarray_contains(&fpc->if_stack, unsigned));
hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
@@ -826,7 +826,7 @@ nvfx_fragprog_parse_instruction(struct nv30_context* nvfx,
struct nvfx_fpc *fpc,
case TGSI_OPCODE_ENDIF:
{
uint32_t *hw;
- if(!nvfx->use_nv4x)
+ if(!nvfx->is_nv4x)
goto nv3x_cflow;
assert(util_dynarray_contains(&fpc->if_stack, unsigned));
hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
@@ -849,19 +849,19 @@ nvfx_fragprog_parse_instruction(struct nv30_context*
nvfx, struct nvfx_fpc *fpc,
break;
case TGSI_OPCODE_CAL:
- if(!nvfx->use_nv4x)
+ if(!nvfx->is_nv4x)
goto nv3x_cflow;
nv40_fp_cal(fpc, finst->Label.Label);
break;
case TGSI_OPCODE_RET:
- if(!nvfx->use_nv4x)
+ if(!nvfx->is_nv4x)
goto nv3x_cflow;
nv40_fp_ret(fpc);
break;
case TGSI_OPCODE_BGNLOOP:
- if(!nvfx->use_nv4x)
+ if(!nvfx->is_nv4x)
goto nv3x_cflow;
/* TODO: we should support using two nested REPs to allow a > 255
iteration count */
nv40_fp_rep(fpc, 255, finst->Label.Label);
@@ -871,7 +871,7 @@ nvfx_fragprog_parse_instruction(struct nv30_context* nvfx,
struct nvfx_fpc *fpc,
break;
case TGSI_OPCODE_BRK:
- if(!nvfx->use_nv4x)
+ if(!nvfx->is_nv4x)
goto nv3x_cflow;
nv40_fp_brk(fpc);
break;
@@ -951,7 +951,7 @@ static boolean
nvfx_fragprog_assign_generic(struct nv30_context *nvfx, struct nvfx_fpc *fpc,
const struct tgsi_full_declaration *fdec)
{
- unsigned num_texcoords = nvfx->use_nv4x ? 10 : 8;
+ unsigned num_texcoords = nvfx->is_nv4x ? 10 : 8;
unsigned idx = fdec->Range.First;
unsigned hw;
@@ -1002,7 +1002,7 @@ nvfx_fragprog_parse_decl_output(struct nv30_context*
nvfx, struct nvfx_fpc *fpc,
case 2: hw = 3; break;
case 3: hw = 4; break;
}
- if(hw > ((nvfx->use_nv4x) ? 4 : 2)) {
+ if(hw > ((nvfx->is_nv4x) ? 4 : 2)) {
NOUVEAU_ERR("bad rcol index\n");
return FALSE;
}
@@ -1129,7 +1129,7 @@ _nvfx_fragprog_translate(struct nv30_context *nvfx,
struct nv30_fragprog *fp,
if (!fpc)
goto out_err;
- fpc->max_temps = nvfx->use_nv4x ? 48 : 32;
+ fpc->max_temps = nvfx->is_nv4x ? 48 : 32;
fpc->fp = fp;
fpc->num_regs = 2;
memset(fp->texcoord, 0xff, sizeof(fp->texcoord));
diff --git a/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c
b/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c
index 3ae51ef..7642c5e 100644
--- a/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c
+++ b/src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c
@@ -313,8
[Mesa-dev] [PATCH 2/4] nv30: remove unused render_mode and hw_pointsprite_control
Signed-off-by: Ilia Mirkin
---
Were these things that didn't get quite ported over from the old nvfx? If so,
does it matter? Are they things we need? Even if they are, they can be
implemented in a way that doesn't put that state into nv30_context.
src/gallium/drivers/nouveau/nv30/nv30_context.c | 1 -
src/gallium/drivers/nouveau/nv30/nv30_context.h | 10 +++---
2 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.c
b/src/gallium/drivers/nouveau/nv30/nv30_context.c
index 4f68eee..4a4538c 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_context.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_context.c
@@ -235,7 +235,6 @@ nv30_context_create(struct pipe_screen *pscreen, void *priv)
/*XXX: nvfx... */
nv30->is_nv4x = (screen->eng3d->oclass >= NV40_3D_CLASS) ? ~0 : 0;
- nv30->render_mode = HW;
nv30->sample_mask = 0x;
nv30_vbo_init(pipe);
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.h
b/src/gallium/drivers/nouveau/nv30/nv30_context.h
index d0cb5f5..864d97a 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_context.h
+++ b/src/gallium/drivers/nouveau/nv30/nv30_context.h
@@ -119,16 +119,12 @@ struct nv30_context {
struct nouveau_heap *blit_vp;
struct pipe_resource *blit_fp;
- /*XXX: nvfx state, DO NOT USE EVER OUTSIDE "STOLEN" NVFX code */
- unsigned is_nv4x;
- bool hw_pointsprite_control;
- enum {
- HW,
- } render_mode;
-
struct pipe_query *render_cond_query;
unsigned render_cond_mode;
boolean render_cond_cond;
+
+ /*XXX: nvfx state, DO NOT USE EVER OUTSIDE "STOLEN" NVFX code */
+ unsigned is_nv4x;
};
static INLINE struct nv30_context *
--
1.8.3.2
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[Mesa-dev] [PATCH 4/4] nv30: remove nv30_context use from nvfx_*prog
This should pave the way to being able to use the compiler without a
context. Also leads to cleaner code.
Signed-off-by: Ilia Mirkin
---
So... there was a bit of an oops on this patch, I realized that NOUVEAU_ERR
was supplied in silly places and decided to move it to a shared
nouveau_debug. Ideally this would have been a separate patch, but I did things
in the wrong order, and it's a pain to split it. Let me know if you _really_
want that, and I'll do it, but I'd rather not.
It's not really great that nvfx_*prog relies on nv30_*prog, but... wtvr. Not a
huge deal. This patch sets up nvfx to be plug-in-able into nouveau_compiler.
src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 2 +-
src/gallium/drivers/nouveau/nouveau_debug.h | 25 +
src/gallium/drivers/nouveau/nv30/nv30_context.c | 3 --
src/gallium/drivers/nouveau/nv30/nv30_context.h | 10
src/gallium/drivers/nouveau/nv30/nv30_fragprog.c | 2 +-
src/gallium/drivers/nouveau/nv30/nv30_screen.h | 4 +-
src/gallium/drivers/nouveau/nv30/nv30_vertprog.c | 3 +-
src/gallium/drivers/nouveau/nv30/nvfx_fragprog.c | 65 +---
src/gallium/drivers/nouveau/nv30/nvfx_shader.h | 12 -
src/gallium/drivers/nouveau/nv30/nvfx_vertprog.c | 62 +++---
src/gallium/drivers/nouveau/nv50/nv50_context.h | 2 +-
src/gallium/drivers/nouveau/nv50/nv50_debug.h| 25 -
src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 2 +-
13 files changed, 110 insertions(+), 107 deletions(-)
create mode 100644 src/gallium/drivers/nouveau/nouveau_debug.h
delete mode 100644 src/gallium/drivers/nouveau/nv50/nv50_debug.h
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
index 90fb51c..a24a66c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
@@ -25,8 +25,8 @@
#include "codegen/nv50_ir_driver.h"
extern "C" {
+#include "nouveau_debug.h"
#include "nv50/nv50_program.h"
-#include "nv50/nv50_debug.h"
}
namespace nv50_ir {
diff --git a/src/gallium/drivers/nouveau/nouveau_debug.h
b/src/gallium/drivers/nouveau/nouveau_debug.h
new file mode 100644
index 000..d17df81
--- /dev/null
+++ b/src/gallium/drivers/nouveau/nouveau_debug.h
@@ -0,0 +1,25 @@
+
+#ifndef __NOUVEAU_DEBUG_H__
+#define __NOUVEAU_DEBUG_H__
+
+#include
+
+#include "util/u_debug.h"
+
+#define NOUVEAU_DEBUG_MISC 0x0001
+#define NOUVEAU_DEBUG_SHADER 0x0100
+#define NOUVEAU_DEBUG_PROG_IR0x0200
+#define NOUVEAU_DEBUG_PROG_RA0x0400
+#define NOUVEAU_DEBUG_PROG_CFLOW 0x0800
+#define NOUVEAU_DEBUG_PROG_ALL 0x1f00
+
+#define NOUVEAU_DEBUG 0
+
+#define NOUVEAU_ERR(fmt, args...) \
+ fprintf(stderr, "%s:%d - "fmt, __FUNCTION__, __LINE__, ##args)
+
+#define NOUVEAU_DBG(ch, args...) \
+ if ((NOUVEAU_DEBUG) & (NOUVEAU_DEBUG_##ch))\
+ debug_printf(args)
+
+#endif /* __NOUVEAU_DEBUG_H__ */
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.c
b/src/gallium/drivers/nouveau/nv30/nv30_context.c
index 4a4538c..f325c5c 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_context.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_context.c
@@ -233,9 +233,6 @@ nv30_context_create(struct pipe_screen *pscreen, void *priv)
if (debug_get_bool_option("NV30_SWTNL", FALSE))
nv30->draw_flags |= NV30_NEW_SWTNL;
- /*XXX: nvfx... */
- nv30->is_nv4x = (screen->eng3d->oclass >= NV40_3D_CLASS) ? ~0 : 0;
-
nv30->sample_mask = 0x;
nv30_vbo_init(pipe);
nv30_query_init(pipe);
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_context.h
b/src/gallium/drivers/nouveau/nv30/nv30_context.h
index 6dfab38..7b32aae 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_context.h
+++ b/src/gallium/drivers/nouveau/nv30/nv30_context.h
@@ -122,9 +122,6 @@ struct nv30_context {
struct pipe_query *render_cond_query;
unsigned render_cond_mode;
boolean render_cond_cond;
-
- /*XXX: nvfx state, DO NOT USE EVER OUTSIDE "STOLEN" NVFX code */
- unsigned is_nv4x;
};
static INLINE struct nv30_context *
@@ -212,13 +209,6 @@ nv30_state_validate(struct nv30_context *nv30, boolean
hwtnl);
void
nv30_state_release(struct nv30_context *nv30);
-//XXX: needed to make it build, clean this up!
-void
-_nvfx_fragprog_translate(struct nv30_context *nvfx, struct nv30_fragprog *fp);
-
-boolean
-_nvfx_vertprog_translate(struct nv30_context *nv30, struct nv30_vertprog *vp);
-
#ifdef NV30_3D_VERTEX_BEGIN_END
#define NV30_PRIM_GL_CASE(n) \
case PIPE_PRIM_##n: return NV30_3D_VERTEX_BEGIN_END_##n
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c
b/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c
index 3551645..a05bfe1 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_fragprog.c
@@ -67,7 +67,7 @@ nv30_fragprog_validate(struct nv30_context *nv30)
int i;
if (!fp->translated) {
- _nvfx_fra
[Mesa-dev] [PATCH V2 00/22] ARB_texture_view support for i965
This series adds support for texture views on i965. I think it's fairly complete, but have probably still missed some things. It would be great if someone at Intel can run the relevant parts of oglconform against this. Big changes from V1: * Level/layer clamping behavior is fixed. [there were patches for this previously, but they have now been folded into the main series]. * Depth clears with a range of layers fixed. * The view's mesa_format is now tracked in intel_texture_object::_Format, rather than assuming the mt's format is always what we want. This fixes rendering tests which reinterpret the underlying texture with a different format. -- Chris ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH V2 03/22] i965: Include #slices in miptree debug
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index eca876b..e43c1ff 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -247,10 +247,10 @@ intel_miptree_create_layout(struct brw_context *brw,
if (!mt)
return NULL;
- DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__,
+ DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__,
_mesa_lookup_enum_by_nr(target),
_mesa_get_format_name(format),
- first_level, last_level, mt);
+ first_level, last_level, depth0, mt);
mt->target = target_to_target(target);
mt->format = format;
--
1.9.0
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[Mesa-dev] [PATCH V2 01/22] i965: Pretend we don't support BRW_SURFACEFORMAT_R16G16B16_FLOAT for textures.
None of the other 3-component 16bpc formats are directly supported, so
they get promoted to XRGB equivalents. *Not* promoting RGB16F the same
way makes texture views much more fiddly -- we don't want to have to do
crazy copying behind the scenes.
(with my other master + my experimental ARB_texture_view support) fixes
the piglit test: `spec/ARB_texture_view/view compare 48bit formats`
No regressions in gpu.tests on Haswell.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c
b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index b2c36d9..2432467 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -267,7 +267,7 @@ const struct surface_format_info surface_formats[] = {
SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R64G64B64_FLOAT)
SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC4_SNORM)
SF( Y, Y, x, x, x, x, x, x, x, BRW_SURFACEFORMAT_BC5_SNORM)
- SF(50, 50, x, x, x, x, 60, x, x, BRW_SURFACEFORMAT_R16G16B16_FLOAT)
+ SF( x, x, x, x, x, x, 60, x, x, BRW_SURFACEFORMAT_R16G16B16_FLOAT)
SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_UNORM)
SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SNORM)
SF( x, x, x, x, x, x, Y, x, x, BRW_SURFACEFORMAT_R16G16B16_SSCALED)
--
1.9.0
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[Mesa-dev] [PATCH V2 02/22] mesa: Adjust _MaxLevel computation to account for views
Signed-off-by: Chris Forbes
---
src/mesa/main/texobj.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index 6adc0ae..67c362d 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -557,6 +557,13 @@ _mesa_test_texobj_completeness( const struct gl_context
*ctx,
/* 'q' in the GL spec */
maxLevels - 1);
+ if (t->Immutable) {
+ /* Adjust max level for views: the data store may have more levels than
+ * the view exposes.
+ */
+ t->_MaxLevel = MIN2(t->_MaxLevel, t->NumLevels - 1);
+ }
+
/* Compute _MaxLambda = q - p in the spec used during mipmapping */
t->_MaxLambda = (GLfloat) (t->_MaxLevel - baseLevel);
--
1.9.0
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[Mesa-dev] [PATCH V2 05/22] i965: refactor format selection for unsupported ETC* formats
We will need to call this to munge view formats.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 76 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++
2 files changed, 45 insertions(+), 34 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d0cbbad..611ce5b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -512,6 +512,47 @@ intel_miptree_choose_tiling(struct brw_context *brw,
return I915_TILING_Y | I915_TILING_X;
}
+
+/**
+ * Choose an appropriate uncompressed format for a requested
+ * compressed format, if unsupported.
+ */
+mesa_format
+intel_lower_compressed_format(struct brw_context *brw, mesa_format format)
+{
+ /* No need to lower ETC formats on these platforms,
+* they are supported natively.
+*/
+ if (brw->gen >= 8 || brw->is_baytrail)
+ return format;
+
+ switch (format) {
+ case MESA_FORMAT_ETC1_RGB8:
+ return MESA_FORMAT_R8G8B8X8_UNORM;
+ case MESA_FORMAT_ETC2_RGB8:
+ return MESA_FORMAT_R8G8B8X8_UNORM;
+ case MESA_FORMAT_ETC2_SRGB8:
+ case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC:
+ case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1:
+ return MESA_FORMAT_B8G8R8A8_SRGB;
+ case MESA_FORMAT_ETC2_RGBA8_EAC:
+ case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1:
+ return MESA_FORMAT_R8G8B8A8_UNORM;
+ case MESA_FORMAT_ETC2_R11_EAC:
+ return MESA_FORMAT_R_UNORM16;
+ case MESA_FORMAT_ETC2_SIGNED_R11_EAC:
+ return MESA_FORMAT_R_SNORM16;
+ case MESA_FORMAT_ETC2_RG11_EAC:
+ return MESA_FORMAT_R16G16_UNORM;
+ case MESA_FORMAT_ETC2_SIGNED_RG11_EAC:
+ return MESA_FORMAT_R16G16_SNORM;
+ default:
+ /* Non ETC1 / ETC2 format */
+ return format;
+ }
+}
+
+
struct intel_mipmap_tree *
intel_miptree_create(struct brw_context *brw,
GLenum target,
@@ -530,40 +571,7 @@ intel_miptree_create(struct brw_context *brw,
mesa_format etc_format = MESA_FORMAT_NONE;
GLuint total_width, total_height;
- if (brw->gen < 8 && !brw->is_baytrail) {
- switch (format) {
- case MESA_FORMAT_ETC1_RGB8:
- format = MESA_FORMAT_R8G8B8X8_UNORM;
- break;
- case MESA_FORMAT_ETC2_RGB8:
- format = MESA_FORMAT_R8G8B8X8_UNORM;
- break;
- case MESA_FORMAT_ETC2_SRGB8:
- case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC:
- case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1:
- format = MESA_FORMAT_B8G8R8A8_SRGB;
- break;
- case MESA_FORMAT_ETC2_RGBA8_EAC:
- case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1:
- format = MESA_FORMAT_R8G8B8A8_UNORM;
- break;
- case MESA_FORMAT_ETC2_R11_EAC:
- format = MESA_FORMAT_R_UNORM16;
- break;
- case MESA_FORMAT_ETC2_SIGNED_R11_EAC:
- format = MESA_FORMAT_R_SNORM16;
- break;
- case MESA_FORMAT_ETC2_RG11_EAC:
- format = MESA_FORMAT_R16G16_UNORM;
- break;
- case MESA_FORMAT_ETC2_SIGNED_RG11_EAC:
- format = MESA_FORMAT_R16G16_SNORM;
- break;
- default:
- /* Non ETC1 / ETC2 format */
- break;
- }
- }
+ format = intel_lower_compressed_format(brw, format);
etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 2ed1941..e9ee11b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -501,6 +501,9 @@ intel_miptree_create_for_renderbuffer(struct brw_context
*brw,
mesa_format
intel_depth_format_for_depthstencil_format(mesa_format format);
+mesa_format
+intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
+
/** \brief Assert that the level and layer are valid for the miptree. */
static inline void
intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
--
1.9.0
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[Mesa-dev] [PATCH V2 06/22] i965: Skip texture validation for immutable-format textures.
We're about to start sharing miptrees in texture views, and I'd rather
not teach this validation code about nonzero MinLevel or MinLayer when
views are guaranteed complete [and all levels resident in the base
miptree].
The only thing we have to do is set up our _MaxLevel derived state.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_tex_validate.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c
b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index d8497a6..c8e1afb 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -77,6 +77,14 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint
unit)
if (tObj->Target == GL_TEXTURE_BUFFER)
return true;
+ /* Immutable textures require no validation either -- we set up a correct
+* miptree for them at creation time.
+*/
+ if (tObj->Immutable) {
+ intel_update_max_level(intelObj, sampler);
+ return true;
+ }
+
/* We know that this is true by now, and if it wasn't, we might have
* mismatched level sizes and the copies would fail.
*/
--
1.9.0
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[Mesa-dev] [PATCH V2 04/22] i965: refactor format munging for separate stencil
We will need this for munging the view's format.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 31 ---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 +++
2 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e43c1ff..d0cbbad 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -227,6 +227,23 @@ intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw,
/**
+ * Determine depth format corresponding to a depth+stencil format,
+ * for separate stencil.
+ */
+mesa_format
+intel_depth_format_for_depthstencil_format(mesa_format format) {
+ switch (format) {
+ case MESA_FORMAT_Z24_UNORM_S8_UINT:
+ return MESA_FORMAT_Z24_UNORM_X8_UINT;
+ case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
+ return MESA_FORMAT_Z_FLOAT32;
+ default:
+ return format;
+ }
+}
+
+
+/**
* @param for_bo Indicates that the caller is
*intel_miptree_create_for_bo(). If true, then do not create
*\c stencil_mt.
@@ -384,14 +401,12 @@ intel_miptree_create_layout(struct brw_context *brw,
/* Fix up the Z miptree format for how we're splitting out separate
* stencil. Gen7 expects there to be no stencil bits in its depth
buffer.
*/
- if (mt->format == MESA_FORMAT_Z24_UNORM_S8_UINT) {
-mt->format = MESA_FORMAT_Z24_UNORM_X8_UINT;
- } else if (mt->format == MESA_FORMAT_Z32_FLOAT_S8X24_UINT) {
-mt->format = MESA_FORMAT_Z_FLOAT32;
-mt->cpp = 4;
- } else {
-_mesa_problem(NULL, "Unknown format %s in separate stencil mt\n",
- _mesa_get_format_name(mt->format));
+ mt->format = intel_depth_format_for_depthstencil_format(mt->format);
+ mt->cpp = 4;
+
+ if (format == mt->format) {
+ _mesa_problem(NULL, "Unknown format %s in separate stencil mt\n",
+ _mesa_get_format_name(mt->format));
}
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 6c45cfd..2ed1941 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -498,6 +498,9 @@ intel_miptree_create_for_renderbuffer(struct brw_context
*brw,
uint32_t height,
uint32_t num_samples);
+mesa_format
+intel_depth_format_for_depthstencil_format(mesa_format format);
+
/** \brief Assert that the level and layer are valid for the miptree. */
static inline void
intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
--
1.9.0
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[Mesa-dev] [PATCH V2 07/22] i965: Add driver hook for TextureView
We need to wire the original texture's mt into the view. All the hard
work of setting up an appropriate tree of gl_texture_image structures
has already been done by core mesa.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_tex.c | 41 +++
1 file changed, 41 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c
b/src/mesa/drivers/dri/i965/intel_tex.c
index 0e08aab..3b14796 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -237,6 +237,46 @@ intel_unmap_texture_image(struct gl_context *ctx,
intel_miptree_unmap(brw, mt, tex_image->Level, slice);
}
+static GLboolean
+intel_texture_view(struct gl_context *ctx,
+ struct gl_texture_object *texObj,
+ struct gl_texture_object *origTexObj)
+{
+ struct intel_texture_object *intel_tex = intel_texture_object(texObj);
+ struct intel_texture_object *intel_orig_tex =
intel_texture_object(origTexObj);
+
+ assert(intel_orig_tex->mt);
+ intel_miptree_reference(&intel_tex->mt, intel_orig_tex->mt);
+
+ /* Since we can only make views of immutable-format textures,
+* we can assume that everything is in origTexObj's miptree.
+*
+* Mesa core has already made us a copy of all the teximage objects,
+* except it hasn't copied our mt pointers, etc.
+*/
+ const int numFaces = _mesa_num_tex_faces(texObj->Target);
+ const int numLevels = texObj->NumLevels;
+
+ int face;
+ int level;
+
+ for (face = 0; face < numFaces; face++) {
+ for (level = 0; level < numLevels; level++) {
+ struct gl_texture_image *image = texObj->Image[face][level];
+ struct intel_texture_image *intel_image = intel_texture_image(image);
+
+ intel_miptree_reference(&intel_image->mt, intel_orig_tex->mt);
+ }
+ }
+
+ /* The miptree is in a validated state, so no need to check later. */
+ intel_tex->needs_validate = false;
+ intel_tex->validated_first_level = 0;
+ intel_tex->validated_last_level = numLevels - 1;
+
+ return GL_TRUE;
+}
+
void
intelInitTextureFuncs(struct dd_function_table *functions)
{
@@ -249,4 +289,5 @@ intelInitTextureFuncs(struct dd_function_table *functions)
functions->AllocTextureStorage = intel_alloc_texture_storage;
functions->MapTextureImage = intel_map_texture_image;
functions->UnmapTextureImage = intel_unmap_texture_image;
+ functions->TextureView = intel_texture_view;
}
--
1.9.0
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[Mesa-dev] [PATCH V2 09/22] i965: Adjust surface_state emission to account for view parameters
Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 17 - 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 154a0fd..ba7a538 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -288,7 +288,7 @@ gen7_update_texture_surface(struct gl_context *ctx, memset(surf, 0, 8 * 4); uint32_t tex_format = translate_tex_format(brw, - mt->format, + intelObj->_Format, sampler->sRGBDecode); if (for_gather && tex_format == BRW_SURFACEFORMAT_R32G32_FLOAT) @@ -310,6 +310,11 @@ gen7_update_texture_surface(struct gl_context *ctx, if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D) surf[0] |= GEN7_SURFACE_IS_ARRAY; + /* if this is a view with restricted NumLayers, then +* our effective depth is not just the miptree depth. */ + uint32_t effective_depth = (tObj->Immutable && tObj->Target != GL_TEXTURE_3D) + ? tObj->NumLayers : mt->logical_depth0; + if (mt->array_spacing_lod0) surf[0] |= GEN7_SURFACE_ARYSPC_LOD0; @@ -317,14 +322,16 @@ gen7_update_texture_surface(struct gl_context *ctx, surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) | SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT); - surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) | + surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) | ((intelObj->mt->region->pitch) - 1); - surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout); + surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) | + SET_FIELD(tObj->MinLayer, GEN7_SURFACE_MIN_ARRAY_ELEMENT); + + surf[4] |= (effective_depth - 1) << 7; surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) | - SET_FIELD(tObj->BaseLevel - mt->first_level, -GEN7_SURFACE_MIN_LOD) | + SET_FIELD(tObj->MinLevel + tObj->BaseLevel - mt->first_level, GEN7_SURFACE_MIN_LOD) | /* mip count */ (intelObj->_MaxLevel - tObj->BaseLevel)); -- 1.9.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH V2 08/22] i965: Add _Format to intel_texobj.
This is the actual mesa_format to use. In non-view cases this is always
the same as the mt's format.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_tex.c | 8
src/mesa/drivers/dri/i965/intel_tex_obj.h | 5 +
src/mesa/drivers/dri/i965/intel_tex_validate.c | 1 +
3 files changed, 14 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c
b/src/mesa/drivers/dri/i965/intel_tex.c
index 3b14796..0bbeeb7 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -168,6 +168,7 @@ intel_alloc_texture_storage(struct gl_context *ctx,
intel_texobj->needs_validate = false;
intel_texobj->validated_first_level = 0;
intel_texobj->validated_last_level = levels - 1;
+ intel_texobj->_Format = intel_texobj->mt->format;
return true;
}
@@ -242,6 +243,7 @@ intel_texture_view(struct gl_context *ctx,
struct gl_texture_object *texObj,
struct gl_texture_object *origTexObj)
{
+ struct brw_context *brw = brw_context(ctx);
struct intel_texture_object *intel_tex = intel_texture_object(texObj);
struct intel_texture_object *intel_orig_tex =
intel_texture_object(origTexObj);
@@ -274,6 +276,12 @@ intel_texture_view(struct gl_context *ctx,
intel_tex->validated_first_level = 0;
intel_tex->validated_last_level = numLevels - 1;
+ /* Set the validated texture format, with the same adjustments that
+* would have been applied to determine the underlying texture's
+* mt->format. */
+ intel_tex->_Format = intel_depth_format_for_depthstencil_format(
+ intel_lower_compressed_format(brw, texObj->Image[0][0]->TexFormat));
+
return GL_TRUE;
}
diff --git a/src/mesa/drivers/dri/i965/intel_tex_obj.h
b/src/mesa/drivers/dri/i965/intel_tex_obj.h
index 78a0990..8f20858 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_obj.h
+++ b/src/mesa/drivers/dri/i965/intel_tex_obj.h
@@ -54,6 +54,11 @@ struct intel_texture_object
* might not all be the mipmap tree above.
*/
bool needs_validate;
+
+ /* Mesa format for the validated texture object. For non-views this
+* will always be the same as mt->format. For views, it may differ
+* since the mt is shared across views with differing formats. */
+ mesa_format _Format;
};
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c
b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index c8e1afb..dbc8fd5 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -176,6 +176,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint
unit)
intelObj->validated_first_level = validate_first_level;
intelObj->validated_last_level = validate_last_level;
+ intelObj->_Format = intelObj->mt->format;
intelObj->needs_validate = false;
return true;
--
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[Mesa-dev] [PATCH V2 18/22] i965/blorp: Use irb->layer_count in clear
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 9159df5..039bc03 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -578,8 +578,7 @@ brw_blorp_clear_color(struct brw_context *brw, struct
gl_framebuffer *fb,
(irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
irb->mt->num_samples : 1;
- unsigned num_layers =
-irb->mt->level[irb->mt_level].depth / layer_multiplier;
+ unsigned num_layers = irb->layer_count;
for (unsigned layer = 0; layer < num_layers; layer++) {
if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear,
layer * layer_multiplier)) {
--
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[Mesa-dev] [PATCH V2 11/22] i965: Adjust map/unmap code for MinLevel/MinLayer
This allows core mesa's TexSubImage paths etc to work correctly with views which have nonzero MinLevel or MinLayer. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/intel_tex.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c index 0bbeeb7..825d4d3 100644 --- a/src/mesa/drivers/dri/i965/intel_tex.c +++ b/src/mesa/drivers/dri/i965/intel_tex.c @@ -220,8 +220,11 @@ intel_map_texture_image(struct gl_context *ctx, if (tex_image->TexObject->Target == GL_TEXTURE_CUBE_MAP) slice = tex_image->Face; - intel_miptree_map(brw, mt, tex_image->Level, slice, x, y, w, h, mode, -(void **)map, stride); + intel_miptree_map(brw, mt, + tex_image->Level + tex_image->TexObject->MinLevel, + slice + tex_image->TexObject->MinLayer, + x, y, w, h, mode, + (void **)map, stride); } static void @@ -235,7 +238,9 @@ intel_unmap_texture_image(struct gl_context *ctx, if (tex_image->TexObject->Target == GL_TEXTURE_CUBE_MAP) slice = tex_image->Face; - intel_miptree_unmap(brw, mt, tex_image->Level, slice); + intel_miptree_unmap(brw, mt, + tex_image->Level + tex_image->TexObject->MinLevel, + slice + tex_image->TexObject->MinLayer); } static GLboolean -- 1.9.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH V2 12/22] i965: Account for MinLevel in texture upload fast path
Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index 489b6ad..c2875dd 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c @@ -634,9 +634,11 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, packing->Alignment, packing->RowLength, packing->SkipPixels, packing->SkipRows, for_glTexImage); + int level = texImage->Level + texImage->TexObject->MinLevel; + /* Adjust x and y offset based on miplevel */ - xoffset += image->mt->level[texImage->Level].level_x; - yoffset += image->mt->level[texImage->Level].level_y; + xoffset += image->mt->level[level].level_x; + yoffset += image->mt->level[level].level_y; linear_to_tiled( xoffset * cpp, (xoffset + width) * cpp, -- 1.9.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH V2 10/22] i965: Don't try to use fast upload path for nontrivial views
This will eventually be relaxed, but we'll get the fallback path working first. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index 6942039..489b6ad 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c @@ -588,6 +588,10 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, if (!mem_copy) return false; + /* If this is a nontrivial texture view, let another path handle it instead. */ + if (texImage->TexObject->MinLevel || texImage->TexObject->MinLayer) + return false; + if (for_glTexImage) ctx->Driver.AllocTextureImageBuffer(ctx, texImage); -- 1.9.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH V2 20/22] i965: Account for view parameters in fast depth clears
V2: - No need for layer_multiplier; multisampled depth surfaces are IMS.
- Remove unused num_layers.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_clear.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index b2cea98..940173b 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -186,9 +186,9 @@ brw_fast_clear_depth(struct gl_context *ctx)
intel_batchbuffer_emit_mi_flush(brw);
if (fb->MaxNumLayers > 0) {
- unsigned num_layers = depth_irb->mt->level[depth_irb->mt_level].depth;
- for (unsigned layer = 0; layer < num_layers; layer++) {
- intel_hiz_exec(brw, mt, depth_irb->mt_level, layer,
+ for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
+ intel_hiz_exec(brw, mt, depth_irb->mt_level,
+depth_irb->mt_layer + layer,
GEN6_HIZ_OP_DEPTH_CLEAR);
}
} else {
--
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[Mesa-dev] [PATCH V2 22/22] docs: Mark off ARB_texture_view and add to release notes for 10.2.
Signed-off-by: Chris Forbes --- docs/GL3.txt| 2 +- docs/relnotes/10.2.html | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index 542ee28..f53e92a 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -162,7 +162,7 @@ GL 4.3: GL_ARB_texture_buffer_range DONE (nv50, nvc0, i965, r600, radeonsi) GL_ARB_texture_query_levels DONE (i965) GL_ARB_texture_storage_multisample DONE (all drivers that support GL_ARB_texture_multisample) - GL_ARB_texture_view started (Courtney Goeltzenleuchter, Chris Forbes) + GL_ARB_texture_view DONE (i965) GL_ARB_vertex_attrib_binding DONE (all drivers) diff --git a/docs/relnotes/10.2.html b/docs/relnotes/10.2.html index 332c33a..7928619 100644 --- a/docs/relnotes/10.2.html +++ b/docs/relnotes/10.2.html @@ -44,6 +44,7 @@ Note: some of the new features are only available with certain drivers. + ARB_texture_view on i965. -- 1.9.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH V2 15/22] i965: Add `layered` parameter to intel_update_renderbuffer_wrapper
We're about to need this so we can determine the layer count of the
wrapper.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_fbo.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index a2ed5d2..b0e7f80 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -499,8 +499,9 @@ intel_new_renderbuffer(struct gl_context * ctx, GLuint name)
static bool
intel_renderbuffer_update_wrapper(struct brw_context *brw,
struct intel_renderbuffer *irb,
- struct gl_texture_image *image,
- uint32_t layer)
+ struct gl_texture_image *image,
+ uint32_t layer,
+ bool layered)
{
struct gl_renderbuffer *rb = &irb->Base.Base;
struct intel_texture_image *intel_image = intel_texture_image(image);
@@ -592,7 +593,7 @@ intel_render_texture(struct gl_context * ctx,
intel_miptree_check_level_layer(mt, att->TextureLevel, layer);
- if (!intel_renderbuffer_update_wrapper(brw, irb, image, layer)) {
+ if (!intel_renderbuffer_update_wrapper(brw, irb, image, layer,
att->Layered)) {
_swrast_render_texture(ctx, fb, att);
return;
}
--
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[Mesa-dev] [PATCH V2 19/22] i965/blorp: Account for nonzero MinLayer in layered clears.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 039bc03..9e7252f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -581,7 +581,7 @@ brw_blorp_clear_color(struct brw_context *brw, struct
gl_framebuffer *fb,
unsigned num_layers = irb->layer_count;
for (unsigned layer = 0; layer < num_layers; layer++) {
if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear,
- layer * layer_multiplier)) {
+ irb->mt_layer + layer *
layer_multiplier)) {
return false;
}
}
--
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[Mesa-dev] [PATCH V2 17/22] i965: Add layer_count to intel_renderbuffer
This is the effective layer count, for clears etc. This differs from the
depth of the miptree level when views are involved.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_fbo.c | 10 ++
src/mesa/drivers/dri/i965/intel_fbo.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index efdffe1..cb37fea 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -317,6 +317,8 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx,
struct gl_renderbuffer
if (!irb->mt)
return false;
+ irb->layer_count = 1;
+
return true;
}
@@ -381,6 +383,7 @@ intel_image_target_renderbuffer_storage(struct gl_context
*ctx,
rb->Format = image->format;
rb->_BaseFormat = _mesa_base_fbo_format(ctx, image->internal_format);
rb->NeedsFinishRenderTexture = true;
+ irb->layer_count = 1;
}
/**
@@ -433,6 +436,7 @@ intel_create_renderbuffer(mesa_format format, unsigned
num_samples)
}
rb = &irb->Base.Base;
+ irb->layer_count = 1;
_mesa_init_renderbuffer(rb, 0);
rb->ClassID = INTEL_RB_CLASS;
@@ -530,6 +534,12 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
irb->mt_layer = layer_multiplier * layer;
+ if (layered) {
+ irb->layer_count = image->TexObject->NumLayers ?: mt->level[level].depth
/ layer_multiplier;
+ } else {
+ irb->layer_count = 1;
+ }
+
intel_miptree_reference(&irb->mt, mt);
intel_renderbuffer_set_draw_offset(irb);
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.h
b/src/mesa/drivers/dri/i965/intel_fbo.h
index b8db7e2..6c761e6 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.h
+++ b/src/mesa/drivers/dri/i965/intel_fbo.h
@@ -90,6 +90,9 @@ struct intel_renderbuffer
*/
unsigned int mt_level;
unsigned int mt_layer;
+
+ /* The number of attached logical layers. */
+ unsigned int layer_count;
/** \} */
GLuint draw_x, draw_y; /**< Offset of drawing within the region */
--
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[Mesa-dev] [PATCH V2 13/22] i965: Enable texture upload fast path with MinLevel
We'll still avoid MinLayer here since the fast path doesn't understand arrays at all, but it's straightforward to do levels. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index c2875dd..a15c588 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c @@ -589,7 +589,7 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, return false; /* If this is a nontrivial texture view, let another path handle it instead. */ - if (texImage->TexObject->MinLevel || texImage->TexObject->MinLayer) + if (texImage->TexObject->MinLayer) return false; if (for_glTexImage) -- 1.9.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH V2 14/22] i965: Adjust renderbuffer wrapper to account for MinLevel/MinLayer
Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/intel_fbo.c | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index d11cdb6..a2ed5d2 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -509,6 +509,10 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw, rb->AllocStorage = intel_nop_alloc_storage; + /* adjust for texture view parameters */ + layer += image->TexObject->MinLayer; + level += image->TexObject->MinLevel; + intel_miptree_check_level_layer(mt, level, layer); irb->mt_level = level; -- 1.9.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH V2 16/22] i965: Pull out layer_multiplier in intel_update_renderbuffer_wrapper
We're about to need this in another place.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_fbo.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index b0e7f80..efdffe1 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -517,16 +517,19 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
intel_miptree_check_level_layer(mt, level, layer);
irb->mt_level = level;
+ int layer_multiplier;
switch (mt->msaa_layout) {
case INTEL_MSAA_LAYOUT_UMS:
case INTEL_MSAA_LAYOUT_CMS:
- irb->mt_layer = layer * mt->num_samples;
+ layer_multiplier = mt->num_samples;
break;
default:
- irb->mt_layer = layer;
+ layer_multiplier = 1;
}
+ irb->mt_layer = layer_multiplier * layer;
+
intel_miptree_reference(&irb->mt, mt);
intel_renderbuffer_set_draw_offset(irb);
--
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[Mesa-dev] [PATCH V2 21/22] i965: Enable ARB_texture_view on Gen7+
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index ef9aa55..0bd1115 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -286,6 +286,7 @@ intelInitExtensions(struct gl_context *ctx)
if (brw->gen >= 7) {
ctx->Extensions.ARB_conservative_depth = true;
ctx->Extensions.AMD_vertex_shader_layer = true;
+ ctx->Extensions.ARB_texture_view = true;
if (can_do_pipelined_register_writes(brw)) {
ctx->Extensions.ARB_transform_feedback2 = true;
ctx->Extensions.ARB_transform_feedback3 = true;
--
1.9.0
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