[Mesa-dev] [PATCH 5/9] i965: Implement NIR intrinsics for loading VS system values.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 51
1 file changed, 51 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index c5ed55c..d700523 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -363,6 +363,30 @@ emit_system_values_block(nir_block *block, void
*void_visitor)
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
switch (intrin-intrinsic) {
+ case nir_intrinsic_load_vertex_id:
+ unreachable(should be lowered by lower_vertex_id().);
+
+ case nir_intrinsic_load_vertex_id_zero_base:
+ assert(v-stage == MESA_SHADER_VERTEX);
+ reg = v-nir_system_values[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE];
+ if (reg-file == BAD_FILE)
+*reg = *v-emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
+ break;
+
+ case nir_intrinsic_load_base_vertex:
+ assert(v-stage == MESA_SHADER_VERTEX);
+ reg = v-nir_system_values[SYSTEM_VALUE_BASE_VERTEX];
+ if (reg-file == BAD_FILE)
+*reg = *v-emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX);
+ break;
+
+ case nir_intrinsic_load_instance_id:
+ assert(v-stage == MESA_SHADER_VERTEX);
+ reg = v-nir_system_values[SYSTEM_VALUE_INSTANCE_ID];
+ if (reg-file == BAD_FILE)
+*reg = *v-emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID);
+ break;
+
case nir_intrinsic_load_sample_pos:
assert(v-stage == MESA_SHADER_FRAGMENT);
reg = v-nir_system_values[SYSTEM_VALUE_SAMPLE_POS];
@@ -1344,6 +1368,33 @@ fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr)
*emit_frontfacing_interpolation()));
break;
+ case nir_intrinsic_load_vertex_id:
+ unreachable(should be lowered by lower_vertex_id());
+
+ case nir_intrinsic_load_vertex_id_zero_base: {
+ fs_reg vertex_id = nir_system_values[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE];
+ assert(vertex_id.file != BAD_FILE);
+ dest.type = vertex_id.type;
+ emit(MOV(dest, vertex_id));
+ break;
+ }
+
+ case nir_intrinsic_load_base_vertex: {
+ fs_reg base_vertex = nir_system_values[SYSTEM_VALUE_BASE_VERTEX];
+ assert(base_vertex.file != BAD_FILE);
+ dest.type = base_vertex.type;
+ emit(MOV(dest, base_vertex));
+ break;
+ }
+
+ case nir_intrinsic_load_instance_id: {
+ fs_reg instance_id = nir_system_values[SYSTEM_VALUE_INSTANCE_ID];
+ assert(instance_id.file != BAD_FILE);
+ dest.type = instance_id.type;
+ emit(MOV(dest, instance_id));
+ break;
+ }
+
case nir_intrinsic_load_sample_mask_in: {
fs_reg sample_mask_in = nir_system_values[SYSTEM_VALUE_SAMPLE_MASK_IN];
assert(sample_mask_in.file != BAD_FILE);
--
2.2.1
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[Mesa-dev] [PATCH 4/9] nir: Add intrinsics for SYSTEM_VALUE_BASE_VERTEX and VERTEX_ID_ZERO_BASE
Ian and I added these around the time Connor was developing NIR. Now that both exist, we should make them work together! Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/glsl/nir/nir_intrinsics.h | 2 ++ src/glsl/nir/nir_lower_system_values.c | 6 ++ 2 files changed, 8 insertions(+) diff --git a/src/glsl/nir/nir_intrinsics.h b/src/glsl/nir/nir_intrinsics.h index 3bf102f..8e28765 100644 --- a/src/glsl/nir/nir_intrinsics.h +++ b/src/glsl/nir/nir_intrinsics.h @@ -95,6 +95,8 @@ ATOMIC(read, NIR_INTRINSIC_CAN_ELIMINATE) SYSTEM_VALUE(front_face, 1) SYSTEM_VALUE(vertex_id, 1) +SYSTEM_VALUE(vertex_id_zero_base, 1) +SYSTEM_VALUE(base_vertex, 1) SYSTEM_VALUE(instance_id, 1) SYSTEM_VALUE(sample_id, 1) SYSTEM_VALUE(sample_pos, 2) diff --git a/src/glsl/nir/nir_lower_system_values.c b/src/glsl/nir/nir_lower_system_values.c index 328d4f1..a6eec65 100644 --- a/src/glsl/nir/nir_lower_system_values.c +++ b/src/glsl/nir/nir_lower_system_values.c @@ -49,6 +49,12 @@ convert_instr(nir_intrinsic_instr *instr) case SYSTEM_VALUE_VERTEX_ID: op = nir_intrinsic_load_vertex_id; break; + case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE: + op = nir_intrinsic_load_vertex_id_zero_base; + break; + case SYSTEM_VALUE_BASE_VERTEX: + op = nir_intrinsic_load_base_vertex; + break; case SYSTEM_VALUE_INSTANCE_ID: op = nir_intrinsic_load_instance_id; break; -- 2.2.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/9] i965/nir: Lower to registers a bit later.
We can't safely call nir_optimize() with register present, since several passes called in the loop can't handle registers, and will fail asserts. Notably, nir_lower_vec_alus() and nir_opt_algebraic() really don't want registers. Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index fbdfc22..c5ed55c 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -108,9 +108,6 @@ fs_visitor::emit_nir_code() nir_lower_io(nir); nir_validate_shader(nir); - nir_lower_locals_to_regs(nir); - nir_validate_shader(nir); - nir_remove_dead_variables(nir); nir_validate_shader(nir); @@ -125,6 +122,9 @@ fs_visitor::emit_nir_code() nir_optimize(nir); + nir_lower_locals_to_regs(nir); + nir_validate_shader(nir); + nir_lower_to_source_mods(nir); nir_validate_shader(nir); nir_copy_prop(nir); -- 2.2.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 7/9] i965/fs: Handle VS inputs in the NIR backend.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 3baafc4..1734d03 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -199,11 +199,32 @@ fs_visitor::nir_setup_inputs(nir_shader *shader)
struct hash_entry *entry;
hash_table_foreach(shader-inputs, entry) {
nir_variable *var = (nir_variable *) entry-data;
+ enum brw_reg_type type = brw_type_for_base_type(var-type);
fs_reg input = offset(nir_inputs, var-data.driver_location);
fs_reg reg;
switch (stage) {
- case MESA_SHADER_VERTEX:
+ case MESA_SHADER_VERTEX: {
+ /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
+ * stored in nir_variable::location.
+ *
+ * However, NIR's load_input intrinsics use a different index - an
+ * offset into a single contiguous array containing all inputs.
+ * This index corresponds to the nir_variable::driver_location field.
+ *
+ * So, we need to copy from fs_reg(ATTR, var-location) to
+ * offset(nir_inputs, var-data.driver_location).
+ */
+ unsigned components = var-type-without_array()-components();
+ unsigned array_length = var-type-is_array() ? var-type-length : 1;
+ for (unsigned i = 0; i array_length; i++) {
+for (unsigned j = 0; j components; j++) {
+ emit(MOV(retype(offset(input, components * i + j), type),
+offset(fs_reg(ATTR, var-data.location + i, type),
j)));
+}
+ }
+ break;
+ }
case MESA_SHADER_GEOMETRY:
case MESA_SHADER_COMPUTE:
unreachable(fs_visitor not used for these stages yet.);
--
2.2.1
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Re: [Mesa-dev] [PATCH] meta: Plug memory leak in blit shader creation
On Friday, March 06, 2015 06:22:00 PM Ben Widawsky wrote:
It looks like this has existed since:
commit f5a477ab76b6e0b268387699cd2253a43db0dfae
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 11:54:08 2013 -0800
meta: Refactor shader generation code out of mipmap generation path
Valgrind was complaining on the piglit test:
fbo-generatemipmap-formats GL_ARB_texture_float -auto -fbo
Cc: Ian Romanick ian.d.roman...@intel.com
Cc: Brian Paul bri...@vmware.com
Cc: Eric Anholt e...@anholt.net
Reported-by: Mark Janes mark.a.ja...@intel.com (Jenkins)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/common/meta.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index fdc4cf1..2c1abe3 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -270,6 +270,7 @@ _mesa_meta_setup_blit_shader(struct gl_context *ctx,
if (shader-shader_prog != 0) {
_mesa_UseProgram(shader-shader_prog);
+ ralloc_free(mem_ctx);
return;
}
Hi Ben,
You're right - in the case where the shader already exists (due to us
hitting this path once before), we do create a ralloc context and fail
to free it. We don't actually need one, since we're not constructing
shader code.
I think it would be better to pull 'mem_ctx = ralloc_context(NULL)' out
of the variable declaration, and put it after this early return.
The early return is the common case, and it'd be nice to avoid
allocating and freeing pointless heap memory for no reason.
--Ken
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Re: [Mesa-dev] [PATCH] i965/fs: Implement SIMD16 dual source blending.
On Sat, 2015-03-07 at 13:35 -0800, Jason Ekstrand wrote: On Thu, Mar 5, 2015 at 9:39 PM, Jason Ekstrand ja...@jlekstrand.net wrote: This looks fine to me. I just kicked off a build on our test farm and, assuming that looks good (I'll send another e-mail in the morning if it does), Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com Jenkins results look god so feel free to apply the R-B above and push it. Don't worry about the shader-db number given that, as ken pointed out, shader-db is kind of useless for this. I wish we knew how many SIMD16 programs this gave us in practice, but short of doing lots of shader-db work, we can't know at the moment so don't worry about it. Ok, I will push now. Thanks for the review and the testing! Iago I ran shader-db on the change and I was kind of surprised to see that it doesn't really do anything. GAINED: shaders/dolphin/smg.1.shader_test FS SIMD16 total instructions in shared programs: 5769629 - 5769629 (0.00%) instructions in affected programs: 0 - 0 helped:0 HURT: 0 GAINED:1 LOST: 0 Perhaps shader-db doesn't account for some other GL state required for dual-source because I doubt only one shader uses it. Ken? --Jason On Thu, Mar 5, 2015 at 3:21 AM, Iago Toral Quiroga ito...@igalia.com wrote: From the SNB PRM, volume 4, part 1, page 193: The dual source render target messages only have SIMD8 forms due to maximum message length limitations. SIMD16 pixel shaders must send two of these messages to cover all of the pixels. Each message contains two colors (4 channels each) for each pixel in the message payload. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82831 --- I sent this patch for review some months ago, but it was bad timing because it was when Jason was doing a large rewrite of the visitor code handling FB writes, so the patch became immediately obsolete. This is the up-to-date version. If anyone wants to test this, I sent this patch to piglit with a test that can be used to check for correct SIMD16 implementation specifically: http://lists.freedesktop.org/archives/piglit/2015-March/015015.html src/mesa/drivers/dri/i965/brw_eu.h | 1 + src/mesa/drivers/dri/i965/brw_eu_emit.c| 3 +- src/mesa/drivers/dri/i965/brw_fs.h | 6 +- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 15 - src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 77 +- 5 files changed, 83 insertions(+), 19 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 736c54b..d9ad5bd 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -266,6 +266,7 @@ void brw_fb_WRITE(struct brw_compile *p, unsigned msg_length, unsigned response_length, bool eot, + bool last_render_target, bool header_present); void brw_SAMPLE(struct brw_compile *p, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 1d6fd67..74cf138 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -2292,6 +2292,7 @@ void brw_fb_WRITE(struct brw_compile *p, unsigned msg_length, unsigned response_length, bool eot, + bool last_render_target, bool
[Mesa-dev] [PATCH] Mesa: Add generated files to .gitignore
src/egl/main/.install-mesa-links src/glx/.install-mesa-links src/mapi/.install-mesa-links src/mesa/drivers/dri/i965/test_fs_cmod_propagation src/mesa/drivers/dri/i965/test_fs_saturate_propagation added to .gitignore files on their own directories Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com --- src/egl/main/.gitignore | 1 + src/glx/.gitignore | 1 + src/mapi/.gitignore | 1 + src/mesa/drivers/dri/i965/.gitignore | 2 ++ 4 files changed, 5 insertions(+) create mode 100644 src/egl/main/.gitignore diff --git a/src/egl/main/.gitignore b/src/egl/main/.gitignore new file mode 100644 index 000..145f53e --- /dev/null +++ b/src/egl/main/.gitignore @@ -0,0 +1 @@ +.install-mesa-links diff --git a/src/glx/.gitignore b/src/glx/.gitignore index 71ad785..c1cb62c 100644 --- a/src/glx/.gitignore +++ b/src/glx/.gitignore @@ -3,3 +3,4 @@ indirect.h indirect_init.c indirect_size.c indirect_size.h +.install-mesa-links diff --git a/src/mapi/.gitignore b/src/mapi/.gitignore index 0d280c9..f23a94b 100644 --- a/src/mapi/.gitignore +++ b/src/mapi/.gitignore @@ -1,2 +1,3 @@ shared-glapi-test glapi-test +.install-mesa-links diff --git a/src/mesa/drivers/dri/i965/.gitignore b/src/mesa/drivers/dri/i965/.gitignore index 8eb9f4e..2e375e4 100644 --- a/src/mesa/drivers/dri/i965/.gitignore +++ b/src/mesa/drivers/dri/i965/.gitignore @@ -3,3 +3,5 @@ test_eu_compact test_vec4_copy_propagation test_vec4_register_coalesce test_vf_float_conversions +test_fs_cmod_propagation +test_fs_saturate_propagation -- 1.8.5.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
