[Mesa-dev] [PATCH 08/11] freedreno: add support for state tracking shader buffers
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/freedreno/freedreno_context.h | 2 ++
src/gallium/drivers/freedreno/freedreno_draw.c | 8
src/gallium/drivers/freedreno/freedreno_resource.c | 8
src/gallium/drivers/freedreno/freedreno_state.c| 24 ++
4 files changed, 42 insertions(+)
diff --git a/src/gallium/drivers/freedreno/freedreno_context.h
b/src/gallium/drivers/freedreno/freedreno_context.h
index 61c4c6d..3a01f1f 100644
--- a/src/gallium/drivers/freedreno/freedreno_context.h
+++ b/src/gallium/drivers/freedreno/freedreno_context.h
@@ -336,6 +336,7 @@ struct fd_context {
FD_DIRTY_STREAMOUT = (1 << 18),
FD_DIRTY_UCP = (1 << 19),
FD_DIRTY_BLEND_DUAL = (1 << 20),
+ FD_DIRTY_BUFFERS = (1 << 21),
} dirty;
struct pipe_blend_state *blend;
@@ -358,6 +359,7 @@ struct fd_context {
struct pipe_index_buffer indexbuf;
struct fd_streamout_stateobj streamout;
struct pipe_clip_state ucp;
+ struct pipe_shader_buffer
buffers[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];
/* GMEM/tile handling fxns: */
void (*emit_tile_init)(struct fd_context *ctx);
diff --git a/src/gallium/drivers/freedreno/freedreno_draw.c
b/src/gallium/drivers/freedreno/freedreno_draw.c
index 6831a58..097c4f2 100644
--- a/src/gallium/drivers/freedreno/freedreno_draw.c
+++ b/src/gallium/drivers/freedreno/freedreno_draw.c
@@ -165,6 +165,14 @@ fd_draw_vbo(struct pipe_context *pctx, const struct
pipe_draw_info *info)
if (ctx->streamout.targets[i])
resource_written(ctx,
ctx->streamout.targets[i]->buffer);
+ /* Mark shader buffers as being read and written */
+ for (i = 0; i < PIPE_MAX_SHADER_BUFFERS; i++) {
+ resource_used(ctx, ctx->buffers[PIPE_SHADER_VERTEX][i].buffer,
+ FD_PENDING_READ | FD_PENDING_WRITE);
+ resource_used(ctx, ctx->buffers[PIPE_SHADER_FRAGMENT][i].buffer,
+ FD_PENDING_READ | FD_PENDING_WRITE);
+ }
+
ctx->num_draws++;
prims = u_reduced_prims_for_vertices(info->mode, info->count);
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c
b/src/gallium/drivers/freedreno/freedreno_resource.c
index 98de096..3b14575 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -68,6 +68,14 @@ fd_invalidate_resource(struct fd_context *ctx, struct
pipe_resource *prsc)
ctx->dirty |= FD_DIRTY_CONSTBUF;
}
+ /* Buffers */
+ for (i = 0; i < 16 && !(ctx->dirty & FD_DIRTY_BUFFERS); i++) {
+ if (ctx->buffers[PIPE_SHADER_VERTEX][i].buffer == prsc)
+ ctx->dirty |= FD_DIRTY_BUFFERS;
+ if (ctx->buffers[PIPE_SHADER_FRAGMENT][i].buffer == prsc)
+ ctx->dirty |= FD_DIRTY_BUFFERS;
+ }
+
/* VBOs */
for (i = 0; i < ctx->vtx.vertexbuf.count && !(ctx->dirty &
FD_DIRTY_VTXBUF); i++) {
if (ctx->vtx.vertexbuf.vb[i].buffer == prsc)
diff --git a/src/gallium/drivers/freedreno/freedreno_state.c
b/src/gallium/drivers/freedreno/freedreno_state.c
index 685d3a7..aba806b 100644
--- a/src/gallium/drivers/freedreno/freedreno_state.c
+++ b/src/gallium/drivers/freedreno/freedreno_state.c
@@ -373,6 +373,28 @@ fd_set_stream_output_targets(struct pipe_context *pctx,
ctx->dirty |= FD_DIRTY_STREAMOUT;
}
+static void
+fd_set_shader_buffers(struct pipe_context *pctx, unsigned shader,
+ unsigned start, unsigned nr,
+ struct pipe_shader_buffer *buffers)
+{
+ struct fd_context *ctx = fd_context(pctx);
+ int i;
+
+ for (i = 0; i < nr; i++) {
+ struct pipe_shader_buffer *buf = &ctx->buffers[shader][start +
i];
+ struct pipe_resource *res = buffers ? buffers[i].buffer : NULL;
+ if (buf->buffer != res)
+ pipe_resource_reference(&buf->buffer, res);
+ if (res) {
+ buf->buffer_offset = buffers[i].buffer_offset;
+ buf->buffer_size = buffers[i].buffer_size;
+ }
+ }
+
+ ctx->dirty |= FD_DIRTY_BUFFERS;
+}
+
void
fd_state_init(struct pipe_context *pctx)
{
@@ -405,4 +427,6 @@ fd_state_init(struct pipe_context *pctx)
pctx->create_stream_output_target = fd_create_stream_output_target;
pctx->stream_output_target_destroy = fd_stream_output_target_destroy;
pctx->set_stream_output_targets = fd_set_stream_output_targets;
+
+ pctx->set_shader_buffers = fd_set_shader_buffers;
}
--
2.4.9
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailma
[Mesa-dev] [PATCH 07/11] ttn: add buffer support
This adds preliminary support for dealing with buffers. There are a few
deficiencies, but nothing that should prevent atomic counters and ssbo
buffers from working. This converts to using ssbo intrinsics.
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/nir/tgsi_to_nir.c | 118 +++-
1 file changed, 117 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 9cfb62a..da84454 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -280,6 +280,8 @@ ttn_emit_declaration(struct ttn_compile *c)
c->addr_reg->num_components = 4;
} else if (file == TGSI_FILE_SYSTEM_VALUE) {
/* Nothing to record for system values. */
+ } else if (file == TGSI_FILE_BUFFER) {
+ /* Nothing to record for buffers. */
} else if (file == TGSI_FILE_SAMPLER) {
/* Nothing to record for samplers. */
} else if (file == TGSI_FILE_SAMPLER_VIEW) {
@@ -763,7 +765,8 @@ ttn_get_src(struct ttn_compile *c, struct
tgsi_full_src_register *tgsi_fsrc)
if (tgsi_src->File == TGSI_FILE_NULL) {
return nir_imm_float(b, 0.0);
- } else if (tgsi_src->File == TGSI_FILE_SAMPLER) {
+ } else if (tgsi_src->File == TGSI_FILE_SAMPLER ||
+ tgsi_src->File == TGSI_FILE_BUFFER) {
/* Only the index of the sampler gets used in texturing, and it will
* handle looking that up on its own instead of using the nir_alu_src.
*/
@@ -1483,6 +1486,100 @@ ttn_txq(struct ttn_compile *c, nir_alu_dest dest,
nir_ssa_def **src)
ttn_move_dest_masked(b, dest, &qlv->dest.ssa, TGSI_WRITEMASK_W);
}
+static void
+ttn_buffer(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
+{
+ nir_builder *b = &c->build;
+ struct tgsi_full_instruction *tgsi_inst = &c->token->FullInstruction;
+ nir_intrinsic_instr *instr;
+ nir_intrinsic_op op;
+ bool buf_offset_const = false;
+
+ switch (tgsi_inst->Instruction.Opcode) {
+ case TGSI_OPCODE_LOAD:
+ op = nir_intrinsic_load_ssbo;
+ /* TODO: figure out how to extract the immediate */
+ if (1 || tgsi_inst->Src[1].Register.File != TGSI_FILE_IMMEDIATE)
+ op = nir_intrinsic_load_ssbo_indirect;
+ else
+ buf_offset_const = true;
+ break;
+ case TGSI_OPCODE_STORE:
+ op = nir_intrinsic_store_ssbo;
+ /* TODO: figure out how to extract the immediate */
+ if (1 || tgsi_inst->Src[1].Register.File != TGSI_FILE_IMMEDIATE)
+ op = nir_intrinsic_store_ssbo_indirect;
+ else
+ buf_offset_const = true;
+ break;
+ case TGSI_OPCODE_ATOMUADD:
+ op = nir_intrinsic_ssbo_atomic_add;
+ break;
+ case TGSI_OPCODE_ATOMXCHG:
+ op = nir_intrinsic_ssbo_atomic_exchange;
+ break;
+ case TGSI_OPCODE_ATOMCAS:
+ op = nir_intrinsic_ssbo_atomic_comp_swap;
+ break;
+ case TGSI_OPCODE_ATOMAND:
+ op = nir_intrinsic_ssbo_atomic_and;
+ break;
+ case TGSI_OPCODE_ATOMOR:
+ op = nir_intrinsic_ssbo_atomic_or;
+ break;
+ case TGSI_OPCODE_ATOMXOR:
+ op = nir_intrinsic_ssbo_atomic_xor;
+ break;
+ case TGSI_OPCODE_ATOMUMIN: /* XXX */
+ case TGSI_OPCODE_ATOMIMIN:
+ op = nir_intrinsic_ssbo_atomic_min;
+ break;
+ case TGSI_OPCODE_ATOMUMAX: /* XXX */
+ case TGSI_OPCODE_ATOMIMAX:
+ op = nir_intrinsic_ssbo_atomic_max;
+ break;
+ default:
+ unreachable("Unexpected buffer opcode");
+ }
+
+ for (unsigned c = 0; c < 4; c++) {
+ if (!(dest.write_mask & (1 << c)))
+ continue;
+
+ instr = nir_intrinsic_instr_create(b->shader, op);
+ instr->src[0] = nir_src_for_ssa(
+nir_imm_int(b, tgsi_inst->Src[0].Register.Index));
+/* TODO: make this work and adjust conditions above.
+ if (buf_offset_const) {
+ nir_const_value *val = nir_src_as_const_value(
+ nir_src_for_ssa(src[1]));
+ instr->const_index[0] = val->u[c];
+ }
+*/
+ if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
+ instr->num_components = 1;
+ if (!buf_offset_const)
+instr->src[1] = nir_src_for_ssa(nir_channel(b, src[1], c));
+ } else if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
+ instr->src[1] = instr->src[0];
+ instr->src[0] = nir_src_for_ssa(nir_channel(b, src[2], c));
+ if (!buf_offset_const)
+instr->src[2] = nir_src_for_ssa(nir_channel(b, src[1], c));
+ } else {
+ instr->num_components = 1;
+ instr->src[1] = nir_src_for_ssa(nir_channel(b, src[1], c));
+ instr->src[2] = nir_src_for_ssa(nir_channel(b, src[2], c));
+ if (op == TGSI_OPCODE_ATOMCAS)
+instr->src[3] = nir_src_for_ssa(nir_channel(b, src[3], c));
+ }
+
+ nir_ssa_dest_init(&instr->instr, &instr->dest, 1, NULL);
+ nir_builder_instr_insert(b, &instr->instr);
+
+ ttn_move_dest_masked(b, dest, &instr->dest.ssa, 1 << c);
[Mesa-dev] [PATCH 03/11] tgsi: add a is_store property
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/tgsi/tgsi_info.c | 446 -
src/gallium/auxiliary/tgsi/tgsi_info.h | 1 +
2 files changed, 224 insertions(+), 223 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 3b40c3d..8a0e9c4 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -37,231 +37,231 @@
static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
{
- { 1, 1, 0, 0, 0, 0, COMP, "ARL", TGSI_OPCODE_ARL },
- { 1, 1, 0, 0, 0, 0, COMP, "MOV", TGSI_OPCODE_MOV },
- { 1, 1, 0, 0, 0, 0, CHAN, "LIT", TGSI_OPCODE_LIT },
- { 1, 1, 0, 0, 0, 0, REPL, "RCP", TGSI_OPCODE_RCP },
- { 1, 1, 0, 0, 0, 0, REPL, "RSQ", TGSI_OPCODE_RSQ },
- { 1, 1, 0, 0, 0, 0, CHAN, "EXP", TGSI_OPCODE_EXP },
- { 1, 1, 0, 0, 0, 0, CHAN, "LOG", TGSI_OPCODE_LOG },
- { 1, 2, 0, 0, 0, 0, COMP, "MUL", TGSI_OPCODE_MUL },
- { 1, 2, 0, 0, 0, 0, COMP, "ADD", TGSI_OPCODE_ADD },
- { 1, 2, 0, 0, 0, 0, REPL, "DP3", TGSI_OPCODE_DP3 },
- { 1, 2, 0, 0, 0, 0, REPL, "DP4", TGSI_OPCODE_DP4 },
- { 1, 2, 0, 0, 0, 0, CHAN, "DST", TGSI_OPCODE_DST },
- { 1, 2, 0, 0, 0, 0, COMP, "MIN", TGSI_OPCODE_MIN },
- { 1, 2, 0, 0, 0, 0, COMP, "MAX", TGSI_OPCODE_MAX },
- { 1, 2, 0, 0, 0, 0, COMP, "SLT", TGSI_OPCODE_SLT },
- { 1, 2, 0, 0, 0, 0, COMP, "SGE", TGSI_OPCODE_SGE },
- { 1, 3, 0, 0, 0, 0, COMP, "MAD", TGSI_OPCODE_MAD },
- { 1, 2, 0, 0, 0, 0, COMP, "SUB", TGSI_OPCODE_SUB },
- { 1, 3, 0, 0, 0, 0, COMP, "LRP", TGSI_OPCODE_LRP },
- { 1, 3, 0, 0, 0, 0, COMP, "FMA", TGSI_OPCODE_FMA },
- { 1, 1, 0, 0, 0, 0, REPL, "SQRT", TGSI_OPCODE_SQRT },
- { 1, 3, 0, 0, 0, 0, REPL, "DP2A", TGSI_OPCODE_DP2A },
- { 0, 0, 0, 0, 0, 0, NONE, "", 22 }, /* removed */
- { 0, 0, 0, 0, 0, 0, NONE, "", 23 }, /* removed */
- { 1, 1, 0, 0, 0, 0, COMP, "FRC", TGSI_OPCODE_FRC },
- { 1, 3, 0, 0, 0, 0, COMP, "CLAMP", TGSI_OPCODE_CLAMP },
- { 1, 1, 0, 0, 0, 0, COMP, "FLR", TGSI_OPCODE_FLR },
- { 1, 1, 0, 0, 0, 0, COMP, "ROUND", TGSI_OPCODE_ROUND },
- { 1, 1, 0, 0, 0, 0, REPL, "EX2", TGSI_OPCODE_EX2 },
- { 1, 1, 0, 0, 0, 0, REPL, "LG2", TGSI_OPCODE_LG2 },
- { 1, 2, 0, 0, 0, 0, REPL, "POW", TGSI_OPCODE_POW },
- { 1, 2, 0, 0, 0, 0, COMP, "XPD", TGSI_OPCODE_XPD },
- { 0, 0, 0, 0, 0, 0, NONE, "", 32 }, /* removed */
- { 1, 1, 0, 0, 0, 0, COMP, "ABS", TGSI_OPCODE_ABS },
- { 0, 0, 0, 0, 0, 0, NONE, "", 34 }, /* removed */
- { 1, 2, 0, 0, 0, 0, REPL, "DPH", TGSI_OPCODE_DPH },
- { 1, 1, 0, 0, 0, 0, REPL, "COS", TGSI_OPCODE_COS },
- { 1, 1, 0, 0, 0, 0, COMP, "DDX", TGSI_OPCODE_DDX },
- { 1, 1, 0, 0, 0, 0, COMP, "DDY", TGSI_OPCODE_DDY },
- { 0, 0, 0, 0, 0, 0, NONE, "KILL", TGSI_OPCODE_KILL },
- { 1, 1, 0, 0, 0, 0, COMP, "PK2H", TGSI_OPCODE_PK2H },
- { 1, 1, 0, 0, 0, 0, COMP, "PK2US", TGSI_OPCODE_PK2US },
- { 1, 1, 0, 0, 0, 0, COMP, "PK4B", TGSI_OPCODE_PK4B },
- { 1, 1, 0, 0, 0, 0, COMP, "PK4UB", TGSI_OPCODE_PK4UB },
- { 0, 1, 0, 0, 0, 1, NONE, "", 44 }, /* removed */
- { 1, 2, 0, 0, 0, 0, COMP, "SEQ", TGSI_OPCODE_SEQ },
- { 0, 1, 0, 0, 0, 1, NONE, "", 46 }, /* removed */
- { 1, 2, 0, 0, 0, 0, COMP, "SGT", TGSI_OPCODE_SGT },
- { 1, 1, 0, 0, 0, 0, REPL, "SIN", TGSI_OPCODE_SIN },
- { 1, 2, 0, 0, 0, 0, COMP, "SLE", TGSI_OPCODE_SLE },
- { 1, 2, 0, 0, 0, 0, COMP, "SNE", TGSI_OPCODE_SNE },
- { 0, 1, 0, 0, 0, 1, NONE, "", 51 }, /* removed */
- { 1, 2, 1, 0, 0, 0, OTHR, "TEX", TGSI_OPCODE_TEX },
- { 1, 4, 1, 0, 0, 0, OTHR, "TXD", TGSI_OPCODE_TXD },
- { 1, 2, 1, 0, 0, 0, OTHR, "TXP", TGSI_OPCODE_TXP },
- { 1, 1, 0, 0, 0, 0, COMP, "UP2H", TGSI_OPCODE_UP2H },
- { 1, 1, 0, 0, 0, 0, COMP, "UP2US", TGSI_OPCODE_UP2US },
- { 1, 1, 0, 0, 0, 0, COMP, "UP4B", TGSI_OPCODE_UP4B },
- { 1, 1, 0, 0, 0, 0, COMP, "UP4UB", TGSI_OPCODE_UP4UB },
- { 0, 1, 0, 0, 0, 1, NONE, "", 59 }, /* removed */
- { 0, 1, 0, 0, 0, 1, NONE, "", 60 }, /* removed */
- { 1, 1, 0, 0, 0, 0, COMP, "ARR", TGSI_OPCODE_ARR },
- { 0, 1, 0, 0, 0, 1, NONE, "", 62 }, /* removed */
- { 0, 0, 0, 1, 0, 0, NONE, "CAL", TGSI_OPCODE_CAL },
- { 0, 0, 0, 0, 0, 0, NONE, "RET", TGSI_OPCODE_RET },
- { 1, 1, 0, 0, 0, 0, COMP, "SSG", TGSI_OPCODE_SSG },
- { 1, 3, 0, 0, 0, 0, COMP, "CMP", TGSI_OPCODE_CMP },
- { 1, 1, 0, 0, 0, 0, CHAN, "SCS", TGSI_OPCODE_SCS },
- { 1, 2, 1, 0, 0, 0, OTHR, "TXB", TGSI_OPCODE_TXB },
- { 0, 1, 0, 0, 0, 1, NONE, "", 69 }, /* removed */
- { 1, 2, 0, 0, 0, 0, COMP, "DIV", TGSI_OPCODE_DIV },
- { 1, 2, 0, 0, 0, 0, REPL, "DP2", TGSI_OPCODE_DP2 },
- { 1, 2, 1, 0, 0, 0, OTHR, "TXL", TGSI_OPCODE_TXL },
- { 0, 0, 0, 0, 0, 0, NONE, "BRK", TGSI_OPCODE_BRK },
- { 0, 1, 0, 1, 0, 1, NONE, "IF", TGSI_OPCODE_IF },
- { 0, 1, 0, 1, 0, 1, NONE, "UIF", TGSI_OPCODE_UIF },
- { 0, 1, 0, 0, 0, 1, NONE, "", 76 }, /* removed */
- { 0, 0, 0, 1, 1, 1, NONE, "ELSE", TGSI_OPCODE_ELSE },
- { 0, 0, 0, 0, 1, 0, NONE, "
[Mesa-dev] [PATCH 09/11] freedreno/ir3: upload shader buffer addresses after ubos
Signed-off-by: Ilia Mirkin
---
.../drivers/freedreno/ir3/ir3_compiler_nir.c | 3 +-
src/gallium/drivers/freedreno/ir3/ir3_shader.c | 42 ++
src/gallium/drivers/freedreno/ir3/ir3_shader.h | 4 ++-
3 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 2b9d200..84f1770 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -264,7 +264,8 @@ compile_init(struct ir3_compiler *compiler,
*/
/* reserve 4 (vec4) slots for ubo base addresses: */
- so->first_immediate += 4;
+ /* reserve 8 (vec4) slots for buffer base addresses: */
+ so->first_immediate += 12;
if (so->type == SHADER_VERTEX) {
/* driver params (see ir3_driver_param): */
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c
b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
index 7b56533..44a4d5e 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
@@ -528,6 +528,34 @@ emit_ubos(struct ir3_shader_variant *v, struct
fd_ringbuffer *ring,
}
static void
+emit_buffers(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
+struct pipe_shader_buffer *buffers)
+{
+ uint32_t offset = v->first_driver_param + IR3_BUFS_OFF;
+ if (v->constlen > offset) {
+ struct fd_context *ctx = fd_context(v->shader->pctx);
+ uint32_t params = MIN2(4, v->constlen - offset) * 4;
+ uint32_t offsets[params];
+ struct fd_bo *bos[params];
+
+ for (uint32_t i = 0; i < params; i++) {
+ struct pipe_shader_buffer *sb = &buffers[i];
+
+ if (sb->buffer) {
+ offsets[i] = sb->buffer_offset;
+ bos[i] = fd_resource(sb->buffer)->bo;
+ } else {
+ offsets[i] = 0;
+ bos[i] = NULL;
+ }
+ }
+
+ fd_wfi(ctx, ring);
+ ctx->emit_const_bo(ring, v->type, true, offset * 4, params,
bos, offsets);
+ }
+}
+
+static void
emit_immediates(struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
{
struct fd_context *ctx = fd_context(v->shader->pctx);
@@ -655,6 +683,20 @@ ir3_emit_consts(struct ir3_shader_variant *v, struct
fd_ringbuffer *ring,
emit_immediates(v, ring);
}
+ if (dirty & (FD_DIRTY_PROG | FD_DIRTY_BUFFERS)) {
+ struct pipe_shader_buffer *buffers;
+
+ if (v->type == SHADER_VERTEX) {
+ buffers = ctx->buffers[PIPE_SHADER_VERTEX];
+ } else if (v->type == SHADER_FRAGMENT) {
+ buffers = ctx->buffers[PIPE_SHADER_FRAGMENT];
+ } else {
+ unreachable("bad shader type");
+ }
+
+ emit_buffers(v, ring, buffers);
+ }
+
/* emit driver params every time: */
/* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
if (info && (v->type == SHADER_VERTEX)) {
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index 6dc0ce1..25c1709 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -50,6 +50,7 @@ enum ir3_driver_param {
*
*num_uniform * vec4 - user consts
*4 * vec4- UBO addresses
+ *8 * vec4- Buffer addresses
*if (vertex shader) {
*N * vec4- driver params (IR3_DP_*)
*1 * vec4- stream-out addresses
@@ -59,7 +60,8 @@ enum ir3_driver_param {
* that we don't need..
*/
#define IR3_UBOS_OFF 0 /* UBOs after user consts */
-#define IR3_DRIVER_PARAM_OFF 4 /* driver params after UBOs */
+#define IR3_BUFS_OFF 4 /* Buffers after UBOs */
+#define IR3_DRIVER_PARAM_OFF 12 /* driver params after buffers */
#define IR3_TFBOS_OFF (IR3_DRIVER_PARAM_OFF + IR3_DP_COUNT/4)
/* Configuration key used to identify a shader variant.. different
--
2.4.9
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 02/11] ureg: add buffer support to ureg
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/tgsi/tgsi_strings.c | 3 ++-
src/gallium/auxiliary/tgsi/tgsi_ureg.c | 27 +++
src/gallium/auxiliary/tgsi/tgsi_ureg.h | 3 +++
src/gallium/include/pipe/p_shader_tokens.h | 1 +
4 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c
b/src/gallium/auxiliary/tgsi/tgsi_strings.c
index 8271ea0..41a03e3 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c
@@ -55,7 +55,8 @@ static const char *tgsi_file_names[] =
"PRED",
"SV",
"RES",
- "SVIEW"
+ "SVIEW",
+ "BUFFER",
};
const char *tgsi_semantic_names[TGSI_SEMANTIC_COUNT] =
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index ff3e4b7..13976c9 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -164,6 +164,9 @@ struct ureg_program
} image[PIPE_MAX_SHADER_IMAGES];
unsigned nr_images;
+ struct ureg_src buffer[PIPE_MAX_SHADER_BUFFERS];
+ unsigned nr_buffers;
+
struct util_bitmask *free_temps;
struct util_bitmask *local_temps;
struct util_bitmask *decl_temps;
@@ -688,6 +691,26 @@ ureg_DECL_image(struct ureg_program *ureg,
return reg;
}
+/* Allocate a new buffer.
+ */
+struct ureg_src ureg_DECL_buffer(struct ureg_program *ureg, unsigned nr)
+{
+ unsigned i;
+
+ for (i = 0; i < ureg->nr_buffers; i++)
+ if (ureg->buffer[i].Index == nr)
+ return ureg->buffer[i];
+
+ if (i < PIPE_MAX_SHADER_BUFFERS) {
+ ureg->buffer[i] = ureg_src_register(TGSI_FILE_BUFFER, nr);
+ ureg->nr_buffers++;
+ return ureg->buffer[i];
+ }
+
+ assert(0);
+ return ureg->buffer[0];
+}
+
static int
match_or_expand_immediate64( const unsigned *v,
int type,
@@ -1712,6 +1735,10 @@ static void emit_decls( struct ureg_program *ureg )
ureg->image[i].raw);
}
+ for (i = 0; i < ureg->nr_buffers; i++) {
+ emit_decl_range(ureg, TGSI_FILE_BUFFER, ureg->buffer[i].Index, 1);
+ }
+
if (ureg->const_decls.nr_constant_ranges) {
for (i = 0; i < ureg->const_decls.nr_constant_ranges; i++) {
emit_decl_range(ureg,
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
index bba2afb..c4b19e2 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
@@ -335,6 +335,9 @@ ureg_DECL_image(struct ureg_program *ureg,
boolean wr,
boolean raw);
+struct ureg_src
+ureg_DECL_buffer(struct ureg_program *ureg, unsigned nr);
+
static inline struct ureg_src
ureg_imm4f( struct ureg_program *ureg,
float a, float b,
diff --git a/src/gallium/include/pipe/p_shader_tokens.h
b/src/gallium/include/pipe/p_shader_tokens.h
index 5498ecd..341c345 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -78,6 +78,7 @@ enum tgsi_file_type {
TGSI_FILE_SYSTEM_VALUE=9,
TGSI_FILE_IMAGE =10,
TGSI_FILE_SAMPLER_VIEW=11,
+ TGSI_FILE_BUFFER =12,
TGSI_FILE_COUNT /**< how many TGSI_FILE_ types */
};
--
2.4.9
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 05/11] gallium: add PIPE_SHADER_CAP_MAX_BUFFERS
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/gallivm/lp_bld_limits.h| 1 +
src/gallium/auxiliary/tgsi/tgsi_exec.h | 1 +
src/gallium/docs/source/screen.rst | 4
src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++
src/gallium/drivers/nouveau/nv30/nv30_screen.c | 2 ++
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 +
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 +
src/gallium/drivers/r300/r300_screen.c | 2 ++
src/gallium/drivers/r600/r600_pipe.c | 1 +
src/gallium/drivers/radeonsi/si_pipe.c | 2 ++
src/gallium/drivers/svga/svga_screen.c | 3 +++
src/gallium/drivers/vc4/vc4_screen.c | 2 ++
src/gallium/include/pipe/p_defines.h | 3 ++-
13 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h
b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
index 571c615..1f49157 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
@@ -136,6 +136,7 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
+ case PIPE_SHADER_CAP_MAX_BUFFERS:
return 0;
}
/* if we get here, we missed a shader cap above (and should have seen
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index a371aa9..be77979 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -473,6 +473,7 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
return 1;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
+ case PIPE_SHADER_CAP_MAX_BUFFERS:
return 0;
}
/* if we get here, we missed a shader cap above (and should have seen
diff --git a/src/gallium/docs/source/screen.rst
b/src/gallium/docs/source/screen.rst
index e780047..e2550f5 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -356,6 +356,10 @@ to be 0.
are supported.
* ``PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE``: Whether the driver doesn't
ignore tgsi_declaration_range::Last for shader inputs and outputs.
+* ``PIPE_SHADER_CAP_MAX_BUFFERS``: Maximum number of memory buffers
+ (also used to implement atomic counters). Having this be non-0 also
+ implies support for the ``LOAD``, ``STORE``, and ``ATOM*`` TGSI
+ opcodes.
.. _pipe_compute_cap:
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c
b/src/gallium/drivers/freedreno/freedreno_screen.c
index c9228c5..34f33c2 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -404,6 +404,8 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
unsigned shader,
return 16;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
+ case PIPE_SHADER_CAP_MAX_BUFFERS:
+ return 0;
}
debug_printf("unknown shader param %d\n", param);
return 0;
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index 806d4e6..461795d 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -261,6 +261,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
unsigned shader,
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
+ case PIPE_SHADER_CAP_MAX_BUFFERS:
return 0;
default:
debug_printf("unknown vertex shader param %d\n", param);
@@ -302,6 +303,7 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
unsigned shader,
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
+ case PIPE_SHADER_CAP_MAX_BUFFERS:
return 0;
default:
debug_printf("unknown fragment shader param %d\n", param);
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index c3bbc83..f74daac 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -297,6 +297,7 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
unsigned shader,
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
+ case PIPE_SHADER_CAP_MAX_BUFFERS:
return 0;
default:
NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
[Mesa-dev] [PATCH 11/11] freedreno: enable ARB_shader_atomic_counters
Signed-off-by: Ilia Mirkin
---
docs/relnotes/11.1.0.html| 1 +
src/gallium/drivers/freedreno/freedreno_screen.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/relnotes/11.1.0.html b/docs/relnotes/11.1.0.html
index e28fab6..6e59294 100644
--- a/docs/relnotes/11.1.0.html
+++ b/docs/relnotes/11.1.0.html
@@ -45,6 +45,7 @@ Note: some of the new features are only available with
certain drivers.
GL_ARB_blend_func_extended on freedreno (a3xx)
+GL_ARB_shader_atomic_counters on freedreno
GL_ARB_shader_texture_image_samples on i965, nv50, nvc0, r600,
radeonsi
GL_ARB_texture_barrier / GL_NV_texture_barrier on i965
GL_ARB_texture_query_lod on softpipe
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c
b/src/gallium/drivers/freedreno/freedreno_screen.c
index 34f33c2..208d8d2 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -405,7 +405,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
unsigned shader,
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_MAX_BUFFERS:
- return 0;
+ return is_ir3(screen) ? PIPE_MAX_SHADER_BUFFERS : 0;
}
debug_printf("unknown shader param %d\n", param);
return 0;
--
2.4.9
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 06/11] st/mesa: add atomic buffer support
Signed-off-by: Ilia Mirkin --- src/mesa/Makefile.sources| 1 + src/mesa/program/ir_to_mesa.cpp | 4 +- src/mesa/state_tracker/st_atom.c | 5 + src/mesa/state_tracker/st_atom.h | 5 + src/mesa/state_tracker/st_atom_atomicbuf.c | 151 +++ src/mesa/state_tracker/st_cb_bufferobjects.c | 3 + src/mesa/state_tracker/st_context.c | 1 + src/mesa/state_tracker/st_context.h | 1 + src/mesa/state_tracker/st_extensions.c | 15 +++ src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 133 +-- 10 files changed, 310 insertions(+), 9 deletions(-) create mode 100644 src/mesa/state_tracker/st_atom_atomicbuf.c diff --git a/src/mesa/Makefile.sources b/src/mesa/Makefile.sources index 0915594..5dd98c3 100644 --- a/src/mesa/Makefile.sources +++ b/src/mesa/Makefile.sources @@ -393,6 +393,7 @@ VBO_FILES = \ STATETRACKER_FILES = \ state_tracker/st_atom_array.c \ + state_tracker/st_atom_atomicbuf.c \ state_tracker/st_atom_blend.c \ state_tracker/st_atom.c \ state_tracker/st_atom_clip.c \ diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp index 4201a80..580f907 100644 --- a/src/mesa/program/ir_to_mesa.cpp +++ b/src/mesa/program/ir_to_mesa.cpp @@ -535,11 +535,11 @@ type_size(const struct glsl_type *type) case GLSL_TYPE_SAMPLER: case GLSL_TYPE_IMAGE: case GLSL_TYPE_SUBROUTINE: + case GLSL_TYPE_ATOMIC_UINT: /* Samplers take up one slot in UNIFORMS[], but they're baked in * at link time. */ return 1; - case GLSL_TYPE_ATOMIC_UINT: case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: @@ -2458,10 +2458,10 @@ _mesa_associate_uniform_storage(struct gl_context *ctx, case GLSL_TYPE_SAMPLER: case GLSL_TYPE_IMAGE: case GLSL_TYPE_SUBROUTINE: + case GLSL_TYPE_ATOMIC_UINT: format = uniform_native; columns = 1; break; - case GLSL_TYPE_ATOMIC_UINT: case GLSL_TYPE_ARRAY: case GLSL_TYPE_VOID: case GLSL_TYPE_STRUCT: diff --git a/src/mesa/state_tracker/st_atom.c b/src/mesa/state_tracker/st_atom.c index 43dbadd..920ee11 100644 --- a/src/mesa/state_tracker/st_atom.c +++ b/src/mesa/state_tracker/st_atom.c @@ -76,6 +76,11 @@ static const struct st_tracked_state *atoms[] = &st_bind_tes_ubos, &st_bind_fs_ubos, &st_bind_gs_ubos, + &st_bind_vs_atomics, + &st_bind_tcs_atomics, + &st_bind_tes_atomics, + &st_bind_fs_atomics, + &st_bind_gs_atomics, &st_update_pixel_transfer, &st_update_tess, diff --git a/src/mesa/state_tracker/st_atom.h b/src/mesa/state_tracker/st_atom.h index a24842b..7cbd52e 100644 --- a/src/mesa/state_tracker/st_atom.h +++ b/src/mesa/state_tracker/st_atom.h @@ -78,6 +78,11 @@ extern const struct st_tracked_state st_bind_vs_ubos; extern const struct st_tracked_state st_bind_gs_ubos; extern const struct st_tracked_state st_bind_tcs_ubos; extern const struct st_tracked_state st_bind_tes_ubos; +extern const struct st_tracked_state st_bind_fs_atomics; +extern const struct st_tracked_state st_bind_vs_atomics; +extern const struct st_tracked_state st_bind_gs_atomics; +extern const struct st_tracked_state st_bind_tcs_atomics; +extern const struct st_tracked_state st_bind_tes_atomics; extern const struct st_tracked_state st_update_pixel_transfer; extern const struct st_tracked_state st_update_tess; diff --git a/src/mesa/state_tracker/st_atom_atomicbuf.c b/src/mesa/state_tracker/st_atom_atomicbuf.c new file mode 100644 index 000..9bc7862 --- /dev/null +++ b/src/mesa/state_tracker/st_atom_atomicbuf.c @@ -0,0 +1,151 @@ +/** + * + * Copyright 2014 Ilia Mirkin. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTH
[Mesa-dev] [PATCH 00/11] Add atomic counters and partial buffer support to gallium
This series is enough to get atomic counters going on freedreno. I half-heartedly started adding image and generic buffer support, but some freedreno-side issues (to do with instruction encoding) would have prevented me from testing it all the way. The idea is that BUFFER[n] represents a shader buffer, and IMAGE[n] represents a shader image. The LOAD/STORE/ATOM* instructions can take either as a resource, and treat the offset/coordinate argument accordingly. I didn't double-check if any image functions ever need more than 4 coordinate args, if so a LOAD2 variant can be added later. Atomic counters are then implemented as LOAD + ATOMUADD on top of buffers. For the TGSI -> NIR bits (required for freedreno), that all gets reimplemented on top of the ssbo intrinsics. The two outstanding issues are that atomic buffer bindings are messed up, see Timothy Arceri's patch [PATCH 14/24] i965: fix atomic buffer index for bindings other than 0 If that gets accepted, a similar solution can be implemented in st/mesa. The other issue is that freedreno doesn't treat discards the way the piglit test likes. This is the age-old "should discard exit the shader" question, and the spec seems to say yes. However I seem to recall there being applications which relied on the answer to be "no" due to derivatives. Either way, this issue shouldn't really block this series. Note that nouveau support for this is blocked on figuring out how to get global memory access to actually work from the graphics pipeline. I have no plans on looking at either r600 or radeonsi for this functionality. Ilia Mirkin (11): tgsi: add ureg support for image decls ureg: add buffer support to ureg tgsi: add a is_store property tgsi: update atomic op docs gallium: add PIPE_SHADER_CAP_MAX_BUFFERS st/mesa: add atomic buffer support ttn: add buffer support freedreno: add support for state tracking shader buffers freedreno/ir3: upload shader buffer addresses after ubos freedreno/ir3: add support for ssbo intrinsics freedreno: enable ARB_shader_atomic_counters docs/relnotes/11.1.0.html | 1 + src/gallium/auxiliary/gallivm/lp_bld_limits.h | 1 + src/gallium/auxiliary/nir/tgsi_to_nir.c| 118 +- src/gallium/auxiliary/tgsi/tgsi_build.c| 62 +-- src/gallium/auxiliary/tgsi/tgsi_dump.c | 10 +- src/gallium/auxiliary/tgsi/tgsi_exec.h | 1 + src/gallium/auxiliary/tgsi/tgsi_info.c | 446 ++--- src/gallium/auxiliary/tgsi/tgsi_info.h | 1 + src/gallium/auxiliary/tgsi/tgsi_parse.c| 4 +- src/gallium/auxiliary/tgsi/tgsi_parse.h| 2 +- src/gallium/auxiliary/tgsi/tgsi_strings.c | 3 +- src/gallium/auxiliary/tgsi/tgsi_text.c | 10 +- src/gallium/auxiliary/tgsi/tgsi_ureg.c | 104 + src/gallium/auxiliary/tgsi/tgsi_ureg.h | 10 + src/gallium/docs/source/screen.rst | 4 + src/gallium/docs/source/tgsi.rst | 93 ++--- src/gallium/drivers/freedreno/freedreno_context.h | 2 + src/gallium/drivers/freedreno/freedreno_draw.c | 8 + src/gallium/drivers/freedreno/freedreno_resource.c | 8 + src/gallium/drivers/freedreno/freedreno_screen.c | 2 + src/gallium/drivers/freedreno/freedreno_state.c| 24 ++ src/gallium/drivers/freedreno/ir3/ir3.c| 2 +- src/gallium/drivers/freedreno/ir3/ir3.h| 20 + .../drivers/freedreno/ir3/ir3_compiler_nir.c | 77 +++- src/gallium/drivers/freedreno/ir3/ir3_depth.c | 3 +- src/gallium/drivers/freedreno/ir3/ir3_legalize.c | 4 +- src/gallium/drivers/freedreno/ir3/ir3_shader.c | 42 ++ src/gallium/drivers/freedreno/ir3/ir3_shader.h | 4 +- .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 12 +- src/gallium/drivers/nouveau/nv30/nv30_screen.c | 2 + src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 + src/gallium/drivers/r300/r300_screen.c | 2 + src/gallium/drivers/r600/r600_pipe.c | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 2 + src/gallium/drivers/svga/svga_screen.c | 3 + src/gallium/drivers/vc4/vc4_screen.c | 2 + src/gallium/include/pipe/p_defines.h | 3 +- src/gallium/include/pipe/p_shader_tokens.h | 8 +- src/mesa/Makefile.sources | 1 + src/mesa/program/ir_to_mesa.cpp| 4 +- src/mesa/state_tracker/st_atom.c | 5 + src/mesa/state_tracker/st_atom.h | 5 + src/mesa/state_tracker/st_atom_atomicbuf.c | 151 +++ src/mesa/state_tracker/st_cb_bufferobjects.c | 3 + src/mesa/state_tracker/st_context.c| 1 + src/mesa/state_tracker/st_context.h| 1 + src/mesa/state_tracker/st_extensions.c
[Mesa-dev] [PATCH 01/11] tgsi: add ureg support for image decls
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/tgsi/tgsi_build.c| 62 +
src/gallium/auxiliary/tgsi/tgsi_dump.c | 10 +--
src/gallium/auxiliary/tgsi/tgsi_parse.c| 4 +-
src/gallium/auxiliary/tgsi/tgsi_parse.h| 2 +-
src/gallium/auxiliary/tgsi/tgsi_text.c | 10 +--
src/gallium/auxiliary/tgsi/tgsi_ureg.c | 77 ++
src/gallium/auxiliary/tgsi/tgsi_ureg.h | 7 ++
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 12 +++-
src/gallium/include/pipe/p_shader_tokens.h | 7 +-
9 files changed, 145 insertions(+), 46 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c
b/src/gallium/auxiliary/tgsi/tgsi_build.c
index fdb7feb..bb9d0cb 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.c
@@ -259,36 +259,39 @@ tgsi_build_declaration_semantic(
return ds;
}
-static struct tgsi_declaration_resource
-tgsi_default_declaration_resource(void)
+static struct tgsi_declaration_image
+tgsi_default_declaration_image(void)
{
- struct tgsi_declaration_resource dr;
+ struct tgsi_declaration_image di;
- dr.Resource = TGSI_TEXTURE_BUFFER;
- dr.Raw = 0;
- dr.Writable = 0;
- dr.Padding = 0;
+ di.Resource = TGSI_TEXTURE_BUFFER;
+ di.Raw = 0;
+ di.Writable = 0;
+ di.Format = 0;
+ di.Padding = 0;
- return dr;
+ return di;
}
-static struct tgsi_declaration_resource
-tgsi_build_declaration_resource(unsigned texture,
-unsigned raw,
-unsigned writable,
-struct tgsi_declaration *declaration,
-struct tgsi_header *header)
+static struct tgsi_declaration_image
+tgsi_build_declaration_image(unsigned texture,
+ unsigned format,
+ unsigned raw,
+ unsigned writable,
+ struct tgsi_declaration *declaration,
+ struct tgsi_header *header)
{
- struct tgsi_declaration_resource dr;
+ struct tgsi_declaration_image di;
- dr = tgsi_default_declaration_resource();
- dr.Resource = texture;
- dr.Raw = raw;
- dr.Writable = writable;
+ di = tgsi_default_declaration_image();
+ di.Resource = texture;
+ di.Format = format;
+ di.Raw = raw;
+ di.Writable = writable;
declaration_grow(declaration, header);
- return dr;
+ return di;
}
static struct tgsi_declaration_sampler_view
@@ -364,7 +367,7 @@ tgsi_default_full_declaration( void )
full_declaration.Range = tgsi_default_declaration_range();
full_declaration.Semantic = tgsi_default_declaration_semantic();
full_declaration.Interp = tgsi_default_declaration_interp();
- full_declaration.Resource = tgsi_default_declaration_resource();
+ full_declaration.Image = tgsi_default_declaration_image();
full_declaration.SamplerView = tgsi_default_declaration_sampler_view();
full_declaration.Array = tgsi_default_declaration_array();
@@ -454,20 +457,21 @@ tgsi_build_full_declaration(
header );
}
- if (full_decl->Declaration.File == TGSI_FILE_RESOURCE) {
- struct tgsi_declaration_resource *dr;
+ if (full_decl->Declaration.File == TGSI_FILE_IMAGE) {
+ struct tgsi_declaration_image *di;
if (maxsize <= size) {
return 0;
}
- dr = (struct tgsi_declaration_resource *)&tokens[size];
+ di = (struct tgsi_declaration_image *)&tokens[size];
size++;
- *dr = tgsi_build_declaration_resource(full_decl->Resource.Resource,
-full_decl->Resource.Raw,
-full_decl->Resource.Writable,
-declaration,
-header);
+ *di = tgsi_build_declaration_image(full_decl->Image.Resource,
+ full_decl->Image.Format,
+ full_decl->Image.Raw,
+ full_decl->Image.Writable,
+ declaration,
+ header);
}
if (full_decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c
b/src/gallium/auxiliary/tgsi/tgsi_dump.c
index 8ceb5b4..dae311d 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_dump.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c
@@ -341,12 +341,14 @@ iter_declaration(
}
}
- if (decl->Declaration.File == TGSI_FILE_RESOURCE) {
+ if (decl->Declaration.File == TGSI_FILE_IMAGE) {
TXT(", ");
- ENM(decl->Resource.Resource, tgsi_texture_names);
- if (decl->Resource.Writable)
+ ENM(decl->Image.Resource, tgsi_texture_names);
+ TXT(", ");
+ UID(decl->Image.Format);
+ if (decl-
[Mesa-dev] [PATCH 10/11] freedreno/ir3: add support for ssbo intrinsics
The non-inc/dec encoding can use some work. But for now that's all we
get in practice.
We add an extra fake register for the benefit of instruction ordering,
based on the last memory op. This could be made smarter to work on a
per-buffer or even per-address basis, but the current solution is
simple.
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/freedreno/ir3/ir3.c| 2 +-
src/gallium/drivers/freedreno/ir3/ir3.h| 20 ++
.../drivers/freedreno/ir3/ir3_compiler_nir.c | 74 ++
src/gallium/drivers/freedreno/ir3/ir3_depth.c | 3 +-
src/gallium/drivers/freedreno/ir3/ir3_legalize.c | 4 +-
5 files changed, 99 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3.c
b/src/gallium/drivers/freedreno/ir3/ir3.c
index b24825c..389d9a0 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3.c
@@ -527,7 +527,7 @@ static int emit_cat6(struct ir3_instruction *instr, void
*ptr,
* indicate to use the src_off encoding even if offset is zero
* (but then what to do about dst_off?)
*/
- if (instr->cat6.src_offset || (instr->opc == OPC_LDG)) {
+ if (instr->cat6.src_offset || (instr->opc == OPC_LDG ||
is_atomic(instr))) {
instr_cat6a_t *cat6a = ptr;
cat6->src_off = true;
diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h
b/src/gallium/drivers/freedreno/ir3/ir3.h
index 12f2ebe..54974e5 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3.h
@@ -84,6 +84,7 @@ struct ir3_register {
*/
IR3_REG_SSA= 0x2000, /* 'instr' is ptr to assigning instr
*/
IR3_REG_PHI_SRC= 0x4000, /* phi src, regs[0]->instr points to
phi */
+ IR3_REG_FAKE = 0x8000, /* fake source, used for ordering */
} flags;
union {
@@ -580,6 +581,21 @@ static inline bool is_load(struct ir3_instruction *instr)
return false;
}
+static inline bool
+is_atomic(struct ir3_instruction *instr)
+{
+ if (!is_mem(instr))
+ return false;
+ switch (instr->opc) {
+ case OPC_ATOMIC_ADD:
+ case OPC_ATOMIC_INC:
+ case OPC_ATOMIC_DEC:
+ return true;
+ default:
+ return false;
+ }
+}
+
static inline bool is_input(struct ir3_instruction *instr)
{
/* in some cases, ldlv is used to fetch varying without
@@ -1071,6 +1087,10 @@ INSTR2(6, LDLV)
INSTR2(6, LDG)
INSTR3(6, STG)
+INSTR2(6, ATOMIC_ADD)
+INSTR1(6, ATOMIC_INC)
+INSTR1(6, ATOMIC_DEC)
+
/* * */
/* split this out or find some helper to use.. like main/bitset.h.. */
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 84f1770..d193da1 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -121,6 +121,8 @@ struct ir3_compile {
* can bail cleanly and fallback to TGSI compiler f/e
*/
bool error;
+
+ struct ir3_instruction *last_mem;
};
@@ -1233,6 +1235,64 @@ emit_intrinsic_load_ubo(struct ir3_compile *ctx,
nir_intrinsic_instr *intr,
}
}
+/* handles buffer reads/writes/atomics: */
+static void
+emit_intrinsic_buffer(struct ir3_compile *ctx, nir_intrinsic_instr *intr,
+ struct ir3_instruction **dst)
+{
+ struct ir3_block *b = ctx->block;
+ struct ir3_instruction *addr, *load, *src[3];
+ /* Buffer addresses are driver params: */
+ unsigned buf = regid(ctx->so->first_driver_param + IR3_BUFS_OFF, 0);
+ nir_const_value *index = nir_src_as_const_value(intr->src[0]);
+ nir_const_value *add;
+ unsigned offset = intr->const_index[0];
+
+ /* Get the buffer address: */
+ assert(index); /* XXX */
+ addr = create_uniform(ctx, buf + (index ? index->u[0] : 0));
+
+ /* Add the buffer offset to the address: */
+ if (intr->intrinsic != nir_intrinsic_load_ssbo &&
+ intr->intrinsic != nir_intrinsic_store_ssbo)
+ addr = ir3_ADD_S(b, addr, 0, get_src(ctx, &intr->src[1])[0], 0);
+ if (offset > 1024) {
+ addr = ir3_ADD_S(b, addr, 0, create_immed(b, offset), 0);
+ offset = 0;
+ }
+
+ switch (intr->intrinsic) {
+ case nir_intrinsic_load_ssbo:
+ case nir_intrinsic_load_ssbo_indirect:
+ load = ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
+ break;
+ case nir_intrinsic_ssbo_atomic_add:
+ add = nir_src_as_const_value(intr->src[2]);
+ if (add && add->i[0] == 1) {
+ load = ir3_ATOMIC_INC(b, addr, 0);
+ } else if (add && add->i[0] == -1) {
+ load = ir3_ATOMIC_DEC(b, addr, 0)
[Mesa-dev] [PATCH 04/11] tgsi: update atomic op docs
Specify that the operation only applies to the x component, not per-component as previously specified. This is unnecessary for GL and creates additional complications for images which need to support these operations as well. Signed-off-by: Ilia Mirkin --- src/gallium/docs/source/tgsi.rst | 93 1 file changed, 47 insertions(+), 46 deletions(-) diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index 314fe1b..32b334a 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -2252,11 +2252,11 @@ after lookup. Resource Access Opcodes ^^^ -.. opcode:: LOAD - Fetch data from a shader resource +.. opcode:: LOAD - Fetch data from a shader buffer or image Syntax: ``LOAD dst, resource, address`` - Example: ``LOAD TEMP[0], RES[0], TEMP[1]`` + Example: ``LOAD TEMP[0], BUFFER[0], TEMP[1]`` Using the provided integer address, LOAD fetches data from the specified buffer or texture without any @@ -2280,7 +2280,7 @@ Resource Access Opcodes Syntax: ``STORE resource, address, src`` - Example: ``STORE RES[0], TEMP[0], TEMP[1]`` + Example: ``STORE BUFFER[0], TEMP[0], TEMP[1]`` Using the provided integer address, STORE writes data to the specified buffer or texture. @@ -2358,158 +2358,159 @@ These opcodes provide atomic variants of some common arithmetic and logical operations. In this context atomicity means that another concurrent memory access operation that affects the same memory location is guaranteed to be performed strictly before or after the -entire execution of the atomic operation. - -For the moment they're only valid in compute programs. +entire execution of the atomic operation. The resource may be a buffer +or an image. In the case of an image, the offset works the same as for +``LOAD`` and ``STORE``, specified above. These atomic operations may +only be used with 32-bit integer image formats. .. opcode:: ATOMUADD - Atomic integer addition Syntax: ``ATOMUADD dst, resource, offset, src`` - Example: ``ATOMUADD TEMP[0], RES[0], TEMP[1], TEMP[2]`` + Example: ``ATOMUADD TEMP[0], BUFFER[0], TEMP[1], TEMP[2]`` - The following operation is performed atomically on each component: + The following operation is performed atomically: .. math:: - dst_i = resource[offset]_i + dst_x = resource[offset] - resource[offset]_i = dst_i + src_i + resource[offset] = dst_x + src_x .. opcode:: ATOMXCHG - Atomic exchange Syntax: ``ATOMXCHG dst, resource, offset, src`` - Example: ``ATOMXCHG TEMP[0], RES[0], TEMP[1], TEMP[2]`` + Example: ``ATOMXCHG TEMP[0], BUFFER[0], TEMP[1], TEMP[2]`` - The following operation is performed atomically on each component: + The following operation is performed atomically: .. math:: - dst_i = resource[offset]_i + dst_x = resource[offset] - resource[offset]_i = src_i + resource[offset] = src_x .. opcode:: ATOMCAS - Atomic compare-and-exchange Syntax: ``ATOMCAS dst, resource, offset, cmp, src`` - Example: ``ATOMCAS TEMP[0], RES[0], TEMP[1], TEMP[2], TEMP[3]`` + Example: ``ATOMCAS TEMP[0], BUFFER[0], TEMP[1], TEMP[2], TEMP[3]`` - The following operation is performed atomically on each component: + The following operation is performed atomically: .. math:: - dst_i = resource[offset]_i + dst_x = resource[offset] - resource[offset]_i = (dst_i == cmp_i ? src_i : dst_i) + resource[offset] = (dst_x == cmp_x ? src_x : dst_x) .. opcode:: ATOMAND - Atomic bitwise And Syntax: ``ATOMAND dst, resource, offset, src`` - Example: ``ATOMAND TEMP[0], RES[0], TEMP[1], TEMP[2]`` + Example: ``ATOMAND TEMP[0], BUFFER[0], TEMP[1], TEMP[2]`` - The following operation is performed atomically on each component: + The following operation is performed atomically: .. math:: - dst_i = resource[offset]_i + dst_x = resource[offset] - resource[offset]_i = dst_i \& src_i + resource[offset] = dst_x \& src_x .. opcode:: ATOMOR - Atomic bitwise Or Syntax: ``ATOMOR dst, resource, offset, src`` - Example: ``ATOMOR TEMP[0], RES[0], TEMP[1], TEMP[2]`` + Example: ``ATOMOR TEMP[0], BUFFER[0], TEMP[1], TEMP[2]`` - The following operation is performed atomically on each component: + The following operation is performed atomically: .. math:: - dst_i = resource[offset]_i + dst_x = resource[offset] - resource[offset]_i = dst_i | src_i + resource[offset] = dst_x | src_x .. opcode:: ATOMXOR - Atomic bitwise Xor Syntax: ``ATOMXOR dst, resource, offset, src`` - Example: ``ATOMXOR TEMP[0], RES[0], TEMP[1], TEMP[2]`` + Example: ``ATOMXOR TEMP[0], BUFFER[0], TEMP[1], TEMP[2]`` - The following operation is performed atomically on each component: + The following operation is performed atomically: .. math:: - ds
Re: [Mesa-dev] [PATCH 1/2] st/dri: don't use _ctx in client_wait_sync
On 25 September 2015 at 23:49, Marek Olšák wrote:
> From: Marek Olšák
>
> Not needed and it can be NULL.
>
> Cc: 10.6 11.0
> ---
> src/gallium/state_trackers/dri/dri2.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/state_trackers/dri/dri2.c
> b/src/gallium/state_trackers/dri/dri2.c
> index 91b4431..ab940e4 100644
> --- a/src/gallium/state_trackers/dri/dri2.c
> +++ b/src/gallium/state_trackers/dri/dri2.c
> @@ -1293,6 +1293,7 @@ dri2_load_opencl_interop(struct dri_screen *screen)
> }
>
> struct dri2_fence {
> + struct dri_screen *driscreen;
> struct pipe_fence_handle *pipe_fence;
> void *cl_event;
> };
> @@ -1313,6 +1314,7 @@ dri2_create_fence(__DRIcontext *_ctx)
>return NULL;
> }
>
> + fence->driscreen = dri_screen(_ctx->driScreenPriv);
> return fence;
> }
>
> @@ -1360,9 +1362,9 @@ static GLboolean
> dri2_client_wait_sync(__DRIcontext *_ctx, void *_fence, unsigned flags,
>uint64_t timeout)
> {
> - struct dri_screen *driscreen = dri_screen(_ctx->driScreenPriv);
> - struct pipe_screen *screen = driscreen->base.screen;
> struct dri2_fence *fence = (struct dri2_fence*)_fence;
> + struct dri_screen *driscreen = fence->driscreen;
> + struct pipe_screen *screen = driscreen->base.screen;
>
> /* No need to flush. The context was flushed when the fence was created.
> */
>
> --
> 2.1.4
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
I think this is required (it is applied on top of your patch against mesa git):
diff --git a/src/gallium/state_trackers/dri/dri2.c
b/src/gallium/state_trackers/dri/dri2.c
index ab940e4..712203b 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -1338,6 +1338,7 @@ dri2_get_fence_from_cl_event(__DRIscreen
*_screen, intptr_t cl_event)
return NULL;
}
+ fence->driscreen = driscreen;
return fence;
}
otherwise
Reviewed-by: Albert Freeman
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Pending issues of lollipop-x86
Hi,
Marek's patches solved Camera and Youtube crashes on nouveau and radeonsi.
I'm available to test on i965, if needed
I think at this point the remaining major problem for lollipop-x86 is the
font artifacts/invisible chars on i965GM (X3100)
still present in mesa 11.0.0, I need to check with 11.0.1
Mauro
2015-09-25 23:03 GMT+02:00 Marek Olšák :
> Guys, can you please try these patches? They should fix it for gallium
> drivers (not i965).
>
> Marek
>
> On Fri, Sep 25, 2015 at 10:35 PM, Marek Olšák wrote:
> > On Fri, Sep 25, 2015 at 5:43 PM, Chih-Wei Huang
> wrote:
> >> CC to mesa-dev for help.
> >>
> >> 2015-09-25 22:12 GMT+08:00 Chih-Wei Huang :
> >>> 2015-09-25 16:21 GMT+08:00 Chih-Wei Huang :
> Actually I'm testing your mesa 11.0 branch
> to see if it is acceptable.
> The major issue I found is the
> Camera and Youtube crashing in mesa.
> >>>
> >>> OK, I can almost confirm this is a known issue
> >>> I reported to mesa devs before.
> >>> It is caused by this commit:
> >>>
> >>> commit c636284ee8ee95bb3f3ad31aaf26a9512ec5006c
> >>> Author: Chad Versace
> >>> Date: Tue May 5 19:05:32 2015 -0700
> >>>
> >>> i965/sync: Implement DRI2_Fence extension
> >>>
> >>> By reverting it the crashing is gone.
> >>>
> >>> However, I still hope we can find
> >>> a correct fix.
> >>
> >> After some debugging, it crashed in
> >> dri2_client_wait_sync() of
> >> ...src/egl/drivers/dri2/egl_dri2.c
> >> The ctx returned by _eglGetCurrentContext()
> >> is NULL.
> >>
> >> static EGLint
> >> dri2_client_wait_sync(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSync *sync,
> >> EGLint flags, EGLTime timeout)
> >> {
> >>_EGLContext *ctx = _eglGetCurrentContext();
> >>
> >> ==> ctx is NULL
> >>
> >>if (dri2_dpy->fence->client_wait_sync(dri2_ctx->dri_context, <==
> OOPS!
> >> dri2_sync->fence, wait_flags,
> >> timeout))
> >>
> >>
> >> Why does _eglGetCurrentContext() return NULL?
> >
> > Yes, we should fix this. A context isn't required here.
> >
> > Marek
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/miptree: Rename intel_miptree_map::mt -> ::linear_mt (v2)
Hi,
Am 25/09/2015 um 23:24 schrieb Chad Versace:
> Because that's what it is. It's an untiled, *linear* miptree.
>
> v2: - Add space after /*. - Use one comment per function argument.
> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 28
> ++-
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +- 2 files
> changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index
> 1259664..067276c 100644 ---
> a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2140,16
> +2140,18 @@ intel_miptree_map_blit(struct brw_context *brw, struct
> intel_miptree_map *map, unsigned int level, unsigned int slice) { -
> map->mt = intel_miptree_create(brw, GL_TEXTURE_2D, mt->format, -
> 0, 0, - map->w, map->h, 1, -
> 0, MIPTREE_LAYOUT_TILING_NONE); + map->linear_mt =
> intel_miptree_create(brw, GL_TEXTURE_2D, mt->format, +
> /* first_level */ 0, + /*
> last_level */ 0,
I am not sure about mesa, but the logical ordering is:
ARG, /* Comment */
Best wishes
Michael
> + map->w, map->h, 1, +
> /* samples */ 0, +
> MIPTREE_LAYOUT_TILING_NONE);
>
> - if (!map->mt) { + if (!map->linear_mt) { fprintf(stderr,
> "Failed to allocate blit temporary\n"); goto fail; } -
> map->stride = map->mt->pitch; + map->stride =
> map->linear_mt->pitch;
>
> /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT
> implies no * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original
> values read in unless @@ -2160,7 +2162,7 @@
> intel_miptree_map_blit(struct brw_context *brw, if
> (!intel_miptree_blit(brw, mt, level, slice, map->x, map->y, false,
> - map->mt, 0, 0, +
> map->linear_mt, 0, 0, 0, 0, false, map->w, map->h, GL_COPY)) {
> fprintf(stderr, "Failed to blit\n"); @@ -2168,7 +2170,7 @@
> intel_miptree_map_blit(struct brw_context *brw, } }
>
> - map->ptr = intel_miptree_map_raw(brw, map->mt); + map->ptr =
> intel_miptree_map_raw(brw, map->linear_mt);
>
> DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__,
> map->x, map->y, map->w, map->h, @@ -2178,7 +2180,7 @@
> intel_miptree_map_blit(struct brw_context *brw, return;
>
> fail: - intel_miptree_release(&map->mt); +
> intel_miptree_release(&map->linear_mt); map->ptr = NULL;
> map->stride = 0; } @@ -2192,11 +2194,11 @@
> intel_miptree_unmap_blit(struct brw_context *brw, { struct
> gl_context *ctx = &brw->ctx;
>
> - intel_miptree_unmap_raw(brw, map->mt); +
> intel_miptree_unmap_raw(brw, map->linear_mt);
>
> if (map->mode & GL_MAP_WRITE_BIT) { bool ok =
> intel_miptree_blit(brw, -
> map->mt, 0, 0, + map->linear_mt,
> 0, 0, 0, 0, false, mt, level, slice, map->x, map->y, false, @@
> -2204,7 +2206,7 @@ intel_miptree_unmap_blit(struct brw_context
> *brw, WARN_ONCE(!ok, "Failed to blit from linear temporary
> mapping"); }
>
> - intel_miptree_release(&map->mt); +
> intel_miptree_release(&map->linear_mt); }
>
> /** @@ -2728,7 +2730,7 @@ intel_miptree_unmap(struct brw_context
> *brw, intel_miptree_unmap_etc(brw, mt, map, level, slice); } else
> if (mt->stencil_mt && !(map->mode & BRW_MAP_DIRECT_BIT)) {
> intel_miptree_unmap_depthstencil(brw, mt, map, level, slice); - }
> else if (map->mt) { + } else if (map->linear_mt) {
> intel_miptree_unmap_blit(brw, mt, map, level, slice); #if
> defined(USE_SSE41) } else if (map->buffer && cpu_has_sse4_1) { diff
> --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index
> 830ff07..9f5397f 100644 ---
> a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -84,7 +84,7 @@
> struct intel_miptree_map { /** Possibly malloced temporary buffer
> for the mapping. */ void *buffer; /** Possible pointer to a
> temporary linear miptree for the mapping. */ - struct
> intel_mipmap_tree *mt; + struct intel_mipmap_tree *linear_mt; /**
> Pointer to the start of (map_x, map_y) returned by the mapping. */
> void *ptr; /** Stride of the mapping. */
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 06/11] loader: use HAVE_LIBDRM instead of ! __NOT_HAVE_DRM_H
Sorry, been slammed and trying to catch up. I forget if I replied to this or
not, but if you're still waiting on me:
Reviewed-by: Jeremy Huddleston Sequoia
> On Jul 9, 2015, at 10:55, Ian Romanick wrote:
>
> I can't really speak to the Android.mk or SConscript changes, but the
> rest of this patch is
>
> Reviewed-by: Ian Romanick
>
> You might also see what Jeremy Huddleston Sequoia
> thinks, since most of this exists to support his platform. :)
>
> On 07/08/2015 10:07 AM, Emil Velikov wrote:
>> Double negatives in English language are normally avoided, plus the
>> former seems cleaner and more consistent.
>>
>> Signed-off-by: Emil Velikov
>> ---
>> src/loader/Android.mk | 6 ++
>> src/loader/Makefile.am | 5 +
>> src/loader/SConscript | 2 --
>> src/loader/loader.c| 8
>> src/loader/pci_id_driver_map.c | 2 +-
>> 5 files changed, 8 insertions(+), 15 deletions(-)
>>
>> diff --git a/src/loader/Android.mk b/src/loader/Android.mk
>> index 92d9fd2..8690565 100644
>> --- a/src/loader/Android.mk
>> +++ b/src/loader/Android.mk
>> @@ -33,10 +33,8 @@ include $(CLEAR_VARS)
>> LOCAL_SRC_FILES := \
>> $(LOADER_C_FILES)
>>
>> -# swrast only
>> -ifeq ($(MESA_GPU_DRIVERS),swrast)
>> -LOCAL_CFLAGS += -D__NOT_HAVE_DRM_H
>> -else
>> +ifneq ($(filter-out swrast,$(MESA_GPU_DRIVERS)),)
>> +LOCAL_CFLAGS += -DHAVE_LIBDRM
>> LOCAL_SHARED_LIBRARIES := libdrm
>> endif
>>
>> diff --git a/src/loader/Makefile.am b/src/loader/Makefile.am
>> index aef1bd6..5190f7f 100644
>> --- a/src/loader/Makefile.am
>> +++ b/src/loader/Makefile.am
>> @@ -48,10 +48,7 @@ libloader_la_CPPFLAGS += \
>>
>> endif
>>
>> -if !HAVE_LIBDRM
>> -libloader_la_CPPFLAGS += \
>> --D__NOT_HAVE_DRM_H
>> -else
>> +if HAVE_LIBDRM
>> libloader_la_CPPFLAGS += \
>> $(LIBDRM_CFLAGS)
>>
>> diff --git a/src/loader/SConscript b/src/loader/SConscript
>> index 16d1053..d98f11e 100644
>> --- a/src/loader/SConscript
>> +++ b/src/loader/SConscript
>> @@ -8,8 +8,6 @@ env.Prepend(CPPPATH = [
>> '#include'
>> ])
>>
>> -env.Append(CPPDEFINES = ['__NOT_HAVE_DRM_H'])
>> -
>> if env['udev']:
>> env.PkgUseModules('UDEV')
>> env.Append(CPPDEFINES = ['HAVE_LIBUDEV'])
>> diff --git a/src/loader/loader.c b/src/loader/loader.c
>> index 8780587..4ed0a1f 100644
>> --- a/src/loader/loader.c
>> +++ b/src/loader/loader.c
>> @@ -85,7 +85,7 @@
>> #endif
>> #include "loader.h"
>>
>> -#ifndef __NOT_HAVE_DRM_H
>> +#ifdef HAVE_LIBDRM
>> #include
>> #endif
>>
>> @@ -501,7 +501,7 @@ sysfs_get_pci_id_for_fd(int fd, int *vendor_id, int
>> *chip_id)
>> }
>> #endif
>>
>> -#if !defined(__NOT_HAVE_DRM_H)
>> +#if defined(HAVE_LIBDRM)
>> /* for i915 */
>> #include
>> /* for radeon */
>> @@ -584,7 +584,7 @@ loader_get_pci_id_for_fd(int fd, int *vendor_id, int
>> *chip_id)
>>if (sysfs_get_pci_id_for_fd(fd, vendor_id, chip_id))
>> return 1;
>> #endif
>> -#if !defined(__NOT_HAVE_DRM_H)
>> +#if HAVE_LIBDRM
>>if (drm_get_pci_id_for_fd(fd, vendor_id, chip_id))
>> return 1;
>> #endif
>> @@ -695,7 +695,7 @@ loader_get_driver_for_fd(int fd, unsigned driver_types)
>>
>>if (!loader_get_pci_id_for_fd(fd, &vendor_id, &chip_id)) {
>>
>> -#ifndef __NOT_HAVE_DRM_H
>> +#if HAVE_LIBDRM
>> /* fallback to drmGetVersion(): */
>> drmVersionPtr version = drmGetVersion(fd);
>>
>> diff --git a/src/loader/pci_id_driver_map.c b/src/loader/pci_id_driver_map.c
>> index cb6f705..3c4657f 100644
>> --- a/src/loader/pci_id_driver_map.c
>> +++ b/src/loader/pci_id_driver_map.c
>> @@ -23,7 +23,7 @@
>>
>> int is_nouveau_vieux(int fd);
>>
>> -#ifndef __NOT_HAVE_DRM_H
>> +#ifdef HAVE_LIBDRM
>>
>> #include
>> #include
>>
>
smime.p7s
Description: S/MIME cryptographic signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] mesa: Reduce libGL.so binary size by about 15%
Reviewing diffs of code that generates code is always ick. =(
This *looks* right to me, but has it been given a beating for correctness? If
not, let me know, and I'll give it a whirl when I have some cycles.
Reviewed-by: Jeremy Huddleston Sequoia
---
You're right that this used to be use in xserver as well, but that was removed
in:
commit e61e19959d9138d5b81b1f25b7aa3e257918170d
Author: Adam Jackson
Date: Tue Dec 3 13:45:43 2013 -0500
xquartz/glx: Convert to non-glapi dispatch
CGL doesn't have anything like glXGetProcAddress, and the old code just
called down to dlsym in any case. It's a little mind-warping since
dlopening a framework actually loads multiple dylibs, but that's just
how OSX rolls.
Signed-off-by: Adam Jackson
Reviewed-by: Jeremy Huddleston Sequoia
> On Sep 22, 2015, at 15:55, Ian Romanick wrote:
>
> On 09/17/2015 03:19 PM, Arlie Davis wrote:
>> Ok, here's v2 of the change, with the suggested edits.
>
> So... I think this code is fine, and I admire the effort. I have a
> couple concerns.
>
> 1. We have no way to test this, so it's quite possible something was broken.
>
> 2. This function is only used in the OSX builds. Jeremy is the
> maintainer for those builds, so I've added him to the CC list.
>
> For every non-OSX build, we should just stop linking
> src/mapi/glapi/glapi_gentable.c. I thought maybe the X sever used it,
> but I couldn't find any evidence of that.
>
> If this is still a viable route, I have a few suggestions of follow-on
> patches...
>
> I guess this patch is
>
> Reviewed-by: Ian Romanick
>
> but I really think we need to get Jeremy's approval before pushing it.
>
>> From 5f393faa058f453408dfc640eecae3fe6335dfed Mon Sep 17 00:00:00 2001
>> From: Arlie Davis
>> Date: Tue, 15 Sep 2015 09:58:34 -0700
>> Subject: [PATCH] This patch significantly reduces the size of the libGL.so
>> binary. It does not change the (externally visible) behavior of libGL.so at
>> all.
>>
>> gl_gentable.py generates a function, _glapi_create_table_from_handle.
>> This function allocates a large dispatch table, consisting of 1300 or so
>> function pointers, and fills this dispatch table by doing symbol lookups
>> on a given shared library. Previously, gl_gentable.py would generate a
>> single, very large _glapi_create_table_from_handle function, with a short
>> cluster of lines for each entry point (function). The idiom it generates
>> was a NULL check, a call to snprintf, a call to dlsym / GetProcAddress,
>> and then a store into the dispatch table. Since this function processes
>> a large number of entry points, this code is duplicated many times over.
>>
>> We can encode the same information much more compactly, by using a lookup
>> table. The previous total size of _glapi_create_table_from_handle on x64
>> was 125848 bytes. By using a lookup table, the size of
>> _glapi_create_table_from_handle (and the related lookup tables) is reduced
>> to 10840 bytes. In other words, this enormous function is reduced by 91%.
>> The size of the entire libGL.so binary (measured when stripped) itself drops
>> by 15%.
>>
>> So the purpose of this change is to reduce the binary size, which frees up
>> disk space, memory, etc.
>> ---
>> src/mapi/glapi/gen/gl_gentable.py | 57
>> ---
>> 1 file changed, 41 insertions(+), 16 deletions(-)
>>
>> diff --git a/src/mapi/glapi/gen/gl_gentable.py
>> b/src/mapi/glapi/gen/gl_gentable.py
>> index 1b3eb72..7cd475a 100644
>> --- a/src/mapi/glapi/gen/gl_gentable.py
>> +++ b/src/mapi/glapi/gen/gl_gentable.py
>> @@ -113,6 +113,9 @@ __glapi_gentable_set_remaining_noop(struct _glapi_table
>> *disp) {
>> dispatch[i] = p.v;
>> }
>>
>> +"""
>> +
>> +footer = """
>> struct _glapi_table *
>> _glapi_create_table_from_handle(void *handle, const char *symbol_prefix) {
>> struct _glapi_table *disp = calloc(_glapi_get_dispatch_table_size(),
>> sizeof(_glapi_proc));
>> @@ -123,27 +126,28 @@ _glapi_create_table_from_handle(void *handle, const
>> char *symbol_prefix) {
>>
>> if(symbol_prefix == NULL)
>> symbol_prefix = "";
>> -"""
>>
>> -footer = """
>> -__glapi_gentable_set_remaining_noop(disp);
>> -
>> -return disp;
>> -}
>> -"""
>> +/* Note: This code relies on _glapi_table_func_names being sorted by the
>> + * entry point index of each function.
>> + */
>> +for (int func_index = 0; func_index < GLAPI_TABLE_COUNT; ++func_index) {
>> +const char *name = _glapi_table_func_names[func_index];
>> +void ** procp = &((void **)disp)[func_index];
>>
>> -body_template = """
>> -if(!disp->%(name)s) {
>> -void ** procp = (void **) &disp->%(name)s;
>> -snprintf(symboln, sizeof(symboln), "%%s%(entry_point)s",
>> symbol_prefix);
>> +snprintf(symboln, sizeof(symboln), \"%s%s\", symbol_prefix, name);
>> #ifdef _WIN32
>> *procp = GetProcAddress(handle, symboln);
>> #else
>> *pro
[Mesa-dev] [Bug 92122] [bisected] Regression with Assault Android Cactus
https://bugs.freedesktop.org/show_bug.cgi?id=92122 --- Comment #2 from MWATTT --- This commit also breaks Cities: Skylines. The ground is not rendered. Tested with a AMD JUNIPER chip and LLVMpipe. -- You are receiving this mail because: You are the QA Contact for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallium/util: avoid unreferencing random memory on buffer alloc failure
Reviewed-by: Albert Freeman
On 27 September 2015 at 09:41, Albert Freeman wrote:
> On 27 September 2015 at 09:35, Ilia Mirkin wrote:
>> On Sat, Sep 26, 2015 at 7:29 PM, Albert Freeman
>> wrote:
>>> On 27 September 2015 at 03:46, Ilia Mirkin wrote:
Found by Coverity
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/util/u_blitter.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/util/u_blitter.c
b/src/gallium/auxiliary/util/u_blitter.c
index 2fbf69c..b7b1ece 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -2065,7 +2065,7 @@ void util_blitter_clear_buffer(struct
blitter_context *blitter,
struct blitter_context_priv *ctx = (struct
blitter_context_priv*)blitter;
struct pipe_context *pipe = ctx->base.pipe;
struct pipe_vertex_buffer vb = {0};
- struct pipe_stream_output_target *so_target;
+ struct pipe_stream_output_target *so_target = NULL;
unsigned offsets[PIPE_MAX_SO_BUFFERS] = {0};
assert(num_channels >= 1);
--
2.4.9
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>>> "so_target = pipe->create_stream_output_target(pipe, dst, offset,
>>> size);" unconditionally assigns to so_target before first use (unless
>>> I am reading something incorrectly).
>>>
>>
>>u_upload_data(ctx->upload, 0, num_channels*4, clear_value,
>> &vb.buffer_offset, &vb.buffer);
>>if (!vb.buffer)
>> goto out;
>> ...
>>so_target = pipe->create_stream_output_target(pipe, dst, offset, size);
>> ...
>> out:
>> ...
>>pipe_so_target_reference(&so_target, NULL);
>>
>> If the goto out is taken, then &so_target gets unreferenced. This is
>> done by (roughly speaking) freeing the pointer that gets passed in,
>> and then assigning it to NULL.
>>
>>> Perhaps all function pointers that don't get implemented by a driver
>>> should be zeroed? I am trying to think where this could be done (in
>>> the gallium drivers themselves? (although that doesn’t seem the ideal
>>> solution)). Perhaps in a function that is part of gallium itself
>>> (outside drivers/[state trackers]/etc) that gets called upon driver
>>> shared library load.
>>
>> Most things are calloc'd and are thus initialized to null. Not sure
>> what that has to do with this issue though.
>>
>> -ilia
> Sorry, I was referencing slightly outdated mesa git code (without the goto).
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallium/util: avoid unreferencing random memory on buffer alloc failure
On 27 September 2015 at 09:35, Ilia Mirkin wrote:
> On Sat, Sep 26, 2015 at 7:29 PM, Albert Freeman
> wrote:
>> On 27 September 2015 at 03:46, Ilia Mirkin wrote:
>>> Found by Coverity
>>>
>>> Signed-off-by: Ilia Mirkin
>>> ---
>>> src/gallium/auxiliary/util/u_blitter.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/src/gallium/auxiliary/util/u_blitter.c
>>> b/src/gallium/auxiliary/util/u_blitter.c
>>> index 2fbf69c..b7b1ece 100644
>>> --- a/src/gallium/auxiliary/util/u_blitter.c
>>> +++ b/src/gallium/auxiliary/util/u_blitter.c
>>> @@ -2065,7 +2065,7 @@ void util_blitter_clear_buffer(struct blitter_context
>>> *blitter,
>>> struct blitter_context_priv *ctx = (struct
>>> blitter_context_priv*)blitter;
>>> struct pipe_context *pipe = ctx->base.pipe;
>>> struct pipe_vertex_buffer vb = {0};
>>> - struct pipe_stream_output_target *so_target;
>>> + struct pipe_stream_output_target *so_target = NULL;
>>> unsigned offsets[PIPE_MAX_SO_BUFFERS] = {0};
>>>
>>> assert(num_channels >= 1);
>>> --
>>> 2.4.9
>>>
>>> ___
>>> mesa-dev mailing list
>>> mesa-dev@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>> "so_target = pipe->create_stream_output_target(pipe, dst, offset,
>> size);" unconditionally assigns to so_target before first use (unless
>> I am reading something incorrectly).
>>
>
>u_upload_data(ctx->upload, 0, num_channels*4, clear_value,
> &vb.buffer_offset, &vb.buffer);
>if (!vb.buffer)
> goto out;
> ...
>so_target = pipe->create_stream_output_target(pipe, dst, offset, size);
> ...
> out:
> ...
>pipe_so_target_reference(&so_target, NULL);
>
> If the goto out is taken, then &so_target gets unreferenced. This is
> done by (roughly speaking) freeing the pointer that gets passed in,
> and then assigning it to NULL.
>
>> Perhaps all function pointers that don't get implemented by a driver
>> should be zeroed? I am trying to think where this could be done (in
>> the gallium drivers themselves? (although that doesn’t seem the ideal
>> solution)). Perhaps in a function that is part of gallium itself
>> (outside drivers/[state trackers]/etc) that gets called upon driver
>> shared library load.
>
> Most things are calloc'd and are thus initialized to null. Not sure
> what that has to do with this issue though.
>
> -ilia
Sorry, I was referencing slightly outdated mesa git code (without the goto).
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallium/util: avoid unreferencing random memory on buffer alloc failure
On Sat, Sep 26, 2015 at 7:29 PM, Albert Freeman
wrote:
> On 27 September 2015 at 03:46, Ilia Mirkin wrote:
>> Found by Coverity
>>
>> Signed-off-by: Ilia Mirkin
>> ---
>> src/gallium/auxiliary/util/u_blitter.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/auxiliary/util/u_blitter.c
>> b/src/gallium/auxiliary/util/u_blitter.c
>> index 2fbf69c..b7b1ece 100644
>> --- a/src/gallium/auxiliary/util/u_blitter.c
>> +++ b/src/gallium/auxiliary/util/u_blitter.c
>> @@ -2065,7 +2065,7 @@ void util_blitter_clear_buffer(struct blitter_context
>> *blitter,
>> struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter;
>> struct pipe_context *pipe = ctx->base.pipe;
>> struct pipe_vertex_buffer vb = {0};
>> - struct pipe_stream_output_target *so_target;
>> + struct pipe_stream_output_target *so_target = NULL;
>> unsigned offsets[PIPE_MAX_SO_BUFFERS] = {0};
>>
>> assert(num_channels >= 1);
>> --
>> 2.4.9
>>
>> ___
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
> "so_target = pipe->create_stream_output_target(pipe, dst, offset,
> size);" unconditionally assigns to so_target before first use (unless
> I am reading something incorrectly).
>
u_upload_data(ctx->upload, 0, num_channels*4, clear_value,
&vb.buffer_offset, &vb.buffer);
if (!vb.buffer)
goto out;
...
so_target = pipe->create_stream_output_target(pipe, dst, offset, size);
...
out:
...
pipe_so_target_reference(&so_target, NULL);
If the goto out is taken, then &so_target gets unreferenced. This is
done by (roughly speaking) freeing the pointer that gets passed in,
and then assigning it to NULL.
> Perhaps all function pointers that don't get implemented by a driver
> should be zeroed? I am trying to think where this could be done (in
> the gallium drivers themselves? (although that doesn’t seem the ideal
> solution)). Perhaps in a function that is part of gallium itself
> (outside drivers/[state trackers]/etc) that gets called upon driver
> shared library load.
Most things are calloc'd and are thus initialized to null. Not sure
what that has to do with this issue though.
-ilia
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallium/util: avoid unreferencing random memory on buffer alloc failure
On 27 September 2015 at 03:46, Ilia Mirkin wrote:
> Found by Coverity
>
> Signed-off-by: Ilia Mirkin
> ---
> src/gallium/auxiliary/util/u_blitter.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/util/u_blitter.c
> b/src/gallium/auxiliary/util/u_blitter.c
> index 2fbf69c..b7b1ece 100644
> --- a/src/gallium/auxiliary/util/u_blitter.c
> +++ b/src/gallium/auxiliary/util/u_blitter.c
> @@ -2065,7 +2065,7 @@ void util_blitter_clear_buffer(struct blitter_context
> *blitter,
> struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter;
> struct pipe_context *pipe = ctx->base.pipe;
> struct pipe_vertex_buffer vb = {0};
> - struct pipe_stream_output_target *so_target;
> + struct pipe_stream_output_target *so_target = NULL;
> unsigned offsets[PIPE_MAX_SO_BUFFERS] = {0};
>
> assert(num_channels >= 1);
> --
> 2.4.9
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
"so_target = pipe->create_stream_output_target(pipe, dst, offset,
size);" unconditionally assigns to so_target before first use (unless
I am reading something incorrectly).
Perhaps all function pointers that don't get implemented by a driver
should be zeroed? I am trying to think where this could be done (in
the gallium drivers themselves? (although that doesn’t seem the ideal
solution)). Perhaps in a function that is part of gallium itself
(outside drivers/[state trackers]/etc) that gets called upon driver
shared library load.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] memoryBarrier + SSBO
On 27 September 2015 at 08:32, Albert Freeman wrote: > On 27 September 2015 at 08:30, Ilia Mirkin wrote: >> On Sat, Sep 26, 2015 at 6:12 PM, Albert Freeman >> wrote: >>> On 26 September 2015 at 03:32, Ilia Mirkin wrote: Hi Ian (and other spec experts), The ARB_ssbo spec mentions the following: OpenGL 4.0 (either core or compatibility profile) is required. ... Additionally, the shading language provides the memoryBarrier() function to control the relative order of memory accesses within individual shader invocations and provides various memory qualifiers controlling how the memory corresponding to individual variables is accessed. However the memoryBarrier() function only becomes available in GLSL 4.20 [along with the glMemoryBarrier() function that the spec also refers to] or with ARB_shader_image_load_store. Is the implication that such functionality should be auto-exposed in image-less drivers that support ssbo? Or that this functionality should just not exist unless images are supported? This is relevant to me as I plan on adding ssbo support to gallium before images. Also, is there really anything in there that would prevent this from being exposed on a GL 3.1 driver (I'm thinking of freedreno which doesn't support GS yet and is my initial target for this, since I can make atomics actually work on there, unlike NVIDIA where the damn things just won't budge without some magic yet-to-be-found make-it-work bit). Cheers, -ilia >>> >>> I think that is an error in the ARB_ssbo spec (as that spec also >>> mentions: "This extension is written against the OpenGL 4.2 >>> (Compatibility Profile) Specification."). I believe this occurred as >>> ARB_ssbo was adapted from NV_ssbo; NV_ssbo does not mention >>> MemoryBarrier (i.e. someone forgot to update the version when NV_ssbo >>> was enhanced for ARB). >> >> Many extension specs are like this though... written as a diff against >> OpenGL version X, but require OpenGL version Y, s.t. Y < X. >> >> What are you saying is the spec error, by the way? The minimum version >> requirement? Or the fact that the interaction isn't listed? >> >> -ilia > The minimum version requirement, it is GL 4.0 on NV_ssbo and wasen't > changed when that was "enhanced" (e.g. Memory Barrier stuff was added) > for ARB_ssbo. Actually, it could be either, probably better for the ARB to decide. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] memoryBarrier + SSBO
On 27 September 2015 at 08:30, Ilia Mirkin wrote: > On Sat, Sep 26, 2015 at 6:12 PM, Albert Freeman > wrote: >> On 26 September 2015 at 03:32, Ilia Mirkin wrote: >>> Hi Ian (and other spec experts), >>> >>> The ARB_ssbo spec mentions the following: >>> >>> OpenGL 4.0 (either core or compatibility profile) is required. >>> >>> ... >>> >>> Additionally, the shading language provides the memoryBarrier() function >>> to control the relative order of memory accesses within individual >>> shader >>> invocations and provides various memory qualifiers controlling how the >>> memory corresponding to individual variables is accessed. >>> >>> However the memoryBarrier() function only becomes available in GLSL >>> 4.20 [along with the glMemoryBarrier() function that the spec also >>> refers to] or with ARB_shader_image_load_store. >>> >>> Is the implication that such functionality should be auto-exposed in >>> image-less drivers that support ssbo? Or that this functionality >>> should just not exist unless images are supported? >>> >>> This is relevant to me as I plan on adding ssbo support to gallium >>> before images. Also, is there really anything in there that would >>> prevent this from being exposed on a GL 3.1 driver (I'm thinking of >>> freedreno which doesn't support GS yet and is my initial target for >>> this, since I can make atomics actually work on there, unlike NVIDIA >>> where the damn things just won't budge without some magic >>> yet-to-be-found make-it-work bit). >>> >>> Cheers, >>> >>> -ilia >> >> I think that is an error in the ARB_ssbo spec (as that spec also >> mentions: "This extension is written against the OpenGL 4.2 >> (Compatibility Profile) Specification."). I believe this occurred as >> ARB_ssbo was adapted from NV_ssbo; NV_ssbo does not mention >> MemoryBarrier (i.e. someone forgot to update the version when NV_ssbo >> was enhanced for ARB). > > Many extension specs are like this though... written as a diff against > OpenGL version X, but require OpenGL version Y, s.t. Y < X. > > What are you saying is the spec error, by the way? The minimum version > requirement? Or the fact that the interaction isn't listed? > > -ilia The minimum version requirement, it is GL 4.0 on NV_ssbo and wasen't changed when that was "enhanced" (e.g. Memory Barrier stuff was added) for ARB_ssbo. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] memoryBarrier + SSBO
On Sat, Sep 26, 2015 at 6:12 PM, Albert Freeman wrote: > On 26 September 2015 at 03:32, Ilia Mirkin wrote: >> Hi Ian (and other spec experts), >> >> The ARB_ssbo spec mentions the following: >> >> OpenGL 4.0 (either core or compatibility profile) is required. >> >> ... >> >> Additionally, the shading language provides the memoryBarrier() function >> to control the relative order of memory accesses within individual shader >> invocations and provides various memory qualifiers controlling how the >> memory corresponding to individual variables is accessed. >> >> However the memoryBarrier() function only becomes available in GLSL >> 4.20 [along with the glMemoryBarrier() function that the spec also >> refers to] or with ARB_shader_image_load_store. >> >> Is the implication that such functionality should be auto-exposed in >> image-less drivers that support ssbo? Or that this functionality >> should just not exist unless images are supported? >> >> This is relevant to me as I plan on adding ssbo support to gallium >> before images. Also, is there really anything in there that would >> prevent this from being exposed on a GL 3.1 driver (I'm thinking of >> freedreno which doesn't support GS yet and is my initial target for >> this, since I can make atomics actually work on there, unlike NVIDIA >> where the damn things just won't budge without some magic >> yet-to-be-found make-it-work bit). >> >> Cheers, >> >> -ilia > > I think that is an error in the ARB_ssbo spec (as that spec also > mentions: "This extension is written against the OpenGL 4.2 > (Compatibility Profile) Specification."). I believe this occurred as > ARB_ssbo was adapted from NV_ssbo; NV_ssbo does not mention > MemoryBarrier (i.e. someone forgot to update the version when NV_ssbo > was enhanced for ARB). Many extension specs are like this though... written as a diff against OpenGL version X, but require OpenGL version Y, s.t. Y < X. What are you saying is the spec error, by the way? The minimum version requirement? Or the fact that the interaction isn't listed? -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] memoryBarrier + SSBO
On 26 September 2015 at 03:32, Ilia Mirkin wrote: > Hi Ian (and other spec experts), > > The ARB_ssbo spec mentions the following: > > OpenGL 4.0 (either core or compatibility profile) is required. > > ... > > Additionally, the shading language provides the memoryBarrier() function > to control the relative order of memory accesses within individual shader > invocations and provides various memory qualifiers controlling how the > memory corresponding to individual variables is accessed. > > However the memoryBarrier() function only becomes available in GLSL > 4.20 [along with the glMemoryBarrier() function that the spec also > refers to] or with ARB_shader_image_load_store. > > Is the implication that such functionality should be auto-exposed in > image-less drivers that support ssbo? Or that this functionality > should just not exist unless images are supported? > > This is relevant to me as I plan on adding ssbo support to gallium > before images. Also, is there really anything in there that would > prevent this from being exposed on a GL 3.1 driver (I'm thinking of > freedreno which doesn't support GS yet and is my initial target for > this, since I can make atomics actually work on there, unlike NVIDIA > where the damn things just won't budge without some magic > yet-to-be-found make-it-work bit). > > Cheers, > > -ilia > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev I think that is an error in the ARB_ssbo spec (as that spec also mentions: "This extension is written against the OpenGL 4.2 (Compatibility Profile) Specification."). I believe this occurred as ARB_ssbo was adapted from NV_ssbo; NV_ssbo does not mention MemoryBarrier (i.e. someone forgot to update the version when NV_ssbo was enhanced for ARB). ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 92125] make check DispatchSanity_test.GL31_CORE regression
https://bugs.freedesktop.org/show_bug.cgi?id=92125 Vinson Lee changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #2 from Vinson Lee --- commit 511a86383b9d6490788a15cca2df791c6d63bfd7 Author: Samuel Iglesias Gonsalvez Date: Tue Sep 15 08:18:39 2015 +0200 main/tests: Enable glShaderStorageBlockBinding() check in dispatch_sanity test Signed-off-by: Samuel Iglesias Gonsalvez Reviewed-by: Matt Turner -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 14/24] i965: fix atomic buffer index for bindings other than 0
On Sat, Sep 26, 2015 at 5:17 PM, Timothy Arceri wrote: > > > On 27 September 2015 6:23:42 am AEST, Ilia Mirkin > wrote: >>On Thu, Sep 17, 2015 at 3:02 AM, Timothy Arceri >>wrote: >>> Since commit c0cd5b var->data.binding was being used as a replacement >>> for atomic buffer index, but they don't have to be the same value >>they >>> just happen to end up the same when binding is 0. >>> >>> Now that we store the atomic uniform location in var->data.location >>> we can use this to lookup the atomic buffer index in uniform storage. >> >>FWIW I ran into a similar problem when trying to implement atomic >>counters in gallium. I assume that this logic depends on some other >>bit from this patch series, since I don't see that we store the value >>in var->data.location in the upstream code? > > It wad added recently [1] as part of my struct indirect indexing fix. > > [1] http://cgit.freedesktop.org/mesa/mesa/tree/src/glsl/link_uniforms.cpp#n750 Oh, that's sneaky. It wasn't where I expected :) -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 14/24] i965: fix atomic buffer index for bindings other than 0
On 27 September 2015 6:23:42 am AEST, Ilia Mirkin wrote:
>On Thu, Sep 17, 2015 at 3:02 AM, Timothy Arceri
>wrote:
>> Since commit c0cd5b var->data.binding was being used as a replacement
>> for atomic buffer index, but they don't have to be the same value
>they
>> just happen to end up the same when binding is 0.
>>
>> Now that we store the atomic uniform location in var->data.location
>> we can use this to lookup the atomic buffer index in uniform storage.
>
>FWIW I ran into a similar problem when trying to implement atomic
>counters in gallium. I assume that this logic depends on some other
>bit from this patch series, since I don't see that we store the value
>in var->data.location in the upstream code?
It wad added recently [1] as part of my struct indirect indexing fix.
[1] http://cgit.freedesktop.org/mesa/mesa/tree/src/glsl/link_uniforms.cpp#n750
>
>>
>> For arrays of arrays the outer arrays have separate uniform locations
>> however they all share the same buffer so we can get the buffer index
>> using the base uniform location.
>>
>> Cc: Alejandro Piñeiro
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90175
>> ---
>> src/glsl/nir/glsl_to_nir.cpp | 2 --
>> src/glsl/nir/nir.h | 4 ++--
>> src/glsl/nir/nir_lower_atomics.c | 18
>--
>> src/mesa/drivers/dri/i965/brw_nir.c| 6 --
>> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 +-
>> 5 files changed, 19 insertions(+), 13 deletions(-)
>>
>> diff --git a/src/glsl/nir/glsl_to_nir.cpp
>b/src/glsl/nir/glsl_to_nir.cpp
>> index c13f953..6b2da89 100644
>> --- a/src/glsl/nir/glsl_to_nir.cpp
>> +++ b/src/glsl/nir/glsl_to_nir.cpp
>> @@ -330,8 +330,6 @@ nir_visitor::visit(ir_variable *ir)
>>
>> var->data.index = ir->data.index;
>> var->data.binding = ir->data.binding;
>> - /* XXX Get rid of buffer_index */
>> - var->data.atomic.buffer_index = ir->data.binding;
>> var->data.atomic.offset = ir->data.atomic.offset;
>> var->data.image.read_only = ir->data.image_read_only;
>> var->data.image.write_only = ir->data.image_write_only;
>> diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
>> index 3a19bd3..a974188 100644
>> --- a/src/glsl/nir/nir.h
>> +++ b/src/glsl/nir/nir.h
>> @@ -308,7 +308,6 @@ typedef struct {
>> * Location an atomic counter is stored at.
>> */
>>struct {
>> - unsigned buffer_index;
>> unsigned offset;
>>} atomic;
>>
>> @@ -1834,7 +1833,8 @@ void nir_lower_system_values(nir_shader
>*shader);
>> void nir_lower_tex_projector(nir_shader *shader);
>> void nir_lower_idiv(nir_shader *shader);
>>
>> -void nir_lower_atomics(nir_shader *shader);
>> +void nir_lower_atomics(nir_shader *shader,
>> + const struct gl_shader_program
>*shader_program);
>> void nir_lower_to_source_mods(nir_shader *shader);
>>
>> void nir_normalize_cubemap_coords(nir_shader *shader);
>> diff --git a/src/glsl/nir/nir_lower_atomics.c
>b/src/glsl/nir/nir_lower_atomics.c
>> index 46e1376..52e7675 100644
>> --- a/src/glsl/nir/nir_lower_atomics.c
>> +++ b/src/glsl/nir/nir_lower_atomics.c
>> @@ -25,6 +25,7 @@
>> *
>> */
>>
>> +#include "ir_uniform.h"
>> #include "nir.h"
>> #include "main/config.h"
>> #include
>> @@ -35,7 +36,8 @@
>> */
>>
>> static void
>> -lower_instr(nir_intrinsic_instr *instr, nir_function_impl *impl)
>> +lower_instr(nir_intrinsic_instr *instr,
>> +const struct gl_shader_program *shader_program)
>> {
>> nir_intrinsic_op op;
>> switch (instr->intrinsic) {
>> @@ -60,10 +62,11 @@ lower_instr(nir_intrinsic_instr *instr,
>nir_function_impl *impl)
>>return; /* atomics passed as function arguments can't be
>lowered */
>>
>> void *mem_ctx = ralloc_parent(instr);
>> + unsigned uniform_loc = instr->variables[0]->var->data.location;
>>
>> nir_intrinsic_instr *new_instr =
>nir_intrinsic_instr_create(mem_ctx, op);
>> new_instr->const_index[0] =
>> - (int) instr->variables[0]->var->data.atomic.buffer_index;
>> +
>shader_program->UniformStorage[uniform_loc].atomic_buffer_index;
>>
>> nir_load_const_instr *offset_const =
>nir_load_const_instr_create(mem_ctx, 1);
>> offset_const->value.u[0] =
>instr->variables[0]->var->data.atomic.offset;
>> @@ -128,22 +131,25 @@ lower_instr(nir_intrinsic_instr *instr,
>nir_function_impl *impl)
>> }
>>
>> static bool
>> -lower_block(nir_block *block, void *state)
>> +lower_block(nir_block *block, void *prog)
>> {
>> nir_foreach_instr_safe(block, instr) {
>>if (instr->type == nir_instr_type_intrinsic)
>> - lower_instr(nir_instr_as_intrinsic(instr), state);
>> + lower_instr(nir_instr_as_intrinsic(instr),
>> + (const struct gl_shader_program *) prog);
>> }
>>
>> return true;
>> }
>>
>> void
>> -nir_lower_atomics(nir_shader *shader)
>> +nir_lower_atomics(nir_shader *shader,
>> + const struct gl
Re: [Mesa-dev] [PATCH] mesa: don't leak interface_name
On 27 September 2015 3:39:22 am AEST, Ilia Mirkin wrote: >Found by Coverity > >Signed-off-by: Ilia Mirkin Reviewed-by: Timothy Arceri >--- > src/mesa/main/shader_query.cpp | 1 + > 1 file changed, 1 insertion(+) > >diff --git a/src/mesa/main/shader_query.cpp >b/src/mesa/main/shader_query.cpp >index 99d9e10..e020dce 100644 >--- a/src/mesa/main/shader_query.cpp >+++ b/src/mesa/main/shader_query.cpp >@@ -995,6 +995,7 @@ program_resource_top_level_array_stride(struct >gl_shader_program *shProg, > } >} > found_top_level_array_size: >+ free(interface_name); >free(var_name); >return array_stride; > } >-- >2.4.9 > >___ >mesa-dev mailing list >mesa-dev@lists.freedesktop.org >http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-stable] [PATCH] i965/fs: Fix hang on IVB and VLV with image format mismatch.
Emil Velikov writes:
> Hi Francisco,
>
> On 9 September 2015 at 18:04, Ian Romanick wrote:
>> On 09/09/2015 05:30 AM, Francisco Jerez wrote:
>>> Ian Romanick writes:
>>>
On 09/03/2015 06:03 AM, Francisco Jerez wrote:
> IVB and VLV hang sporadically when an untyped surface read or write
> message is used to access a surface of format other than RAW, as may
> happen when there is a mismatch between the format qualifier of the
> image uniform and the format of the actual image bound to the
> pipeline. According to the spec this condition gives undefined
> results but may not lead to program termination (which is one of the
> possible outcomes of the hang). Fix it by checking at runtime whether
> the surface is of the right type.
>
> Fixes the "arb_shader_image_load_store.invalid/format mismatch" piglit
> subtest.
>
> Reported-by: Mark Janes
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91718
> CC: mesa-sta...@lists.freedesktop.org
> ---
> .../drivers/dri/i965/brw_fs_surface_builder.cpp| 42
> +++---
> 1 file changed, 38 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
> index f60afc9..57ce87f 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
> @@ -313,12 +313,42 @@ namespace {
>
> namespace image_validity {
>/**
> + * Check whether the bound image is suitable for untyped access.
> + */
> + brw_predicate
> + emit_untyped_image_check(const fs_builder &bld, const fs_reg
> &image,
> + brw_predicate pred)
> + {
> + const brw_device_info *devinfo = bld.shader->devinfo;
> + const fs_reg stride = offset(image, bld,
> BRW_IMAGE_PARAM_STRIDE_OFFSET);
> +
> + if (devinfo->gen == 7 && !devinfo->is_haswell) {
> +/* Check whether the first stride component (i.e. the Bpp
> value)
> + * is greater than four, what on Gen7 indicates that a
> surface of
> + * type RAW has been bound for untyped access. Reading or
> writing
> + * to a surface of type other than RAW using untyped surface
> + * messages causes a hang on IVB and VLV.
> + */
> +set_predicate(pred,
> + bld.CMP(bld.null_reg_ud(), stride, fs_reg(4),
> + BRW_CONDITIONAL_G));
> +
> +return BRW_PREDICATE_NORMAL;
> + } else {
> +/* More recent generations handle the format mismatch
> + * gracefully.
> + */
> +return pred;
> + }
> + }
> +
> + /**
> * Check whether there is an image bound at the given index and
> write
> * the comparison result to f0.0. Returns an appropriate
> predication
> * mode to use on subsequent image operations.
> */
>brw_predicate
> - emit_surface_check(const fs_builder &bld, const fs_reg &image)
> + emit_typed_atomic_check(const fs_builder &bld, const fs_reg &image)
This change seems spurious (and also reasonable).
>>> The problem is that this patch introduces a new kind of surface check
>>> applicable to untyped surface reads and writes only, so it would have
>>> been confusing to keep the other surface check which is applicable to
>>> atomics only with its previous rather unspecific name.
>>>
>{
> const brw_device_info *devinfo = bld.shader->devinfo;
> const fs_reg size = offset(image, bld,
> BRW_IMAGE_PARAM_SIZE_OFFSET);
> @@ -895,7 +925,9 @@ namespace brw {
> * surface read on the result,
> */
> const brw_predicate pred =
> - emit_bounds_check(bld, image, saddr, dims);
> + emit_untyped_image_check(bld, image,
> +emit_bounds_check(bld, image,
> + saddr, dims));
These appear to be the only two users of emit_bounds_check... shouldn't
the bounds still be tested?
>>> Yes, they are still.
>>
>> Ah... I completely missed that emit_bounds_check was moved into a
>> parameter of the call to emit_untyped_image_check.
>>
>> Reviewed-by: Ian Romanick
>>
> Considering Ian's r-b, are there any obstacles why this hasn't landed
> in master yet ?
>
Nope, sorry, I've been on vacation and with intermittent connectivity
since it was reviewed, I'll push the patch on Monday if no-one beats me
to it.
> Tha
Re: [Mesa-dev] [PATCH] i965: Don't tell the hardware about our UAV access.
Emil Velikov writes: > Hi all, > > On 10 September 2015 at 00:30, Mark Janes wrote: >> Mark Janes writes: >> >>> Francisco Jerez writes: >>> Mark Janes writes: > When I tested this, I saw an intermittent BSW gpu hang. I haven't been > able to confirm that it is due to the host-mem-barrier test. > It would probably be useful to know if the hang is due to any of the image load/store tests or if it's something unrelated. >>> >>> Yes, you are right. I will take some time tomorrow to catch the >>> specific test. Given the low rate of gpu hangs on BSW lately, I expect >>> it will be due to image load/store tests. However I need to confirm it. >> >> I spent time attempting to reproduce hangs with this patch on BSW today. >> I forced 3 hangs, but none of them could be attributed to image >> load/store tests. >> > With the above said, should we consider this as inconclusive fix ? If > so, what is the plan going forward - is this going to the bin or we'll > beat it into shape and merge it ? > Heh... The above means that there is an outstanding hang bug on BSW, but it's unrelated to the problem addressed by this patch (or ARB_shader_image_load_store at any rate). This patch fixes a GPU hang on both BDW and BSW and I recommend it's included in the next stable release. > Thanks > Emil signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 14/24] i965: fix atomic buffer index for bindings other than 0
On Thu, Sep 17, 2015 at 3:02 AM, Timothy Arceri wrote:
> Since commit c0cd5b var->data.binding was being used as a replacement
> for atomic buffer index, but they don't have to be the same value they
> just happen to end up the same when binding is 0.
>
> Now that we store the atomic uniform location in var->data.location
> we can use this to lookup the atomic buffer index in uniform storage.
FWIW I ran into a similar problem when trying to implement atomic
counters in gallium. I assume that this logic depends on some other
bit from this patch series, since I don't see that we store the value
in var->data.location in the upstream code?
>
> For arrays of arrays the outer arrays have separate uniform locations
> however they all share the same buffer so we can get the buffer index
> using the base uniform location.
>
> Cc: Alejandro Piñeiro
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90175
> ---
> src/glsl/nir/glsl_to_nir.cpp | 2 --
> src/glsl/nir/nir.h | 4 ++--
> src/glsl/nir/nir_lower_atomics.c | 18 --
> src/mesa/drivers/dri/i965/brw_nir.c| 6 --
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 +-
> 5 files changed, 19 insertions(+), 13 deletions(-)
>
> diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
> index c13f953..6b2da89 100644
> --- a/src/glsl/nir/glsl_to_nir.cpp
> +++ b/src/glsl/nir/glsl_to_nir.cpp
> @@ -330,8 +330,6 @@ nir_visitor::visit(ir_variable *ir)
>
> var->data.index = ir->data.index;
> var->data.binding = ir->data.binding;
> - /* XXX Get rid of buffer_index */
> - var->data.atomic.buffer_index = ir->data.binding;
> var->data.atomic.offset = ir->data.atomic.offset;
> var->data.image.read_only = ir->data.image_read_only;
> var->data.image.write_only = ir->data.image_write_only;
> diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
> index 3a19bd3..a974188 100644
> --- a/src/glsl/nir/nir.h
> +++ b/src/glsl/nir/nir.h
> @@ -308,7 +308,6 @@ typedef struct {
> * Location an atomic counter is stored at.
> */
>struct {
> - unsigned buffer_index;
> unsigned offset;
>} atomic;
>
> @@ -1834,7 +1833,8 @@ void nir_lower_system_values(nir_shader *shader);
> void nir_lower_tex_projector(nir_shader *shader);
> void nir_lower_idiv(nir_shader *shader);
>
> -void nir_lower_atomics(nir_shader *shader);
> +void nir_lower_atomics(nir_shader *shader,
> + const struct gl_shader_program *shader_program);
> void nir_lower_to_source_mods(nir_shader *shader);
>
> void nir_normalize_cubemap_coords(nir_shader *shader);
> diff --git a/src/glsl/nir/nir_lower_atomics.c
> b/src/glsl/nir/nir_lower_atomics.c
> index 46e1376..52e7675 100644
> --- a/src/glsl/nir/nir_lower_atomics.c
> +++ b/src/glsl/nir/nir_lower_atomics.c
> @@ -25,6 +25,7 @@
> *
> */
>
> +#include "ir_uniform.h"
> #include "nir.h"
> #include "main/config.h"
> #include
> @@ -35,7 +36,8 @@
> */
>
> static void
> -lower_instr(nir_intrinsic_instr *instr, nir_function_impl *impl)
> +lower_instr(nir_intrinsic_instr *instr,
> +const struct gl_shader_program *shader_program)
> {
> nir_intrinsic_op op;
> switch (instr->intrinsic) {
> @@ -60,10 +62,11 @@ lower_instr(nir_intrinsic_instr *instr, nir_function_impl
> *impl)
>return; /* atomics passed as function arguments can't be lowered */
>
> void *mem_ctx = ralloc_parent(instr);
> + unsigned uniform_loc = instr->variables[0]->var->data.location;
>
> nir_intrinsic_instr *new_instr = nir_intrinsic_instr_create(mem_ctx, op);
> new_instr->const_index[0] =
> - (int) instr->variables[0]->var->data.atomic.buffer_index;
> + shader_program->UniformStorage[uniform_loc].atomic_buffer_index;
>
> nir_load_const_instr *offset_const = nir_load_const_instr_create(mem_ctx,
> 1);
> offset_const->value.u[0] = instr->variables[0]->var->data.atomic.offset;
> @@ -128,22 +131,25 @@ lower_instr(nir_intrinsic_instr *instr,
> nir_function_impl *impl)
> }
>
> static bool
> -lower_block(nir_block *block, void *state)
> +lower_block(nir_block *block, void *prog)
> {
> nir_foreach_instr_safe(block, instr) {
>if (instr->type == nir_instr_type_intrinsic)
> - lower_instr(nir_instr_as_intrinsic(instr), state);
> + lower_instr(nir_instr_as_intrinsic(instr),
> + (const struct gl_shader_program *) prog);
> }
>
> return true;
> }
>
> void
> -nir_lower_atomics(nir_shader *shader)
> +nir_lower_atomics(nir_shader *shader,
> + const struct gl_shader_program *shader_program)
> {
> nir_foreach_overload(shader, overload) {
>if (overload->impl) {
> - nir_foreach_block(overload->impl, lower_block, overload->impl);
> + nir_foreach_block(overload->impl, lower_block,
> + (void *) shader_program);
> nir_metadata_pr
[Mesa-dev] [PATCH 2/2] egl: Fix missing Haiku include path
--- src/egl/SConscript |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/egl/SConscript b/src/egl/SConscript index f8102db..8f8b11a 100644 --- a/src/egl/SConscript +++ b/src/egl/SConscript @@ -8,6 +8,7 @@ env = env.Clone() env.Append(CPPPATH = [ '#/include', +'#/include/HaikuGL', '#/src/egl/main', '#/src', ]) -- 1.7.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] state_trackers/hgl: Fix missing include path
--- src/gallium/state_trackers/hgl/SConscript |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/gallium/state_trackers/hgl/SConscript b/src/gallium/state_trackers/hgl/SConscript index 82a0ce0..d2389c8 100644 --- a/src/gallium/state_trackers/hgl/SConscript +++ b/src/gallium/state_trackers/hgl/SConscript @@ -9,6 +9,7 @@ env.Append(CPPPATH = [ '#/src', '#/src/mapi', '#/src/mesa', +'#/include/HaikuGL', ]) sources = [ -- 1.7.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] gallium/util: avoid unreferencing random memory on buffer alloc failure
Found by Coverity
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/util/u_blitter.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/util/u_blitter.c
b/src/gallium/auxiliary/util/u_blitter.c
index 2fbf69c..b7b1ece 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -2065,7 +2065,7 @@ void util_blitter_clear_buffer(struct blitter_context
*blitter,
struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter;
struct pipe_context *pipe = ctx->base.pipe;
struct pipe_vertex_buffer vb = {0};
- struct pipe_stream_output_target *so_target;
+ struct pipe_stream_output_target *so_target = NULL;
unsigned offsets[PIPE_MAX_SO_BUFFERS] = {0};
assert(num_channels >= 1);
--
2.4.9
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] Returning 0 from std430_base_alignment
Hi Samuel, Coverity is up in a tizzy because std430_base_alignment can return 0 (which in turn would cause tons of errors since it's used with glsl_align). Is there a better starting value that can be used for its is_record() case? For std140 it's 16... I assume for std430 it's 4 or something? That would allow Coverity to conclude that 0 will never be returned from the function... as-is an empty struct would get an alignment of 0 and create lots of div-by-zero. Not sure if that's a legit scenario though. Alternatively, an assert(base_alignment > 0) will most likely appease it. -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: don't leak interface_name
Found by Coverity Signed-off-by: Ilia Mirkin --- src/mesa/main/shader_query.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp index 99d9e10..e020dce 100644 --- a/src/mesa/main/shader_query.cpp +++ b/src/mesa/main/shader_query.cpp @@ -995,6 +995,7 @@ program_resource_top_level_array_stride(struct gl_shader_program *shProg, } } found_top_level_array_size: + free(interface_name); free(var_name); return array_stride; } -- 2.4.9 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/6] main/tests: Enable glShaderStorageBlockBinding() check in dispatch_sanity test
On 25/09/15 18:45, Matt Turner wrote: > Reviewed-by: Matt Turner > > Please commit this one as soon as possible. > Pushed. Thanks, Sam ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] Mesa 11.0.1
Mesa 11.0.1 is now available. With this release we have mostly nouveau and i965 fixes, although there is the odd llvmpipe (big endian) and gbm bugfix. Antia Puentes (2): i965/vec4: Fix saturation errors when coalescing registers i965/vec4_nir: Load constants as integers Anuj Phogat (1): meta: Abort meta pbo path if TexSubImage need signed unsigned conversion Emil Velikov (3): docs: add sha256 checksums for 11.0.0 Update version to 11.0.1 docs: add release notes for 11.0.1 Iago Toral Quiroga (1): mesa: Fix GL_FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE for default framebuffer. Ian Romanick (5): t_dd_dmatmp: Make "count" actually be the count t_dd_dmatmp: Clean up improper code formatting from previous patch t_dd_dmatmp: Use '& 3' instead of '% 4' everywhere t_dd_dmatmp: Pull out common 'count -= count & 3' code t_dd_dmatmp: Use addition instead of subtraction in loop bounds Ilia Mirkin (6): st/mesa: avoid integer overflows with buffers >= 512MB nv50, nvc0: fix max texture buffer size to 128M elements freedreno/a3xx: fix blending of L8 format nv50,nvc0: detect underlying resource changes and update tic nv50,nvc0: flush texture cache in presence of coherent bufs radeonsi: load fmask ptr relative to the resources array Jason Ekstrand (2): nir: Fix a bunch of ralloc parenting errors i965/vec4: Don't reswizzle hardware registers Jeremy Huddleston (1): configure.ac: Add support to enable read-only text segment on x86. Ray Strode (1): gbm: convert gbm bo format to fourcc format on dma-buf import Tapani Pälli (2): mesa: fix errors when reading depth with glReadPixels i965: fix textureGrad for cubemaps Ulrich Weigand (1): mesa: Fix texture compression on big-endian systems git tag: mesa-11.0.1 ftp://ftp.freedesktop.org/pub/mesa/11.0.1/mesa-11.0.1.tar.gz MD5: 7c4065b88206ab878f8ad8de620daf4b mesa-11.0.1.tar.gz SHA1: 28214092898e3abf9e6beff67f429cc6fc90feca mesa-11.0.1.tar.gz SHA256: 6dab262877e12c0546a0e2970c6835a0f217e6d4026ccecb3cd5dd733d1ce867 mesa-11.0.1.tar.gz PGP: ftp://ftp.freedesktop.org/pub/mesa/11.0.1/mesa-11.0.1.tar.gz.sig ftp://ftp.freedesktop.org/pub/mesa/11.0.1/mesa-11.0.1.tar.xz MD5: 52335bcd40be8e17e3af18d879d6a72f mesa-11.0.1.tar.xz SHA1: cd6334fcb6f9047155d22d13de70e1d78fdfef87 mesa-11.0.1.tar.xz SHA256: 43d0dfcd1f1e36f07f8228cd76d90175d3fc74c1ed25d7071794a100a98ef2a6 mesa-11.0.1.tar.xz PGP: ftp://ftp.freedesktop.org/pub/mesa/11.0.1/mesa-11.0.1.tar.xz.sig -- -Emil signature.asc Description: OpenPGP digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 91020] Mesa's demo / tools won't compile since EGL changes
https://bugs.freedesktop.org/show_bug.cgi?id=91020 Marek Olšák changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |DUPLICATE --- Comment #6 from Marek Olšák --- *** This bug has been marked as a duplicate of bug 91643 *** -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 91643] mesa-demos-8.2.0 (latest released version) fails to build against mesa-10.6.4-2.mga6.tainted.src.rpm
https://bugs.freedesktop.org/show_bug.cgi?id=91643 Marek Olšák changed: What|Removed |Added CC||m...@fireburn.co.uk --- Comment #8 from Marek Olšák --- *** Bug 91020 has been marked as a duplicate of this bug. *** -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 91643] mesa-demos-8.2.0 (latest released version) fails to build against mesa-10.6.4-2.mga6.tainted.src.rpm
https://bugs.freedesktop.org/show_bug.cgi?id=91643 Marek Olšák changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #7 from Marek Olšák --- Fixed by demos commit 74443c6ee79f3251f643ea05e94df58183e37d0d. Closing. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 91797] [r600g] Company of Heroes 2 crash when zooming on the map
https://bugs.freedesktop.org/show_bug.cgi?id=91797 --- Comment #2 from Marek Olšák --- Is it always reproducible? If yes, could you create an apitrace? -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 6/6] i965: Simplify handling of VUE map changes.
For the v2 series:
Reviewed-by: Chris Forbes
On Sat, Sep 12, 2015 at 6:58 PM, Kenneth Graunke
wrote:
> The old code was disasterously complex - spread across multiple atoms
> which may not even run, inspecting the dirty bits to try and decide
> whether it was necessary to do checks...storing VS information in
> brw_context...extra flagging...
>
> This code tripped me and Carl up very badly when working on the
> shader cache code. It's very fragile and hard to maintain.
>
> Now that geometry shaders only depend on their inputs and don't have
> to worry about the VS VUE map, we can dramatically simplify this:
> just compute the VUE map coming out of the geometry shader stage
> in brw_upload_programs. If it changes, flag it. Done.
>
> v2: Also check vue_map.separable.
>
> Signed-off-by: Kenneth Graunke
> Reviewed-by: Chris Forbes [v1]
> ---
> src/mesa/drivers/dri/i965/brw_context.h | 12 +---
> src/mesa/drivers/dri/i965/brw_gs.c | 16 +---
> src/mesa/drivers/dri/i965/brw_state_upload.c | 16 +++-
> src/mesa/drivers/dri/i965/brw_vs.c | 15 ---
> 4 files changed, 17 insertions(+), 42 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h
> b/src/mesa/drivers/dri/i965/brw_context.h
> index 772a9fd..4cac30c 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -194,7 +194,6 @@ enum brw_state_id {
> BRW_STATE_GS_CONSTBUF,
> BRW_STATE_PROGRAM_CACHE,
> BRW_STATE_STATE_BASE_ADDRESS,
> - BRW_STATE_VUE_MAP_VS,
> BRW_STATE_VUE_MAP_GEOM_OUT,
> BRW_STATE_TRANSFORM_FEEDBACK,
> BRW_STATE_RASTERIZER_DISCARD,
> @@ -276,7 +275,6 @@ enum brw_state_id {
> #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
> #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
> #define BRW_NEW_STATE_BASE_ADDRESS (1ull <<
> BRW_STATE_STATE_BASE_ADDRESS)
> -#define BRW_NEW_VUE_MAP_VS (1ull << BRW_STATE_VUE_MAP_VS)
> #define BRW_NEW_VUE_MAP_GEOM_OUT(1ull <<
> BRW_STATE_VUE_MAP_GEOM_OUT)
> #define BRW_NEW_TRANSFORM_FEEDBACK (1ull <<
> BRW_STATE_TRANSFORM_FEEDBACK)
> #define BRW_NEW_RASTERIZER_DISCARD (1ull <<
> BRW_STATE_RASTERIZER_DISCARD)
> @@ -1375,16 +1373,8 @@ struct brw_context
> } curbe;
>
> /**
> -* Layout of vertex data exiting the vertex shader.
> -*
> -* BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
> -*/
> - struct brw_vue_map vue_map_vs;
> -
> - /**
> * Layout of vertex data exiting the geometry portion of the pipleine.
> -* This comes from the geometry shader if one exists, otherwise from
> the
> -* vertex shader.
> +* This comes from the last enabled shader stage (GS, DS, or VS).
> *
> * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
> */
> diff --git a/src/mesa/drivers/dri/i965/brw_gs.c
> b/src/mesa/drivers/dri/i965/brw_gs.c
> index 77be9d9..1f219c0 100644
> --- a/src/mesa/drivers/dri/i965/brw_gs.c
> +++ b/src/mesa/drivers/dri/i965/brw_gs.c
> @@ -297,8 +297,7 @@ brw_gs_state_dirty(struct brw_context *brw)
> return brw_state_dirty(brw,
>_NEW_TEXTURE,
>BRW_NEW_GEOMETRY_PROGRAM |
> - BRW_NEW_TRANSFORM_FEEDBACK |
> - BRW_NEW_VUE_MAP_VS);
> + BRW_NEW_TRANSFORM_FEEDBACK);
> }
>
> static void
> @@ -336,11 +335,6 @@ brw_upload_gs_prog(struct brw_context *brw)
>
> if (gp == NULL) {
>/* No geometry shader. Vertex data just passes straight through. */
> - if (brw->ctx.NewDriverState & BRW_NEW_VUE_MAP_VS) {
> - brw->vue_map_geom_out = brw->vue_map_vs;
> - brw->ctx.NewDriverState |= BRW_NEW_VUE_MAP_GEOM_OUT;
> - }
> -
>if (brw->gen == 6 &&
>(brw->ctx.NewDriverState & BRW_NEW_TRANSFORM_FEEDBACK)) {
> gen6_brw_upload_ff_gs_prog(brw);
> @@ -367,14 +361,6 @@ brw_upload_gs_prog(struct brw_context *brw)
>(void)success;
> }
> brw->gs.base.prog_data = &brw->gs.prog_data->base.base;
> -
> - if (brw->gs.prog_data->base.vue_map.slots_valid !=
> - brw->vue_map_geom_out.slots_valid ||
> - brw->gs.prog_data->base.vue_map.separate !=
> - brw->vue_map_geom_out.separate) {
> - brw->vue_map_geom_out = brw->gs.prog_data->base.vue_map;
> - brw->ctx.NewDriverState |= BRW_NEW_VUE_MAP_GEOM_OUT;
> - }
> }
>
> bool
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
> b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index 14627d5..89fde52 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -593,7 +593,6 @@ static struct dirty_bit_map brw_bits[] = {
> DEFINE_BIT(BRW_NEW_GS_CONSTBUF),
> DEFINE_BIT(BRW_NEW_PROGRAM_CACHE),
> DEFINE_BIT(BRW_NEW_STATE_BASE_ADDRESS),
> - DEFINE_BIT(BRW_NEW_VUE_MAP_VS),
Re: [Mesa-dev] [PATCH 2/6] mesa: rename gl_shader_program's NumUniformBlocks to NumUniformShaderStorageBlocks
On 2015-09-25 01:24:46, Samuel Iglesias Gonsalvez wrote:
> Because it counts shader storage blocks too.
>
> Signed-off-by: Samuel Iglesias Gonsalvez
> ---
> src/glsl/link_uniform_initializers.cpp | 2 +-
> src/glsl/link_uniforms.cpp | 4 ++--
> src/glsl/linker.cpp| 10 +-
> src/glsl/standalone_scaffolding.cpp| 2 +-
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 2 +-
> src/mesa/main/mtypes.h | 2 +-
> src/mesa/main/shaderapi.c | 2 +-
> src/mesa/main/shaderobj.c | 2 +-
> src/mesa/main/uniforms.c | 8
> 11 files changed, 25 insertions(+), 25 deletions(-)
>
> diff --git a/src/glsl/link_uniform_initializers.cpp
> b/src/glsl/link_uniform_initializers.cpp
> index 05000fc..f7fbcb0 100644
> --- a/src/glsl/link_uniform_initializers.cpp
> +++ b/src/glsl/link_uniform_initializers.cpp
> @@ -48,7 +48,7 @@ static unsigned
> get_uniform_block_index(const gl_shader_program *shProg,
> const char *uniformBlockName)
> {
> - for (unsigned i = 0; i < shProg->NumUniformBlocks; i++) {
> + for (unsigned i = 0; i < shProg->NumUniformShaderStorageBlocks; i++) {
Since UBO and SSBO both fall under the interface blocks category, what
about NumBufferInterfaceBlocks instead? 'Buffer' seems to distinguish
them from interstage interface blocks.
-Jordan
>if (!strcmp(shProg->UniformBlocks[i].Name, uniformBlockName))
> return i;
> }
> diff --git a/src/glsl/link_uniforms.cpp b/src/glsl/link_uniforms.cpp
> index 1c901e2..7b6c6d6 100644
> --- a/src/glsl/link_uniforms.cpp
> +++ b/src/glsl/link_uniforms.cpp
> @@ -504,7 +504,7 @@ public:
> if (var->is_interface_instance() && var->type->is_array()) {
> unsigned l = strlen(var->get_interface_type()->name);
>
> -for (unsigned i = 0; i < prog->NumUniformBlocks; i++) {
> +for (unsigned i = 0; i < prog->NumUniformShaderStorageBlocks;
> i++) {
> if (strncmp(var->get_interface_type()->name,
> prog->UniformBlocks[i].Name,
> l) == 0
> @@ -514,7 +514,7 @@ public:
> }
> }
> } else {
> -for (unsigned i = 0; i < prog->NumUniformBlocks; i++) {
> +for (unsigned i = 0; i < prog->NumUniformShaderStorageBlocks;
> i++) {
> if (strcmp(var->get_interface_type()->name,
>prog->UniformBlocks[i].Name) == 0) {
>ubo_block_index = i;
> diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
> index 9d419ac..d6a62bf 100644
> --- a/src/glsl/linker.cpp
> +++ b/src/glsl/linker.cpp
> @@ -1187,7 +1187,7 @@ interstage_cross_validate_uniform_blocks(struct
> gl_shader_program *prog)
>for (unsigned int j = 0; j < sh->NumUniformBlocks; j++) {
> int index = link_cross_validate_uniform_block(prog,
>&prog->UniformBlocks,
> -
> &prog->NumUniformBlocks,
> +
> &prog->NumUniformShaderStorageBlocks,
>&sh->UniformBlocks[j]);
>
> if (index == -1) {
> @@ -2802,7 +2802,7 @@ check_resources(struct gl_context *ctx, struct
> gl_shader_program *prog)
> unsigned shader_blocks[MESA_SHADER_STAGES] = {0};
> unsigned total_shader_storage_blocks = 0;
>
> - for (unsigned i = 0; i < prog->NumUniformBlocks; i++) {
> + for (unsigned i = 0; i < prog->NumUniformShaderStorageBlocks; i++) {
>/* Don't check SSBOs for Uniform Block Size */
>if (!prog->UniformBlocks[i].IsShaderStorage &&
>prog->UniformBlocks[i].UniformBufferSize >
> ctx->Const.MaxUniformBlockSize) {
> @@ -2836,7 +2836,7 @@ check_resources(struct gl_context *ctx, struct
> gl_shader_program *prog)
>
>if (total_uniform_blocks > ctx->Const.MaxCombinedUniformBlocks) {
> linker_error(prog, "Too many combined uniform blocks (%d/%d)\n",
> - prog->NumUniformBlocks,
> + prog->NumUniformShaderStorageBlocks,
> ctx->Const.MaxCombinedUniformBlocks);
>} else {
> for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
> @@ -2939,7 +2939,7 @@ check_image_resources(struct gl_context *ctx, struct
> gl_shader_program *prog)
>
> total_image_units += sh->NumImages;
>
> - for (unsigned j = 0; j < prog->NumUniformBlocks; j++) {
> + for (unsigned j = 0; j < prog->NumUniformShaderStorageBlocks; j++) {
> int stage_index = prog->UniformBlockStageIndex[i][j];
> if (stage_index != -
