Re: [Mesa-dev] [PATCH 3/3] glsl: remove out of date comments from file header

[Timothy Arceri]

Ping. Are people ok with this historical text being removed?


On Thu, 2016-02-11 at 15:45 +1100, Timothy Arceri wrote:
> The bison/flex generated code hasn't been keeped in version control
> for a long time, and I doubt anyone is going to argue for putting
> all this validation in the parser.
> ---
>  src/compiler/glsl/ast_to_hir.cpp | 18 +-
>  1 file changed, 1 insertion(+), 17 deletions(-)
> 
> diff --git a/src/compiler/glsl/ast_to_hir.cpp
> b/src/compiler/glsl/ast_to_hir.cpp
> index b558589..fc0d448 100644
> --- a/src/compiler/glsl/ast_to_hir.cpp
> +++ b/src/compiler/glsl/ast_to_hir.cpp
> @@ -23,7 +23,7 @@
>  
>  /**
>   * \file ast_to_hir.c
> - * Convert abstract syntax to to high-level intermediate
> reprensentation (HIR).
> + * Convert abstract syntax to high-level intermediate
> reprensentation (HIR).
>   *
>   * During the conversion to HIR, the majority of the symantic
> checking is
>   * preformed on the program.  This includes:
> @@ -31,22 +31,6 @@
>   ** Symbol table management
>   ** Type checking
>   ** Function binding
> - *
> - * The majority of this work could be done during parsing, and the
> parser could
> - * probably generate HIR directly.  However, this results in
> frequent changes
> - * to the parser code.  Since we do not assume that every system
> this complier
> - * is built on will have Flex and Bison installed, we have to store
> the code
> - * generated by these tools in our version control system.  In other
> parts of
> - * the system we've seen problems where a parser was changed but the
> generated
> - * code was not committed, merge conflicts where created because two
> developers
> - * had slightly different versions of Bison installed, etc.
> - *
> - * I have also noticed that running Bison generated parsers in GDB
> is very
> - * irritating.  When you get a segfault on '$$ = $1->foo', you can't
> very
> - * well 'print $1' in GDB.
> - *
> - * As a result, my preference is to put as little C code as possible
> in the
> - * parser (and lexer) sources.
>   */
>  
>  #include "glsl_symbol_table.h"
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Re: [Mesa-dev] [PATCH] glsl: Add function parameters to the parser symbol table.

[Timothy Arceri]

On Fri, 2016-03-04 at 22:30 -0800, Kenneth Graunke wrote:
> In a shader such as:
> 
> struct S { float f; }
> float identity(float S) { return S; }
> 
> we would think that "S" in "return S" referred to a structure, even
> though it's shadowed by the "float S" parameter in the inner struct.
> 
> This led to the parser's grammar seeing TYPE_IDENTIFIER and getting
> confused.
> 
> Fixes dEQP-GLES2.functional.shaders.scoping.valid.
> function_parameter_hides_struct_type_{vertex,fragment}.
> 
> Signed-off-by: Kenneth Graunke 
> ---

Reviewed-by: Timothy Arceri 
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[Mesa-dev] [PATCH] mesa: Add GL_RED and GL_RG to ES3 effective internal format mapping.

[Kenneth Graunke]

The dEQP-GLES3.functional.fbo.completeness.renderable.texture.
{color0,depth,stencil}.{red,rg}_unsigned_byte tests appear to expect
GL_RED/GL_RG and GL_UNSIGNED_BYTE to map to GL_R8/GL_RG8, rather than
returning an INVALID_OPERATION error.

This makes perfect sense.  However, RED and RG are strangely missing
from the ES 3.0/3.1/3.2 spec's "Effective internal format corresponding
to external format and type" tables.  It may be worth filing a spec bug.

Fixes the 6 dEQP tests mentioned above.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/main/glformats.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index edfd7d6..cf64958 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -2603,6 +2603,10 @@ 
_mesa_es3_effective_internal_format_for_format_and_type(GLenum format,
  return GL_RGBA8;
   case GL_RGB:
  return GL_RGB8;
+  case GL_RG:
+ return GL_RG8;
+  case GL_RED:
+ return GL_R8;
   /* Although LUMINANCE_ALPHA, LUMINANCE and ALPHA appear in table 3.12,
* (section 3.8 Texturing, page 128 of the OpenGL-ES 3.0.4) as effective
* internal formats, they do not correspond to GL constants, so the base
-- 
2.7.2

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Re: [Mesa-dev] [PATCH] glsl: Add single declaration variables to the symbol table too.

[Timothy Arceri]

On Fri, 2016-03-04 at 21:11 -0800, Kenneth Graunke wrote:
> The lexer/parser use a symbol table to classify identifiers as
> variables, functions, or structure types.
> 
> For some reason, we neglected to add variables in simple declarations
> such as
> 
> int x = 5;
> 
> but did add subsequent variables in multi-declarations:
> 
> int x = 5, y = 6; // y gets added, but not x, for some reason
> 
> Fixes Piglit's spec/glsl-1.20/compiler/scoping-struct-vs-
> variable.vert.
> 
> Fixes four dEQP-GLES2.functional.shaders.scoping.valid subcases:
> - local_int_variable_hides_struct_type_vertex
> - local_int_variable_hides_struct_type_fragment
> - local_struct_variable_hides_struct_type_vertex
> - local_struct_variable_hides_struct_type_fragment
> 
> Signed-off-by: Kenneth Graunke 

Reviewed-by: Timothy Arceri 


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[Mesa-dev] [PATCH] glsl: Add function parameters to the parser symbol table.

[Kenneth Graunke]

In a shader such as:

struct S { float f; }
float identity(float S) { return S; }

we would think that "S" in "return S" referred to a structure, even
though it's shadowed by the "float S" parameter in the inner struct.

This led to the parser's grammar seeing TYPE_IDENTIFIER and getting
confused.

Fixes dEQP-GLES2.functional.shaders.scoping.valid.
function_parameter_hides_struct_type_{vertex,fragment}.

Signed-off-by: Kenneth Graunke 
---
 src/compiler/glsl/glsl_parser.yy | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index d69c48e..709d801 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -894,6 +894,7 @@ parameter_declarator:
   $$->type->set_location(@1);
   $$->type->specifier = $1;
   $$->identifier = $2;
+  state->symbols->add_variable(new(state) ir_variable(NULL, $2, 
ir_var_auto));
}
| type_specifier any_identifier array_specifier
{
@@ -905,6 +906,7 @@ parameter_declarator:
   $$->type->specifier = $1;
   $$->identifier = $2;
   $$->array_specifier = $3;
+  state->symbols->add_variable(new(state) ir_variable(NULL, $2, 
ir_var_auto));
}
;
 
-- 
2.7.2

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Re: [Mesa-dev] [PATCH v2 2/2] mesa: Change GLboolean to bool in GenerateMipmap target checker.

[Matt Turner]

Both are

Reviewed-by: Matt Turner 
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[Mesa-dev] [PATCH] glsl: Add single declaration variables to the symbol table too.

[Kenneth Graunke]

The lexer/parser use a symbol table to classify identifiers as
variables, functions, or structure types.

For some reason, we neglected to add variables in simple declarations
such as

int x = 5;

but did add subsequent variables in multi-declarations:

int x = 5, y = 6; // y gets added, but not x, for some reason

Fixes Piglit's spec/glsl-1.20/compiler/scoping-struct-vs-variable.vert.

Fixes four dEQP-GLES2.functional.shaders.scoping.valid subcases:
- local_int_variable_hides_struct_type_vertex
- local_int_variable_hides_struct_type_fragment
- local_struct_variable_hides_struct_type_vertex
- local_struct_variable_hides_struct_type_fragment

Signed-off-by: Kenneth Graunke 
---
 src/compiler/glsl/glsl_parser.yy | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index 99bd0e6..d69c48e 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -1062,6 +1062,7 @@ single_declaration:
   $$ = new(ctx) ast_declarator_list($1);
   $$->set_location_range(@1, @2);
   $$->declarations.push_tail(>link);
+  state->symbols->add_variable(new(state) ir_variable(NULL, $2, 
ir_var_auto));
}
| fully_specified_type any_identifier array_specifier
{
@@ -1072,6 +1073,7 @@ single_declaration:
   $$ = new(ctx) ast_declarator_list($1);
   $$->set_location_range(@1, @3);
   $$->declarations.push_tail(>link);
+  state->symbols->add_variable(new(state) ir_variable(NULL, $2, 
ir_var_auto));
}
| fully_specified_type any_identifier array_specifier '=' initializer
{
@@ -1082,6 +1084,7 @@ single_declaration:
   $$ = new(ctx) ast_declarator_list($1);
   $$->set_location_range(@1, @3);
   $$->declarations.push_tail(>link);
+  state->symbols->add_variable(new(state) ir_variable(NULL, $2, 
ir_var_auto));
}
| fully_specified_type any_identifier '=' initializer
{
@@ -1092,6 +1095,7 @@ single_declaration:
   $$ = new(ctx) ast_declarator_list($1);
   $$->set_location_range(@1, @2);
   $$->declarations.push_tail(>link);
+  state->symbols->add_variable(new(state) ir_variable(NULL, $2, 
ir_var_auto));
}
| INVARIANT variable_identifier
{
-- 
2.7.2

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[Mesa-dev] [PATCH v2 2/2] mesa: Change GLboolean to bool in GenerateMipmap target checker.

[Kenneth Graunke]

This is not API facing, so just use bool.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/main/genmipmap.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/main/genmipmap.c b/src/mesa/main/genmipmap.c
index 2a6..6eacd42 100644
--- a/src/mesa/main/genmipmap.c
+++ b/src/mesa/main/genmipmap.c
@@ -42,14 +42,14 @@ bool
 _mesa_is_valid_generate_texture_mipmap_target(struct gl_context *ctx,
   GLenum target)
 {
-   GLboolean error;
+   bool error;
 
switch (target) {
case GL_TEXTURE_1D:
   error = _mesa_is_gles(ctx);
   break;
case GL_TEXTURE_2D:
-  error = GL_FALSE;
+  error = false;
   break;
case GL_TEXTURE_3D:
   error = ctx->API == API_OPENGLES;
@@ -69,10 +69,10 @@ _mesa_is_valid_generate_texture_mipmap_target(struct 
gl_context *ctx,
   !ctx->Extensions.ARB_texture_cube_map_array;
   break;
default:
-  error = GL_TRUE;
+  error = true;
}
 
-   return (error != GL_TRUE);
+   return !error;
 }
 
 bool
-- 
2.7.2

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[Mesa-dev] [PATCH v2 1/2] mesa: Make GenerateMipmap check the target before finding an object.

[Kenneth Graunke]

If glGenerateMipmap was called with a bogus target, then it would
pass that to _mesa_get_current_tex_object(), which would raise a
_mesa_problem() telling people to file bugs.  We'd then do the
proper error checking, raise an error, and bail.

Doing the check first avoids the _mesa_problem().  The DSA variant
doesn't take a target parameter, so we leave the target validation
exactly as it was in that case.

Fixes one dEQP GLES2 test:
dEQP-GLES2.functional.negative_api.texture.generatemipmap.invalid_target.

v2: Rebase on Antia's recent patch to this area.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Brian Paul  [v1]
---
 src/mesa/main/genmipmap.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

Sorry for the resend - here's basically the same change, but it applies
on master now that ARB_internal_format_query2 has landed.

diff --git a/src/mesa/main/genmipmap.c b/src/mesa/main/genmipmap.c
index f9ef2d1..2a6 100644
--- a/src/mesa/main/genmipmap.c
+++ b/src/mesa/main/genmipmap.c
@@ -99,12 +99,6 @@ _mesa_generate_texture_mipmap(struct gl_context *ctx,
 
FLUSH_VERTICES(ctx, 0);
 
-   if (!_mesa_is_valid_generate_texture_mipmap_target(ctx, target)) {
-  _mesa_error(ctx, GL_INVALID_ENUM, "glGenerate%sMipmap(target=%s)",
-  suffix, _mesa_enum_to_string(target));
-  return;
-   }
-
if (texObj->BaseLevel >= texObj->MaxLevel) {
   /* nothing to do */
   return;
@@ -159,6 +153,12 @@ _mesa_GenerateMipmap(GLenum target)
struct gl_texture_object *texObj;
GET_CURRENT_CONTEXT(ctx);
 
+   if (!_mesa_is_valid_generate_texture_mipmap_target(ctx, target)) {
+  _mesa_error(ctx, GL_INVALID_ENUM, "glGenerateMipmap(target=%s)",
+  _mesa_enum_to_string(target));
+  return;
+   }
+
texObj = _mesa_get_current_tex_object(ctx, target);
if (!texObj)
   return;
@@ -179,5 +179,11 @@ _mesa_GenerateTextureMipmap(GLuint texture)
if (!texObj)
   return;
 
+   if (!_mesa_is_valid_generate_texture_mipmap_target(ctx, texObj->Target)) {
+  _mesa_error(ctx, GL_INVALID_ENUM, "glGenerateTextureMipmap(target=%s)",
+  _mesa_enum_to_string(texObj->Target));
+  return;
+   }
+
_mesa_generate_texture_mipmap(ctx, texObj, texObj->Target, true);
 }
-- 
2.7.2

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Re: [Mesa-dev] [PATCH 09/10] i965: Add and use is_scheduling_barrier() function.

[Francisco Jerez]

Matt Turner  writes:

> Though there is a lot of overlap with has_side_effects(), these do mean
> different things.

Can we do it the other way around and implement is_scheduling_barrier()
in terms of has_side_effects()?  has_side_effects() seems like the more
fundamental of the two and because is_scheduling_barrier() is specific
to the scheduler it would make more sense to keep it static inline in
brw_schedule_instructions.cpp for the sake of encapsulation.

AFAIUI is_scheduling_barrier() is merely a makeshift approximation at
missing memory dependency analysis, and in the long term is the wrong
question to ask (IMHO the right question is "does this instruction have
an execution dependency with respect to this other?", which implies that
either of the two instructions has some sort of side effect, but not the
converse).  has_side_effects() OTOH has a well-defined answer that can
be answered by looking at the semantics of the instruction alone,
independent from scheduling heuristics and surrounding compiler
infrastructure.

I think for the moment I'd make is_scheduling_barrier return true if the
instruction has side effects, except where you have the guarantee that
the side-effectful instruction won't have a (non-dataflow related)
execution dependency with any other instruction of the program, which is
currently only the case for non-EOT FB_WRITE -- Pretty much has Ken had
open-coded it in his scheduling changes except for the non-EOT part.

> ---
>  src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp |  6 ++
>  src/mesa/drivers/dri/i965/brw_shader.cpp| 12 +++-
>  src/mesa/drivers/dri/i965/brw_shader.h  |  2 ++
>  3 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp 
> b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> index 98fa5e3..67b713b 100644
> --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> @@ -917,9 +917,7 @@ fs_instruction_scheduler::calculate_deps()
> foreach_in_list(schedule_node, n, ) {
>fs_inst *inst = (fs_inst *)n->inst;
>  
> -  if (inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
> -  inst->is_control_flow() ||
> -  inst->has_side_effects())
> +  if (inst->is_scheduling_barrier() || inst->is_control_flow())
>   add_barrier_deps(n);
>  
>/* read-after-write deps. */
> @@ -1152,7 +1150,7 @@ vec4_instruction_scheduler::calculate_deps()
> foreach_in_list(schedule_node, n, ) {
>vec4_instruction *inst = (vec4_instruction *)n->inst;
>  
> -  if (inst->is_control_flow() || inst->has_side_effects())
> +  if (inst->is_scheduling_barrier() || inst->is_control_flow())
>   add_barrier_deps(n);
>  
>/* read-after-write deps. */
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
> b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index d007ed0..80673e5 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@ -879,7 +879,7 @@ backend_instruction::writes_accumulator_implicitly(const 
> struct brw_device_info
>  }
>  
>  bool
> -backend_instruction::has_side_effects() const
> +backend_instruction::is_scheduling_barrier() const
>  {
> switch (opcode) {
> case SHADER_OPCODE_UNTYPED_ATOMIC:
> @@ -896,6 +896,7 @@ backend_instruction::has_side_effects() const
> case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
> case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
> case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
> +   case FS_OPCODE_PLACEHOLDER_HALT:
> case FS_OPCODE_FB_WRITE:
> case SHADER_OPCODE_BARRIER:
> case TCS_OPCODE_URB_WRITE:
> @@ -907,6 +908,15 @@ backend_instruction::has_side_effects() const
>  }
>  
>  bool
> +backend_instruction::has_side_effects() const
> +{
> +   switch (opcode) {
> +   default:
> +  return is_scheduling_barrier();
> +   }
> +}
> +
> +bool
>  backend_instruction::is_volatile() const
>  {
> switch (opcode) {
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
> b/src/mesa/drivers/dri/i965/brw_shader.h
> index 82374a4..0ec2a84 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.h
> +++ b/src/mesa/drivers/dri/i965/brw_shader.h
> @@ -124,6 +124,8 @@ struct backend_instruction : public exec_node {
>  */
> bool has_side_effects() const;
>  
> +   bool is_scheduling_barrier() const;
> +
> /**
>  * True if the instruction might be affected by side effects of other
>  * instructions.
> -- 
> 2.4.10
>
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Re: [Mesa-dev] [vulkan] Fix AM_CPPFLAGS

[Sedat Dilek]

Thank you Jason for taking care and Aaron for testing /o\.

- Sedat -

On 3/2/16, Aaron Watry  wrote:
> On Wed, Mar 2, 2016 at 1:46 PM, Jason Ekstrand 
> wrote:
>
>> On Wed, Mar 2, 2016 at 9:03 AM, Sedat Dilek 
>> wrote:
>>
>>> Any news on that?
>>>
>>
>> Out-of-tree builds including make check should be working now.
>> --Jason
>>
>
> Confirmed.  I just did a pull/rebuild out of tree, and make check works
> again.
>
> --Aaron
>
>
>>
>>
>>>
>>> - Sedat -
>>>
>>> On 2/24/16, Aaron Watry  wrote:
>>> > To clarify, I've also been doing out-of-tree builds with make check
>>> > and
>>> a
>>> > vulkan build (on a haswell system, but I don't think that matters at
>>> build
>>> > time).
>>> >
>>> > On Tue, Feb 23, 2016 at 8:46 PM, Aaron Watry  wrote:
>>> >
>>> >> To expand on what Sedat said here, make check is broken when building
>>> anv
>>> >> at the moment. due to a combination of the genxml/isl/vulkan
>>> >> directory
>>> >> moves.
>>> >>
>>> >> I've been poking at it on one of my laptops over the last few days,
>>> but I
>>> >> wouldn't complain if someone beat me to a fix.
>>> >>
>>> >> --Aaron
>>> >>
>>> >> On Tue, Feb 23, 2016 at 9:01 AM, Sedat Dilek 
>>> >> wrote:
>>> >>
>>> >>> [ Low Internet bandwidth - no Git pulling possible ]
>>> >>>
>>> >>> Hi,
>>> >>>
>>> >>> From [1]...
>>> >>>
>>> >>> AM_CPPFLAGS = \
>>> >>> $(INTEL_CFLAGS) \
>>> >>> $(VALGRIND_CFLAGS) \
>>> >>> $(DEFINES) \
>>> >>> -I$(top_srcdir)/include \
>>> >>> -I$(top_srcdir)/src \
>>> >>> -I$(top_srcdir)/src/compiler \
>>> >>> -I$(top_srcdir)/src/mapi \
>>> >>> -I$(top_srcdir)/src/mesa \
>>> >>> -I$(top_srcdir)/src/mesa/drivers/dri/common \
>>> >>> -I$(top_srcdir)/src/mesa/drivers/dri/i965 \
>>> >>> -I$(top_srcdir)/src/gallium/auxiliary \
>>> >>> -I$(top_srcdir)/src/gallium/include \
>>> >>> -I$(top_srcdir)/src/intel/ \
>>> >>> -I$(top_builddir)/src \
>>> >>> -I$(top_builddir)/src/compiler \
>>> >>> -I$(top_builddir)/src/compiler/nir \
>>> >>> -I$(top_builddir)/src/intel \
>>> >>> -I$(top_builddir)/src/intel/genxml \
>>> >>> -I$(top_builddir)/src/vulkan <--- XXX: Should be
>>> >>> .../src/intel/vulkan
>>> ?
>>> >>>
>>> >>> See commit 9851c8285f7bf70a6cb4bede2ee94110c14acc19 ("Move the intel
>>> >>> vulkan driver to src/intel/vulkan")
>>> >>>
>>> >>> - Sedat -
>>> >>>
>>> >>> [1]
>>> >>>
>>> https://cgit.freedesktop.org/mesa/mesa/tree/src/intel/vulkan/Makefile.am?h=vulkan#n70
>>> >>> [2]
>>> >>>
>>> https://cgit.freedesktop.org/mesa/mesa/commit/?h=vulkan=9851c8285f7bf70a6cb4bede2ee94110c14acc19
>>> >>> ___
>>> >>> mesa-dev mailing list
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>>> >>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>>> >>>
>>> >>
>>> >>
>>> >
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[Mesa-dev] [PATCH 08/10] i965: Remove NOP insertion kludge in scheduler.

[Matt Turner]

Instead of removing every instruction in add_insts_from_block(), just
move the instruction to its scheduled location. This is a step towards
doing both bottom-up and top-down scheduling without conflicts.

Note that this patch changes cycle counts for programs because it begins
including control flow instructions in the estimates.
---
 .../drivers/dri/i965/brw_schedule_instructions.cpp | 25 +-
 1 file changed, 5 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp 
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 46b45a5..98fa5e3 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -783,26 +783,13 @@ schedule_node::schedule_node(backend_instruction *inst,
 void
 instruction_scheduler::add_insts_from_block(bblock_t *block)
 {
-   /* Removing the last instruction from a basic block removes the block as
-* well, so put a NOP at the end to keep it alive.
-*/
-   if (!block->end()->is_control_flow()) {
-  backend_instruction *nop = new(mem_ctx) backend_instruction();
-  nop->opcode = BRW_OPCODE_NOP;
-  block->end()->insert_after(block, nop);
-   }
-
-   foreach_inst_in_block_safe(backend_instruction, inst, block) {
-  if (inst->opcode == BRW_OPCODE_NOP || inst->is_control_flow())
- continue;
-
+   foreach_inst_in_block(backend_instruction, inst, block) {
   schedule_node *n = new(mem_ctx) schedule_node(inst, this);
 
-  this->instructions_to_schedule++;
-
-  inst->remove(block);
   instructions.push_tail(n);
}
+
+   this->instructions_to_schedule = block->end_ip - block->start_ip + 1;
 }
 
 /** Recursive computation of the delay member of a node. */
@@ -1463,7 +1450,6 @@ void
 instruction_scheduler::schedule_instructions(bblock_t *block)
 {
const struct brw_device_info *devinfo = bs->devinfo;
-   backend_instruction *inst = block->end();
time = 0;
if (!post_reg_alloc)
   reg_pressure = reg_pressure_in[block->num];
@@ -1482,7 +1468,8 @@ instruction_scheduler::schedule_instructions(bblock_t 
*block)
   /* Schedule this instruction. */
   assert(chosen);
   chosen->remove();
-  inst->insert_before(block, chosen->inst);
+  chosen->inst->exec_node::remove();
+  block->instructions.push_tail(chosen->inst);
   instructions_to_schedule--;
 
   if (!post_reg_alloc) {
@@ -1551,8 +1538,6 @@ instruction_scheduler::schedule_instructions(bblock_t 
*block)
   }
}
 
-   if (block->end()->opcode == BRW_OPCODE_NOP)
-  block->end()->remove(block);
assert(instructions_to_schedule == 0);
 
block->cycle_count = time;
-- 
2.4.10

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[Mesa-dev] [PATCH 10/10] i965: Don't add barrier deps for FB write messages.

[Matt Turner]

Ken did this earlier, and this is just me reimplementing his patch a
little differently.
---
 src/mesa/drivers/dri/i965/brw_fs.cpp | 6 ++
 src/mesa/drivers/dri/i965/brw_ir_fs.h| 1 +
 src/mesa/drivers/dri/i965/brw_shader.cpp | 3 ++-
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 261dff6..2ebd490 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -409,6 +409,12 @@ fs_inst::can_change_types() const
 }
 
 bool
+fs_inst::is_scheduling_barrier() const
+{
+   return this->eot || backend_instruction::is_scheduling_barrier();
+}
+
+bool
 fs_inst::has_side_effects() const
 {
return this->eot || backend_instruction::has_side_effects();
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h 
b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index c3eec2e..827c991 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -204,6 +204,7 @@ public:
int regs_read(int arg) const;
bool can_do_source_mods(const struct brw_device_info *devinfo);
bool can_change_types() const;
+   bool is_scheduling_barrier() const;
bool has_side_effects() const;
bool has_source_and_destination_hazard() const;
 
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 80673e5..8a0e0a0 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -897,7 +897,6 @@ backend_instruction::is_scheduling_barrier() const
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
case FS_OPCODE_PLACEHOLDER_HALT:
-   case FS_OPCODE_FB_WRITE:
case SHADER_OPCODE_BARRIER:
case TCS_OPCODE_URB_WRITE:
case TCS_OPCODE_RELEASE_INPUT:
@@ -911,6 +910,8 @@ bool
 backend_instruction::has_side_effects() const
 {
switch (opcode) {
+   case FS_OPCODE_FB_WRITE:
+  return true;
default:
   return is_scheduling_barrier();
}
-- 
2.4.10

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[Mesa-dev] [PATCH 09/10] i965: Add and use is_scheduling_barrier() function.

[Matt Turner]

Though there is a lot of overlap with has_side_effects(), these do mean
different things.
---
 src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp |  6 ++
 src/mesa/drivers/dri/i965/brw_shader.cpp| 12 +++-
 src/mesa/drivers/dri/i965/brw_shader.h  |  2 ++
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp 
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 98fa5e3..67b713b 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -917,9 +917,7 @@ fs_instruction_scheduler::calculate_deps()
foreach_in_list(schedule_node, n, ) {
   fs_inst *inst = (fs_inst *)n->inst;
 
-  if (inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
-  inst->is_control_flow() ||
-  inst->has_side_effects())
+  if (inst->is_scheduling_barrier() || inst->is_control_flow())
  add_barrier_deps(n);
 
   /* read-after-write deps. */
@@ -1152,7 +1150,7 @@ vec4_instruction_scheduler::calculate_deps()
foreach_in_list(schedule_node, n, ) {
   vec4_instruction *inst = (vec4_instruction *)n->inst;
 
-  if (inst->is_control_flow() || inst->has_side_effects())
+  if (inst->is_scheduling_barrier() || inst->is_control_flow())
  add_barrier_deps(n);
 
   /* read-after-write deps. */
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index d007ed0..80673e5 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -879,7 +879,7 @@ backend_instruction::writes_accumulator_implicitly(const 
struct brw_device_info
 }
 
 bool
-backend_instruction::has_side_effects() const
+backend_instruction::is_scheduling_barrier() const
 {
switch (opcode) {
case SHADER_OPCODE_UNTYPED_ATOMIC:
@@ -896,6 +896,7 @@ backend_instruction::has_side_effects() const
case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
+   case FS_OPCODE_PLACEHOLDER_HALT:
case FS_OPCODE_FB_WRITE:
case SHADER_OPCODE_BARRIER:
case TCS_OPCODE_URB_WRITE:
@@ -907,6 +908,15 @@ backend_instruction::has_side_effects() const
 }
 
 bool
+backend_instruction::has_side_effects() const
+{
+   switch (opcode) {
+   default:
+  return is_scheduling_barrier();
+   }
+}
+
+bool
 backend_instruction::is_volatile() const
 {
switch (opcode) {
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index 82374a4..0ec2a84 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -124,6 +124,8 @@ struct backend_instruction : public exec_node {
 */
bool has_side_effects() const;
 
+   bool is_scheduling_barrier() const;
+
/**
 * True if the instruction might be affected by side effects of other
 * instructions.
-- 
2.4.10

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[Mesa-dev] [PATCH 06/10] i965: Relax restriction on scheduling last instruction.

[Matt Turner]

I think when this code was written, basic blocks were always ended by a
control flow instruction or an end-of-thread message. That's no longer
the case, and removing this restriction actually helps things:

   instructions in affected programs: 7267 -> 7244 (-0.32%)
   helped: 4

   total cycles in shared programs: 66559580 -> 66431900 (-0.19%)
   cycles in affected programs: 28310152 -> 28182472 (-0.45%)
   helped: 9577
   HURT: 879

   GAINED: 2

The addition of the is_control_flow() checks is not a functional change,
since the add_insts_from_block() does not put them in the list of
instructions to schedule. I plan to change this in a later patch.
---
 .../drivers/dri/i965/brw_schedule_instructions.cpp | 23 +++---
 1 file changed, 3 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp 
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 66eb07e..46b45a5 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -923,15 +923,6 @@ fs_instruction_scheduler::calculate_deps()
 */
schedule_node *last_fixed_grf_write = NULL;
 
-   /* The last instruction always needs to still be the last
-* instruction.  Either it's flow control (IF, ELSE, ENDIF, DO,
-* WHILE) and scheduling other things after it would disturb the
-* basic block, or it's FB_WRITE and we should do a better job at
-* dead code elimination anyway.
-*/
-   schedule_node *last = (schedule_node *)instructions.get_tail();
-   add_barrier_deps(last);
-
memset(last_grf_write, 0, sizeof(last_grf_write));
memset(last_mrf_write, 0, sizeof(last_mrf_write));
 
@@ -940,7 +931,8 @@ fs_instruction_scheduler::calculate_deps()
   fs_inst *inst = (fs_inst *)n->inst;
 
   if (inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
- inst->has_side_effects())
+  inst->is_control_flow() ||
+  inst->has_side_effects())
  add_barrier_deps(n);
 
   /* read-after-write deps. */
@@ -1166,15 +1158,6 @@ vec4_instruction_scheduler::calculate_deps()
 */
schedule_node *last_fixed_grf_write = NULL;
 
-   /* The last instruction always needs to still be the last instruction.
-* Either it's flow control (IF, ELSE, ENDIF, DO, WHILE) and scheduling
-* other things after it would disturb the basic block, or it's the EOT
-* URB_WRITE and we should do a better job at dead code eliminating
-* anything that could have been scheduled after it.
-*/
-   schedule_node *last = (schedule_node *)instructions.get_tail();
-   add_barrier_deps(last);
-
memset(last_grf_write, 0, sizeof(last_grf_write));
memset(last_mrf_write, 0, sizeof(last_mrf_write));
 
@@ -1182,7 +1165,7 @@ vec4_instruction_scheduler::calculate_deps()
foreach_in_list(schedule_node, n, ) {
   vec4_instruction *inst = (vec4_instruction *)n->inst;
 
-  if (inst->has_side_effects())
+  if (inst->is_control_flow() || inst->has_side_effects())
  add_barrier_deps(n);
 
   /* read-after-write deps. */
-- 
2.4.10

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[Mesa-dev] [PATCH 04/10] Revert "i965: Don't add barrier deps for FB write messages."

[Matt Turner]

This reverts commit d0e1d6b7e27bf5f05436e47080d326d7daa63af2.

The change in the vec4 code is a mistake -- there's never an
FS_OPCODE_FB_WRITE in vec4 code.

The change in the fs code had the (harmless) effect of not recognizing
an FB_WRITE as a scheduling barrier even if it was marked EOT --
harmless because the scheduler marked the last instruction of a block as
a barrier, something I'm changing in the following patches.

This will be reimplemented later in the series.
---
 src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp 
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 2153898..66eb07e 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -939,9 +939,8 @@ fs_instruction_scheduler::calculate_deps()
foreach_in_list(schedule_node, n, ) {
   fs_inst *inst = (fs_inst *)n->inst;
 
-  if ((inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
-   inst->has_side_effects()) &&
-  inst->opcode != FS_OPCODE_FB_WRITE)
+  if (inst->opcode == FS_OPCODE_PLACEHOLDER_HALT ||
+ inst->has_side_effects())
  add_barrier_deps(n);
 
   /* read-after-write deps. */
@@ -1183,7 +1182,7 @@ vec4_instruction_scheduler::calculate_deps()
foreach_in_list(schedule_node, n, ) {
   vec4_instruction *inst = (vec4_instruction *)n->inst;
 
-  if (inst->has_side_effects() && inst->opcode != FS_OPCODE_FB_WRITE)
+  if (inst->has_side_effects())
  add_barrier_deps(n);
 
   /* read-after-write deps. */
-- 
2.4.10

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[Mesa-dev] [PATCH 01/10] i965: Remove incorrect cycle estimates.

[Matt Turner]

These printed the cycle count the last basic block (sched.time is set
per basic block!). We have accurate, full program, data printed
elsewhere.
---
 src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 10 --
 1 file changed, 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp 
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 4f97577..2c7e4f7 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -1684,11 +1684,6 @@ 
fs_visitor::schedule_instructions(instruction_scheduler_mode mode)
   cfg->num_blocks, mode);
sched.run(cfg);
 
-   if (unlikely(debug_enabled) && mode == SCHEDULE_POST) {
-  fprintf(stderr, "%s%d estimated execution time: %d cycles\n",
-  stage_abbrev, dispatch_width, sched.time);
-   }
-
invalidate_live_intervals();
 }
 
@@ -1698,10 +1693,5 @@ vec4_visitor::opt_schedule_instructions()
vec4_instruction_scheduler sched(this, prog_data->total_grf);
sched.run(cfg);
 
-   if (unlikely(debug_enabled)) {
-  fprintf(stderr, "%s estimated execution time: %d cycles\n",
-  stage_abbrev, sched.time);
-   }
-
invalidate_live_intervals();
 }
-- 
2.4.10

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[Mesa-dev] [PATCH 05/10] i965/vec4: Mark TCS_OPCODE_SRC0_010_IS_ZERO as writing the flag.

[Matt Turner]

Missing this causes an assertion failure in the scheduler with the next
patch.
---
 src/mesa/drivers/dri/i965/brw_ir_vec4.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h 
b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 660beca..7cedf8e 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -201,7 +201,8 @@ public:
{
   return (conditional_mod && (opcode != BRW_OPCODE_SEL &&
   opcode != BRW_OPCODE_IF &&
-  opcode != BRW_OPCODE_WHILE));
+  opcode != BRW_OPCODE_WHILE)) ||
+ opcode == TCS_OPCODE_SRC0_010_IS_ZERO;
}
 };
 
-- 
2.4.10

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[Mesa-dev] [PATCH 07/10] i965: Assert that an instruction is not inserted around itself.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_shader.cpp | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index dfe6afc..d007ed0 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -948,6 +948,8 @@ adjust_later_block_ips(bblock_t *start_block, int 
ip_adjustment)
 void
 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
 {
+   assert(this != inst);
+
if (!this->is_head_sentinel())
   assert(inst_is_in_block(block, this) || !"Instruction not in block");
 
@@ -961,6 +963,8 @@ backend_instruction::insert_after(bblock_t *block, 
backend_instruction *inst)
 void
 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
 {
+   assert(this != inst);
+
if (!this->is_tail_sentinel())
   assert(inst_is_in_block(block, this) || !"Instruction not in block");
 
-- 
2.4.10

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[Mesa-dev] [PATCH 03/10] i965: Simplify full scheduling-barrier conditions.

[Matt Turner]

All of these were simply code for "architecture register file" (and in
the case of destinations, "not the null register").
---
 .../drivers/dri/i965/brw_schedule_instructions.cpp | 35 +-
 1 file changed, 8 insertions(+), 27 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp 
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 51d9ce1..2153898 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -964,10 +964,7 @@ fs_instruction_scheduler::calculate_deps()
 }
  } else if (inst->src[i].is_accumulator()) {
 add_dep(last_accumulator_write, n);
- } else if (inst->src[i].file != BAD_FILE &&
-inst->src[i].file != IMM &&
-inst->src[i].file != UNIFORM) {
-assert(inst->src[i].file != MRF);
+ } else if (inst->src[i].file == ARF) {
 add_barrier_deps(n);
  }
   }
@@ -1026,8 +1023,7 @@ fs_instruction_scheduler::calculate_deps()
   } else if (inst->dst.is_accumulator()) {
  add_dep(last_accumulator_write, n);
  last_accumulator_write = n;
-  } else if (inst->dst.file != BAD_FILE &&
- !inst->dst.is_null()) {
+  } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
  add_barrier_deps(n);
   }
 
@@ -1080,10 +1076,7 @@ fs_instruction_scheduler::calculate_deps()
 }
  } else if (inst->src[i].is_accumulator()) {
 add_dep(n, last_accumulator_write, 0);
- } else if (inst->src[i].file != BAD_FILE &&
-inst->src[i].file != IMM &&
-inst->src[i].file != UNIFORM) {
-assert(inst->src[i].file != MRF);
+ } else if (inst->src[i].file == ARF) {
 add_barrier_deps(n);
  }
   }
@@ -1140,8 +1133,7 @@ fs_instruction_scheduler::calculate_deps()
  }
   } else if (inst->dst.is_accumulator()) {
  last_accumulator_write = n;
-  } else if (inst->dst.file != BAD_FILE &&
- !inst->dst.is_null()) {
+  } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
  add_barrier_deps(n);
   }
 
@@ -1204,12 +1196,7 @@ vec4_instruction_scheduler::calculate_deps()
  } else if (inst->src[i].is_accumulator()) {
 assert(last_accumulator_write);
 add_dep(last_accumulator_write, n);
- } else if (inst->src[i].file != BAD_FILE &&
-inst->src[i].file != IMM &&
-inst->src[i].file != UNIFORM) {
-/* No reads from MRF, and ATTR is already translated away */
-assert(inst->src[i].file != MRF &&
-   inst->src[i].file != ATTR);
+ } else if (inst->src[i].file == ARF) {
 add_barrier_deps(n);
  }
   }
@@ -1248,8 +1235,7 @@ vec4_instruction_scheduler::calculate_deps()
   } else if (inst->dst.is_accumulator()) {
  add_dep(last_accumulator_write, n);
  last_accumulator_write = n;
-  } else if (inst->dst.file != BAD_FILE &&
- !inst->dst.is_null()) {
+  } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
  add_barrier_deps(n);
   }
 
@@ -1291,11 +1277,7 @@ vec4_instruction_scheduler::calculate_deps()
 add_dep(n, last_fixed_grf_write);
  } else if (inst->src[i].is_accumulator()) {
 add_dep(n, last_accumulator_write);
- } else if (inst->src[i].file != BAD_FILE &&
-inst->src[i].file != IMM &&
-inst->src[i].file != UNIFORM) {
-assert(inst->src[i].file != MRF &&
-   inst->src[i].file != ATTR);
+ } else if (inst->src[i].file == ARF) {
 add_barrier_deps(n);
  }
   }
@@ -1330,8 +1312,7 @@ vec4_instruction_scheduler::calculate_deps()
  last_fixed_grf_write = n;
   } else if (inst->dst.is_accumulator()) {
  last_accumulator_write = n;
-  } else if (inst->dst.file != BAD_FILE &&
- !inst->dst.is_null()) {
+  } else if (inst->dst.file == ARF && !inst->dst.is_null()) {
  add_barrier_deps(n);
   }
 
-- 
2.4.10

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[Mesa-dev] [PATCH 02/10] i965: Use foreach_in_list_reverse_safe() macro.

[Matt Turner]

---
 src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 14 ++
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp 
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 2c7e4f7..51d9ce1 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -1057,12 +1057,7 @@ fs_instruction_scheduler::calculate_deps()
last_accumulator_write = NULL;
last_fixed_grf_write = NULL;
 
-   exec_node *node;
-   exec_node *prev;
-   for (node = instructions.get_tail(), prev = node->prev;
-!node->is_head_sentinel();
-node = prev, prev = node->prev) {
-  schedule_node *n = (schedule_node *)node;
+   foreach_in_list_reverse_safe(schedule_node, n, ) {
   fs_inst *inst = (fs_inst *)n->inst;
 
   /* write-after-read deps. */
@@ -1284,12 +1279,7 @@ vec4_instruction_scheduler::calculate_deps()
last_accumulator_write = NULL;
last_fixed_grf_write = NULL;
 
-   exec_node *node;
-   exec_node *prev;
-   for (node = instructions.get_tail(), prev = node->prev;
-!node->is_head_sentinel();
-node = prev, prev = node->prev) {
-  schedule_node *n = (schedule_node *)node;
+   foreach_in_list_reverse_safe(schedule_node, n, ) {
   vec4_instruction *inst = (vec4_instruction *)n->inst;
 
   /* write-after-read deps. */
-- 
2.4.10

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[Mesa-dev] [PATCH 4/4] glcpp: Remove empty mid-rule action which changes test behavior.

[Kenneth Graunke]

Apparently this causes a slight difference in the parser's token
expectations, leading to a different error message.

It seems harmless, but I wanted to be cautious and separate it out.

Signed-off-by: Kenneth Graunke 
---
 src/compiler/glsl/glcpp/glcpp-parse.y  | 2 +-
 src/compiler/glsl/glcpp/tests/129-define-non-identifier.c.expected | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y 
b/src/compiler/glsl/glcpp/glcpp-parse.y
index 1f416a1..e677811 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -279,7 +279,7 @@ control_line:
 ;
 
 control_line_success:
-   HASH_TOKEN DEFINE_TOKEN { } define
+   HASH_TOKEN DEFINE_TOKEN define
 |  HASH_TOKEN UNDEF IDENTIFIER NEWLINE {
macro_t *macro;
if (strcmp("__LINE__", $3) == 0
diff --git a/src/compiler/glsl/glcpp/tests/129-define-non-identifier.c.expected 
b/src/compiler/glsl/glcpp/tests/129-define-non-identifier.c.expected
index fd0b413..5206a5c 100644
--- a/src/compiler/glsl/glcpp/tests/129-define-non-identifier.c.expected
+++ b/src/compiler/glsl/glcpp/tests/129-define-non-identifier.c.expected
@@ -1,2 +1,2 @@
 0:1(9): preprocessor error: #define followed by a non-identifier: 123
-0:1(9): preprocessor error: syntax error, unexpected INTEGER_STRING, expecting 
FUNC_IDENTIFIER or OBJ_IDENTIFIER
+0:1(9): preprocessor error: syntax error, unexpected INTEGER_STRING, expecting 
FUNC_IDENTIFIER or OBJ_IDENTIFIER or NEWLINE
-- 
2.7.2

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[Mesa-dev] [PATCH 3/4] glcpp: Clean up most empty mid-rule actions left by previous commit.

[Kenneth Graunke]

I didn't want to pollute the previous patch with all the $4 -> $3
changes.

Signed-off-by: Kenneth Graunke 
---
 src/compiler/glsl/glcpp/glcpp-parse.y | 36 +--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y 
b/src/compiler/glsl/glcpp/glcpp-parse.y
index a93a138..1f416a1 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -266,13 +266,13 @@ control_line:
ralloc_asprintf_rewrite_tail (>output, 
>output_length, "\n");
}
 |  control_line_error
-|  HASH_TOKEN LINE { } pp_tokens NEWLINE {
+|  HASH_TOKEN LINE pp_tokens NEWLINE {
 
if (parser->skip_stack == NULL ||
parser->skip_stack->type == SKIP_NO_SKIP)
{
_glcpp_parser_expand_and_lex_from (parser,
-  LINE_EXPANDED, $4,
+  LINE_EXPANDED, $3,
   
EXPANSION_MODE_IGNORE_DEFINED);
}
}
@@ -280,23 +280,23 @@ control_line:
 
 control_line_success:
HASH_TOKEN DEFINE_TOKEN { } define
-|  HASH_TOKEN UNDEF { } IDENTIFIER NEWLINE {
+|  HASH_TOKEN UNDEF IDENTIFIER NEWLINE {
macro_t *macro;
-   if (strcmp("__LINE__", $4) == 0
-   || strcmp("__FILE__", $4) == 0
-   || strcmp("__VERSION__", $4) == 0
-   || strncmp("GL_", $4, 3) == 0)
+   if (strcmp("__LINE__", $3) == 0
+   || strcmp("__FILE__", $3) == 0
+   || strcmp("__VERSION__", $3) == 0
+   || strncmp("GL_", $3, 3) == 0)
glcpp_error(& @1, parser, "Built-in (pre-defined)"
" macro names cannot be undefined.");
 
-   macro = hash_table_find (parser->defines, $4);
+   macro = hash_table_find (parser->defines, $3);
if (macro) {
-   hash_table_remove (parser->defines, $4);
+   hash_table_remove (parser->defines, $3);
ralloc_free (macro);
}
-   ralloc_free ($4);
+   ralloc_free ($3);
}
-|  HASH_TOKEN IF { } pp_tokens NEWLINE {
+|  HASH_TOKEN IF pp_tokens NEWLINE {
/* Be careful to only evaluate the 'if' expression if
 * we are not skipping. When we are skipping, we
 * simply push a new 0-valued 'if' onto the skip
@@ -308,7 +308,7 @@ control_line_success:
parser->skip_stack->type == SKIP_NO_SKIP)
{
_glcpp_parser_expand_and_lex_from (parser,
-  IF_EXPANDED, $4,
+  IF_EXPANDED, $3,
   
EXPANSION_MODE_EVALUATE_DEFINED);
}   
else
@@ -327,14 +327,14 @@ control_line_success:
}   
_glcpp_parser_skip_stack_push_if (parser, & @1, 0);
}
-|  HASH_TOKEN IFDEF { } IDENTIFIER junk NEWLINE {
-   macro_t *macro = hash_table_find (parser->defines, $4);
-   ralloc_free ($4);
+|  HASH_TOKEN IFDEF IDENTIFIER junk NEWLINE {
+   macro_t *macro = hash_table_find (parser->defines, $3);
+   ralloc_free ($3);
_glcpp_parser_skip_stack_push_if (parser, & @1, macro != NULL);
}
-|  HASH_TOKEN IFNDEF { } IDENTIFIER junk NEWLINE {
-   macro_t *macro = hash_table_find (parser->defines, $4);
-   ralloc_free ($4);
+|  HASH_TOKEN IFNDEF IDENTIFIER junk NEWLINE {
+   macro_t *macro = hash_table_find (parser->defines, $3);
+   ralloc_free ($3);
_glcpp_parser_skip_stack_push_if (parser, & @3, macro == NULL);
}
 |  HASH_TOKEN ELIF pp_tokens NEWLINE {
-- 
2.7.2

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[Mesa-dev] [PATCH 1/4] glcpp: Implicitly resolve version after the first non-space/hash token.

[Kenneth Graunke]

We resolved the implicit version directive when processing control lines,
such as #ifdef, to ensure any built-in macros exist.  However, we failed
to resolve it when handling ordinary text.

For example,

int x = __VERSION__;

should resolve __VERSION__ to 110, but since we never resolved the implicit
version, none of the built-in macros exist, so it was left as is.

This also meant we allowed the following shader to slop through:

123
#version 120

Nothing would cause the implicit version to take effect, so when we saw
the #version directive, we thought everything was peachy.

This patch makes the lexer's per-token action resolve the implicit
version on the first non-space/newline/hash token that isn't part of
a #version directive, fulfilling the GLSL language spec:

"The #version directive must occur in a shader before anything else,
 except for comments and white space."

Because we emit #version as HASH_TOKEN then VERSION_TOKEN, we have to
allow HASH_TOKEN to slop through as well, so we don't resolve the
implicit version as soon as we see the # character.  However, this is
fine, because the parser's HASH_TOKEN NEWLINE rule does resolve the
version, disallowing cases like:

#
#version 120

This patch also adds the above shaders as new glcpp tests.

Fixes dEQP-GLES2.functional.shaders.preprocessor.predefined_macros.
{gl_es_1_vertex,gl_es_1_fragment}.

Signed-off-by: Kenneth Graunke 
---
 src/compiler/glsl/glcpp/glcpp-lex.l | 8 
 src/compiler/glsl/glcpp/glcpp.h | 1 +
 src/compiler/glsl/glcpp/tests/144-implicit-version.c| 1 +
 src/compiler/glsl/glcpp/tests/144-implicit-version.c.expected   | 1 +
 src/compiler/glsl/glcpp/tests/145-version-first.c   | 2 ++
 src/compiler/glsl/glcpp/tests/145-version-first.c.expected  | 3 +++
 src/compiler/glsl/glcpp/tests/146-version-first-hash.c  | 2 ++
 src/compiler/glsl/glcpp/tests/146-version-first-hash.c.expected | 3 +++
 8 files changed, 21 insertions(+)
 create mode 100644 src/compiler/glsl/glcpp/tests/144-implicit-version.c
 create mode 100644 
src/compiler/glsl/glcpp/tests/144-implicit-version.c.expected
 create mode 100644 src/compiler/glsl/glcpp/tests/145-version-first.c
 create mode 100644 src/compiler/glsl/glcpp/tests/145-version-first.c.expected
 create mode 100644 src/compiler/glsl/glcpp/tests/146-version-first-hash.c
 create mode 100644 
src/compiler/glsl/glcpp/tests/146-version-first-hash.c.expected

diff --git a/src/compiler/glsl/glcpp/glcpp-lex.l 
b/src/compiler/glsl/glcpp/glcpp-lex.l
index fa9aa50..071918e 100644
--- a/src/compiler/glsl/glcpp/glcpp-lex.l
+++ b/src/compiler/glsl/glcpp/glcpp-lex.l
@@ -120,6 +120,11 @@ void glcpp_set_column (int  column_no , yyscan_t 
yyscanner);
 static int
 glcpp_lex_update_state_per_token (glcpp_parser_t *parser, int token)
 {
+   if (token != NEWLINE && token != SPACE && token != HASH_TOKEN &&
+   !parser->lexing_version_directive) {
+   glcpp_parser_resolve_implicit_version(parser);
+   }
+
/* After the first non-space token in a line, we won't
 * allow any '#' to introduce a directive. */
if (token == NEWLINE) {
@@ -285,6 +290,7 @@ HEXADECIMAL_INTEGER 0[xX][0-9a-fA-F]+[uU]?
 version{HSPACE}+ {
BEGIN INITIAL;
yyextra->space_tokens = 0;
+   yyextra->lexing_version_directive = 1;
RETURN_STRING_TOKEN (VERSION_TOKEN);
 }
 
@@ -536,6 +542,7 @@ HEXADECIMAL_INTEGER 0[xX][0-9a-fA-F]+[uU]?
}
yyextra->space_tokens = 1;
yyextra->lexing_directive = 0;
+   yyextra->lexing_version_directive = 0;
yylineno++;
yycolumn = 0;
RETURN_TOKEN_NEVER_SKIP (NEWLINE);
@@ -546,6 +553,7 @@ HEXADECIMAL_INTEGER 0[xX][0-9a-fA-F]+[uU]?
glcpp_error(yylloc, yyextra, "Unterminated comment");
BEGIN DONE; /* Don't keep matching this rule forever. */
yyextra->lexing_directive = 0;
+   yyextra->lexing_version_directive = 0;
if (! parser->last_token_was_newline)
RETURN_TOKEN (NEWLINE);
 }
diff --git a/src/compiler/glsl/glcpp/glcpp.h b/src/compiler/glsl/glcpp/glcpp.h
index 70aa14b..d87e6b7 100644
--- a/src/compiler/glsl/glcpp/glcpp.h
+++ b/src/compiler/glsl/glcpp/glcpp.h
@@ -176,6 +176,7 @@ struct glcpp_parser {
struct hash_table *defines;
active_list_t *active;
int lexing_directive;
+   int lexing_version_directive;
int space_tokens;
int last_token_was_newline;
int last_token_was_space;
diff --git a/src/compiler/glsl/glcpp/tests/144-implicit-version.c 
b/src/compiler/glsl/glcpp/tests/144-implicit-version.c
new file mode 100644
index 000..7bf72fc
--- /dev/null
+++ b/src/compiler/glsl/glcpp/tests/144-implicit-version.c
@@ -0,0 +1 @@
+int x = __VERSION__;
diff --git a/src/compiler/glsl/glcpp/tests/144-implicit-version.c.expected 

[Mesa-dev] [PATCH 2/4] glcpp: Delete unnecessary implicit version resolves.

[Kenneth Graunke]

We now have a bigger hammer.  The HASH_TOKEN NEWLINE rule still needs
to exist to ensure the 146-version-hash-first.c test still passes.

Signed-off-by: Kenneth Graunke 
---
 src/compiler/glsl/glcpp/glcpp-parse.y | 24 ++--
 1 file changed, 6 insertions(+), 18 deletions(-)

diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y 
b/src/compiler/glsl/glcpp/glcpp-parse.y
index 5c38f86..a93a138 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -266,9 +266,7 @@ control_line:
ralloc_asprintf_rewrite_tail (>output, 
>output_length, "\n");
}
 |  control_line_error
-|  HASH_TOKEN LINE {
-   glcpp_parser_resolve_implicit_version(parser);
-   } pp_tokens NEWLINE {
+|  HASH_TOKEN LINE { } pp_tokens NEWLINE {
 
if (parser->skip_stack == NULL ||
parser->skip_stack->type == SKIP_NO_SKIP)
@@ -281,12 +279,8 @@ control_line:
 ;
 
 control_line_success:
-   HASH_TOKEN DEFINE_TOKEN {
-   glcpp_parser_resolve_implicit_version(parser);
-   } define
-|  HASH_TOKEN UNDEF {
-   glcpp_parser_resolve_implicit_version(parser);
-   } IDENTIFIER NEWLINE {
+   HASH_TOKEN DEFINE_TOKEN { } define
+|  HASH_TOKEN UNDEF { } IDENTIFIER NEWLINE {
macro_t *macro;
if (strcmp("__LINE__", $4) == 0
|| strcmp("__FILE__", $4) == 0
@@ -302,9 +296,7 @@ control_line_success:
}
ralloc_free ($4);
}
-|  HASH_TOKEN IF {
-   glcpp_parser_resolve_implicit_version(parser);
-   } pp_tokens NEWLINE {
+|  HASH_TOKEN IF { } pp_tokens NEWLINE {
/* Be careful to only evaluate the 'if' expression if
 * we are not skipping. When we are skipping, we
 * simply push a new 0-valued 'if' onto the skip
@@ -335,16 +327,12 @@ control_line_success:
}   
_glcpp_parser_skip_stack_push_if (parser, & @1, 0);
}
-|  HASH_TOKEN IFDEF {
-   glcpp_parser_resolve_implicit_version(parser);
-   } IDENTIFIER junk NEWLINE {
+|  HASH_TOKEN IFDEF { } IDENTIFIER junk NEWLINE {
macro_t *macro = hash_table_find (parser->defines, $4);
ralloc_free ($4);
_glcpp_parser_skip_stack_push_if (parser, & @1, macro != NULL);
}
-|  HASH_TOKEN IFNDEF {
-   glcpp_parser_resolve_implicit_version(parser);
-   } IDENTIFIER junk NEWLINE {
+|  HASH_TOKEN IFNDEF { } IDENTIFIER junk NEWLINE {
macro_t *macro = hash_table_find (parser->defines, $4);
ralloc_free ($4);
_glcpp_parser_skip_stack_push_if (parser, & @3, macro == NULL);
-- 
2.7.2

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[Mesa-dev] [PATCH] opencl: fix .gitignore for .install-gallium-links

[Dieter Nützel]

Signed-off-by: Dieter Nützel 
---
 src/gallium/targets/opencl/.gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/targets/opencl/.gitignore 
b/src/gallium/targets/opencl/.gitignore
index dad573f..8f12fdd 100644
--- a/src/gallium/targets/opencl/.gitignore
+++ b/src/gallium/targets/opencl/.gitignore
@@ -1 +1,2 @@
 /mesa.icd
+.install-gallium-links
-- 
2.1.4

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Re: [Mesa-dev] [PATCH 2/3] i965/vec4/nir: remove emit_untyped_surface_read and emit_untyped_atomic at brw_vec4_visitor

[Francisco Jerez]

Alejandro Piñeiro  writes:

> surface_access emit_untyped_read and emit_untyped_atomic provides the same
> functionality.
> ---
>
> This patch also fixes the indentation at switch (instr->intrinsic).
>
>  src/mesa/drivers/dri/i965/brw_vec4.h   |  7 
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 39 --
>  src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 55 
> --
>  3 files changed, 26 insertions(+), 75 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
> b/src/mesa/drivers/dri/i965/brw_vec4.h
> index 633f13c..1e9f1e2 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
> @@ -276,13 +276,6 @@ public:
> void emit_shader_time_end();
> void emit_shader_time_write(int shader_time_subindex, src_reg value);
>  
> -   void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
> -dst_reg dst, src_reg offset, src_reg src0,
> -src_reg src1);
> -
> -   void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
> -  src_reg offset);
> -
> src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
> src_reg *reladdr, int reg_offset);
> src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 9b721e5..8ae8d9e 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -724,24 +724,37 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr 
> *instr)
>   (unsigned) instr->const_index[0];
>src_reg offset = get_nir_src(instr->src[0], nir_type_int,
> instr->num_components);
> +  src_reg surface = brw_imm_ud(surf_index);

const.

> +  const vec4_builder bld =
> + vec4_builder(this).at_end().annotate(current_annotation, base_ir);
> +  src_reg tmp;
> +
>dest = get_nir_dest(instr->dest);
>  
>switch (instr->intrinsic) {
> - case nir_intrinsic_atomic_counter_inc:
> -emit_untyped_atomic(BRW_AOP_INC, surf_index, dest, offset,
> -src_reg(), src_reg());
> -break;
> - case nir_intrinsic_atomic_counter_dec:
> -emit_untyped_atomic(BRW_AOP_PREDEC, surf_index, dest, offset,
> -src_reg(), src_reg());
> -break;
> - case nir_intrinsic_atomic_counter_read:
> -emit_untyped_surface_read(surf_index, dest, offset);
> -break;
> - default:
> -unreachable("Unreachable");
> +  case nir_intrinsic_atomic_counter_inc:
> + tmp = emit_untyped_atomic(bld, surface, offset,
> +   src_reg(), src_reg(),
> +   1, 1,
> +   BRW_AOP_INC,
> +   BRW_PREDICATE_NONE);

No need to specify a predicate.

> + break;
> +  case nir_intrinsic_atomic_counter_dec:
> + tmp = emit_untyped_atomic(bld, surface, offset,
> +   src_reg(), src_reg(),
> +   1, 1,
> +   BRW_AOP_PREDEC,
> +   BRW_PREDICATE_NONE);

Same here.

> + break;
> +  case nir_intrinsic_atomic_counter_read:
> + tmp = emit_untyped_read(bld, surface, offset, 1, 1);
> + break;
> +  default:
> + unreachable("Unreachable");
>}
>  
> +  dest.type = tmp.type;
> +  bld.MOV(dest, tmp);

You can use retype(dest, tmp.type).  With these nit-picks addressed:

Reviewed-by: Francisco Jerez 

>brw_mark_surface_used(stage_prog_data, surf_index);
>break;
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index cfd4d9b..d30330a 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -1115,61 +1115,6 @@ vec4_visitor::gs_end_primitive()
>  }
>  
>  void
> -vec4_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
> -  dst_reg dst, src_reg surf_offset,
> -  src_reg src0, src_reg src1)
> -{
> -   unsigned mlen = 1 + (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
> -   src_reg src_payload(this, glsl_type::uint_type, mlen);
> -   dst_reg payload(src_payload);
> -   payload.writemask = WRITEMASK_X;
> -
> -   /* Set the atomic operation offset. */
> -   emit(MOV(offset(payload, 0), surf_offset));
> -   unsigned i = 1;
> -
> -   /* Set the atomic operation arguments. */
> -   if (src0.file != BAD_FILE) {
> -  

Re: [Mesa-dev] [PATCH 3/3] i965/vec4/nir: no need to use surface_access:: to call emit_untyped_atomic

[Francisco Jerez]

Alejandro Piñeiro  writes:

> Now that brw_vec4_visitor::emit_untyped_atomic was removed, there is no need
> to explicitly set it.

Reviewed-by: Francisco Jerez 

> ---
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 11 +--
>  1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 8ae8d9e..c30b27e 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -881,12 +881,11 @@ vec4_visitor::nir_emit_ssbo_atomic(int op, 
> nir_intrinsic_instr *instr)
> const vec4_builder bld =
>vec4_builder(this).at_end().annotate(current_annotation, base_ir);
>  
> -   src_reg atomic_result =
> -  surface_access::emit_untyped_atomic(bld, surface, offset,
> -  data1, data2,
> -  1 /* dims */, 1 /* rsize */,
> -  op,
> -  BRW_PREDICATE_NONE);
> +   src_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
> +   data1, data2,
> +   1 /* dims */, 1 /* rsize */,
> +   op,
> +   BRW_PREDICATE_NONE);
> dest.type = atomic_result.type;
> bld.MOV(dest, atomic_result);
>  }
> -- 
> 2.5.0
>
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Re: [Mesa-dev] [PATCH 00/16] Add infrastructure for GL_OES_texture_compression_astc

[Ilia Mirkin]

Not that I'm against this, but is there actual HW that supports the full 3d
stuff? From what I gather, no proprietary drivers expose this ext.
On Mar 4, 2016 8:17 PM, "Anuj Phogat"  wrote:

> Anuj Phogat (16):
>   mesa: Add block depth field in struct gl_format_info
>   mesa: Add support to query block depth using
> _mesa_get_format_block_size()
>   mesa: Add error conditions for compressed textures with 3D blocks
>   mesa: Account for block depth in _mesa_format_image_size()
>   glapi: Update dispatch XML files for OES_texture_compression_astc.xml
>   mesa: Add mesa formats for astc 3d formats
>   mesa: Add entries for astc 3d formats initializing struct
> gl_format_info
>   mesa: Add OES_texture_compression_astc to extension table and
> gl_extensions
>   mesa: Align the values of #define's in glheader.h
>   mesa: Add the missing defines for GL_OES_texture_compression_astc
>   mesa: Add a helper function is_astc_3d_format()
>   mesa: Account for astc 3d formats in _mesa_is_astc_format()
>   mesa: Handle astc 3d formats in _mesa_base_tex_format()
>   mesa: Handle astc 3d formats in _mesa_get_compressed_formats()
>   mesa: Enable translation between astc 3d gl formats and mesa formats
>   swrast: Add texfetch_funcs entries for astc 3d formats
>
>  src/mapi/glapi/gen/Makefile.am |   1 +
>  .../glapi/gen/OES_texture_compression_astc.xml |  61 +++
>  src/mapi/glapi/gen/gl_API.xml  |   2 +
>  src/mesa/drivers/dri/i915/intel_mipmap_tree.c  |   8 +-
>  src/mesa/drivers/dri/i915/intel_tex_layout.c   |   4 +-
>  src/mesa/drivers/dri/i965/brw_tex_layout.c |  21 +-
>  src/mesa/drivers/dri/i965/intel_copy_image.c   |  14 +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c  |   8 +-
>  src/mesa/drivers/dri/nouveau/nouveau_util.h|   8 +-
>  src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c   |  11 +-
>  src/mesa/drivers/dri/radeon/radeon_texture.c   |   4 +-
>  src/mesa/main/copyimage.c  |   6 +-
>  src/mesa/main/extensions_table.h   |   1 +
>  src/mesa/main/format_info.py   |   5 +-
>  src/mesa/main/format_parser.py |  15 +-
>  src/mesa/main/formatquery.c|   4 +-
>  src/mesa/main/formats.c|  52 +-
>  src/mesa/main/formats.csv  | 550
> +++--
>  src/mesa/main/formats.h|  24 +-
>  src/mesa/main/glformats.c  |  54 +-
>  src/mesa/main/glheader.h   |  81 +--
>  src/mesa/main/mtypes.h |   1 +
>  src/mesa/main/texcompress.c| 117 -
>  src/mesa/main/texgetimage.c|   4 +-
>  src/mesa/main/teximage.c   |  17 +-
>  src/mesa/main/texstore.c   |   4 +-
>  src/mesa/swrast/s_texfetch.c   |  27 +-
>  src/mesa/swrast/s_texture.c|   4 +-
>  28 files changed, 719 insertions(+), 389 deletions(-)
>  create mode 100644 src/mapi/glapi/gen/OES_texture_compression_astc.xml
>
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH 1/3] i965/vec4: don't load src on emit_send if it is BAD_FILE

[Francisco Jerez]

Alejandro Piñeiro  writes:

> This can happens if using emit_untyped_atomic for an atomic dec/inc
> ---
>  src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp
> index 28002c5..ba1e670f 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp
> @@ -131,9 +131,10 @@ namespace brw {
> bld.MOV(offset(payload, n++),
> offset(retype(addr, BRW_REGISTER_TYPE_UD), i));
>  
> -for (unsigned i = 0; i < src_sz; i++)
> -   bld.MOV(offset(payload, n++),
> -   offset(retype(src, BRW_REGISTER_TYPE_UD), i));
> +if (src.file != BAD_FILE)
> +   for (unsigned i = 0; i < src_sz; i++)
> +  bld.MOV(offset(payload, n++),
> +  offset(retype(src, BRW_REGISTER_TYPE_UD), i));
>  
I don't think this is right, the calculated message size will be off if
src is invalid but src_sz is non-zero.  In cases where the source is not
present you need to make sure you pass src_sz=0 to emit_send() (e.g. in
emit_untyped_atomic).

Thanks.

>  /* Reduce the dynamically uniform surface index to a single
>   * scalar.
> -- 
> 2.5.0
>
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[Mesa-dev] [PATCH 12/16] mesa: Account for astc 3d formats in _mesa_is_astc_format()

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/glformats.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 607db95..f939b8b 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -823,10 +823,10 @@ _mesa_is_enum_format_signed_int(GLenum format)
 }
 
 /**
- * Test if the given format is an ASTC format.
+ * Test if the given format is an ASTC 2D format.
  */
-GLboolean
-_mesa_is_astc_format(GLenum internalFormat)
+static bool
+is_astc_2d_format(GLenum internalFormat)
 {
switch (internalFormat) {
case GL_COMPRESSED_RGBA_ASTC_4x4_KHR:
@@ -897,6 +897,16 @@ is_astc_3d_format(GLenum internalFormat)
 }
 
 /**
+ * Test if the given format is an ASTC format.
+ */
+GLboolean
+_mesa_is_astc_format(GLenum internalFormat)
+{
+   return is_astc_2d_format(internalFormat) ||
+  is_astc_3d_format(internalFormat);
+}
+
+/**
  * Test if the given format is an integer (non-normalized) format.
  */
 GLboolean
-- 
2.5.0

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[Mesa-dev] [PATCH 16/16] swrast: Add texfetch_funcs entries for astc 3d formats

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/swrast/s_texfetch.c | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/mesa/swrast/s_texfetch.c b/src/mesa/swrast/s_texfetch.c
index 4a9ec2c..0acbc69 100644
--- a/src/mesa/swrast/s_texfetch.c
+++ b/src/mesa/swrast/s_texfetch.c
@@ -440,7 +440,28 @@ texfetch_funcs[] =
FETCH_NULL(SRGB8_ALPHA8_ASTC_10x8),
FETCH_NULL(SRGB8_ALPHA8_ASTC_10x10),
FETCH_NULL(SRGB8_ALPHA8_ASTC_12x10),
-   FETCH_NULL(SRGB8_ALPHA8_ASTC_12x12)
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_12x12),
+
+   FETCH_NULL(RGBA_ASTC_3x3x3),
+   FETCH_NULL(RGBA_ASTC_4x3x3),
+   FETCH_NULL(RGBA_ASTC_4x4x3),
+   FETCH_NULL(RGBA_ASTC_4x4x4),
+   FETCH_NULL(RGBA_ASTC_5x4x4),
+   FETCH_NULL(RGBA_ASTC_5x5x4),
+   FETCH_NULL(RGBA_ASTC_5x5x5),
+   FETCH_NULL(RGBA_ASTC_6x5x5),
+   FETCH_NULL(RGBA_ASTC_6x6x5),
+   FETCH_NULL(RGBA_ASTC_6x6x6),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_3x3x3),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_4x3x3),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_4x4x3),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_4x4x4),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_5x4x4),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_5x5x4),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_5x5x5),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_6x5x5),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_6x6x5),
+   FETCH_NULL(SRGB8_ALPHA8_ASTC_6x6x6)
 };
 
 
-- 
2.5.0

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[Mesa-dev] [PATCH 03/16] mesa: Add error conditions for compressed textures with 3D blocks

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/teximage.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index ba72353..f5de1c5 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1187,11 +1187,11 @@ error_check_subtexture_dimensions(struct gl_context 
*ctx, GLuint dims,
 */
_mesa_get_format_block_size(destImage->TexFormat, , , );
 
-   if (bw != 1 || bh != 1) {
+   if (bw != 1 || bh != 1 || bd != 1) {
   /* offset must be multiple of block size */
-  if ((xoffset % bw != 0) || (yoffset % bh != 0)) {
+  if ((xoffset % bw != 0) || (yoffset % bh != 0) || (zoffset % bd != 0)) {
  _mesa_error(ctx, GL_INVALID_OPERATION,
- "%s(xoffset = %d, yoffset = %d)",
+ "%s(xoffset = %d, yoffset = %d, zoffset = %d)",
  func, xoffset, yoffset);
  return GL_TRUE;
   }
@@ -1214,6 +1214,13 @@ error_check_subtexture_dimensions(struct gl_context 
*ctx, GLuint dims,
  "%s(height = %d)", func, subHeight);
  return GL_TRUE;
   }
+
+  if ((subDepth % bd != 0) &&
+  (zoffset + subDepth != (GLint) destImage->Depth)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "%s(depth = %d)", func, subDepth);
+ return GL_TRUE;
+  }
}
 
return GL_FALSE;
-- 
2.5.0

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[Mesa-dev] [PATCH 13/16] mesa: Handle astc 3d formats in _mesa_base_tex_format()

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/glformats.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index f939b8b..110ce47 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -2387,8 +2387,10 @@ _mesa_base_tex_format(const struct gl_context *ctx, 
GLint internalFormat)
 return base_compressed;
}
 
-   if (ctx->Extensions.KHR_texture_compression_astc_ldr &&
-  _mesa_is_astc_format(internalFormat))
+   if ((ctx->Extensions.KHR_texture_compression_astc_ldr &&
+is_astc_2d_format(internalFormat)) ||
+   (ctx->Extensions.OES_texture_compression_astc &&
+is_astc_3d_format(internalFormat)))
 return GL_RGBA;
 
if (ctx->Extensions.MESA_ycbcr_texture) {
-- 
2.5.0

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[Mesa-dev] [PATCH 10/16] mesa: Add the missing defines for GL_OES_texture_compression_astc

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/glheader.h | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/src/mesa/main/glheader.h b/src/mesa/main/glheader.h
index 9d299e8..40fada1 100644
--- a/src/mesa/main/glheader.h
+++ b/src/mesa/main/glheader.h
@@ -99,6 +99,29 @@ typedef void *GLeglImageOES;
 #define GL_PALETTE8_RGB5_A1_OES 0x8B99
 #endif
 
+#ifndef GL_OES_texture_compression_astc
+#define GL_COMPRESSED_RGBA_ASTC_3x3x3_OES   0x93C0
+#define GL_COMPRESSED_RGBA_ASTC_4x3x3_OES   0x93C1
+#define GL_COMPRESSED_RGBA_ASTC_4x4x3_OES   0x93C2
+#define GL_COMPRESSED_RGBA_ASTC_4x4x4_OES   0x93C3
+#define GL_COMPRESSED_RGBA_ASTC_5x4x4_OES   0x93C4
+#define GL_COMPRESSED_RGBA_ASTC_5x5x4_OES   0x93C5
+#define GL_COMPRESSED_RGBA_ASTC_5x5x5_OES   0x93C6
+#define GL_COMPRESSED_RGBA_ASTC_6x5x5_OES   0x93C7
+#define GL_COMPRESSED_RGBA_ASTC_6x6x5_OES   0x93C8
+#define GL_COMPRESSED_RGBA_ASTC_6x6x6_OES   0x93C9
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_3x3x3_OES   0x93E0
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x3x3_OES   0x93E1
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x3_OES   0x93E2
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x4_OES   0x93E3
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4x4_OES   0x93E4
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x4_OES   0x93E5
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x5_OES   0x93E6
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5x5_OES   0x93E7
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x5_OES   0x93E8
+#define GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x6_OES   0x93E9
+#endif
+
 #ifndef GL_ES_VERSION_2_0
 #define GL_SHADER_BINARY_FORMATS0x8DF8
 #define GL_NUM_SHADER_BINARY_FORMATS0x8DF9
-- 
2.5.0

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[Mesa-dev] [PATCH 04/16] mesa: Account for block depth in _mesa_format_image_size()

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/formats.c | 44 +++-
 1 file changed, 23 insertions(+), 21 deletions(-)

diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 6c23dda..cd96bd6 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -839,20 +839,22 @@ _mesa_format_image_size(mesa_format format, GLsizei width,
 GLsizei height, GLsizei depth)
 {
const struct gl_format_info *info = _mesa_get_format_info(format);
+   GLuint sz;
/* Strictly speaking, a conditional isn't needed here */
-   if (info->BlockWidth > 1 || info->BlockHeight > 1) {
+   if (info->BlockWidth > 1 || info->BlockHeight > 1 || info->BlockDepth > 1) {
   /* compressed format (2D only for now) */
-  const GLuint bw = info->BlockWidth, bh = info->BlockHeight;
+  const GLuint bw = info->BlockWidth;
+  const GLuint bh = info->BlockHeight;
+  const GLuint bd = info->BlockDepth;
   const GLuint wblocks = (width + bw - 1) / bw;
   const GLuint hblocks = (height + bh - 1) / bh;
-  const GLuint sz = wblocks * hblocks * info->BytesPerBlock;
-  return sz * depth;
-   }
-   else {
+  const GLuint dblocks = (depth + bd - 1) / bd;
+  sz = wblocks * hblocks * dblocks * info->BytesPerBlock;
+   } else
   /* non-compressed */
-  const GLuint sz = width * height * depth * info->BytesPerBlock;
-  return sz;
-   }
+  sz = width * height * depth * info->BytesPerBlock;
+
+   return sz;
 }
 
 
@@ -865,23 +867,23 @@ _mesa_format_image_size64(mesa_format format, GLsizei 
width,
   GLsizei height, GLsizei depth)
 {
const struct gl_format_info *info = _mesa_get_format_info(format);
+   uint64_t sz;
/* Strictly speaking, a conditional isn't needed here */
-   if (info->BlockWidth > 1 || info->BlockHeight > 1) {
+   if (info->BlockWidth > 1 || info->BlockHeight > 1 || info->BlockDepth > 1) {
   /* compressed format (2D only for now) */
-  const uint64_t bw = info->BlockWidth, bh = info->BlockHeight;
+  const uint64_t bw = info->BlockWidth;
+  const uint64_t bh = info->BlockHeight;
+  const uint64_t bd = info->BlockDepth;
   const uint64_t wblocks = (width + bw - 1) / bw;
   const uint64_t hblocks = (height + bh - 1) / bh;
-  const uint64_t sz = wblocks * hblocks * info->BytesPerBlock;
-  return sz * depth;
-   }
-   else {
+  const uint64_t dblocks = (depth + bd - 1) / bd;
+  sz = wblocks * hblocks * dblocks * info->BytesPerBlock;
+   } else
   /* non-compressed */
-  const uint64_t sz = ((uint64_t) width *
-   (uint64_t) height *
-   (uint64_t) depth *
-   info->BytesPerBlock);
-  return sz;
-   }
+  sz = ((uint64_t) width * (uint64_t) height *
+(uint64_t) depth * info->BytesPerBlock);
+
+   return sz;
 }
 
 
-- 
2.5.0

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[Mesa-dev] [PATCH 06/16] mesa: Add mesa formats for astc 3d formats

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/formats.h | 21 +
 1 file changed, 21 insertions(+)

diff --git a/src/mesa/main/formats.h b/src/mesa/main/formats.h
index 2f8f63c..50bd63f 100644
--- a/src/mesa/main/formats.h
+++ b/src/mesa/main/formats.h
@@ -635,6 +635,27 @@ typedef enum
MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10,
MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10,
MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12,
+
+   MESA_FORMAT_RGBA_ASTC_3x3x3,
+   MESA_FORMAT_RGBA_ASTC_4x3x3,
+   MESA_FORMAT_RGBA_ASTC_4x4x3,
+   MESA_FORMAT_RGBA_ASTC_4x4x4,
+   MESA_FORMAT_RGBA_ASTC_5x4x4,
+   MESA_FORMAT_RGBA_ASTC_5x5x4,
+   MESA_FORMAT_RGBA_ASTC_5x5x5,
+   MESA_FORMAT_RGBA_ASTC_6x5x5,
+   MESA_FORMAT_RGBA_ASTC_6x6x5,
+   MESA_FORMAT_RGBA_ASTC_6x6x6,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5,
+   MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6,
MESA_FORMAT_COUNT
 } mesa_format;
 
-- 
2.5.0

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[Mesa-dev] [PATCH 15/16] mesa: Enable translation between astc 3d gl formats and mesa formats

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/texcompress.c | 80 +
 1 file changed, 80 insertions(+)

diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 23b6fbc..c5a1129 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -612,6 +612,46 @@ _mesa_glenum_to_compressed_format(GLenum format)
   return MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10;
case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR:
   return MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12;
+   case GL_COMPRESSED_RGBA_ASTC_3x3x3_OES:
+  return MESA_FORMAT_RGBA_ASTC_3x3x3;
+   case GL_COMPRESSED_RGBA_ASTC_4x3x3_OES:
+  return MESA_FORMAT_RGBA_ASTC_4x3x3;
+   case GL_COMPRESSED_RGBA_ASTC_4x4x3_OES:
+  return MESA_FORMAT_RGBA_ASTC_4x4x3;
+   case GL_COMPRESSED_RGBA_ASTC_4x4x4_OES:
+  return MESA_FORMAT_RGBA_ASTC_4x4x4;
+   case GL_COMPRESSED_RGBA_ASTC_5x4x4_OES:
+  return MESA_FORMAT_RGBA_ASTC_5x4x4;
+   case GL_COMPRESSED_RGBA_ASTC_5x5x4_OES:
+  return MESA_FORMAT_RGBA_ASTC_5x5x4;
+   case GL_COMPRESSED_RGBA_ASTC_5x5x5_OES:
+  return MESA_FORMAT_RGBA_ASTC_5x5x5;
+   case GL_COMPRESSED_RGBA_ASTC_6x5x5_OES:
+  return MESA_FORMAT_RGBA_ASTC_6x5x5;
+   case GL_COMPRESSED_RGBA_ASTC_6x6x5_OES:
+  return MESA_FORMAT_RGBA_ASTC_6x6x5;
+   case GL_COMPRESSED_RGBA_ASTC_6x6x6_OES:
+  return MESA_FORMAT_RGBA_ASTC_6x6x6;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_3x3x3_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x3x3_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x3_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x4_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4x4_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x4_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x5_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5x5_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x5_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5;
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x6_OES:
+  return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6;
 
default:
   return MESA_FORMAT_NONE;
@@ -760,6 +800,46 @@ _mesa_compressed_format_to_glenum(struct gl_context *ctx, 
mesa_format mesaFormat
case MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12:
   return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR;
 
+   case MESA_FORMAT_RGBA_ASTC_3x3x3:
+  return GL_COMPRESSED_RGBA_ASTC_3x3x3_OES;
+   case MESA_FORMAT_RGBA_ASTC_4x3x3:
+  return GL_COMPRESSED_RGBA_ASTC_4x3x3_OES;
+   case MESA_FORMAT_RGBA_ASTC_4x4x3:
+  return GL_COMPRESSED_RGBA_ASTC_4x4x3_OES;
+   case MESA_FORMAT_RGBA_ASTC_4x4x4:
+  return GL_COMPRESSED_RGBA_ASTC_4x4x4_OES;
+   case MESA_FORMAT_RGBA_ASTC_5x4x4:
+  return GL_COMPRESSED_RGBA_ASTC_5x4x4_OES;
+   case MESA_FORMAT_RGBA_ASTC_5x5x4:
+  return GL_COMPRESSED_RGBA_ASTC_5x5x4_OES;
+   case MESA_FORMAT_RGBA_ASTC_5x5x5:
+  return GL_COMPRESSED_RGBA_ASTC_5x5x5_OES;
+   case MESA_FORMAT_RGBA_ASTC_6x5x5:
+  return GL_COMPRESSED_RGBA_ASTC_6x5x5_OES;
+   case MESA_FORMAT_RGBA_ASTC_6x6x5:
+  return GL_COMPRESSED_RGBA_ASTC_6x6x5_OES;
+   case MESA_FORMAT_RGBA_ASTC_6x6x6:
+  return GL_COMPRESSED_RGBA_ASTC_6x6x6_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_3x3x3_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x3x3_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x3_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x4_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4x4_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x4_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x5_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5x5_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x5_OES;
+   case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6:
+  return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x6_OES;
default:
   _mesa_problem(ctx, "Unexpected mesa texture format in"
 " _mesa_compressed_format_to_glenum()");
-- 
2.5.0

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[Mesa-dev] [PATCH 14/16] mesa: Handle astc 3d formats in _mesa_get_compressed_formats()

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/texcompress.c | 29 +
 1 file changed, 29 insertions(+)

diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 9f2f171..23b6fbc 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -438,6 +438,35 @@ _mesa_get_compressed_formats(struct gl_context *ctx, GLint 
*formats)
   }
}
 
+   if (_mesa_is_gles3(ctx) &&
+   ctx->Extensions.OES_texture_compression_astc) {
+  if (formats) {
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_3x3x3_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_4x3x3_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_4x4x3_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_4x4x4_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_5x4x4_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_5x5x4_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_5x5x5_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_6x5x5_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_6x6x5_OES;
+ formats[n++] = GL_COMPRESSED_RGBA_ASTC_6x6x6_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_3x3x3_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x3x3_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x3_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x4_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4x4_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x4_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x5_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5x5_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x5_OES;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x6_OES;
+  }
+  else {
+ n += 20;
+  }
+   }
+
return n;
 }
 
-- 
2.5.0

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[Mesa-dev] [PATCH 08/16] mesa: Add OES_texture_compression_astc to extension table and gl_extensions

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/extensions_table.h | 1 +
 src/mesa/main/mtypes.h   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 674eb5c..4b04f6a 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -338,6 +338,7 @@ EXT(OES_stencil_wrap, dummy_true
 EXT(OES_surfaceless_context , dummy_true   
  ,  x ,  x , ES1, ES2, 2012)
 EXT(OES_texture_3D  , dummy_true   
  ,  x ,  x ,  x , ES2, 2005)
 EXT(OES_texture_border_clamp, ARB_texture_border_clamp 
  ,  x ,  x ,  x , ES2, 2014)
+EXT(OES_texture_compression_astc, OES_texture_compression_astc 
  ,  x ,  x , ES1, ES2, 2015)
 EXT(OES_texture_cube_map, ARB_texture_cube_map 
  ,  x ,  x , ES1,  x , 2007)
 EXT(OES_texture_env_crossbar, ARB_texture_env_crossbar 
  ,  x ,  x , ES1,  x , 2005)
 EXT(OES_texture_float   , OES_texture_float
  ,  x ,  x ,  x , ES2, 2005)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index b99f41c..fe2e0c6 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3940,6 +3940,7 @@ struct gl_extensions
GLboolean OES_texture_half_float_linear;
GLboolean OES_compressed_ETC1_RGB8_texture;
GLboolean OES_geometry_shader;
+   GLboolean OES_texture_compression_astc;
GLboolean extension_sentinel;
/** The extension string */
const GLubyte *String;
-- 
2.5.0

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[Mesa-dev] [PATCH 11/16] mesa: Add a helper function is_astc_3d_format()

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/glformats.c | 32 
 1 file changed, 32 insertions(+)

diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index edfd7d6..607db95 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -863,6 +863,38 @@ _mesa_is_astc_format(GLenum internalFormat)
}
 }
 
+/**
+ * Test if the given format is an ASTC 3D format.
+ */
+static bool
+is_astc_3d_format(GLenum internalFormat)
+{
+   switch (internalFormat) {
+   case GL_COMPRESSED_RGBA_ASTC_3x3x3_OES:
+   case GL_COMPRESSED_RGBA_ASTC_4x3x3_OES:
+   case GL_COMPRESSED_RGBA_ASTC_4x4x3_OES:
+   case GL_COMPRESSED_RGBA_ASTC_4x4x4_OES:
+   case GL_COMPRESSED_RGBA_ASTC_5x4x4_OES:
+   case GL_COMPRESSED_RGBA_ASTC_5x5x4_OES:
+   case GL_COMPRESSED_RGBA_ASTC_5x5x5_OES:
+   case GL_COMPRESSED_RGBA_ASTC_6x5x5_OES:
+   case GL_COMPRESSED_RGBA_ASTC_6x6x5_OES:
+   case GL_COMPRESSED_RGBA_ASTC_6x6x6_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_3x3x3_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x3x3_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x3_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_4x4x4_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x4x4_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x4_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_5x5x5_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x5x5_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x5_OES:
+   case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_6x6x6_OES:
+  return true;
+   default:
+  return false;
+   }
+}
 
 /**
  * Test if the given format is an integer (non-normalized) format.
-- 
2.5.0

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[Mesa-dev] [PATCH 01/16] mesa: Add block depth field in struct gl_format_info

[Anuj Phogat]

This will be later required for 3D ASTC formats.

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/format_info.py   |   5 +-
 src/mesa/main/format_parser.py |  15 +-
 src/mesa/main/formats.c|   4 +-
 src/mesa/main/formats.csv  | 529 +
 4 files changed, 279 insertions(+), 274 deletions(-)

diff --git a/src/mesa/main/format_info.py b/src/mesa/main/format_info.py
index 50626a85..729edbb 100644
--- a/src/mesa/main/format_info.py
+++ b/src/mesa/main/format_info.py
@@ -185,8 +185,9 @@ for fmat in formats:
 
print '  {0:d},'.format(fmat.colorspace == 'srgb')
 
-   print '  {0}, {1}, {2},'.format(fmat.block_width, fmat.block_height,
-   int(fmat.block_size() / 8))
+   print '  {0}, {1}, {2}, {3},'.format(fmat.block_width, 
fmat.block_height,
+fmat.block_depth,
+int(fmat.block_size() / 8))
 
print '  {{ {0} }},'.format(', '.join(map(str, fmat.swizzle)))
if fmat.is_array():
diff --git a/src/mesa/main/format_parser.py b/src/mesa/main/format_parser.py
index a29f207..6cd2fbc 100755
--- a/src/mesa/main/format_parser.py
+++ b/src/mesa/main/format_parser.py
@@ -227,7 +227,7 @@ class Swizzle:
 class Format:
"""Describes a pixel format."""
 
-   def __init__(self, name, layout, block_width, block_height, channels, 
swizzle, colorspace):
+   def __init__(self, name, layout, block_width, block_height, block_depth, 
channels, swizzle, colorspace):
   """Constructs a Format from some metadata and a list of channels.
 
   The channel objects must be unique to this Format and should not be
@@ -241,6 +241,7 @@ class Format:
   layout -- One of 'array', 'packed' 'other', or a compressed layout
   block_width -- The block width if the format is compressed, 1 otherwise
   block_height -- The block height if the format is compressed, 1 otherwise
+  block_depth -- The block depth if the format is compressed, 1 otherwise
   channels -- A list of Channel objects
   swizzle -- A Swizzle from this format to rgba
   colorspace -- one of 'rgb', 'srgb', 'yuv', or 'zs'
@@ -249,6 +250,7 @@ class Format:
   self.layout = layout
   self.block_width = block_width
   self.block_height = block_height
+  self.block_depth = block_depth
   self.channels = channels
   assert isinstance(swizzle, Swizzle)
   self.swizzle = swizzle
@@ -361,7 +363,7 @@ class Format:
 
def is_compressed(self):
   """Returns true if this is a compressed format."""
-  return self.block_width != 1 or self.block_height != 1
+  return self.block_width != 1 or self.block_height != 1 or 
self.block_depth != 1
 
def is_int(self):
   """Returns true if this format is an integer format.
@@ -555,12 +557,13 @@ def parse(filename):
  layout = fields[1]
  block_width = int(fields[2])
  block_height = int(fields[3])
- colorspace = fields[9]
+ block_depth = int(fields[4])
+ colorspace = fields[10]
 
  try:
-swizzle = Swizzle(fields[8])
+swizzle = Swizzle(fields[9])
  except:
 sys.exit("error parsing swizzle for format " + name)
- channels = _parse_channels(fields[4:8], layout, colorspace, swizzle)
+ channels = _parse_channels(fields[5:9], layout, colorspace, swizzle)
 
- yield Format(name, layout, block_width, block_height, channels, 
swizzle, colorspace)
+ yield Format(name, layout, block_width, block_height, block_depth, 
channels, swizzle, colorspace)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index 41d40a5..3d2349b 100644
--- a/src/mesa/main/formats.c
+++ b/src/mesa/main/formats.c
@@ -68,9 +68,9 @@ struct gl_format_info
bool IsSRGBFormat;
 
/**
-* To describe compressed formats.  If not compressed, Width=Height=1.
+* To describe compressed formats.  If not compressed, Width=Height=Depth=1.
 */
-   GLubyte BlockWidth, BlockHeight;
+   GLubyte BlockWidth, BlockHeight, BlockDepth;
GLubyte BytesPerBlock;
 
uint8_t Swizzle[4];
diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
index a663c1e..8eb69ad 100644
--- a/src/mesa/main/formats.csv
+++ b/src/mesa/main/formats.csv
@@ -33,6 +33,7 @@
 # - layout
 # - pixel block's width
 # - pixel block's height
+# - pixel block's depth
 # - channel encoding (only meaningful for array or packed layout), containing 
for each
 #   channel the following information:
 #   - type, one of
@@ -48,303 +49,303 @@
 
 # None
 # Described as regular uint_8 bytes, i.e. MESA_FORMAT_R8_USCALED
-MESA_FORMAT_NONE  , other , 1, 1, x8  , , ,
 , 0001, rgb
+MESA_FORMAT_NONE  , other , 1, 1, 1, x8  , , , 
, 0001, rgb
 
 # Packed unorm formats
-MESA_FORMAT_A8B8G8R8_UNORM, packed, 1, 1, 

[Mesa-dev] [PATCH 07/16] mesa: Add entries for astc 3d formats initializing struct gl_format_info

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/formats.csv | 21 +
 1 file changed, 21 insertions(+)

diff --git a/src/mesa/main/formats.csv b/src/mesa/main/formats.csv
index 8eb69ad..285921e 100644
--- a/src/mesa/main/formats.csv
+++ b/src/mesa/main/formats.csv
@@ -349,3 +349,24 @@ MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8, astc  ,10, 8, 
1, x128, , ,
 MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10   , astc  ,10,10, 1, x128, , , 
, xyzw, srgb
 MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10   , astc  ,12,10, 1, x128, , , 
, xyzw, srgb
 MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12   , astc  ,12,12, 1, x128, , , 
, xyzw, srgb
+
+MESA_FORMAT_RGBA_ASTC_3x3x3   , astc  , 3, 3, 3, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_4x3x3   , astc  , 4, 3, 3, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_4x4x3   , astc  , 4, 4, 3, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_4x4x4   , astc  , 4, 4, 4, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_5x4x4   , astc  , 5, 4, 4, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_5x5x4   , astc  , 5, 5, 4, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_5x5x5   , astc  , 5, 5, 5, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_6x5x5   , astc  , 6, 5, 5, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_6x6x5   , astc  , 6, 6, 5, x128, , , 
, xyzw, rgb
+MESA_FORMAT_RGBA_ASTC_6x6x6   , astc  , 6, 6, 6, x128, , , 
, xyzw, rgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3   , astc  , 3, 3, 3, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3   , astc  , 4, 3, 3, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3   , astc  , 4, 4, 3, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4   , astc  , 4, 4, 4, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4   , astc  , 5, 4, 4, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4   , astc  , 5, 5, 4, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5   , astc  , 5, 5, 5, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5   , astc  , 6, 5, 5, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5   , astc  , 6, 6, 5, x128, , , 
, xyzw, srgb
+MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6   , astc  , 6, 6, 6, x128, , , 
, xyzw, srgb
-- 
2.5.0

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[Mesa-dev] [PATCH 09/16] mesa: Align the values of #define's in glheader.h

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/main/glheader.h | 58 
 1 file changed, 29 insertions(+), 29 deletions(-)

diff --git a/src/mesa/main/glheader.h b/src/mesa/main/glheader.h
index a2d98d4..9d299e8 100644
--- a/src/mesa/main/glheader.h
+++ b/src/mesa/main/glheader.h
@@ -69,17 +69,17 @@ typedef void *GLeglImageOES;
 
 
 #ifndef GL_OES_draw_texture
-#define GL_TEXTURE_CROP_RECT_OES  0x8B9D
+#define GL_TEXTURE_CROP_RECT_OES0x8B9D
 #endif
 
 
 #ifndef GL_PROGRAM_BINARY_LENGTH_OES
-#define GL_PROGRAM_BINARY_LENGTH_OES 0x8741
+#define GL_PROGRAM_BINARY_LENGTH_OES0x8741
 #endif
 
 /* GLES 2.0 tokens */
 #ifndef GL_RGB565
-#define GL_RGB565 0x8D62
+#define GL_RGB565   0x8D62
 #endif
 
 #ifndef GL_TEXTURE_GEN_STR_OES
@@ -100,17 +100,17 @@ typedef void *GLeglImageOES;
 #endif
 
 #ifndef GL_ES_VERSION_2_0
-#define GL_SHADER_BINARY_FORMATS0x8DF8
-#define GL_NUM_SHADER_BINARY_FORMATS0x8DF9
-#define GL_SHADER_COMPILER  0x8DFA
-#define GL_MAX_VERTEX_UNIFORM_VECTORS   0x8DFB
-#define GL_MAX_VARYING_VECTORS  0x8DFC
-#define GL_MAX_FRAGMENT_UNIFORM_VECTORS 0x8DFD
+#define GL_SHADER_BINARY_FORMATS0x8DF8
+#define GL_NUM_SHADER_BINARY_FORMATS0x8DF9
+#define GL_SHADER_COMPILER  0x8DFA
+#define GL_MAX_VERTEX_UNIFORM_VECTORS   0x8DFB
+#define GL_MAX_VARYING_VECTORS  0x8DFC
+#define GL_MAX_FRAGMENT_UNIFORM_VECTORS 0x8DFD
 #endif
 
 #ifndef GL_ATI_texture_compression_3dc
-#define GL_ATI_texture_compression_3dc 1
-#define GL_COMPRESSED_LUMINANCE_ALPHA_3DC_ATI 0x8837
+#define GL_ATI_texture_compression_3dc  1
+#define GL_COMPRESSED_LUMINANCE_ALPHA_3DC_ATI   0x8837
 #endif
 
 #ifndef GL_OES_compressed_ETC1_RGB8_texture
@@ -121,7 +121,7 @@ typedef void *GLeglImageOES;
 /* Inexplicably, GL_HALF_FLOAT_OES has a different value than GL_HALF_FLOAT.
  */
 #ifndef GL_HALF_FLOAT_OES
-#define GL_HALF_FLOAT_OES 0x8D61
+#define GL_HALF_FLOAT_OES   0x8D61
 #endif
 
 
@@ -132,29 +132,29 @@ typedef void *GLeglImageOES;
  * so we need a value that's different from any of the
  * GL_VERTEX/FRAGMENT/GEOMETRY_PROGRAM tokens.
  */
-#define GL_SHADER_PROGRAM_MESA 0x
+#define GL_SHADER_PROGRAM_MESA  0x
 
 
 /* Several fields of struct gl_config can take these as values.  Since
  * GLX header files may not be available everywhere they need to be used,
  * redefine them here.
  */
-#define GLX_NONE   0x8000
-#define GLX_SLOW_CONFIG0x8001
-#define GLX_TRUE_COLOR 0x8002
-#define GLX_DIRECT_COLOR   0x8003
-#define GLX_PSEUDO_COLOR   0x8004
-#define GLX_STATIC_COLOR   0x8005
-#define GLX_GRAY_SCALE 0x8006
-#define GLX_STATIC_GRAY0x8007
-#define GLX_TRANSPARENT_RGB0x8008
-#define GLX_TRANSPARENT_INDEX  0x8009
-#define GLX_NON_CONFORMANT_CONFIG  0x800D
-#define GLX_SWAP_EXCHANGE_OML  0x8061
-#define GLX_SWAP_COPY_OML  0x8062
-#define GLX_SWAP_UNDEFINED_OML 0x8063
-
-#define GLX_DONT_CARE  0x
+#define GLX_NONE0x8000
+#define GLX_SLOW_CONFIG 0x8001
+#define GLX_TRUE_COLOR  0x8002
+#define GLX_DIRECT_COLOR0x8003
+#define GLX_PSEUDO_COLOR0x8004
+#define GLX_STATIC_COLOR0x8005
+#define GLX_GRAY_SCALE  0x8006
+#define GLX_STATIC_GRAY 0x8007
+#define GLX_TRANSPARENT_RGB 0x8008
+#define GLX_TRANSPARENT_INDEX   0x8009
+#define GLX_NON_CONFORMANT_CONFIG   0x800D
+#define GLX_SWAP_EXCHANGE_OML   0x8061
+#define GLX_SWAP_COPY_OML   0x8062
+#define GLX_SWAP_UNDEFINED_OML  0x8063
+
+#define GLX_DONT_CARE   0x
 
 
 #ifdef __cplusplus
-- 
2.5.0

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[Mesa-dev] [PATCH 05/16] glapi: Update dispatch XML files for OES_texture_compression_astc.xml

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mapi/glapi/gen/Makefile.am |  1 +
 .../glapi/gen/OES_texture_compression_astc.xml | 61 ++
 src/mapi/glapi/gen/gl_API.xml  |  2 +
 3 files changed, 64 insertions(+)
 create mode 100644 src/mapi/glapi/gen/OES_texture_compression_astc.xml

diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
index 8421af4..d94fd0a 100644
--- a/src/mapi/glapi/gen/Makefile.am
+++ b/src/mapi/glapi/gen/Makefile.am
@@ -209,6 +209,7 @@ API_XML = \
OES_EGL_image.xml \
OES_fixed_point.xml \
OES_single_precision.xml \
+   OES_texture_compression_astc.xml \
GL3x.xml \
GL4x.xml
 
diff --git a/src/mapi/glapi/gen/OES_texture_compression_astc.xml 
b/src/mapi/glapi/gen/OES_texture_compression_astc.xml
new file mode 100644
index 000..4e8de71
--- /dev/null
+++ b/src/mapi/glapi/gen/OES_texture_compression_astc.xml
@@ -0,0 +1,61 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 8b49f91..03adf08 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -8271,6 +8271,8 @@
 
 
 
+http://www.w3.org/2001/XInclude"/>
+
 http://www.w3.org/2001/XInclude"/>
 
 http://www.w3.org/2001/XInclude"/>
-- 
2.5.0

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[Mesa-dev] [PATCH 02/16] mesa: Add support to query block depth using _mesa_get_format_block_size()

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i915/intel_mipmap_tree.c|  8 
 src/mesa/drivers/dri/i915/intel_tex_layout.c |  4 ++--
 src/mesa/drivers/dri/i965/brw_tex_layout.c   | 21 +++--
 src/mesa/drivers/dri/i965/intel_copy_image.c | 14 +++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c|  8 
 src/mesa/drivers/dri/nouveau/nouveau_util.h  |  8 ++--
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 11 +++
 src/mesa/drivers/dri/radeon/radeon_texture.c |  4 ++--
 src/mesa/main/copyimage.c|  6 +++---
 src/mesa/main/formatquery.c  |  4 ++--
 src/mesa/main/formats.c  |  4 +++-
 src/mesa/main/formats.h  |  3 ++-
 src/mesa/main/texcompress.c  |  8 
 src/mesa/main/texgetimage.c  |  4 ++--
 src/mesa/main/teximage.c |  4 ++--
 src/mesa/main/texstore.c |  4 ++--
 src/mesa/swrast/s_texfetch.c |  4 ++--
 src/mesa/swrast/s_texture.c  |  4 ++--
 18 files changed, 67 insertions(+), 56 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
index 5cbf763..947a556 100644
--- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c
@@ -90,8 +90,8 @@ intel_miptree_create_layout(struct intel_context *intel,
/* The cpp is bytes per (1, blockheight)-sized block for compressed
 * textures.  This is why you'll see divides by blockheight all over
 */
-   unsigned bw, bh;
-   _mesa_get_format_block_size(format, , );
+   unsigned bw, bh, bd;
+   _mesa_get_format_block_size(format, , , );
assert(_mesa_get_format_bytes(mt->format) % bw == 0);
mt->cpp = _mesa_get_format_bytes(mt->format) / bw;
 
@@ -726,7 +726,7 @@ intel_miptree_map_gtt(struct intel_context *intel,
  struct intel_miptree_map *map,
  unsigned int level, unsigned int slice)
 {
-   unsigned int bw, bh;
+   unsigned int bw, bh, bd;
void *base;
unsigned int image_x, image_y;
int x = map->x;
@@ -736,7 +736,7 @@ intel_miptree_map_gtt(struct intel_context *intel,
 * row of blocks.  intel_miptree_get_image_offset() already does
 * the divide.
 */
-   _mesa_get_format_block_size(mt->format, , );
+   _mesa_get_format_block_size(mt->format, , , );
assert(y % bh == 0);
y /= bh;
 
diff --git a/src/mesa/drivers/dri/i915/intel_tex_layout.c 
b/src/mesa/drivers/dri/i915/intel_tex_layout.c
index 01ea165..401282c 100644
--- a/src/mesa/drivers/dri/i915/intel_tex_layout.c
+++ b/src/mesa/drivers/dri/i915/intel_tex_layout.c
@@ -69,8 +69,8 @@ intel_horizontal_texture_alignment_unit(struct intel_context 
*intel,
/* The hardware alignment requirements for compressed textures
 * happen to match the block boundaries.
 */
-  unsigned int i, j;
-  _mesa_get_format_block_size(format, , );
+  unsigned int i, j, k;
+  _mesa_get_format_block_size(format, , , );
   return i;
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index a294829..67923e9 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -296,9 +296,9 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
unsigned width = mt->physical_width0;
unsigned height = mt->physical_height0;
unsigned depth = mt->physical_depth0; /* number of array layers. */
-   unsigned int bw, bh;
+   unsigned int bw, bh, bd;
 
-   _mesa_get_format_block_size(mt->format, , );
+   _mesa_get_format_block_size(mt->format, , , );
 
mt->total_width = mt->physical_width0;
 
@@ -515,9 +515,9 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
mt->total_height = 0;
 
unsigned ysum = 0;
-   unsigned bh, bw;
+   unsigned bh, bw, bd;
 
-   _mesa_get_format_block_size(mt->format, , );
+   _mesa_get_format_block_size(mt->format, , , );
 
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
   unsigned WL = MAX2(mt->physical_width0 >> level, 1);
@@ -745,10 +745,11 @@ intel_miptree_set_alignment(struct brw_context *brw,
  mt->valign = 32;
   }
} else if (mt->compressed) {
-   /* The hardware alignment requirements for compressed textures
-* happen to match the block boundaries.
-*/
-  _mesa_get_format_block_size(mt->format, >halign, >valign);
+  unsigned int bd;
+  /* The hardware alignment requirements for compressed textures
+   * happen to match the block boundaries.
+   */
+  _mesa_get_format_block_size(mt->format, >halign, >valign, );
 
   /* On Gen9+ we can pick our own alignment for compressed textures but it
* has to be a multiple of the block size. The 

Re: [Mesa-dev] [PATCH] r600g: Add support for PK2H/UP2H

[Dieter Nützel]

Ping.

Ilia and Marek voted for it.

Any progress?

Dieter


[Mesa-dev] [PATCH] r600g: Add support for PK2H/UP2H

Glenn Kennard glenn.kennard at gmail.com
Sun Jan 3 14:47:18 PST 2016
Previous message: [Mesa-dev] [PATCH 1/2] WIP gallivm: add support for
PK2H/UP2H Next message: [Mesa-dev] [PATCH] mesa: use gl_shader_variable 
in
program resource list Messages sorted by: [ date ] [ thread ] [ subject 
] [

author ]
Based off of Ilia's original patch, but with output values replicated 
so

that it matches the TGSI semantics.

Signed-off-by: Glenn Kennard 
---

 src/gallium/drivers/r600/r600_pipe.c   |   2 +-
 src/gallium/drivers/r600/r600_shader.c | 107
 +++-- 2 files changed, 104 insertions(+), 
5

 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c index d71082f..3b5d26c 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -328,6 +328,7 @@ static int r600_get_param(struct pipe_screen* 
pscreen,

enum pipe_cap param)>
case PIPE_CAP_TEXTURE_QUERY_LOD:
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:

case PIPE_CAP_SAMPLER_VIEW_TARGET:
+   case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
return family >= CHIP_CEDAR ? 1 : 0;

case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return family >= CHIP_CEDAR ? 4 : 0;

@@ -349,7 +350,6 @@ static int r600_get_param(struct pipe_screen* 
pscreen,

enum pipe_cap param)>
case PIPE_CAP_SHAREABLE_SHADERS:
case PIPE_CAP_CLEAR_TEXTURE:

case PIPE_CAP_DRAW_PARAMETERS:
-   case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
return 0;

case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c index 9c040ae..7b1eade 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -8960,6 +8960,105 @@ static int tgsi_umad(struct r600_shader_ctx 
*ctx)


return 0;

 }

+static int tgsi_pk2h(struct r600_shader_ctx *ctx)
+{
+   struct tgsi_full_instruction *inst =
>parse.FullToken.FullInstruction;
+   struct r600_bytecode_alu alu;
+   int r, i;
+   int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+
+   /* temp.xy = f32_to_f16(src) */
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP1_FLT32_TO_FLT16;
+   alu.dst.chan = 0;
+   alu.dst.sel = ctx->temp_reg;
+   alu.dst.write = 1;
+   r600_bytecode_src([0], >src[0], 0);
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+   alu.dst.chan = 1;
+   r600_bytecode_src([0], >src[0], 1);
+   alu.last = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+
+   /* dst.x = temp.y * 0x1 + temp.x */
+   for (i = 0; i < lasti + 1; i++) {
+   if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
+   continue;
+
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP3_MULADD_UINT24;
+   alu.is_op3 = 1;
+   tgsi_dst(ctx, >Dst[0], i, );
+   alu.last = i == lasti;
+   alu.src[0].sel = ctx->temp_reg;
+   alu.src[0].chan = 1;
+   alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+   alu.src[1].value = 0x1;
+   alu.src[2].sel = ctx->temp_reg;
+   alu.src[2].chan = 0;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+   }
+
+   return 0;
+}
+
+static int tgsi_up2h(struct r600_shader_ctx *ctx)
+{
+   struct tgsi_full_instruction *inst =
>parse.FullToken.FullInstruction;
+   struct r600_bytecode_alu alu;
+   int r, i;
+   int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+
+   /* temp.x = src.x */
+   /* note: no need to mask out the high bits */
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP1_MOV;
+   alu.dst.chan = 0;
+   alu.dst.sel = ctx->temp_reg;
+   alu.dst.write = 1;
+   r600_bytecode_src([0], >src[0], 0);
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+
+   /* temp.y = src.x >> 16 */
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP2_LSHR_INT;
+   alu.dst.chan = 1;
+   alu.dst.sel = ctx->temp_reg;
+   alu.dst.write = 1;
+   r600_bytecode_src([0], >src[0], 0);
+   alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
+   alu.src[1].value = 16;
+   alu.last = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+
+   /* dst.wz = dst.xy = f16_to_f32(temp.xy) */
+   for (i = 0; i < lasti + 1; i++) {
+   if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
+   continue;
+ 

[Mesa-dev] [PATCH] gallium/tests: silence warning in compute.c

[Brian Paul]

compute.c: In function ‘launch_grid’:
compute.c:435:20: warning: assignment discards ‘const’ qualifier from pointer 
target type [enabled by default]
 info.input = input;
^

Maybe the pipe_grid_info::input field should be const void *?
---
 src/gallium/tests/trivial/compute.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/tests/trivial/compute.c 
b/src/gallium/tests/trivial/compute.c
index 288cf2a..5d5e0b0 100644
--- a/src/gallium/tests/trivial/compute.c
+++ b/src/gallium/tests/trivial/compute.c
@@ -421,7 +421,7 @@ static void destroy_globals(struct context *ctx)
 
 static void launch_grid(struct context *ctx, const uint *block_layout,
 const uint *grid_layout, uint32_t pc,
-const void *input)
+void *input)
 {
 struct pipe_context *pipe = ctx->pipe;
 struct pipe_grid_info info;
-- 
1.9.1

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[Mesa-dev] [PATCH 2/3] svga: add new flush-time HUD query

[Brian Paul]

To measure the time spent flushing the command buffer.
---
 src/gallium/drivers/svga/svga_context.c|  4 
 src/gallium/drivers/svga/svga_context.h| 16 +---
 src/gallium/drivers/svga/svga_pipe_query.c |  9 +
 src/gallium/drivers/svga/svga_screen.c |  2 ++
 4 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_context.c 
b/src/gallium/drivers/svga/svga_context.c
index 32917cd..da42814 100644
--- a/src/gallium/drivers/svga/svga_context.c
+++ b/src/gallium/drivers/svga/svga_context.c
@@ -31,6 +31,7 @@
 #include "util/u_memory.h"
 #include "util/u_bitmask.h"
 #include "util/u_upload_mgr.h"
+#include "os/os_time.h"
 
 #include "svga_context.h"
 #include "svga_screen.h"
@@ -299,6 +300,7 @@ void svga_context_flush( struct svga_context *svga,
 {
struct svga_screen *svgascreen = svga_screen(svga->pipe.screen);
struct pipe_fence_handle *fence = NULL;
+   uint64_t t0;
 
svga->curr.nr_fbs = 0;
 
@@ -312,7 +314,9 @@ void svga_context_flush( struct svga_context *svga,
 
/* Flush pending commands to hardware:
 */
+   t0 = os_time_get();
svga->swc->flush(svga->swc, );
+   svga->hud.flush_time += (os_time_get() - t0);
 
svga->hud.num_flushes++;
 
diff --git a/src/gallium/drivers/svga/svga_context.h 
b/src/gallium/drivers/svga/svga_context.h
index 2a1ad14..61e82a2 100644
--- a/src/gallium/drivers/svga/svga_context.h
+++ b/src/gallium/drivers/svga/svga_context.h
@@ -53,16 +53,17 @@
 #define SVGA_QUERY_NUM_RESOURCES_MAPPED(PIPE_QUERY_DRIVER_SPECIFIC + 5)
 #define SVGA_QUERY_NUM_BYTES_UPLOADED  (PIPE_QUERY_DRIVER_SPECIFIC + 6)
 #define SVGA_QUERY_COMMAND_BUFFER_SIZE (PIPE_QUERY_DRIVER_SPECIFIC + 7)
+#define SVGA_QUERY_FLUSH_TIME  (PIPE_QUERY_DRIVER_SPECIFIC + 8)
 
 /* running total counters */
-#define SVGA_QUERY_MEMORY_USED (PIPE_QUERY_DRIVER_SPECIFIC + 8)
-#define SVGA_QUERY_NUM_SHADERS (PIPE_QUERY_DRIVER_SPECIFIC + 9)
-#define SVGA_QUERY_NUM_RESOURCES   (PIPE_QUERY_DRIVER_SPECIFIC + 10)
-#define SVGA_QUERY_NUM_STATE_OBJECTS   (PIPE_QUERY_DRIVER_SPECIFIC + 11)
-#define SVGA_QUERY_NUM_SURFACE_VIEWS   (PIPE_QUERY_DRIVER_SPECIFIC + 12)
-#define SVGA_QUERY_NUM_GENERATE_MIPMAP (PIPE_QUERY_DRIVER_SPECIFIC + 13)
+#define SVGA_QUERY_MEMORY_USED (PIPE_QUERY_DRIVER_SPECIFIC + 9)
+#define SVGA_QUERY_NUM_SHADERS (PIPE_QUERY_DRIVER_SPECIFIC + 10)
+#define SVGA_QUERY_NUM_RESOURCES   (PIPE_QUERY_DRIVER_SPECIFIC + 11)
+#define SVGA_QUERY_NUM_STATE_OBJECTS   (PIPE_QUERY_DRIVER_SPECIFIC + 12)
+#define SVGA_QUERY_NUM_SURFACE_VIEWS   (PIPE_QUERY_DRIVER_SPECIFIC + 13)
+#define SVGA_QUERY_NUM_GENERATE_MIPMAP (PIPE_QUERY_DRIVER_SPECIFIC + 14)
 /*SVGA_QUERY_MAX has to be last because it is size of an array*/
-#define SVGA_QUERY_MAX (PIPE_QUERY_DRIVER_SPECIFIC + 14)
+#define SVGA_QUERY_MAX (PIPE_QUERY_DRIVER_SPECIFIC + 15)
 
 /**
  * Maximum supported number of constant buffers per shader
@@ -504,6 +505,7 @@ struct svga_context
   uint64_t map_buffer_time;  /**< SVGA_QUERY_MAP_BUFFER_TIME */
   uint64_t num_resources_mapped; /**< SVGA_QUERY_NUM_RESOURCES_MAPPED */
   uint64_t command_buffer_size;  /**< SVGA_QUERY_COMMAND_BUFFER_SIZE */
+  uint64_t flush_time;   /**< SVGA_QUERY_FLUSH_TIME */
   uint64_t num_shaders;  /**< SVGA_QUERY_NUM_SHADERS */
   uint64_t num_state_objects;/**< SVGA_QUERY_NUM_STATE_OBJECTS */
   uint64_t num_surface_views;/**< SVGA_QUERY_NUM_SURFACE_VIEWS */
diff --git a/src/gallium/drivers/svga/svga_pipe_query.c 
b/src/gallium/drivers/svga/svga_pipe_query.c
index 08adaed..15decd4 100644
--- a/src/gallium/drivers/svga/svga_pipe_query.c
+++ b/src/gallium/drivers/svga/svga_pipe_query.c
@@ -728,6 +728,7 @@ svga_create_query(struct pipe_context *pipe,
case SVGA_QUERY_NUM_RESOURCES_MAPPED:
case SVGA_QUERY_NUM_BYTES_UPLOADED:
case SVGA_QUERY_COMMAND_BUFFER_SIZE:
+   case SVGA_QUERY_FLUSH_TIME:
case SVGA_QUERY_MEMORY_USED:
case SVGA_QUERY_NUM_SHADERS:
case SVGA_QUERY_NUM_RESOURCES:
@@ -798,6 +799,7 @@ svga_destroy_query(struct pipe_context *pipe, struct 
pipe_query *q)
case SVGA_QUERY_NUM_RESOURCES_MAPPED:
case SVGA_QUERY_NUM_BYTES_UPLOADED:
case SVGA_QUERY_COMMAND_BUFFER_SIZE:
+   case SVGA_QUERY_FLUSH_TIME:
case SVGA_QUERY_MEMORY_USED:
case SVGA_QUERY_NUM_SHADERS:
case SVGA_QUERY_NUM_RESOURCES:
@@ -889,6 +891,9 @@ svga_begin_query(struct pipe_context *pipe, struct 
pipe_query *q)
case SVGA_QUERY_COMMAND_BUFFER_SIZE:
   sq->begin_count = svga->hud.command_buffer_size;
   break;
+   case SVGA_QUERY_FLUSH_TIME:
+  sq->begin_count = svga->hud.flush_time;
+  break;
case SVGA_QUERY_MEMORY_USED:
case SVGA_QUERY_NUM_SHADERS:
case SVGA_QUERY_NUM_RESOURCES:
@@ -986,6 +991,9 @@ svga_end_query(struct pipe_context *pipe, struct pipe_query 
*q)
case 

[Mesa-dev] [PATCH 00/16] Add infrastructure for GL_OES_texture_compression_astc

[Anuj Phogat]

Anuj Phogat (16):
  mesa: Add block depth field in struct gl_format_info
  mesa: Add support to query block depth using
_mesa_get_format_block_size()
  mesa: Add error conditions for compressed textures with 3D blocks
  mesa: Account for block depth in _mesa_format_image_size()
  glapi: Update dispatch XML files for OES_texture_compression_astc.xml
  mesa: Add mesa formats for astc 3d formats
  mesa: Add entries for astc 3d formats initializing struct
gl_format_info
  mesa: Add OES_texture_compression_astc to extension table and
gl_extensions
  mesa: Align the values of #define's in glheader.h
  mesa: Add the missing defines for GL_OES_texture_compression_astc
  mesa: Add a helper function is_astc_3d_format()
  mesa: Account for astc 3d formats in _mesa_is_astc_format()
  mesa: Handle astc 3d formats in _mesa_base_tex_format()
  mesa: Handle astc 3d formats in _mesa_get_compressed_formats()
  mesa: Enable translation between astc 3d gl formats and mesa formats
  swrast: Add texfetch_funcs entries for astc 3d formats

 src/mapi/glapi/gen/Makefile.am |   1 +
 .../glapi/gen/OES_texture_compression_astc.xml |  61 +++
 src/mapi/glapi/gen/gl_API.xml  |   2 +
 src/mesa/drivers/dri/i915/intel_mipmap_tree.c  |   8 +-
 src/mesa/drivers/dri/i915/intel_tex_layout.c   |   4 +-
 src/mesa/drivers/dri/i965/brw_tex_layout.c |  21 +-
 src/mesa/drivers/dri/i965/intel_copy_image.c   |  14 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c  |   8 +-
 src/mesa/drivers/dri/nouveau/nouveau_util.h|   8 +-
 src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c   |  11 +-
 src/mesa/drivers/dri/radeon/radeon_texture.c   |   4 +-
 src/mesa/main/copyimage.c  |   6 +-
 src/mesa/main/extensions_table.h   |   1 +
 src/mesa/main/format_info.py   |   5 +-
 src/mesa/main/format_parser.py |  15 +-
 src/mesa/main/formatquery.c|   4 +-
 src/mesa/main/formats.c|  52 +-
 src/mesa/main/formats.csv  | 550 +++--
 src/mesa/main/formats.h|  24 +-
 src/mesa/main/glformats.c  |  54 +-
 src/mesa/main/glheader.h   |  81 +--
 src/mesa/main/mtypes.h |   1 +
 src/mesa/main/texcompress.c| 117 -
 src/mesa/main/texgetimage.c|   4 +-
 src/mesa/main/teximage.c   |  17 +-
 src/mesa/main/texstore.c   |   4 +-
 src/mesa/swrast/s_texfetch.c   |  27 +-
 src/mesa/swrast/s_texture.c|   4 +-
 28 files changed, 719 insertions(+), 389 deletions(-)
 create mode 100644 src/mapi/glapi/gen/OES_texture_compression_astc.xml

-- 
2.5.0

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[Mesa-dev] [PATCH 1/3] svga: also dump SVGA3D_BUFFER surfaces in svga_screen_cache_dump()

[Brian Paul]

---
 src/gallium/drivers/svga/svga_screen_cache.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_screen_cache.c 
b/src/gallium/drivers/svga/svga_screen_cache.c
index 5b44129..321c564 100644
--- a/src/gallium/drivers/svga/svga_screen_cache.c
+++ b/src/gallium/drivers/svga/svga_screen_cache.c
@@ -563,8 +563,14 @@ svga_screen_cache_dump(const struct svga_screen 
*svgascreen)
  struct svga_host_surface_cache_entry *entry =
 LIST_ENTRY(struct svga_host_surface_cache_entry,
curr, bucket_head);
- if (entry->key.format != 37) {
-debug_printf("  %u x %u x %u format %u\n",
+ if (entry->key.format == SVGA3D_BUFFER) {
+debug_printf("  %p: buffer %u bytes\n",
+ entry->handle,
+ entry->key.size.width);
+ }
+ else {
+debug_printf("  %p: %u x %u x %u format %u\n",
+ entry->handle,
  entry->key.size.width,
  entry->key.size.height,
  entry->key.size.depth,
-- 
1.9.1

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[Mesa-dev] [PATCH] st/mesa: 78-column wrapping in st_extensions.c

[Brian Paul]

---
 src/mesa/state_tracker/st_extensions.c | 175 -
 1 file changed, 107 insertions(+), 68 deletions(-)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 24c6444..063daae 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -109,23 +109,20 @@ void st_init_limits(struct pipe_screen *screen,
   _clamp(screen->get_param(screen, PIPE_CAP_MAX_RENDER_TARGETS),
  1, MAX_DRAW_BUFFERS);
 
-   c->MaxDualSourceDrawBuffers
-  = _clamp(screen->get_param(screen, 
PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS),
-  0, MAX_DRAW_BUFFERS);
-
-   c->MaxLineWidth
-  = _maxf(1.0f, screen->get_paramf(screen,
-   PIPE_CAPF_MAX_LINE_WIDTH));
-   c->MaxLineWidthAA
-  = _maxf(1.0f, screen->get_paramf(screen,
-   PIPE_CAPF_MAX_LINE_WIDTH_AA));
-
-   c->MaxPointSize
-  = _maxf(1.0f, screen->get_paramf(screen,
-   PIPE_CAPF_MAX_POINT_WIDTH));
-   c->MaxPointSizeAA
-  = _maxf(1.0f, screen->get_paramf(screen,
-   PIPE_CAPF_MAX_POINT_WIDTH_AA));
+   c->MaxDualSourceDrawBuffers =
+  _clamp(screen->get_param(screen,
+   PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS),
+ 0, MAX_DRAW_BUFFERS);
+
+   c->MaxLineWidth =
+  _maxf(1.0f, screen->get_paramf(screen, PIPE_CAPF_MAX_LINE_WIDTH));
+   c->MaxLineWidthAA =
+  _maxf(1.0f, screen->get_paramf(screen, PIPE_CAPF_MAX_LINE_WIDTH_AA));
+
+   c->MaxPointSize =
+  _maxf(1.0f, screen->get_paramf(screen, PIPE_CAPF_MAX_POINT_WIDTH));
+   c->MaxPointSizeAA =
+  _maxf(1.0f, screen->get_paramf(screen, PIPE_CAPF_MAX_POINT_WIDTH_AA));
 
/* these are not queryable. Note that GL basically mandates a 1.0 minimum
 * for non-aa sizes, but we can go down to 0.0 for aa points.
@@ -133,15 +130,16 @@ void st_init_limits(struct pipe_screen *screen,
c->MinPointSize = 1.0f;
c->MinPointSizeAA = 0.0f;
 
-   c->MaxTextureMaxAnisotropy
-  = _maxf(2.0f, screen->get_paramf(screen,
- PIPE_CAPF_MAX_TEXTURE_ANISOTROPY));
+   c->MaxTextureMaxAnisotropy =
+  _maxf(2.0f,
+screen->get_paramf(screen, PIPE_CAPF_MAX_TEXTURE_ANISOTROPY));
 
-   c->MaxTextureLodBias
-  = screen->get_paramf(screen, PIPE_CAPF_MAX_TEXTURE_LOD_BIAS);
+   c->MaxTextureLodBias =
+  screen->get_paramf(screen, PIPE_CAPF_MAX_TEXTURE_LOD_BIAS);
 
-   c->QuadsFollowProvokingVertexConvention = screen->get_param(
-  screen, PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION);
+   c->QuadsFollowProvokingVertexConvention =
+  screen->get_param(screen,
+PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION);
 
c->MaxUniformBlockSize =
   screen->get_shader_param(screen, PIPE_SHADER_FRAGMENT,
@@ -195,21 +193,31 @@ void st_init_limits(struct pipe_screen *screen,
PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS),
   MAX_TEXTURE_IMAGE_UNITS);
 
-  pc->MaxInstructions= pc->MaxNativeInstructions=
+  pc->MaxInstructions =
+  pc->MaxNativeInstructions =
  screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_INSTRUCTIONS);
-  pc->MaxAluInstructions = pc->MaxNativeAluInstructions =
- screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS);
-  pc->MaxTexInstructions = pc->MaxNativeTexInstructions =
- screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS);
-  pc->MaxTexIndirections = pc->MaxNativeTexIndirections =
- screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS);
-  pc->MaxAttribs = pc->MaxNativeAttribs =
+  pc->MaxAluInstructions =
+  pc->MaxNativeAluInstructions =
+ screen->get_shader_param(screen, sh,
+  PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS);
+  pc->MaxTexInstructions =
+  pc->MaxNativeTexInstructions =
+ screen->get_shader_param(screen, sh,
+  PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS);
+  pc->MaxTexIndirections =
+  pc->MaxNativeTexIndirections =
+ screen->get_shader_param(screen, sh,
+  PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS);
+  pc->MaxAttribs =
+  pc->MaxNativeAttribs =
  screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_MAX_INPUTS);
-  pc->MaxTemps   = pc->MaxNativeTemps   =
+  pc->MaxTemps =
+  pc->MaxNativeTemps =
  screen->get_shader_param(screen, sh, PIPE_SHADER_CAP_MAX_TEMPS);
-  pc->MaxAddressRegs = pc->MaxNativeAddressRegs =
- sh == PIPE_SHADER_VERTEX ? 1 : 0;
-  pc->MaxParameters  = pc->MaxNativeParameters  =
+  pc->MaxAddressRegs =
+  pc->MaxNativeAddressRegs = sh == 

[Mesa-dev] [PATCH 3/3] svga: add new surface-write-flushes HUD query

[Brian Paul]

To know when we're flushing the command buffer because we need to
write to surface in the command buffer.
---
 src/gallium/drivers/svga/svga_context.h  | 16 +---
 src/gallium/drivers/svga/svga_pipe_query.c   |  9 +
 src/gallium/drivers/svga/svga_resource_texture.c |  4 +++-
 src/gallium/drivers/svga/svga_screen.c   |  2 ++
 4 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_context.h 
b/src/gallium/drivers/svga/svga_context.h
index 61e82a2..1976f98 100644
--- a/src/gallium/drivers/svga/svga_context.h
+++ b/src/gallium/drivers/svga/svga_context.h
@@ -54,16 +54,17 @@
 #define SVGA_QUERY_NUM_BYTES_UPLOADED  (PIPE_QUERY_DRIVER_SPECIFIC + 6)
 #define SVGA_QUERY_COMMAND_BUFFER_SIZE (PIPE_QUERY_DRIVER_SPECIFIC + 7)
 #define SVGA_QUERY_FLUSH_TIME  (PIPE_QUERY_DRIVER_SPECIFIC + 8)
+#define SVGA_QUERY_SURFACE_WRITE_FLUSHES   (PIPE_QUERY_DRIVER_SPECIFIC + 9)
 
 /* running total counters */
-#define SVGA_QUERY_MEMORY_USED (PIPE_QUERY_DRIVER_SPECIFIC + 9)
-#define SVGA_QUERY_NUM_SHADERS (PIPE_QUERY_DRIVER_SPECIFIC + 10)
-#define SVGA_QUERY_NUM_RESOURCES   (PIPE_QUERY_DRIVER_SPECIFIC + 11)
-#define SVGA_QUERY_NUM_STATE_OBJECTS   (PIPE_QUERY_DRIVER_SPECIFIC + 12)
-#define SVGA_QUERY_NUM_SURFACE_VIEWS   (PIPE_QUERY_DRIVER_SPECIFIC + 13)
-#define SVGA_QUERY_NUM_GENERATE_MIPMAP (PIPE_QUERY_DRIVER_SPECIFIC + 14)
+#define SVGA_QUERY_MEMORY_USED (PIPE_QUERY_DRIVER_SPECIFIC + 10)
+#define SVGA_QUERY_NUM_SHADERS (PIPE_QUERY_DRIVER_SPECIFIC + 11)
+#define SVGA_QUERY_NUM_RESOURCES   (PIPE_QUERY_DRIVER_SPECIFIC + 12)
+#define SVGA_QUERY_NUM_STATE_OBJECTS   (PIPE_QUERY_DRIVER_SPECIFIC + 13)
+#define SVGA_QUERY_NUM_SURFACE_VIEWS   (PIPE_QUERY_DRIVER_SPECIFIC + 14)
+#define SVGA_QUERY_NUM_GENERATE_MIPMAP (PIPE_QUERY_DRIVER_SPECIFIC + 15)
 /*SVGA_QUERY_MAX has to be last because it is size of an array*/
-#define SVGA_QUERY_MAX (PIPE_QUERY_DRIVER_SPECIFIC + 15)
+#define SVGA_QUERY_MAX (PIPE_QUERY_DRIVER_SPECIFIC + 16)
 
 /**
  * Maximum supported number of constant buffers per shader
@@ -506,6 +507,7 @@ struct svga_context
   uint64_t num_resources_mapped; /**< SVGA_QUERY_NUM_RESOURCES_MAPPED */
   uint64_t command_buffer_size;  /**< SVGA_QUERY_COMMAND_BUFFER_SIZE */
   uint64_t flush_time;   /**< SVGA_QUERY_FLUSH_TIME */
+  uint64_t surface_write_flushes; /**< SVGA_QUERY_SURFACE_WRITE_FLUSHES */
   uint64_t num_shaders;  /**< SVGA_QUERY_NUM_SHADERS */
   uint64_t num_state_objects;/**< SVGA_QUERY_NUM_STATE_OBJECTS */
   uint64_t num_surface_views;/**< SVGA_QUERY_NUM_SURFACE_VIEWS */
diff --git a/src/gallium/drivers/svga/svga_pipe_query.c 
b/src/gallium/drivers/svga/svga_pipe_query.c
index 15decd4..845f4ef 100644
--- a/src/gallium/drivers/svga/svga_pipe_query.c
+++ b/src/gallium/drivers/svga/svga_pipe_query.c
@@ -729,6 +729,7 @@ svga_create_query(struct pipe_context *pipe,
case SVGA_QUERY_NUM_BYTES_UPLOADED:
case SVGA_QUERY_COMMAND_BUFFER_SIZE:
case SVGA_QUERY_FLUSH_TIME:
+   case SVGA_QUERY_SURFACE_WRITE_FLUSHES:
case SVGA_QUERY_MEMORY_USED:
case SVGA_QUERY_NUM_SHADERS:
case SVGA_QUERY_NUM_RESOURCES:
@@ -800,6 +801,7 @@ svga_destroy_query(struct pipe_context *pipe, struct 
pipe_query *q)
case SVGA_QUERY_NUM_BYTES_UPLOADED:
case SVGA_QUERY_COMMAND_BUFFER_SIZE:
case SVGA_QUERY_FLUSH_TIME:
+   case SVGA_QUERY_SURFACE_WRITE_FLUSHES:
case SVGA_QUERY_MEMORY_USED:
case SVGA_QUERY_NUM_SHADERS:
case SVGA_QUERY_NUM_RESOURCES:
@@ -894,6 +896,9 @@ svga_begin_query(struct pipe_context *pipe, struct 
pipe_query *q)
case SVGA_QUERY_FLUSH_TIME:
   sq->begin_count = svga->hud.flush_time;
   break;
+   case SVGA_QUERY_SURFACE_WRITE_FLUSHES:
+  sq->begin_count = svga->hud.surface_write_flushes;
+  break;
case SVGA_QUERY_MEMORY_USED:
case SVGA_QUERY_NUM_SHADERS:
case SVGA_QUERY_NUM_RESOURCES:
@@ -994,6 +999,9 @@ svga_end_query(struct pipe_context *pipe, struct pipe_query 
*q)
case SVGA_QUERY_FLUSH_TIME:
   sq->end_count = svga->hud.flush_time;
   break;
+   case SVGA_QUERY_SURFACE_WRITE_FLUSHES:
+  sq->end_count = svga->hud.surface_write_flushes;
+  break;
case SVGA_QUERY_MEMORY_USED:
case SVGA_QUERY_NUM_SHADERS:
case SVGA_QUERY_NUM_RESOURCES:
@@ -1094,6 +1102,7 @@ svga_get_query_result(struct pipe_context *pipe,
case SVGA_QUERY_NUM_BYTES_UPLOADED:
case SVGA_QUERY_COMMAND_BUFFER_SIZE:
case SVGA_QUERY_FLUSH_TIME:
+   case SVGA_QUERY_SURFACE_WRITE_FLUSHES:
   vresult->u64 = sq->end_count - sq->begin_count;
   break;
/* These are running total counters */
diff --git a/src/gallium/drivers/svga/svga_resource_texture.c 
b/src/gallium/drivers/svga/svga_resource_texture.c
index e898ff2..1edb41d 100644
--- 

[Mesa-dev] [PATCH 1/4] gallium/util: re-indent u_debug_refcnt.[ch]

[Brian Paul]

Wrap comments to 78 columns, etc.
---
 src/gallium/auxiliary/util/u_debug_refcnt.c | 103 +++-
 src/gallium/auxiliary/util/u_debug_refcnt.h |  12 +++-
 2 files changed, 65 insertions(+), 50 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_debug_refcnt.c 
b/src/gallium/auxiliary/util/u_debug_refcnt.c
index 2c3dc98..a23f191 100644
--- a/src/gallium/auxiliary/util/u_debug_refcnt.c
+++ b/src/gallium/auxiliary/util/u_debug_refcnt.c
@@ -42,30 +42,38 @@
 
 int debug_refcnt_state;
 
-FILE* stream;
+FILE *stream;
 
-/* TODO: maybe move this serial machinery to a stand-alone module and expose 
it? */
+/* TODO: maybe move this serial machinery to a stand-alone module and
+ * expose it?
+ */
 pipe_static_mutex(serials_mutex);
 
-static struct util_hash_table* serials_hash;
+static struct util_hash_table *serials_hash;
 static unsigned serials_last;
 
-static unsigned hash_ptr(void* p)
+
+static unsigned
+hash_ptr(void *p)
 {
-   return (unsigned)(uintptr_t)p;
+   return (unsigned) (uintptr_t) p;
 }
 
-static int compare_ptr(void* a, void* b)
+
+static int
+compare_ptr(void *a, void *b)
 {
-   if(a == b)
+   if (a == b)
   return 0;
-   else if(a < b)
+   else if (a < b)
   return -1;
else
   return 1;
 }
 
-static boolean debug_serial(void* p, unsigned* pserial)
+
+static boolean
+debug_serial(void *p, unsigned *pserial)
 {
unsigned serial;
boolean found = TRUE;
@@ -81,79 +89,82 @@ static boolean debug_serial(void* p, unsigned* pserial)
pipe_mutex_lock(serials_mutex);
if (!serials_hash)
   serials_hash = util_hash_table_create(hash_ptr, compare_ptr);
-   serial = (unsigned)(uintptr_t)util_hash_table_get(serials_hash, p);
-   if(!serial)
-   {
-  /* time to stop logging... (you'll have a 100 GB logfile at least at 
this point)
-   * TODO: avoid this
+
+   serial = (unsigned) (uintptr_t) util_hash_table_get(serials_hash, p);
+   if (!serial) {
+  /* time to stop logging... (you'll have a 100 GB logfile at least at
+   * this point)  TODO: avoid this
*/
   serial = ++serials_last;
-  if(!serial)
-  {
+  if (!serial) {
  debug_error("More than 2^32 objects detected, aborting.\n");
  os_abort();
   }
 
-  util_hash_table_set(serials_hash, p, (void*)(uintptr_t)serial);
+  util_hash_table_set(serials_hash, p, (void *) (uintptr_t) serial);
   found = FALSE;
}
pipe_mutex_unlock(serials_mutex);
+
*pserial = serial;
+
return found;
 }
 
-static void debug_serial_delete(void* p)
+
+static void
+debug_serial_delete(void *p)
 {
pipe_mutex_lock(serials_mutex);
util_hash_table_remove(serials_hash, p);
pipe_mutex_unlock(serials_mutex);
 }
 
+
 #define STACK_LEN 64
 
-static void dump_stack(const char* symbols[STACK_LEN])
+static void
+dump_stack(const char *symbols[STACK_LEN])
 {
unsigned i;
-   for(i = 0; i < STACK_LEN; ++i)
-   {
-  if(symbols[i])
+   for (i = 0; i < STACK_LEN; ++i) {
+  if (symbols[i])
  fprintf(stream, "%s\n", symbols[i]);
}
fprintf(stream, "\n");
 }
 
-void debug_reference_slowpath(const struct pipe_reference* p, 
debug_reference_descriptor get_desc, int change)
+
+void
+debug_reference_slowpath(const struct pipe_reference *p,
+ debug_reference_descriptor get_desc, int change)
 {
-   if(debug_refcnt_state < 0)
+   if (debug_refcnt_state < 0)
   return;
 
-   if(!debug_refcnt_state)
-   {
-  const char* filename = debug_get_option("GALLIUM_REFCNT_LOG", NULL);
-  if(filename && filename[0])
+   if (!debug_refcnt_state) {
+  const char *filename = debug_get_option("GALLIUM_REFCNT_LOG", NULL);
+  if (filename && filename[0])
  stream = fopen(filename, "wt");
 
-  if(stream)
+  if (stream)
  debug_refcnt_state = 1;
   else
  debug_refcnt_state = -1;
}
 
-   if(debug_refcnt_state > 0)
-   {
+   if (debug_refcnt_state > 0) {
   struct debug_stack_frame frames[STACK_LEN];
-  const char* symbols[STACK_LEN];
+  const char *symbols[STACK_LEN];
   char buf[1024];
-
   unsigned i;
   unsigned refcnt = p->count;
   unsigned serial;
-  boolean existing = debug_serial((void*)p, );
+  boolean existing = debug_serial((void *) p, );
 
   debug_backtrace_capture(frames, 1, STACK_LEN);
-  for(i = 0; i < STACK_LEN; ++i)
-  {
- if(frames[i].function)
+  for (i = 0; i < STACK_LEN; ++i) {
+ if (frames[i].function)
 symbols[i] = debug_symbol_name_cached(frames[i].function);
  else
 symbols[i] = 0;
@@ -161,30 +172,28 @@ void debug_reference_slowpath(const struct 
pipe_reference* p, debug_reference_de
 
   get_desc(buf, p);
 
-  if(!existing)
-  {
+  if (!existing) {
  fprintf(stream, "<%s> %p %u Create\n", buf, (void *) p, serial);
  dump_stack(symbols);
 
- /* this is there to provide a gradual change even if we don't see the 

[Mesa-dev] [PATCH 4/4] gallium/util: add new comments, assertions in u_debug_refcnt.c

[Brian Paul]

---
 src/gallium/auxiliary/util/u_debug_refcnt.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/src/gallium/auxiliary/util/u_debug_refcnt.c 
b/src/gallium/auxiliary/util/u_debug_refcnt.c
index c17c65f..3c030d7 100644
--- a/src/gallium/auxiliary/util/u_debug_refcnt.c
+++ b/src/gallium/auxiliary/util/u_debug_refcnt.c
@@ -77,6 +77,9 @@ compare_ptr(void *a, void *b)
 }
 
 
+/**
+ * Return a small integer serial number for the given pointer.
+ */
 static boolean
 debug_serial(void *p, unsigned *pserial)
 {
@@ -117,6 +120,9 @@ debug_serial(void *p, unsigned *pserial)
 }
 
 
+/**
+ * Free the serial number for the given pointer.
+ */
 static void
 debug_serial_delete(void *p)
 {
@@ -140,10 +146,24 @@ dump_stack(const char *symbols[STACK_LEN])
 }
 
 
+/**
+ * Log a reference count change to the log file (if enabled).
+ * This is called via the pipe_reference() and debug_reference() functions,
+ * basically whenever a reference count is initialized or changed.
+ *
+ * \param p  the refcount being changed (the value is not changed here)
+ * \param get_desc  a function which will be called to print an object's
+ *  name/pointer into a string buffer during logging
+ * \param change  the reference count change which must be +/-1 or 0 when
+ *creating the object and initializing the refcount.
+ */
 void
 debug_reference_slowpath(const struct pipe_reference *p,
  debug_reference_descriptor get_desc, int change)
 {
+   assert(change >= -1);
+   assert(change <= 1);
+
if (debug_refcnt_state < 0)
   return;
 
-- 
1.9.1

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[Mesa-dev] [PATCH 2/4] gallium/util: make stream variable static in u_debug_refcnt.c

[Brian Paul]

---
 src/gallium/auxiliary/util/u_debug_refcnt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/util/u_debug_refcnt.c 
b/src/gallium/auxiliary/util/u_debug_refcnt.c
index a23f191..f486492 100644
--- a/src/gallium/auxiliary/util/u_debug_refcnt.c
+++ b/src/gallium/auxiliary/util/u_debug_refcnt.c
@@ -42,7 +42,7 @@
 
 int debug_refcnt_state;
 
-FILE *stream;
+static FILE *stream;
 
 /* TODO: maybe move this serial machinery to a stand-alone module and
  * expose it?
-- 
1.9.1

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[Mesa-dev] [PATCH 3/4] gallium/util: update comments and URL in u_debug_refcnt.c

[Brian Paul]

---
 src/gallium/auxiliary/util/u_debug_refcnt.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_debug_refcnt.c 
b/src/gallium/auxiliary/util/u_debug_refcnt.c
index f486492..c17c65f 100644
--- a/src/gallium/auxiliary/util/u_debug_refcnt.c
+++ b/src/gallium/auxiliary/util/u_debug_refcnt.c
@@ -26,9 +26,14 @@
 
 #if defined(DEBUG)
 
-/* see http://www.mozilla.org/performance/refcnt-balancer.html for what do 
with the output
- * on Linux, use tools/addr2line.sh to postprocess it before anything else
- **/
+/**
+ * If the GALLIUM_REFCNT_LOG env var is defined as a filename, gallium
+ * reference counting will be logged to the file.
+ *
+ * See http://www-archive.mozilla.org/performance/refcnt-balancer.html
+ * for what do with the output on Linux, use tools/addr2line.sh to
+ * postprocess it before anything else.
+ */
 
 #include 
 
@@ -201,4 +206,5 @@ debug_reference_slowpath(const struct pipe_reference *p,
   fflush(stream);
}
 }
-#endif
+
+#endif /* DEBUG */
-- 
1.9.1

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Re: [Mesa-dev] [PATCH] swrast: fix GL_ANY_SAMPLES_PASSED values in Result

[Brian Paul]

On 03/03/2016 07:02 PM, Ilia Mirkin wrote:

Since commit 922be4eab, the expectation is that the query result
contains the correct value. Unfortunately swrast does not distinguish
between GL_SAMPLES_PASSED and GL_ANY_SAMPLES_PASSED. As a result, we
must fix up the query result in a post-draw fixup.

Bugzilla: 
https://urldefense.proofpoint.com/v2/url?u=https-3A__bugs.freedesktop.org_show-5Fbug.cgi-3Fid-3D94274=BQIGaQ=Sqcl0Ez6M0X8aeM67LKIiDJAXVeAw-YihVMNtXt-uEs=T0t4QG7chq2ZwJo6wilkFznRSFy-8uDKartPGbomVj8=QpL4ebdKGLz2VcCpBgsSDbi7BxcwF1fUKAPVLNZHo80=5GBr_B_K9wZ4XP3CkFsQPbDoO7x-ayRlShmW3-wycIE=
Signed-off-by: Ilia Mirkin 
Tested-by: Vinson Lee 
---
  src/mesa/swrast/s_context.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/src/mesa/swrast/s_context.c b/src/mesa/swrast/s_context.c
index af24207..0a5fc7e 100644
--- a/src/mesa/swrast/s_context.c
+++ b/src/mesa/swrast/s_context.c
@@ -900,11 +900,16 @@ void
  _swrast_render_finish( struct gl_context *ctx )
  {
 SWcontext *swrast = SWRAST_CONTEXT(ctx);
+   struct gl_query_object *query = ctx->Query.CurrentOcclusionObject;

 _swrast_flush(ctx);

 if (swrast->Driver.SpanRenderFinish)
swrast->Driver.SpanRenderFinish( ctx );
+
+   if (query && (query->Target == GL_ANY_SAMPLES_PASSED ||
+ query->Target == GL_ANY_SAMPLES_PASSED_CONSERVATIVE))
+  query->Result = !!query->Result;
  }





Reviewed-by: Brian Paul 

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[Mesa-dev] [Bug 94399] [swrast] piglit getuniform-03 regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94399

Bug ID: 94399
   Summary: [swrast] piglit getuniform-03 regression
   Product: Mesa
   Version: 11.2
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Keywords: bisected, regression
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: v...@freedesktop.org
QA Contact: mesa-dev@lists.freedesktop.org
CC: imir...@alum.mit.edu, lem...@gmail.com,
plamena.manol...@intel.com

mesa: 1f862e923cba1d5cd54a707f70f0be113635e855 (master 11.3.0-devel)

$ ./bin/getuniform-03 -auto
Failed to link: error: count of uniform locations >
MAX_UNIFORM_LOCATIONS(4294967295 > 98304)
Compilation error. Aborting...
PIGLIT: {"result": "fail" }


65dfb3048e8291675ca33581aeff8921f7ea509d is the first bad commit
commit 65dfb3048e8291675ca33581aeff8921f7ea509d
Author: Plamena Manolova 
Date:   Thu Feb 11 15:00:02 2016 +0200

compiler/glsl: Fix uniform location counting.

This patch moves the calculation of current uniforms to
link_uniforms, which makes use of UniformRemapTable which
stores all the reserved uniform locations.

Location assignment for implicit uniforms now tries to use
any gaps left in the table after the location assignment
for explicit uniforms. This gives us more space to store more
uniforms.

Patch is based on earlier patch with following changes/additions:

   1: Move the counting of explicit locations to
  check_explicit_uniform_locations and then pass
  the number to link_assign_uniform_locations.
   2: Count the number of empty slots in UniformRemapTable
  and store them in a list_head.
   3: Try to find an empty slot for implicit locations from
  the list, if that fails resize UniformRemapTable.

Fixes following CTS tests:
   ES31-CTS.explicit_uniform_location.uniform-loc-mix-with-implicit-max
  
ES31-CTS.explicit_uniform_location.uniform-loc-mix-with-implicit-max-array

Signed-off-by: Tapani Pälli 
Signed-off-by: Plamena Manolova 
Reviewed-by: Ilia Mirkin 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93696

:04 04 5848c556c369c2c798c1c1e036c70c740b56a97a
25915fac71a54954aafd0139a55045ba394969e6 Msrc
bisect run success

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Re: [Mesa-dev] [PATCH] i965/hsw: Initialize SLM index in state register

[Matt Turner]

On Mon, Feb 22, 2016 at 11:35 AM, Jordan Justen
 wrote:
> For Haswell, we need to initialize the SLM index in the state
> register. This can be copied out of the CS header dword 0.
>
> Fixes piglit: arb_compute_shader/execution/shared-atomics.shader_test
>
> Signed-off-by: Jordan Justen 
> Cc: Ilia Mirkin 
> Cc: "11.2" 
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp |  7 +++
>  src/mesa/drivers/dri/i965/brw_reg.h  | 16 
>  2 files changed, 23 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index b506040..377c83d 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -5470,6 +5470,13 @@ fs_visitor::run_cs()
> if (shader_time_index >= 0)
>emit_shader_time_begin();
>
> +   if (devinfo->is_haswell && prog_data->total_shared > 0) {
> +  /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
> +  fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
> +  const fs_builder abld = bld.exec_all().group(1, 0);
> +  abld.SHR(suboffset(brw_sr0_reg(), 1), g0, brw_imm_d(16));

Nit: since the dst and src0 are UD, use brw_imm_ud(16).

The only other field in sr0.1 is "Fixed Function Thread ID" at 31:23.
I don't have any idea what overwriting that might do. Is that safe? Or
is the register simply uninitialized?

If that's safe, this patch is

Reviewed-by: Matt Turner 

But I don't think I can make that determination by myself.

Alternatively, if overwriting FFTID is bad, instead of emitting

   shr(1)  sr0.1:UD  g0.0:UD  16UD

you could write only the low word:

   mov(1)  sr0.2:UW  g0.1:UW

or maybe use an AND to ensure you're writing zeros to the MBZ bits of
the status register.
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[Mesa-dev] [Bug 94394] Compile Mesa , specific compilation , /usr/bin/ld: cannot find -ldrm

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94394

--- Comment #4 from Emil Velikov  ---
You are attempting to do a 32bit build on a 64bit platform. Thus the 32bit
dependencies should be met, there is no other way ;-)
The PKG... variable should be set before the configure call, and must point the
the .pc files for the 32bit libraries. 

So something like the following

$ export PKG_CONFIG_PATH=/usr/lib/pkgconfig
$ ./configure ...

As configure runs it will prompt for the missing libraries. Install those and
retry,

If you want to build 64bit mesa on a 64bit platform, you don't need any 32bit
libraries.

Hope that makes things clearer.

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[Mesa-dev] [Bug 94394] Compile Mesa , specific compilation , /usr/bin/ld: cannot find -ldrm

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94394

--- Comment #3 from tele  ---
* - Do I need install all 32 bit dependencies before compile on 64 bit system ?

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[Mesa-dev] [Bug 94394] Compile Mesa , specific compilation , /usr/bin/ld: cannot find -ldrm

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94394

--- Comment #2 from tele  ---
 - Do I need all 32 bit dependencies before compile on 64 bit system ?

#
$ echo $PKG_CONFIG_PATH
/usr/lib64/pkgconfig

$ echo $PKG_CONFIG_PATH
/usr/lib64/pkgconfig

$ ld -ldrm --verbose
...
attempt to open /usr/lib64/libdrm.so succeeded
-ldrm (/usr/lib64/libdrm.so)
libm.so.6 needed by /usr/lib64/libdrm.so
found libm.so.6 at /lib64/libm.so.6
libc.so.6 needed by /usr/lib64/libdrm.so
found libc.so.6 at /lib64/libc.so.6
ld-linux-x86-64.so.2 needed by /lib64/libc.so.6
found ld-linux-x86-64.so.2 at /lib64/ld-linux-x86-64.so.2
ld: warning: cannot find entry symbol _start; not setting start address


$ ls /usr/lib64/pkgconfig | grep libdrm.pc
libdrm.pc
#

./configure CC="gcc -m32" CXX="g++ -m32" --build=x86_64-pc-linux-gnu
--host=i686-pc-linux-gnu --disable-static  PKG_CONFIG_PATH=/usr/lib64/pkgconfig

http://wklejto.pl/249051

make snd the same error
http://wklejto.pl/249052

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[Mesa-dev] [PATCH] anv/meta: Use ISL to get the image tile height

[Nanley Chery]

From: Nanley Chery 

In addition to making the height addition more understandable, this
future-proofs the code for new tiling modes and keeps the image
height as small as possible.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_meta_blit.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_meta_blit.c b/src/intel/vulkan/anv_meta_blit.c
index b8a42f9..8b5873e 100644
--- a/src/intel/vulkan/anv_meta_blit.c
+++ b/src/intel/vulkan/anv_meta_blit.c
@@ -443,6 +443,12 @@ anv_meta_blit2d(struct anv_cmd_buffer *cmd_buffer,
 
for (unsigned r = 0; r < num_rects; ++r) {
 
+  /* Used to store the height of a tile in the src/dst surface.
+   * The tile height is added to the image height to compensate
+   * for the rect's src/dst y-offsets.
+   */
+  struct isl_tile_info tile_info;
+
   /* Create VkImages */
   VkImageCreateInfo image_info = {
  .sType = VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO,
@@ -450,8 +456,7 @@ anv_meta_blit2d(struct anv_cmd_buffer *cmd_buffer,
  .format = 0, /* TEMPLATE */
  .extent = {
 .width = 0, /* TEMPLATE */
-/* Pad to highest tile height to compensate for a vertical 
intratile offset */
-.height = MIN(rects[r].height + 64, 1 << 14),
+.height = 0, /* TEMPLATE */
 .depth = 1,
  },
  .mipLevels = 1,
@@ -470,6 +475,8 @@ anv_meta_blit2d(struct anv_cmd_buffer *cmd_buffer,
 VK_IMAGE_TILING_LINEAR : VK_IMAGE_TILING_OPTIMAL;
   image_info.usage = VK_IMAGE_USAGE_SAMPLED_BIT;
   image_info.format = src_format,
+  isl_tiling_get_info(_buffer->device->isl_dev, src->tiling, src->bs, 
_info);
+  image_info.extent.height = MIN(rects[r].height + tile_info.height, 1 << 
14);
   image_info.extent.width = src->pitch / src->bs;
   VkImage src_image;
   anv_image_create(vk_device, _image_info,
@@ -480,6 +487,8 @@ anv_meta_blit2d(struct anv_cmd_buffer *cmd_buffer,
 VK_IMAGE_TILING_LINEAR : VK_IMAGE_TILING_OPTIMAL;
   image_info.usage = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
   image_info.format = dst_format,
+  isl_tiling_get_info(_buffer->device->isl_dev, dst->tiling, dst->bs, 
_info);
+  image_info.extent.height = MIN(rects[r].height + tile_info.height, 1 << 
14);
   image_info.extent.width = dst->pitch / dst->bs;
   VkImage dst_image;
   anv_image_create(vk_device, _image_info,
-- 
2.7.2

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Re: [Mesa-dev] [PATCH 2/2] i965/compute: Skip SIMD8 generation if it can't be used

[Matt Turner]

On Thu, Feb 25, 2016 at 11:50 PM, Jordan Justen
 wrote:
> If the local workgroup size is sufficiently large, then the SIMD8
> program can't be used. In this case we can skip generating the SIMD8
> program. For complex programs this can save a significant amount of
> time.

That's a good idea.

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH 1/2] i965/fs: Allow spilling for SIMD16 compute shaders

[Matt Turner]

On Thu, Feb 25, 2016 at 11:50 PM, Jordan Justen
 wrote:
> For fragment shaders, we can always use a SIMD8 program. Therefore, if
> we detect spilling with a SIMD16 program, then it is better to skip
> generating a SIMD16 program to only rely on a SIMD8 program.
>
> Unfortunately, this doesn't work for compute shaders. For a compute
> shader, we may be required to use SIMD16 if the local workgroup size
> is bigger than a certain size. For example, on gen7, if the local
> workgroup size is larger than 512, then a SIMD16 program is required.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93840
> Signed-off-by: Jordan Justen 
> Cc: "11.2" 
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp |  2 +-
>  src/mesa/drivers/dri/i965/brw_fs.h   |  1 +
>  src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 11 +++
>  3 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index b506040..3f063a9 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -5228,7 +5228,7 @@ fs_visitor::allocate_registers()
> * SIMD8.  There's probably actually some intermediate point where
> * SIMD16 with a couple of spills is still better.
> */
> -  if (dispatch_width == 16) {
> +  if (dispatch_width == 16 && min_dispatch_width <= 8) {
>   fail("Failure to register allocate.  Reduce number of "
>"live scalar values to avoid this.");
>} else {
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
> b/src/mesa/drivers/dri/i965/brw_fs.h
> index 7446ca1..43d8a9d 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.h
> +++ b/src/mesa/drivers/dri/i965/brw_fs.h
> @@ -407,6 +407,7 @@ public:
> bool spilled_any_registers;
>
> const unsigned dispatch_width; /**< 8 or 16 */
> +   unsigned min_dispatch_width;
>
> int shader_time_index;
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 88b1896..753d97f 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -1021,6 +1021,17 @@ fs_visitor::init()
>unreachable("unhandled shader stage");
> }
>
> +   if (stage == MESA_SHADER_COMPUTE) {
> +  const brw_cs_prog_data *cs_prog_data =
> + (const brw_cs_prog_data*) prog_data;

Space before *

> +  unsigned size = cs_prog_data->local_size[0] *
> + cs_prog_data->local_size[1] * cs_prog_data->local_size[2];

I'd probably write this as

unsigned size = cs_prog_data->local_size[0] *
cs_prog_data->local_size[1] *
cs_prog_data->local_size[2];

where cs_prog_data is aligned. I don't care too much.

> +  size = DIV_ROUND_UP(size, devinfo->max_cs_threads);
> +  min_dispatch_width = size > 16 ? 32 : (size > 8 ? 16 : 8);

O_o

> +   } else {
> +  min_dispatch_width = 8;
> +   }
> +

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH] gallium/swr: fix issues preventing 32-bit build

[Emil Velikov]

Hi Tim,

On 4 March 2016 at 19:28, Tim Rowley  wrote:
> Not a currently tested configuration, but these couple of small changes
> allow a 32-bit build.
A couple of trivial suggestions:

Please add the bugzilla link, before pushing.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94383

> ---
>  src/gallium/drivers/swr/rasterizer/common/os.h  | 1 -
>  src/gallium/drivers/swr/rasterizer/core/utils.h | 2 +-
>  2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h 
> b/src/gallium/drivers/swr/rasterizer/common/os.h
> index 736d298..522ae0d 100644
> --- a/src/gallium/drivers/swr/rasterizer/common/os.h
> +++ b/src/gallium/drivers/swr/rasterizer/common/os.h
> @@ -81,7 +81,6 @@ typedef CARD8 BOOL;
>  typedef wchar_tWCHAR;
>  typedef uint16_t   UINT16;
>  typedef intINT;
> -typedef int INT32;
>  typedef unsigned int   UINT;
>  typedef uint32_t   UINT32;
>  typedef uint64_t   UINT64;
If you can remove this abstraction and use plain C types that will be
amazing. With future commits of course.

For the patch:
Acked-by: Emil Velikov 

Thanks
Emil
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Re: [Mesa-dev] [PATCH v5] i965: add opportunistic behaviour to opt_vector_float()

[Matt Turner]

On Wed, Mar 2, 2016 at 4:21 AM, Juan A. Suarez Romero
 wrote:
> opt_vector_float() transforms several scalar MOV operations to a single
> vectorial MOV.
>
> This is done when those MOV covers all the components of the destination
> register. So something like:
>
> mov vgrf3.0.xy:D, 0D
> mov vgrf3.0.w:D, 1065353216D
> mov vgrf3.0.z:D, 0D
>
> is transformed in:
>
> mov vgrf3.0:F, [0F, 0F, 0F, 1F]
>
> But there are cases where not all the components are written. For
> example, in:
>
> mov vgrf2.0.x:D, 1073741824D
> mov vgrf3.0.xy:D, 0D
> mov vgrf3.0.w:D, 1065353216D
> mov vgrf4.0.xy:D, 1065353216D
> mov vgrf4.0.w:D, 0D
> mov vgrf6.0:UD, u4.xyzw:UD
>
> Nor vgrf3 nor vgrf4 .z components are written, so the optimization is
> not applied.
>
> But it could be applied anyway with the components covered, using a
> writemask to select the ones written. So we could transform it in:
>
> mov vgrf2.0.x:D, 1073741824D
> mov vgrf3.0.xyw:F, [0F, 0F, 0F, 1F]
> mov vgrf4.0.xyw:F, [1F, 1F, 0F, 0F]
> mov vgrf6.0:UD, u4.xyzw:UD
>
> This commit does precisely that: opportunistically apply
> opt_vector_float() when possible.
>
> The improvement obtained regarding current upstream
> (11.2-branchpoint-139-ge8fd60e) is:
>
> total instructions in shared programs: 7385826 -> 7378040 (-0.11%)
> instructions in affected programs: 427528 -> 419742 (-1.82%)
> helped: 3980
> HURT: 0
>
> total cycles in shared programs: 98989662 -> 98974744 (-0.02%)
> cycles in affected programs: 1748966 -> 1734048 (-0.85%)
> helped: 2149
> HURT: 30
>
> total loops in shared programs: 1979 -> 1979 (0.00%)
> loops in affected programs: 0 -> 0
> helped: 0
> HURT: 0

I get even better results with my copy of shader-db :)

total instructions in shared programs: 7124660 -> 7114784 (-0.14%)
instructions in affected programs: 443078 -> 433202 (-2.23%)
helped: 4998
HURT: 0

total cycles in shared programs: 64757760 -> 64728016 (-0.05%)
cycles in affected programs: 1401686 -> 1371942 (-2.12%)
helped: 3243
HURT: 38

I'll update the stats, fix some whitespace issues noted below and push
this patch with my Reviewed-by.

Thanks Juan!

> LOST:   0
> GAINED: 0
>
> v2: change vectorize_mov() signature (Matt).
> v3: take in account predicates (Juan).
>
> Signed-off-by: Juan A. Suarez Romero 
> ---
>  src/mesa/drivers/dri/i965/brw_vec4.cpp | 62 
> ++
>  src/mesa/drivers/dri/i965/brw_vec4.h   |  4 +++
>  2 files changed, 44 insertions(+), 22 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index 3618c72..15e71b4 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> @@ -321,6 +321,29 @@ src_reg::equals(const src_reg ) const
>  }
>
>  bool
> +vec4_visitor::vectorize_mov(bblock_t *block, vec4_instruction *inst, uint8_t 
> imm[4],

I linewrapped this.

> +vec4_instruction *imm_inst[4], int inst_count,
> +unsigned writemask)
> +{
> +   if (inst_count < 2) {
> +  return false;
> +   }

I've removed the braces here.

> +
> +   unsigned vf;
> +   memcpy(, imm, sizeof(vf));
> +   vec4_instruction *mov = MOV(imm_inst[0]->dst, brw_imm_vf(vf));
> +   mov->dst.type = BRW_REGISTER_TYPE_F;
> +   mov->dst.writemask = writemask;
> +   inst->insert_before(block, mov);
> +
> +   for (int i = 0; i < inst_count; i++) {
> +  imm_inst[i]->remove(block);
> +   }
> +
> +   return true;}

} was likely meant to be on its own line.

> +
> +
> +bool
>  vec4_visitor::opt_vector_float()
>  {
> bool progress = false;
> @@ -328,27 +351,37 @@ vec4_visitor::opt_vector_float()
> int last_reg = -1, last_reg_offset = -1;
> enum brw_reg_file last_reg_file = BAD_FILE;
>
> -   int remaining_channels = 0;
> -   uint8_t imm[4];
> +   uint8_t imm[4] = { 0 };
> int inst_count = 0;
> vec4_instruction *imm_inst[4];
> +   unsigned writemask = 0;
>
> foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
>if (last_reg != inst->dst.nr ||
>last_reg_offset != inst->dst.reg_offset ||
>last_reg_file != inst->dst.file) {
> +
> + progress |= vectorize_mov(block, inst, imm, imm_inst, inst_count, 
> writemask);

I removed the blank line before this and linewrapped the arguments.

> +
> + inst_count = 0;
> + writemask = 0;
>   last_reg = inst->dst.nr;
>   last_reg_offset = inst->dst.reg_offset;
>   last_reg_file = inst->dst.file;
> - remaining_channels = WRITEMASK_XYZW;
> -
> - inst_count = 0;
> + for (int i = 0; i < 4; i++) {
> +imm[i] = 0;
> + }
>}
>
>if (inst->opcode != BRW_OPCODE_MOV ||
>inst->dst.writemask == WRITEMASK_XYZW ||
> -  inst->src[0].file != IMM)
> +  inst->src[0].file != IMM ||
> +  inst->predicate != BRW_PREDICATE_NONE) {
> + progress |= 

Re: [Mesa-dev] [PATCH] GLX: Don't destroy screen on XCloseDisplay()

[Brian Paul]

On 03/04/2016 12:26 PM, George Kyriazis wrote:

screen may still be used by other resources that are not yet freed.
To correctly fix this there will be a need to account for resources
differently, but this quick fix is not any worse than the original
code that leaked screens anyway.
---
  src/gallium/state_trackers/glx/xlib/xm_api.c | 10 +++---
  1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/gallium/state_trackers/glx/xlib/xm_api.c 
b/src/gallium/state_trackers/glx/xlib/xm_api.c
index cee4f18..5799cce 100644
--- a/src/gallium/state_trackers/glx/xlib/xm_api.c
+++ b/src/gallium/state_trackers/glx/xlib/xm_api.c
@@ -174,9 +174,13 @@ xmesa_close_display(Display *display)
 /* don't forget to clean up mesaDisplay */
 XMesaDisplay xmdpy = >mesaDisplay;

-   if (xmdpy->screen) {
-  xmdpy->screen->destroy(xmdpy->screen);
-   }
+   /**
+* XXX: Don't destroy the screens here, since there may still
+* be some dangling screen pointers that are used after this point
+* if (xmdpy->screen) {
+*xmdpy->screen->destroy(xmdpy->screen);
+* }
+*/
 free(xmdpy->smapi);

 XFree((char *) info);



Looks OK to me.

Reviewed-by: Brian Paul 

I'll push this in a bit.

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Re: [Mesa-dev] [PATCH] gallium/swr: fix issues preventing 32-bit build

[Brian Paul]

On 03/04/2016 12:28 PM, Tim Rowley wrote:

Not a currently tested configuration, but these couple of small changes
allow a 32-bit build.
---
  src/gallium/drivers/swr/rasterizer/common/os.h  | 1 -
  src/gallium/drivers/swr/rasterizer/core/utils.h | 2 +-
  2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h 
b/src/gallium/drivers/swr/rasterizer/common/os.h
index 736d298..522ae0d 100644
--- a/src/gallium/drivers/swr/rasterizer/common/os.h
+++ b/src/gallium/drivers/swr/rasterizer/common/os.h
@@ -81,7 +81,6 @@ typedef CARD8 BOOL;
  typedef wchar_t   WCHAR;
  typedef uint16_t  UINT16;
  typedef int   INT;
-typedef int INT32;
  typedef unsigned int  UINT;
  typedef uint32_t  UINT32;
  typedef uint64_t  UINT64;
diff --git a/src/gallium/drivers/swr/rasterizer/core/utils.h 
b/src/gallium/drivers/swr/rasterizer/core/utils.h
index 8a59ef2..b9dc48c 100644
--- a/src/gallium/drivers/swr/rasterizer/core/utils.h
+++ b/src/gallium/drivers/swr/rasterizer/core/utils.h
@@ -676,7 +676,7 @@ struct UnrollerL {
  INLINE
  uint32_t ComputeCRC(uint32_t crc, const void *pData, uint32_t size)
  {
-#if defined(_WIN64) || defined(__linux__) || defined(__gnu_linux__)
+#if defined(_WIN64) || defined(__x86_64__)
  uint32_t sizeInQwords = size / sizeof(uint64_t);
  uint32_t sizeRemainderBytes = size % sizeof(uint64_t);
  uint64_t* pDataWords = (uint64_t*)pData;



Not familiar with the code, but looks sane.

Ack-by: Brian Paul 

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[Mesa-dev] [Bug 94394] Compile Mesa , specific compilation , /usr/bin/ld: cannot find -ldrm

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94394

Emil Velikov  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |INVALID

--- Comment #1 from Emil Velikov  ---
I tend to recommend people getting latest mesa from their distribution.
Although that's not always possible.

That aside the issue here is that you've not set the PKG_CONFIG_PATH variable
to point to the 32bit .pc files, as mentioned in the instructions [1]

If you've set it and compilation still fails, feel free to reopen. For the
future please attach files to bugzilla, just in case ;-)

Thanks
Emil

[1] http://www.mesa3d.org/autoconf.html

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[Mesa-dev] [Bug 91101] [softpipe] piglit glsl-1.50@execution@geometry@max-input-components regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=91101

Vinson Lee  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

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[Mesa-dev] [Bug 89960] [softpipe] piglit copy-pixels regreession

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=89960

Vinson Lee  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

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[Mesa-dev] [Bug 79706] [TRACKER] Mesa regression tracker

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=79706
Bug 79706 depends on bug 89960, which changed state.

Bug 89960 Summary: [softpipe] piglit copy-pixels regreession
https://bugs.freedesktop.org/show_bug.cgi?id=89960

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

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Re: [Mesa-dev] [PATCH] r600g: Adjust pipe format when decompressing depth in BE

[Marek Olšák]

On Fri, Mar 4, 2016 at 6:53 PM, Oded Gabbay  wrote:
> On Fri, Mar 4, 2016 at 6:59 PM, Marek Olšák  wrote:
>> On Fri, Mar 4, 2016 at 4:56 PM, Oded Gabbay  wrote:
>>> On Fri, Mar 4, 2016 at 2:19 PM, Marek Olšák  wrote:
 Note that the DB only supports tiling and separate depth and stencil, so
 it's unmappable. Before transfers and sometimes even texturing, the buffer
 must be copied via the DB->CB path, because CB supports both interleaved 
 and
 linear layouts. The result is the flushed texture. The goal here is to
 ensure the flushed texture uses the correct format.

 Marek

>>> Marek,
>>> Thanks for the info, makes the code more clear :)
>>>
>>> I can do what you asked, but frankly, I don't think it looks better:
>>>
>>> @@ -2657,9 +2657,15 @@ uint32_t r600_translate_colorformat(enum
>>> chip_class chip, enum pipe_format forma
>>> return V_0280A0_COLOR_32_32;
>>> }
>>> } else if (HAS_SIZE(8,24,0,0)) {
>>> -   return V_0280A0_COLOR_24_8;
>>> +   if (R600_BIG_ENDIAN)
>>> +   return V_0280A0_COLOR_8_24;
>>> +   else
>>> +   return V_0280A0_COLOR_24_8;
>>> } else if (HAS_SIZE(24,8,0,0)) {
>>> -   return V_0280A0_COLOR_8_24;
>>> +   if (R600_BIG_ENDIAN)
>>> +   return V_0280A0_COLOR_24_8;
>>> +   else
>>> +   return V_0280A0_COLOR_8_24;
>>> }
>>> break;
>>> case 3:
>>>
>>>
>>> @@ -1296,7 +1296,11 @@ unsigned r600_translate_colorswap(enum
>>> pipe_format format)
>>>  (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
>>>  (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X))) {
>>> entry = 2;
>>> +#ifdef PIPE_ARCH_LITTLE_ENDIAN
>>> ret = V_0280A0_SWAP_STD_REV; /* YX__ */
>>> +#else
>>> +   ret = V_0280A0_SWAP_STD; /* YX__ */
>>> +#endif
>>> } else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y)) {
>>> entry = 3;
>>> ret = V_0280A0_SWAP_ALT; /* X__Y */
>>>
>>>
>>> Actually I think it looks worse as we need to intervene in two places
>>> to get the same result I got with just switching the pipe format of
>>> the CB. And I still didn't check what happens with textures.
>>>
>>> In any case, this is basically a workaround, because gallium still
>>> thinks it uses the PIPE_FORMAT_Z24_UNORM_S8_UINT format, while we
>>> program the GPU with the PIPE_FORMAT_S8_UINT_Z24_UNORM parameters.
>>>
>>> I think that if we use a workaround, better use a cleaner/simpler one.
>>
>> Have you tested entire piglit with your first workaround? I doubt it
>> passes depth texturing tests.
>
> No. I only focused so far on getting gl-1.0-readpixsanity to work...
>
> piglit run on BE r600g is in such worse shape, there is no way of
> telling. It crashes after about 300 tests (out of 8600) and in those
> 300 tests, about 50 are failing, and I get dmesg errors from the
> kernel driver.
> Really, BE r600g is so broken, that there can be no baseline until I
> manage to fix things so I get at least an entire piglit run without
> dmesg errors and computer crashes. And I think I'm not anywhere near
> that yet.

I suggest disabling as many features as possible, degrading the driver
to GL 1.x if you have to and running piglit on that. Then you can add
features and see if they work.

I can easily see where the GPU can hang without byteswapping in the
right places. For example, uniform buffer objects and indirect draws.

>
> I'm sure I will find out that some of my current fixes don't match all
> of the cases and they will need better tweaking. I don't see that as
> problematic.
>
>>
>> The problem with hacking the DB->CB decompression blit path is that
>> it's sometimes used for texturing and other times it's not, and it
>> depends on the format and the chip. The other option is that the
>> DB->CB copy is not used for texturing if the hardware supports
>> in-place DB decompression; if so, the DB->CB copy is only used for
>> downloads. The result is that we have to maintain 2 texturing
>> codepaths: one that uses the original texture used by DB and
>> decompressed in-place, and one that is the result of the DB->CB copy.
>
> I assume you mean r600_blit_decompress_depth() and
> r600_blit_decompress_depth_in_place() ?

Yes.

>
>>
>> If you want to change the format of the flushed texture, fine, but you
>> should change it for all users of that codepath, not just texture
>> downloads.
>
> I'm not sure what you mean by that. Could you please give me an
> example or point me to the relevant functions ?

What I mean is that there 

[Mesa-dev] [Bug 94394] Compile Mesa , specific compilation , /usr/bin/ld: cannot find -ldrm

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94394

Bug ID: 94394
   Summary: Compile Mesa , specific compilation , /usr/bin/ld:
cannot find -ldrm
   Product: Mesa
   Version: 11.2
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: Other
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: swojskichlo...@wp.pl
QA Contact: mesa-dev@lists.freedesktop.org

Hi! On 64 bit system I have only 64 bit packages,
but I have Steam, part wine in 32bit and needs 32 bit driver,
Problem is with Mesa, my linux distribution
not provide Mesa 32bit package for 64 bit system,
I tried add 32 bit repository, but it want all 32 bit dependencies.

AMD ATI driver (example)
$ locate fglrx_dri.so
/usr/lib/dri/fglrx_dri.so
/usr/lib64/dri/fglrx_dri.so


Nvidia driver (example)
$ locate libnvidia-glcore.so.352.63
/usr/lib/nvidia-current/libnvidia-glcore.so.352.63
/usr/lib64/nvidia-current/libnvidia-glcore.so.352.63

Mesa (example)
$ locate swrast_dri.so
/usr/lib64/dri/kms_swrast_dri.so
/usr/lib64/dri/swrast_dri.so

I created "wish" Steam 64 bit, but what do with games 32bit,
and 32bit apps from wine ?

So I need 32 bit drivers,
 - How compile Mesa ? 
 - I need install all 32 bit dependencies before compile on 64 bit system ?

Default compilation working without errors,
 but I have only 64 bit drivers.

I tried compile for 32 bit like this

#=
./configure CC="gcc -m32" CXX="g++ -m32" --build=x86_64-pc-linux-gnu
--host=i686-pc-linux-gnu --disable-static

http://wklejto.pl/249041
#=

make
#
$ make
Making all in src
make[1]: Entering directory '/home/gg/Downloads/Down1/mesa-11.1.2/src'
Making all in .
make[2]: Entering directory '/home/gg/Downloads/Down1/mesa-11.1.2/src'
make[2]: Nie ma nic do zrobienia w 'all-am'.
make[2]: Leaving directory '/home/gg/Downloads/Down1/mesa-11.1.2/src'
Making all in gtest
make[2]: Entering directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/gtest'
make[2]: Nie ma nic do zrobienia w 'all'.
make[2]: Leaving directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/gtest'
Making all in util
make[2]: Entering directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/util'
make  all-recursive
make[3]: Entering directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/util'
Making all in .
make[4]: Entering directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/util'
make[4]: Nie ma nic do zrobienia w 'all-am'.
make[4]: Leaving directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/util'
Making all in tests/hash_table
make[4]: Entering directory
'/home/gg/Downloads/Down1/mesa-11.1.2/src/util/tests/hash_table'
make[4]: Nie ma nic do zrobienia w 'all'.
make[4]: Leaving directory
'/home/gg/Downloads/Down1/mesa-11.1.2/src/util/tests/hash_table'
make[3]: Leaving directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/util'
make[2]: Leaving directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/util'
Making all in mapi/glapi/gen
make[2]: Entering directory
'/home/gg/Downloads/Down1/mesa-11.1.2/src/mapi/glapi/gen'
make  all-am
make[3]: Entering directory
'/home/gg/Downloads/Down1/mesa-11.1.2/src/mapi/glapi/gen'
make[3]: Nie ma nic do zrobienia w 'all-am'.
make[3]: Leaving directory
'/home/gg/Downloads/Down1/mesa-11.1.2/src/mapi/glapi/gen'
make[2]: Leaving directory
'/home/gg/Downloads/Down1/mesa-11.1.2/src/mapi/glapi/gen'
Making all in mapi
make[2]: Entering directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/mapi'
make  all-recursive
make[3]: Entering directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/mapi'
make[4]: Entering directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/mapi'
  CCLD es1api/libGLESv1_CM.la
/usr/bin/ld: skipping incompatible /usr/lib64/libdrm.so when searching for
-ldrm
/usr/bin/ld: cannot find -ldrm
collect2: error: ld returned 1 exit status
Makefile:1187: commands for your object 'es1api/libGLESv1_CM.la' failed
make[4]: *** [es1api/libGLESv1_CM.la] Error 1
make[4]: Leaving directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/mapi'
Makefile:1637: commands for your object 'all-recursive' failed
make[3]: *** [all-recursive] Error 1
make[3]: Leaving directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/mapi'
Makefile:1102: commands for your object 'all' failed
make[2]: *** [all] Error 2
make[2]: Leaving directory '/home/gg/Downloads/Down1/mesa-11.1.2/src/mapi'
Makefile:685: commands for your object 'all-recursive' failed
make[1]: *** [all-recursive] Error 1
make[1]: Leaving directory '/home/gg/Downloads/Down1/mesa-11.1.2/src'
Makefile:630: commands for your object 'all-recursive' failed
make: *** [all-recursive] Error 1
#

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Re: [Mesa-dev] gralloc_drm_pipe

[Rob Clark]

On Fri, Mar 4, 2016 at 2:43 PM, Thomas Hellstrom  wrote:
> On 03/04/2016 07:07 PM, Rob Clark wrote:
>> On Fri, Mar 4, 2016 at 12:59 PM, Rob Clark  wrote:
>>> So, I've been advocating that for android, gallium drivers use
>>> gralloc_drm_pipe, since with android it seems like you end up with
>>> both gralloc and libGL in the same process, and having both share the
>>> same pipe_screen avoids lots of headaches with multiple gem handles
>>> pointing to same underlying buffer.
>>>
>>> But the awkward thing is that gralloc_drm_pipe is using gallium APIs
>>> that aren't particularly intended to be used out-of-tree.  Ie. not
>>> really stable APIs.  At the time, the thing that made sense to me was
>>> to pull drm_gralloc into mesa.  But at the time, there were no
>>> non-mesa users of drm_gralloc, which isn't really true anymore.
>>>
>>> Maybe what makes more sense now is to implement a gralloc state
>>> tracker, which exposes a stable API for drm_gralloc?  It would mostly
>>> be a shim to expose gallium import/export/transfer APIs in a stable
>>> way, but would also be where the code that figures out which driver to
>>> use to create/get the pipe_screen.
>> and actually, we might just be able to use XA state tracker for this..
>> I think it exposes all the necessary import/export/etc stuff that
>> gralloc would need..
>>
>> BR,
>> -R
>>
> and it was created for a very similar purpose, except that we also
> needed some
> render functionality, enough to composite surfaces.

right, and since we have the ability to import/export dmabuf handles,
I think it is a superset of what is needed.  (gralloc is using blits
instead of flips for vmwgfx, for reasons I don't fully understand..
but XA can do these blits and more, so we are still good there)

BR,
-R
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Re: [Mesa-dev] About tests for extensions that are later integrated in the core specs

[Matt Turner]

On Fri, Mar 4, 2016 at 6:50 AM, Andres Gomez  wrote:
> Hi,
>
> as complementary work to the one done to "Add FP64 support to the i965
> shader backends" at:
> https://bugs.freedesktop.org/show_bug.cgi?id=92760
>
> We've been working to add piglit tests that would check the new features
> added by this addition. Because of this, we have created several
> generators.
>
> Checking other generators that also apply to fp64, we have seen that
> those generate "duplicated" tests for:
>   * glsl-4.00
>   * arb_gpu_shader_fp64
>
> Probably, this makes sense but we are also seeing that individual tests
> that are coded for the extension at:
>   * tests/spec/arb_gpu_shader_fp64
>
> Do not have a counterpart at:
>   * tests/spec/glsl-4.00
>
> So, the question would be, when doing tests for an extension:
>   * Should we make the generators create "duplicated" tests for the
> extension and for the glsl version that takes the features of
> the extension into the core? Our guess is, "yes".

Right, since it's usually trivial to make the generator scripts
produce tests for multiple APIs, we do it.

>   * Should we duplicate also the individual tests in the same way?
> Our guess is, again, "yes", but we do not know if this would be
> too overkill.

We don't usually duplicate non-generated tests. There's usually not
any chance of a feature working in one API but not the other.

One case where we do sometimes duplicate non-generated tests for
equivalent functionality is Desktop GL vs ES, partly because the
equivalent functionality is often provided by different extensions
between the APIs.

So to answer your main question, I would generate tests for both
glsl-4.00 and arb_gpu_shader_fp64, but only manually write tests for
arb_gpu_shader_fp64.
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Re: [Mesa-dev] gralloc_drm_pipe

[Thomas Hellstrom]

On 03/04/2016 07:07 PM, Rob Clark wrote:
> On Fri, Mar 4, 2016 at 12:59 PM, Rob Clark  wrote:
>> So, I've been advocating that for android, gallium drivers use
>> gralloc_drm_pipe, since with android it seems like you end up with
>> both gralloc and libGL in the same process, and having both share the
>> same pipe_screen avoids lots of headaches with multiple gem handles
>> pointing to same underlying buffer.
>>
>> But the awkward thing is that gralloc_drm_pipe is using gallium APIs
>> that aren't particularly intended to be used out-of-tree.  Ie. not
>> really stable APIs.  At the time, the thing that made sense to me was
>> to pull drm_gralloc into mesa.  But at the time, there were no
>> non-mesa users of drm_gralloc, which isn't really true anymore.
>>
>> Maybe what makes more sense now is to implement a gralloc state
>> tracker, which exposes a stable API for drm_gralloc?  It would mostly
>> be a shim to expose gallium import/export/transfer APIs in a stable
>> way, but would also be where the code that figures out which driver to
>> use to create/get the pipe_screen.
> and actually, we might just be able to use XA state tracker for this..
> I think it exposes all the necessary import/export/etc stuff that
> gralloc would need..
>
> BR,
> -R
>
and it was created for a very similar purpose, except that we also
needed some
render functionality, enough to composite surfaces.

/Thomas




>> Thoughts?
>>
>> BR,
>> -R
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[Mesa-dev] [PATCH] i965/fs/nir: "surface_access::" prefix not needed

[Alejandro Piñeiro]

"using namespace brw::surface_access" is already present at the
top of the source file.
---
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 24 ++--
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index db20c71..2d868cd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2299,8 +2299,6 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
case nir_intrinsic_atomic_counter_inc:
case nir_intrinsic_atomic_counter_dec:
case nir_intrinsic_atomic_counter_read: {
-  using namespace surface_access;
-
   /* Get the arguments of the atomic intrinsic. */
   const fs_reg offset = get_nir_src(instr->src[0]);
   const unsigned surface = (stage_prog_data->binding_table.abo_start +
@@ -2886,12 +2884,11 @@ fs_visitor::nir_emit_ssbo_atomic(const fs_builder ,
 
/* Emit the actual atomic operation operation */
 
-   fs_reg atomic_result =
-  surface_access::emit_untyped_atomic(bld, surface, offset,
-  data1, data2,
-  1 /* dims */, 1 /* rsize */,
-  op,
-  BRW_PREDICATE_NONE);
+   fs_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
+  data1, data2,
+  1 /* dims */, 1 /* rsize */,
+  op,
+  BRW_PREDICATE_NONE);
dest.type = atomic_result.type;
bld.MOV(dest, atomic_result);
 }
@@ -2913,12 +2910,11 @@ fs_visitor::nir_emit_shared_atomic(const fs_builder 
,
 
/* Emit the actual atomic operation operation */
 
-   fs_reg atomic_result =
-  surface_access::emit_untyped_atomic(bld, surface, offset,
-  data1, data2,
-  1 /* dims */, 1 /* rsize */,
-  op,
-  BRW_PREDICATE_NONE);
+   fs_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
+  data1, data2,
+  1 /* dims */, 1 /* rsize */,
+  op,
+  BRW_PREDICATE_NONE);
dest.type = atomic_result.type;
bld.MOV(dest, atomic_result);
 }
-- 
2.5.0

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Re: [Mesa-dev] [PATCH 1/2] isl: Get rid of isl_surf_fill_state_info::level0_extent_px

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Fri, Mar 4, 2016 at 10:03 AM, Nanley Chery  wrote:

> From: Nanley Chery 
>
> This field is no longer needed.
>
> Signed-off-by: Nanley Chery 
> ---
>  src/intel/isl/isl.h   |  9 -
>  src/intel/isl/isl_surface_state.c |  8 
>  src/intel/vulkan/anv_image.c  | 33 +++--
>  3 files changed, 7 insertions(+), 43 deletions(-)
>
> diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
> index 5a48bce..248a94d 100644
> --- a/src/intel/isl/isl.h
> +++ b/src/intel/isl/isl.h
> @@ -773,15 +773,6 @@ struct isl_surf_fill_state_info {
> uint32_t mocs;
>
> /**
> -* This allows the caller to over-ride the dimensions of the surface.
> -* This is used at the moment for compressed surfaces to let us hack
> -* around the fact that we can't actually render to them.
> -*
> -* FIXME: We really need to get rid of this.  It's a lie.
> -*/
> -   struct isl_extent4d level0_extent_px;
> -
> -   /**
>  * The clear color for this surface
>  *
>  * Valid values depend on hardware generation.
> diff --git a/src/intel/isl/isl_surface_state.c
> b/src/intel/isl/isl_surface_state.c
> index 1607aa6..fe8f07c 100644
> --- a/src/intel/isl/isl_surface_state.c
> +++ b/src/intel/isl/isl_surface_state.c
> @@ -257,8 +257,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device
> *dev, void *state,
>.SurfaceQPitch = get_qpitch(info->surf) >> 2,
>  #endif
>
> -  .Width = info->level0_extent_px.width - 1,
> -  .Height = info->level0_extent_px.height - 1,
> +  .Width = info->surf->logical_level0_px.width - 1,
> +  .Height = info->surf->logical_level0_px.height - 1,
>.Depth = 0, /* TEMPLATE */
>
>.SurfacePitch = info->surf->row_pitch - 1,
> @@ -338,7 +338,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device
> *dev, void *state,
> *If the volume texture is MIP-mapped, this field specifies the
> *depth of the base MIP level.
> */
> -  s.Depth = info->level0_extent_px.depth - 1;
> +  s.Depth = info->surf->logical_level0_px.depth - 1;
>
>/* From the Broadwell PRM >>
> RENDER_SURFACE_STATE::RenderTargetViewExtent:
> *
> @@ -346,7 +346,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device
> *dev, void *state,
> *indicates the extent of the accessible 'R' coordinates minus
> 1 on
> *the LOD currently being rendered to.
> */
> -  s.RenderTargetViewExtent = info->level0_extent_px.depth - 1;
> +  s.RenderTargetViewExtent = info->surf->logical_level0_px.depth - 1;
>break;
> default:
>unreachable(!"bad SurfaceType");
> diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
> index dc1ea9c..c76a5f6 100644
> --- a/src/intel/vulkan/anv_image.c
> +++ b/src/intel/vulkan/anv_image.c
> @@ -540,30 +540,6 @@ anv_image_view_init(struct anv_image_view *iview,
>},
> };
>
> -   struct isl_extent4d level0_extent_px;
> -
> -   if (!isl_format_is_compressed(format) &&
> -   isl_format_is_compressed(image->format->isl_format)) {
> -  /* Scale the ImageView extent by the backing Image. This is used
> -   * internally when an uncompressed ImageView is created on a
> -   * compressed Image. The ImageView can therefore be used for copying
> -   * data from a source Image to a destination Image.
> -   */
> -  const struct isl_format_layout * isl_layout =
> image->format->isl_layout;
> -
> -  level0_extent_px.depth  = anv_minify(image->extent.depth,
> range->baseMipLevel);
> -  level0_extent_px.depth  = DIV_ROUND_UP(level0_extent_px.depth,
> isl_layout->bd);
> -
> -  level0_extent_px.height =
> isl_surf_get_array_pitch_el_rows(>isl) * image->array_size;
> -  level0_extent_px.width  = isl_surf_get_row_pitch_el(>isl);
> -  isl_view.base_level = 0;
> -  isl_view.base_array_layer = 0;
> -   } else {
> -  level0_extent_px.width  = image->extent.width;
> -  level0_extent_px.height = image->extent.height;
> -  level0_extent_px.depth  = image->extent.depth;
> -   }
> -
> iview->extent = (VkExtent3D) {
>.width  = anv_minify(image->extent.width , range->baseMipLevel),
>.height = anv_minify(image->extent.height, range->baseMipLevel),
> @@ -586,8 +562,7 @@ anv_image_view_init(struct anv_image_view *iview,
>iview->sampler_surface_state.map,
>.surf = >isl,
>.view = _view,
> -  .mocs = device->default_mocs,
> -  .level0_extent_px = level0_extent_px);
> +  .mocs = device->default_mocs);
>
>if (!device->info.has_llc)
>   anv_state_clflush(iview->sampler_surface_state);
> @@ -603,8 +578,7 @@ anv_image_view_init(struct anv_image_view 

Re: [Mesa-dev] [PATCH 2/2] isl: Fix RenderTargetViewExtent for mipmapped 3D surfaces

[Jason Ekstrand]

LGTM

On Fri, Mar 4, 2016 at 10:03 AM, Nanley Chery  wrote:

> From: Nanley Chery 
>
> Match the comment stated above the assignment.
>
> Signed-off-by: Nanley Chery 
> ---
>  src/intel/isl/isl_surface_state.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/isl/isl_surface_state.c
> b/src/intel/isl/isl_surface_state.c
> index fe8f07c..f3390a6 100644
> --- a/src/intel/isl/isl_surface_state.c
> +++ b/src/intel/isl/isl_surface_state.c
> @@ -346,7 +346,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device
> *dev, void *state,
> *indicates the extent of the accessible 'R' coordinates minus
> 1 on
> *the LOD currently being rendered to.
> */
> -  s.RenderTargetViewExtent = info->surf->logical_level0_px.depth - 1;
> +  s.RenderTargetViewExtent =
> isl_minify(info->surf->logical_level0_px.depth,
> +info->view->base_level) - 1;
>break;
> default:
>unreachable(!"bad SurfaceType");
> --
> 2.7.2
>
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[Mesa-dev] [PATCH] gallium/swr: fix issues preventing 32-bit build

[Tim Rowley]

Not a currently tested configuration, but these couple of small changes
allow a 32-bit build.
---
 src/gallium/drivers/swr/rasterizer/common/os.h  | 1 -
 src/gallium/drivers/swr/rasterizer/core/utils.h | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h 
b/src/gallium/drivers/swr/rasterizer/common/os.h
index 736d298..522ae0d 100644
--- a/src/gallium/drivers/swr/rasterizer/common/os.h
+++ b/src/gallium/drivers/swr/rasterizer/common/os.h
@@ -81,7 +81,6 @@ typedef CARD8 BOOL;
 typedef wchar_tWCHAR;
 typedef uint16_t   UINT16;
 typedef intINT;
-typedef int INT32;
 typedef unsigned int   UINT;
 typedef uint32_t   UINT32;
 typedef uint64_t   UINT64;
diff --git a/src/gallium/drivers/swr/rasterizer/core/utils.h 
b/src/gallium/drivers/swr/rasterizer/core/utils.h
index 8a59ef2..b9dc48c 100644
--- a/src/gallium/drivers/swr/rasterizer/core/utils.h
+++ b/src/gallium/drivers/swr/rasterizer/core/utils.h
@@ -676,7 +676,7 @@ struct UnrollerL {
 INLINE
 uint32_t ComputeCRC(uint32_t crc, const void *pData, uint32_t size)
 {
-#if defined(_WIN64) || defined(__linux__) || defined(__gnu_linux__)
+#if defined(_WIN64) || defined(__x86_64__)
 uint32_t sizeInQwords = size / sizeof(uint64_t);
 uint32_t sizeRemainderBytes = size % sizeof(uint64_t);
 uint64_t* pDataWords = (uint64_t*)pData;
-- 
2.5.0

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[Mesa-dev] [PATCH] GLX: Don't destroy screen on XCloseDisplay()

[George Kyriazis]

screen may still be used by other resources that are not yet freed.
To correctly fix this there will be a need to account for resources
differently, but this quick fix is not any worse than the original
code that leaked screens anyway.
---
 src/gallium/state_trackers/glx/xlib/xm_api.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/gallium/state_trackers/glx/xlib/xm_api.c 
b/src/gallium/state_trackers/glx/xlib/xm_api.c
index cee4f18..5799cce 100644
--- a/src/gallium/state_trackers/glx/xlib/xm_api.c
+++ b/src/gallium/state_trackers/glx/xlib/xm_api.c
@@ -174,9 +174,13 @@ xmesa_close_display(Display *display)
/* don't forget to clean up mesaDisplay */
XMesaDisplay xmdpy = >mesaDisplay;
 
-   if (xmdpy->screen) {
-  xmdpy->screen->destroy(xmdpy->screen);
-   }
+   /**
+* XXX: Don't destroy the screens here, since there may still
+* be some dangling screen pointers that are used after this point
+* if (xmdpy->screen) {
+*xmdpy->screen->destroy(xmdpy->screen);
+* }
+*/
free(xmdpy->smapi);
 
XFree((char *) info);
-- 
2.5.0

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Re: [Mesa-dev] [PATCH] r600g: Adjust pipe format when decompressing depth in BE

[Oded Gabbay]

On Mar 4, 2016 7:53 PM, "Oded Gabbay"  wrote:
>
> On Fri, Mar 4, 2016 at 6:59 PM, Marek Olšák  wrote:
> > On Fri, Mar 4, 2016 at 4:56 PM, Oded Gabbay 
wrote:
> >> On Fri, Mar 4, 2016 at 2:19 PM, Marek Olšák  wrote:
> >>> Note that the DB only supports tiling and separate depth and stencil,
so
> >>> it's unmappable. Before transfers and sometimes even texturing, the
buffer
> >>> must be copied via the DB->CB path, because CB supports both
interleaved and
> >>> linear layouts. The result is the flushed texture. The goal here is to
> >>> ensure the flushed texture uses the correct format.
> >>>
> >>> Marek
> >>>
> >> Marek,
> >> Thanks for the info, makes the code more clear :)
> >>
> >> I can do what you asked, but frankly, I don't think it looks better:
> >>
> >> @@ -2657,9 +2657,15 @@ uint32_t r600_translate_colorformat(enum
> >> chip_class chip, enum pipe_format forma
> >> return V_0280A0_COLOR_32_32;
> >> }
> >> } else if (HAS_SIZE(8,24,0,0)) {
> >> -   return V_0280A0_COLOR_24_8;
> >> +   if (R600_BIG_ENDIAN)
> >> +   return V_0280A0_COLOR_8_24;
> >> +   else
> >> +   return V_0280A0_COLOR_24_8;
> >> } else if (HAS_SIZE(24,8,0,0)) {
> >> -   return V_0280A0_COLOR_8_24;
> >> +   if (R600_BIG_ENDIAN)
> >> +   return V_0280A0_COLOR_24_8;
> >> +   else
> >> +   return V_0280A0_COLOR_8_24;
> >> }
> >> break;
> >> case 3:
> >>
> >>
> >> @@ -1296,7 +1296,11 @@ unsigned r600_translate_colorswap(enum
> >> pipe_format format)
> >>  (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
> >>  (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X))) {
> >> entry = 2;
> >> +#ifdef PIPE_ARCH_LITTLE_ENDIAN
> >> ret = V_0280A0_SWAP_STD_REV; /* YX__ */
> >> +#else
> >> +   ret = V_0280A0_SWAP_STD; /* YX__ */
> >> +#endif
> >> } else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y)) {
> >> entry = 3;
> >> ret = V_0280A0_SWAP_ALT; /* X__Y */
> >>
> >>
> >> Actually I think it looks worse as we need to intervene in two places
> >> to get the same result I got with just switching the pipe format of
> >> the CB. And I still didn't check what happens with textures.
> >>
> >> In any case, this is basically a workaround, because gallium still
> >> thinks it uses the PIPE_FORMAT_Z24_UNORM_S8_UINT format, while we
> >> program the GPU with the PIPE_FORMAT_S8_UINT_Z24_UNORM parameters.
> >>
> >> I think that if we use a workaround, better use a cleaner/simpler one.
> >
> > Have you tested entire piglit with your first workaround? I doubt it
> > passes depth texturing tests.
>
> No. I only focused so far on getting gl-1.0-readpixsanity to work...
>
> piglit run on BE r600g is in such worse shape, there is no way of
> telling. It crashes after about 300 tests (out of 8600) and in those
> 300 tests, about 50 are failing, and I get dmesg errors from the
> kernel driver.
> Really, BE r600g is so broken, that there can be no baseline until I
> manage to fix things so I get at least an entire piglit run without
> dmesg errors and computer crashes. And I think I'm not anywhere near
> that yet.
>
> I'm sure I will find out that some of my current fixes don't match all
> of the cases and they will need better tweaking. I don't see that as
> problematic.
>
> >
> > The problem with hacking the DB->CB decompression blit path is that
> > it's sometimes used for texturing and other times it's not, and it
> > depends on the format and the chip. The other option is that the
> > DB->CB copy is not used for texturing if the hardware supports
> > in-place DB decompression; if so, the DB->CB copy is only used for
> > downloads. The result is that we have to maintain 2 texturing
> > codepaths: one that uses the original texture used by DB and
> > decompressed in-place, and one that is the result of the DB->CB copy.
>
> I assume you mean r600_blit_decompress_depth() and
> r600_blit_decompress_depth_in_place() ?
>
> >
> > If you want to change the format of the flushed texture, fine, but you
> > should change it for all users of that codepath, not just texture
> > downloads.
>
> I'm not sure what you mean by that. Could you please give me an
> example or point me to the relevant functions ?
>
> Thanks,
>
>  Oded
> >
> > Marek
Marek,
fwiw, 3 weeks ago was the first time I ever saw the r600g driver, so my
questions maybe a bit basic.

Oded
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[Mesa-dev] [PATCH 3/3] i965/vec4/nir: no need to use surface_access:: to call emit_untyped_atomic

[Alejandro Piñeiro]

Now that brw_vec4_visitor::emit_untyped_atomic was removed, there is no need
to explicitly set it.
---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 11 +--
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 8ae8d9e..c30b27e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -881,12 +881,11 @@ vec4_visitor::nir_emit_ssbo_atomic(int op, 
nir_intrinsic_instr *instr)
const vec4_builder bld =
   vec4_builder(this).at_end().annotate(current_annotation, base_ir);
 
-   src_reg atomic_result =
-  surface_access::emit_untyped_atomic(bld, surface, offset,
-  data1, data2,
-  1 /* dims */, 1 /* rsize */,
-  op,
-  BRW_PREDICATE_NONE);
+   src_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
+   data1, data2,
+   1 /* dims */, 1 /* rsize */,
+   op,
+   BRW_PREDICATE_NONE);
dest.type = atomic_result.type;
bld.MOV(dest, atomic_result);
 }
-- 
2.5.0

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[Mesa-dev] [PATCH 1/3] i965/vec4: don't load src on emit_send if it is BAD_FILE

[Alejandro Piñeiro]

This can happens if using emit_untyped_atomic for an atomic dec/inc
---
 src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp
index 28002c5..ba1e670f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_surface_builder.cpp
@@ -131,9 +131,10 @@ namespace brw {
bld.MOV(offset(payload, n++),
offset(retype(addr, BRW_REGISTER_TYPE_UD), i));
 
-for (unsigned i = 0; i < src_sz; i++)
-   bld.MOV(offset(payload, n++),
-   offset(retype(src, BRW_REGISTER_TYPE_UD), i));
+if (src.file != BAD_FILE)
+   for (unsigned i = 0; i < src_sz; i++)
+  bld.MOV(offset(payload, n++),
+  offset(retype(src, BRW_REGISTER_TYPE_UD), i));
 
 /* Reduce the dynamically uniform surface index to a single
  * scalar.
-- 
2.5.0

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[Mesa-dev] [PATCH 2/3] i965/vec4/nir: remove emit_untyped_surface_read and emit_untyped_atomic at brw_vec4_visitor

[Alejandro Piñeiro]

surface_access emit_untyped_read and emit_untyped_atomic provides the same
functionality.
---

This patch also fixes the indentation at switch (instr->intrinsic).

 src/mesa/drivers/dri/i965/brw_vec4.h   |  7 
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 39 --
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 55 --
 3 files changed, 26 insertions(+), 75 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 633f13c..1e9f1e2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -276,13 +276,6 @@ public:
void emit_shader_time_end();
void emit_shader_time_write(int shader_time_subindex, src_reg value);
 
-   void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
-dst_reg dst, src_reg offset, src_reg src0,
-src_reg src1);
-
-   void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
-  src_reg offset);
-
src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
  src_reg *reladdr, int reg_offset);
src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 9b721e5..8ae8d9e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -724,24 +724,37 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr 
*instr)
  (unsigned) instr->const_index[0];
   src_reg offset = get_nir_src(instr->src[0], nir_type_int,
instr->num_components);
+  src_reg surface = brw_imm_ud(surf_index);
+  const vec4_builder bld =
+ vec4_builder(this).at_end().annotate(current_annotation, base_ir);
+  src_reg tmp;
+
   dest = get_nir_dest(instr->dest);
 
   switch (instr->intrinsic) {
- case nir_intrinsic_atomic_counter_inc:
-emit_untyped_atomic(BRW_AOP_INC, surf_index, dest, offset,
-src_reg(), src_reg());
-break;
- case nir_intrinsic_atomic_counter_dec:
-emit_untyped_atomic(BRW_AOP_PREDEC, surf_index, dest, offset,
-src_reg(), src_reg());
-break;
- case nir_intrinsic_atomic_counter_read:
-emit_untyped_surface_read(surf_index, dest, offset);
-break;
- default:
-unreachable("Unreachable");
+  case nir_intrinsic_atomic_counter_inc:
+ tmp = emit_untyped_atomic(bld, surface, offset,
+   src_reg(), src_reg(),
+   1, 1,
+   BRW_AOP_INC,
+   BRW_PREDICATE_NONE);
+ break;
+  case nir_intrinsic_atomic_counter_dec:
+ tmp = emit_untyped_atomic(bld, surface, offset,
+   src_reg(), src_reg(),
+   1, 1,
+   BRW_AOP_PREDEC,
+   BRW_PREDICATE_NONE);
+ break;
+  case nir_intrinsic_atomic_counter_read:
+ tmp = emit_untyped_read(bld, surface, offset, 1, 1);
+ break;
+  default:
+ unreachable("Unreachable");
   }
 
+  dest.type = tmp.type;
+  bld.MOV(dest, tmp);
   brw_mark_surface_used(stage_prog_data, surf_index);
   break;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index cfd4d9b..d30330a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1115,61 +1115,6 @@ vec4_visitor::gs_end_primitive()
 }
 
 void
-vec4_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
-  dst_reg dst, src_reg surf_offset,
-  src_reg src0, src_reg src1)
-{
-   unsigned mlen = 1 + (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
-   src_reg src_payload(this, glsl_type::uint_type, mlen);
-   dst_reg payload(src_payload);
-   payload.writemask = WRITEMASK_X;
-
-   /* Set the atomic operation offset. */
-   emit(MOV(offset(payload, 0), surf_offset));
-   unsigned i = 1;
-
-   /* Set the atomic operation arguments. */
-   if (src0.file != BAD_FILE) {
-  emit(MOV(offset(payload, i), src0));
-  i++;
-   }
-
-   if (src1.file != BAD_FILE) {
-  emit(MOV(offset(payload, i), src1));
-  i++;
-   }
-
-   /* Emit the instruction.  Note that this maps to the normal SIMD8
-* untyped atomic message on Ivy Bridge, but that's OK because
-* unused channels will be masked out.
-*/
-   vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst,
- 

[Mesa-dev] [PATCH 0/3] Remove brw_vec4_visitor::emit_untyped_atomic/emit_untyped_surface_read

[Alejandro Piñeiro]

The same functionality is provided by emit_untyped_atomic and
emit_untyped_read at surface_access. Having two implementations of the
same is among other things confusing (I initially spent some time
checking if there was any practical reason to have both).

The real removal is done on the second patch. I also fixed the
indentation of that part.

The first patch fixes a small problem on surface_access::emit_send, as
it didn't take into account that the src could be a bad_file. This can
happens on inc/dec atomic counters.

The last patch is just some minor cleaning.

Alejandro Piñeiro (3):
  i965/vec4: don't load src on emit_send if it is BAD_FILE
  i965/vec4/nir: remove emit_untyped_surface_read and
emit_untyped_atomic at brw_vec4_visitor
  i965/vec4/nir: no need to use surface_access:: to call
emit_untyped_atomic

 src/mesa/drivers/dri/i965/brw_vec4.h   |  7 ---
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 50 
 .../drivers/dri/i965/brw_vec4_surface_builder.cpp  |  7 +--
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 55 --
 4 files changed, 35 insertions(+), 84 deletions(-)

-- 
2.5.0

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Re: [Mesa-dev] [PATCH RFC 0/2] GBM API extension to support fusing KMS and render devices

[Emil Velikov]

On 4 March 2016 at 17:38, Lucas Stach  wrote:
> Am Freitag, den 04.03.2016, 17:20 + schrieb Daniel Stone:
>> Hi,
>>
>> On 4 March 2016 at 16:08, Lucas Stach  wrote:
>> > Am Freitag, den 04.03.2016, 15:09 + schrieb Daniel Stone:
>> >> Thanks for taking this on, it looks really good! I just have the one
>> >> question though - did you look at the EGLDevice extension? Using that
>> >> to enumerate the GPUs, we could create the gbm_device using the KMS
>> >> device and pass that in to the EGLDisplay, with an additional attrib
>> >> to pass in an EGLDevice handle to eglGetPlatformDisplay. This could
>> >> possibly be better since it is more independent of DRM as the API, and
>> >> also allows people to share device enumeration/selection code with
>> >> other platforms (e.g. choosing between multiple GPUs when using a
>> >> winsys like Wayland or X11).
>> >>
>> > I have not looked at this in detail yet, but I think it's just an
>> > extension to the interface outlined by this series.
>> >
>> > If we require the KMS device to have a DRI2/Gallium driver it should be
>> > easy to hook up the EGLDevice discovery for them.
>> > Passing in a second device handle for the KMS device is then just the
>> > EGL implementation calling gbm_device_set_kms_provider() on the render
>> > GBM device, instead of the application doing it manually.
>>
>> It turns the API backwards a bit though ...
>>
>> Right now, what we require is that the GBM device passed in is the KMS
>> device, not the GPU device; what you're suggesting is that we discover
>> the GPU device and then add the KMS device.
>>
>> So, with your proposal:
>> gbm_gpu = gbm_device_create("/dev/dri/renderD128");
>> egl_dpy = eglGetDisplay(gbm_gpu);
>> gbm_kms = gbm_device_create("/dev/dri/card0");
>> gbm_device_set_kms_provider(gbm_gpu, gbm_kms);
>>
>> i.e. the device the user creates first is the GPU device.
>>
>> With EGLDevice, we would have:
>> gbm_kms = gbm_device_create("/dev/dri/card0");
>> egl_gpus = eglGetDevicesEXT();
>> egl_dpy = eglGetPlatformDisplay(gbm_kms, { EGL_TARGET_DEVICE, egl_gpus[0] });
>>
>> So, the first/main device the user deals with is the KMS device - same
>> as today. This makes sense, since GBM is the allocation API for KMS,
>> and EGL should be the one dealing with the GPU ...
>>
> Right, my API design was from my view of GBM being the API to bootstrap
> EGL rendering, but defining it as the KMS allocation API makes a lot
> more sense, when you think about it.
>
>> Maybe it would make sense to reverse the API, so rather than creating
>> a GBM device for the GPU and then linking that to the KMS device -
>> requiring users to make different calls, e.g. gbm_bo_get_kms_bo(),
>> which makes it harder to use and means we need to port current users -
>> we create a GBM device for KMS and then link that to a GPU device.
>> This would then mean that eglGetPlatformDisplay could do the linkage
>> internally, and then existing users using gbm_bo_get_handle() etc
>> would still work without needing any different codepaths.
>
> Yes, this will make the implementation inside GBM a bit more involved,
> but it seems more natural this way around when thinking about hooking it
> up to EGLDevice. I'll try it out and send an updated RFC after the
> weekend.
>
While I'm more inclined to Daniel's suggestion, I wonder why people
moved away from Thierry's approach - creating a composite/wrapped dri
module ? Is there anything wrong with it - be that from technical or
conceptual POV ?

I believe it has a few advantages over the above two proposals - it
allows greater flexibility as both drivers will be tightly coupled and
can communicate directly, does not expand the internal/hidden ABI that
we currently have between GBM and EGL, could (in theory) work with
GLX.

Thoughts ?
-Emil
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Re: [Mesa-dev] [PATCH v2] st/mesa: don't force per-sample interp if only sampleid/pos are used

[Ilia Mirkin]

On Fri, Mar 4, 2016 at 12:26 PM, Ilia Mirkin  wrote:
> The OES extensions clarify this behaviour to differentiate between
> per-sample invocation and per-sample interpolation. Using sampleid/pos
> will force per-sample invocation but not per-sample interpolation.
>
> See https://www.khronos.org/bugzilla/show_bug.cgi?id=1462
>
> Signed-off-by: Ilia Mirkin 
> Reviewed-by: Marek Olšák  (v1)
>
> v1 -> v2:
>   set key.persample_shading in the same way as raster->force_persample_interp
>   except with an inverted dep on st->force_persample_in_shader
> ---
>
> I realized that my old method would end up setting key.persample_shading when
> the shader used sample id/sample pos. Rather than futz around with the
> condition or add more helpers, this just reuses the current logic for setting
> raster->force_persample_interp but flips the dependency on whether it has to 
> be
> done by hand or not. (And uses the semi-new mesa_geometric_samples helper.)

And naturally I was too eager to send this out... minor compile fixes
folded in here:

https://github.com/imirkin/mesa/commit/2c4f19554adc5e9d7bea1164169381184eac50e1

Didn't think it was worth resending.

>
>  src/mesa/state_tracker/st_atom_shader.c | 13 +
>  src/mesa/state_tracker/st_program.c |  4 
>  2 files changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_atom_shader.c 
> b/src/mesa/state_tracker/st_atom_shader.c
> index a88f035..f7e85c1 100644
> --- a/src/mesa/state_tracker/st_atom_shader.c
> +++ b/src/mesa/state_tracker/st_atom_shader.c
> @@ -70,16 +70,13 @@ update_fp( struct st_context *st )
> key.clamp_color = st->clamp_frag_color_in_shader &&
>   st->ctx->Color._ClampFragmentColor;
>
> -   /* Don't set it if the driver can force the interpolation by itself.
> -* If SAMPLE_ID or SAMPLE_POS are used, the interpolation is set
> -* automatically.
> -* Ignore sample qualifier while computing this flag.
> -*/
> +   /* _NEW_MULTISAMPLE | _NEW_BUFFERS */
> key.persample_shading =
>st->force_persample_in_shader &&
> -  !(stfp->Base.Base.SystemValuesRead & (SYSTEM_BIT_SAMPLE_ID |
> -SYSTEM_BIT_SAMPLE_POS)) &&
> -  _mesa_get_min_invocations_per_fragment(st->ctx, >Base, true) > 1;
> +  ctx->Multisample._Enabled &&
> +  ctx->Multisample.SampleShading &&
> +  ctx->Multisample.MinSampleShadingValue *
> +  _mesa_geometric_samples(ctx->DrawBuffer) > 1;
>
> st->fp_variant = st_get_fp_variant(st, stfp, );
>
> diff --git a/src/mesa/state_tracker/st_program.c 
> b/src/mesa/state_tracker/st_program.c
> index 2e21d02..c9f390a 100644
> --- a/src/mesa/state_tracker/st_program.c
> +++ b/src/mesa/state_tracker/st_program.c
> @@ -573,10 +573,6 @@ st_translate_fragment_program(struct st_context *st,
>   else
>  interpLocation[slot] = TGSI_INTERPOLATE_LOC_CENTER;
>
> - if (stfp->Base.Base.SystemValuesRead & (SYSTEM_BIT_SAMPLE_ID |
> - SYSTEM_BIT_SAMPLE_POS))
> -interpLocation[slot] = TGSI_INTERPOLATE_LOC_SAMPLE;
> -
>   switch (attr) {
>   case VARYING_SLOT_POS:
>  input_semantic_name[slot] = TGSI_SEMANTIC_POSITION;
> --
> 2.4.10
>
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Re: [Mesa-dev] gralloc_drm_pipe

[Rob Clark]

On Fri, Mar 4, 2016 at 12:59 PM, Rob Clark  wrote:
> So, I've been advocating that for android, gallium drivers use
> gralloc_drm_pipe, since with android it seems like you end up with
> both gralloc and libGL in the same process, and having both share the
> same pipe_screen avoids lots of headaches with multiple gem handles
> pointing to same underlying buffer.
>
> But the awkward thing is that gralloc_drm_pipe is using gallium APIs
> that aren't particularly intended to be used out-of-tree.  Ie. not
> really stable APIs.  At the time, the thing that made sense to me was
> to pull drm_gralloc into mesa.  But at the time, there were no
> non-mesa users of drm_gralloc, which isn't really true anymore.
>
> Maybe what makes more sense now is to implement a gralloc state
> tracker, which exposes a stable API for drm_gralloc?  It would mostly
> be a shim to expose gallium import/export/transfer APIs in a stable
> way, but would also be where the code that figures out which driver to
> use to create/get the pipe_screen.

and actually, we might just be able to use XA state tracker for this..
I think it exposes all the necessary import/export/etc stuff that
gralloc would need..

BR,
-R

> Thoughts?
>
> BR,
> -R
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[Mesa-dev] gralloc_drm_pipe

[Rob Clark]

So, I've been advocating that for android, gallium drivers use
gralloc_drm_pipe, since with android it seems like you end up with
both gralloc and libGL in the same process, and having both share the
same pipe_screen avoids lots of headaches with multiple gem handles
pointing to same underlying buffer.

But the awkward thing is that gralloc_drm_pipe is using gallium APIs
that aren't particularly intended to be used out-of-tree.  Ie. not
really stable APIs.  At the time, the thing that made sense to me was
to pull drm_gralloc into mesa.  But at the time, there were no
non-mesa users of drm_gralloc, which isn't really true anymore.

Maybe what makes more sense now is to implement a gralloc state
tracker, which exposes a stable API for drm_gralloc?  It would mostly
be a shim to expose gallium import/export/transfer APIs in a stable
way, but would also be where the code that figures out which driver to
use to create/get the pipe_screen.

Thoughts?

BR,
-R
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[Mesa-dev] [PATCH 2/2] isl: Fix RenderTargetViewExtent for mipmapped 3D surfaces

[Nanley Chery]

From: Nanley Chery 

Match the comment stated above the assignment.

Signed-off-by: Nanley Chery 
---
 src/intel/isl/isl_surface_state.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index fe8f07c..f3390a6 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -346,7 +346,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
*indicates the extent of the accessible 'R' coordinates minus 1 on
*the LOD currently being rendered to.
*/
-  s.RenderTargetViewExtent = info->surf->logical_level0_px.depth - 1;
+  s.RenderTargetViewExtent = 
isl_minify(info->surf->logical_level0_px.depth,
+info->view->base_level) - 1;
   break;
default:
   unreachable(!"bad SurfaceType");
-- 
2.7.2

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[Mesa-dev] [PATCH 1/2] isl: Get rid of isl_surf_fill_state_info::level0_extent_px

[Nanley Chery]

From: Nanley Chery 

This field is no longer needed.

Signed-off-by: Nanley Chery 
---
 src/intel/isl/isl.h   |  9 -
 src/intel/isl/isl_surface_state.c |  8 
 src/intel/vulkan/anv_image.c  | 33 +++--
 3 files changed, 7 insertions(+), 43 deletions(-)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 5a48bce..248a94d 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -773,15 +773,6 @@ struct isl_surf_fill_state_info {
uint32_t mocs;
 
/**
-* This allows the caller to over-ride the dimensions of the surface.
-* This is used at the moment for compressed surfaces to let us hack
-* around the fact that we can't actually render to them.
-*
-* FIXME: We really need to get rid of this.  It's a lie.
-*/
-   struct isl_extent4d level0_extent_px;
-
-   /**
 * The clear color for this surface
 *
 * Valid values depend on hardware generation.
diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index 1607aa6..fe8f07c 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -257,8 +257,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
   .SurfaceQPitch = get_qpitch(info->surf) >> 2,
 #endif
 
-  .Width = info->level0_extent_px.width - 1,
-  .Height = info->level0_extent_px.height - 1,
+  .Width = info->surf->logical_level0_px.width - 1,
+  .Height = info->surf->logical_level0_px.height - 1,
   .Depth = 0, /* TEMPLATE */
 
   .SurfacePitch = info->surf->row_pitch - 1,
@@ -338,7 +338,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
*If the volume texture is MIP-mapped, this field specifies the
*depth of the base MIP level.
*/
-  s.Depth = info->level0_extent_px.depth - 1;
+  s.Depth = info->surf->logical_level0_px.depth - 1;
 
   /* From the Broadwell PRM >> 
RENDER_SURFACE_STATE::RenderTargetViewExtent:
*
@@ -346,7 +346,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
*indicates the extent of the accessible 'R' coordinates minus 1 on
*the LOD currently being rendered to.
*/
-  s.RenderTargetViewExtent = info->level0_extent_px.depth - 1;
+  s.RenderTargetViewExtent = info->surf->logical_level0_px.depth - 1;
   break;
default:
   unreachable(!"bad SurfaceType");
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index dc1ea9c..c76a5f6 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -540,30 +540,6 @@ anv_image_view_init(struct anv_image_view *iview,
   },
};
 
-   struct isl_extent4d level0_extent_px;
-
-   if (!isl_format_is_compressed(format) &&
-   isl_format_is_compressed(image->format->isl_format)) {
-  /* Scale the ImageView extent by the backing Image. This is used
-   * internally when an uncompressed ImageView is created on a
-   * compressed Image. The ImageView can therefore be used for copying
-   * data from a source Image to a destination Image.
-   */
-  const struct isl_format_layout * isl_layout = image->format->isl_layout;
-
-  level0_extent_px.depth  = anv_minify(image->extent.depth, 
range->baseMipLevel);
-  level0_extent_px.depth  = DIV_ROUND_UP(level0_extent_px.depth, 
isl_layout->bd);
-
-  level0_extent_px.height = 
isl_surf_get_array_pitch_el_rows(>isl) * image->array_size;
-  level0_extent_px.width  = isl_surf_get_row_pitch_el(>isl);
-  isl_view.base_level = 0;
-  isl_view.base_array_layer = 0;
-   } else {
-  level0_extent_px.width  = image->extent.width;
-  level0_extent_px.height = image->extent.height;
-  level0_extent_px.depth  = image->extent.depth;
-   }
-
iview->extent = (VkExtent3D) {
   .width  = anv_minify(image->extent.width , range->baseMipLevel),
   .height = anv_minify(image->extent.height, range->baseMipLevel),
@@ -586,8 +562,7 @@ anv_image_view_init(struct anv_image_view *iview,
   iview->sampler_surface_state.map,
   .surf = >isl,
   .view = _view,
-  .mocs = device->default_mocs,
-  .level0_extent_px = level0_extent_px);
+  .mocs = device->default_mocs);
 
   if (!device->info.has_llc)
  anv_state_clflush(iview->sampler_surface_state);
@@ -603,8 +578,7 @@ anv_image_view_init(struct anv_image_view *iview,
   iview->color_rt_surface_state.map,
   .surf = >isl,
   .view = _view,
-  .mocs = device->default_mocs,
-  .level0_extent_px = level0_extent_px);
+  .mocs = device->default_mocs);
 
   if 

Re: [Mesa-dev] [PATCH] r600g: Adjust pipe format when decompressing depth in BE

[Oded Gabbay]

On Fri, Mar 4, 2016 at 6:59 PM, Marek Olšák  wrote:
> On Fri, Mar 4, 2016 at 4:56 PM, Oded Gabbay  wrote:
>> On Fri, Mar 4, 2016 at 2:19 PM, Marek Olšák  wrote:
>>> Note that the DB only supports tiling and separate depth and stencil, so
>>> it's unmappable. Before transfers and sometimes even texturing, the buffer
>>> must be copied via the DB->CB path, because CB supports both interleaved and
>>> linear layouts. The result is the flushed texture. The goal here is to
>>> ensure the flushed texture uses the correct format.
>>>
>>> Marek
>>>
>> Marek,
>> Thanks for the info, makes the code more clear :)
>>
>> I can do what you asked, but frankly, I don't think it looks better:
>>
>> @@ -2657,9 +2657,15 @@ uint32_t r600_translate_colorformat(enum
>> chip_class chip, enum pipe_format forma
>> return V_0280A0_COLOR_32_32;
>> }
>> } else if (HAS_SIZE(8,24,0,0)) {
>> -   return V_0280A0_COLOR_24_8;
>> +   if (R600_BIG_ENDIAN)
>> +   return V_0280A0_COLOR_8_24;
>> +   else
>> +   return V_0280A0_COLOR_24_8;
>> } else if (HAS_SIZE(24,8,0,0)) {
>> -   return V_0280A0_COLOR_8_24;
>> +   if (R600_BIG_ENDIAN)
>> +   return V_0280A0_COLOR_24_8;
>> +   else
>> +   return V_0280A0_COLOR_8_24;
>> }
>> break;
>> case 3:
>>
>>
>> @@ -1296,7 +1296,11 @@ unsigned r600_translate_colorswap(enum
>> pipe_format format)
>>  (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
>>  (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X))) {
>> entry = 2;
>> +#ifdef PIPE_ARCH_LITTLE_ENDIAN
>> ret = V_0280A0_SWAP_STD_REV; /* YX__ */
>> +#else
>> +   ret = V_0280A0_SWAP_STD; /* YX__ */
>> +#endif
>> } else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y)) {
>> entry = 3;
>> ret = V_0280A0_SWAP_ALT; /* X__Y */
>>
>>
>> Actually I think it looks worse as we need to intervene in two places
>> to get the same result I got with just switching the pipe format of
>> the CB. And I still didn't check what happens with textures.
>>
>> In any case, this is basically a workaround, because gallium still
>> thinks it uses the PIPE_FORMAT_Z24_UNORM_S8_UINT format, while we
>> program the GPU with the PIPE_FORMAT_S8_UINT_Z24_UNORM parameters.
>>
>> I think that if we use a workaround, better use a cleaner/simpler one.
>
> Have you tested entire piglit with your first workaround? I doubt it
> passes depth texturing tests.

No. I only focused so far on getting gl-1.0-readpixsanity to work...

piglit run on BE r600g is in such worse shape, there is no way of
telling. It crashes after about 300 tests (out of 8600) and in those
300 tests, about 50 are failing, and I get dmesg errors from the
kernel driver.
Really, BE r600g is so broken, that there can be no baseline until I
manage to fix things so I get at least an entire piglit run without
dmesg errors and computer crashes. And I think I'm not anywhere near
that yet.

I'm sure I will find out that some of my current fixes don't match all
of the cases and they will need better tweaking. I don't see that as
problematic.

>
> The problem with hacking the DB->CB decompression blit path is that
> it's sometimes used for texturing and other times it's not, and it
> depends on the format and the chip. The other option is that the
> DB->CB copy is not used for texturing if the hardware supports
> in-place DB decompression; if so, the DB->CB copy is only used for
> downloads. The result is that we have to maintain 2 texturing
> codepaths: one that uses the original texture used by DB and
> decompressed in-place, and one that is the result of the DB->CB copy.

I assume you mean r600_blit_decompress_depth() and
r600_blit_decompress_depth_in_place() ?

>
> If you want to change the format of the flushed texture, fine, but you
> should change it for all users of that codepath, not just texture
> downloads.

I'm not sure what you mean by that. Could you please give me an
example or point me to the relevant functions ?

Thanks,

 Oded
>
> Marek
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Re: [Mesa-dev] [PATCH RFC 0/2] GBM API extension to support fusing KMS and render devices

[Lucas Stach]

Am Freitag, den 04.03.2016, 17:20 + schrieb Daniel Stone:
> Hi,
> 
> On 4 March 2016 at 16:08, Lucas Stach  wrote:
> > Am Freitag, den 04.03.2016, 15:09 + schrieb Daniel Stone:
> >> Thanks for taking this on, it looks really good! I just have the one
> >> question though - did you look at the EGLDevice extension? Using that
> >> to enumerate the GPUs, we could create the gbm_device using the KMS
> >> device and pass that in to the EGLDisplay, with an additional attrib
> >> to pass in an EGLDevice handle to eglGetPlatformDisplay. This could
> >> possibly be better since it is more independent of DRM as the API, and
> >> also allows people to share device enumeration/selection code with
> >> other platforms (e.g. choosing between multiple GPUs when using a
> >> winsys like Wayland or X11).
> >>
> > I have not looked at this in detail yet, but I think it's just an
> > extension to the interface outlined by this series.
> >
> > If we require the KMS device to have a DRI2/Gallium driver it should be
> > easy to hook up the EGLDevice discovery for them.
> > Passing in a second device handle for the KMS device is then just the
> > EGL implementation calling gbm_device_set_kms_provider() on the render
> > GBM device, instead of the application doing it manually.
> 
> It turns the API backwards a bit though ...
> 
> Right now, what we require is that the GBM device passed in is the KMS
> device, not the GPU device; what you're suggesting is that we discover
> the GPU device and then add the KMS device.
> 
> So, with your proposal:
> gbm_gpu = gbm_device_create("/dev/dri/renderD128");
> egl_dpy = eglGetDisplay(gbm_gpu);
> gbm_kms = gbm_device_create("/dev/dri/card0");
> gbm_device_set_kms_provider(gbm_gpu, gbm_kms);
> 
> i.e. the device the user creates first is the GPU device.
> 
> With EGLDevice, we would have:
> gbm_kms = gbm_device_create("/dev/dri/card0");
> egl_gpus = eglGetDevicesEXT();
> egl_dpy = eglGetPlatformDisplay(gbm_kms, { EGL_TARGET_DEVICE, egl_gpus[0] });
> 
> So, the first/main device the user deals with is the KMS device - same
> as today. This makes sense, since GBM is the allocation API for KMS,
> and EGL should be the one dealing with the GPU ...
> 
Right, my API design was from my view of GBM being the API to bootstrap
EGL rendering, but defining it as the KMS allocation API makes a lot
more sense, when you think about it.

> Maybe it would make sense to reverse the API, so rather than creating
> a GBM device for the GPU and then linking that to the KMS device -
> requiring users to make different calls, e.g. gbm_bo_get_kms_bo(),
> which makes it harder to use and means we need to port current users -
> we create a GBM device for KMS and then link that to a GPU device.
> This would then mean that eglGetPlatformDisplay could do the linkage
> internally, and then existing users using gbm_bo_get_handle() etc
> would still work without needing any different codepaths.

Yes, this will make the implementation inside GBM a bit more involved,
but it seems more natural this way around when thinking about hooking it
up to EGLDevice. I'll try it out and send an updated RFC after the
weekend.

Regards,
Lucas

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[Mesa-dev] [PATCH v2] st/mesa: don't force per-sample interp if only sampleid/pos are used

[Ilia Mirkin]

The OES extensions clarify this behaviour to differentiate between
per-sample invocation and per-sample interpolation. Using sampleid/pos
will force per-sample invocation but not per-sample interpolation.

See https://www.khronos.org/bugzilla/show_bug.cgi?id=1462

Signed-off-by: Ilia Mirkin 
Reviewed-by: Marek Olšák  (v1)

v1 -> v2:
  set key.persample_shading in the same way as raster->force_persample_interp
  except with an inverted dep on st->force_persample_in_shader
---

I realized that my old method would end up setting key.persample_shading when
the shader used sample id/sample pos. Rather than futz around with the
condition or add more helpers, this just reuses the current logic for setting
raster->force_persample_interp but flips the dependency on whether it has to be
done by hand or not. (And uses the semi-new mesa_geometric_samples helper.)

 src/mesa/state_tracker/st_atom_shader.c | 13 +
 src/mesa/state_tracker/st_program.c |  4 
 2 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_shader.c 
b/src/mesa/state_tracker/st_atom_shader.c
index a88f035..f7e85c1 100644
--- a/src/mesa/state_tracker/st_atom_shader.c
+++ b/src/mesa/state_tracker/st_atom_shader.c
@@ -70,16 +70,13 @@ update_fp( struct st_context *st )
key.clamp_color = st->clamp_frag_color_in_shader &&
  st->ctx->Color._ClampFragmentColor;
 
-   /* Don't set it if the driver can force the interpolation by itself.
-* If SAMPLE_ID or SAMPLE_POS are used, the interpolation is set
-* automatically.
-* Ignore sample qualifier while computing this flag.
-*/
+   /* _NEW_MULTISAMPLE | _NEW_BUFFERS */
key.persample_shading =
   st->force_persample_in_shader &&
-  !(stfp->Base.Base.SystemValuesRead & (SYSTEM_BIT_SAMPLE_ID |
-SYSTEM_BIT_SAMPLE_POS)) &&
-  _mesa_get_min_invocations_per_fragment(st->ctx, >Base, true) > 1;
+  ctx->Multisample._Enabled &&
+  ctx->Multisample.SampleShading &&
+  ctx->Multisample.MinSampleShadingValue *
+  _mesa_geometric_samples(ctx->DrawBuffer) > 1;
 
st->fp_variant = st_get_fp_variant(st, stfp, );
 
diff --git a/src/mesa/state_tracker/st_program.c 
b/src/mesa/state_tracker/st_program.c
index 2e21d02..c9f390a 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -573,10 +573,6 @@ st_translate_fragment_program(struct st_context *st,
  else
 interpLocation[slot] = TGSI_INTERPOLATE_LOC_CENTER;
 
- if (stfp->Base.Base.SystemValuesRead & (SYSTEM_BIT_SAMPLE_ID |
- SYSTEM_BIT_SAMPLE_POS))
-interpLocation[slot] = TGSI_INTERPOLATE_LOC_SAMPLE;
-
  switch (attr) {
  case VARYING_SLOT_POS:
 input_semantic_name[slot] = TGSI_SEMANTIC_POSITION;
-- 
2.4.10

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Re: [Mesa-dev] [PATCH RFC 0/2] GBM API extension to support fusing KMS and render devices

[Daniel Stone]

Hi,

On 4 March 2016 at 16:08, Lucas Stach  wrote:
> Am Freitag, den 04.03.2016, 15:09 + schrieb Daniel Stone:
>> Thanks for taking this on, it looks really good! I just have the one
>> question though - did you look at the EGLDevice extension? Using that
>> to enumerate the GPUs, we could create the gbm_device using the KMS
>> device and pass that in to the EGLDisplay, with an additional attrib
>> to pass in an EGLDevice handle to eglGetPlatformDisplay. This could
>> possibly be better since it is more independent of DRM as the API, and
>> also allows people to share device enumeration/selection code with
>> other platforms (e.g. choosing between multiple GPUs when using a
>> winsys like Wayland or X11).
>>
> I have not looked at this in detail yet, but I think it's just an
> extension to the interface outlined by this series.
>
> If we require the KMS device to have a DRI2/Gallium driver it should be
> easy to hook up the EGLDevice discovery for them.
> Passing in a second device handle for the KMS device is then just the
> EGL implementation calling gbm_device_set_kms_provider() on the render
> GBM device, instead of the application doing it manually.

It turns the API backwards a bit though ...

Right now, what we require is that the GBM device passed in is the KMS
device, not the GPU device; what you're suggesting is that we discover
the GPU device and then add the KMS device.

So, with your proposal:
gbm_gpu = gbm_device_create("/dev/dri/renderD128");
egl_dpy = eglGetDisplay(gbm_gpu);
gbm_kms = gbm_device_create("/dev/dri/card0");
gbm_device_set_kms_provider(gbm_gpu, gbm_kms);

i.e. the device the user creates first is the GPU device.

With EGLDevice, we would have:
gbm_kms = gbm_device_create("/dev/dri/card0");
egl_gpus = eglGetDevicesEXT();
egl_dpy = eglGetPlatformDisplay(gbm_kms, { EGL_TARGET_DEVICE, egl_gpus[0] });

So, the first/main device the user deals with is the KMS device - same
as today. This makes sense, since GBM is the allocation API for KMS,
and EGL should be the one dealing with the GPU ...

Maybe it would make sense to reverse the API, so rather than creating
a GBM device for the GPU and then linking that to the KMS device -
requiring users to make different calls, e.g. gbm_bo_get_kms_bo(),
which makes it harder to use and means we need to port current users -
we create a GBM device for KMS and then link that to a GPU device.
This would then mean that eglGetPlatformDisplay could do the linkage
internally, and then existing users using gbm_bo_get_handle() etc
would still work without needing any different codepaths.

Cheers,
Daniel
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Re: [Mesa-dev] [PATCH] r600g: Adjust pipe format when decompressing depth in BE

[Marek Olšák]

On Fri, Mar 4, 2016 at 4:56 PM, Oded Gabbay  wrote:
> On Fri, Mar 4, 2016 at 2:19 PM, Marek Olšák  wrote:
>> Note that the DB only supports tiling and separate depth and stencil, so
>> it's unmappable. Before transfers and sometimes even texturing, the buffer
>> must be copied via the DB->CB path, because CB supports both interleaved and
>> linear layouts. The result is the flushed texture. The goal here is to
>> ensure the flushed texture uses the correct format.
>>
>> Marek
>>
> Marek,
> Thanks for the info, makes the code more clear :)
>
> I can do what you asked, but frankly, I don't think it looks better:
>
> @@ -2657,9 +2657,15 @@ uint32_t r600_translate_colorformat(enum
> chip_class chip, enum pipe_format forma
> return V_0280A0_COLOR_32_32;
> }
> } else if (HAS_SIZE(8,24,0,0)) {
> -   return V_0280A0_COLOR_24_8;
> +   if (R600_BIG_ENDIAN)
> +   return V_0280A0_COLOR_8_24;
> +   else
> +   return V_0280A0_COLOR_24_8;
> } else if (HAS_SIZE(24,8,0,0)) {
> -   return V_0280A0_COLOR_8_24;
> +   if (R600_BIG_ENDIAN)
> +   return V_0280A0_COLOR_24_8;
> +   else
> +   return V_0280A0_COLOR_8_24;
> }
> break;
> case 3:
>
>
> @@ -1296,7 +1296,11 @@ unsigned r600_translate_colorswap(enum
> pipe_format format)
>  (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
>  (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X))) {
> entry = 2;
> +#ifdef PIPE_ARCH_LITTLE_ENDIAN
> ret = V_0280A0_SWAP_STD_REV; /* YX__ */
> +#else
> +   ret = V_0280A0_SWAP_STD; /* YX__ */
> +#endif
> } else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y)) {
> entry = 3;
> ret = V_0280A0_SWAP_ALT; /* X__Y */
>
>
> Actually I think it looks worse as we need to intervene in two places
> to get the same result I got with just switching the pipe format of
> the CB. And I still didn't check what happens with textures.
>
> In any case, this is basically a workaround, because gallium still
> thinks it uses the PIPE_FORMAT_Z24_UNORM_S8_UINT format, while we
> program the GPU with the PIPE_FORMAT_S8_UINT_Z24_UNORM parameters.
>
> I think that if we use a workaround, better use a cleaner/simpler one.

Have you tested entire piglit with your first workaround? I doubt it
passes depth texturing tests.

The problem with hacking the DB->CB decompression blit path is that
it's sometimes used for texturing and other times it's not, and it
depends on the format and the chip. The other option is that the
DB->CB copy is not used for texturing if the hardware supports
in-place DB decompression; if so, the DB->CB copy is only used for
downloads. The result is that we have to maintain 2 texturing
codepaths: one that uses the original texture used by DB and
decompressed in-place, and one that is the result of the DB->CB copy.

If you want to change the format of the flushed texture, fine, but you
should change it for all users of that codepath, not just texture
downloads.

Marek
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