[Mesa-dev] [PATCH 2/3] gallium/radeon: remove use_reusable_pool parameter from r600_init_resource

[Nicolai Hähnle]

From: Nicolai Hähnle 

All callers set it to true.
---
 src/gallium/drivers/r600/r600_state_common.c| 2 +-
 src/gallium/drivers/radeon/r600_buffer_common.c | 7 +++
 src/gallium/drivers/radeon/r600_pipe_common.h   | 3 +--
 src/gallium/drivers/radeon/r600_texture.c   | 2 +-
 src/gallium/drivers/radeonsi/si_descriptors.c   | 2 +-
 5 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_state_common.c 
b/src/gallium/drivers/r600/r600_state_common.c
index abc41e0..7386f9f 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -2744,7 +2744,7 @@ static void r600_invalidate_buffer(struct pipe_context 
*ctx, struct pipe_resourc
 
/* Reallocate the buffer in the same pipe_resource. */
r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0,
-  alignment, TRUE);
+  alignment);
 
/* We changed the buffer, now we need to bind it where the old one was 
bound. */
/* Vertex buffers. */
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index ab5eab9..1955dab 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -102,8 +102,7 @@ void *r600_buffer_map_sync_with_rings(struct 
r600_common_context *ctx,
 
 bool r600_init_resource(struct r600_common_screen *rscreen,
struct r600_resource *res,
-   uint64_t size, unsigned alignment,
-   bool use_reusable_pool)
+   uint64_t size, unsigned alignment)
 {
struct r600_texture *rtex = (struct r600_texture*)res;
struct pb_buffer *old_buf, *new_buf;
@@ -177,7 +176,7 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
 
/* Allocate a new resource. */
new_buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
-use_reusable_pool,
+true,
 res->domains, flags);
if (!new_buf) {
return false;
@@ -493,7 +492,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen 
*screen,
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
 
-   if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, 
TRUE)) {
+   if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment)) {
FREE(rbuffer);
return NULL;
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 44ab675..ba7a414 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -549,8 +549,7 @@ void *r600_buffer_map_sync_with_rings(struct 
r600_common_context *ctx,
   unsigned usage);
 bool r600_init_resource(struct r600_common_screen *rscreen,
struct r600_resource *res,
-   uint64_t size, unsigned alignment,
-   bool use_reusable_pool);
+   uint64_t size, unsigned alignment);
 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 const struct pipe_resource *templ,
 unsigned alignment);
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 4bbe04d..d6719ef 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -878,7 +878,7 @@ r600_texture_create_object(struct pipe_screen *screen,
/* Now create the backing buffer. */
if (!buf) {
if (!r600_init_resource(rscreen, resource, rtex->size,
-   rtex->surface.bo_alignment, TRUE)) {
+   rtex->surface.bo_alignment)) {
FREE(rtex);
return NULL;
}
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 798deb6..0b32045 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1203,7 +1203,7 @@ static void si_invalidate_buffer(struct pipe_context 
*ctx, struct pipe_resource
 
/* Reallocate the buffer in the same pipe_resource. */
r600_init_resource(&sctx->screen->b, rbuffer, rbuffer->b.b.width0,
-  alignment, TRUE);
+  alignment);
 
/* We changed the buffer, now we need to bind it where the old one
 * was bound. This consists of 2 things:
-- 
2.5.0

_

[Mesa-dev] [PATCH 3/3] winsys/radeon: remove use_reusable_pool parameter from buffer_create

[Nicolai Hähnle]

From: Nicolai Hähnle 

All callers set this parameter to true.
---
 src/gallium/drivers/r300/r300_query.c   |  2 +-
 src/gallium/drivers/r300/r300_render.c  |  2 +-
 src/gallium/drivers/r300/r300_screen_buffer.c   |  4 ++--
 src/gallium/drivers/r300/r300_texture.c |  2 +-
 src/gallium/drivers/radeon/r600_buffer_common.c |  1 -
 src/gallium/drivers/radeon/radeon_video.c   |  2 +-
 src/gallium/drivers/radeon/radeon_winsys.h  |  1 -
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c   | 14 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c   |  2 +-
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c   | 11 ---
 src/gallium/winsys/radeon/drm/radeon_drm_cs.c   |  2 +-
 11 files changed, 17 insertions(+), 26 deletions(-)

diff --git a/src/gallium/drivers/r300/r300_query.c 
b/src/gallium/drivers/r300/r300_query.c
index 8557eb7..f788f58 100644
--- a/src/gallium/drivers/r300/r300_query.c
+++ b/src/gallium/drivers/r300/r300_query.c
@@ -58,7 +58,7 @@ static struct pipe_query *r300_create_query(struct 
pipe_context *pipe,
 else
 q->num_pipes = r300screen->info.r300_num_gb_pipes;
 
-q->buf = r300->rws->buffer_create(r300->rws, 4096, 4096, TRUE,
+q->buf = r300->rws->buffer_create(r300->rws, 4096, 4096,
   RADEON_DOMAIN_GTT, 0);
 if (!q->buf) {
 FREE(q);
diff --git a/src/gallium/drivers/r300/r300_render.c 
b/src/gallium/drivers/r300/r300_render.c
index 7eda675..43860f3 100644
--- a/src/gallium/drivers/r300/r300_render.c
+++ b/src/gallium/drivers/r300/r300_render.c
@@ -904,7 +904,7 @@ static boolean r300_render_allocate_vertices(struct 
vbuf_render* render,
 
 r300->vbo = rws->buffer_create(rws,
MAX2(R300_MAX_DRAW_VBO_SIZE, size),
-   R300_BUFFER_ALIGNMENT, TRUE,
+   R300_BUFFER_ALIGNMENT,
RADEON_DOMAIN_GTT, 0);
 if (!r300->vbo) {
 return FALSE;
diff --git a/src/gallium/drivers/r300/r300_screen_buffer.c 
b/src/gallium/drivers/r300/r300_screen_buffer.c
index 42c8e3a..5b69b24 100644
--- a/src/gallium/drivers/r300/r300_screen_buffer.c
+++ b/src/gallium/drivers/r300/r300_screen_buffer.c
@@ -102,7 +102,7 @@ r300_buffer_transfer_map( struct pipe_context *context,
 
 /* Create a new one in the same pipe_resource. */
 new_buf = r300->rws->buffer_create(r300->rws, rbuf->b.b.width0,
-   R300_BUFFER_ALIGNMENT, TRUE,
+   R300_BUFFER_ALIGNMENT,
rbuf->domain, 0);
 if (new_buf) {
 /* Discard the old buffer. */
@@ -183,7 +183,7 @@ struct pipe_resource *r300_buffer_create(struct pipe_screen 
*screen,
 
 rbuf->buf =
 r300screen->rws->buffer_create(r300screen->rws, rbuf->b.b.width0,
-   R300_BUFFER_ALIGNMENT, TRUE,
+   R300_BUFFER_ALIGNMENT,
rbuf->domain, 0);
 if (!rbuf->buf) {
 FREE(rbuf);
diff --git a/src/gallium/drivers/r300/r300_texture.c 
b/src/gallium/drivers/r300/r300_texture.c
index da51661..df01673 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -1047,7 +1047,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
 
 /* Create the backing buffer if needed. */
 if (!tex->buf) {
-tex->buf = rws->buffer_create(rws, tex->tex.size_in_bytes, 2048, TRUE,
+tex->buf = rws->buffer_create(rws, tex->tex.size_in_bytes, 2048,
   tex->domain, 0);
 
 if (!tex->buf) {
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index 1955dab..6b46dfa 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -176,7 +176,6 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
 
/* Allocate a new resource. */
new_buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
-true,
 res->domains, flags);
if (!new_buf) {
return false;
diff --git a/src/gallium/drivers/radeon/radeon_video.c 
b/src/gallium/drivers/radeon/radeon_video.c
index 8dd32ea..e2ff037 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -185,7 +185,7 @@ void rvid_join_surfaces(struct radeon_winsys* ws,
/* TODO: 2D tiling workaround */
alignment *= 2;
 
-   pb = ws->buffer_create(ws, size, alignment, TRUE, RADEON_DOMAIN_VRAM, 
0);
+   pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, 0);
if (!pb)
re

[Mesa-dev] [PATCH 1/3] radeon/video: always use the reusable buffer pool

[Nicolai Hähnle]

From: Nicolai Hähnle 

A semantic error was introduced in a past refactoring that caused the bind
parameter to be passed into the use_reusable_pool parameter of buffer_create.
Since this clearly makes no sense, and there is no clear reason why the
cache _shouldn't_ be used, just use the cache always.

Cc: Christian König 
---
 src/gallium/drivers/r600/r600_uvd.c   | 2 +-
 src/gallium/drivers/radeon/radeon_video.c | 4 ++--
 src/gallium/drivers/radeon/radeon_video.h | 2 +-
 src/gallium/drivers/radeonsi/si_uvd.c | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_uvd.c 
b/src/gallium/drivers/r600/r600_uvd.c
index 0c92834..628ba2a 100644
--- a/src/gallium/drivers/r600/r600_uvd.c
+++ b/src/gallium/drivers/r600/r600_uvd.c
@@ -115,7 +115,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct 
pipe_context *pipe,
surfaces[i] = &resources[i]->surface;
}
 
-   rvid_join_surfaces(ctx->b.ws, templ.bind, pbs, surfaces);
+   rvid_join_surfaces(ctx->b.ws, pbs, surfaces);
 
for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
if (!resources[i])
diff --git a/src/gallium/drivers/radeon/radeon_video.c 
b/src/gallium/drivers/radeon/radeon_video.c
index 24b0eed..8dd32ea 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -130,7 +130,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct 
rvid_buffer* buffer)
  * join surfaces into the same buffer with identical tiling params
  * sumup their sizes and replace the backend buffers with a single bo
  */
-void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
+void rvid_join_surfaces(struct radeon_winsys* ws,
struct pb_buffer** buffers[VL_NUM_COMPONENTS],
struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 {
@@ -185,7 +185,7 @@ void rvid_join_surfaces(struct radeon_winsys* ws, unsigned 
bind,
/* TODO: 2D tiling workaround */
alignment *= 2;
 
-   pb = ws->buffer_create(ws, size, alignment, bind, RADEON_DOMAIN_VRAM, 
0);
+   pb = ws->buffer_create(ws, size, alignment, TRUE, RADEON_DOMAIN_VRAM, 
0);
if (!pb)
return;
 
diff --git a/src/gallium/drivers/radeon/radeon_video.h 
b/src/gallium/drivers/radeon/radeon_video.h
index c9ee67f..39305b4 100644
--- a/src/gallium/drivers/radeon/radeon_video.h
+++ b/src/gallium/drivers/radeon/radeon_video.h
@@ -66,7 +66,7 @@ void rvid_clear_buffer(struct pipe_context *context, struct 
rvid_buffer* buffer)
 
 /* join surfaces into the same buffer with identical tiling params
sumup their sizes and replace the backend buffers with a single bo */
-void rvid_join_surfaces(struct radeon_winsys* ws, unsigned bind,
+void rvid_join_surfaces(struct radeon_winsys* ws,
 struct pb_buffer** buffers[VL_NUM_COMPONENTS],
 struct radeon_surf *surfaces[VL_NUM_COMPONENTS]);
 
diff --git a/src/gallium/drivers/radeonsi/si_uvd.c 
b/src/gallium/drivers/radeonsi/si_uvd.c
index 95bfecd..8c3e5fd 100644
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -97,7 +97,7 @@ struct pipe_video_buffer *si_video_buffer_create(struct 
pipe_context *pipe,
pbs[i] = &resources[i]->resource.buf;
}
 
-   rvid_join_surfaces(ctx->b.ws, templ.bind, pbs, surfaces);
+   rvid_join_surfaces(ctx->b.ws, pbs, surfaces);
 
for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
if (!resources[i])
-- 
2.5.0

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Re: [Mesa-dev] [PATCH 4/4] gbm: Add map/unmap functions

[Rob Herring]

On Fri, Apr 22, 2016 at 6:32 PM, Emil Velikov  wrote:
> Hi Rob,
>
> On 22 April 2016 at 16:50, Rob Herring  wrote:
>> This adds map and unmap functions to GBM utilizing the DRIimage extension
>> mapImage/unmapImage functions or existing internal mapping for dumb
>> buffers.
> Ftr that this is quite sensitive and apart from the obvious breakage
> (coming in a second) it will need some testing on a gnome-continuous
> setup (iirc some used to hand out in #xorg-devel)
>
>> Unlike prior attempts, this version provides a region to map and
>> usage flags for the mapping. The operation follows the same semantics as
>> the gallium transfer_map() function.
>>
>> This was tested with GBM based gralloc on Android.
>>
>> This still creates a context, but I've moved it into gbm_create_device
>> rather than in the map function. This should remove any need for reference
>> counting and problems with memory leaks.
>>
>> Signed-off-by: Rob Herring 

[...]

>> +static void *
>> +gbm_dri_bo_map(struct gbm_bo *_bo,
>> +  uint32_t x, uint32_t y,
>> +  uint32_t width, uint32_t height,
>> +  uint32_t flags, uint32_t *stride, void **map_data)
>> +{
>> +   struct gbm_dri_device *dri = gbm_dri_device(_bo->gbm);
>> +   struct gbm_dri_bo *bo = gbm_dri_bo(_bo);
>> +
>> +   /* If it's a dumb buffer, we already have a mapping */
>> +   if (bo->map) {
>> +  *map_data = (char *)bo->map + (bo->base.base.stride * y) + (x * 4);
>> +  *stride = bo->base.base.stride;
>> +  return *map_data;
> How did you test this ? I'm not sure if we'll even hit it (or we
> should hit it actually).

I haven't. It will get hit if you use GBM_BO_USE_WRITE. That (or no
image ext) causes a dumb buffer to be used and mmapped on allocate.

[...]

>> @@ -1004,6 +1058,10 @@ dri_device_create(int fd)
>> if (ret)
>>goto err_dri;
>>
>> +   if (dri->image->base.version >= 12)
>> +  dri->context = dri->dri2->createNewContext(dri->screen, NULL,
>> + NULL, NULL);
>> +
> Have you measured how much this costs us (cpu time and/or memory) ?

No, will do.

>> + * and errno is set.
>> + *
>> + * \sa enum gbm_bo_transfer_flags for the list of flags
>> + */
> Imho the documentation would be better in the header - for users to
> see. Actually same goes for the rest of the file.

I just followed what was done for the rest of the file. Are you
suggesting I do that first?

> Can we take a look at the GBM gralloc as well. One thing that worries
> me is that (most likely) you are requesting/creating a bo without
> GBM_BO_USE_WRITE whist using MAP + CPU write UNMAP. If you do set the
> USE_WRITE flag, you're getting a dumb buffer, which I'm not sure how
> well is going to work.

I'm not using GBM_BO_USE_WRITE and that is not a condition for mapping
given that flag is tied to cursors (according to comments) and gives
dumb buffers. Also of note, if gralloc flags are set for r/w often,
then I request a linear buffer. Here's the gralloc side:

https://github.com/robherring/gbm_gralloc

> Whichever way one goes, we want to clearly define/describe the
> expected behaviour with the different GBM_BO_USE and GBM_BO_TRANSFER
> flags.

Ultimately, it is probably going to be dependent on the gallium
drivers. At the GBM level there is no restriction. If the drivers have
cases where mappings can fail, then that is going to propagate up. I
was under the impression that is not the case, but that the mapping
process could be slow. I'm not sure how we would determine either it
could fail or that it would be slow.

Rob
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Re: [Mesa-dev] [PATCH v2] anv_device: Set the compressed texture feature flags correctly

[Jason Ekstrand]

On Fri, Apr 22, 2016 at 6:58 PM, Nanley Chery  wrote:

> On Fri, Apr 22, 2016 at 05:22:13PM -0700, Jason Ekstrand wrote:
> > On Fri, Apr 22, 2016 at 4:38 PM, Nanley Chery 
> wrote:
> >
> > > From: Nanley Chery 
> > >
> > > Sampling from an ETC2 texture is supported on Bay Trail and
> > > from Gen8 onwards. While ASTC_LDR is supported on Gen9, the
> > > logic to handle such formats has not yet been implemented in
> > > the driver.
> > >
> > > Fixes dEQP-VK.api.info.format_properties.compressed_formats.
> > >
> > > v2: Enable ETC2 for Bay Trail (Kenneth Graunke)
> > >
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94896
> > > Signed-off-by: Nanley Chery 
> > > ---
> > >  src/intel/vulkan/anv_device.c | 5 +++--
> > >  1 file changed, 3 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/src/intel/vulkan/anv_device.c
> b/src/intel/vulkan/anv_device.c
> > > index 00edd95..4abcdf9 100644
> > > --- a/src/intel/vulkan/anv_device.c
> > > +++ b/src/intel/vulkan/anv_device.c
> > > @@ -380,8 +380,9 @@ void anv_GetPhysicalDeviceFeatures(
> > >.alphaToOne   = true,
> > >.multiViewport= true,
> > >.samplerAnisotropy= false, /* FINISHME
> */
> > > -  .textureCompressionETC2   = true,
> > > -  .textureCompressionASTC_LDR   = true,
> > > +  .textureCompressionETC2   = pdevice->info->gen
> >= 8
> > > ||
> > > +
> > > pdevice->info->is_baytrail,
> > > +  .textureCompressionASTC_LDR   = false, /* FINISHME
> */
> > >
> >
> > So... I thought that when I turned this on it passed all the ASTC CTS
> > tests.  We should double-check that before turning it off.
> > --Jason
> >
>
> We currently pass the dEQP-VK.api.info.format_properties.astc* tests
> because they don't penalize the driver for advertising a featureless
> format (VkFormatProperties = {0}) when the format isn't required. The
> compressed_formats test fails however, because it actually references
> VkPhysicalDeviceFeatures and sees the discrepancy.
>

Ok.  We should try turning them on at some point and see how far we get on
the CTS tests.


> - Nanley
>
> >
> > >.textureCompressionBC = true,
> > >.occlusionQueryPrecise= true,
> > >.pipelineStatisticsQuery  = false,
> > > --
> > > 2.8.0
> > >
> > > ___
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> > > mesa-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > >
>
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Re: [Mesa-dev] [PATCH v2] anv_device: Set the compressed texture feature flags correctly

[Nanley Chery]

On Fri, Apr 22, 2016 at 05:22:13PM -0700, Jason Ekstrand wrote:
> On Fri, Apr 22, 2016 at 4:38 PM, Nanley Chery  wrote:
> 
> > From: Nanley Chery 
> >
> > Sampling from an ETC2 texture is supported on Bay Trail and
> > from Gen8 onwards. While ASTC_LDR is supported on Gen9, the
> > logic to handle such formats has not yet been implemented in
> > the driver.
> >
> > Fixes dEQP-VK.api.info.format_properties.compressed_formats.
> >
> > v2: Enable ETC2 for Bay Trail (Kenneth Graunke)
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94896
> > Signed-off-by: Nanley Chery 
> > ---
> >  src/intel/vulkan/anv_device.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> > index 00edd95..4abcdf9 100644
> > --- a/src/intel/vulkan/anv_device.c
> > +++ b/src/intel/vulkan/anv_device.c
> > @@ -380,8 +380,9 @@ void anv_GetPhysicalDeviceFeatures(
> >.alphaToOne   = true,
> >.multiViewport= true,
> >.samplerAnisotropy= false, /* FINISHME */
> > -  .textureCompressionETC2   = true,
> > -  .textureCompressionASTC_LDR   = true,
> > +  .textureCompressionETC2   = pdevice->info->gen >= 8
> > ||
> > +
> > pdevice->info->is_baytrail,
> > +  .textureCompressionASTC_LDR   = false, /* FINISHME */
> >
> 
> So... I thought that when I turned this on it passed all the ASTC CTS
> tests.  We should double-check that before turning it off.
> --Jason
> 

We currently pass the dEQP-VK.api.info.format_properties.astc* tests
because they don't penalize the driver for advertising a featureless
format (VkFormatProperties = {0}) when the format isn't required. The
compressed_formats test fails however, because it actually references
VkPhysicalDeviceFeatures and sees the discrepancy.

- Nanley

> 
> >.textureCompressionBC = true,
> >.occlusionQueryPrecise= true,
> >.pipelineStatisticsQuery  = false,
> > --
> > 2.8.0
> >
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> >
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Re: [Mesa-dev] [PATCH 1/4] gbm: Add Android build support

[Rob Herring]

On Fri, Apr 22, 2016 at 5:57 PM, Emil Velikov  wrote:
> Hi Rob,
>
> On 22 April 2016 at 16:50, Rob Herring  wrote:
>
>> --- /dev/null
>> +++ b/src/gbm/Android.mk
>
>> +LOCAL_EXPORT_C_INCLUDE_DIRS := \
>> +   $(LOCAL_PATH)/main
>> +
> You don't need this.

Uhh, yes I do. This is how you get the include path added when
gbm_gralloc adds libgbm as a dependency.

Rob
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Re: [Mesa-dev] [PATCH 10/13] i965/blorp: Make all of brw_blorp.h accessable to C

[Matt Turner]

Subject: s/accessable/accessible/
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Re: [Mesa-dev] [PATCH v2] anv_device: Set the compressed texture feature flags correctly

[Jason Ekstrand]

On Fri, Apr 22, 2016 at 4:38 PM, Nanley Chery  wrote:

> From: Nanley Chery 
>
> Sampling from an ETC2 texture is supported on Bay Trail and
> from Gen8 onwards. While ASTC_LDR is supported on Gen9, the
> logic to handle such formats has not yet been implemented in
> the driver.
>
> Fixes dEQP-VK.api.info.format_properties.compressed_formats.
>
> v2: Enable ETC2 for Bay Trail (Kenneth Graunke)
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94896
> Signed-off-by: Nanley Chery 
> ---
>  src/intel/vulkan/anv_device.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 00edd95..4abcdf9 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -380,8 +380,9 @@ void anv_GetPhysicalDeviceFeatures(
>.alphaToOne   = true,
>.multiViewport= true,
>.samplerAnisotropy= false, /* FINISHME */
> -  .textureCompressionETC2   = true,
> -  .textureCompressionASTC_LDR   = true,
> +  .textureCompressionETC2   = pdevice->info->gen >= 8
> ||
> +
> pdevice->info->is_baytrail,
> +  .textureCompressionASTC_LDR   = false, /* FINISHME */
>

So... I thought that when I turned this on it passed all the ASTC CTS
tests.  We should double-check that before turning it off.
--Jason


>.textureCompressionBC = true,
>.occlusionQueryPrecise= true,
>.pipelineStatisticsQuery  = false,
> --
> 2.8.0
>
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[Mesa-dev] [PATCH v2] anv_device: Set the compressed texture feature flags correctly

[Nanley Chery]

From: Nanley Chery 

Sampling from an ETC2 texture is supported on Bay Trail and
from Gen8 onwards. While ASTC_LDR is supported on Gen9, the
logic to handle such formats has not yet been implemented in
the driver.

Fixes dEQP-VK.api.info.format_properties.compressed_formats.

v2: Enable ETC2 for Bay Trail (Kenneth Graunke)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94896
Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_device.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 00edd95..4abcdf9 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -380,8 +380,9 @@ void anv_GetPhysicalDeviceFeatures(
   .alphaToOne   = true,
   .multiViewport= true,
   .samplerAnisotropy= false, /* FINISHME */
-  .textureCompressionETC2   = true,
-  .textureCompressionASTC_LDR   = true,
+  .textureCompressionETC2   = pdevice->info->gen >= 8 ||
+  pdevice->info->is_baytrail,
+  .textureCompressionASTC_LDR   = false, /* FINISHME */
   .textureCompressionBC = true,
   .occlusionQueryPrecise= true,
   .pipelineStatisticsQuery  = false,
-- 
2.8.0

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Re: [Mesa-dev] [PATCH v2 03/25] anv: tweak the %.json rule

[Jason Ekstrand]

On Apr 22, 2016 11:05, "Emil Velikov"  wrote:
>
> On 22 April 2016 at 18:58, Jason Ekstrand  wrote:
> > I'm not sure what I think of this.  I don't think dev_icd is the only
icd
> > file we're going to need to build.  Right now, we don't build the
regular
> > ICD but I think we want to eventually in which case having a general
rule is
> > a good thing.
> >
> How about we revert the patch when/if that happens ?

I'm fine with that

Ack
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Re: [Mesa-dev] [PATCH 4/4] gbm: Add map/unmap functions

[Emil Velikov]

Hi Rob,

On 22 April 2016 at 16:50, Rob Herring  wrote:
> This adds map and unmap functions to GBM utilizing the DRIimage extension
> mapImage/unmapImage functions or existing internal mapping for dumb
> buffers.
Ftr that this is quite sensitive and apart from the obvious breakage
(coming in a second) it will need some testing on a gnome-continuous
setup (iirc some used to hand out in #xorg-devel)

> Unlike prior attempts, this version provides a region to map and
> usage flags for the mapping. The operation follows the same semantics as
> the gallium transfer_map() function.
>
> This was tested with GBM based gralloc on Android.
>
> This still creates a context, but I've moved it into gbm_create_device
> rather than in the map function. This should remove any need for reference
> counting and problems with memory leaks.
>
> Signed-off-by: Rob Herring 
> ---
>  src/gbm/backends/dri/gbm_dri.c| 62 
> +--
>  src/gbm/backends/dri/gbm_driint.h |  5 ++--
>  src/gbm/gbm-symbols-check |  2 ++
>  src/gbm/main/gbm.c| 51 
>  src/gbm/main/gbm.h| 25 
>  src/gbm/main/gbmint.h |  6 
>  6 files changed, 147 insertions(+), 4 deletions(-)
>
> diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
> index 0625422..c93dc9c 100644
> --- a/src/gbm/backends/dri/gbm_dri.c
> +++ b/src/gbm/backends/dri/gbm_dri.c
> @@ -32,6 +32,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>
>  #include 
>  #include 
> @@ -603,7 +604,7 @@ gbm_dri_bo_destroy(struct gbm_bo *_bo)
> if (bo->image != NULL) {
>dri->image->destroyImage(bo->image);
> } else {
> -  gbm_dri_bo_unmap(bo);
> +  gbm_dri_bo_unmap_dumb(bo);
Trivial things first - please split the renames to a separate patch.
As is the egl+gbm on swrast is broken - it should be using the *_dumb
functions.

>memset(&arg, 0, sizeof(arg));
>arg.handle = bo->handle;
>drmIoctl(dri->base.base.fd, DRM_IOCTL_MODE_DESTROY_DUMB, &arg);
> @@ -828,7 +829,7 @@ create_dumb(struct gbm_device *gbm,
> bo->handle = create_arg.handle;
> bo->size = create_arg.size;
>
> -   if (gbm_dri_bo_map(bo) == NULL)
> +   if (gbm_dri_bo_map_dumb(bo) == NULL)
>goto destroy_dumb;
>
> return &bo->base.base;
> @@ -924,6 +925,54 @@ failed:
> return NULL;
>  }
>
> +static void *
> +gbm_dri_bo_map(struct gbm_bo *_bo,
> +  uint32_t x, uint32_t y,
> +  uint32_t width, uint32_t height,
> +  uint32_t flags, uint32_t *stride, void **map_data)
> +{
> +   struct gbm_dri_device *dri = gbm_dri_device(_bo->gbm);
> +   struct gbm_dri_bo *bo = gbm_dri_bo(_bo);
> +
> +   /* If it's a dumb buffer, we already have a mapping */
> +   if (bo->map) {
> +  *map_data = (char *)bo->map + (bo->base.base.stride * y) + (x * 4);
> +  *stride = bo->base.base.stride;
> +  return *map_data;
How did you test this ? I'm not sure if we'll even hit it (or we
should hit it actually).

> +   }
> +
> +   if (!dri->image || dri->image->base.version < 12) {
> +  errno = ENOSYS;
> +  return NULL;
> +   }
> +
> +   if (!dri->context)
> +  return NULL;
> +
> +   /* GBM flags and DRI flags are the same, so just pass them on */
> +   return dri->image->mapImage(dri->context, bo->image, x, y,
> +   width, height, flags, stride, map_data);
> +}
> +
> +static void
> +gbm_dri_bo_unmap(struct gbm_bo *_bo, void *map_data)
> +{
> +   struct gbm_dri_device *dri = gbm_dri_device(_bo->gbm);
> +   struct gbm_dri_bo *bo = gbm_dri_bo(_bo);
> +
> +   /* Check if it's a dumb buffer */
> +   if (bo->map) {
> +  assert((map_data >= bo->map) && (map_data < (bo->map + bo->size)));
Nit: try to avoid multiple expressions within single assert. Then
again the whole if statement should go imho (similar to the map above)

> +  return;
> +   }
> +
> +   if (!dri->image || !dri->context || dri->image->base.version < 12)
Bikeshed: flip the order - context, image, image.foo

> +  return;
> +
> +   dri->image->unmapImage(dri->context, bo->image, map_data);
> +}
> +
> +
>  static struct gbm_surface *
>  gbm_dri_surface_create(struct gbm_device *gbm,
> uint32_t width, uint32_t height,
> @@ -958,6 +1007,9 @@ dri_destroy(struct gbm_device *gbm)
> struct gbm_dri_device *dri = gbm_dri_device(gbm);
> unsigned i;
>
> +   if (dri->context)
> +  dri->core->destroyContext(dri->context);
> +
> dri->core->destroyScreen(dri->screen);
> for (i = 0; dri->driver_configs[i]; i++)
>free((__DRIconfig *) dri->driver_configs[i]);
> @@ -981,6 +1033,8 @@ dri_device_create(int fd)
> dri->base.base.fd = fd;
> dri->base.base.bo_create = gbm_dri_bo_create;
> dri->base.base.bo_import = gbm_dri_bo_import;
> +   dri->base.base.bo_map = gbm_dri_bo_map;
> +   dri->base.base.bo_unmap = gbm_dri_bo_unmap;
> dri->base.base.is_format_s

Re: [Mesa-dev] [PATCH] i965: Disable KHR_texture_compression_astc_hdr on Gen9

[Kenneth Graunke]

On Tuesday, April 12, 2016 5:34:49 PM PDT Nanley Chery wrote:
> From: Nanley Chery 
> 
> Although Gen9 samples from most HDR ASTC surfaces of correctly,
> there currently are no software workarounds to fix the incorrect
> sampling that occurs in others of certain color endpoint modes.
> 
> With this change, we are no longer failing the 14 tests from:
>dEQP-GLES3.functional.texture.compressed.astc.endpoint_value_hdr_cem_15.*
> 
> Signed-off-by: Nanley Chery 
> ---
>  src/mesa/drivers/dri/i965/brw_surface_formats.c | 6 +++---
>  src/mesa/drivers/dri/i965/intel_extensions.c| 1 -
>  2 files changed, 3 insertions(+), 4 deletions(-)

This seems like the right thing to do, given that we believe the Windows
driver isn't planning on exposing this either.  We could probably store
alpha separately and double-sample, but I'm not sure whether it's worth
doing or not.

Acked-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 2/2] i965/tex_image: Flush certain subnormal ASTC channel values

[Kenneth Graunke]

On Tuesday, April 12, 2016 3:30:14 PM PDT Nanley Chery wrote:
> From: Nanley Chery 
> 
> When uploading a linear, void-extent, ASTC LDR block on Skylake, we are
> required to flush to zero the UNORM16 channel values that would be
> denormalized. This is specifically required for the values: 1, 2, and 3.
> 
> Fixes the 14 failing tests in:
>dEQP-GLES3.functional.texture.compressed.astc.void_extent_ldr.*
> 
> v2: Split out flushing function (Kristian Høgsberg)
> 
> Signed-off-by: Nanley Chery 
> ---
>  src/mesa/drivers/dri/i965/intel_tex_image.c | 87 ++
+++
>  1 file changed, 87 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/
dri/i965/intel_tex_image.c
> index 1601edd..9a26450 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_image.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
> @@ -5,6 +5,7 @@
>  #include "main/bufferobj.h"
>  #include "main/context.h"
>  #include "main/formats.h"
> +#include "main/glformats.h"
>  #include "main/image.h"
>  #include "main/pbo.h"
>  #include "main/renderbuffer.h"
> @@ -511,10 +512,96 @@ intel_get_tex_sub_image(struct gl_context *ctx,
> DBG("%s - DONE\n", __func__);
>  }
>  
> +static void
> +flush_astc_denorms(struct gl_context *ctx, GLuint dims,
> +   struct gl_texture_image *texImage,
> +   GLint xoffset, GLint yoffset, GLint zoffset,
> +   GLsizei width, GLsizei height, GLsizei depth)
> +{
> +   struct compressed_pixelstore store;
> +   _mesa_compute_compressed_pixelstore(dims, texImage->TexFormat,
> +   width, height, depth,
> +   &ctx->Unpack, &store);
> +
> +   for (int slice = 0; slice < store.CopySlices; slice++) {
> +
> +  /* Map dest texture buffer */
> +  GLubyte *dstMap;
> +  GLint dstRowStride;
> +  ctx->Driver.MapTextureImage(ctx, texImage, slice + zoffset,
> +  xoffset, yoffset, width, height,
> +  GL_MAP_WRITE_BIT | 
GL_MAP_INVALIDATE_RANGE_BIT,

It looks like you're reading the data from the buffer and rewriting it,
so shouldn't this be GL_MAP_READ_BIT | GL_MAP_WRITE_BIT?

With that fixed, this patch is:
Acked-by: Kenneth Graunke 

> +  &dstMap, &dstRowStride);
> +  if (!dstMap)
> + continue;
> +
> +  for (int i = 0; i < store.CopyRowsPerSlice; i++) {
> +
> + /* An ASTC block is stored in little endian mode. The byte that
> +  * contains bits 0..7 is stored at the lower address in memory.
> +  */
> + struct astc_void_extent {
> +uint16_t header : 12;
> +uint16_t dontcare[3];
> +uint16_t R;
> +uint16_t G;
> +uint16_t B;
> +uint16_t A;
> + } *blocks = (struct astc_void_extent*) dstMap;
> +
> + /* Iterate over every copied block in the row */
> + for (int j = 0; j < store.CopyBytesPerRow / 16; j++) {
> +
> +/* Check if the header matches that of an LDR void-extent block 
*/
> +if (blocks[j].header == 0xDFC) {
> +
> +   /* Flush UNORM16 values that would be denormalized */
> +   if (blocks[j].A < 4) blocks[j].A = 0;
> +   if (blocks[j].B < 4) blocks[j].B = 0;
> +   if (blocks[j].G < 4) blocks[j].G = 0;
> +   if (blocks[j].R < 4) blocks[j].R = 0;
> +}
> + }
> +
> + dstMap += dstRowStride;
> +  }
> +
> +  ctx->Driver.UnmapTextureImage(ctx, texImage, slice + zoffset);
> +   }
> +}
> +
> +
> +static void
> +intelCompressedTexSubImage(struct gl_context *ctx, GLuint dims,
> +struct gl_texture_image *texImage,
> +GLint xoffset, GLint yoffset, GLint zoffset,
> +GLsizei width, GLsizei height, GLsizei depth,
> +GLenum format,
> +GLsizei imageSize, const GLvoid *data)
> +{
> +   /* Upload the compressed data blocks */
> +   _mesa_store_compressed_texsubimage(ctx, dims, texImage,
> +  xoffset, yoffset, zoffset,
> +  width, height, depth,
> +  format, imageSize, data);
> +
> +   /* Fix up copied ASTC blocks if necessary */
> +   GLenum gl_format = _mesa_compressed_format_to_glenum(ctx,
> +texImage-
>TexFormat);
> +   bool is_linear_astc = _mesa_is_astc_format(gl_format) &&
> +!_mesa_is_srgb_format(gl_format);
> +   struct brw_context *brw = (struct brw_context*) ctx;
> +   if (brw->gen == 9 && is_linear_astc)
> +  flush_astc_denorms(ctx, dims, texImage,
> + xoffset, yoffset, zoffset,
> + width, height, depth);
> +}
> +
>  void
>  intelInitTextureIm

[Mesa-dev] [PATCH 04/13] i965/blorp: Remove the hiz params class

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.cpp | 58 +
 src/mesa/drivers/dri/i965/brw_blorp.h   | 21 +++-
 2 files changed, 42 insertions(+), 37 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 0fa1734..19cb90f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -176,6 +176,15 @@ brw_blorp_params::brw_blorp_params()
 }
 
 extern "C" {
+/**
+ * Perform a HiZ or depth resolve operation.
+ *
+ * For an overview of HiZ ops, see the following sections of the Sandy Bridge
+ * PRM, Volume 1, Part 2:
+ *   - 7.5.3.1 Depth Buffer Clear
+ *   - 7.5.3.2 Depth Buffer Resolve
+ *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
+ */
 void
 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
   unsigned int level, unsigned int layer, gen6_hiz_op op)
@@ -203,8 +212,7 @@ intel_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
if (brw->gen >= 8) {
   gen8_hiz_exec(brw, mt, level, layer, op);
} else {
-  brw_hiz_op_params params(mt, level, layer, op);
-  brw_blorp_exec(brw, ¶ms);
+  gen6_blorp_hiz_exec(brw, mt, level, layer, op);
}
 }
 
@@ -298,14 +306,15 @@ retry:
brw_emit_mi_flush(brw);
 }
 
-brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
- unsigned int level,
- unsigned int layer,
- gen6_hiz_op op)
+void
+gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
+unsigned int level, unsigned int layer, enum gen6_hiz_op 
op)
 {
-   this->hiz_op = op;
+   brw_blorp_params params;
 
-   depth.set(mt, level, layer);
+   params.hiz_op = op;
+
+   params.depth.set(mt, level, layer);
 
/* Align the rectangle primitive to 8x4 pixels.
 *
@@ -332,24 +341,33 @@ brw_hiz_op_params::brw_hiz_op_params(struct 
intel_mipmap_tree *mt,
 * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
 * prevents the clobbering.
 */
-   dst.num_samples = mt->num_samples;
-   if (dst.num_samples > 1) {
-  depth.width = ALIGN(mt->logical_width0, 8);
-  depth.height = ALIGN(mt->logical_height0, 4);
+   params.dst.num_samples = mt->num_samples;
+   if (params.dst.num_samples > 1) {
+  params.depth.width = ALIGN(mt->logical_width0, 8);
+  params.depth.height = ALIGN(mt->logical_height0, 4);
} else {
-  depth.width = ALIGN(depth.width, 8);
-  depth.height = ALIGN(depth.height, 4);
+  params.depth.width = ALIGN(params.depth.width, 8);
+  params.depth.height = ALIGN(params.depth.height, 4);
}
 
-   x1 = depth.width;
-   y1 = depth.height;
+   params.x1 = params.depth.width;
+   params.y1 = params.depth.height;
 
assert(intel_miptree_level_has_hiz(mt, level));
 
switch (mt->format) {
-   case MESA_FORMAT_Z_UNORM16:   depth_format = BRW_DEPTHFORMAT_D16_UNORM; 
break;
-   case MESA_FORMAT_Z_FLOAT32: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break;
-   case MESA_FORMAT_Z24_UNORM_X8_UINT:depth_format = 
BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break;
-   default:unreachable("not reached");
+   case MESA_FORMAT_Z_UNORM16:
+  params.depth_format = BRW_DEPTHFORMAT_D16_UNORM;
+  break;
+   case MESA_FORMAT_Z_FLOAT32:
+  params.depth_format = BRW_DEPTHFORMAT_D32_FLOAT;
+  break;
+   case MESA_FORMAT_Z24_UNORM_X8_UINT:
+  params.depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
+  break;
+   default:
+  unreachable("not reached");
}
+
+   brw_blorp_exec(brw, ¶ms);
 }
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 64f197e..96657e1 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -266,6 +266,10 @@ void
 brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params);
 
 void
+gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
+unsigned level, unsigned layer, enum gen6_hiz_op op);
+
+void
 gen6_blorp_exec(struct brw_context *brw,
 const brw_blorp_params *params);
 
@@ -276,23 +280,6 @@ gen7_blorp_exec(struct brw_context *brw,
 void
 gen8_blorp_exec(struct brw_context *brw, const brw_blorp_params *params);
 
-/**
- * Parameters for a HiZ or depth resolve operation.
- *
- * For an overview of HiZ ops, see the following sections of the Sandy Bridge
- * PRM, Volume 1, Part 2:
- *   - 7.5.3.1 Depth Buffer Clear
- *   - 7.5.3.2 Depth Buffer Resolve
- *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
- */
-class brw_hiz_op_params : public brw_blorp_params
-{
-public:
-   brw_hiz_op_params(struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int layer,
- gen6_hiz_op op);
-};
-
 struct brw_blorp_blit_prog_key
 {
/* Number of samples per pixel tha

[Mesa-dev] [PATCH 11/13] i965/blorp: Convert brw_blorp.cpp to a C file

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/Makefile.sources |   2 +-
 src/mesa/drivers/dri/i965/brw_blorp.c  | 344 
 src/mesa/drivers/dri/i965/brw_blorp.cpp| 347 -
 3 files changed, 345 insertions(+), 348 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/brw_blorp.c
 delete mode 100644 src/mesa/drivers/dri/i965/brw_blorp.cpp

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 632f2e9..fe70d3a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -100,7 +100,7 @@ i965_FILES = \
brw_blorp_blit_eu.cpp \
brw_blorp_blit_eu.h \
brw_blorp_clear.cpp \
-   brw_blorp.cpp \
+   brw_blorp.c \
brw_blorp.h \
brw_cc.c \
brw_clear.c \
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
new file mode 100644
index 000..9f05cb9
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include "intel_batchbuffer.h"
+#include "intel_fbo.h"
+
+#include "brw_blorp.h"
+#include "brw_state.h"
+
+#define FILE_DEBUG_FLAG DEBUG_BLORP
+
+void
+brw_blorp_surface_info_init(struct brw_context *brw,
+struct brw_blorp_surface_info *info,
+struct intel_mipmap_tree *mt,
+unsigned int level, unsigned int layer,
+mesa_format format, bool is_render_target)
+{
+   /* Layer is a physical layer, so if this is a 2D multisample array texture
+* using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
+* be a multiple of num_samples.
+*/
+   if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
+   mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+  assert(layer % mt->num_samples == 0);
+   }
+
+   intel_miptree_check_level_layer(mt, level, layer);
+
+   info->mt = mt;
+   info->level = level;
+   info->layer = layer;
+   info->width = minify(mt->physical_width0, level - mt->first_level);
+   info->height = minify(mt->physical_height0, level - mt->first_level);
+
+   intel_miptree_get_image_offset(mt, level, layer,
+  &info->x_offset, &info->y_offset);
+
+   info->num_samples = mt->num_samples;
+   info->array_layout = mt->array_layout;
+   info->map_stencil_as_y_tiled = false;
+   info->msaa_layout = mt->msaa_layout;
+   info->swizzle = SWIZZLE_XYZW;
+
+   if (format == MESA_FORMAT_NONE)
+  format = mt->format;
+
+   switch (format) {
+   case MESA_FORMAT_S_UINT8:
+  /* The miptree is a W-tiled stencil buffer.  Surface states can't be set
+   * up for W tiling, so we'll need to use Y tiling and have the WM
+   * program swizzle the coordinates.
+   */
+  info->map_stencil_as_y_tiled = true;
+  info->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
+BRW_SURFACEFORMAT_R8_UNORM;
+  break;
+   case MESA_FORMAT_Z24_UNORM_X8_UINT:
+  /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS
+   * here, but unfortunately it isn't supported as a render target, which
+   * would prevent us from blitting to 24-bit depth.
+   *
+   * The miptree consists of 32 bits per pixel, arranged as 24-bit depth
+   * values interleaved with 8 "don't care" bits.  Since depth values don't
+   * require any blending, it doesn't matter how we interpret the bit
+   * pattern as long as we copy the right amount of data, so just map it
+   * as 8-bit BGRA.
+   */
+  info->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
+  break;
+   case MESA_FORMAT_Z_FLOAT32:
+  info->brw_surfaceformat = BRW_SURF

[Mesa-dev] [PATCH 01/13] i965/blorp: Refactor to get rid of the get_wm_prog virtual function

[Jason Ekstrand]

Instead of having a virtual member function for getting the WM/PS kernel,
we simply add fields for prog_data and the kernel to brw_blorp_parms and
always make sure those get set as part of the different constructors.
---
 src/mesa/drivers/dri/i965/brw_blorp.cpp   | 12 ++-
 src/mesa/drivers/dri/i965/brw_blorp.h | 19 +-
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  | 12 ++-
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 50 ---
 src/mesa/drivers/dri/i965/gen6_blorp.cpp  | 25 ++
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  | 28 +++
 src/mesa/drivers/dri/i965/gen8_blorp.cpp  | 18 --
 7 files changed, 68 insertions(+), 96 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index ce09b09..9dbbd83 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -165,10 +165,11 @@ brw_blorp_params::brw_blorp_params(unsigned num_varyings,
  depth_format(0),
  hiz_op(GEN6_HIZ_OP_NONE),
  fast_clear_op(0),
- use_wm_prog(false),
  num_varyings(num_varyings),
  num_draw_buffers(num_draw_buffers),
- num_layers(num_layers)
+ num_layers(num_layers),
+ wm_prog_kernel(BRW_BLORP_NO_WM_PROG),
+ wm_prog_data(NULL)
 {
color_write_disable[0] = false;
color_write_disable[1] = false;
@@ -354,10 +355,3 @@ brw_hiz_op_params::brw_hiz_op_params(struct 
intel_mipmap_tree *mt,
default:unreachable("not reached");
}
 }
-
-uint32_t
-brw_hiz_op_params::get_wm_prog(struct brw_context *brw,
-   brw_blorp_prog_data **prog_data) const
-{
-   return 0;
-}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 79dc59a..4981afd 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -229,6 +229,7 @@ struct brw_blorp_prog_data
bool persample_msaa_dispatch;
 };
 
+#define BRW_BLORP_NO_WM_PROG 1
 
 class brw_blorp_params
 {
@@ -237,9 +238,6 @@ public:
 unsigned num_draw_buffers = 1,
 unsigned num_layers = 1);
 
-   virtual uint32_t get_wm_prog(struct brw_context *brw,
-brw_blorp_prog_data **prog_data) const = 0;
-
uint32_t x0;
uint32_t y0;
uint32_t x1;
@@ -251,11 +249,18 @@ public:
enum gen6_hiz_op hiz_op;
unsigned fast_clear_op;
bool color_write_disable[4];
-   bool use_wm_prog;
brw_blorp_wm_push_constants wm_push_consts;
const unsigned num_varyings;
const unsigned num_draw_buffers;
const unsigned num_layers;
+
+   /**
+* The pointer (relative to instruction state base address) to the WM/PS
+* kernel to use for this operation.  If set to BLORP_NO_WM_PROG, the WM
+* stage will be disabled.
+*/
+   uint32_t wm_prog_kernel;
+   struct brw_blorp_prog_data *wm_prog_data;
 };
 
 
@@ -288,9 +293,6 @@ public:
brw_hiz_op_params(struct intel_mipmap_tree *mt,
  unsigned int level, unsigned int layer,
  gen6_hiz_op op);
-
-   virtual uint32_t get_wm_prog(struct brw_context *brw,
-brw_blorp_prog_data **prog_data) const;
 };
 
 struct brw_blorp_blit_prog_key
@@ -388,9 +390,6 @@ public:
  GLfloat dst_x1, GLfloat dst_y1,
  GLenum filter, bool mirror_x, bool mirror_y);
 
-   virtual uint32_t get_wm_prog(struct brw_context *brw,
-brw_blorp_prog_data **prog_data) const;
-
 private:
brw_blorp_blit_prog_key wm_prog_key;
 };
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 7556d6a..cbf2d97 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1967,7 +1967,6 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct 
brw_context *brw,
   src.brw_surfaceformat = dst.brw_surfaceformat;
}
 
-   use_wm_prog = true;
memset(&wm_prog_key, 0, sizeof(wm_prog_key));
 
/* texture_data_type indicates the register type that should be used to
@@ -2203,16 +2202,10 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct 
brw_context *brw,
   src.x_offset *= 2;
   src.y_offset /= 2;
}
-}
 
-uint32_t
-brw_blorp_blit_params::get_wm_prog(struct brw_context *brw,
-   brw_blorp_prog_data **prog_data) const
-{
-   uint32_t prog_offset = 0;
if (!brw_search_cache(&brw->cache, BRW_CACHE_BLORP_PROG,
  &this->wm_prog_key, sizeof(this->wm_prog_key),
- &prog_offset, prog_data)) {
+ &this->wm_prog_kernel, &this->wm_prog_data)) {
   brw_blorp_blit_program prog(brw, &this->wm_prog_key);
   GLuint program_size;
   const GLuint *program = prog.compile(brw, INTEL_DEBUG & DEBUG_BLORP,
@@ -

[Mesa-dev] [PATCH 06/13] i965/blorp: Roll mip_info into surface_info

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.cpp | 26 --
 src/mesa/drivers/dri/i965/brw_blorp.h   | 28 +---
 2 files changed, 17 insertions(+), 37 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 19cb90f..e501818 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -30,27 +30,25 @@
 
 #define FILE_DEBUG_FLAG DEBUG_BLORP
 
-brw_blorp_mip_info::brw_blorp_mip_info()
+brw_blorp_surface_info::brw_blorp_surface_info()
: mt(NULL),
  level(0),
  layer(0),
  width(0),
  height(0),
  x_offset(0),
- y_offset(0)
-{
-}
-
-brw_blorp_surface_info::brw_blorp_surface_info()
-   : map_stencil_as_y_tiled(false),
+ y_offset(0),
+ map_stencil_as_y_tiled(false),
  num_samples(0),
  swizzle(SWIZZLE_XYZW)
 {
 }
 
 void
-brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
-unsigned int level, unsigned int layer)
+brw_blorp_surface_info::set(struct brw_context *brw,
+struct intel_mipmap_tree *mt,
+unsigned int level, unsigned int layer,
+mesa_format format, bool is_render_target)
 {
/* Layer is a physical layer, so if this is a 2D multisample array texture
 * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better
@@ -70,15 +68,7 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
this->height = minify(mt->physical_height0, level - mt->first_level);
 
intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
-}
 
-void
-brw_blorp_surface_info::set(struct brw_context *brw,
-struct intel_mipmap_tree *mt,
-unsigned int level, unsigned int layer,
-mesa_format format, bool is_render_target)
-{
-   brw_blorp_mip_info::set(mt, level, layer);
this->num_samples = mt->num_samples;
this->array_layout = mt->array_layout;
this->map_stencil_as_y_tiled = false;
@@ -314,7 +304,7 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
 
params.hiz_op = op;
 
-   params.depth.set(mt, level, layer);
+   params.depth.set(brw, mt, level, layer, mt->format, true);
 
/* Align the rectangle primitive to 8x4 pixels.
 *
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index ca5b1eb..e08693f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -69,14 +69,17 @@ enum {
BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
 };
 
-
-class brw_blorp_mip_info
+class brw_blorp_surface_info
 {
 public:
-   brw_blorp_mip_info();
+   brw_blorp_surface_info();
+
+   void set(struct brw_context *brw,
+struct intel_mipmap_tree *mt,
+unsigned int level, unsigned int layer,
+mesa_format format, bool is_render_target);
 
-   void set(struct intel_mipmap_tree *mt,
-unsigned int level, unsigned int layer);
+   uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 
struct intel_mipmap_tree *mt;
 
@@ -121,19 +124,6 @@ public:
 * pixels.
 */
uint32_t y_offset;
-};
-
-class brw_blorp_surface_info : public brw_blorp_mip_info
-{
-public:
-   brw_blorp_surface_info();
-
-   void set(struct brw_context *brw,
-struct intel_mipmap_tree *mt,
-unsigned int level, unsigned int layer,
-mesa_format format, bool is_render_target);
-
-   uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const;
 
/* Setting this flag indicates that the buffer's contents are W-tiled
 * stencil data, but the surface state should be set up for Y tiled
@@ -240,7 +230,7 @@ public:
uint32_t y0;
uint32_t x1;
uint32_t y1;
-   brw_blorp_mip_info depth;
+   brw_blorp_surface_info depth;
uint32_t depth_format;
brw_blorp_surface_info src;
brw_blorp_surface_info dst;
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 09/13] i965/blorp: Turn brw_blorp_params into a C-stlye struct

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.cpp   | 35 --
 src/mesa/drivers/dri/i965/brw_blorp.h | 43 +--
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  |  3 +-
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  6 ++--
 src/mesa/drivers/dri/i965/gen6_blorp.cpp  | 42 +-
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  | 14 -
 src/mesa/drivers/dri/i965/gen8_blorp.cpp  | 14 -
 7 files changed, 75 insertions(+), 82 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index cd37922..7d7790a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -134,27 +134,17 @@ brw_blorp_compute_tile_offsets(const struct 
brw_blorp_surface_info *info,
 }
 
 
-brw_blorp_params::brw_blorp_params()
-   : x0(0),
- y0(0),
- x1(0),
- y1(0),
- depth_format(0),
- hiz_op(GEN6_HIZ_OP_NONE),
- fast_clear_op(0),
- num_varyings(0),
- num_draw_buffers(1),
- num_layers(1),
- wm_prog_kernel(BRW_BLORP_NO_WM_PROG),
- wm_prog_data(NULL)
+void
+brw_blorp_params_init(struct brw_blorp_params *params)
 {
-   memset(&src, 0, sizeof(src));
-   memset(&dst, 0, sizeof(dst));
-   memset(&depth, 0, sizeof(depth));
-   color_write_disable[0] = false;
-   color_write_disable[1] = false;
-   color_write_disable[2] = false;
-   color_write_disable[3] = false;
+   memset(params, 0, sizeof(*params));
+   params->hiz_op = GEN6_HIZ_OP_NONE;
+   params->fast_clear_op = 0;
+   params->num_varyings = 0;
+   params->num_draw_buffers = 1;
+   params->num_layers = 1;
+   params->wm_prog_kernel = BRW_BLORP_NO_WM_PROG;
+   params->wm_prog_data = NULL;
 }
 
 extern "C" {
@@ -201,7 +191,7 @@ intel_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
 } /* extern "C" */
 
 void
-brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
+brw_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params)
 {
struct gl_context *ctx = &brw->ctx;
const uint32_t estimated_max_batch_usage = brw->gen >= 8 ? 1800 : 1500;
@@ -292,7 +282,8 @@ void
 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 unsigned int level, unsigned int layer, enum gen6_hiz_op 
op)
 {
-   brw_blorp_params params;
+   struct brw_blorp_params params;
+   brw_blorp_params_init(¶ms);
 
params.hiz_op = op;
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index ff36ff4..e9db063 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -219,11 +219,8 @@ struct brw_blorp_prog_data
 
 #define BRW_BLORP_NO_WM_PROG 1
 
-class brw_blorp_params
+struct brw_blorp_params
 {
-public:
-   brw_blorp_params();
-
uint32_t x0;
uint32_t y0;
uint32_t x1;
@@ -235,10 +232,10 @@ public:
enum gen6_hiz_op hiz_op;
unsigned fast_clear_op;
bool color_write_disable[4];
-   brw_blorp_wm_push_constants wm_push_consts;
-   const unsigned num_varyings;
-   const unsigned num_draw_buffers;
-   const unsigned num_layers;
+   struct brw_blorp_wm_push_constants wm_push_consts;
+   unsigned num_varyings;
+   unsigned num_draw_buffers;
+   unsigned num_layers;
 
/**
 * The pointer (relative to instruction state base address) to the WM/PS
@@ -249,9 +246,11 @@ public:
struct brw_blorp_prog_data *wm_prog_data;
 };
 
+void
+brw_blorp_params_init(struct brw_blorp_params *params);
 
 void
-brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params);
+brw_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params);
 
 void
 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
@@ -259,14 +258,14 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
 
 void
 gen6_blorp_exec(struct brw_context *brw,
-const brw_blorp_params *params);
+const struct brw_blorp_params *params);
 
 void
 gen7_blorp_exec(struct brw_context *brw,
-const brw_blorp_params *params);
+const struct brw_blorp_params *params);
 
 void
-gen8_blorp_exec(struct brw_context *brw, const brw_blorp_params *params);
+gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params 
*params);
 
 struct brw_blorp_blit_prog_key
 {
@@ -359,26 +358,26 @@ gen6_blorp_init(struct brw_context *brw);
 
 void
 gen6_blorp_emit_state_base_address(struct brw_context *brw,
-   const brw_blorp_params *params);
+   const struct brw_blorp_params *params);
 
 void
 gen6_blorp_emit_vertices(struct brw_context *brw,
- const brw_blorp_params *params);
+ const struct brw_blorp_params *params);
 
 uint32_t
 gen6_blorp_emit_blend_state(struct brw_context *brw,
-const brw_blorp_params *param

[Mesa-dev] [PATCH 05/13] i965/blorp: Get rid of the blorp_blit_params class

[Jason Ekstrand]

It was really just a wrapper around the function that constructed it.
---
 src/mesa/drivers/dri/i965/brw_blorp.h|  20 --
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 276 +--
 2 files changed, 130 insertions(+), 166 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 96657e1..ca5b1eb 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -359,26 +359,6 @@ struct brw_blorp_blit_prog_key
bool bilinear_filter;
 };
 
-class brw_blorp_blit_params : public brw_blorp_params
-{
-public:
-   brw_blorp_blit_params(struct brw_context *brw,
- struct intel_mipmap_tree *src_mt,
- unsigned src_level, unsigned src_layer,
- mesa_format src_format,
- struct intel_mipmap_tree *dst_mt,
- unsigned dst_level, unsigned dst_layer,
- mesa_format dst_format,
- GLfloat src_x0, GLfloat src_y0,
- GLfloat src_x1, GLfloat src_y1,
- GLfloat dst_x0, GLfloat dst_y0,
- GLfloat dst_x1, GLfloat dst_y1,
- GLenum filter, bool mirror_x, bool mirror_y);
-
-private:
-   brw_blorp_blit_prog_key wm_prog_key;
-};
-
 /**
  * \name BLORP internals
  * \{
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index cbf2d97..56f6ced 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -44,74 +44,6 @@ find_miptree(GLbitfield buffer_bit, struct 
intel_renderbuffer *irb)
return mt;
 }
 
-
-/**
- * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
- * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
- * the physical layer holding sample 0.  So, for example, if
- * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
- * 4*n.
- */
-void
-brw_blorp_blit_miptrees(struct brw_context *brw,
-struct intel_mipmap_tree *src_mt,
-unsigned src_level, unsigned src_layer,
-mesa_format src_format, int src_swizzle,
-struct intel_mipmap_tree *dst_mt,
-unsigned dst_level, unsigned dst_layer,
-mesa_format dst_format,
-float src_x0, float src_y0,
-float src_x1, float src_y1,
-float dst_x0, float dst_y0,
-float dst_x1, float dst_y1,
-GLenum filter, bool mirror_x, bool mirror_y,
-bool decode_srgb, bool encode_srgb)
-{
-   /* Get ready to blit.  This includes depth resolving the src and dst
-* buffers if necessary.  Note: it's not necessary to do a color resolve on
-* the destination buffer because we use the standard render path to render
-* to destination color buffers, and the standard render path is
-* fast-color-aware.
-* Lossless compression is only introduced for gen9 onwards whereas
-* blorp is not supported even for gen8. Therefore it should be impossible
-* to end up here with single sampled compressed surfaces.
-*/
-   assert(!intel_miptree_is_lossless_compressed(brw, src_mt));
-   assert(!intel_miptree_is_lossless_compressed(brw, dst_mt));
-   intel_miptree_resolve_color(brw, src_mt, 0);
-   intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
-   intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
-
-   DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
-   "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
-   __func__,
-   src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
-   src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
-   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
-   dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
-   mirror_x, mirror_y);
-
-   if (!decode_srgb && _mesa_get_format_color_encoding(src_format) == GL_SRGB)
-  src_format = _mesa_get_srgb_format_linear(src_format);
-
-   if (!encode_srgb && _mesa_get_format_color_encoding(dst_format) == GL_SRGB)
-  dst_format = _mesa_get_srgb_format_linear(dst_format);
-
-   brw_blorp_blit_params params(brw,
-src_mt, src_level, src_layer, src_format,
-dst_mt, dst_level, dst_layer, dst_format,
-src_x0, src_y0,
-src_x1, src_y1,
-dst_x0, dst_y0,
-dst_x1, dst_y1,
-filter, mirror_x, mirror_y);
-   params.src.swizzle = src_swizzle;
-
-   brw_blorp_exec(brw, ¶ms);
-
-   intel_miptree

[Mesa-dev] [PATCH 08/13] i965/blorp: Turn coord_transform into a C-stlye struct

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.h| 10 +++---
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 23 +--
 2 files changed, 16 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index be5485c..ff36ff4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -175,16 +175,12 @@ brw_blorp_compute_tile_offsets(const struct 
brw_blorp_surface_info *info,
 
 
 
-struct brw_blorp_coord_transform_params
+struct brw_blorp_coord_transform
 {
-   void setup(GLfloat src0, GLfloat src1, GLfloat dst0, GLfloat dst1,
-  bool mirror);
-
float multiplier;
float offset;
 };
 
-
 struct brw_blorp_wm_push_constants
 {
uint32_t dst_x0;
@@ -194,8 +190,8 @@ struct brw_blorp_wm_push_constants
/* Top right coordinates of the rectangular grid used for scaled blitting */
float rect_grid_x1;
float rect_grid_y1;
-   brw_blorp_coord_transform_params x_transform;
-   brw_blorp_coord_transform_params y_transform;
+   struct brw_blorp_coord_transform x_transform;
+   struct brw_blorp_coord_transform y_transform;
 
/* Minimum layer setting works for all the textures types but texture_3d
 * for which the setting has no effect. Use the z-coordinate instead.
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 00e9e3c..2da9368 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1783,10 +1783,11 @@ brw_blorp_blit_program::render_target_write()
 }
 
 
-void
-brw_blorp_coord_transform_params::setup(GLfloat src0, GLfloat src1,
-GLfloat dst0, GLfloat dst1,
-bool mirror)
+static void
+brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform *xform,
+GLfloat src0, GLfloat src1,
+GLfloat dst0, GLfloat dst1,
+bool mirror)
 {
float scale = (src1 - src0) / (dst1 - dst0);
if (!mirror) {
@@ -1800,16 +1801,16 @@ brw_blorp_coord_transform_params::setup(GLfloat src0, 
GLfloat src1,
* whereas the behaviour we actually want is "round to nearest",
* so 0.5 provides the necessary correction.
*/
-  multiplier = scale;
-  offset = src0 + (-dst0 + 0.5f) * scale;
+  xform->multiplier = scale;
+  xform->offset = src0 + (-dst0 + 0.5f) * scale;
} else {
   /* When mirroring X we need:
*   src_x - src_x0 = dst_x1 - dst_x - 0.5
* Therefore:
*   src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
*/
-  multiplier = -scale;
-  offset = src0 + (dst1 - 0.5f) * scale;
+  xform->multiplier = -scale;
+  xform->offset = src0 + (dst1 - 0.5f) * scale;
}
 }
 
@@ -2062,8 +2063,10 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
params.wm_push_consts.rect_grid_y1 =
   minify(src_mt->logical_height0, src_level) * wm_prog_key.y_scale - 1.0f;
 
-   params.wm_push_consts.x_transform.setup(src_x0, src_x1, dst_x0, dst_x1, 
mirror_x);
-   params.wm_push_consts.y_transform.setup(src_y0, src_y1, dst_y0, dst_y1, 
mirror_y);
+   brw_blorp_setup_coord_transform(¶ms.wm_push_consts.x_transform,
+   src_x0, src_x1, dst_x0, dst_x1, mirror_x);
+   brw_blorp_setup_coord_transform(¶ms.wm_push_consts.y_transform,
+   src_y0, src_y1, dst_y0, dst_y1, mirror_y);
 
params.wm_push_consts.src_z =
   params.src.mt->target == GL_TEXTURE_3D ? params.src.layer : 0;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 12/13] i965/blorp: Make state setup C-safe

[Jason Ekstrand]

Previously they (very rarely) used C++isms that prevented them from being
compiled as C.  As of this commit, they can be compiled as either C or C++.
---
 src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 ++--
 src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 +-
 src/mesa/drivers/dri/i965/gen8_blorp.cpp | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 120ec1d..dabe8b5 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -742,7 +742,7 @@ gen6_blorp_emit_constant_ps(struct brw_context *brw,
/* Make sure the push constants fill an exact integer number of
 * registers.
 */
-   assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
+   assert(sizeof(struct brw_blorp_wm_push_constants) % 32 == 0);
 
/* There must be at least one register worth of push constant data. */
assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
@@ -971,7 +971,7 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 }
 
 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
-void
+static void
 gen6_blorp_emit_viewport_state(struct brw_context *brw,
   const struct brw_blorp_params *params)
 {
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 36d90b7..0dcdcf6 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -598,7 +598,7 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw,
/* Make sure the push constants fill an exact integer number of
 * registers.
 */
-   assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
+   assert(sizeof(struct brw_blorp_wm_push_constants) % 32 == 0);
 
/* There must be at least one register worth of push constant data. */
assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen8_blorp.cpp
index 8e3eadc..8da51e1 100644
--- a/src/mesa/drivers/dri/i965/gen8_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.cpp
@@ -599,7 +599,7 @@ gen8_blorp_emit_surface_states(struct brw_context *brw,
 true /* is_render_target */);
if (params->src.mt) {
   const struct brw_blorp_surface_info *surface = ¶ms->src;
-  intel_mipmap_tree *mt = surface->mt;
+  struct intel_mipmap_tree *mt = surface->mt;
 
   /* Textures are always sampled as 2D. */
   const bool is_cube = mt->target == GL_TEXTURE_CUBE_MAP_ARRAY ||
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 10/13] i965/blorp: Make all of brw_blorp.h accessable to C

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.h | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index e9db063..3953955 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -57,9 +57,6 @@ void
 brw_blorp_resolve_color(struct brw_context *brw,
 struct intel_mipmap_tree *mt);
 
-#ifdef __cplusplus
-} /* end extern "C" */
-
 /**
  * Binding table indices used by BLORP.
  */
@@ -203,8 +200,8 @@ struct brw_blorp_wm_push_constants
 };
 
 /* Every 32 bytes of push constant data constitutes one GEN register. */
-const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
-   sizeof(brw_blorp_wm_push_constants) / 32;
+static const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
+   sizeof(struct brw_blorp_wm_push_constants) / 32;
 
 struct brw_blorp_prog_data
 {
@@ -277,13 +274,13 @@ struct brw_blorp_blit_prog_key
/* MSAA layout that has been configured in the surface state for texturing
 * from.
 */
-   intel_msaa_layout tex_layout;
+   enum intel_msaa_layout tex_layout;
 
/* Actual number of samples per pixel in the source image. */
unsigned src_samples;
 
/* Actual MSAA layout used by the source image. */
-   intel_msaa_layout src_layout;
+   enum intel_msaa_layout src_layout;
 
/* Number of samples per pixel that have been configured in the render
 * target.
@@ -291,13 +288,13 @@ struct brw_blorp_blit_prog_key
unsigned rt_samples;
 
/* MSAA layout that has been configured in the render target. */
-   intel_msaa_layout rt_layout;
+   enum intel_msaa_layout rt_layout;
 
/* Actual number of samples per pixel in the destination image. */
unsigned dst_samples;
 
/* Actual MSAA layout used by the destination image. */
-   intel_msaa_layout dst_layout;
+   enum intel_msaa_layout dst_layout;
 
/* Type of the data to be read from the texture (one of
 * BRW_REGISTER_TYPE_{UD,D,F}).
@@ -445,4 +442,6 @@ gen7_blorp_emit_primitive(struct brw_context *brw,
 
 /** \} */
 
+#ifdef __cplusplus
+} /* end extern "C" */
 #endif /* __cplusplus */
-- 
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[Mesa-dev] [PATCH 03/13] i965/blorp: Remove the clear params classes

[Jason Ekstrand]

They didn't really add anything other than a key and extra layers of
function calls.  This commit just inlines the extra functions and gets rid
of the extra classes.
---
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 224 ++
 1 file changed, 87 insertions(+), 137 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index c7e57bc..b16102c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -44,43 +44,6 @@ struct brw_blorp_const_color_prog_key
bool pad[3];
 };
 
-/**
- * Parameters for a blorp operation where the fragment shader outputs a
- * constant color.  This is used for both fast color clears and color
- * resolves.
- */
-class brw_blorp_const_color_params : public brw_blorp_params
-{
-public:
-   brw_blorp_const_color_prog_key wm_prog_key;
-};
-
-class brw_blorp_clear_params : public brw_blorp_const_color_params
-{
-public:
-   brw_blorp_clear_params(struct brw_context *brw,
-  struct gl_framebuffer *fb,
-  struct gl_renderbuffer *rb,
-  GLubyte *color_mask,
-  bool partial_clear,
-  bool encode_srgb,
-  unsigned layer);
-};
-
-
-/**
- * Parameters for a blorp operation that performs a "render target resolve".
- * This is used to resolve pending fast clear pixels before a color buffer is
- * used for texturing, ReadPixels, or scanout.
- */
-class brw_blorp_rt_resolve_params : public brw_blorp_const_color_params
-{
-public:
-   brw_blorp_rt_resolve_params(struct brw_context *brw,
-   struct intel_mipmap_tree *mt);
-};
-
-
 class brw_blorp_const_color_program
 {
 public:
@@ -151,102 +114,6 @@ brw_blorp_params_get_clear_kernel(struct brw_context *brw,
}
 }
 
-brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
-   struct gl_framebuffer *fb,
-   struct gl_renderbuffer *rb,
-   GLubyte *color_mask,
-   bool partial_clear,
-   bool encode_srgb,
-   unsigned layer)
-{
-   struct gl_context *ctx = &brw->ctx;
-   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-   mesa_format format = irb->mt->format;
-
-   if (!encode_srgb && _mesa_get_format_color_encoding(format) == GL_SRGB)
-  format = _mesa_get_srgb_format_linear(format);
-
-   dst.set(brw, irb->mt, irb->mt_level, layer, format, true);
-
-   /* Override the surface format according to the context's sRGB rules. */
-   dst.brw_surfaceformat = brw->render_target_format[format];
-
-   x0 = fb->_Xmin;
-   x1 = fb->_Xmax;
-   if (rb->Name != 0) {
-  y0 = fb->_Ymin;
-  y1 = fb->_Ymax;
-   } else {
-  y0 = rb->Height - fb->_Ymax;
-  y1 = rb->Height - fb->_Ymin;
-   }
-
-   memcpy(&wm_push_consts.dst_x0, ctx->Color.ClearColor.f, sizeof(float) * 4);
-
-   memset(&wm_prog_key, 0, sizeof(wm_prog_key));
-
-   wm_prog_key.use_simd16_replicated_data = true;
-
-   /* From the SNB PRM (Vol4_Part1):
-*
-* "Replicated data (Message Type = 111) is only supported when
-*  accessing tiled memory.  Using this Message Type to access linear
-*  (untiled) memory is UNDEFINED."
-*/
-   if (irb->mt->tiling == I915_TILING_NONE)
-  wm_prog_key.use_simd16_replicated_data = false;
-
-   /* Constant color writes ignore everyting in blend and color calculator
-* state.  This is not documented.
-*/
-   for (int i = 0; i < 4; i++) {
-  if (_mesa_format_has_color_component(irb->mt->format, i) &&
-  !color_mask[i]) {
- color_write_disable[i] = true;
- wm_prog_key.use_simd16_replicated_data = false;
-  }
-   }
-
-   if (irb->mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS &&
-   !partial_clear && wm_prog_key.use_simd16_replicated_data &&
-   brw_is_color_fast_clear_compatible(brw, irb->mt,
-  &ctx->Color.ClearColor)) {
-  memset(&wm_push_consts, 0xff, 4*sizeof(float));
-  fast_clear_op = GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
-
-  brw_get_fast_clear_rect(brw, fb, irb->mt, &x0, &y0, &x1, &y1);
-   } else {
-  brw_meta_get_buffer_rect(fb, &x0, &y0, &x1, &y1);
-   }
-
-   brw_blorp_params_get_clear_kernel(brw, this, &wm_prog_key);
-}
-
-
-brw_blorp_rt_resolve_params::brw_blorp_rt_resolve_params(
-  struct brw_context *brw,
-  struct intel_mipmap_tree *mt)
-{
-   const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
-
-   dst.set(brw, mt, 0 /* level */, 0 /* layer */, format, true);
-
-   brw_get_resolve_rect(brw, mt, &x0, &y0, &x1, &y1);
-
-   fast_clear_op = GEN7_PS_RENDER_TARGET_RESOLVE_ENA

[Mesa-dev] [PATCH 02/13] i965/blorp: Remove the arguments to brw_blorp_params()

[Jason Ekstrand]

No one was using anything other than the defaults.
---
 src/mesa/drivers/dri/i965/brw_blorp.cpp | 10 --
 src/mesa/drivers/dri/i965/brw_blorp.h   |  4 +---
 2 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 9dbbd83..0fa1734 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -155,9 +155,7 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t 
*tile_x,
 }
 
 
-brw_blorp_params::brw_blorp_params(unsigned num_varyings,
-   unsigned num_draw_buffers,
-   unsigned num_layers)
+brw_blorp_params::brw_blorp_params()
: x0(0),
  y0(0),
  x1(0),
@@ -165,9 +163,9 @@ brw_blorp_params::brw_blorp_params(unsigned num_varyings,
  depth_format(0),
  hiz_op(GEN6_HIZ_OP_NONE),
  fast_clear_op(0),
- num_varyings(num_varyings),
- num_draw_buffers(num_draw_buffers),
- num_layers(num_layers),
+ num_varyings(0),
+ num_draw_buffers(1),
+ num_layers(1),
  wm_prog_kernel(BRW_BLORP_NO_WM_PROG),
  wm_prog_data(NULL)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 4981afd..64f197e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -234,9 +234,7 @@ struct brw_blorp_prog_data
 class brw_blorp_params
 {
 public:
-   brw_blorp_params(unsigned num_varyings = 0,
-unsigned num_draw_buffers = 1,
-unsigned num_layers = 1);
+   brw_blorp_params();
 
uint32_t x0;
uint32_t y0;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 07/13] i965/blorp: Turn blorp_surface_info into a C-style struct

[Jason Ekstrand]

This commit is mostly mechanical except that it changes where we set the
swizzle.  Previously, the blorp_surface_info constructor defaulted the
swizzle to SWIZZLE_XYZW.  Now, we memset to zero and fill out the swizzle
when we setup the rest of the struct.
---
 src/mesa/drivers/dri/i965/brw_blorp.cpp   | 77 ---
 src/mesa/drivers/dri/i965/brw_blorp.h | 32 +--
 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  |  6 ++-
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  6 ++-
 src/mesa/drivers/dri/i965/gen6_blorp.cpp  |  4 +-
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  |  6 +--
 src/mesa/drivers/dri/i965/gen8_blorp.cpp  |  7 +--
 7 files changed, 69 insertions(+), 69 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index e501818..cd37922 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -30,22 +30,9 @@
 
 #define FILE_DEBUG_FLAG DEBUG_BLORP
 
-brw_blorp_surface_info::brw_blorp_surface_info()
-   : mt(NULL),
- level(0),
- layer(0),
- width(0),
- height(0),
- x_offset(0),
- y_offset(0),
- map_stencil_as_y_tiled(false),
- num_samples(0),
- swizzle(SWIZZLE_XYZW)
-{
-}
-
 void
-brw_blorp_surface_info::set(struct brw_context *brw,
+brw_blorp_surface_info_init(struct brw_context *brw,
+struct brw_blorp_surface_info *info,
 struct intel_mipmap_tree *mt,
 unsigned int level, unsigned int layer,
 mesa_format format, bool is_render_target)
@@ -61,18 +48,20 @@ brw_blorp_surface_info::set(struct brw_context *brw,
 
intel_miptree_check_level_layer(mt, level, layer);
 
-   this->mt = mt;
-   this->level = level;
-   this->layer = layer;
-   this->width = minify(mt->physical_width0, level - mt->first_level);
-   this->height = minify(mt->physical_height0, level - mt->first_level);
+   info->mt = mt;
+   info->level = level;
+   info->layer = layer;
+   info->width = minify(mt->physical_width0, level - mt->first_level);
+   info->height = minify(mt->physical_height0, level - mt->first_level);
 
-   intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
+   intel_miptree_get_image_offset(mt, level, layer,
+  &info->x_offset, &info->y_offset);
 
-   this->num_samples = mt->num_samples;
-   this->array_layout = mt->array_layout;
-   this->map_stencil_as_y_tiled = false;
-   this->msaa_layout = mt->msaa_layout;
+   info->num_samples = mt->num_samples;
+   info->array_layout = mt->array_layout;
+   info->map_stencil_as_y_tiled = false;
+   info->msaa_layout = mt->msaa_layout;
+   info->swizzle = SWIZZLE_XYZW;
 
if (format == MESA_FORMAT_NONE)
   format = mt->format;
@@ -83,8 +72,8 @@ brw_blorp_surface_info::set(struct brw_context *brw,
* up for W tiling, so we'll need to use Y tiling and have the WM
* program swizzle the coordinates.
*/
-  this->map_stencil_as_y_tiled = true;
-  this->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
+  info->map_stencil_as_y_tiled = true;
+  info->brw_surfaceformat = brw->gen >= 8 ? BRW_SURFACEFORMAT_R8_UINT :
 BRW_SURFACEFORMAT_R8_UNORM;
   break;
case MESA_FORMAT_Z24_UNORM_X8_UINT:
@@ -98,20 +87,20 @@ brw_blorp_surface_info::set(struct brw_context *brw,
* pattern as long as we copy the right amount of data, so just map it
* as 8-bit BGRA.
*/
-  this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
+  info->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
   break;
case MESA_FORMAT_Z_FLOAT32:
-  this->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
+  info->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT;
   break;
case MESA_FORMAT_Z_UNORM16:
-  this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
+  info->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM;
   break;
default: {
   if (is_render_target) {
  assert(brw->format_supported_as_render_target[format]);
- this->brw_surfaceformat = brw->render_target_format[format];
+ info->brw_surfaceformat = brw->render_target_format[format];
   } else {
- this->brw_surfaceformat = brw_format_for_mesa_format(format);
+ info->brw_surfaceformat = brw_format_for_mesa_format(format);
   }
   break;
}
@@ -127,21 +116,21 @@ brw_blorp_surface_info::set(struct brw_context *brw,
  * directly from the adjusted offsets.
  */
 uint32_t
-brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x,
- uint32_t *tile_y) const
+brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info,
+   uint32_t *tile_x, uint32_t *tile_y)
 {
uint32_t mask_x, mask_y;
 
-   intel_ge

Re: [Mesa-dev] [PATCH] anv_device: Set the compressed texture feature flags correctly

[Kenneth Graunke]

On Monday, April 18, 2016 2:33:38 PM PDT Nanley Chery wrote:
> From: Nanley Chery 
> 
> Sampling from an ETC2 texture is supported from Gen8 onwards.
> While ASTC_LDR is supported on Gen9, the logic to handle such
> formats has not yet been implemented in the driver.
> 
> Fixes dEQP-VK.api.info.format_properties.compressed_formats.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94896
> Signed-off-by: Nanley Chery 
> ---
>  src/intel/vulkan/anv_device.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index e477fe1..5433dd3 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -380,8 +380,8 @@ void anv_GetPhysicalDeviceFeatures(
>.alphaToOne   = true,
>.multiViewport= true,
>.samplerAnisotropy= false, /* FINISHME */
> -  .textureCompressionETC2   = true,
> -  .textureCompressionASTC_LDR   = true,
> +  .textureCompressionETC2   = pdevice->info->gen >= 8,
> +  .textureCompressionASTC_LDR   = false, /* FINISHME */
>.textureCompressionBC = true,
>.occlusionQueryPrecise= true,
>.pipelineStatisticsQuery  = false,
> 

ETC2 is also supported on Baytrail.  Otherwise, looks good to me.


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Re: [Mesa-dev] [PATCH 00/11] update swr rasterizer

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak  On Apr 14, 2016, at 2:53 PM, Tim Rowley  wrote:
> 
> Another batch of updates to the swr rasterizer.  No huge new features,
> but should fix at least one of the coverity flagged issues.
> 
> Tim Rowley (11):
>  swr: [rasterizer core] Use CS spill/fill size in core
>  swr: [rasterizer fetch] Add support for fetching non-uniform component
>formats
>  swr: [rasterizer core] Fix thread binding for 32-bit windows
>  swr: [rasterizer core] Fix global arena allocator bug
>  swr: [rasterizer core] Arena: make most allocated blocks the same size
>  swr: [rasterizer core] TemplateArgUnroller
>  swr: [rasterizer] Interpolation utility functions
>  swr: [rasterizer scripts] Knob scripts tweaks
>  swr: [rasterizer] Small cleanups
>  swr: [rasterizer core] CompleteDrawContext changes for gcc
>  swr: [rasterizer memory] Constify load tiles
> 
> .../drivers/swr/rasterizer/common/simdintrin.h |  51 +-
> src/gallium/drivers/swr/rasterizer/core/api.cpp|  45 +
> src/gallium/drivers/swr/rasterizer/core/api.h  |   6 +-
> src/gallium/drivers/swr/rasterizer/core/arena.h| 146 ++--
> .../drivers/swr/rasterizer/core/backend.cpp|   6 +-
> src/gallium/drivers/swr/rasterizer/core/context.h  |   1 +
> .../drivers/swr/rasterizer/core/frontend.cpp   | 123 +++--
> src/gallium/drivers/swr/rasterizer/core/frontend.h |  24 ++-
> src/gallium/drivers/swr/rasterizer/core/pa.h   |   6 +-
> src/gallium/drivers/swr/rasterizer/core/state.h|   2 -
> .../drivers/swr/rasterizer/core/threads.cpp|  31 +++-
> src/gallium/drivers/swr/rasterizer/core/utils.cpp  |  31 ++--
> src/gallium/drivers/swr/rasterizer/core/utils.h|  34 +++-
> .../drivers/swr/rasterizer/jitter/JitManager.cpp   |   6 -
> .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 190 -
> .../drivers/swr/rasterizer/jitter/jit_api.h|   3 +
> .../drivers/swr/rasterizer/memory/LoadTile.cpp |  12 +-
> .../drivers/swr/rasterizer/memory/StoreTile.cpp|   1 -
> .../drivers/swr/rasterizer/scripts/knob_defs.py|   4 +-
> .../rasterizer/scripts/templates/knobs.template|  25 ++-
> src/gallium/drivers/swr/swr_memory.h   |   2 +-
> 21 files changed, 544 insertions(+), 205 deletions(-)
> 
> -- 
> 1.9.1
> 
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Re: [Mesa-dev] [PATCH 1/4] gbm: Add Android build support

[Emil Velikov]

Hi Rob,

On 22 April 2016 at 16:50, Rob Herring  wrote:

> --- /dev/null
> +++ b/src/gbm/Android.mk

> +LOCAL_EXPORT_C_INCLUDE_DIRS := \
> +   $(LOCAL_PATH)/main
> +
You don't need this.

> +LOCAL_C_INCLUDES := \
> +   $(LOCAL_PATH)/main
> +
> +ifeq ($(MESA_LOLLIPOP_BUILD),true)
> +LOCAL_CFLAGS_32 := 
> -DDEFAULT_DRIVER_DIR=\"/system/lib/$(MESA_DRI_MODULE_REL_PATH)\"
> +LOCAL_CFLAGS_64 := 
> -DDEFAULT_DRIVER_DIR=\"/system/lib64/$(MESA_DRI_MODULE_REL_PATH)\"
> +else
> +LOCAL_CFLAGS += 
> -DDEFAULT_DRIVER_DIR=\"/system/lib/$(MESA_DRI_MODULE_REL_PATH)\"
> +endif
> +
Can you factor out the existing copy from src/egl/Android.mk to
$(top)/Android.mk.
The following should work ... I think.

define set-default-driver-dir
   ifeq ($(MESA_LOLLIPOP_BUILD),true)
   LOCAL_CFLAGS_32 :=
-DDEFAULT_DRIVER_DIR=\"/system/lib/$(MESA_DRI_MODULE_REL_PATH)\"
   LOCAL_CFLAGS_64 :=
-DDEFAULT_DRIVER_DIR=\"/system/lib64/$(MESA_DRI_MODULE_REL_PATH)\"
   else
   LOCAL_CFLAGS +=
-DDEFAULT_DRIVER_DIR=\"/system/lib/$(MESA_DRI_MODULE_REL_PATH)\"
  endif

To use it
$(call set-default-driver-dir)

> +LOCAL_SHARED_LIBRARIES := libdrm
> +LOCAL_STATIC_LIBRARIES := libmesa_loader
> +LOCAL_MODULE := libgbm
> +
Nit: Please move these three after LOCAL_SRC_FILES.

> +LOCAL_SRC_FILES := \
> +   $(gbm_core_FILES) \
> +   $(gbm_dri_FILES)
> +
> +include $(MESA_COMMON_MK)
> +include $(BUILD_SHARED_LIBRARY)
> diff --git a/src/gbm/Makefile.am b/src/gbm/Makefile.am
> index 9a584ca..68dc8f2 100644
> --- a/src/gbm/Makefile.am
> +++ b/src/gbm/Makefile.am
> @@ -15,12 +15,7 @@ lib_LTLIBRARIES = libgbm.la

Add following line just after the license. Also please split out
autoconf changes (move the sources list to Makefile.sources) to a
separate patch.

include Makefile.sources


> --- /dev/null
> +++ b/src/gbm/Makefile.sources
> @@ -0,0 +1,12 @@
> +
Nit: Kill off this empty line.


> --- a/src/gbm/backends/dri/gbm_dri.c
> +++ b/src/gbm/backends/dri/gbm_dri.c
> @@ -341,6 +341,15 @@ dri_open_driver(struct gbm_dri_device *dri)
>/* not need continue to loop all paths once the driver is found */
>if (dri->driver != NULL)
>   break;
> +
> +#ifdef ANDROID
> +  snprintf(path, sizeof path, "%.*s/gallium_dri.so", len, p);
> +  dri->driver = dlopen(path, RTLD_NOW | RTLD_GLOBAL);
> +  if (dri->driver == NULL)
> + sprintf("failed to open %s: %s\n", path, dlerror());
> +  else
> + break;
> +#endif

And this should be separate commit. Unless you insist on re-factoring
these dri functions to a common place.

Thanks
Emil
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Re: [Mesa-dev] [PATCH 1/3] configure.ac: search for and set PYTHON3

[Kenneth Graunke]

On Saturday, April 23, 2016 5:34:33 AM PDT Jonathan Gray wrote:
> On Fri, Apr 22, 2016 at 11:09:52AM -0700, Kenneth Graunke wrote:
> > On Saturday, April 23, 2016 1:21:38 AM PDT Jonathan Gray wrote:
> > > src/intel/genxml/gen_pack_header.py requires python3.
> > > 
> > > Signed-off-by: Jonathan Gray 
> > > ---
> > >  configure.ac | 2 ++
> > >  1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/configure.ac b/configure.ac
> > > index 6b00cf9..9459489 100644
> > > --- a/configure.ac
> > > +++ b/configure.ac
> > > @@ -99,6 +99,7 @@ AM_PROG_CC_C_O
> > >  AM_PROG_AS
> > >  AX_CHECK_GNU_MAKE
> > >  AC_CHECK_PROGS([PYTHON2], [python2.7 python2 python])
> > > +AC_CHECK_PROGS([PYTHON3], [python3.4 python3])
> > >  AC_PROG_SED
> > >  AC_PROG_MKDIR_P
> > 
> > Why mention python3.4 explicitly?  Are we trying to check for 3.4+?
> > 
> > My system has /usr/bin/python3 -> /usr/bin/python3.5, FWIW...no 3.4.
> 
> Yes, I realised that after sending it out and added 3.5
> 
> The default python3 version here is python3.4 with python3.5 also
> available.  There are no 'python' or 'python3' symlinks.

Ah, interesting.  Thanks! :)

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH v2] swr: fix clang warnings

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak 
mailto:bruce.chern...@intel.com>>

On Apr 21, 2016, at 11:50 AM, Tim Rowley 
mailto:timothy.o.row...@intel.com>> wrote:

v2: use alternate logic version in swr_check_render_cond
---
src/gallium/drivers/swr/swr_query.cpp | 2 +-
src/gallium/drivers/swr/swr_shader.h  | 8 
2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_query.cpp 
b/src/gallium/drivers/swr/swr_query.cpp
index e4b8b68..76708ba 100644
--- a/src/gallium/drivers/swr/swr_query.cpp
+++ b/src/gallium/drivers/swr/swr_query.cpp
@@ -314,7 +314,7 @@ swr_check_render_cond(struct pipe_context *pipe)
   b = pipe->get_query_result(
  pipe, ctx->render_cond_query, wait, (union pipe_query_result *)&result);
   if (b)
-  return (!result == ctx->render_cond_cond);
+  return ((!result) == ctx->render_cond_cond);
   else
  return TRUE;
}
diff --git a/src/gallium/drivers/swr/swr_shader.h 
b/src/gallium/drivers/swr/swr_shader.h
index 3f79570..11d50c3 100644
--- a/src/gallium/drivers/swr/swr_shader.h
+++ b/src/gallium/drivers/swr/swr_shader.h
@@ -23,10 +23,10 @@

#pragma once

-class swr_vertex_shader;
-class swr_fragment_shader;
-class swr_jit_fs_key;
-class swr_jit_vs_key;
+struct swr_vertex_shader;
+struct swr_fragment_shader;
+struct swr_jit_fs_key;
+struct swr_jit_vs_key;

PFN_VERTEX_FUNC
swr_compile_vs(struct swr_context *ctx, swr_jit_vs_key &key);
--
1.9.1

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[Mesa-dev] [PATCH 6/9] radeonsi: only decompress the required ZS planes from si_blit

[Nicolai Hähnle]

From: Nicolai Hähnle 

This happens to "fix" a rendering bug in KotOR2, because it avoids a still
not quite understood bug with MSAA fast stencil clear decompress. For the
stencil clear bug, I have sent a piglit test 
(arb_texture_multisample-stencil-clear).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93767
---
 src/gallium/drivers/radeonsi/si_blit.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index e044538..39ef98e 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -596,17 +596,17 @@ static void si_clear_depth_stencil(struct pipe_context 
*ctx,
  * rendering. */
 static void si_decompress_subresource(struct pipe_context *ctx,
  struct pipe_resource *tex,
- unsigned level,
+ unsigned planes, unsigned level,
  unsigned first_layer, unsigned last_layer)
 {
struct si_context *sctx = (struct si_context *)ctx;
struct r600_texture *rtex = (struct r600_texture*)tex;
 
if (rtex->is_depth && !rtex->is_flushing_texture) {
-   unsigned planes = PIPE_MASK_Z;
+   planes &= PIPE_MASK_Z | PIPE_MASK_S;
 
-   if (rtex->surface.flags & RADEON_SURF_SBUFFER)
-   planes |= PIPE_MASK_S;
+   if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
+   planes &= ~PIPE_MASK_S;
 
si_blit_decompress_zs_in_place(sctx, rtex, planes,
   level, level,
@@ -652,7 +652,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
 
/* The driver doesn't decompress resources automatically while
 * u_blitter is rendering. */
-   si_decompress_subresource(ctx, src, src_level,
+   si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
  src_box->z, src_box->z + src_box->depth - 1);
 
dst_width = u_minify(dst->width0, dst_level);
@@ -868,7 +868,8 @@ static void si_blit(struct pipe_context *ctx,
 
/* The driver doesn't decompress resources automatically while
 * u_blitter is rendering. */
-   si_decompress_subresource(ctx, info->src.resource, info->src.level,
+   si_decompress_subresource(ctx, info->src.resource, info->mask,
+ info->src.level,
  info->src.box.z,
  info->src.box.z + info->src.box.depth - 1);
 
-- 
2.5.0

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[Mesa-dev] [PATCH 2/9] radeonsi: fix brace style

[Nicolai Hähnle]

From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_blit.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 7b028c1..2b00da9 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -403,11 +403,13 @@ static void si_decompress_textures(struct si_context 
*sctx, int shader_start,
}
 }
 
-void si_decompress_graphics_textures(struct si_context *sctx) {
+void si_decompress_graphics_textures(struct si_context *sctx)
+{
si_decompress_textures(sctx, 0, SI_NUM_GRAPHICS_SHADERS);
 }
 
-void si_decompress_compute_textures(struct si_context *sctx) {
+void si_decompress_compute_textures(struct si_context *sctx)
+{
si_decompress_textures(sctx, SI_NUM_GRAPHICS_SHADERS, SI_NUM_SHADERS);
 }
 
-- 
2.5.0

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[Mesa-dev] [PATCH 7/9] radeonsi: si_blit_decompress_depth is only used for staging

[Nicolai Hähnle]

From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_blit.c | 26 +-
 1 file changed, 5 insertions(+), 21 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 39ef98e..09f3207 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -108,18 +108,13 @@ static void si_blit_decompress_depth(struct pipe_context 
*ctx,
 unsigned first_sample, unsigned 
last_sample)
 {
struct si_context *sctx = (struct si_context *)ctx;
-   unsigned layer, level, sample, checked_last_layer, max_layer, 
max_sample;
+   unsigned layer, level, sample, checked_last_layer, max_layer;
float depth = 1.0f;
const struct util_format_description *desc;
-   struct r600_texture *flushed_depth_texture = staging ?
-   staging : texture->flushed_depth_texture;
 
-   if (!staging && !texture->dirty_level_mask)
-   return;
-
-   max_sample = u_max_sample(&texture->resource.b.b);
+   assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
 
-   desc = 
util_format_description(flushed_depth_texture->resource.b.b.format);
+   desc = util_format_description(staging->resource.b.b.format);
 
if (util_format_has_depth(desc))
sctx->dbcb_depth_copy_enabled = true;
@@ -129,9 +124,6 @@ static void si_blit_decompress_depth(struct pipe_context 
*ctx,
assert(sctx->dbcb_depth_copy_enabled || 
sctx->dbcb_stencil_copy_enabled);
 
for (level = first_level; level <= last_level; level++) {
-   if (!staging && !(texture->dirty_level_mask & (1 << level)))
-   continue;
-
/* The smaller the mipmap level, the less layers there are
 * as far as 3D textures are concerned. */
max_layer = util_max_layer(&texture->resource.b.b, level);
@@ -151,9 +143,9 @@ static void si_blit_decompress_depth(struct pipe_context 
*ctx,
 
zsurf = ctx->create_surface(ctx, 
&texture->resource.b.b, &surf_tmpl);
 
-   surf_tmpl.format = 
flushed_depth_texture->resource.b.b.format;
+   surf_tmpl.format = staging->resource.b.b.format;
cbsurf = ctx->create_surface(ctx,
-   (struct 
pipe_resource*)flushed_depth_texture, &surf_tmpl);
+   (struct pipe_resource*)staging, 
&surf_tmpl);
 
si_blitter_begin(ctx, SI_DECOMPRESS);

util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
@@ -164,14 +156,6 @@ static void si_blit_decompress_depth(struct pipe_context 
*ctx,
pipe_surface_reference(&cbsurf, NULL);
}
}
-
-   /* The texture will always be dirty if some layers aren't 
flushed.
-* I don't think this case can occur though. */
-   if (!staging &&
-   first_layer == 0 && last_layer == max_layer &&
-   first_sample == 0 && last_sample == max_sample) {
-   texture->dirty_level_mask &= ~(1 << level);
-   }
}
 
sctx->dbcb_depth_copy_enabled = false;
-- 
2.5.0

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[Mesa-dev] [PATCH 4/9] radeonsi: early out of si_blit_decompress_depth_in_place based on dirty mask

[Nicolai Hähnle]

From: Nicolai Hähnle 

Avoid dirtying the db_render_state atom when possible.
---
 src/gallium/drivers/radeonsi/si_blit.c | 20 ++--
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 6db73f7..5882f7d 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -186,23 +186,31 @@ static void si_blit_decompress_depth_in_place(struct 
si_context *sctx,
   unsigned first_layer, unsigned 
last_layer)
 {
struct pipe_surface *zsurf, surf_tmpl = {{0}};
-   unsigned layer, max_layer, checked_last_layer, level;
+   unsigned layer, max_layer, checked_last_layer;
unsigned *dirty_level_mask;
+   unsigned level_mask =
+   u_bit_consecutive(first_level, last_level - first_level + 1);
 
if (is_stencil_sampler) {
-   sctx->db_flush_stencil_inplace = true;
dirty_level_mask = &texture->stencil_dirty_level_mask;
} else {
-   sctx->db_flush_depth_inplace = true;
dirty_level_mask = &texture->dirty_level_mask;
}
+
+   level_mask &= *dirty_level_mask;
+   if (!level_mask)
+   return;
+
+   if (is_stencil_sampler)
+   sctx->db_flush_stencil_inplace = true;
+   else
+   sctx->db_flush_depth_inplace = true;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
 
surf_tmpl.format = texture->resource.b.b.format;
 
-   for (level = first_level; level <= last_level; level++) {
-   if (!(*dirty_level_mask & (1 << level)))
-   continue;
+   while (level_mask) {
+   unsigned level = u_bit_scan(&level_mask);
 
surf_tmpl.u.tex.level = level;
 
-- 
2.5.0

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[Mesa-dev] [PATCH 8/9] radeonsi: use level mask for early out in si_blit_decompress_color

[Nicolai Hähnle]

From: Nicolai Hähnle 

Mostly for consistency with the other decompress functions, but note that
in the non-DCC decompress case, the function can now early-out in slightly
more (albeit probably rare) cases.
---
 src/gallium/drivers/radeonsi/si_blit.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 09f3207..32f953d 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -309,17 +309,19 @@ static void si_blit_decompress_color(struct pipe_context 
*ctx,
bool need_dcc_decompress)
 {
struct si_context *sctx = (struct si_context *)ctx;
-   unsigned layer, level, checked_last_layer, max_layer;
+   unsigned layer, checked_last_layer, max_layer;
+   unsigned level_mask =
+   u_bit_consecutive(first_level, last_level - first_level + 1);
 
-   if (!rtex->dirty_level_mask && !need_dcc_decompress)
+   if (!need_dcc_decompress)
+   level_mask &= rtex->dirty_level_mask;
+   if (!level_mask)
return;
 
-   for (level = first_level; level <= last_level; level++) {
+   while (level_mask) {
+   unsigned level = u_bit_scan(&level_mask);
void* custom_blend;
 
-   if (!(rtex->dirty_level_mask & (1 << level)) && 
!need_dcc_decompress)
-   continue;
-
if (rtex->dcc_offset && need_dcc_decompress) {
custom_blend = sctx->custom_blend_dcc_decompress;
} else if (rtex->fmask.size) {
-- 
2.5.0

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[Mesa-dev] [PATCH 5/9] radeonsi: decompress Z & S planes in one pass

[Nicolai Hähnle]

From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_blit.c | 101 -
 1 file changed, 73 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 5882f7d..e044538 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -179,31 +179,24 @@ static void si_blit_decompress_depth(struct pipe_context 
*ctx,
si_mark_atom_dirty(sctx, &sctx->db_render_state);
 }
 
-static void si_blit_decompress_depth_in_place(struct si_context *sctx,
-  struct r600_texture *texture,
- bool is_stencil_sampler,
-  unsigned first_level, unsigned 
last_level,
-  unsigned first_layer, unsigned 
last_layer)
+/* Helper function for si_blit_decompress_zs_in_place.
+ */
+static void
+si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
+ struct r600_texture *texture,
+ unsigned planes, unsigned level_mask,
+ unsigned first_layer, unsigned last_layer)
 {
struct pipe_surface *zsurf, surf_tmpl = {{0}};
unsigned layer, max_layer, checked_last_layer;
-   unsigned *dirty_level_mask;
-   unsigned level_mask =
-   u_bit_consecutive(first_level, last_level - first_level + 1);
+   unsigned fully_decompressed_mask = 0;
 
-   if (is_stencil_sampler) {
-   dirty_level_mask = &texture->stencil_dirty_level_mask;
-   } else {
-   dirty_level_mask = &texture->dirty_level_mask;
-   }
-
-   level_mask &= *dirty_level_mask;
if (!level_mask)
return;
 
-   if (is_stencil_sampler)
+   if (planes & PIPE_MASK_S)
sctx->db_flush_stencil_inplace = true;
-   else
+   if (planes & PIPE_MASK_Z)
sctx->db_flush_depth_inplace = true;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
 
@@ -237,15 +230,65 @@ static void si_blit_decompress_depth_in_place(struct 
si_context *sctx,
/* The texture will always be dirty if some layers aren't 
flushed.
 * I don't think this case occurs often though. */
if (first_layer == 0 && last_layer == max_layer) {
-   *dirty_level_mask &= ~(1 << level);
+   fully_decompressed_mask |= 1u << level;
}
}
 
+   if (planes & PIPE_MASK_Z)
+   texture->dirty_level_mask &= ~fully_decompressed_mask;
+   if (planes & PIPE_MASK_S)
+   texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
+
sctx->db_flush_depth_inplace = false;
sctx->db_flush_stencil_inplace = false;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
 }
 
+/* Decompress Z and/or S planes in place, depending on mask.
+ */
+static void
+si_blit_decompress_zs_in_place(struct si_context *sctx,
+  struct r600_texture *texture,
+  unsigned planes,
+  unsigned first_level, unsigned last_level,
+  unsigned first_layer, unsigned last_layer)
+{
+   unsigned level_mask =
+   u_bit_consecutive(first_level, last_level - first_level + 1);
+   unsigned cur_level_mask;
+
+   /* First, do combined Z & S decompresses for levels that need it. */
+   if (planes == (PIPE_MASK_Z | PIPE_MASK_S)) {
+   cur_level_mask =
+   level_mask &
+   texture->dirty_level_mask &
+   texture->stencil_dirty_level_mask;
+   si_blit_decompress_zs_planes_in_place(
+   sctx, texture, PIPE_MASK_Z | PIPE_MASK_S,
+   cur_level_mask,
+   first_layer, last_layer);
+   level_mask &= ~cur_level_mask;
+   }
+
+   /* Now do separate Z and S decompresses. */
+   if (planes & PIPE_MASK_Z) {
+   cur_level_mask = level_mask & texture->dirty_level_mask;
+   si_blit_decompress_zs_planes_in_place(
+   sctx, texture, PIPE_MASK_Z,
+   cur_level_mask,
+   first_layer, last_layer);
+   level_mask &= ~cur_level_mask;
+   }
+
+   if (planes & PIPE_MASK_S) {
+   cur_level_mask = level_mask & texture->stencil_dirty_level_mask;
+   si_blit_decompress_zs_planes_in_place(
+   sctx, texture, PIPE_MASK_S,
+   cur_level_mask,
+   first_layer, last_layer);
+   }
+}
+
 static void
 si_flush_depth_textures(struct si_context

[Mesa-dev] [PATCH 9/9] radeonsi: move blend choice out of loop in si_blit_decompress_color

[Nicolai Hähnle]

From: Nicolai Hähnle 

It does not depend on the level or layer.
---
 src/gallium/drivers/radeonsi/si_blit.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 32f953d..b87275d 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -309,6 +309,7 @@ static void si_blit_decompress_color(struct pipe_context 
*ctx,
bool need_dcc_decompress)
 {
struct si_context *sctx = (struct si_context *)ctx;
+   void* custom_blend;
unsigned layer, checked_last_layer, max_layer;
unsigned level_mask =
u_bit_consecutive(first_level, last_level - first_level + 1);
@@ -318,17 +319,16 @@ static void si_blit_decompress_color(struct pipe_context 
*ctx,
if (!level_mask)
return;
 
+   if (rtex->dcc_offset && need_dcc_decompress) {
+   custom_blend = sctx->custom_blend_dcc_decompress;
+   } else if (rtex->fmask.size) {
+   custom_blend = sctx->custom_blend_decompress;
+   } else {
+   custom_blend = sctx->custom_blend_fastclear;
+   }
+
while (level_mask) {
unsigned level = u_bit_scan(&level_mask);
-   void* custom_blend;
-
-   if (rtex->dcc_offset && need_dcc_decompress) {
-   custom_blend = sctx->custom_blend_dcc_decompress;
-   } else if (rtex->fmask.size) {
-   custom_blend = sctx->custom_blend_decompress;
-   } else {
-   custom_blend = sctx->custom_blend_fastclear;
-   }
 
/* The smaller the mipmap level, the less layers there are
 * as far as 3D textures are concerned. */
-- 
2.5.0

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[Mesa-dev] [PATCH 3/9] radeonsi: use MIN2 instead of expanded ?: operator

[Nicolai Hähnle]

From: Nicolai Hähnle 

---
 src/gallium/drivers/radeonsi/si_blit.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 2b00da9..6db73f7 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -135,7 +135,7 @@ static void si_blit_decompress_depth(struct pipe_context 
*ctx,
/* The smaller the mipmap level, the less layers there are
 * as far as 3D textures are concerned. */
max_layer = util_max_layer(&texture->resource.b.b, level);
-   checked_last_layer = last_layer < max_layer ? last_layer : 
max_layer;
+   checked_last_layer = MIN2(last_layer, max_layer);
 
for (layer = first_layer; layer <= checked_last_layer; layer++) 
{
for (sample = first_sample; sample <= last_sample; 
sample++) {
@@ -209,7 +209,7 @@ static void si_blit_decompress_depth_in_place(struct 
si_context *sctx,
/* The smaller the mipmap level, the less layers there are
 * as far as 3D textures are concerned. */
max_layer = util_max_layer(&texture->resource.b.b, level);
-   checked_last_layer = last_layer < max_layer ? last_layer : 
max_layer;
+   checked_last_layer = MIN2(last_layer, max_layer);
 
for (layer = first_layer; layer <= checked_last_layer; layer++) 
{
surf_tmpl.u.tex.first_layer = layer;
@@ -295,7 +295,7 @@ static void si_blit_decompress_color(struct pipe_context 
*ctx,
/* The smaller the mipmap level, the less layers there are
 * as far as 3D textures are concerned. */
max_layer = util_max_layer(&rtex->resource.b.b, level);
-   checked_last_layer = last_layer < max_layer ? last_layer : 
max_layer;
+   checked_last_layer = MIN2(last_layer, max_layer);
 
for (layer = first_layer; layer <= checked_last_layer; layer++) 
{
struct pipe_surface *cbsurf, surf_tmpl;
-- 
2.5.0

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[Mesa-dev] [PATCH 1/9] gallium/util: add u_bit_consecutive for generating a consecutive range of bits

[Nicolai Hähnle]

From: Nicolai Hähnle 

There are some undefined behavior subtleties, so having a function to match
the u_bit_scan_consecutive_range makes sense.
---
 src/gallium/auxiliary/util/u_math.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/gallium/auxiliary/util/u_math.h 
b/src/gallium/auxiliary/util/u_math.h
index 10f158b..be6b5a3 100644
--- a/src/gallium/auxiliary/util/u_math.h
+++ b/src/gallium/auxiliary/util/u_math.h
@@ -543,6 +543,18 @@ u_bit_scan_consecutive_range64(uint64_t *mask, int *start, 
int *count)
*mask &= ~(((1llu << *count) - 1) << *start);
 }
 
+/* Returns a bitfield in which the first count bits starting at start are
+ * set.
+ */
+static inline unsigned
+u_bit_consecutive(unsigned start, unsigned count)
+{
+   assert(start + count <= 32);
+   if (count == 32)
+  return ~0;
+   return ((1u << count) - 1) << start;
+}
+
 /**
  * Return float bits.
  */
-- 
2.5.0

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[Mesa-dev] [PATCH 0/9] radeonsi: decompression cleanups and ZS optimization

[Nicolai Hähnle]

Hi,

this series contains a bunch of minor cleanups to the various decompression
routines. The biggest functional change is that we decompress Z & S in-place
simultaneously now when asked for decompressing both, while at the same time
being slightly more precise about which of the two we decompress in the first
place: if a blit only asks for Z or only S, there's no need to decompress both.
  
Note that this doesn't cover all cases - in particular, when a ZS texture is
bound both with a depth and with a stencil sampler, we still decompress them
individually, since this is difficult to detect.

I started out wanting to also move the si_blitter_begin/_end calls out of
loops to reduce potential state churn, but the blitter isn't really designed
for that, and many drivers rely on the current blitter behavior.

I guess one could add a "manual" mode to the blitter, where we call
util_blitter_begin/_end functions and explicitly restore all state in
si_blitter_end. This could be implemented in a way that drivers can
"opt in" to this new behavior, where the caller is responsible for
restoring state. What do people think about that?

Thanks,
Nicolai  
--
 src/gallium/auxiliary/util/u_math.h|  12 ++
 src/gallium/drivers/radeonsi/si_blit.c | 184 ++-
 2 files changed, 125 insertions(+), 71 deletions(-)

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[Mesa-dev] [PATCH 1/2] radeonsi: expclear must be disabled on first Z/S clear

[Nicolai Hähnle]

From: Nicolai Hähnle 

The documentation and the HW team say so.
---
 src/gallium/drivers/radeonsi/si_blit.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index b87275d..6fa5b97 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -497,7 +497,7 @@ static void si_clear(struct pipe_context *ctx, unsigned 
buffers,
if (buffers & PIPE_CLEAR_DEPTH) {
/* Need to disable EXPCLEAR temporarily if clearing
 * to a new value. */
-   if (zstex->depth_cleared && zstex->depth_clear_value != 
depth) {
+   if (!zstex->depth_cleared || zstex->depth_clear_value 
!= depth) {
sctx->db_depth_disable_expclear = true;
}
 
@@ -513,7 +513,7 @@ static void si_clear(struct pipe_context *ctx, unsigned 
buffers,
 
/* Need to disable EXPCLEAR temporarily if clearing
 * to a new value. */
-   if (zstex->stencil_cleared && 
zstex->stencil_clear_value != stencil) {
+   if (!zstex->stencil_cleared || 
zstex->stencil_clear_value != stencil) {
sctx->db_stencil_disable_expclear = true;
}
 
-- 
2.5.0

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[Mesa-dev] [PATCH 2/2] radeonsi: work around an MSAA fast stencil clear problem

[Nicolai Hähnle]

From: Nicolai Hähnle 

A piglit test (arb_texture_multisample-stencil-clear) has been sent.
This problem was discovered analyzing

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93767
---
 src/gallium/drivers/radeonsi/si_state.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 7ae6e8a..eb733f4 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2383,9 +2383,21 @@ static void si_init_depth_surface(struct si_context 
*sctx,
z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
  S_028040_ALLOW_EXPCLEAR(1);
 
-   if (rtex->surface.flags & RADEON_SURF_SBUFFER)
-   s_info |= S_028044_ALLOW_EXPCLEAR(1);
-   else
+   if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+   /* Workaround: For a not yet understood reason, the
+* combination of MSAA, fast stencil clear and stencil
+* decompress messes with subsequent stencil buffer
+* uses. Problem was reproduced on Verde, Bonaire,
+* Tonga, and Carrizo.
+*
+* Disabling EXPCLEAR works around the problem.
+*
+* Check piglit's arb_texture_multisample-stencil-clear
+* test if you want to try changing this.
+*/
+   if (rtex->resource.b.b.nr_samples <= 1)
+   s_info |= S_028044_ALLOW_EXPCLEAR(1);
+   } else
/* Use all of the htile_buffer for depth if there's no 
stencil. */
s_info |= S_028044_TILE_STENCIL_DISABLE(1);
 
-- 
2.5.0

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Re: [Mesa-dev] Mesa (master): 29 new commits

[Marek Olšák]

On Fri, Apr 22, 2016 at 11:28 PM, Nicolai Hähnle  wrote:
> On 22.04.2016 12:29, Nicolai Hähnle wrote:
>>
>> On 20.04.2016 23:02, Michel Dänzer wrote:
>>>
>>> On 21.04.2016 02:42, Marek Olšák wrote:

 On Thu, Apr 14, 2016 at 9:29 AM, Michel Dänzer 
 wrote:
>
> On 14.04.2016 11:37, Michel Dänzer wrote:
>>
>> On 12.04.2016 21:33, Marek =?UNKNOWN?B?T2zFocOhaw==?= wrote:
>>>
>>>
>>> URL:
>>>
>>> http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a4b74d1ba2c156766a7a5dbfef099c7db5d6694
>>>
>>> Author: Marek Olšák 
>>> Date:   Mon Apr 11 19:56:07 2016 +0200
>>>
>>>  gallium/radeon: relax requirements on VRAM placements on APUs
>>
>>
>> This change caused a bunch of ARB_shader_load_image_store piglit tests
>> to fail on my Kaveri, see some examples below. The incorrect values
>> seem consistent.
>>
>> I suppose some buffers end up in GTT instead of VRAM with this
>> change, but I'm not sure how that could cause problems. Any ideas?
>
>
> Also, with the code modified to use GTT only for everything but
> (potential) scanout buffers, the performance of Unigine Valley and the
> Unreal Engine 4 Elemental demo is reduced by about 30%. So the premise
> that GTT is about as fast as VRAM doesn't seem to hold true in practice
> (at least with Kaveri and presumably other (pre-)CIK APUs; maybe it's
> better with Carrizo and newer), which means that this change may cause
> performance of long-running processes to drop significantly over time.
>
> Given all these issues, I'm afraid it may be better to revert this
> change for now, until we have a better plan for dealing with this.


 Assuming you use the radeon kernel driver and you are not busy, would
 you please check whether the performance is lower on amdgpu as well?
>>>
>>>
>>> I am using the radeon driver, but also quite busy. Nicolai, can you try
>>> it on your Carrizo?
>>
>>
>> I don't see any difference on Unigine Valley with my Carrizo (512MB of
>> VRAM).
>
>
> I have learned an important lesson today: the Phoronix Test Suite runner
> eats my environment variables (and possibly babies?). So my earlier tests
> were for nothing.
>
> In reality, Unigine Valley gains about 30% frame rate with the VRAM_GTT
> placement.

It looks like we do need Kaveri results on amdgpu to know if CIK or
radeon is the issue. Then, we can either turn it off for radeon or
CIK.

Marek
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Re: [Mesa-dev] [PATCH 09/13] nir/lower_double_ops: lower round_even()

[Jason Ekstrand]

Matt,
Care to take this one?  I'm not that familiar with roundeven.
--Jason

On Tue, Apr 12, 2016 at 1:05 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Iago Toral Quiroga 
>
> At least i965 hardware does not have native support for round_even() on
> doubles.
> ---
>  src/compiler/nir/nir.h  |  3 +-
>  src/compiler/nir/nir_lower_double_ops.c | 58
> +
>  2 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index 4a57e74..0d17ce0 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -2289,7 +2289,8 @@ typedef enum {
> nir_lower_dtrunc = (1 << 3),
> nir_lower_dfloor = (1 << 4),
> nir_lower_dceil = (1 << 5),
> -   nir_lower_dfract = (1 << 6)
> +   nir_lower_dfract = (1 << 6),
> +   nir_lower_dround_even = (1 << 7)
>  } nir_lower_doubles_options;
>
>  void nir_lower_doubles(nir_shader *shader, nir_lower_doubles_options
> options);
> diff --git a/src/compiler/nir/nir_lower_double_ops.c
> b/src/compiler/nir/nir_lower_double_ops.c
> index 0f42c21..3d98075 100644
> --- a/src/compiler/nir/nir_lower_double_ops.c
> +++ b/src/compiler/nir/nir_lower_double_ops.c
> @@ -423,6 +423,55 @@ lower_fract(nir_builder *b, nir_ssa_def *src)
> return nir_fsub(b, src, nir_ffloor(b, src));
>  }
>
> +static nir_ssa_def *
> +lower_round_even(nir_builder *b, nir_ssa_def *src)
> +{
> +   /* If fract(src) == 0.5, then we will have to decide the rounding
> direction.
> +* We will do this by computing the mod(abs(src), 2) and testing if it
> +* is < 1 or not.
> +*
> +* We compute mod(abs(src), 2) as:
> +* abs(src) - 2.0 * floor(abs(src) / 2.0)
> +*/
> +   nir_ssa_def *two = nir_imm_double(b, 2.0);
> +   nir_ssa_def *abs_src = nir_fabs(b, src);
> +   nir_ssa_def *mod =
> +  nir_fsub(b,
> +   abs_src,
> +   nir_fmul(b,
> +two,
> +nir_ffloor(b,
> +   nir_fmul(b,
> +abs_src,
> +nir_imm_double(b, 0.5);
> +
> +   /*
> +* If fract(src) != 0.5, then we round as floor(src + 0.5)
> +*
> +* If fract(src) == 0.5, then we have to check the modulo:
> +*
> +*   if it is < 1 we need a trunc operation so we get:
> +*  0.5 -> 0,   -0.5 -> -0
> +*  2.5 -> 2,   -2.5 -> -2
> +*
> +*   otherwise we need to check if src >= 0, in which case we need to
> round
> +*   upwards, or not, in which case we need to round downwards so we
> get:
> +*  1.5 -> 2,   -1.5 -> -2
> +*  3.5 -> 4,   -3.5 -> -4
> +*/
> +   nir_ssa_def *fract = nir_ffract(b, src);
> +   return nir_bcsel(b,
> +nir_fne(b, fract, nir_imm_double(b, 0.5)),
> +nir_ffloor(b, nir_fadd(b, src, nir_imm_double(b,
> 0.5))),
> +nir_bcsel(b,
> +  nir_flt(b, mod, nir_imm_double(b, 1.0)),
> +  nir_ftrunc(b, src),
> +  nir_bcsel(b,
> +nir_fge(b, src, nir_imm_double(b,
> 0.0)),
> +nir_fadd(b, src,
> nir_imm_double(b, 0.5)),
> +nir_fsub(b, src,
> nir_imm_double(b, 0.5);
> +}
> +
>  static void
>  lower_doubles_instr(nir_alu_instr *instr, nir_lower_doubles_options
> options)
>  {
> @@ -466,6 +515,11 @@ lower_doubles_instr(nir_alu_instr *instr,
> nir_lower_doubles_options options)
>   return;
>break;
>
> +   case nir_op_fround_even:
> +  if (!(options & nir_lower_dround_even))
> + return;
> +  break;
> +
> default:
>return;
> }
> @@ -501,6 +555,10 @@ lower_doubles_instr(nir_alu_instr *instr,
> nir_lower_doubles_options options)
> case nir_op_ffract:
>result = lower_fract(&bld, src);
>break;
> +   case nir_op_fround_even:
> +  result = lower_round_even(&bld, src);
> +  break;
> +
> default:
>unreachable("unhandled opcode");
> }
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH 03/13] nir/builder: add nir_imm_double()

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Tue, Apr 12, 2016 at 1:05 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Connor Abbott 
>
> ---
>  src/compiler/nir/nir_builder.h | 8 
>  1 file changed, 8 insertions(+)
>
> diff --git a/src/compiler/nir/nir_builder.h
> b/src/compiler/nir/nir_builder.h
> index 84fc9bf..5787ba8 100644
> --- a/src/compiler/nir/nir_builder.h
> +++ b/src/compiler/nir/nir_builder.h
> @@ -116,6 +116,14 @@ nir_imm_float(nir_builder *build, float x)
>  }
>
>  static inline nir_ssa_def *
> +nir_imm_double(nir_builder *build, double x)
> +{
> +   nir_const_value v = { { .f64 = {x, 0, 0, 0} } };
> +   nir_ssa_def *def = nir_build_imm(build, 1, v, 64);
> +   return def;
> +}
> +
> +static inline nir_ssa_def *
>  nir_imm_vec4(nir_builder *build, float x, float y, float z, float w)
>  {
> nir_const_value v;
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH 07/13] nir/lower_double_ops: lower ceil()

[Jason Ekstrand]

On Tue, Apr 19, 2016 at 3:48 PM, Jason Ekstrand 
wrote:

> Reviewed-by: Jason Ekstrand 
>
> On Tue, Apr 12, 2016 at 1:05 AM, Samuel Iglesias Gonsálvez <
> sigles...@igalia.com> wrote:
>
>> From: Iago Toral Quiroga 
>>
>> At least i965 hardware does not have native support for ceil on doubles.
>> ---
>>  src/compiler/nir/nir.h  |  1 +
>>  src/compiler/nir/nir_lower_double_ops.c | 27 +++
>>  2 files changed, 28 insertions(+)
>>
>> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
>> index b7231a7..7c9e498 100644
>> --- a/src/compiler/nir/nir.h
>> +++ b/src/compiler/nir/nir.h
>> @@ -2288,6 +2288,7 @@ typedef enum {
>> nir_lower_drsq = (1 << 2),
>> nir_lower_dtrunc = (1 << 3),
>> nir_lower_dfloor = (1 << 4),
>> +   nir_lower_dceil = (1 << 5),
>>  } nir_lower_doubles_options;
>>
>>  void nir_lower_doubles(nir_shader *shader, nir_lower_doubles_options
>> options);
>> diff --git a/src/compiler/nir/nir_lower_double_ops.c
>> b/src/compiler/nir/nir_lower_double_ops.c
>> index e1ec6da..66e2be4 100644
>> --- a/src/compiler/nir/nir_lower_double_ops.c
>> +++ b/src/compiler/nir/nir_lower_double_ops.c
>> @@ -398,6 +398,25 @@ lower_floor(nir_builder *b, nir_ssa_def *src)
>>src));
>>  }
>>
>> +static nir_ssa_def *
>> +lower_ceil(nir_builder *b, nir_ssa_def *src)
>> +{
>> +   /* if x < 0,ceil(x) = trunc(x)
>> +* else if (x - trunc(x) == 0), ceil(x) = x
>> +* else,ceil(x) = trunc(x) + 1
>> +*/
>> +   nir_ssa_def *tr = nir_ftrunc(b, src);
>> +   return nir_bcsel(b,
>> +nir_flt(b, src, nir_imm_double(b, 0.0)),
>> +tr,
>> +nir_bcsel(b,
>> +  nir_fne(b,
>> +  nir_fsub(b, src, tr),
>> +  nir_imm_double(b, 0.0)),
>> +  nir_fadd(b, tr, nir_imm_double(b, 1.0)),
>> +  src));
>>
>
The comments I made on floor() apply here as well


> +}
>> +
>>  static void
>>  lower_doubles_instr(nir_alu_instr *instr, nir_lower_doubles_options
>> options)
>>  {
>> @@ -431,6 +450,11 @@ lower_doubles_instr(nir_alu_instr *instr,
>> nir_lower_doubles_options options)
>>   return;
>>break;
>>
>> +   case nir_op_fceil:
>> +  if (!(options & nir_lower_dceil))
>> + return;
>> +  break;
>> +
>> default:
>>return;
>> }
>> @@ -460,6 +484,9 @@ lower_doubles_instr(nir_alu_instr *instr,
>> nir_lower_doubles_options options)
>> case nir_op_ffloor:
>>result = lower_floor(&bld, src);
>>break;
>> +   case nir_op_fceil:
>> +  result = lower_ceil(&bld, src);
>> +  break;
>> default:
>>unreachable("unhandled opcode");
>> }
>> --
>> 2.5.0
>>
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>
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Re: [Mesa-dev] [PATCH 06/13] nir/lower_double_ops: lower floor()

[Jason Ekstrand]

On Fri, Apr 22, 2016 at 3:13 PM, Jason Ekstrand 
wrote:

>
>
> On Tue, Apr 12, 2016 at 1:05 AM, Samuel Iglesias Gonsálvez <
> sigles...@igalia.com> wrote:
>
>> From: Iago Toral Quiroga 
>>
>> At least i965 hardware does not have native support for floor on doubles.
>> ---
>>  src/compiler/nir/nir.h  |  1 +
>>  src/compiler/nir/nir_lower_double_ops.c | 29
>> +
>>  2 files changed, 30 insertions(+)
>>
>> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
>> index f83b2e0..b7231a7 100644
>> --- a/src/compiler/nir/nir.h
>> +++ b/src/compiler/nir/nir.h
>> @@ -2287,6 +2287,7 @@ typedef enum {
>> nir_lower_dsqrt = (1 << 1),
>> nir_lower_drsq = (1 << 2),
>> nir_lower_dtrunc = (1 << 3),
>> +   nir_lower_dfloor = (1 << 4),
>>  } nir_lower_doubles_options;
>>
>>  void nir_lower_doubles(nir_shader *shader, nir_lower_doubles_options
>> options);
>> diff --git a/src/compiler/nir/nir_lower_double_ops.c
>> b/src/compiler/nir/nir_lower_double_ops.c
>> index 9eec858..e1ec6da 100644
>> --- a/src/compiler/nir/nir_lower_double_ops.c
>> +++ b/src/compiler/nir/nir_lower_double_ops.c
>> @@ -377,6 +377,27 @@ lower_trunc(nir_builder *b, nir_ssa_def *src)
>> return nir_pack_double_2x32_split(b, new_src_lo, new_src_hi);
>>  }
>>
>> +static nir_ssa_def *
>> +lower_floor(nir_builder *b, nir_ssa_def *src)
>> +{
>> +   /*
>> +* For x >= 0, floor(x) = trunc(x)
>> +* For x < 0,
>> +*- if x is integer, floor(x) = x
>> +*- otherwise, floor(x) = trunc(x) - 1
>> +*/
>> +   nir_ssa_def *tr = nir_ftrunc(b, src);
>> +   return nir_bcsel(b,
>> +nir_fge(b, src, nir_imm_double(b, 0.0)),
>> +tr,
>> +nir_bcsel(b,
>> +  nir_fne(b,
>> +  nir_fsub(b, src, tr),
>> +  nir_imm_double(b, 0.0)),
>>
>
> As an aside, you can just as easily check "x is integer" by "x ==
> truc(x)".  That might be simpler.  Same goes for ceil().
>

One more thought (Sorry for all the e-mails): It might be better to
implement this as

floor(x) = (x >= 0 || x == trunc(x)) ? trunc(x) : trunc(x) - 1;

That way you only have one bcsel and fewer 64-bit values floating around.
It *might* reduce register pressure (not sure if it actually will).
--Jason


> +  nir_fsub(b, tr, nir_imm_double(b, 1.0)),
>> +  src));
>> +}
>> +
>>  static void
>>  lower_doubles_instr(nir_alu_instr *instr, nir_lower_doubles_options
>> options)
>>  {
>> @@ -405,6 +426,11 @@ lower_doubles_instr(nir_alu_instr *instr,
>> nir_lower_doubles_options options)
>>   return;
>>break;
>>
>> +   case nir_op_ffloor:
>> +  if (!(options & nir_lower_dfloor))
>> + return;
>> +  break;
>> +
>> default:
>>return;
>> }
>> @@ -431,6 +457,9 @@ lower_doubles_instr(nir_alu_instr *instr,
>> nir_lower_doubles_options options)
>> case nir_op_ftrunc:
>>result = lower_trunc(&bld, src);
>>break;
>> +   case nir_op_ffloor:
>> +  result = lower_floor(&bld, src);
>> +  break;
>> default:
>>unreachable("unhandled opcode");
>> }
>> --
>> 2.5.0
>>
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Re: [Mesa-dev] [PATCH 06/13] nir/lower_double_ops: lower floor()

[Jason Ekstrand]

On Tue, Apr 12, 2016 at 1:05 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Iago Toral Quiroga 
>
> At least i965 hardware does not have native support for floor on doubles.
> ---
>  src/compiler/nir/nir.h  |  1 +
>  src/compiler/nir/nir_lower_double_ops.c | 29 +
>  2 files changed, 30 insertions(+)
>
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index f83b2e0..b7231a7 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -2287,6 +2287,7 @@ typedef enum {
> nir_lower_dsqrt = (1 << 1),
> nir_lower_drsq = (1 << 2),
> nir_lower_dtrunc = (1 << 3),
> +   nir_lower_dfloor = (1 << 4),
>  } nir_lower_doubles_options;
>
>  void nir_lower_doubles(nir_shader *shader, nir_lower_doubles_options
> options);
> diff --git a/src/compiler/nir/nir_lower_double_ops.c
> b/src/compiler/nir/nir_lower_double_ops.c
> index 9eec858..e1ec6da 100644
> --- a/src/compiler/nir/nir_lower_double_ops.c
> +++ b/src/compiler/nir/nir_lower_double_ops.c
> @@ -377,6 +377,27 @@ lower_trunc(nir_builder *b, nir_ssa_def *src)
> return nir_pack_double_2x32_split(b, new_src_lo, new_src_hi);
>  }
>
> +static nir_ssa_def *
> +lower_floor(nir_builder *b, nir_ssa_def *src)
> +{
> +   /*
> +* For x >= 0, floor(x) = trunc(x)
> +* For x < 0,
> +*- if x is integer, floor(x) = x
> +*- otherwise, floor(x) = trunc(x) - 1
> +*/
> +   nir_ssa_def *tr = nir_ftrunc(b, src);
> +   return nir_bcsel(b,
> +nir_fge(b, src, nir_imm_double(b, 0.0)),
> +tr,
> +nir_bcsel(b,
> +  nir_fne(b,
> +  nir_fsub(b, src, tr),
> +  nir_imm_double(b, 0.0)),
>

As an aside, you can just as easily check "x is integer" by "x ==
truc(x)".  That might be simpler.  Same goes for ceil().


> +  nir_fsub(b, tr, nir_imm_double(b, 1.0)),
> +  src));
> +}
> +
>  static void
>  lower_doubles_instr(nir_alu_instr *instr, nir_lower_doubles_options
> options)
>  {
> @@ -405,6 +426,11 @@ lower_doubles_instr(nir_alu_instr *instr,
> nir_lower_doubles_options options)
>   return;
>break;
>
> +   case nir_op_ffloor:
> +  if (!(options & nir_lower_dfloor))
> + return;
> +  break;
> +
> default:
>return;
> }
> @@ -431,6 +457,9 @@ lower_doubles_instr(nir_alu_instr *instr,
> nir_lower_doubles_options options)
> case nir_op_ftrunc:
>result = lower_trunc(&bld, src);
>break;
> +   case nir_op_ffloor:
> +  result = lower_floor(&bld, src);
> +  break;
> default:
>unreachable("unhandled opcode");
> }
> --
> 2.5.0
>
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Re: [Mesa-dev] [PATCH v2] nir/lower_double_ops: lower trunc()

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

Did the v2 fix anything other than newly added tests?
--Jason

On Thu, Apr 21, 2016 at 10:13 PM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

> From: Iago Toral Quiroga 
>
> At least i965 hardware does not have native support for truncating doubles.
>
> v2:
>   - Simplified the implementation significantly.
>   - Fixed the else branch, that was not doing what we wanted.
> ---
>  src/compiler/nir/nir.h  |  1 +
>  src/compiler/nir/nir_lower_double_ops.c | 60
> +
>  2 files changed, 61 insertions(+)
>
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index 9bfb24a..ab8ae99 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -2330,6 +2330,7 @@ typedef enum {
> nir_lower_drcp = (1 << 0),
> nir_lower_dsqrt = (1 << 1),
> nir_lower_drsq = (1 << 2),
> +   nir_lower_dtrunc = (1 << 3),
>  } nir_lower_doubles_options;
>
>  void nir_lower_doubles(nir_shader *shader, nir_lower_doubles_options
> options);
> diff --git a/src/compiler/nir/nir_lower_double_ops.c
> b/src/compiler/nir/nir_lower_double_ops.c
> index e22e822..e8ae884 100644
> --- a/src/compiler/nir/nir_lower_double_ops.c
> +++ b/src/compiler/nir/nir_lower_double_ops.c
> @@ -299,6 +299,58 @@ lower_sqrt_rsq(nir_builder *b, nir_ssa_def *src, bool
> sqrt)
>  return res;
>  }
>
> +static nir_ssa_def *
> +lower_trunc(nir_builder *b, nir_ssa_def *src)
> +{
> +   nir_ssa_def *unbiased_exp = nir_isub(b, get_exponent(b, src),
> +nir_imm_int(b, 1023));
> +
> +   nir_ssa_def *frac_bits = nir_isub(b, nir_imm_int(b, 52), unbiased_exp);
> +
> +   /*
> +* Decide the operation to apply depending on the unbiased exponent:
> +*
> +* if (unbiased_exp < 0)
> +*return 0
> +* else if (unbiased_exp > 52)
> +*return src
> +* else
> +*return src & (~0 << frac_bits)
> +*
> +* Notice that the else branch is a 64-bit integer operation that we
> need
> +* to implement in terms of 32-bit integer arithmetics (at least until
> we
> +* support 64-bit integer arithmetics).
> +*/
> +
> +   /* Compute "~0 << frac_bits" in terms of hi/lo 32-bit integer math */
> +   nir_ssa_def *mask_lo =
> +  nir_bcsel(b,
> +nir_ige(b, frac_bits, nir_imm_int(b, 32)),
> +nir_imm_int(b, 0),
> +nir_ishl(b, nir_imm_int(b, ~0), frac_bits));
> +
> +   nir_ssa_def *mask_hi =
> +  nir_bcsel(b,
> +nir_ilt(b, frac_bits, nir_imm_int(b, 33)),
> +nir_imm_int(b, ~0),
> +nir_ishl(b,
> + nir_imm_int(b, ~0),
> + nir_isub(b, frac_bits, nir_imm_int(b, 32;
> +
> +   nir_ssa_def *src_lo = nir_unpack_double_2x32_split_x(b, src);
> +   nir_ssa_def *src_hi = nir_unpack_double_2x32_split_y(b, src);
> +
> +   return
> +  nir_bcsel(b,
> +nir_ilt(b, unbiased_exp, nir_imm_int(b, 0)),
> +nir_imm_double(b, 0.0),
> +nir_bcsel(b, nir_ige(b, unbiased_exp, nir_imm_int(b, 53)),
> +  src,
> +  nir_pack_double_2x32_split(b,
> + nir_iand(b, mask_lo,
> src_lo),
> + nir_iand(b, mask_hi,
> src_hi;
> +}
> +
>  static void
>  lower_doubles_instr(nir_alu_instr *instr, nir_lower_doubles_options
> options)
>  {
> @@ -322,6 +374,11 @@ lower_doubles_instr(nir_alu_instr *instr,
> nir_lower_doubles_options options)
>   return;
>break;
>
> +   case nir_op_ftrunc:
> +  if (!(options & nir_lower_dtrunc))
> + return;
> +  break;
> +
> default:
>return;
> }
> @@ -345,6 +402,9 @@ lower_doubles_instr(nir_alu_instr *instr,
> nir_lower_doubles_options options)
> case nir_op_frsq:
>result = lower_sqrt_rsq(&bld, src, false);
>break;
> +   case nir_op_ftrunc:
> +  result = lower_trunc(&bld, src);
> +  break;
> default:
>unreachable("unhandled opcode");
> }
> --
> 2.5.0
>
>
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Re: [Mesa-dev] [PATCH 4/4] gbm: Add map/unmap functions

[Rob Herring]

On Fri, Apr 22, 2016 at 1:21 PM, Eric Anholt  wrote:
> Rob Herring  writes:
>
>> This adds map and unmap functions to GBM utilizing the DRIimage extension
>> mapImage/unmapImage functions or existing internal mapping for dumb
>> buffers. Unlike prior attempts, this version provides a region to map and
>> usage flags for the mapping. The operation follows the same semantics as
>> the gallium transfer_map() function.
>>
>> This was tested with GBM based gralloc on Android.
>>
>> This still creates a context, but I've moved it into gbm_create_device
>> rather than in the map function. This should remove any need for reference
>> counting and problems with memory leaks.
>>
>> Signed-off-by: Rob Herring 
>
>
>
>> @@ -981,6 +1033,8 @@ dri_device_create(int fd)
>> dri->base.base.fd = fd;
>> dri->base.base.bo_create = gbm_dri_bo_create;
>> dri->base.base.bo_import = gbm_dri_bo_import;
>> +   dri->base.base.bo_map = gbm_dri_bo_map;
>> +   dri->base.base.bo_unmap = gbm_dri_bo_unmap;
>> dri->base.base.is_format_supported = gbm_dri_is_format_supported;
>> dri->base.base.bo_write = gbm_dri_bo_write;
>> dri->base.base.bo_get_fd = gbm_dri_bo_get_fd;
>> @@ -1004,6 +1058,10 @@ dri_device_create(int fd)
>> if (ret)
>>goto err_dri;
>>
>> +   if (dri->image->base.version >= 12)
>> +  dri->context = dri->dri2->createNewContext(dri->screen, NULL,
>> + NULL, NULL);
>> +
>> return &dri->base.base;
>
> I don't think we want to always make a spare context just in case
> someone uses the map API.  Contexts can be pretty expensive to set up,
> in time (for piglit tests on gbm) and memory (for X.Org).

There was some discussion about this context in the last version. I
put it here for now for simplicity given what to do here is not clear.
It's not clear to me exactly what the concurrency guarantees there are
with GBM. I was assuming gbm_device_create doesn't need to be thread
safe, but creating and mapping BOs does.

Rob
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Re: [Mesa-dev] Mesa (master): 29 new commits

[Nicolai Hähnle]

On 22.04.2016 12:29, Nicolai Hähnle wrote:

On 20.04.2016 23:02, Michel Dänzer wrote:

On 21.04.2016 02:42, Marek Olšák wrote:

On Thu, Apr 14, 2016 at 9:29 AM, Michel Dänzer 
wrote:

On 14.04.2016 11:37, Michel Dänzer wrote:

On 12.04.2016 21:33, Marek =?UNKNOWN?B?T2zFocOhaw==?= wrote:


URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a4b74d1ba2c156766a7a5dbfef099c7db5d6694

Author: Marek Olšák 
Date:   Mon Apr 11 19:56:07 2016 +0200

 gallium/radeon: relax requirements on VRAM placements on APUs


This change caused a bunch of ARB_shader_load_image_store piglit tests
to fail on my Kaveri, see some examples below. The incorrect values
seem consistent.

I suppose some buffers end up in GTT instead of VRAM with this
change, but I'm not sure how that could cause problems. Any ideas?


Also, with the code modified to use GTT only for everything but
(potential) scanout buffers, the performance of Unigine Valley and the
Unreal Engine 4 Elemental demo is reduced by about 30%. So the premise
that GTT is about as fast as VRAM doesn't seem to hold true in practice
(at least with Kaveri and presumably other (pre-)CIK APUs; maybe it's
better with Carrizo and newer), which means that this change may cause
performance of long-running processes to drop significantly over time.

Given all these issues, I'm afraid it may be better to revert this
change for now, until we have a better plan for dealing with this.


Assuming you use the radeon kernel driver and you are not busy, would
you please check whether the performance is lower on amdgpu as well?


I am using the radeon driver, but also quite busy. Nicolai, can you try
it on your Carrizo?


I don't see any difference on Unigine Valley with my Carrizo (512MB of
VRAM).


I have learned an important lesson today: the Phoronix Test Suite runner 
eats my environment variables (and possibly babies?). So my earlier 
tests were for nothing.


In reality, Unigine Valley gains about 30% frame rate with the VRAM_GTT 
placement.


Nicolai
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Re: [Mesa-dev] [PATCH v3 4/4] r600g: use do_endian_swap in texture swapping function

[Marek Olšák]

On Thu, Apr 21, 2016 at 4:39 PM, Oded Gabbay  wrote:
> For some texture formats we need to take "do_endian_swap" into account
> when configuring their swizzling.
>
> Signed-off-by: Oded Gabbay 
> ---
>  src/gallium/drivers/r600/r600_state_common.c | 35 
> +++-
>  1 file changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/r600/r600_state_common.c 
> b/src/gallium/drivers/r600/r600_state_common.c
> index fea2bcb..2c82e7e 100644
> --- a/src/gallium/drivers/r600/r600_state_common.c
> +++ b/src/gallium/drivers/r600/r600_state_common.c
> @@ -2227,6 +2227,9 @@ uint32_t r600_translate_texformat(struct pipe_screen 
> *screen,
> bool is_srgb_valid = FALSE;
> const unsigned char swizzle_[4] = {0, 0, 0, 0};
> const unsigned char swizzle_[4] = {1, 1, 1, 1};
> +   const unsigned char swizzle_xxxy[4] = {0, 0, 0, 1};
> +   const unsigned char swizzle_zyx1[4] = {2, 1, 0, 5};
> +   const unsigned char swizzle_zyxw[4] = {2, 1, 0, 3};
>
> int i;
> const uint32_t sign_bit[4] = {
> @@ -2235,11 +2238,41 @@ uint32_t r600_translate_texformat(struct pipe_screen 
> *screen,
> S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
> S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
> };
> +
> +   /* Need to replace the specified texture formats in case of 
> big-endian.
> +* These formats are formats that have channels with number of bits
> +* not divisible by 8.
> +* Mesa conversion functions don't swap bits for those formats, and 
> because
> +* we transmit this over a serial bus to the GPU (PCIe), the
> +* bit-endianess is important!!!
> +* In case we have an "opposite" format, just use that for the 
> swizzling
> +* information. If we don't have such an "opposite" format, we need
> +* to use a fixed swizzle info instead (see below)
> +*/
> +   if (format == PIPE_FORMAT_R4A4_UNORM && do_endian_swap)
> +   format = PIPE_FORMAT_A4R4_UNORM;
> +
> desc = util_format_description(format);
>
> /* Depth and stencil swizzling is handled separately. */
> if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
> -   word4 |= r600_get_swizzle_combined(desc->swizzle, 
> swizzle_view, FALSE);
> +   /* Need to check for specific texture formats that don't have
> +* an "opposite" format we can use. For those formats, we 
> directly
> +* specify the swizzling, which is the LE swizzling as 
> defined in
> +* u_format.csv
> +*/
> +   if (do_endian_swap) {
> +   if (format == PIPE_FORMAT_L4A4_UNORM)
> +   word4 |= 
> r600_get_swizzle_combined(swizzle_xxxy, swizzle_view, FALSE);
> +   else if (format == PIPE_FORMAT_B4G4R4A4_UNORM)
> +   word4 |= 
> r600_get_swizzle_combined(swizzle_zyxw, swizzle_view, FALSE);
> +   else if (format == PIPE_FORMAT_B4G4R4X4_UNORM || 
> format == PIPE_FORMAT_B5G6R5_UNORM)
> +   word4 |= 
> r600_get_swizzle_combined(swizzle_zyx1, swizzle_view, FALSE);
> +   else
> +   word4 |= 
> r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
> +   } else {
> +   word4 |= r600_get_swizzle_combined(desc->swizzle, 
> swizzle_view, FALSE);
> +   }

Since I can't say if this is correct or if it just hides bugs
elsewhere, I'm okay with it if nobody else comments.

Marek
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Re: [Mesa-dev] [PATCH v3 3/4] r600g: use do_endian_swap in color swapping functions

[Marek Olšák]

On Thu, Apr 21, 2016 at 4:39 PM, Oded Gabbay  wrote:
> For some formats we need to take "do_endian_swap" into account when
> configuring swapping for color buffers.
>
> Signed-off-by: Oded Gabbay 
> ---
>  src/gallium/drivers/r600/r600_state_common.c |  2 +-
>  src/gallium/drivers/radeon/r600_texture.c| 20 +---
>  2 files changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_state_common.c 
> b/src/gallium/drivers/r600/r600_state_common.c
> index 1d44ef0..fea2bcb 100644
> --- a/src/gallium/drivers/r600/r600_state_common.c
> +++ b/src/gallium/drivers/r600/r600_state_common.c
> @@ -2639,7 +2639,7 @@ uint32_t r600_translate_colorformat(enum chip_class 
> chip, enum pipe_format forma
> return V_0280A0_COLOR_32_32;
> }
> } else if (HAS_SIZE(8,24,0,0)) {
> -   return V_0280A0_COLOR_24_8;
> +   return (do_endian_swap ? V_0280A0_COLOR_8_24 : 
> V_0280A0_COLOR_24_8);
> } else if (HAS_SIZE(24,8,0,0)) {
> return V_0280A0_COLOR_8_24;
> }
> diff --git a/src/gallium/drivers/radeon/r600_texture.c 
> b/src/gallium/drivers/radeon/r600_texture.c
> index d446061..ead4dd7 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -1419,7 +1419,8 @@ unsigned r600_translate_colorswap(enum pipe_format 
> format, bool do_endian_swap)
> else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
>  (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
>  (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
> -   return V_0280A0_SWAP_STD_REV; /* YX__ */
> +   /* YX__ */
> +   return (do_endian_swap ? V_0280A0_SWAP_STD : 
> V_0280A0_SWAP_STD_REV);
> else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
> return V_0280A0_SWAP_ALT; /* X__Y */
> else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
> @@ -1427,20 +1428,25 @@ unsigned r600_translate_colorswap(enum pipe_format 
> format, bool do_endian_swap)
> break;
> case 3:
> if (HAS_SWIZZLE(0,X))
> -   return V_0280A0_SWAP_STD; /* XYZ */
> +   return (do_endian_swap ? V_0280A0_SWAP_STD_REV : 
> V_0280A0_SWAP_STD);
> else if (HAS_SWIZZLE(0,Z))
> return V_0280A0_SWAP_STD_REV; /* ZYX */
> break;
> case 4:
> /* check the middle channels, the 1st and 4th channel can be 
> NONE */
> -   if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
> +   if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
> return V_0280A0_SWAP_STD; /* XYZW */
> -   else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
> +   } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
> return V_0280A0_SWAP_STD_REV; /* WZYX */
> -   else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
> +   } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
> return V_0280A0_SWAP_ALT; /* ZYXW */

These braces don't have to be there.

I don't understand the logic behind this patch, but I'm okay with it
if nobody else comments.

Marek
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[Mesa-dev] [Bug 94955] Uninitialized variables leads to random segfaults (valgrind log, apitrace attached)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94955

--- Comment #20 from Roland Scheidegger  ---
(In reply to Bruce Cherniak from comment #19)
> Thanks Roland!  You patch fixes the segv I get when running both llvmpipe
> and OpenSWR; and the test itself now passes on llvmpipe.

I wonder what the test expects, I haven't seen anything but NaN coords with
that sampler ;-). That can't have possibly given really useful results, unless
not crashing is good enough to pass :-).

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Re: [Mesa-dev] [PATCH mesa v2] nouveau: codegen: combineLd/St do not combine indirect loads

[Ilia Mirkin]

Reviewed-by: Ilia Mirkin 

On Fri, Apr 22, 2016 at 7:07 AM, Hans de Goede  wrote:
> combineLd/St would combine, i.e. :
>
> st  u32 # g[$r2+0x0] $r2
> st  u32 # g[$r2+0x4] $r3
>
> into:
>
> st  u64 # g[$r2+0x0] $r2d
>
> But this is only valid if r2 contains an 8 byte aligned address,
> which is not guaranteed for compute shaders
>
> This commit checks for src0 dim 0 not being indirect when combining
> loads / stores as combining indirect loads / stores may break alignment
> rules.
>
> Signed-off-by: Hans de Goede 
> ---
> Changes in v2:
> -Only check for indirect loads/stores in the compute case
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 7 +++
>  1 file changed, 7 insertions(+)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> index 6ec5fa5..9ce062e 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> @@ -2216,6 +2216,9 @@ MemoryOpt::combineLd(Record *rec, Instruction *ld)
> if (((size == 0x8) && (MIN2(offLd, offRc) & 0x7)) ||
> ((size == 0xc) && (MIN2(offLd, offRc) & 0xf)))
>return false;
> +   // for compute indirect loads are not guaranteed to be aligned
> +   if (prog->getType() == Program::TYPE_COMPUTE && rec->rel[0])
> +  return false;
>
> assert(sizeRc + sizeLd <= 16 && offRc != offLd);
>
> @@ -2268,8 +2271,12 @@ MemoryOpt::combineSt(Record *rec, Instruction *st)
> if (!prog->getTarget()->
> isAccessSupported(st->getSrc(0)->reg.file, typeOfSize(size)))
>return false;
> +   // no unaligned stores
> if (size == 8 && MIN2(offRc, offSt) & 0x7)
>return false;
> +   // for compute indirect stores are not guaranteed to be aligned
> +   if (prog->getType() == Program::TYPE_COMPUTE && rec->rel[0])
> +  return false;
>
> st->takeExtraSources(0, extra); // save predicate and indirect address
>
> --
> 2.7.3
>
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Re: [Mesa-dev] [PATCH 1/3] configure.ac: search for and set PYTHON3

[Jonathan Gray]

On Fri, Apr 22, 2016 at 11:09:52AM -0700, Kenneth Graunke wrote:
> On Saturday, April 23, 2016 1:21:38 AM PDT Jonathan Gray wrote:
> > src/intel/genxml/gen_pack_header.py requires python3.
> > 
> > Signed-off-by: Jonathan Gray 
> > ---
> >  configure.ac | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/configure.ac b/configure.ac
> > index 6b00cf9..9459489 100644
> > --- a/configure.ac
> > +++ b/configure.ac
> > @@ -99,6 +99,7 @@ AM_PROG_CC_C_O
> >  AM_PROG_AS
> >  AX_CHECK_GNU_MAKE
> >  AC_CHECK_PROGS([PYTHON2], [python2.7 python2 python])
> > +AC_CHECK_PROGS([PYTHON3], [python3.4 python3])
> >  AC_PROG_SED
> >  AC_PROG_MKDIR_P
> 
> Why mention python3.4 explicitly?  Are we trying to check for 3.4+?
> 
> My system has /usr/bin/python3 -> /usr/bin/python3.5, FWIW...no 3.4.

Yes, I realised that after sending it out and added 3.5

The default python3 version here is python3.4 with python3.5 also
available.  There are no 'python' or 'python3' symlinks.

commit 9b8a12fea59a6fa81b190686aef5298ba3b6b4f8
Author: Jonathan Gray 
Date:   Fri Apr 22 15:04:47 2016 +1000

configure.ac: search for and set PYTHON3

src/intel/genxml/gen_pack_header.py requires python3.

v2: check for python3.5 as well

Signed-off-by: Jonathan Gray 
Reviewed-by: Emil Velikov 

diff --git a/configure.ac b/configure.ac
index 6b00cf9..2474078 100644
--- a/configure.ac
+++ b/configure.ac
@@ -99,6 +99,7 @@ AM_PROG_CC_C_O
 AM_PROG_AS
 AX_CHECK_GNU_MAKE
 AC_CHECK_PROGS([PYTHON2], [python2.7 python2 python])
+AC_CHECK_PROGS([PYTHON3], [python3.5 python3.4 python3])
 AC_PROG_SED
 AC_PROG_MKDIR_P
 
@@ -2788,6 +2789,7 @@ if test "x$MESA_LLVM" = x1; then
 echo ""
 fi
 echo "PYTHON2: $PYTHON2"
+echo "PYTHON3: $PYTHON3"
 
 echo ""
 echo "Run '${MAKE-make}' to build Mesa"
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[Mesa-dev] [Bug 94955] Uninitialized variables leads to random segfaults (valgrind log, apitrace attached)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94955

--- Comment #19 from Bruce Cherniak  ---
Thanks Roland!  You patch fixes the segv I get when running both llvmpipe and
OpenSWR; and the test itself now passes on llvmpipe.

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Re: [Mesa-dev] [PATCH v3 2/4] r600g: set endianess of 16/32-bit buffers according to do_endian_swap

[Marek Olšák]

On Thu, Apr 21, 2016 at 4:39 PM, Oded Gabbay  wrote:
> This patch modifies r600_colorformat_endian_swap(), so for 16-bit and for
> 32-bit buffers, the endianess configuration will be determined not only
> by the color/texture format, but also by the do_endian_swap parameter.
>
> The only exception is for array formats, which are always set to not do
> swapping, because for them gallium sets an alias based on the machine's
> endianess.
>
> Signed-off-by: Oded Gabbay 
> ---
>  src/gallium/drivers/r600/r600_state_common.c | 17 -
>  1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_state_common.c 
> b/src/gallium/drivers/r600/r600_state_common.c
> index 2aea982..1d44ef0 100644
> --- a/src/gallium/drivers/r600/r600_state_common.c
> +++ b/src/gallium/drivers/r600/r600_state_common.c
> @@ -2691,17 +2691,25 @@ uint32_t r600_colorformat_endian_swap(uint32_t 
> colorformat, bool do_endian_swap)
> return ENDIAN_NONE;
>
> /* 16-bit buffers. */
> +   case V_0280A0_COLOR_8_8:
> +   /*
> +* No need to do endian swaps on array formats,
> +* as mesa<-->pipe formats conversion take into 
> account
> +* the endianess
> +*/
> +   return ENDIAN_NONE;
> +
> case V_0280A0_COLOR_5_6_5:
> case V_0280A0_COLOR_1_5_5_5:
> case V_0280A0_COLOR_4_4_4_4:
> case V_0280A0_COLOR_16:
> -   case V_0280A0_COLOR_8_8:
> -   return ENDIAN_8IN16;
> +   return (do_endian_swap ? ENDIAN_8IN16 : ENDIAN_NONE);
>
> /* 32-bit buffers. */
> case V_0280A0_COLOR_8_8_8_8:
> +   case V_0280A0_COLOR_16_16:

I think 16_16 should set ENDIAN_8IN16 unless there is a bug in
src/mesa/. It's the same as 16 and 16_16_16_16, because the number of
components doesn't matter for array formats. The same applies to
FLOAT.

Marek
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Re: [Mesa-dev] [PATCH 1/4] scons: Move fallback HAVE_* definitions to headers.

[Jose Fonseca]

On 22/04/16 15:03, Roland Scheidegger wrote:

Am 22.04.2016 um 10:35 schrieb Jose Fonseca:

These were being defined in SCons, but it's not practical:

- we actually need to include Gallium headers from external source trees, with
completely disjoint build infrastructure, and it's unsustainable to
replicate the HAVE_xxx checks or even hard-coded defines across
everywhere.

- checking compiler version via command line doesn't really work due to
   Clang essentially being like a cameleon which can fake either GCC or
   MSVC

There's no change for autoconf.
---
  include/c99_compat.h | 44 
  scons/gallium.py | 48 +---
  src/util/macros.h|  2 ++
  3 files changed, 51 insertions(+), 43 deletions(-)

diff --git a/include/c99_compat.h b/include/c99_compat.h
index b55ad9c..bfe655b 100644
--- a/include/c99_compat.h
+++ b/include/c99_compat.h
@@ -135,4 +135,48 @@ test_c99_compat_h(const void * restrict a,
  #endif


+/* Fallback definitions, for build systems other than autoconfig which don't
+ * auto-detect these things. */
+#ifdef HAVE_NO_AUTOCONF
+
+#  ifndef _WIN32
+#define HAVE_PTHREAD
+#define HAVE_POSIX_MEMALIGN
+#  endif
+
+#  ifdef __GNUC__
+#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 2)
+#  error "GCC version 4.2 or higher required"
+#endif
+
+ /* https://gcc.gnu.org/onlinedocs/gcc-4.2.4/gcc/Other-Builtins.html */
+#define HAVE___BUILTIN_CLZ 1
+#define HAVE___BUILTIN_CLZLL 1
+#define HAVE___BUILTIN_CTZ 1
+#define HAVE___BUILTIN_EXPECT 1
+#define HAVE___BUILTIN_FFS 1
+#define HAVE___BUILTIN_FFSLL 1
+#define HAVE___BUILTIN_POPCOUNT 1
+#define HAVE___BUILTIN_POPCOUNTLL 1
+ /* https://gcc.gnu.org/onlinedocs/gcc-4.2.4/gcc/Function-Attributes.html 
*/
+#define HAVE_FUNC_ATTRIBUTE_FLATTEN 1
+#define HAVE_FUNC_ATTRIBUTE_UNUSED 1
+#define HAVE_FUNC_ATTRIBUTE_FORMAT 1
+#define HAVE_FUNC_ATTRIBUTE_PACKED 1
+
+#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)
+   /* https://gcc.gnu.org/onlinedocs/gcc-4.3.6/gcc/Other-Builtins.html */
+#  define HAVE___BUILTIN_BSWAP32 1
+#  define HAVE___BUILTIN_BSWAP64 1
+#endif
+
+#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+#  define HAVE___BUILTIN_UNREACHABLE 1
+#endif
+
+#  endif /* __GNUC__ */
+
+#endif /* !HAVE_AUTOCONF */
+
+
  #endif /* _C99_COMPAT_H_ */

Is that the right file for putting them in?


I could put them in a seperate header.

The ideal would be for autotools to generate "mesa_config.h" somewhere 
with all the #defines instead of passing -DHAVE foo in the command line. 
 In that case, Scons would use a handwritten mesa_config.h with the the 
above definitions, and would use it by merely adding it's include path.


But until that happens it doesn't make much difference.


But either way, for the series:
Reviewed-by: Roland Scheidegger 


Thanks.

Jose
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Re: [Mesa-dev] [PATCH v3 1/4] r600g/radeonsi: send endian info to format translation functions

[Marek Olšák]

On Thu, Apr 21, 2016 at 4:39 PM, Oded Gabbay  wrote:
> Because r600 GPUs can't do swap in their DB unit, we need to disable
> endianess swapping for textures that are handled by DB.
>
> There are four format translation functions in r600g driver:
>
> - r600_translate_texformat
> - r600_colorformat_endian_swap
> - r600_translate_colorformat
> - r600_translate_colorswap
>
> This patch adds a new parameters to those functions, called
> "do_endian_swap". When running in a big-endian machine, the calling
> functions will check whether the texture/color is handled by DB -
> "rtex->is_depth && !rtex->is_flushing_texture" - and if so, they will
> send FALSE through this parameter. Otherwise, they will send TRUE.
>
> The translation functions, in specific cases, will look at this parameter
> and configure the swapping accordingly.
>
> Signed-off-by: Oded Gabbay 
> ---
>  src/gallium/drivers/r600/evergreen_state.c| 42 
> ++-
>  src/gallium/drivers/r600/r600_pipe.h  |  8 +++--
>  src/gallium/drivers/r600/r600_state.c | 27 +++--
>  src/gallium/drivers/r600/r600_state_common.c  |  8 +++--
>  src/gallium/drivers/radeon/r600_pipe_common.h |  2 +-
>  src/gallium/drivers/radeon/r600_texture.c |  4 +--
>  src/gallium/drivers/radeonsi/si_state.c   |  4 +--
>  7 files changed, 62 insertions(+), 33 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/evergreen_state.c 
> b/src/gallium/drivers/r600/evergreen_state.c
> index 2ad9e3e..8ff40aa 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -213,13 +213,14 @@ static uint32_t r600_translate_dbformat(enum 
> pipe_format format)
>
>  static bool r600_is_sampler_format_supported(struct pipe_screen *screen, 
> enum pipe_format format)
>  {
> -   return r600_translate_texformat(screen, format, NULL, NULL, NULL) != 
> ~0U;
> +   return r600_translate_texformat(screen, format, NULL, NULL, NULL,
> +   FALSE) != ~0U;
>  }
>
>  static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum 
> pipe_format format)
>  {
> -   return r600_translate_colorformat(chip, format) != ~0U &&
> -   r600_translate_colorswap(format) != ~0U;
> +   return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
> +   r600_translate_colorswap(format, FALSE) != ~0U;
>  }
>
>  static bool r600_is_zs_format_supported(enum pipe_format format)
> @@ -677,6 +678,7 @@ evergreen_create_sampler_view_custom(struct pipe_context 
> *ctx,
> unsigned base_level, first_level, last_level;
> unsigned dim, last_layer;
> uint64_t va;
> +   bool do_endian_swap = FALSE;
>
> if (!view)
> return NULL;
> @@ -722,16 +724,19 @@ evergreen_create_sampler_view_custom(struct 
> pipe_context *ctx,
> }
> }
>
> +   if (R600_BIG_ENDIAN)
> +   do_endian_swap = !(tmp->is_depth && 
> !tmp->is_flushing_texture);
> +
> format = r600_translate_texformat(ctx->screen, pipe_format,
>   swizzle,
> - &word4, &yuv_format);
> + &word4, &yuv_format, 
> do_endian_swap);
> assert(format != ~0);
> if (format == ~0) {
> FREE(view);
> return NULL;
> }
>
> -   endian = r600_colorformat_endian_swap(format);
> +   endian = r600_colorformat_endian_swap(format, do_endian_swap);
>
> base_level = 0;
> first_level = state->u.tex.first_level;
> @@ -942,15 +947,22 @@ void evergreen_init_color_surface_rat(struct 
> r600_context *rctx,
> struct r600_surface *surf)
>  {
> struct pipe_resource *pipe_buffer = surf->base.texture;
> -   unsigned format = r600_translate_colorformat(rctx->b.chip_class,
> -surf->base.format);
> -   unsigned endian = r600_colorformat_endian_swap(format);
> -   unsigned swap = r600_translate_colorswap(surf->base.format);
> +   struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
> unsigned block_size =
> align(util_format_get_blocksize(pipe_buffer->format), 4);
> unsigned pitch_alignment =
> MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / 
> block_size);
> unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
> +   unsigned format, endian, swap;
> +   bool do_endian_swap = FALSE;
> +
> +   if (R600_BIG_ENDIAN)
> +   do_endian_swap = !(rtex->is_depth && 
> !rtex->is_flushing_texture);
> +
> +   format = r600_translate_colorformat(rctx->b.chip_class, 
> surf->base.format,
> + do_endian_swap);
> +   endian = r600_colorformat_endian_swap(format, do_endian_swap);
> 

Re: [Mesa-dev] [v2 7/7] i965/blorp: Do not tricker re-emission of base state address

[Pohjolainen, Topi]

On Fri, Apr 22, 2016 at 11:59:47AM -0700, Matt Turner wrote:
> On Fri, Apr 22, 2016 at 11:05 AM, Topi Pohjolainen
>  wrote:
> > In case blorp needs to configure it will be just as if render or
> > compute pipeline had configured it.
> 
> s/tricker/trigger/ in the title.

Ken told me the same thing :), need to remember from now on. I've been
writing it wrong all these years.
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Re: [Mesa-dev] [v2 7/7] i965/blorp: Do not tricker re-emission of base state address

[Matt Turner]

On Fri, Apr 22, 2016 at 11:05 AM, Topi Pohjolainen
 wrote:
> In case blorp needs to configure it will be just as if render or
> compute pipeline had configured it.

s/tricker/trigger/ in the title.
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Re: [Mesa-dev] [PATCH 01/13] i965: Add a dependency on libisl

[Jonathan Gray]

On Fri, Apr 22, 2016 at 10:50:33AM -0700, Jason Ekstrand wrote:
> On Fri, Apr 22, 2016 at 10:15 AM, Jonathan Gray  wrote:
>
> > On Fri, Apr 22, 2016 at 05:31:29PM +0100, Emil Velikov wrote:
> > > On 22 April 2016 at 16:08, Jonathan Gray  wrote:
> > > > It is worth noting that the isl code extensively requires designated
> > > > initialisers on anonymous structs.  It isn't clear to me when gcc
> > introduced
> > > > support for this but it isn't in 4.2.
> > > >
> > > I think it should work for GCC 4.2 with -fms-extensions. We used to
> > > set -std=gnu99 for pre 4.6 which effectively enables it the extension.
> > > Can you double-check ?
> >
> > The part that sets gnu99 for < gcc 4.6 is still there, using
> > -fms-extensions
> > does not help for these.
> >
> > libtool: compile:  gcc -DPACKAGE_NAME=\"Mesa\" -DPACKAGE_TARNAME=\"mesa\"
> > -DPACKAGE_VERSION=\"11.3.0-devel\" "-DPACKAGE_STRING=\"Mesa 11.3.0-devel\""
> > "-DPACKAGE_BUGREPORT=\"
> > https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\"";
> > -DPACKAGE_URL=\"\" -DPACKAGE=\"mesa\" -DVERSION=\"11.3.0-devel\"
> > -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1
> > -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1
> > -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_DLFCN_H=1 -DLT_OBJDIR=\".libs/\"
> > -DYYTEXT_POINTER=1 -DHAVE___BUILTIN_CLZ=1 -DHAVE___BUILTIN_CLZLL=1
> > -DHAVE___BUILTIN_CTZ=1 -DHAVE___BUILTIN_EXPECT=1 -DHAVE___BUILTIN_FFS=1
> > -DHAVE___BUILTIN_FFSLL=1 -DHAVE___BUILTIN_POPCOUNT=1
> > -DHAVE___BUILTIN_POPCOUNTLL=1 -DHAVE_FUNC_ATTRIBUTE_CONST=1
> > -DHAVE_FUNC_ATTRIBUTE_FLATTEN=1 -DHAVE_FUNC_ATTRIBUTE_FORMAT=1
> > -DHAVE_FUNC_ATTRIBUTE_MALLOC=1 -DHAVE_FUNC_ATTRIBUTE_PACKED=1
> > -DHAVE_FUNC_ATTRIBUTE_PURE=1 -DHAVE_FUNC_ATTRIBUTE_UNUSED=1
> > -DHAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT=1 -DHAVE_DLADDR=1
> > -DHAVE_CLOCK_GETTIME=1 -DHAVE_PTHREAD_PRIO_INHERIT=1 -DHAVE_PTHREAD=1
> > -DHAVE_SHA1_IN_LIBC=1 -DHAVE_VALGRIND=1 -I. -I/usr/X11R6/include
> > -I/usr/X11R6/include/libdrm -I/usr/local/include/valgrind
> > -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -DDEBUG
> > -DTEXTURE_FLOAT_ENABLED -DUSE_X86_64_ASM -DHAVE_SYS_SYSCTL_H -DHAVE_STRTOF
> > -DHAVE_MKOSTEMP -DHAVE_DLOPEN -DHAVE_POSIX_MEMALIGN -DHAVE_LIBDRM
> > -DHAVE_SHA1 -DGLX_USE_DRM -DGLX_INDIRECT_RENDERING -DGLX_DIRECT_RENDERING
> > -DHAVE_ALIAS -DHAVE_MINCORE -I../../../include -I../../../src
> > -I../../../src/intel -I../../../src/mapi -I../../../src/mesa
> > -I../../../src/mesa/drivers/dri/common -I../../../src/mesa/drivers/dri/i965
> > -I../../../src/gallium/auxiliary -I../../../src/gallium/include
> > -I../../../src -I../../../src/intel -g -O2 -Wall -std=gnu99
> > -Werror=implicit-function-declaration -Werror=missing-prototypes
> > -fno-strict-aliasing -fno-math-errno -fno-trapping-math -fno-builtin-memcmp
> > -Wno-override-init -DGEN_VERSIONx10=70 -g -O2 -Wall -std=gnu99
> > -Werror=implicit-function-declaration -Werror=missing-prototypes
> > -fno-strict-aliasing -fno-math-errno -fno-trapping-math -fno-builtin-memcmp
> > -MT libisl_gen7_la-isl_gen7.lo -MD -MP -MF
> > .deps/libisl_gen7_la-isl_gen7.Tpo -c isl_gen7.c  -fPIC -DPIC -o
> > .libs/libisl_gen7_la-isl_gen7.o
> > In file included from isl_gen7.h:26,
> >  from isl_gen7.c:24:
> > isl_priv.h: In function 'isl_extent3d_sa_to_el':
> > isl_priv.h:119: error: unknown field 'w' specified in initializer
> > isl_priv.h:119: warning: missing braces around initializer
> > isl_priv.h:119: warning: (near initialization for
> > '(anonymous).')
> > isl_priv.h:120: error: unknown field 'h' specified in initializer
> > isl_priv.h:121: error: unknown field 'd' specified in initializer
> > isl_priv.h: In function 'isl_extent3d_el_to_sa':
> > isl_priv.h:131: error: unknown field 'w' specified in initializer
> > isl_priv.h:131: warning: missing braces around initializer
> > isl_priv.h:131: warning: (near initialization for
> > '(anonymous).')
> > isl_priv.h:132: error: unknown field 'h' specified in initializer
> > isl_priv.h:133: error: unknown field 'd' specified in initializer
> > isl_gen7.c: In function 'gen7_choose_image_alignment_el':
> > isl_gen7.c:391: error: unknown field 'w' specified in initializer
> > isl_gen7.c:391: warning: missing braces around initializer
> > isl_gen7.c:391: warning: (near initialization for
> > '(anonymous).')
> > isl_gen7.c:392: error: unknown field 'h' specified in initializer
> > isl_gen7.c:393: error: unknown field 'd' specified in initializer
> > *** Error 1 in src/intel/isl (Makefile:744 'libisl_gen7_la-isl_gen7.lo')
> >
>
> At least for the errors you're seeing there, I see two options:  1) Use the
> isl_extentNd constructor functions in isl.h.  2) Stop making isl_extentNd
> have anonymous unions.  I'm not sure how much the anonymous unions are
> really doing for us but I'd like chad to chip in before we throw them out.
>
> Here's another question: I know BSD doesn't ship gcc newer than 4.2 for
> license issues, but do you have a recent

Re: [Mesa-dev] [PATCH] gallivm: make sampling more robust against bogus coordinates

[Cherniak, Bruce]

Tested-by: Bruce Cherniak 





On 4/22/16, 8:33 AM, "mesa-dev on behalf of srol...@vmware.com" 
 wrote:

>From: Roland Scheidegger 
>
>Some cases (especially these using fract for coord wrapping) did not handle
>NaNs (or Infs) correctly - the following code assumed the fract result
>could not be outside [0,1], but if the input is a NaN (or +-Inf) the fract
>result was NaN - which then could produce out-of-bound offsets.
>
>(Note that the explicit NaN behavior changes for min/max on x86 sse don't
>result in actual changes in the generated jit code, but may on other
>architectures. Found by looking through all the wrap functions.)
>
>This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94955
>
>Cc: "11.1 11.2" 
>---
> src/gallium/auxiliary/gallivm/lp_bld_arit.c   |  9 ---
> src/gallium/auxiliary/gallivm/lp_bld_sample_aos.c | 13 -
> src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 33 +--
> 3 files changed, 42 insertions(+), 13 deletions(-)
>
>diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c 
>b/src/gallium/auxiliary/gallivm/lp_bld_arit.c
>index beff414..17cf296 100644
>--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c
>+++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c
>@@ -2069,8 +2069,8 @@ lp_build_fract(struct lp_build_context *bld,
> 
> 
> /**
>- * Prevent returning a fractional part of 1.0 for very small negative values 
>of
>- * 'a' by clamping against 0.9(9).
>+ * Prevent returning 1.0 for very small negative values of 'a' by clamping
>+ * against 0.9(9). (Will also return that value for NaNs.)
>  */
> static inline LLVMValueRef
> clamp_fract(struct lp_build_context *bld, LLVMValueRef fract)
>@@ -2080,13 +2080,14 @@ clamp_fract(struct lp_build_context *bld, LLVMValueRef 
>fract)
>/* this is the largest number smaller than 1.0 representable as float */
>max = lp_build_const_vec(bld->gallivm, bld->type,
> 1.0 - 1.0/(1LL << (lp_mantissa(bld->type) + 1)));
>-   return lp_build_min(bld, fract, max);
>+   return lp_build_min_ext(bld, fract, max,
>+   GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN);
> }
> 
> 
> /**
>  * Same as lp_build_fract, but guarantees that the result is always smaller
>- * than one.
>+ * than one. Will also return the smaller-than-one value for infs, NaNs.
>  */
> LLVMValueRef
> lp_build_fract_safe(struct lp_build_context *bld,
>diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_aos.c 
>b/src/gallium/auxiliary/gallivm/lp_bld_sample_aos.c
>index 729c5b8..6bf92c8 100644
>--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_aos.c
>+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_aos.c
>@@ -246,6 +246,12 @@ lp_build_coord_repeat_npot_linear_int(struct 
>lp_build_sample_context *bld,
>mask = lp_build_compare(int_coord_bld->gallivm, int_coord_bld->type,
>PIPE_FUNC_LESS, *coord0_i, int_coord_bld->zero);
>*coord0_i = lp_build_select(int_coord_bld, mask, length_minus_one, 
> *coord0_i);
>+   /*
>+* We should never get values too large - except if coord was nan or inf,
>+* in which case things go terribly wrong...
>+* Alternatively, could use fract_safe above...
>+*/
>+   *coord0_i = lp_build_min(int_coord_bld, *coord0_i, length_minus_one);
> }
> 
> 
>@@ -490,6 +496,10 @@ lp_build_sample_wrap_linear_float(struct 
>lp_build_sample_context *bld,
>  *coord1 = lp_build_add(coord_bld, coord, half);
>  coord = lp_build_sub(coord_bld, coord, half);
>  *weight = lp_build_fract(coord_bld, coord);
>+ /*
>+  * It is important for this comparison to be unordered
>+  * (or need fract_safe above).
>+  */
>  mask = lp_build_compare(coord_bld->gallivm, coord_bld->type,
>  PIPE_FUNC_LESS, coord, coord_bld->zero);
>  *coord0 = lp_build_select(coord_bld, mask, length_minus_one, coord);
>@@ -514,7 +524,8 @@ lp_build_sample_wrap_linear_float(struct 
>lp_build_sample_context *bld,
>  coord = lp_build_sub(coord_bld, coord, half);
>   }
>   /* clamp to [0, length - 1] */
>-  coord = lp_build_min(coord_bld, coord, length_minus_one);
>+  coord = lp_build_min_ext(coord_bld, coord, length_minus_one,
>+   GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN);
>   coord = lp_build_max(coord_bld, coord, coord_bld->zero);
>   *coord1 = lp_build_add(coord_bld, coord, coord_bld->one);
>   /* convert to int, compute lerp weight */
>diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c 
>b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
>index 1727105..ace24fd 100644
>--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
>+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
>@@ -228,11 +228,15 @@ lp_build_coord_mirror(struct lp_build_sample_context 
>*bld,
>LLVMValueRef fract, flr, isOdd;
> 
>lp_build_ifloor_fract(coord_bld, coord, &flr, &fract);
>+   /* kill off NaNs */
>+   fract = lp_build_

Re: [Mesa-dev] [v2] i965/blorp: State emission optimizations

[Kenneth Graunke]

On Friday, April 22, 2016 9:05:22 PM PDT Topi Pohjolainen wrote:
> Ken came up with an idea to introduce new state flag for blorp and
> to use it instead of trashing all the other bits. This series
> introduces the flag and makes every atom to track it by default.
> Finally blorp is made to track base state address and urb setup
> allowing one to skip unnecessary re-emissions.
> 
> Kenneth Graunke (1):
>   i965: Make all atoms to track BRW_NEW_BLORP by default
> 
> Topi Pohjolainen (6):
>   i965: Remove pointers to non-existing atoms
>   i965/blorp/gen6: Use normal base state address setup
>   i965: Introduce state flag for blorp
>   i965/blorp: Use BRW_NEW_BLORP instead of trashing all state bits
>   i965/blorp: Reconfigure base state address only if needed
>   i965/blorp: Do not tricker re-emission of base state address

A few other atoms that could drop BRW_NEW_BLORP safely:

- brw_polygon_stipple
- brw_polygon_stipple_offset
- brw_line_stipple
- brw_aa_line_parameters

(these generate huge packets...)

- gen6_clip_vp
- gen6_sf_vp
- gen7_sf_clip_viewport
- gen8_sf_clip_viewport

- gen6_scissor_state

- gen7_push_constant_space - probably?

I think we might also be able to drop it on brw_*_pull_constants and
brw_*_surfaces.  But I haven't looked closely enough to tell for sure.



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Re: [Mesa-dev] [PATCH 1/4] gallium: add bool return to pipe_context::end_query

[Roland Scheidegger]

Am 22.04.2016 um 19:28 schrieb Nicolai Hähnle:
> On 22.04.2016 11:52, Roland Scheidegger wrote:
>> Am 22.04.2016 um 18:22 schrieb Nicolai Hähnle:
>>> On 22.04.2016 08:56, Roland Scheidegger wrote:
 I don't quite understand why this is necessary.
 Couldn't you just handle such failures in the driver easily?
>>>
>>> How? When we need a new query buffer due to command buffer flush, and
>>> that buffer allocation fails, there's no easy way out (that still
>>> produces correct results). I suppose we could try to stall everything,
>>> store results so far off to the side on the CPU, and then try to
>>> continue by re-using the already allocated buffer.
>>
>> But if you couldn't end the query due to this failure, how are you going
>> to return correct results anyway?
> 
> We're not going to return correct results, but we tell the application
> about it by signaling GL_OUT_OF_MEMORY.

Ah ok. Please mention that in the commit message it's just done so state
trackers can return an error.

Reviewed-by: Roland Scheidegger 

> 
>> That's what I don't understand. I
>> don't think the gl error will really help an app much.
>> There's likely more functions which potentially do allocation as a side
>> effect somewhere in the driver, and we don't really care about that
>> neither.
> 
> Quite likely, but IMO that's a bad thing. We should follow the spec
> unless there are _very_ good reasons not to.

I think the problem is that it's literally impossible to tell if a
function is going to trigger allocations in a driver, thus would have to
add that to just about every function.

Roland

> Cheers,
> Nicolai
> 
>>
>> Roland
>>
>>
>>
>>>
>>> But that seems like an awful lot of work + a lot of code that won't
>>> really ever be tested for handling what is an out of memory condition
>>> that will soon lead to failures elsewhere anyway.
>>>
>>> Nicolai
>>>
 I can't
 quite see why informing the state tracker of it really helps.

 Roland

 Am 20.04.2016 um 17:43 schrieb Nicolai Hähnle:
> From: Nicolai Hähnle 
>
> Even when begin_query succeeds, there can still be failures in query
> handling.
> For example for radeon, additional buffers may have to be allocated
> when
> queries span multiple command buffers.
> ---
>src/gallium/drivers/ddebug/dd_context.c | 4 ++--
>src/gallium/drivers/freedreno/freedreno_query.c | 3 ++-
>src/gallium/drivers/i915/i915_query.c   | 3 ++-
>src/gallium/drivers/ilo/ilo_query.c | 6 --
>src/gallium/drivers/llvmpipe/lp_query.c | 4 +++-
>src/gallium/drivers/noop/noop_pipe.c| 3 ++-
>src/gallium/drivers/nouveau/nv30/nv30_query.c   | 3 ++-
>src/gallium/drivers/nouveau/nv50/nv50_query.c   | 3 ++-
>src/gallium/drivers/nouveau/nvc0/nvc0_query.c   | 3 ++-
>src/gallium/drivers/r300/r300_query.c   | 8 +---
>src/gallium/drivers/radeon/r600_query.c | 3 ++-
>src/gallium/drivers/rbug/rbug_context.c | 9 ++---
>src/gallium/drivers/softpipe/sp_query.c | 3 ++-
>src/gallium/drivers/svga/svga_pipe_query.c  | 3 ++-
>src/gallium/drivers/swr/swr_query.cpp   | 3 ++-
>src/gallium/drivers/trace/tr_context.c  | 6 --
>src/gallium/drivers/vc4/vc4_query.c | 3 ++-
>src/gallium/drivers/virgl/virgl_query.c | 3 ++-
>src/gallium/include/pipe/p_context.h| 2 +-
>19 files changed, 49 insertions(+), 26 deletions(-)
>
> diff --git a/src/gallium/drivers/ddebug/dd_context.c
> b/src/gallium/drivers/ddebug/dd_context.c
> index 72a950a..d06efbc 100644
> --- a/src/gallium/drivers/ddebug/dd_context.c
> +++ b/src/gallium/drivers/ddebug/dd_context.c
> @@ -104,13 +104,13 @@ dd_context_begin_query(struct pipe_context
> *_pipe, struct pipe_query *query)
>   return pipe->begin_query(pipe, dd_query_unwrap(query));
>}
>
> -static void
> +static bool
>dd_context_end_query(struct pipe_context *_pipe, struct pipe_query
> *query)
>{
>   struct dd_context *dctx = dd_context(_pipe);
>   struct pipe_context *pipe = dctx->pipe;
>
> -   pipe->end_query(pipe, dd_query_unwrap(query));
> +   return pipe->end_query(pipe, dd_query_unwrap(query));
>}
>
>static boolean
> diff --git a/src/gallium/drivers/freedreno/freedreno_query.c
> b/src/gallium/drivers/freedreno/freedreno_query.c
> index a942705..18e0c79 100644
> --- a/src/gallium/drivers/freedreno/freedreno_query.c
> +++ b/src/gallium/drivers/freedreno/freedreno_query.c
> @@ -66,11 +66,12 @@ fd_begin_query(struct pipe_context *pctx, struct
> pipe_query *pq)
>return q->funcs->begin_query(fd_context(pctx), q);
>}
>
> -static void
> +static bool
>fd_end_query(struct pipe_co

Re: [Mesa-dev] [v2 3/7] i965: Introduce state flag for blorp

[Kenneth Graunke]

On Friday, April 22, 2016 9:05:25 PM PDT Topi Pohjolainen wrote:
> CC: Kenneth Graunke 
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_context.h  | 2 ++
>  src/mesa/drivers/dri/i965/brw_state_upload.c | 1 +
>  2 files changed, 3 insertions(+)

Here's a bit more commit message:

In the past, BLORP has clobbered all BRW_NEW_* state flags, to trigger
re-emission of the entire 3D pipeline on the next draw.  However, there
are some packets BLORP simply leaves alone, so there's no need to
re-emit them.  Trying to reduce the set of dirty bits flagged after
BLORP runs is tricky.

Instead, we introduce a BRW_NEW_BLORP flag.  This should be set on any
atom which emits a packet that BLORP also emits.  When BLORP runs, it
will flag BRW_NEW_BLORP, causing those packets to get re-emitted.

This also makes it easy to avoid re-emitting specific atoms - we can
simply drop the BRW_NEW_BLORP flag on those.

To start, we assume that all packets need to be re-emitted.  This is the
safest approach and closest to the existing code's behavior.  Many of
these are obviously not required, and can be dropped in subsequent
patches.

Signed-off-by: Topi Pohjolainen 
Signed-off-by: Kenneth Graunke 

Series is:
Reviewed-by: Kenneth Graunke 

> diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/
i965/brw_context.h
> index 39c3d91..e449982 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -222,6 +222,7 @@ enum brw_state_id {
> BRW_STATE_CS_WORK_GROUPS,
> BRW_STATE_URB_SIZE,
> BRW_STATE_CC_STATE,
> +   BRW_STATE_BLORP,
> BRW_NUM_STATE_BITS
>  };
>  
> @@ -311,6 +312,7 @@ enum brw_state_id {
>  #define BRW_NEW_CS_WORK_GROUPS  (1ull << BRW_STATE_CS_WORK_GROUPS)
>  #define BRW_NEW_URB_SIZE(1ull << BRW_STATE_URB_SIZE)
>  #define BRW_NEW_CC_STATE(1ull << BRW_STATE_CC_STATE)
> +#define BRW_NEW_BLORP   (1ull << BRW_STATE_BLORP)
>  
>  struct brw_state_flags {
> /** State update flags signalled by mesa internals */
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/
drivers/dri/i965/brw_state_upload.c
> index a91d074..56bb95c 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -667,6 +667,7 @@ static struct dirty_bit_map brw_bits[] = {
> DEFINE_BIT(BRW_NEW_CS_WORK_GROUPS),
> DEFINE_BIT(BRW_NEW_URB_SIZE),
> DEFINE_BIT(BRW_NEW_CC_STATE),
> +   DEFINE_BIT(BRW_NEW_BLORP),
> {0, 0, 0}
>  };
>  
> 



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Re: [Mesa-dev] [PATCH] vid_enc: Fix resource leak on OMX_ErrorNone

[Emil Velikov]

On 21 April 2016 at 22:49,   wrote:
> From: Robert Foss 
>
> Avoid leaking buffer allocated for task if an
> error has occured.
>
s|vid_env|st/omx| in the commit message and s|occured|occurred| in the message.

> Coverity id: 1213929
> Signed-off-by: Robert Foss 
Reviewed-by: Emil Velikov 

I'll amend the above and push this shortly.

Thanks
Emil
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Re: [Mesa-dev] [PATCH 4/4] gbm: Add map/unmap functions

[Eric Anholt]

Rob Herring  writes:

> This adds map and unmap functions to GBM utilizing the DRIimage extension
> mapImage/unmapImage functions or existing internal mapping for dumb
> buffers. Unlike prior attempts, this version provides a region to map and
> usage flags for the mapping. The operation follows the same semantics as
> the gallium transfer_map() function.
>
> This was tested with GBM based gralloc on Android.
>
> This still creates a context, but I've moved it into gbm_create_device
> rather than in the map function. This should remove any need for reference
> counting and problems with memory leaks.
>
> Signed-off-by: Rob Herring 



> @@ -981,6 +1033,8 @@ dri_device_create(int fd)
> dri->base.base.fd = fd;
> dri->base.base.bo_create = gbm_dri_bo_create;
> dri->base.base.bo_import = gbm_dri_bo_import;
> +   dri->base.base.bo_map = gbm_dri_bo_map;
> +   dri->base.base.bo_unmap = gbm_dri_bo_unmap;
> dri->base.base.is_format_supported = gbm_dri_is_format_supported;
> dri->base.base.bo_write = gbm_dri_bo_write;
> dri->base.base.bo_get_fd = gbm_dri_bo_get_fd;
> @@ -1004,6 +1058,10 @@ dri_device_create(int fd)
> if (ret)
>goto err_dri;
>  
> +   if (dri->image->base.version >= 12)
> +  dri->context = dri->dri2->createNewContext(dri->screen, NULL,
> + NULL, NULL);
> +
> return &dri->base.base;

I don't think we want to always make a spare context just in case
someone uses the map API.  Contexts can be pretty expensive to set up,
in time (for piglit tests on gbm) and memory (for X.Org).

It's too bad I don't think we have a way to get the existing
__DRIcontext from EGL to pass as an arg to map/unmap here, which could
be nice for glamor.

> diff --git a/src/gbm/main/gbm.c b/src/gbm/main/gbm.c
> index c046b1a..0f70bbd 100644
> --- a/src/gbm/main/gbm.c
> +++ b/src/gbm/main/gbm.c
> @@ -386,6 +386,57 @@ gbm_bo_import(struct gbm_device *gbm,
>  }
>  
>  /**
> + * Map a region of a gbm buffer object for cpu access
> + *
> + * This function maps a region of a gbm bo for cpu read and/or write
> + * access.
> + *
> + * \param bo The buffer object
> + * \param x The X starting position of the mapped region for the buffer
> + * \param y The Y starting position of the mapped region for the buffer
> + * \param width The width of the mapped region for the buffer
> + * \param height The height of the mapped region for the buffer
> + * \param flags The union of the usage flags for this buffer

This should probably say at least "transfer flags", or even better "the
union of the GBM_BO_TRANSFER_* flags" to help people grep.

> + * \param stride Returned stride in bytes of the mapped region.
> + * \param map_data Returned opaque ptr for the mapped region
> + *
> + * \return Address of the mapped buffer
> + * gbm_bo_unmap() when no longer needed. On error, %NULL is returned
> + * and errno is set.
> + *
> + * \sa enum gbm_bo_transfer_flags for the list of flags
> + */
> +GBM_EXPORT void *
> +gbm_bo_map(struct gbm_bo *bo,
> +  uint32_t x, uint32_t y,
> +  uint32_t width, uint32_t height,
> +  uint32_t flags, uint32_t *stride, void **map_data)
> +{
> +   if (!bo || width == 0 || height == 0 || !stride || !map_data) {
> +  errno = EINVAL;
> +  return NULL;
> +   }
> +
> +   return bo->gbm->bo_map(bo, x, y, width, height,
> +  flags, stride, map_data);
> +}



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Re: [Mesa-dev] [PATCH 01/13] i965: Add a dependency on libisl

[Chad Versace]

On 04/22/2016 10:50 AM, Jason Ekstrand wrote:
> 
> 
> On Fri, Apr 22, 2016 at 10:15 AM, Jonathan Gray  > wrote:
> 
> On Fri, Apr 22, 2016 at 05:31:29PM +0100, Emil Velikov wrote:
>> On 22 April 2016 at 16:08, Jonathan Gray > > wrote:
>>> It is worth noting that the isl code extensively requires
>>> designated initialisers on anonymous structs.  It isn't clear to
>>> me when gcc introduced support for this but it isn't in 4.2.
>>> 
>> I think it should work for GCC 4.2 with -fms-extensions. We used
>> to set -std=gnu99 for pre 4.6 which effectively enables it the
>> extension. Can you double-check ?
> 
> The part that sets gnu99 for < gcc 4.6 is still there, using
> -fms-extensions does not help for these. 


> At least for the errors you're seeing there, I see two options:  1)
> Use the isl_extentNd constructor functions in isl.h.  2) Stop making
> isl_extentNd have anonymous unions.  I'm not sure how much the
> anonymous unions are really doing for us but I'd like chad to chip in
> before we throw them out.

I like the anonymous unions because they make some equations more concise.
But, they don't provide anymore than that. I'll accept patches to remove
them, as other people have also commented on their awkwardness.
 
> Here's another question: I know BSD doesn't ship gcc newer than 4.2
> for license issues, but do you have a recent version of clang
> available?

GCC 4.2 was released in 2007, and BSD won't upgrade it due to GPLv3.
I believe it's unreasonable to promise Mesa will indefinitely restrict
all new code to the feature set provided by a 2007-era GCC. As the years
roll by, such a promise would become untenable.

Please try clang.

>>> Would you accept patches to remove them?
>> While I cannot comment if they're OK with the idea, there might be 
>> some confusion on the topic. There is anonymous and named. I
>> believe developers were against the latter. Examples form [1]
>> 
>> struct bar { int i; }; // (1) unnamed, but tagged, ie *not*
>> anonymous struct { int j; }; // (2) unnamed, but anonymous 
>> struct { int k; } baz; // (3) named, but not tagged
>> 
>> Fwiw it would be great to use the more portable solution. Would
>> C11 buy us anything ?

I believe that C11 does fix the problem. It standardized anonymous unions and 
structs.
However, if we need to support GCC 4.2, then we can't use C11. In fact, GCC's 
C11 support
is still incomplete as 5.0. I've discovered serious bugs as recently as GCC 4.9.

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Re: [Mesa-dev] [PATCH 3/4] st/dri: Add support for DRIimage extension mapImage/unmapImage

[Eric Anholt]

Rob Herring  writes:

> Implement support for mapImage/unmapImage functions in version 12 of the
> DRIimage extension.
>
> Signed-off-by: Rob Herring 

This looks good to me, other than my previous comment about looking at
the read flag.  Once we sort that out, I'll be ready to give r-b.


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Re: [Mesa-dev] [PATCH 2/4] DRI: Add DRIimage map and unmap functions

[Eric Anholt]

Rob Herring  writes:

> Add mapImage and unmapImage functions to DRIimage extension for mapping
> and unmapping DRIimages for CPU access. The caller provides the region of
> the image to map and is returned a pointer to the beginning of the region
> and the stride (which could be different from the original).
>
> Signed-off-by: Rob Herring 
> ---
>  include/GL/internal/dri_interface.h | 24 +++-
>  1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/include/GL/internal/dri_interface.h 
> b/include/GL/internal/dri_interface.h
> index b38f87f..082dc10 100644
> --- a/include/GL/internal/dri_interface.h
> +++ b/include/GL/internal/dri_interface.h
> @@ -1094,7 +1094,7 @@ struct __DRIdri2ExtensionRec {
>   * extensions.
>   */
>  #define __DRI_IMAGE "DRI_IMAGE"
> -#define __DRI_IMAGE_VERSION 11
> +#define __DRI_IMAGE_VERSION 12
>  
>  /**
>   * These formats correspond to the similarly named MESA_FORMAT_*
> @@ -1133,6 +1133,11 @@ struct __DRIdri2ExtensionRec {
>  #define __DRI_IMAGE_USE_BACKBUFFER  0x0010
>  
>  
> +#define __DRI_IMAGE_TRANSFER_READ0x1
> +#define __DRI_IMAGE_TRANSFER_WRITE   0x2
> +#define __DRI_IMAGE_TRANSFER_READ_WRITE  \
> +(__DRI_IMAGE_TRANSFER_READ | __DRI_IMAGE_TRANSFER_WRITE)
> +
>  /**
>   * Four CC formats that matches with WL_DRM_FORMAT_* from wayland_drm.h,
>   * GBM_FORMAT_* from gbm.h, and DRM_FORMAT_* from drm_fourcc.h. Used with
> @@ -1381,6 +1386,23 @@ struct __DRIimageExtensionRec {
>  * \since 10
>  */
> int (*getCapabilities)(__DRIscreen *screen);
> +
> +   /**
> +* Map specified region of a __DRIimage for specified usage
> +*
> +* \since 12
> +*/
> +   void *(*mapImage)(__DRIcontext *context, __DRIimage *image,
> + int x0, int y0, int width, int height,
> + unsigned int flags, int *stride, void **data);

I think this needs a longer comment to explain what the interface does:

"Returns a map of the specified region of a __DRIimage for the specified
usage.

flags must always include __DRI_IMAGE_TRANSFER_READ and may include
__DRI_IMAGE_TRANSFER_WRITE if the mapping is written[*].  If
__DRI_IMAGE_TRANSFER_WRITE is not included, behavior when writing the
mapping is undefined.

Returns the byte stride in *stride, and an opaque pointer to data
tracking the mapping in **data, which must be passed to unmapImage()."

I don't know how the READ flag is actually intended to be used, and 3/4
doesn't look at it at all, so it should probably either be used or
deleted.

At some point we may want the other usual mapping flags
(invalidate_buffer/range/unsync), but I think we can bolt those on
afterward when we need them.

> +
> +   /**
> +* Unmap a previously mapped __DRIimage
> +*
> +* \since 12
> +*/
> +   void (*unmapImage)(__DRIcontext *context, __DRIimage *image, void *data);
> +
>  };



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Re: [Mesa-dev] [PATCH 1/3] configure.ac: search for and set PYTHON3

[Kenneth Graunke]

On Saturday, April 23, 2016 1:21:38 AM PDT Jonathan Gray wrote:
> src/intel/genxml/gen_pack_header.py requires python3.
> 
> Signed-off-by: Jonathan Gray 
> ---
>  configure.ac | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/configure.ac b/configure.ac
> index 6b00cf9..9459489 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -99,6 +99,7 @@ AM_PROG_CC_C_O
>  AM_PROG_AS
>  AX_CHECK_GNU_MAKE
>  AC_CHECK_PROGS([PYTHON2], [python2.7 python2 python])
> +AC_CHECK_PROGS([PYTHON3], [python3.4 python3])
>  AC_PROG_SED
>  AC_PROG_MKDIR_P

Why mention python3.4 explicitly?  Are we trying to check for 3.4+?

My system has /usr/bin/python3 -> /usr/bin/python3.5, FWIW...no 3.4.


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Re: [Mesa-dev] [PATCH] i965/blorb: remove dead code in brw_blorp_const_color_program::compile()

[Matt Turner]

On Fri, Apr 22, 2016 at 5:01 AM, Juha-Pekka Heikkila
 wrote:
> base_mrf is unsigned, checking if its greater or equal to zero will
> not fail.

Please s/blorb/blorp/ in the commit title before pushing.
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[Mesa-dev] [v2 4/7] i965: Make all atoms to track BRW_NEW_BLORP by default

[Topi Pohjolainen]

From: Kenneth Graunke 

From: Kenneth Graunke 

Signed-off-by: Topi Pohjolainen https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [v2 7/7] i965/blorp: Do not tricker re-emission of base state address

[Topi Pohjolainen]

In case blorp needs to configure it will be just as if render or
compute pipeline had configured it.

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_misc_state.c  | 1 -
 src/mesa/drivers/dri/i965/gen8_misc_state.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index ae7787c..71a7fdd 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -1173,7 +1173,6 @@ const struct brw_tracked_state brw_state_base_address = {
.dirty = {
   .mesa = 0,
   .brw = BRW_NEW_BATCH |
- BRW_NEW_BLORP |
  BRW_NEW_PROGRAM_CACHE,
},
.emit = upload_state_base_address
diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c 
b/src/mesa/drivers/dri/i965/gen8_misc_state.c
index 13275b3..b20038e 100644
--- a/src/mesa/drivers/dri/i965/gen8_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c
@@ -76,7 +76,6 @@ const struct brw_tracked_state gen8_state_base_address = {
.dirty = {
   .mesa = 0,
   .brw = BRW_NEW_BATCH |
- BRW_NEW_BLORP |
  BRW_NEW_PROGRAM_CACHE,
},
.emit = gen8_upload_state_base_address
-- 
2.5.5

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[Mesa-dev] [v2 6/7] i965/blorp: Reconfigure base state address only if needed

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/gen6_blorp.cpp | 3 ++-
 src/mesa/drivers/dri/i965/gen7_blorp.cpp | 3 ++-
 src/mesa/drivers/dri/i965/gen8_blorp.cpp | 4 +++-
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index cc7cbd5..5c0fa0c 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -989,7 +989,8 @@ gen6_blorp_exec(struct brw_context *brw,
/* Emit workaround flushes when we switch from drawing to blorping. */
brw_emit_post_sync_nonzero_flush(brw);
 
-   brw_state_base_address.emit(brw);
+   if (brw_state_base_address.dirty.brw & brw->ctx.NewDriverState)
+  brw_state_base_address.emit(brw);
 
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_sample_mask(brw,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index a44c186..1520469 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -814,7 +814,8 @@ gen7_blorp_exec(struct brw_context *brw,
 
uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 
-   brw_state_base_address.emit(brw);
+   if (brw_state_base_address.dirty.brw & brw->ctx.NewDriverState)
+  brw_state_base_address.emit(brw);
 
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_sample_mask(brw,
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen8_blorp.cpp
index 1bd9b97..d8ad5ea 100644
--- a/src/mesa/drivers/dri/i965/gen8_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.cpp
@@ -635,7 +635,9 @@ gen8_blorp_exec(struct brw_context *brw, const 
brw_blorp_params *params)
 
uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 
-   gen8_upload_state_base_address(brw);
+   if (gen8_state_base_address.dirty.brw & brw->ctx.NewDriverState)
+  gen8_upload_state_base_address(brw);
+
gen7_blorp_emit_cc_viewport(brw);
gen7_l3_state.emit(brw);
 
-- 
2.5.5

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[Mesa-dev] [v2 5/7] i965/blorp: Use BRW_NEW_BLORP instead of trashing all state bits

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.cpp | 4 +---
 src/mesa/drivers/dri/i965/gen7_urb.c| 3 +--
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index ce09b09..76c9fbe 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -284,12 +284,10 @@ retry:
if (unlikely(brw->always_flush_batch))
   intel_batchbuffer_flush(brw);
 
-   const uint64_t do_not_smash_bits = BRW_NEW_URB_SIZE;
-
/* We've smashed all state compared to what the normal 3D pipeline
 * rendering tracks for GL.
 */
-   brw->ctx.NewDriverState |= ~do_not_smash_bits;
+   brw->ctx.NewDriverState |= BRW_NEW_BLORP;
brw->no_depth_or_stencil = false;
brw->ib.type = -1;
 
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c 
b/src/mesa/drivers/dri/i965/gen7_urb.c
index 3f731df..a412a42 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -418,8 +418,7 @@ gen7_emit_urb_state(struct brw_context *brw,
 const struct brw_tracked_state gen7_urb = {
.dirty = {
   .mesa = 0,
-  .brw = BRW_NEW_BLORP |
- BRW_NEW_CONTEXT |
+  .brw = BRW_NEW_CONTEXT |
  BRW_NEW_URB_SIZE |
  BRW_NEW_GEOMETRY_PROGRAM |
  BRW_NEW_TESS_PROGRAMS |
-- 
2.5.5

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[Mesa-dev] [v2 2/7] i965/blorp/gen6: Use normal base state address setup

[Topi Pohjolainen]

This is identical to the blorp version which only differs in case
fragment shader isn't used. In that case blorp would reset batch
buffer address to zero.
This is not really needed, and having blorp to use base state
address setup that is compatible with normal upload allows one to
skip resetting it.

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.h|  4 ---
 src/mesa/drivers/dri/i965/gen6_blorp.cpp | 51 ++--
 src/mesa/drivers/dri/i965/gen7_blorp.cpp |  4 ++-
 3 files changed, 5 insertions(+), 54 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 79dc59a..5a79710 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -406,10 +406,6 @@ void
 gen6_blorp_init(struct brw_context *brw);
 
 void
-gen6_blorp_emit_state_base_address(struct brw_context *brw,
-   const brw_blorp_params *params);
-
-void
 gen6_blorp_emit_vertices(struct brw_context *brw,
  const brw_blorp_params *params);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index cf30f71..cc7cbd5 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -31,54 +31,6 @@
 
 #include "brw_blorp.h"
 
-/**
- * CMD_STATE_BASE_ADDRESS
- *
- * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS:
- * The following commands must be reissued following any change to the
- * base addresses:
- * 3DSTATE_CC_POINTERS
- * 3DSTATE_BINDING_TABLE_POINTERS
- * 3DSTATE_SAMPLER_STATE_POINTERS
- * 3DSTATE_VIEWPORT_STATE_POINTERS
- * MEDIA_STATE_POINTERS
- */
-void
-gen6_blorp_emit_state_base_address(struct brw_context *brw,
-   const brw_blorp_params *params)
-{
-   uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
-
-   BEGIN_BATCH(10);
-   OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
-   OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */
- mocs << 4 | /* StatelessDataPortAccessMemoryObjectControlState */
- 1); /* GeneralStateBaseAddressModifyEnable */
-
-   /* SurfaceStateBaseAddress */
-   OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
-   /* DynamicStateBaseAddress */
-   OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
-   I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
-   OUT_BATCH(1); /* IndirectObjectBaseAddress */
-   if (params->use_wm_prog) {
-  OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
-1); /* Instruction base address: shader kernels */
-   } else {
-  OUT_BATCH(1); /* InstructionBaseAddress */
-   }
-   OUT_BATCH(1); /* GeneralStateUpperBound */
-   /* Dynamic state upper bound.  Although the documentation says that
-* programming it to zero will cause it to be ignored, that is a lie.
-* If this isn't programmed to a real bound, the sampler border color
-* pointer is rejected, causing border color to mysteriously fail.
-*/
-   OUT_BATCH(0xf001);
-   OUT_BATCH(1); /* IndirectObjectUpperBound*/
-   OUT_BATCH(1); /* InstructionAccessUpperBound */
-   ADVANCE_BATCH();
-}
-
 static void
 gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw,
 unsigned num_elems,
@@ -1037,11 +989,12 @@ gen6_blorp_exec(struct brw_context *brw,
/* Emit workaround flushes when we switch from drawing to blorping. */
brw_emit_post_sync_nonzero_flush(brw);
 
+   brw_state_base_address.emit(brw);
+
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_sample_mask(brw,
  params->dst.num_samples > 1 ?
  (1 << params->dst.num_samples) - 1 : 1);
-   gen6_blorp_emit_state_base_address(brw, params);
gen6_blorp_emit_vertices(brw, params);
gen6_blorp_emit_urb_config(brw, params);
if (params->use_wm_prog) {
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 414ec9c..a44c186 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -813,11 +813,13 @@ gen7_blorp_exec(struct brw_context *brw,
uint32_t wm_bind_bo_offset = 0;
 
uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
+
+   brw_state_base_address.emit(brw);
+
gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
gen6_emit_3dstate_sample_mask(brw,
  params->dst.num_samples > 1 ?
  (1 << params->dst.num_samples) - 1 : 1);
-   gen6_blorp_emit_state_base_address(brw, params);
gen6_blorp_emit_vertices(brw, params);
gen7_blorp_emit_urb_config(brw);
if (params->use_wm_prog) {
-- 
2.5.5

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[Mesa-dev] [v2] i965/blorp: State emission optimizations

[Topi Pohjolainen]

Ken came up with an idea to introduce new state flag for blorp and
to use it instead of trashing all the other bits. This series
introduces the flag and makes every atom to track it by default.
Finally blorp is made to track base state address and urb setup
allowing one to skip unnecessary re-emissions.

Kenneth Graunke (1):
  i965: Make all atoms to track BRW_NEW_BLORP by default

Topi Pohjolainen (6):
  i965: Remove pointers to non-existing atoms
  i965/blorp/gen6: Use normal base state address setup
  i965: Introduce state flag for blorp
  i965/blorp: Use BRW_NEW_BLORP instead of trashing all state bits
  i965/blorp: Reconfigure base state address only if needed
  i965/blorp: Do not tricker re-emission of base state address

 src/mesa/drivers/dri/i965/brw_binding_tables.c | 10 -
 src/mesa/drivers/dri/i965/brw_blorp.cpp|  4 +-
 src/mesa/drivers/dri/i965/brw_blorp.h  |  4 --
 src/mesa/drivers/dri/i965/brw_cc.c |  7 ++-
 src/mesa/drivers/dri/i965/brw_clip.c   |  3 +-
 src/mesa/drivers/dri/i965/brw_clip_state.c |  1 +
 src/mesa/drivers/dri/i965/brw_context.h|  2 +
 src/mesa/drivers/dri/i965/brw_curbe.c  |  2 +
 src/mesa/drivers/dri/i965/brw_draw_upload.c|  5 ++-
 src/mesa/drivers/dri/i965/brw_gs_state.c   |  1 +
 src/mesa/drivers/dri/i965/brw_gs_surface_state.c   |  4 ++
 src/mesa/drivers/dri/i965/brw_interpolation_map.c  |  3 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c | 22 ++---
 src/mesa/drivers/dri/i965/brw_primitive_restart.c  |  3 +-
 src/mesa/drivers/dri/i965/brw_sampler_state.c  |  6 +++
 src/mesa/drivers/dri/i965/brw_sf.c |  3 +-
 src/mesa/drivers/dri/i965/brw_sf_state.c   |  4 +-
 src/mesa/drivers/dri/i965/brw_state.h  |  8 
 src/mesa/drivers/dri/i965/brw_state_upload.c   |  1 +
 src/mesa/drivers/dri/i965/brw_tcs_surface_state.c  |  4 ++
 src/mesa/drivers/dri/i965/brw_tes_surface_state.c  |  4 ++
 src/mesa/drivers/dri/i965/brw_urb.c|  3 +-
 src/mesa/drivers/dri/i965/brw_vs_state.c   |  1 +
 src/mesa/drivers/dri/i965/brw_vs_surface_state.c   |  4 ++
 src/mesa/drivers/dri/i965/brw_wm_state.c   |  1 +
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c   | 16 ++-
 src/mesa/drivers/dri/i965/gen6_blorp.cpp   | 52 ++
 src/mesa/drivers/dri/i965/gen6_cc.c|  2 +
 src/mesa/drivers/dri/i965/gen6_clip_state.c|  6 ++-
 src/mesa/drivers/dri/i965/gen6_depthstencil.c  |  1 +
 src/mesa/drivers/dri/i965/gen6_gs_state.c  |  2 +
 src/mesa/drivers/dri/i965/gen6_multisample_state.c |  3 +-
 src/mesa/drivers/dri/i965/gen6_sampler_state.c |  1 +
 src/mesa/drivers/dri/i965/gen6_scissor_state.c |  3 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c  |  3 +-
 src/mesa/drivers/dri/i965/gen6_sol.c   |  2 +
 src/mesa/drivers/dri/i965/gen6_urb.c   |  3 +-
 src/mesa/drivers/dri/i965/gen6_viewport_state.c|  7 ++-
 src/mesa/drivers/dri/i965/gen6_vs_state.c  |  2 +
 src/mesa/drivers/dri/i965/gen6_wm_state.c  |  2 +
 src/mesa/drivers/dri/i965/gen7_blorp.cpp   |  5 ++-
 src/mesa/drivers/dri/i965/gen7_cs_state.c  |  3 ++
 src/mesa/drivers/dri/i965/gen7_ds_state.c  |  2 +
 src/mesa/drivers/dri/i965/gen7_gs_state.c  |  1 +
 src/mesa/drivers/dri/i965/gen7_hs_state.c  |  2 +
 src/mesa/drivers/dri/i965/gen7_l3_state.c  |  1 +
 src/mesa/drivers/dri/i965/gen7_misc_state.c|  3 +-
 src/mesa/drivers/dri/i965/gen7_sf_state.c  |  6 ++-
 src/mesa/drivers/dri/i965/gen7_sol_state.c |  1 +
 src/mesa/drivers/dri/i965/gen7_te_state.c  |  3 +-
 src/mesa/drivers/dri/i965/gen7_urb.c   |  3 +-
 src/mesa/drivers/dri/i965/gen7_viewport_state.c|  3 +-
 src/mesa/drivers/dri/i965/gen7_vs_state.c  |  1 +
 src/mesa/drivers/dri/i965/gen7_wm_state.c  |  2 +
 src/mesa/drivers/dri/i965/gen8_blend_state.c   |  4 +-
 src/mesa/drivers/dri/i965/gen8_blorp.cpp   |  4 +-
 src/mesa/drivers/dri/i965/gen8_depth_state.c   |  3 +-
 src/mesa/drivers/dri/i965/gen8_disable.c   |  3 +-
 src/mesa/drivers/dri/i965/gen8_draw_upload.c   |  5 ++-
 src/mesa/drivers/dri/i965/gen8_ds_state.c  |  1 +
 src/mesa/drivers/dri/i965/gen8_gs_state.c  |  1 +
 src/mesa/drivers/dri/i965/gen8_hs_state.c  |  1 +
 src/mesa/drivers/dri/i965/gen8_multisample_state.c |  3 +-
 src/mesa/drivers/dri/i965/gen8_ps_state.c  |  7 ++-
 src/mesa/drivers/dri/i965/gen8_sf_state.c  |  9 ++--
 src/mesa/drivers/dri/i965/gen8_sol_state.c |  1 +
 src/mesa/drivers/dri/i965/gen8_viewport_state.c|  3 +-
 src/mesa/drivers/dri/i965/gen8_vs_state.c  |  1 +
 src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c  |  3 +-
 69 files changed, 189 insertions(+), 111 deletions(-)

-- 
2.5.5

[Mesa-dev] [v2 3/7] i965: Introduce state flag for blorp

[Topi Pohjolainen]

CC: Kenneth Graunke 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_context.h  | 2 ++
 src/mesa/drivers/dri/i965/brw_state_upload.c | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 39c3d91..e449982 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -222,6 +222,7 @@ enum brw_state_id {
BRW_STATE_CS_WORK_GROUPS,
BRW_STATE_URB_SIZE,
BRW_STATE_CC_STATE,
+   BRW_STATE_BLORP,
BRW_NUM_STATE_BITS
 };
 
@@ -311,6 +312,7 @@ enum brw_state_id {
 #define BRW_NEW_CS_WORK_GROUPS  (1ull << BRW_STATE_CS_WORK_GROUPS)
 #define BRW_NEW_URB_SIZE(1ull << BRW_STATE_URB_SIZE)
 #define BRW_NEW_CC_STATE(1ull << BRW_STATE_CC_STATE)
+#define BRW_NEW_BLORP   (1ull << BRW_STATE_BLORP)
 
 struct brw_state_flags {
/** State update flags signalled by mesa internals */
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index a91d074..56bb95c 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -667,6 +667,7 @@ static struct dirty_bit_map brw_bits[] = {
DEFINE_BIT(BRW_NEW_CS_WORK_GROUPS),
DEFINE_BIT(BRW_NEW_URB_SIZE),
DEFINE_BIT(BRW_NEW_CC_STATE),
+   DEFINE_BIT(BRW_NEW_BLORP),
{0, 0, 0}
 };
 
-- 
2.5.5

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[Mesa-dev] [v2 1/7] i965: Remove pointers to non-existing atoms

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_state.h | 8 
 1 file changed, 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 9f15326..e89b388 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -57,7 +57,6 @@ extern const struct brw_tracked_state brw_constant_buffer;
 extern const struct brw_tracked_state brw_curbe_offsets;
 extern const struct brw_tracked_state brw_invariant_state;
 extern const struct brw_tracked_state brw_fs_samplers;
-extern const struct brw_tracked_state brw_ff_gs_prog;
 extern const struct brw_tracked_state brw_gs_unit;
 extern const struct brw_tracked_state brw_line_stipple;
 extern const struct brw_tracked_state brw_aa_line_parameters;
@@ -70,8 +69,6 @@ extern const struct brw_tracked_state brw_sf_prog;
 extern const struct brw_tracked_state brw_sf_unit;
 extern const struct brw_tracked_state brw_sf_vp;
 extern const struct brw_tracked_state brw_state_base_address;
-extern const struct brw_tracked_state brw_urb_fence;
-extern const struct brw_tracked_state brw_vs_prog;
 extern const struct brw_tracked_state brw_vs_samplers;
 extern const struct brw_tracked_state brw_tcs_samplers;
 extern const struct brw_tracked_state brw_tes_samplers;
@@ -91,10 +88,6 @@ extern const struct brw_tracked_state brw_gs_ubo_surfaces;
 extern const struct brw_tracked_state brw_gs_abo_surfaces;
 extern const struct brw_tracked_state brw_gs_image_surfaces;
 extern const struct brw_tracked_state brw_vs_unit;
-extern const struct brw_tracked_state brw_hs_prog;
-extern const struct brw_tracked_state brw_ds_prog;
-extern const struct brw_tracked_state brw_gs_prog;
-extern const struct brw_tracked_state brw_wm_prog;
 extern const struct brw_tracked_state brw_renderbuffer_surfaces;
 extern const struct brw_tracked_state brw_texture_surfaces;
 extern const struct brw_tracked_state brw_wm_binding_table;
@@ -121,7 +114,6 @@ extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_blend_state;
-extern const struct brw_tracked_state gen6_cc_state_pointers;
 extern const struct brw_tracked_state gen6_clip_state;
 extern const struct brw_tracked_state gen6_clip_vp;
 extern const struct brw_tracked_state gen6_color_calc_state;
-- 
2.5.5

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Re: [Mesa-dev] [PATCH v2 03/25] anv: tweak the %.json rule

[Emil Velikov]

On 22 April 2016 at 18:58, Jason Ekstrand  wrote:
> I'm not sure what I think of this.  I don't think dev_icd is the only icd
> file we're going to need to build.  Right now, we don't build the regular
> ICD but I think we want to eventually in which case having a general rule is
> a good thing.
>
How about we revert the patch when/if that happens ?

-Emil
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Re: [Mesa-dev] [PATCH 20/25] anv: minor tweak in the generation script

[Emil Velikov]

On 22 April 2016 at 18:52, Jason Ekstrand  wrote:
> On Fri, Apr 22, 2016 at 10:27 AM, Emil Velikov 
> wrote:
>>
>> On 22 April 2016 at 04:36, Kristian Høgsberg  wrote:
>> > On Thu, Apr 21, 2016 at 5:18 PM, Emil Velikov 
>> > wrote:
>> >> On 21 April 2016 at 22:50, Jason Ekstrand  wrote:
>> >>> On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov
>> >>> 
>> >>> wrote:
>> 
>>  From: Emil Velikov 
>> 
>>  Rather than parsing through the same files (public headers) twice,
>>  tweak
>>  the python script to create both files at the same time.
>> >>>
>> >>>
>> >>> Yes, but it takes almost zero time to generate them and it's going to
>> >>> run in
>> >>> parallel before anything else gets built.  I don't know that this
>> >>> really
>> >>> saves us anything.
>> >>>
>> >> Are you sure about this one? Based on my brief testing - things were
>> >> pretty much stalled until both files were generated. I'll take another
>> >> look.
>> >>
>> >> If anything the approach cuts down the bash output redirection and
>> >> some nasty handling around it.
>> >> Talking about the following $(PYHON)   > $@ || ($(RM) $@; false)
>> >> and how often we forget to add it.
>> >>
>> Things get stalled for all the sources to be generated before proceeding
>> with
>> the compilation. Thus there isn't much benefit with the current approach
>> afaict.
>
>
> Yes, but if they run in parallel (which they will on *any* modern machine),
> then it only takes as long as the longest one takes to run.  I don't think
> it's actually helping anything to do them both with one python invocation
> except for the make -j1 case.
>
Which afaict does not make any difference, as the overhead of starting
a second instance mitigates any benefits. Also there is the makefile
simplification/bugfix.

-Emil
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Re: [Mesa-dev] [PATCH 2/2] i965/blorp: Fix clear code for ignoring colormask for XRGB formats on Gen9+

[Kenneth Graunke]

On Friday, April 22, 2016 11:49:03 AM PDT Topi Pohjolainen wrote:
> This is equivalent of 73b01e2711ff45a1f313d5372d6c8fa4fe55d4d2
> for blorp.
> 
> CC: Iago Toral Quiroga 
> CC: Kenneth Graunke 
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 36 
+--
>  1 file changed, 29 insertions(+), 7 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/
drivers/dri/i965/brw_blorp_clear.cpp
> index 41ff2a5..f4513be 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> @@ -25,6 +25,7 @@
>  #include "main/blend.h"
>  #include "main/fbobject.h"
>  #include "main/renderbuffer.h"
> +#include "main/glformats.h"
>  
>  #include "util/ralloc.h"
>  
> @@ -135,6 +136,32 @@ 
brw_blorp_const_color_program::~brw_blorp_const_color_program()
> ralloc_free(mem_ctx);
>  }
>  
> +static bool
> +set_write_disables(const struct intel_renderbuffer *irb, 
> +   const GLubyte *color_mask, bool *color_write_disable)
> +{
> +   /* Format information in the renderbuffer represents the requirements
> +* given by the client. There are cases where the backing miptree uses,
> +* for example, RGBA to represent RGBX. Since the client is only 
expecting
> +* RGB we can treat alpha as not used and write whatever we like into 
it.
> +*/
> +   const GLenum base_format = irb->Base.Base._BaseFormat;
> +   const mesa_format format = irb->mt->format;
> +   const int components = _mesa_base_format_component_count(base_format);
> +   bool disables = false;
> +
> +   assert(components > 0);
> +
> +   for (int i = 0; i < components; i++) {
> + if (_mesa_format_has_color_component(format, i) && !color_mask[i]) {

I think the _mesa_format_has_color_component() stuff shouldn't be
necessary now that we're doing the equivalent thing with _BaseFormat.

So you could probably simplify this to:

  if (!color_mask[i]) {

Either way, series is:
Reviewed-by: Kenneth Graunke 

It might also be nice to set the remaining color_write_disable[i] flags
to false explicitly here - they're set in the constructor, but this
would consolidate that logic.  *shrug*

> + color_write_disable[i] = true;
> + disables = true;
> +  }
> +   }
> +
> +   return disables;
> +}
> +
>  brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
> struct gl_framebuffer *fb,
> struct gl_renderbuffer *rb,
> @@ -185,13 +212,8 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct 
brw_context *brw,
> /* Constant color writes ignore everyting in blend and color calculator
>  * state.  This is not documented.
>  */
> -   for (int i = 0; i < 4; i++) {
> -  if (_mesa_format_has_color_component(irb->mt->format, i) &&
> -  !color_mask[i]) {
> - color_write_disable[i] = true;
> - wm_prog_key.use_simd16_replicated_data = false;
> -  }
> -   }
> +   if (set_write_disables(irb, color_mask, color_write_disable))
> +  wm_prog_key.use_simd16_replicated_data = false;
>  
> if (irb->mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS &&
> !partial_clear && wm_prog_key.use_simd16_replicated_data &&
> 



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Re: [Mesa-dev] [PATCH v2 03/25] anv: tweak the %.json rule

[Jason Ekstrand]

I'm not sure what I think of this.  I don't think dev_icd is the only icd
file we're going to need to build.  Right now, we don't build the regular
ICD but I think we want to eventually in which case having a general rule
is a good thing.

On Fri, Apr 22, 2016 at 11:55 AM, Emil Velikov 
wrote:

> From: Emil Velikov 
>
> It's used only by dev_icd.json so just call it that way. While we're
> here, manually expand $< (as it might cause issue on some systems)
> and drop the unneeded install_libdir substitution.
>
> Cc: Jason Ekstrand 
> Signed-off-by: Emil Velikov 
> ---
> This commit replaces "anv: remove no longer needed %.json rule"
> ---
>  src/intel/vulkan/Makefile.am | 7 +++
>  1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
> index 916f171..6d93906 100644
> --- a/src/intel/vulkan/Makefile.am
> +++ b/src/intel/vulkan/Makefile.am
> @@ -190,11 +190,10 @@ icdconf_DATA = intel_icd.json
>  # The following is used for development purposes, by setting
> VK_ICD_FILENAMES.
>  noinst_DATA = dev_icd.json
>
> -%.json : %.json.in
> +dev_icd.json : dev_icd.json.in
> $(AM_V_GEN) $(SED) \
> -   -e "s#@build_libdir@#${abs_top_builddir}/${LIB_DIR}#" \
> -   -e "s#@install_libdir@#${libdir}#" < $< > $@
> -
> +   -e "s#@build_libdir@#${abs_top_builddir}/${LIB_DIR}#"
> +   < $(srcdir)/dev_icd.json.in > $@
>
>  # Libvulkan with dummy gem. Used for unit tests.
>
> --
> 2.8.0
>
>
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[Mesa-dev] [PATCH v2 03/25] anv: tweak the %.json rule

[Emil Velikov]

From: Emil Velikov 

It's used only by dev_icd.json so just call it that way. While we're
here, manually expand $< (as it might cause issue on some systems)
and drop the unneeded install_libdir substitution.

Cc: Jason Ekstrand 
Signed-off-by: Emil Velikov 
---
This commit replaces "anv: remove no longer needed %.json rule"
---
 src/intel/vulkan/Makefile.am | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
index 916f171..6d93906 100644
--- a/src/intel/vulkan/Makefile.am
+++ b/src/intel/vulkan/Makefile.am
@@ -190,11 +190,10 @@ icdconf_DATA = intel_icd.json
 # The following is used for development purposes, by setting VK_ICD_FILENAMES.
 noinst_DATA = dev_icd.json
 
-%.json : %.json.in
+dev_icd.json : dev_icd.json.in
$(AM_V_GEN) $(SED) \
-   -e "s#@build_libdir@#${abs_top_builddir}/${LIB_DIR}#" \
-   -e "s#@install_libdir@#${libdir}#" < $< > $@
-
+   -e "s#@build_libdir@#${abs_top_builddir}/${LIB_DIR}#"
+   < $(srcdir)/dev_icd.json.in > $@
 
 # Libvulkan with dummy gem. Used for unit tests.
 
-- 
2.8.0

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Re: [Mesa-dev] [PATCH v2 02/25] anv: add a comment about dev_icd.json

[Jason Ekstrand]

R-B

On Fri, Apr 22, 2016 at 11:54 AM, Emil Velikov 
wrote:

> From: Emil Velikov 
>
> Cc: Jason Ekstrand 
> Signed-off-by: Emil Velikov 
> ---
> This patch replaces "anv: remove unused dev_icd.json"
> ---
>  src/intel/vulkan/Makefile.am | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
> index edbe213..916f171 100644
> --- a/src/intel/vulkan/Makefile.am
> +++ b/src/intel/vulkan/Makefile.am
> @@ -187,6 +187,7 @@ libvulkan_intel_la_LDFLAGS = \
>
>  icdconfdir=$(sysconfdir)/vulkan/icd.d
>  icdconf_DATA = intel_icd.json
> +# The following is used for development purposes, by setting
> VK_ICD_FILENAMES.
>  noinst_DATA = dev_icd.json
>
>  %.json : %.json.in
> --
> 2.8.0
>
>
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[Mesa-dev] [PATCH v2 02/25] anv: add a comment about dev_icd.json

[Emil Velikov]

From: Emil Velikov 

Cc: Jason Ekstrand 
Signed-off-by: Emil Velikov 
---
This patch replaces "anv: remove unused dev_icd.json"
---
 src/intel/vulkan/Makefile.am | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
index edbe213..916f171 100644
--- a/src/intel/vulkan/Makefile.am
+++ b/src/intel/vulkan/Makefile.am
@@ -187,6 +187,7 @@ libvulkan_intel_la_LDFLAGS = \
 
 icdconfdir=$(sysconfdir)/vulkan/icd.d
 icdconf_DATA = intel_icd.json
+# The following is used for development purposes, by setting VK_ICD_FILENAMES.
 noinst_DATA = dev_icd.json
 
 %.json : %.json.in
-- 
2.8.0

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[Mesa-dev] [PATCH v2 01/25] genxml: ship all the files needed in the tarball

[Emil Velikov]

From: Emil Velikov 

v2: The xml files are not called "gen*_pack.xml" (Jason)

Signed-off-by: Emil Velikov 
Acked-by: Jason Ekstrand  (v1)
---
 src/intel/genxml/Makefile.am | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/intel/genxml/Makefile.am b/src/intel/genxml/Makefile.am
index 77b2f19..64ecc5a 100644
--- a/src/intel/genxml/Makefile.am
+++ b/src/intel/genxml/Makefile.am
@@ -30,3 +30,14 @@ BUILT_SOURCES = \
$(AM_V_GEN) $(srcdir)/gen_pack_header.py $< > $@
 
 CLEANFILES = $(BUILT_SOURCES)
+
+EXTRA_DIST = \
+   gen6.xml \
+   gen7.xml \
+   gen75.xml \
+   gen8.xml \
+   gen9.xml \
+   genX_pack.h \
+   gen_macros.h \
+   gen_pack_header.py \
+   README
-- 
2.8.0

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Re: [Mesa-dev] [PATCH 20/25] anv: minor tweak in the generation script

[Jason Ekstrand]

On Fri, Apr 22, 2016 at 10:27 AM, Emil Velikov 
wrote:

> On 22 April 2016 at 04:36, Kristian Høgsberg  wrote:
> > On Thu, Apr 21, 2016 at 5:18 PM, Emil Velikov 
> wrote:
> >> On 21 April 2016 at 22:50, Jason Ekstrand  wrote:
> >>> On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov <
> emil.l.veli...@gmail.com>
> >>> wrote:
> 
>  From: Emil Velikov 
> 
>  Rather than parsing through the same files (public headers) twice,
> tweak
>  the python script to create both files at the same time.
> >>>
> >>>
> >>> Yes, but it takes almost zero time to generate them and it's going to
> run in
> >>> parallel before anything else gets built.  I don't know that this
> really
> >>> saves us anything.
> >>>
> >> Are you sure about this one? Based on my brief testing - things were
> >> pretty much stalled until both files were generated. I'll take another
> >> look.
> >>
> >> If anything the approach cuts down the bash output redirection and
> >> some nasty handling around it.
> >> Talking about the following $(PYHON)   > $@ || ($(RM) $@; false)
> >> and how often we forget to add it.
> >>
> Things get stalled for all the sources to be generated before proceeding
> with
> the compilation. Thus there isn't much benefit with the current approach
> afaict.
>

Yes, but if they run in parallel (which they will on *any* modern machine),
then it only takes as long as the longest one takes to run.  I don't think
it's actually helping anything to do them both with one python invocation
except for the make -j1 case.


> 
>  Chances are that if the public headers change, both files will need to
>  be regenerated.
> 
>  Note to the python masters: this patch aims to be the least evasive
>  change. Feel free to change/rewrite things to your liking.
> 
>  Signed-off-by: Emil Velikov 
>  ---
>   src/intel/vulkan/Makefile.am|  8 +++
>   src/intel/vulkan/anv_entrypoints_gen.py | 41
>  -
>   2 files changed, 33 insertions(+), 16 deletions(-)
> 
>  diff --git a/src/intel/vulkan/Makefile.am
> b/src/intel/vulkan/Makefile.am
>  index 360e97f..110961e 100644
>  --- a/src/intel/vulkan/Makefile.am
>  +++ b/src/intel/vulkan/Makefile.am
>  @@ -126,11 +126,9 @@ VULKAN_LIB_DEPS += \
> 
>   libvulkan_intel_la_SOURCES = $(VULKAN_GEM_FILES)
> 
>  -anv_entrypoints.h : anv_entrypoints_gen.py $(vulkan_include_HEADERS)
>  -   $(AM_V_GEN) cat $(vulkan_include_HEADERS) | $(CPP)
> $(AM_CPPFLAGS)
>  - | $(PYTHON2) $< header > $@
>  -
>  -anv_entrypoints.c : anv_entrypoints_gen.py $(vulkan_include_HEADERS)
>  -   $(AM_V_GEN) cat $(vulkan_include_HEADERS) | $(CPP)
> $(AM_CPPFLAGS)
>  - | $(PYTHON2) $< code > $@
>  +anv_entrypoints.c anv_entrypoints.h : anv_entrypoints_gen.py
>  $(vulkan_include_HEADERS)
>  +   $(AM_V_GEN) cat $(vulkan_include_HEADERS) | $(CPP)
> $(AM_CPPFLAGS)
>  - | \
>  +   $(PYTHON2) $(srcdir)/anv_entrypoints_gen.py $(builddir)
> 
>   CLEANFILES = $(BUILT_SOURCES)
> 
>  diff --git a/src/intel/vulkan/anv_entrypoints_gen.py
>  b/src/intel/vulkan/anv_entrypoints_gen.py
>  index cedecfe..19bfb93 100644
>  --- a/src/intel/vulkan/anv_entrypoints_gen.py
>  +++ b/src/intel/vulkan/anv_entrypoints_gen.py
>  @@ -22,7 +22,7 @@
>   # IN THE SOFTWARE.
>   #
> 
>  -import fileinput, re, sys
>  +import fileinput, re, sys, os
> 
>   # Each function typedef in the vulkan.h header is all on one line and
>  matches
>   # this regepx. We hope that won't change.
>  @@ -51,15 +51,21 @@ def hash(name):
> 
>   return h
> 
>  -opt_header = False
>  -opt_code = False
>  +if len(sys.argv[1:]) != 1:
>  +print "Usage: %s " % sys.argv[0]
>  +exit(1)
>  +
>  +output_dir = sys.argv[1]
>  +if not os.path.isdir(output_dir):
>  +if os.path.exists(output_dir):
>  +print "ERROR: Invalid output directory: %s" % output_dir
>  +exit(1)
>  +
>  +sys.argv.pop()
>  +# Output path exists, now just run the template
>  +output_file = os.sep.join([output_dir, 'anv_entrypoints.c'])
>  +output_header = os.sep.join([output_dir, 'anv_entrypoints.h'])
> 
>  -if (sys.argv[1] == "header"):
>  -opt_header = True
>  -sys.argv.pop()
>  -elif (sys.argv[1] == "code"):
>  -opt_code = True
>  -sys.argv.pop()
> 
>   # Parse the entry points in the header
> 
>  @@ -77,7 +83,11 @@ for line in fileinput.input():
>   # For outputting entrypoints.h we generate a anv_EntryPoint()
> prototype
>   # per entry point.
> 
>  -if opt_header:
>  +def generate_header(output_header):
>  +orig_stdout = sys.stdout
>  +hdr = file(output_header, 'w')
>  +sys.stdout = hdr
> >>>
> >>>
> >>> This is a bit ugly...
> >>>
> >> s/a b

Re: [Mesa-dev] [PATCH] i965/blorb: remove dead code in brw_blorp_const_color_program::compile()

[Pohjolainen, Topi]

On Fri, Apr 22, 2016 at 10:39:37AM -0700, Kenneth Graunke wrote:
> On Friday, April 22, 2016 3:01:27 PM PDT Juha-Pekka Heikkila wrote:
> > base_mrf is unsigned, checking if its greater or equal to zero will
> > not fail.
> > 
> > Signed-off-by: Juha-Pekka Heikkila 
> > ---
> >  src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/
> drivers/dri/i965/brw_blorp_clear.cpp
> > index 51f915d..06ac69e 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> > @@ -314,7 +314,7 @@ brw_blorp_const_color_program::compile(struct 
> brw_context *brw,
> > /* Now write to the render target and terminate the thread */
> > brw_fb_WRITE(&func,
> >  16 /* dispatch_width */,
> > -base_mrf >= 0 ? brw_message_reg(base_mrf) : mrf_rt_write,
> > +brw_message_reg(base_mrf),
> >  brw_null_reg() /* header */,
> >  msg_type,
> >  BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
> > 
> 
> Yeah, this is definitely dead - base_mrf seems to always equal 2.
> Thanks for catching this :)
> 
> The two parts of the conditional should be equivalent.  One has an
> <8,8,1> region and the other <16,16,1> but those refer to the same
> region, AFAIK.
> 
> I'd be tempted to just use mrf_rt_write unconditionally.  If we go with
> your patch, we should delete mrf_rt_write because it becomes dead.
> 
> Topi, thoughts?

I agree. I think I we can drop it also in
fs_generator::generate_blorp_fb_write(), just need to adjust
brw_blorp_blit_program::render_target_write() accordingly.
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Re: [Mesa-dev] [PATCH 01/13] i965: Add a dependency on libisl

[Jason Ekstrand]

On Fri, Apr 22, 2016 at 10:15 AM, Jonathan Gray  wrote:

> On Fri, Apr 22, 2016 at 05:31:29PM +0100, Emil Velikov wrote:
> > On 22 April 2016 at 16:08, Jonathan Gray  wrote:
> > > It is worth noting that the isl code extensively requires designated
> > > initialisers on anonymous structs.  It isn't clear to me when gcc
> introduced
> > > support for this but it isn't in 4.2.
> > >
> > I think it should work for GCC 4.2 with -fms-extensions. We used to
> > set -std=gnu99 for pre 4.6 which effectively enables it the extension.
> > Can you double-check ?
>
> The part that sets gnu99 for < gcc 4.6 is still there, using
> -fms-extensions
> does not help for these.
>
> libtool: compile:  gcc -DPACKAGE_NAME=\"Mesa\" -DPACKAGE_TARNAME=\"mesa\"
> -DPACKAGE_VERSION=\"11.3.0-devel\" "-DPACKAGE_STRING=\"Mesa 11.3.0-devel\""
> "-DPACKAGE_BUGREPORT=\"
> https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\"";
> -DPACKAGE_URL=\"\" -DPACKAGE=\"mesa\" -DVERSION=\"11.3.0-devel\"
> -DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1
> -DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1
> -DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_DLFCN_H=1 -DLT_OBJDIR=\".libs/\"
> -DYYTEXT_POINTER=1 -DHAVE___BUILTIN_CLZ=1 -DHAVE___BUILTIN_CLZLL=1
> -DHAVE___BUILTIN_CTZ=1 -DHAVE___BUILTIN_EXPECT=1 -DHAVE___BUILTIN_FFS=1
> -DHAVE___BUILTIN_FFSLL=1 -DHAVE___BUILTIN_POPCOUNT=1
> -DHAVE___BUILTIN_POPCOUNTLL=1 -DHAVE_FUNC_ATTRIBUTE_CONST=1
> -DHAVE_FUNC_ATTRIBUTE_FLATTEN=1 -DHAVE_FUNC_ATTRIBUTE_FORMAT=1
> -DHAVE_FUNC_ATTRIBUTE_MALLOC=1 -DHAVE_FUNC_ATTRIBUTE_PACKED=1
> -DHAVE_FUNC_ATTRIBUTE_PURE=1 -DHAVE_FUNC_ATTRIBUTE_UNUSED=1
> -DHAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT=1 -DHAVE_DLADDR=1
> -DHAVE_CLOCK_GETTIME=1 -DHAVE_PTHREAD_PRIO_INHERIT=1 -DHAVE_PTHREAD=1
> -DHAVE_SHA1_IN_LIBC=1 -DHAVE_VALGRIND=1 -I. -I/usr/X11R6/include
> -I/usr/X11R6/include/libdrm -I/usr/local/include/valgrind
> -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -DDEBUG
> -DTEXTURE_FLOAT_ENABLED -DUSE_X86_64_ASM -DHAVE_SYS_SYSCTL_H -DHAVE_STRTOF
> -DHAVE_MKOSTEMP -DHAVE_DLOPEN -DHAVE_POSIX_MEMALIGN -DHAVE_LIBDRM
> -DHAVE_SHA1 -DGLX_USE_DRM -DGLX_INDIRECT_RENDERING -DGLX_DIRECT_RENDERING
> -DHAVE_ALIAS -DHAVE_MINCORE -I../../../include -I../../../src
> -I../../../src/intel -I../../../src/mapi -I../../../src/mesa
> -I../../../src/mesa/drivers/dri/common -I../../../src/mesa/drivers/dri/i965
> -I../../../src/gallium/auxiliary -I../../../src/gallium/include
> -I../../../src -I../../../src/intel -g -O2 -Wall -std=gnu99
> -Werror=implicit-function-declaration -Werror=missing-prototypes
> -fno-strict-aliasing -fno-math-errno -fno-trapping-math -fno-builtin-memcmp
> -Wno-override-init -DGEN_VERSIONx10=70 -g -O2 -Wall -std=gnu99
> -Werror=implicit-function-declaration -Werror=missing-prototypes
> -fno-strict-aliasing -fno-math-errno -fno-trapping-math -fno-builtin-memcmp
> -MT libisl_gen7_la-isl_gen7.lo -MD -MP -MF
> .deps/libisl_gen7_la-isl_gen7.Tpo -c isl_gen7.c  -fPIC -DPIC -o
> .libs/libisl_gen7_la-isl_gen7.o
> In file included from isl_gen7.h:26,
>  from isl_gen7.c:24:
> isl_priv.h: In function 'isl_extent3d_sa_to_el':
> isl_priv.h:119: error: unknown field 'w' specified in initializer
> isl_priv.h:119: warning: missing braces around initializer
> isl_priv.h:119: warning: (near initialization for
> '(anonymous).')
> isl_priv.h:120: error: unknown field 'h' specified in initializer
> isl_priv.h:121: error: unknown field 'd' specified in initializer
> isl_priv.h: In function 'isl_extent3d_el_to_sa':
> isl_priv.h:131: error: unknown field 'w' specified in initializer
> isl_priv.h:131: warning: missing braces around initializer
> isl_priv.h:131: warning: (near initialization for
> '(anonymous).')
> isl_priv.h:132: error: unknown field 'h' specified in initializer
> isl_priv.h:133: error: unknown field 'd' specified in initializer
> isl_gen7.c: In function 'gen7_choose_image_alignment_el':
> isl_gen7.c:391: error: unknown field 'w' specified in initializer
> isl_gen7.c:391: warning: missing braces around initializer
> isl_gen7.c:391: warning: (near initialization for
> '(anonymous).')
> isl_gen7.c:392: error: unknown field 'h' specified in initializer
> isl_gen7.c:393: error: unknown field 'd' specified in initializer
> *** Error 1 in src/intel/isl (Makefile:744 'libisl_gen7_la-isl_gen7.lo')
>

At least for the errors you're seeing there, I see two options:  1) Use the
isl_extentNd constructor functions in isl.h.  2) Stop making isl_extentNd
have anonymous unions.  I'm not sure how much the anonymous unions are
really doing for us but I'd like chad to chip in before we throw them out.

Here's another question: I know BSD doesn't ship gcc newer than 4.2 for
license issues, but do you have a recent version of clang available?
--Jason


> >
> > > Would you accept patches to remove them?
> > While I cannot comment if they're OK with the idea, there might be
> > some confusion on the topic.
> > There is anonymous and named. I bel

Re: [Mesa-dev] [PATCH] i965/blorb: remove dead code in brw_blorp_const_color_program::compile()

[Kenneth Graunke]

On Friday, April 22, 2016 3:01:27 PM PDT Juha-Pekka Heikkila wrote:
> base_mrf is unsigned, checking if its greater or equal to zero will
> not fail.
> 
> Signed-off-by: Juha-Pekka Heikkila 
> ---
>  src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/
drivers/dri/i965/brw_blorp_clear.cpp
> index 51f915d..06ac69e 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
> @@ -314,7 +314,7 @@ brw_blorp_const_color_program::compile(struct 
brw_context *brw,
> /* Now write to the render target and terminate the thread */
> brw_fb_WRITE(&func,
>  16 /* dispatch_width */,
> -base_mrf >= 0 ? brw_message_reg(base_mrf) : mrf_rt_write,
> +brw_message_reg(base_mrf),
>  brw_null_reg() /* header */,
>  msg_type,
>  BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
> 

Yeah, this is definitely dead - base_mrf seems to always equal 2.
Thanks for catching this :)

The two parts of the conditional should be equivalent.  One has an
<8,8,1> region and the other <16,16,1> but those refer to the same
region, AFAIK.

I'd be tempted to just use mrf_rt_write unconditionally.  If we go with
your patch, we should delete mrf_rt_write because it becomes dead.

Topi, thoughts?


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Re: [Mesa-dev] Mesa (master): 29 new commits

[Nicolai Hähnle]

On 20.04.2016 23:02, Michel Dänzer wrote:

On 21.04.2016 02:42, Marek Olšák wrote:

On Thu, Apr 14, 2016 at 9:29 AM, Michel Dänzer  wrote:

On 14.04.2016 11:37, Michel Dänzer wrote:

On 12.04.2016 21:33, Marek =?UNKNOWN?B?T2zFocOhaw==?= wrote:


URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a4b74d1ba2c156766a7a5dbfef099c7db5d6694
Author: Marek Olšák 
Date:   Mon Apr 11 19:56:07 2016 +0200

 gallium/radeon: relax requirements on VRAM placements on APUs


This change caused a bunch of ARB_shader_load_image_store piglit tests
to fail on my Kaveri, see some examples below. The incorrect values
seem consistent.

I suppose some buffers end up in GTT instead of VRAM with this
change, but I'm not sure how that could cause problems. Any ideas?


Also, with the code modified to use GTT only for everything but
(potential) scanout buffers, the performance of Unigine Valley and the
Unreal Engine 4 Elemental demo is reduced by about 30%. So the premise
that GTT is about as fast as VRAM doesn't seem to hold true in practice
(at least with Kaveri and presumably other (pre-)CIK APUs; maybe it's
better with Carrizo and newer), which means that this change may cause
performance of long-running processes to drop significantly over time.

Given all these issues, I'm afraid it may be better to revert this
change for now, until we have a better plan for dealing with this.


Assuming you use the radeon kernel driver and you are not busy, would
you please check whether the performance is lower on amdgpu as well?


I am using the radeon driver, but also quite busy. Nicolai, can you try
it on your Carrizo?


I don't see any difference on Unigine Valley with my Carrizo (512MB of 
VRAM).


Nicolai





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Re: [Mesa-dev] [PATCH 1/4] gallium: add bool return to pipe_context::end_query

[Nicolai Hähnle]

On 22.04.2016 11:52, Roland Scheidegger wrote:

Am 22.04.2016 um 18:22 schrieb Nicolai Hähnle:

On 22.04.2016 08:56, Roland Scheidegger wrote:

I don't quite understand why this is necessary.
Couldn't you just handle such failures in the driver easily?


How? When we need a new query buffer due to command buffer flush, and
that buffer allocation fails, there's no easy way out (that still
produces correct results). I suppose we could try to stall everything,
store results so far off to the side on the CPU, and then try to
continue by re-using the already allocated buffer.


But if you couldn't end the query due to this failure, how are you going
to return correct results anyway?


We're not going to return correct results, but we tell the application 
about it by signaling GL_OUT_OF_MEMORY.


> That's what I don't understand. I

don't think the gl error will really help an app much.
There's likely more functions which potentially do allocation as a side
effect somewhere in the driver, and we don't really care about that neither.


Quite likely, but IMO that's a bad thing. We should follow the spec 
unless there are _very_ good reasons not to.


Cheers,
Nicolai



Roland





But that seems like an awful lot of work + a lot of code that won't
really ever be tested for handling what is an out of memory condition
that will soon lead to failures elsewhere anyway.

Nicolai


I can't
quite see why informing the state tracker of it really helps.

Roland

Am 20.04.2016 um 17:43 schrieb Nicolai Hähnle:

From: Nicolai Hähnle 

Even when begin_query succeeds, there can still be failures in query
handling.
For example for radeon, additional buffers may have to be allocated when
queries span multiple command buffers.
---
   src/gallium/drivers/ddebug/dd_context.c | 4 ++--
   src/gallium/drivers/freedreno/freedreno_query.c | 3 ++-
   src/gallium/drivers/i915/i915_query.c   | 3 ++-
   src/gallium/drivers/ilo/ilo_query.c | 6 --
   src/gallium/drivers/llvmpipe/lp_query.c | 4 +++-
   src/gallium/drivers/noop/noop_pipe.c| 3 ++-
   src/gallium/drivers/nouveau/nv30/nv30_query.c   | 3 ++-
   src/gallium/drivers/nouveau/nv50/nv50_query.c   | 3 ++-
   src/gallium/drivers/nouveau/nvc0/nvc0_query.c   | 3 ++-
   src/gallium/drivers/r300/r300_query.c   | 8 +---
   src/gallium/drivers/radeon/r600_query.c | 3 ++-
   src/gallium/drivers/rbug/rbug_context.c | 9 ++---
   src/gallium/drivers/softpipe/sp_query.c | 3 ++-
   src/gallium/drivers/svga/svga_pipe_query.c  | 3 ++-
   src/gallium/drivers/swr/swr_query.cpp   | 3 ++-
   src/gallium/drivers/trace/tr_context.c  | 6 --
   src/gallium/drivers/vc4/vc4_query.c | 3 ++-
   src/gallium/drivers/virgl/virgl_query.c | 3 ++-
   src/gallium/include/pipe/p_context.h| 2 +-
   19 files changed, 49 insertions(+), 26 deletions(-)

diff --git a/src/gallium/drivers/ddebug/dd_context.c
b/src/gallium/drivers/ddebug/dd_context.c
index 72a950a..d06efbc 100644
--- a/src/gallium/drivers/ddebug/dd_context.c
+++ b/src/gallium/drivers/ddebug/dd_context.c
@@ -104,13 +104,13 @@ dd_context_begin_query(struct pipe_context
*_pipe, struct pipe_query *query)
  return pipe->begin_query(pipe, dd_query_unwrap(query));
   }

-static void
+static bool
   dd_context_end_query(struct pipe_context *_pipe, struct pipe_query
*query)
   {
  struct dd_context *dctx = dd_context(_pipe);
  struct pipe_context *pipe = dctx->pipe;

-   pipe->end_query(pipe, dd_query_unwrap(query));
+   return pipe->end_query(pipe, dd_query_unwrap(query));
   }

   static boolean
diff --git a/src/gallium/drivers/freedreno/freedreno_query.c
b/src/gallium/drivers/freedreno/freedreno_query.c
index a942705..18e0c79 100644
--- a/src/gallium/drivers/freedreno/freedreno_query.c
+++ b/src/gallium/drivers/freedreno/freedreno_query.c
@@ -66,11 +66,12 @@ fd_begin_query(struct pipe_context *pctx, struct
pipe_query *pq)
   return q->funcs->begin_query(fd_context(pctx), q);
   }

-static void
+static bool
   fd_end_query(struct pipe_context *pctx, struct pipe_query *pq)
   {
   struct fd_query *q = fd_query(pq);
   q->funcs->end_query(fd_context(pctx), q);
+return true;
   }

   static boolean
diff --git a/src/gallium/drivers/i915/i915_query.c
b/src/gallium/drivers/i915/i915_query.c
index fa1b01d..d6015a6 100644
--- a/src/gallium/drivers/i915/i915_query.c
+++ b/src/gallium/drivers/i915/i915_query.c
@@ -60,8 +60,9 @@ static boolean i915_begin_query(struct pipe_context
*ctx,
  return true;
   }

-static void i915_end_query(struct pipe_context *ctx, struct
pipe_query *query)
+static bool i915_end_query(struct pipe_context *ctx, struct
pipe_query *query)
   {
+   return true;
   }

   static boolean i915_get_query_result(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/ilo/ilo_query.c
b/src/gallium/drivers/ilo/ilo_query.c
index 8a42f58..3088c96 100644
--- a/src/gallium/drivers/ilo/ilo

Re: [Mesa-dev] [PATCH 20/25] anv: minor tweak in the generation script

[Emil Velikov]

On 22 April 2016 at 04:36, Kristian Høgsberg  wrote:
> On Thu, Apr 21, 2016 at 5:18 PM, Emil Velikov  
> wrote:
>> On 21 April 2016 at 22:50, Jason Ekstrand  wrote:
>>> On Thu, Apr 21, 2016 at 6:16 AM, Emil Velikov 
>>> wrote:

 From: Emil Velikov 

 Rather than parsing through the same files (public headers) twice, tweak
 the python script to create both files at the same time.
>>>
>>>
>>> Yes, but it takes almost zero time to generate them and it's going to run in
>>> parallel before anything else gets built.  I don't know that this really
>>> saves us anything.
>>>
>> Are you sure about this one? Based on my brief testing - things were
>> pretty much stalled until both files were generated. I'll take another
>> look.
>>
>> If anything the approach cuts down the bash output redirection and
>> some nasty handling around it.
>> Talking about the following $(PYHON)   > $@ || ($(RM) $@; false)
>> and how often we forget to add it.
>>
Things get stalled for all the sources to be generated before proceeding with
the compilation. Thus there isn't much benefit with the current approach afaict.


 Chances are that if the public headers change, both files will need to
 be regenerated.

 Note to the python masters: this patch aims to be the least evasive
 change. Feel free to change/rewrite things to your liking.

 Signed-off-by: Emil Velikov 
 ---
  src/intel/vulkan/Makefile.am|  8 +++
  src/intel/vulkan/anv_entrypoints_gen.py | 41
 -
  2 files changed, 33 insertions(+), 16 deletions(-)

 diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
 index 360e97f..110961e 100644
 --- a/src/intel/vulkan/Makefile.am
 +++ b/src/intel/vulkan/Makefile.am
 @@ -126,11 +126,9 @@ VULKAN_LIB_DEPS += \

  libvulkan_intel_la_SOURCES = $(VULKAN_GEM_FILES)

 -anv_entrypoints.h : anv_entrypoints_gen.py $(vulkan_include_HEADERS)
 -   $(AM_V_GEN) cat $(vulkan_include_HEADERS) | $(CPP) $(AM_CPPFLAGS)
 - | $(PYTHON2) $< header > $@
 -
 -anv_entrypoints.c : anv_entrypoints_gen.py $(vulkan_include_HEADERS)
 -   $(AM_V_GEN) cat $(vulkan_include_HEADERS) | $(CPP) $(AM_CPPFLAGS)
 - | $(PYTHON2) $< code > $@
 +anv_entrypoints.c anv_entrypoints.h : anv_entrypoints_gen.py
 $(vulkan_include_HEADERS)
 +   $(AM_V_GEN) cat $(vulkan_include_HEADERS) | $(CPP) $(AM_CPPFLAGS)
 - | \
 +   $(PYTHON2) $(srcdir)/anv_entrypoints_gen.py $(builddir)

  CLEANFILES = $(BUILT_SOURCES)

 diff --git a/src/intel/vulkan/anv_entrypoints_gen.py
 b/src/intel/vulkan/anv_entrypoints_gen.py
 index cedecfe..19bfb93 100644
 --- a/src/intel/vulkan/anv_entrypoints_gen.py
 +++ b/src/intel/vulkan/anv_entrypoints_gen.py
 @@ -22,7 +22,7 @@
  # IN THE SOFTWARE.
  #

 -import fileinput, re, sys
 +import fileinput, re, sys, os

  # Each function typedef in the vulkan.h header is all on one line and
 matches
  # this regepx. We hope that won't change.
 @@ -51,15 +51,21 @@ def hash(name):

  return h

 -opt_header = False
 -opt_code = False
 +if len(sys.argv[1:]) != 1:
 +print "Usage: %s " % sys.argv[0]
 +exit(1)
 +
 +output_dir = sys.argv[1]
 +if not os.path.isdir(output_dir):
 +if os.path.exists(output_dir):
 +print "ERROR: Invalid output directory: %s" % output_dir
 +exit(1)
 +
 +sys.argv.pop()
 +# Output path exists, now just run the template
 +output_file = os.sep.join([output_dir, 'anv_entrypoints.c'])
 +output_header = os.sep.join([output_dir, 'anv_entrypoints.h'])

 -if (sys.argv[1] == "header"):
 -opt_header = True
 -sys.argv.pop()
 -elif (sys.argv[1] == "code"):
 -opt_code = True
 -sys.argv.pop()

  # Parse the entry points in the header

 @@ -77,7 +83,11 @@ for line in fileinput.input():
  # For outputting entrypoints.h we generate a anv_EntryPoint() prototype
  # per entry point.

 -if opt_header:
 +def generate_header(output_header):
 +orig_stdout = sys.stdout
 +hdr = file(output_header, 'w')
 +sys.stdout = hdr
>>>
>>>
>>> This is a bit ugly...
>>>
>> s/a bit/a fair bit/
>>
>> Definitely, but in all honesty the currently the script isn't the
>> prettiest one either. I'm pretty sure Dylan will end up rewriting the
>> whole thing if he has the time/chance. Even without this patch ;-)
>
> The rewrite that would be worthwhile is to make it parse the spec xml.
> Not sure churning this script really helps anything.
>
Precisely why I've went ahead with the fastest/least evasive solution :-)

-Emil
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Re: [Mesa-dev] [PATCH 01/13] i965: Add a dependency on libisl

[Jonathan Gray]

On Fri, Apr 22, 2016 at 05:31:29PM +0100, Emil Velikov wrote:
> On 22 April 2016 at 16:08, Jonathan Gray  wrote:
> > It is worth noting that the isl code extensively requires designated
> > initialisers on anonymous structs.  It isn't clear to me when gcc introduced
> > support for this but it isn't in 4.2.
> >
> I think it should work for GCC 4.2 with -fms-extensions. We used to
> set -std=gnu99 for pre 4.6 which effectively enables it the extension.
> Can you double-check ?

The part that sets gnu99 for < gcc 4.6 is still there, using -fms-extensions
does not help for these.

libtool: compile:  gcc -DPACKAGE_NAME=\"Mesa\" -DPACKAGE_TARNAME=\"mesa\" 
-DPACKAGE_VERSION=\"11.3.0-devel\" "-DPACKAGE_STRING=\"Mesa 11.3.0-devel\"" 
"-DPACKAGE_BUGREPORT=\"https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa\"";
 -DPACKAGE_URL=\"\" -DPACKAGE=\"mesa\" -DVERSION=\"11.3.0-devel\" 
-DSTDC_HEADERS=1 -DHAVE_SYS_TYPES_H=1 -DHAVE_SYS_STAT_H=1 -DHAVE_STDLIB_H=1 
-DHAVE_STRING_H=1 -DHAVE_MEMORY_H=1 -DHAVE_STRINGS_H=1 -DHAVE_INTTYPES_H=1 
-DHAVE_STDINT_H=1 -DHAVE_UNISTD_H=1 -DHAVE_DLFCN_H=1 -DLT_OBJDIR=\".libs/\" 
-DYYTEXT_POINTER=1 -DHAVE___BUILTIN_CLZ=1 -DHAVE___BUILTIN_CLZLL=1 
-DHAVE___BUILTIN_CTZ=1 -DHAVE___BUILTIN_EXPECT=1 -DHAVE___BUILTIN_FFS=1 
-DHAVE___BUILTIN_FFSLL=1 -DHAVE___BUILTIN_POPCOUNT=1 
-DHAVE___BUILTIN_POPCOUNTLL=1 -DHAVE_FUNC_ATTRIBUTE_CONST=1 
-DHAVE_FUNC_ATTRIBUTE_FLATTEN=1 -DHAVE_FUNC_ATTRIBUTE_FORMAT=1 
-DHAVE_FUNC_ATTRIBUTE_MALLOC=1 -DHAVE_FUNC_ATTRIBUTE_PACKED=1 
-DHAVE_FUNC_ATTRIBUTE_PURE=1 -DHAVE_FUNC_ATTRIBUTE_UNUSED=1 
-DHAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT=1 -DHAVE_DLADDR=1 
-DHAVE_CLOCK_GETTIME=1 -DHAVE_PTHREAD_PRIO_INHERIT=1 -DHAVE_PTHREAD=1 
-DHAVE_SHA1_IN_LIBC=1 -DHAVE_VALGRIND=1 -I. -I/usr/X11R6/include 
-I/usr/X11R6/include/libdrm -I/usr/local/include/valgrind -D__STDC_LIMIT_MACROS 
-D__STDC_CONSTANT_MACROS -DDEBUG -DTEXTURE_FLOAT_ENABLED -DUSE_X86_64_ASM 
-DHAVE_SYS_SYSCTL_H -DHAVE_STRTOF -DHAVE_MKOSTEMP -DHAVE_DLOPEN 
-DHAVE_POSIX_MEMALIGN -DHAVE_LIBDRM -DHAVE_SHA1 -DGLX_USE_DRM 
-DGLX_INDIRECT_RENDERING -DGLX_DIRECT_RENDERING -DHAVE_ALIAS -DHAVE_MINCORE 
-I../../../include -I../../../src -I../../../src/intel -I../../../src/mapi 
-I../../../src/mesa -I../../../src/mesa/drivers/dri/common 
-I../../../src/mesa/drivers/dri/i965 -I../../../src/gallium/auxiliary 
-I../../../src/gallium/include -I../../../src -I../../../src/intel -g -O2 -Wall 
-std=gnu99 -Werror=implicit-function-declaration -Werror=missing-prototypes 
-fno-strict-aliasing -fno-math-errno -fno-trapping-math -fno-builtin-memcmp 
-Wno-override-init -DGEN_VERSIONx10=70 -g -O2 -Wall -std=gnu99 
-Werror=implicit-function-declaration -Werror=missing-prototypes 
-fno-strict-aliasing -fno-math-errno -fno-trapping-math -fno-builtin-memcmp -MT 
libisl_gen7_la-isl_gen7.lo -MD -MP -MF .deps/libisl_gen7_la-isl_gen7.Tpo -c 
isl_gen7.c  -fPIC -DPIC -o .libs/libisl_gen7_la-isl_gen7.o
In file included from isl_gen7.h:26,
 from isl_gen7.c:24:
isl_priv.h: In function 'isl_extent3d_sa_to_el':
isl_priv.h:119: error: unknown field 'w' specified in initializer
isl_priv.h:119: warning: missing braces around initializer
isl_priv.h:119: warning: (near initialization for '(anonymous).')
isl_priv.h:120: error: unknown field 'h' specified in initializer
isl_priv.h:121: error: unknown field 'd' specified in initializer
isl_priv.h: In function 'isl_extent3d_el_to_sa':
isl_priv.h:131: error: unknown field 'w' specified in initializer
isl_priv.h:131: warning: missing braces around initializer
isl_priv.h:131: warning: (near initialization for '(anonymous).')
isl_priv.h:132: error: unknown field 'h' specified in initializer
isl_priv.h:133: error: unknown field 'd' specified in initializer
isl_gen7.c: In function 'gen7_choose_image_alignment_el':
isl_gen7.c:391: error: unknown field 'w' specified in initializer
isl_gen7.c:391: warning: missing braces around initializer
isl_gen7.c:391: warning: (near initialization for '(anonymous).')
isl_gen7.c:392: error: unknown field 'h' specified in initializer
isl_gen7.c:393: error: unknown field 'd' specified in initializer
*** Error 1 in src/intel/isl (Makefile:744 'libisl_gen7_la-isl_gen7.lo')

> 
> > Would you accept patches to remove them?
> While I cannot comment if they're OK with the idea, there might be
> some confusion on the topic.
> There is anonymous and named. I believe developers were against the
> latter. Examples form [1]
> 
> struct bar { int i; }; // (1) unnamed, but tagged, ie *not* anonymous
> struct { int j; }; // (2) unnamed, but anonymous
> struct { int k; } baz; // (3) named, but not tagged
> 
> Fwiw it would be great to use the more portable solution. Would C11
> buy us anything ?
> 
> 
> Thanks
> Emil
> 
> [1] 
> http://stackoverflow.com/questions/5063548/initialization-of-anonymous-structures-or-unions-in-c1x
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Re: [Mesa-dev] [PATCH] i965: Disable channel expressions for scalar GS, TCS, TES.

[Matt Turner]

Looks good to me:

Reviewed-by: Matt Turner 
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