Re: [Mesa-dev] [PATCH v2 3/4] gallium/winsys/kms: Move display target handle lookup to separate function (v2)
On Fri, Aug 12, 2016 at 8:03 AM, Jordan Justen wrote: > On 2016-08-08 01:55:18, Tomasz Figa wrote: >>On Fri, Aug 5, 2016 at 2:37 AM, Jordan Justen >>wrote: >> >> On 2016-08-02 03:46:27, Tomasz Figa wrote: >> > +kms_sw_displaytarget_lookup(struct kms_sw_winsys *kms_sw, >> > +unsigned int kms_handle) >> >> I don't think the 'lookup' name is appropriate, since it has the >> ref-count side effect. Instead of 'lookup', how about import, or >> find_and_import or something similar? >> >>How about "get_by_handle"? IMHO "import" is kind of confusing, because the >>function doesn't end up creating any new objects, but instead just looks >>through already known ones. > > How about find_and_ref? Sounds good to me. :) Best regards, Tomasz ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] nir/algebraic: Optimize common array indexing sequence
On Thu, 2016-08-11 at 20:54 +0200, Thomas Helland wrote: > 2016-08-11 18:19 GMT+02:00 Ian Romanick : > > > > ping > > > > On 07/19/2016 10:37 PM, Ian Romanick wrote: > > > > > > From: Ian Romanick > > > > > > Some shaders include code that looks like: > > > > > > uniform int i; > > > uniform vec4 bones[...]; > > > > > > foo(bones[i * 3], bones[i * 3 + 1], bones[i * 3 + 2]); > > > > > > CSE would do some work on this: > > > > > > x = i * 3 > > > foo(bones[x], bones[x + 1], bones[x + 2]); > > > > > > The compiler may then add '<< 4 + base' to the index > > > calculations. > > > This results in expressions like > > > > > > x = i * 3 > > > foo(bones[x << 4], bones[(x + 1) << 4], bones[(x + 2) << 4]); > > > > > This may just be me being dense, but why is the compiler adding the > shift? > It seems like this would be "un-optimizing" and so it shouldn't be > added? > > This patch is also a good argument for adding a constant > reassociation pass. > At least the (a * #b) << #c--->a * (#b << #c) would be caught > by that. > > I was confused whether the optimization was preserving signed-ness > correctly > but after a couple rounds with myself I believe it is correct. > > The change looks good and is: > > Reviewed-by: Thomas Helland > > (Oh, and yes, I'm back to hobby mesa development after finally > securing a new job and a new apartment) Congrats and welcome back. I did send you an email but just in case you missed it I've picked up on your loop unrolling work. > > > > > > > > > Just rearranging the math to produce (i * 48) + 16 saves an > > > instruction, and it allows CSE to do more work. > > > > > > x = i * 48; > > > foo(bones[x], bones[x + 16], bones[x + 32]); > > > > > > So, ~6 instructions becomes ~3. > > > > > > Some individual shader-db results look pretty bad. However, I > > > have a > > > really, really hard time believing the change in estimated cycles > > > in, > > > for example, 3dmmes-taiji/51.shader_test after looking that > > > change in > > > the generated code. > > > > > > G45 > > > total instructions in shared programs: 4020840 -> 4010070 (- > > > 0.27%) > > > instructions in affected programs: 177460 -> 166690 (-6.07%) > > > helped: 894 > > > HURT: 0 > > > > > > total cycles in shared programs: 98829000 -> 98784990 (-0.04%) > > > cycles in affected programs: 3936648 -> 3892638 (-1.12%) > > > helped: 894 > > > HURT: 0 > > > > > > Ironlake > > > total instructions in shared programs: 6418887 -> 6408117 (- > > > 0.17%) > > > instructions in affected programs: 177460 -> 166690 (-6.07%) > > > helped: 894 > > > HURT: 0 > > > > > > total cycles in shared programs: 143504542 -> 143460532 (-0.03%) > > > cycles in affected programs: 3936648 -> 3892638 (-1.12%) > > > helped: 894 > > > HURT: 0 > > > > > > Sandy Bridge > > > total instructions in shared programs: 8357887 -> 8339251 (- > > > 0.22%) > > > instructions in affected programs: 432715 -> 414079 (-4.31%) > > > helped: 2795 > > > HURT: 0 > > > > > > total cycles in shared programs: 118284184 -> 118207412 (-0.06%) > > > cycles in affected programs: 6114626 -> 6037854 (-1.26%) > > > helped: 2478 > > > HURT: 317 > > > > > > Ivy Bridge > > > total instructions in shared programs: 7669390 -> 7653822 (- > > > 0.20%) > > > instructions in affected programs: 388234 -> 372666 (-4.01%) > > > helped: 2795 > > > HURT: 0 > > > > > > total cycles in shared programs: 68381982 -> 68263684 (-0.17%) > > > cycles in affected programs: 1972658 -> 1854360 (-6.00%) > > > helped: 2458 > > > HURT: 307 > > > > > > Haswell > > > total instructions in shared programs: 7082636 -> 7067068 (- > > > 0.22%) > > > instructions in affected programs: 388234 -> 372666 (-4.01%) > > > helped: 2795 > > > HURT: 0 > > > > > > total cycles in shared programs: 68282020 -> 68164158 (-0.17%) > > > cycles in affected programs: 1891820 -> 1773958 (-6.23%) > > > helped: 2459 > > > HURT: 261 > > > > > > Broadwell > > > total instructions in shared programs: 9002466 -> 8985875 (- > > > 0.18%) > > > instructions in affected programs: 658784 -> 642193 (-2.52%) > > > helped: 2795 > > > HURT: 5 > > > > > > total cycles in shared programs: 78503092 -> 78450404 (-0.07%) > > > cycles in affected programs: 2873304 -> 2820616 (-1.83%) > > > helped: 2275 > > > HURT: 415 > > > > > > Skylake > > > total instructions in shared programs: 9156978 -> 9140387 (- > > > 0.18%) > > > instructions in affected programs: 682625 -> 666034 (-2.43%) > > > helped: 2795 > > > HURT: 5 > > > > > > total cycles in shared programs: 75591392 -> 75550574 (-0.05%) > > > cycles in affected programs: 3192120 -> 3151302 (-1.28%) > > > helped: 2271 > > > HURT: 425 > > > > > > Signed-off-by: Ian Romanick > > > --- > > > src/compiler/nir/nir_opt_algebraic.py | 11 +++ > > > 1 file changed, 11 insertions(+) > > > > > > diff --git a/src/compiler/nir/nir_opt_algebraic.py > > > b/src/compiler/nir/nir_opt_algebraic.py > > > index 0f0896b..37cb700 100644
Re: [Mesa-dev] [PATCH 2/2] anv: GetDeviceImageFormatProperties: fix TRANSFER formats
On Aug 11, 2016 10:25 AM, "Lionel Landwerlin" wrote:
>
> We let the user believe we support some transfer formats which we don't.
> This can lead to crashes when actually trying to use those formats for
> example on dEQP-VK.api.copy_and_blit.image_to_image.* tests.
>
> Let all formats we can render to or sample from as meta implements
transfers
> using attachments.
>
> Signed-off-by: Lionel Landwerlin
> Cc: Jason Ekstrand
> ---
> src/intel/vulkan/anv_formats.c | 16 +++-
> 1 file changed, 7 insertions(+), 9 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_formats.c
b/src/intel/vulkan/anv_formats.c
> index b26e48a..13bde90 100644
> --- a/src/intel/vulkan/anv_formats.c
> +++ b/src/intel/vulkan/anv_formats.c
> @@ -509,23 +509,21 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties(
>
> if (usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
>/* Meta implements transfers by sampling from the source image. */
I think this change is functionally correct. However, the comment above is
bogus. The reason for the restriction is that we only want to support
transfer operations on formats that we support for other things. In other
words, we don't want transfer-only formats.
> - if (!(format_feature_flags & VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT))
{
> + if (!(format_feature_flags &
(VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT |
> +
VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT |
> +
VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT))) {
> goto unsupported;
>}
> }
>
> -#if 0
> if (usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT) {
> - if (anv_format_for_vk_format(format)->has_stencil) {
> - /* Not yet implemented because copying to a W-tiled surface is
crazy
> - * hard.
> - */
> - anv_finishme("support VK_IMAGE_USAGE_TRANSFER_DST_BIT for "
> - "stencil format");
> + /* Meta implements transfers by rendering to the attachment image.
*/
> + if (!(format_feature_flags &
(VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT |
> +
VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT |
> +
VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT))) {
While we're here, let's combine the two checks since they now do the same
thing.
> goto unsupported;
>}
> }
> -#endif
>
> if (usage & VK_IMAGE_USAGE_SAMPLED_BIT) {
>if (!(format_feature_flags & VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT))
{
> --
> 2.8.1
>
___
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Re: [Mesa-dev] [PATCH 2/2] nir/algebraic: Optimize common array indexing sequence
On Aug 11, 2016 6:16 PM, "Ian Romanick" wrote: > > On 08/11/2016 11:54 AM, Thomas Helland wrote: > > 2016-08-11 18:19 GMT+02:00 Ian Romanick : > >> ping > >> > >> On 07/19/2016 10:37 PM, Ian Romanick wrote: > >>> From: Ian Romanick > >>> > >>> Some shaders include code that looks like: > >>> > >>>uniform int i; > >>>uniform vec4 bones[...]; > >>> > >>>foo(bones[i * 3], bones[i * 3 + 1], bones[i * 3 + 2]); > >>> > >>> CSE would do some work on this: > >>> > >>>x = i * 3 > >>>foo(bones[x], bones[x + 1], bones[x + 2]); > >>> > >>> The compiler may then add '<< 4 + base' to the index calculations. > >>> This results in expressions like > >>> > >>>x = i * 3 > >>>foo(bones[x << 4], bones[(x + 1) << 4], bones[(x + 2) << 4]); > >>> > > > > This may just be me being dense, but why is the compiler adding the shift? > > It seems like this would be "un-optimizing" and so it shouldn't be added? > > The shift is to convert the array offset to a byte offset. A vec4 is 16 > bytes. > > > This patch is also a good argument for adding a constant reassociation pass. > > At least the (a * #b) << #c--->a * (#b << #c) would be caught by that. > > > > I was confused whether the optimization was preserving signed-ness correctly > > but after a couple rounds with myself I believe it is correct. I believe so too. "<< c" as an operator is equivalent to "* (1 << c)" so association and distributivity apply. > > The change looks good and is: > > > > Reviewed-by: Thomas Helland Reviewed-by: Jason Ekstrand > > (Oh, and yes, I'm back to hobby mesa development after finally > > securing a new job and a new apartment) > > Welcome back! Woohoo! > >>> Just rearranging the math to produce (i * 48) + 16 saves an > >>> instruction, and it allows CSE to do more work. > >>> > >>>x = i * 48; > >>>foo(bones[x], bones[x + 16], bones[x + 32]); > >>> > >>> So, ~6 instructions becomes ~3. > >>> > >>> Some individual shader-db results look pretty bad. However, I have a > >>> really, really hard time believing the change in estimated cycles in, > >>> for example, 3dmmes-taiji/51.shader_test after looking that change in > >>> the generated code. > >>> > >>> G45 > >>> total instructions in shared programs: 4020840 -> 4010070 (-0.27%) > >>> instructions in affected programs: 177460 -> 166690 (-6.07%) > >>> helped: 894 > >>> HURT: 0 > >>> > >>> total cycles in shared programs: 98829000 -> 98784990 (-0.04%) > >>> cycles in affected programs: 3936648 -> 3892638 (-1.12%) > >>> helped: 894 > >>> HURT: 0 > >>> > >>> Ironlake > >>> total instructions in shared programs: 6418887 -> 6408117 (-0.17%) > >>> instructions in affected programs: 177460 -> 166690 (-6.07%) > >>> helped: 894 > >>> HURT: 0 > >>> > >>> total cycles in shared programs: 143504542 -> 143460532 (-0.03%) > >>> cycles in affected programs: 3936648 -> 3892638 (-1.12%) > >>> helped: 894 > >>> HURT: 0 > >>> > >>> Sandy Bridge > >>> total instructions in shared programs: 8357887 -> 8339251 (-0.22%) > >>> instructions in affected programs: 432715 -> 414079 (-4.31%) > >>> helped: 2795 > >>> HURT: 0 > >>> > >>> total cycles in shared programs: 118284184 -> 118207412 (-0.06%) > >>> cycles in affected programs: 6114626 -> 6037854 (-1.26%) > >>> helped: 2478 > >>> HURT: 317 > >>> > >>> Ivy Bridge > >>> total instructions in shared programs: 7669390 -> 7653822 (-0.20%) > >>> instructions in affected programs: 388234 -> 372666 (-4.01%) > >>> helped: 2795 > >>> HURT: 0 > >>> > >>> total cycles in shared programs: 68381982 -> 68263684 (-0.17%) > >>> cycles in affected programs: 1972658 -> 1854360 (-6.00%) > >>> helped: 2458 > >>> HURT: 307 > >>> > >>> Haswell > >>> total instructions in shared programs: 7082636 -> 7067068 (-0.22%) > >>> instructions in affected programs: 388234 -> 372666 (-4.01%) > >>> helped: 2795 > >>> HURT: 0 > >>> > >>> total cycles in shared programs: 68282020 -> 68164158 (-0.17%) > >>> cycles in affected programs: 1891820 -> 1773958 (-6.23%) > >>> helped: 2459 > >>> HURT: 261 > >>> > >>> Broadwell > >>> total instructions in shared programs: 9002466 -> 8985875 (-0.18%) > >>> instructions in affected programs: 658784 -> 642193 (-2.52%) > >>> helped: 2795 > >>> HURT: 5 > >>> > >>> total cycles in shared programs: 78503092 -> 78450404 (-0.07%) > >>> cycles in affected programs: 2873304 -> 2820616 (-1.83%) > >>> helped: 2275 > >>> HURT: 415 > >>> > >>> Skylake > >>> total instructions in shared programs: 9156978 -> 9140387 (-0.18%) > >>> instructions in affected programs: 682625 -> 666034 (-2.43%) > >>> helped: 2795 > >>> HURT: 5 > >>> > >>> total cycles in shared programs: 75591392 -> 75550574 (-0.05%) > >>> cycles in affected programs: 3192120 -> 3151302 (-1.28%) > >>> helped: 2271 > >>> HURT: 425 > >>> > >>> Signed-off-by: Ian Romanick > >>> --- > >>> src/compiler/nir/nir_opt_algebraic.py | 11 +++ > >>> 1 file changed, 11 insertions(+) > >>> > >>> diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_al
Re: [Mesa-dev] [PATCH 2/2] nir/algebraic: Optimize common array indexing sequence
On 08/11/2016 11:54 AM, Thomas Helland wrote:
> 2016-08-11 18:19 GMT+02:00 Ian Romanick :
>> ping
>>
>> On 07/19/2016 10:37 PM, Ian Romanick wrote:
>>> From: Ian Romanick
>>>
>>> Some shaders include code that looks like:
>>>
>>>uniform int i;
>>>uniform vec4 bones[...];
>>>
>>>foo(bones[i * 3], bones[i * 3 + 1], bones[i * 3 + 2]);
>>>
>>> CSE would do some work on this:
>>>
>>>x = i * 3
>>>foo(bones[x], bones[x + 1], bones[x + 2]);
>>>
>>> The compiler may then add '<< 4 + base' to the index calculations.
>>> This results in expressions like
>>>
>>>x = i * 3
>>>foo(bones[x << 4], bones[(x + 1) << 4], bones[(x + 2) << 4]);
>>>
>
> This may just be me being dense, but why is the compiler adding the shift?
> It seems like this would be "un-optimizing" and so it shouldn't be added?
The shift is to convert the array offset to a byte offset. A vec4 is 16
bytes.
> This patch is also a good argument for adding a constant reassociation pass.
> At least the (a * #b) << #c--->a * (#b << #c) would be caught by that.
>
> I was confused whether the optimization was preserving signed-ness correctly
> but after a couple rounds with myself I believe it is correct.
>
> The change looks good and is:
>
> Reviewed-by: Thomas Helland
>
> (Oh, and yes, I'm back to hobby mesa development after finally
> securing a new job and a new apartment)
Welcome back!
>>> Just rearranging the math to produce (i * 48) + 16 saves an
>>> instruction, and it allows CSE to do more work.
>>>
>>>x = i * 48;
>>>foo(bones[x], bones[x + 16], bones[x + 32]);
>>>
>>> So, ~6 instructions becomes ~3.
>>>
>>> Some individual shader-db results look pretty bad. However, I have a
>>> really, really hard time believing the change in estimated cycles in,
>>> for example, 3dmmes-taiji/51.shader_test after looking that change in
>>> the generated code.
>>>
>>> G45
>>> total instructions in shared programs: 4020840 -> 4010070 (-0.27%)
>>> instructions in affected programs: 177460 -> 166690 (-6.07%)
>>> helped: 894
>>> HURT: 0
>>>
>>> total cycles in shared programs: 98829000 -> 98784990 (-0.04%)
>>> cycles in affected programs: 3936648 -> 3892638 (-1.12%)
>>> helped: 894
>>> HURT: 0
>>>
>>> Ironlake
>>> total instructions in shared programs: 6418887 -> 6408117 (-0.17%)
>>> instructions in affected programs: 177460 -> 166690 (-6.07%)
>>> helped: 894
>>> HURT: 0
>>>
>>> total cycles in shared programs: 143504542 -> 143460532 (-0.03%)
>>> cycles in affected programs: 3936648 -> 3892638 (-1.12%)
>>> helped: 894
>>> HURT: 0
>>>
>>> Sandy Bridge
>>> total instructions in shared programs: 8357887 -> 8339251 (-0.22%)
>>> instructions in affected programs: 432715 -> 414079 (-4.31%)
>>> helped: 2795
>>> HURT: 0
>>>
>>> total cycles in shared programs: 118284184 -> 118207412 (-0.06%)
>>> cycles in affected programs: 6114626 -> 6037854 (-1.26%)
>>> helped: 2478
>>> HURT: 317
>>>
>>> Ivy Bridge
>>> total instructions in shared programs: 7669390 -> 7653822 (-0.20%)
>>> instructions in affected programs: 388234 -> 372666 (-4.01%)
>>> helped: 2795
>>> HURT: 0
>>>
>>> total cycles in shared programs: 68381982 -> 68263684 (-0.17%)
>>> cycles in affected programs: 1972658 -> 1854360 (-6.00%)
>>> helped: 2458
>>> HURT: 307
>>>
>>> Haswell
>>> total instructions in shared programs: 7082636 -> 7067068 (-0.22%)
>>> instructions in affected programs: 388234 -> 372666 (-4.01%)
>>> helped: 2795
>>> HURT: 0
>>>
>>> total cycles in shared programs: 68282020 -> 68164158 (-0.17%)
>>> cycles in affected programs: 1891820 -> 1773958 (-6.23%)
>>> helped: 2459
>>> HURT: 261
>>>
>>> Broadwell
>>> total instructions in shared programs: 9002466 -> 8985875 (-0.18%)
>>> instructions in affected programs: 658784 -> 642193 (-2.52%)
>>> helped: 2795
>>> HURT: 5
>>>
>>> total cycles in shared programs: 78503092 -> 78450404 (-0.07%)
>>> cycles in affected programs: 2873304 -> 2820616 (-1.83%)
>>> helped: 2275
>>> HURT: 415
>>>
>>> Skylake
>>> total instructions in shared programs: 9156978 -> 9140387 (-0.18%)
>>> instructions in affected programs: 682625 -> 666034 (-2.43%)
>>> helped: 2795
>>> HURT: 5
>>>
>>> total cycles in shared programs: 75591392 -> 75550574 (-0.05%)
>>> cycles in affected programs: 3192120 -> 3151302 (-1.28%)
>>> helped: 2271
>>> HURT: 425
>>>
>>> Signed-off-by: Ian Romanick
>>> ---
>>> src/compiler/nir/nir_opt_algebraic.py | 11 +++
>>> 1 file changed, 11 insertions(+)
>>>
>>> diff --git a/src/compiler/nir/nir_opt_algebraic.py
>>> b/src/compiler/nir/nir_opt_algebraic.py
>>> index 0f0896b..37cb700 100644
>>> --- a/src/compiler/nir/nir_opt_algebraic.py
>>> +++ b/src/compiler/nir/nir_opt_algebraic.py
>>> @@ -119,6 +119,17 @@ optimizations = [
>>> (('~fadd@64', a, ('fmul', c , ('fadd', b, ('fneg', a,
>>> ('flrp', a, b, c), '!options->lower_flrp64'),
>>> (('ffma', a, b, c), ('fadd', ('fmul', a, b), c), 'options->lower_ffma'),
>>> (('~fadd', ('fmul', a, b), c), ('ffma', a, b, c), 'options->fuse_ffma
Re: [Mesa-dev] [PATCH V2 2/2] i965: Change 8X MSAA sample mapping
On Aug 11, 2016 5:34 PM, "Anuj Phogat" wrote:
>
> Thanks for the review. Can you also review the piglit patch?
> "multisample_blit_scaled: Change 8X MSAA sample mapping"
Done
>
> On Thu, Aug 11, 2016 at 3:56 PM, Jason Ekstrand
wrote:
> > This looks good. Thanks! I think we should probably squash it in to
the
> > other one because there's technically a regression between the two.
Both
> > are
> >
> > Reviewed-by: Jason Ekstrand
> >
> > On Thu, Aug 11, 2016 at 12:28 PM, Anuj Phogat
wrote:
> >>
> >> This is required following the change in 8X sample positions.
> >> Fixes the recently modified multisample-scaled-blit piglit tests.
> >>
> >> Signed-off-by: Anuj Phogat
> >> ---
> >> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
> >> src/mesa/drivers/dri/i965/gen6_multisample_state.c | 2 +-
> >> 2 files changed, 6 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> >> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> >> index b903de1..f7f685b 100644
> >> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> >> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> >> @@ -1094,13 +1094,13 @@ blorp_nir_manual_blend_bilinear(nir_builder *b,
> >> nir_ssa_def *pos,
> >> *
> >> * In case of 8x MSAA the two layouts don't match.
> >> * sample index layout : -sample number layout :
> >> -
> >> - *| 0 | 1 |
| 5
> >> | 2 |
> >> + *| 0 | 1 |
| 3
> >> | 7 |
> >> *-
> >> -
> >> - *| 2 | 3 |
| 4
> >> | 6 |
> >> + *| 2 | 3 |
| 5
> >> | 0 |
> >> *-
> >> -
> >> - *| 4 | 5 |
| 0
> >> | 3 |
> >> + *| 4 | 5 |
| 1
> >> | 2 |
> >> *-
> >> -
> >> - *| 6 | 7 |
| 7
> >> | 1 |
> >> + *| 6 | 7 |
| 4
> >> | 6 |
> >> *-
> >> -
> >> *
> >> * Fortunately, this can be done fairly easily as:
> >> @@ -1128,7 +1128,7 @@ blorp_nir_manual_blend_bilinear(nir_builder *b,
> >> nir_ssa_def *pos,
> >>sample = nir_f2i(b, sample);
> >>
> >>if (tex_samples == 8) {
> >> - sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x17306425),
> >> + sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x64210573),
> >> nir_ishl(b, sample,
nir_imm_int(b,
> >> 2))),
> >> nir_imm_int(b, 0xf));
> >>} else if (tex_samples == 16) {
> >> diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> >> b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> >> index a47e323..a59ffec 100644
> >> --- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> >> +++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> >> @@ -109,7 +109,7 @@ gen6_set_sample_maps(struct gl_context *ctx)
> >> {
> >> uint8_t map_2x[2] = {0, 1};
> >> uint8_t map_4x[4] = {0, 1, 2, 3};
> >> - uint8_t map_8x[8] = {5, 2, 4, 6, 0, 3, 7, 1};
> >> + uint8_t map_8x[8] = {3, 7, 5, 0, 1, 2, 4, 6};
> >> uint8_t map_16x[16] = { 15, 10, 9, 7, 4, 1, 3, 13,
> >> 12, 2, 0, 6, 11, 8, 5, 14 };
> >>
> >> --
> >> 2.5.5
> >>
> >> ___
> >> mesa-dev mailing list
> >> mesa-dev@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> >
> >
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Re: [Mesa-dev] [PATCH] anv: Use macro to avoid code duplication for sample positions
On Aug 11, 2016 5:12 PM, "Anuj Phogat" wrote: > > On Thu, Aug 11, 2016 at 4:06 PM, Jason Ekstrand wrote: > > Thanks! > > > > Reviewed-by: Jason Ekstrand > > > > On Thu, Aug 11, 2016 at 10:39 AM, Anuj Phogat wrote: > >> > >> Suggested-by: Jason Ekstrand > >> Signed-off-by: Anuj Phogat > >> --- > >> src/intel/vulkan/genX_multisample.h | 95 > >> +++ > >> src/intel/vulkan/genX_pipeline_util.h | 35 ++--- > >> src/intel/vulkan/genX_state.c | 68 +++-- > >> 3 files changed, 106 insertions(+), 92 deletions(-) > >> create mode 100644 src/intel/vulkan/genX_multisample.h > >> > >> diff --git a/src/intel/vulkan/genX_multisample.h > >> b/src/intel/vulkan/genX_multisample.h > >> new file mode 100644 > >> index 000..0deb48f > >> --- /dev/null > >> +++ b/src/intel/vulkan/genX_multisample.h > >> @@ -0,0 +1,95 @@ > >> +/* > >> + * Copyright © 2016 Intel Corporation > >> + * > >> + * Permission is hereby granted, free of charge, to any person obtaining > >> a > >> + * copy of this software and associated documentation files (the > >> "Software"), > >> + * to deal in the Software without restriction, including without > >> limitation > >> + * the rights to use, copy, modify, merge, publish, distribute, > >> sublicense, > >> + * and/or sell copies of the Software, and to permit persons to whom the > >> + * Software is furnished to do so, subject to the following conditions: > >> + * > >> + * The above copyright notice and this permission notice (including the > >> next > >> + * paragraph) shall be included in all copies or substantial portions of > >> the > >> + * Software. > >> + * > >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > >> EXPRESS OR > >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > >> MERCHANTABILITY, > >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT > >> SHALL > >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR > >> OTHER > >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > >> ARISING > >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER > >> DEALINGS > >> + * IN THE SOFTWARE. > >> + */ > >> +#pragma once > >> + > >> +#define SAMPLE_POS_1X(prefix) \ > >> +prefix##0XOffset = 0.5; \ > >> +prefix##0YOffset = 0.5; > >> + > >> +#define SAMPLE_POS_2X(prefix) \ > >> +prefix##0XOffset = 0.25; \ > > > > > > If I were to write the patch, I would probably make it > > "prefix##Sample0Offset = 0.25" but this is totally fine and you don't need > > to rework it. > > > That's what I did initially but compiler wasn't happy with a prefix > ending with '.' in "ms.". There might be a better way to avoid this > than what I came up with. Ah! That makes sense. I'm not that familiar with the preprocessing rules. > >> > >> +prefix##0YOffset = 0.25; \ > >> +prefix##1XOffset = 0.75; \ > >> +prefix##1YOffset = 0.75; > >> + > >> +#define SAMPLE_POS_4X(prefix) \ > >> +prefix##0XOffset = 0.375; \ > >> +prefix##0YOffset = 0.125; \ > >> +prefix##1XOffset = 0.875; \ > >> +prefix##1YOffset = 0.375; \ > >> +prefix##2XOffset = 0.125; \ > >> +prefix##2YOffset = 0.625; \ > >> +prefix##3XOffset = 0.625; \ > >> +prefix##3YOffset = 0.875; > >> + > >> +#define SAMPLE_POS_8X(prefix) \ > >> +prefix##0XOffset = 0.5625; \ > >> +prefix##0YOffset = 0.3125; \ > >> +prefix##1XOffset = 0.4375; \ > >> +prefix##1YOffset = 0.6875; \ > >> +prefix##2XOffset = 0.8125; \ > >> +prefix##2YOffset = 0.5625; \ > >> +prefix##3XOffset = 0.3125; \ > >> +prefix##3YOffset = 0.1875; \ > >> +prefix##4XOffset = 0.1875; \ > >> +prefix##4YOffset = 0.8125; \ > >> +prefix##5XOffset = 0.0625; \ > >> +prefix##5YOffset = 0.4375; \ > >> +prefix##6XOffset = 0.6875; \ > >> +prefix##6YOffset = 0.9375; \ > >> +prefix##7XOffset = 0.9375; \ > >> +prefix##7YOffset = 0.0625; > >> + > >> +#define SAMPLE_POS_16X(prefix) \ > >> +prefix##0XOffset = 0.5625; \ > >> +prefix##0YOffset = 0.5625; \ > >> +prefix##1XOffset = 0.4375; \ > >> +prefix##1YOffset = 0.3125; \ > >> +prefix##2XOffset = 0.3125; \ > >> +prefix##2YOffset = 0.6250; \ > >> +prefix##3XOffset = 0.7500; \ > >> +prefix##3YOffset = 0.4375; \ > >> +prefix##4XOffset = 0.1875; \ > >> +prefix##4YOffset = 0.3750; \ > >> +prefix##5XOffset = 0.6250; \ > >> +prefix##5YOffset = 0.8125; \ > >> +prefix##6XOffset = 0.8125; \ > >> +prefix##6YOffset = 0.6875; \ > >> +prefix##7XOffset = 0.6875; \ > >> +prefix##7YOffset = 0.1875; \ > >> +prefix##8XOffset = 0.3750; \ > >> +prefix##8YOffset = 0.8750; \ > >> +prefix##9XOffset = 0.5000; \ > >> +prefix##9YOffset = 0.0625; \ > >> +prefix##10XOffset = 0.2500; \ > >> +prefix##10YOffset = 0.1250; \ > >> +prefix##11XOffset = 0.1250; \ > >> +prefix##11YOffset = 0.7500; \ > >> +prefix##12XOffset = 0.; \ > >> +prefix##12YOffset = 0.5000; \ > >> +prefix##13XOffset = 0.9375; \ > >> +prefix##13YO
Re: [Mesa-dev] [PATCH 2/3] glsl: Tidy stream handling in merge_qualifier().
On Friday, August 12, 2016 9:44:42 AM PDT Timothy Arceri wrote: > On Thu, 2016-08-11 at 13:43 -0700, Kenneth Graunke wrote: > > The previous commit fixed xfb_buffer handling, which was largely copy > > and pasted from the stream handling. The difference is that stream > > was set in input_layout_mask, so it worked. > > > > However, that's totally rubbish: stream is only valid on geometry > > shader > > outputs. Presumably this was to hack around inout. Instead, apply > > the > > solution I used in the previous fix. > > > > Really, we just need to separate shader interface and parameter > > qualifier handling so this isn't a mess, but this patch at least > > tidies it slightly. > > Agreed. I added a FIXME for this when I added input_layout_mask. Anyway > thanks for fixing this up. > > Series: > > Reviewed-by: Timothy Arceri Yup, I saw your FIXME and couldn't agree more. Then I thought about actually doing it and said 'ugg', that'll probably be a mess :) Thanks! signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH V2 2/2] i965: Change 8X MSAA sample mapping
Thanks for the review. Can you also review the piglit patch?
"multisample_blit_scaled: Change 8X MSAA sample mapping"
On Thu, Aug 11, 2016 at 3:56 PM, Jason Ekstrand wrote:
> This looks good. Thanks! I think we should probably squash it in to the
> other one because there's technically a regression between the two. Both
> are
>
> Reviewed-by: Jason Ekstrand
>
> On Thu, Aug 11, 2016 at 12:28 PM, Anuj Phogat wrote:
>>
>> This is required following the change in 8X sample positions.
>> Fixes the recently modified multisample-scaled-blit piglit tests.
>>
>> Signed-off-by: Anuj Phogat
>> ---
>> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
>> src/mesa/drivers/dri/i965/gen6_multisample_state.c | 2 +-
>> 2 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
>> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
>> index b903de1..f7f685b 100644
>> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
>> @@ -1094,13 +1094,13 @@ blorp_nir_manual_blend_bilinear(nir_builder *b,
>> nir_ssa_def *pos,
>> *
>> * In case of 8x MSAA the two layouts don't match.
>> * sample index layout : -sample number layout :
>> -
>> - *| 0 | 1 || 5
>> | 2 |
>> + *| 0 | 1 || 3
>> | 7 |
>> *-
>> -
>> - *| 2 | 3 || 4
>> | 6 |
>> + *| 2 | 3 || 5
>> | 0 |
>> *-
>> -
>> - *| 4 | 5 || 0
>> | 3 |
>> + *| 4 | 5 || 1
>> | 2 |
>> *-
>> -
>> - *| 6 | 7 || 7
>> | 1 |
>> + *| 6 | 7 || 4
>> | 6 |
>> *-
>> -
>> *
>> * Fortunately, this can be done fairly easily as:
>> @@ -1128,7 +1128,7 @@ blorp_nir_manual_blend_bilinear(nir_builder *b,
>> nir_ssa_def *pos,
>>sample = nir_f2i(b, sample);
>>
>>if (tex_samples == 8) {
>> - sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x17306425),
>> + sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x64210573),
>> nir_ishl(b, sample, nir_imm_int(b,
>> 2))),
>> nir_imm_int(b, 0xf));
>>} else if (tex_samples == 16) {
>> diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
>> b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
>> index a47e323..a59ffec 100644
>> --- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
>> +++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
>> @@ -109,7 +109,7 @@ gen6_set_sample_maps(struct gl_context *ctx)
>> {
>> uint8_t map_2x[2] = {0, 1};
>> uint8_t map_4x[4] = {0, 1, 2, 3};
>> - uint8_t map_8x[8] = {5, 2, 4, 6, 0, 3, 7, 1};
>> + uint8_t map_8x[8] = {3, 7, 5, 0, 1, 2, 4, 6};
>> uint8_t map_16x[16] = { 15, 10, 9, 7, 4, 1, 3, 13,
>> 12, 2, 0, 6, 11, 8, 5, 14 };
>>
>> --
>> 2.5.5
>>
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>
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Re: [Mesa-dev] [PATCH 0/5] isl: Update the format table and add asserts
On Tue, Jul 26, 2016 at 10:04:21PM -0700, Jason Ekstrand wrote: > The real objective of this series is patch 5 which prevents us from > accidentally creating a surface state with a format unsupported by the > hardware. This turns some of the new Vulkan CTS tests from a hang into an > informative crash. In order to get there, however, we needed to update the > format table in isl with some of the new formats added on Haswell and later > generations. In order to do that, we had to fix up the dri driver, and own > the rabbit hole we go! > > At the end of the series, the hangs in the latest CTS are gone (they came > from trying to clear an unsupported image format). With the spelling correction and the removal of the filtering feature for integer formats, patches 1-3 are: Reviewed-by: Nanley Chery > > Jason Ekstrand (5): > i965/surface_formats: Don't advertise 8 or 16-bit RGB formats > isl/formats: Report ETC as being samplable on Bay Trail > isl/formats: Update the table with more samplable formats > anv/image: Don't create invalid render target surfaces > isl/state: Add some asserts about format capabilities > > src/intel/isl/isl_format.c | 48 > + > src/intel/isl/isl_surface_state.c | 5 +++ > src/intel/vulkan/anv_image.c| 13 ++- > src/mesa/drivers/dri/i965/brw_surface_formats.c | 10 ++ > 4 files changed, 60 insertions(+), 16 deletions(-) > > -- > 2.5.0.400.gff86faf > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 3/5] isl/formats: Update the table with more samplable formats
On Thu, Aug 11, 2016 at 11:34:38AM -0700, Nanley Chery wrote:
> On Tue, Jul 26, 2016 at 10:04:24PM -0700, Jason Ekstrand wrote:
> > There were a lot of formats where support was added on Haswell or later but
> > we never updated the format table.
> > ---
> > src/intel/isl/isl_format.c | 30 +++---
> > 1 file changed, 15 insertions(+), 15 deletions(-)
> >
> > diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
> > index 366d32e..73688a7 100644
> > --- a/src/intel/isl/isl_format.c
> > +++ b/src/intel/isl/isl_format.c
> > @@ -218,8 +218,8 @@ static const struct surface_format_info format_info[] =
> > {
> > SF(50, 50, x, x, x, x, x, x, x,x, P8A8_UNORM_PALETTE1)
> > SF( x, x, x, x, x, x, x, x, x,x, A1B5G5R5_UNORM)
> > SF(90, 90, x, x, 90, x, x, x, x,x, A4B4G4R4_UNORM)
> > - SF( x, x, x, x, x, x, x, x, x,x, L8A8_UINT)
> > - SF( x, x, x, x, x, x, x, x, x,x, L8A8_SINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, L8A8_UINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, L8A8_SINT)
> > SF( Y, Y, x, 45, Y, Y, Y, x, x,x, R8_UNORM)
> > SF( Y, Y, x, x, Y, 60, Y, x, x,x, R8_SNORM)
> > SF( Y, x, x, x, Y, x, Y, x, x,x, R8_SINT)
> > @@ -237,10 +237,10 @@ static const struct surface_format_info format_info[]
> > = {
> > SF(45, 45, x, x, x, x, x, x, x,x, P4A4_UNORM_PALETTE1)
> > SF(45, 45, x, x, x, x, x, x, x,x, A4P4_UNORM_PALETTE1)
> > SF( x, x, x, x, x, x, x, x, x,x, Y8_UNORM)
> > - SF( x, x, x, x, x, x, x, x, x,x, L8_UINT)
> > - SF( x, x, x, x, x, x, x, x, x,x, L8_SINT)
> > - SF( x, x, x, x, x, x, x, x, x,x, I8_UINT)
> > - SF( x, x, x, x, x, x, x, x, x,x, I8_SINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, L8_UINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, L8_SINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, I8_UINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, I8_SINT)
> > SF(45, 45, x, x, x, x, x, x, x,x, DXT1_RGB_SRGB)
> > SF( Y, Y, x, x, x, x, x, x, x,x, R1_UNORM)
> > SF( Y, Y, x, Y, Y, x, x, x, 60,x, YCRCB_NORMAL)
> > @@ -261,8 +261,8 @@ static const struct surface_format_info format_info[] =
> > {
> > SF( Y, Y, x, x, x, x, x, x, x,x, DXT1_RGB)
> > /* smpl filt shad CK RT AB VB SO color ccs_e */
> > SF( Y, Y, x, x, x, x, x, x, x,x, FXT1)
> > - SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_UNORM)
> > - SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_SNORM)
> > + SF(75, 75, x, x, x, x, Y, x, x,x, R8G8B8_UNORM)
> > + SF(75, 75, x, x, x, x, Y, x, x,x, R8G8B8_SNORM)
> > SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_SSCALED)
> > SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_USCALED)
> > SF( x, x, x, x, x, x, Y, x, x,x, R64G64B64A64_FLOAT)
> > @@ -270,8 +270,8 @@ static const struct surface_format_info format_info[] =
> > {
> > SF( Y, Y, x, x, x, x, x, x, x,x, BC4_SNORM)
> > SF( Y, Y, x, x, x, x, x, x, x,x, BC5_SNORM)
> > SF(50, 50, x, x, x, x, 60, x, x,x, R16G16B16_FLOAT)
> > - SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_UNORM)
> > - SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_SNORM)
> > + SF(75, 75, x, x, x, x, Y, x, x,x, R16G16B16_UNORM)
> > + SF(75, 75, x, x, x, x, Y, x, x,x, R16G16B16_SNORM)
> > SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_SSCALED)
> > SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_USCALED)
> > SF(70, 70, x, x, x, x, x, x, x,x, BC6H_SF16)
> > @@ -279,7 +279,7 @@ static const struct surface_format_info format_info[] =
> > {
> > SF(70, 70, x, x, x, x, x, x, x,x, BC7_UNORM_SRGB)
> > SF(70, 70, x, x, x, x, x, x, x,x, BC6H_UF16)
> > SF( x, x, x, x, x, x, x, x, x,x, PLANAR_420_8)
> > - SF( x, x, x, x, x, x, x, x, x,x, R8G8B8_UNORM_SRGB)
> > + SF(75, 75, x, x, x, x, x, x, x,x, R8G8B8_UNORM_SRGB)
>
> I could not find support for this change in Vol7 of the HSW PRM. I did
> find such support for BDW however.
>
(For the list) Jason and I had a chance to discuss this in person. He
showed me BSpec page which mentioned HSW's support for this format.
- Nanley
> - Nanley
>
> > SF(80, 80, x, x, x, x, x, x, x,x, ETC1_RGB8)
> > SF(80, 80, x, x, x, x, x, x, x,x, ETC2_RGB8)
> > SF(80, 80, x, x, x, x, x, x, x,x, EAC_R11)
> > @@ -287,8 +287,8 @@ static const struct surface_format_info format_info[] =
> > {
> > SF(80, 80, x, x, x, x, x, x, x,x, EAC_SIGNED_R11)
> > SF(80, 80,
Re: [Mesa-dev] Question about tesselation shader out varyings and transform feedback
On Thu, 2016-08-11 at 17:10 +0200, Alejandro Piñeiro wrote:
> On 05/08/16 12:20, Alejandro Piñeiro wrote:
> >
> > On 05/08/16 01:53, Timothy Arceri wrote:
> > >
> > > On Thu, 2016-08-04 at 18:36 +0200, Alejandro Piñeiro wrote:
> > > >
> > > > Hi,
> > > >
> > > > these days I have been trying to fix a test that uses transform
> > > > feedback
> > > > on the out varying of a tessellation shader. The relevant part
> > > > on
> > > > that
> > > > shader is like this:
> > > >
> > > > layout (vertices=4) out;
> > > >
> > > > out block { vec4 value; } user_out[];
> > > >
> > > > The test tries to use block.value as the varying name when
> > > > calling
> > > > glTransformFeedbackVaryings, in order to get the data of the 4
> > > > vertices.
> > > > The test fails because on link time, it doesn't find that
> > > > varying
> > > > name.
> > > >
> > > > On mesa, when linked, mesa tfeedback_candidate_generator (at
> > > > src/compiler/glsl/link_varyings) adds to the hashmap of
> > > > possible
> > > > varyings for transform feedback the following names:
> > > > block[0].value,
> > > > block[1].value, block[2].value, block[3].value. If I change the
> > > > test
> > > > to
> > > > use those 4 varyings names, instead of try to get the array
> > > > directly,
> > > > the test passes.
> > > >
> > > > So now is the moment to justify who is wrong per-spec, if mesa
> > > > or the
> > > > test. At this moment Im biased to conclude that the test is
> > > > wrong.
> > > > But
> > > > after reading transform feedback specs (ext, feedback2,
> > > > feedback3,
> > > > gl44)
> > > > and tessellation shader, I was not able to find anything.
> > > >
> > > > Could someone (I bet that the best person is Timothy Arceri)
> > > > guide me
> > > > a
> > > > little to know in which part of the spec should I look for?
> > > For block arrays block[0].value,> block[1].value, block[2].value,
> > > block[3].value are the correct strings for matching transform
> > > feedback
> > > varyings. I forget which spec states this but its in there
> > > somewhere I
> > > recall looking for it and finding it.
> > Ok, thanks for confirming. BTW, while looking for info for this
> > email
> > (see below) I found this paragraph at ARB_separate_shader_objects,
> > that
> > I think that is what I was searching:
> >
> > Tessellation control shader per-vertex output variables and
> > blocks and
> > tessellation control, tessellation evaluation, and geometry
> > shader
> > per-vertex input variables and blocks are required to be
> > declared as
> > arrays, with each element representing input or output values
> > for a single
> > vertex of a multi-vertex primitive. For the purposes of
> > interface
> > matching, such variables and blocks are treated as though they
> > were not
> > declared as arrays.
> >
> >
> > Specifically the last sentence. What do you think?
>
> I think that I found a better part of the spec. From GL spec 4.4,
> section "7.3.1 Program interfaces":
>
> "For interfaces involving variables, interface blocks, or
> subroutines,
> the entries of active resource lists are
> generated as follows:"
>
> "• For an active interface block declared as an array of instances,
> separate en-
> tries will be generated for each active instance. The name of the
> instance
> is formed by concatenating the block name, the "[" character, an
> integer
> identifying the instance number, and the "]" character."
>
> Although I think that it is clear, Timothy, do you mind to confirm if
> that paragraph justifies properly that the test was wrong, and needs
> to
> use block[1].value, block[2].value, etc?
No, as I said before I think you likely need to remove the outermost
array from tcs outputs. See: get_varying_type()
>
> Thanks in advance.
>
> BR
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Re: [Mesa-dev] [PATCH] anv: Use macro to avoid code duplication for sample positions
On Thu, Aug 11, 2016 at 4:06 PM, Jason Ekstrand wrote: > Thanks! > > Reviewed-by: Jason Ekstrand > > On Thu, Aug 11, 2016 at 10:39 AM, Anuj Phogat wrote: >> >> Suggested-by: Jason Ekstrand >> Signed-off-by: Anuj Phogat >> --- >> src/intel/vulkan/genX_multisample.h | 95 >> +++ >> src/intel/vulkan/genX_pipeline_util.h | 35 ++--- >> src/intel/vulkan/genX_state.c | 68 +++-- >> 3 files changed, 106 insertions(+), 92 deletions(-) >> create mode 100644 src/intel/vulkan/genX_multisample.h >> >> diff --git a/src/intel/vulkan/genX_multisample.h >> b/src/intel/vulkan/genX_multisample.h >> new file mode 100644 >> index 000..0deb48f >> --- /dev/null >> +++ b/src/intel/vulkan/genX_multisample.h >> @@ -0,0 +1,95 @@ >> +/* >> + * Copyright © 2016 Intel Corporation >> + * >> + * Permission is hereby granted, free of charge, to any person obtaining >> a >> + * copy of this software and associated documentation files (the >> "Software"), >> + * to deal in the Software without restriction, including without >> limitation >> + * the rights to use, copy, modify, merge, publish, distribute, >> sublicense, >> + * and/or sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice (including the >> next >> + * paragraph) shall be included in all copies or substantial portions of >> the >> + * Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT >> SHALL >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR >> OTHER >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER >> DEALINGS >> + * IN THE SOFTWARE. >> + */ >> +#pragma once >> + >> +#define SAMPLE_POS_1X(prefix) \ >> +prefix##0XOffset = 0.5; \ >> +prefix##0YOffset = 0.5; >> + >> +#define SAMPLE_POS_2X(prefix) \ >> +prefix##0XOffset = 0.25; \ > > > If I were to write the patch, I would probably make it > "prefix##Sample0Offset = 0.25" but this is totally fine and you don't need > to rework it. > That's what I did initially but compiler wasn't happy with a prefix ending with '.' in "ms.". There might be a better way to avoid this than what I came up with. >> >> +prefix##0YOffset = 0.25; \ >> +prefix##1XOffset = 0.75; \ >> +prefix##1YOffset = 0.75; >> + >> +#define SAMPLE_POS_4X(prefix) \ >> +prefix##0XOffset = 0.375; \ >> +prefix##0YOffset = 0.125; \ >> +prefix##1XOffset = 0.875; \ >> +prefix##1YOffset = 0.375; \ >> +prefix##2XOffset = 0.125; \ >> +prefix##2YOffset = 0.625; \ >> +prefix##3XOffset = 0.625; \ >> +prefix##3YOffset = 0.875; >> + >> +#define SAMPLE_POS_8X(prefix) \ >> +prefix##0XOffset = 0.5625; \ >> +prefix##0YOffset = 0.3125; \ >> +prefix##1XOffset = 0.4375; \ >> +prefix##1YOffset = 0.6875; \ >> +prefix##2XOffset = 0.8125; \ >> +prefix##2YOffset = 0.5625; \ >> +prefix##3XOffset = 0.3125; \ >> +prefix##3YOffset = 0.1875; \ >> +prefix##4XOffset = 0.1875; \ >> +prefix##4YOffset = 0.8125; \ >> +prefix##5XOffset = 0.0625; \ >> +prefix##5YOffset = 0.4375; \ >> +prefix##6XOffset = 0.6875; \ >> +prefix##6YOffset = 0.9375; \ >> +prefix##7XOffset = 0.9375; \ >> +prefix##7YOffset = 0.0625; >> + >> +#define SAMPLE_POS_16X(prefix) \ >> +prefix##0XOffset = 0.5625; \ >> +prefix##0YOffset = 0.5625; \ >> +prefix##1XOffset = 0.4375; \ >> +prefix##1YOffset = 0.3125; \ >> +prefix##2XOffset = 0.3125; \ >> +prefix##2YOffset = 0.6250; \ >> +prefix##3XOffset = 0.7500; \ >> +prefix##3YOffset = 0.4375; \ >> +prefix##4XOffset = 0.1875; \ >> +prefix##4YOffset = 0.3750; \ >> +prefix##5XOffset = 0.6250; \ >> +prefix##5YOffset = 0.8125; \ >> +prefix##6XOffset = 0.8125; \ >> +prefix##6YOffset = 0.6875; \ >> +prefix##7XOffset = 0.6875; \ >> +prefix##7YOffset = 0.1875; \ >> +prefix##8XOffset = 0.3750; \ >> +prefix##8YOffset = 0.8750; \ >> +prefix##9XOffset = 0.5000; \ >> +prefix##9YOffset = 0.0625; \ >> +prefix##10XOffset = 0.2500; \ >> +prefix##10YOffset = 0.1250; \ >> +prefix##11XOffset = 0.1250; \ >> +prefix##11YOffset = 0.7500; \ >> +prefix##12XOffset = 0.; \ >> +prefix##12YOffset = 0.5000; \ >> +prefix##13XOffset = 0.9375; \ >> +prefix##13YOffset = 0.2500; \ >> +prefix##14XOffset = 0.8750; \ >> +prefix##14YOffset = 0.9375; \ >> +prefix##15XOffset = 0.0625; \ >> +prefix##15YOffset = 0.; >> diff --git a/src/intel/vulkan/genX_pipeline_util.h >> b/src/intel/vulkan/genX_pipeline_util.h >> index 64b89cd..cf2adb0 100644 >> --- a/src/intel/vulkan/genX_pipeline_util.h >> +++ b/src/intel/vulkan/genX_pipeline_util.h >> @@ -22,6 +22,7 @@
Re: [Mesa-dev] [PATCH 0/5] isl: Update the format table and add asserts
On Thu, Aug 11, 2016 at 04:22:04PM -0700, Jason Ekstrand wrote: > On Thu, Aug 11, 2016 at 12:55 PM, Nanley Chery > wrote: > > > On Tue, Jul 26, 2016 at 10:04:21PM -0700, Jason Ekstrand wrote: > > > The real objective of this series is patch 5 which prevents us from > > > accidentally creating a surface state with a format unsupported by the > > > hardware. This turns some of the new Vulkan CTS tests from a hang into > > an > > > informative crash. In order to get there, however, we needed to update > > the > > > format table in isl with some of the new formats added on Haswell and > > later > > > generations. In order to do that, we had to fix up the dri driver, and > > own > > > the rabbit hole we go! > > > > > > > Contrary to your introduction, I cannot see how patches 4 and 5 are > > dependent > > on patches 1-3. Could you please explain this further? > > > > 4 doesn't depend on 1-3 because it's only render and 1-3 are only for > sampling. I'm not sure about 5. It may not depend on 2-3 because if those > formats aren't returning sampling support, applications shouldn't be > creating surfaces with them. I'm not 100% sure though. :/ No problem. I just wanted to make sure I wasn't missing an important interaction between the two patch sets. - Nanley > > --Jason > > > > - Nanley > > > > > At the end of the series, the hangs in the latest CTS are gone (they came > > > from trying to clear an unsupported image format). > > > > > > Jason Ekstrand (5): > > > i965/surface_formats: Don't advertise 8 or 16-bit RGB formats > > > isl/formats: Report ETC as being samplable on Bay Trail > > > isl/formats: Update the table with more samplable formats > > > anv/image: Don't create invalid render target surfaces > > > isl/state: Add some asserts about format capabilities > > > > > > src/intel/isl/isl_format.c | 48 > > + > > > src/intel/isl/isl_surface_state.c | 5 +++ > > > src/intel/vulkan/anv_image.c| 13 ++- > > > src/mesa/drivers/dri/i965/brw_surface_formats.c | 10 ++ > > > 4 files changed, 60 insertions(+), 16 deletions(-) > > > > > > -- > > > 2.5.0.400.gff86faf > > > > > > ___ > > > mesa-dev mailing list > > > mesa-dev@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/3] glsl: Tidy stream handling in merge_qualifier().
On Thu, 2016-08-11 at 13:43 -0700, Kenneth Graunke wrote:
> The previous commit fixed xfb_buffer handling, which was largely copy
> and pasted from the stream handling. The difference is that stream
> was set in input_layout_mask, so it worked.
>
> However, that's totally rubbish: stream is only valid on geometry
> shader
> outputs. Presumably this was to hack around inout. Instead, apply
> the
> solution I used in the previous fix.
>
> Really, we just need to separate shader interface and parameter
> qualifier handling so this isn't a mess, but this patch at least
> tidies it slightly.
Agreed. I added a FIXME for this when I added input_layout_mask. Anyway
thanks for fixing this up.
Series:
Reviewed-by: Timothy Arceri
>
> Cc: Timothy Arceri
> Signed-off-by: Kenneth Graunke
> ---
> src/compiler/glsl/ast_type.cpp | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/src/compiler/glsl/ast_type.cpp
> b/src/compiler/glsl/ast_type.cpp
> index 248b647..cabc698 100644
> --- a/src/compiler/glsl/ast_type.cpp
> +++ b/src/compiler/glsl/ast_type.cpp
> @@ -178,8 +178,6 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
> if (state->stage == MESA_SHADER_GEOMETRY) {
> allowed_duplicates_mask.flags.i |=
> stream_layout_mask.flags.i;
> - input_layout_mask.flags.i |=
> - stream_layout_mask.flags.i;
> }
>
> if (is_single_layout_merge && !state->has_enhanced_layouts() &&
> @@ -229,7 +227,8 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
> if (q.flags.q.stream) {
> this->flags.q.stream = 1;
> this->stream = q.stream;
> - } else if (!this->flags.q.stream && this->flags.q.out) {
> + } else if (!this->flags.q.stream && this->flags.q.out &&
> +!this->flags.q.in) {
> /* Assign default global stream value */
> this->flags.q.stream = 1;
> this->stream = state->out_qualifier->stream;
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Re: [Mesa-dev] [PATCH 1/5] i965/surface_formats: Don't advertise 8 or 16-bit RGB formats
On Thu, Aug 11, 2016 at 04:23:51PM -0700, Jason Ekstrand wrote: > On Thu, Aug 11, 2016 at 11:26 AM, Nanley Chery > wrote: > > > On Tue, Jul 26, 2016 at 10:04:22PM -0700, Jason Ekstrand wrote: > > > We have implicitly been not advertising these formats since we had them > > > turned off in the format capabilities table. We are about to update that > > > table and this prevents a change in behavior. The only change in > > behavior > > > created by this patch is that we no longer advertise support for > > > R16G16B16_FLOAT which means that it's now renderable which seems like a > > > bonus. Maybe someday we'll want to change things to start supporting > > > > I don't understand this sentence. Assuming "renderable" means that we can > > render to a texture with such a format, why does preventing the user from > > creating an R16G16B16_FLOAT texture mean that it's now renderable? > > > > Because mesa will fall back to R16G16B16A16_FLOAT and fake RGB. That > format is renderable. > Got it. Thanks for the clarification. - Nanley > > > > > - Nanley > > > > > 16-bit RGB formats natively but, at the moment, there's no need. > > > --- > > > src/mesa/drivers/dri/i965/brw_surface_formats.c | 10 ++ > > > 1 file changed, 10 insertions(+) > > > > > > diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c > > b/src/mesa/drivers/dri/i965/brw_surface_formats.c > > > index 2543f4b..69d3bd4 100644 > > > --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c > > > +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c > > > @@ -311,6 +311,16 @@ brw_init_surface_formats(struct brw_context *brw) > > >if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32) > > >continue; > > > > > > + /* Don't advertisel 8 and 16-bit RGB formats to core mesa. This > > ensures > > > + * that they are renderable from an API perspective since core > > mesa will > > > + * fall back to RGBA or RGBX (we can't render to non-power-of-two > > > + * formats). For 8-bit, formats, this also keeps us from hitting > > some > > > + * nasty corners in intel_miptree_map_blit if you ever try to map > > one. > > > + */ > > > + int format_size = _mesa_get_format_bytes(format); > > > + if (format_size == 3 || format_size == 6) > > > + continue; > > > + > > >if (isl_format_supports_sampling(devinfo, texture) && > > >(isl_format_supports_filtering(devinfo, texture) || > > is_integer)) > > >ctx->TextureFormatSupported[format] = true; > > > -- > > > 2.5.0.400.gff86faf > > > > > > ___ > > > mesa-dev mailing list > > > mesa-dev@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radeonsi: initialize and finalize the LLVM function pass manager
From: Marek Olšák
we should do that allegedly
---
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index d75311e..e04e26a 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1918,21 +1918,23 @@ void radeon_llvm_finalize_module(struct
radeon_llvm_context *ctx)
LLVMAddPromoteMemoryToRegisterPass(gallivm->passmgr);
/* Add some optimization passes */
LLVMAddScalarReplAggregatesPass(gallivm->passmgr);
LLVMAddLICMPass(gallivm->passmgr);
LLVMAddAggressiveDCEPass(gallivm->passmgr);
LLVMAddCFGSimplificationPass(gallivm->passmgr);
LLVMAddInstructionCombiningPass(gallivm->passmgr);
/* Run the pass */
+ LLVMInitializeFunctionPassManager(gallivm->passmgr);
LLVMRunFunctionPassManager(gallivm->passmgr, ctx->main_fn);
+ LLVMFinalizeFunctionPassManager(gallivm->passmgr);
LLVMDisposeBuilder(gallivm->builder);
LLVMDisposePassManager(gallivm->passmgr);
gallivm_dispose_target_library_info(target_library_info);
}
void radeon_llvm_dispose(struct radeon_llvm_context *ctx)
{
LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module);
LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context);
--
2.7.4
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Re: [Mesa-dev] [PATCH 3/5] isl/formats: Update the table with more samplable formats
On Thu, Aug 11, 2016 at 12:14 PM, Nanley Chery
wrote:
> On Tue, Jul 26, 2016 at 10:04:24PM -0700, Jason Ekstrand wrote:
> > There were a lot of formats where support was added on Haswell or later
> but
> > we never updated the format table.
> > ---
> > src/intel/isl/isl_format.c | 30 +++---
> > 1 file changed, 15 insertions(+), 15 deletions(-)
> >
> > diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
> > index 366d32e..73688a7 100644
> > --- a/src/intel/isl/isl_format.c
> > +++ b/src/intel/isl/isl_format.c
> > @@ -218,8 +218,8 @@ static const struct surface_format_info
> format_info[] = {
> > SF(50, 50, x, x, x, x, x, x, x,x, P8A8_UNORM_PALETTE1)
> > SF( x, x, x, x, x, x, x, x, x,x, A1B5G5R5_UNORM)
> > SF(90, 90, x, x, 90, x, x, x, x,x, A4B4G4R4_UNORM)
> > - SF( x, x, x, x, x, x, x, x, x,x, L8A8_UINT)
> > - SF( x, x, x, x, x, x, x, x, x,x, L8A8_SINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, L8A8_UINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, L8A8_SINT)
>
> How were you able to determine that these formats are filterable? In
> this table, it generally seems to be the case that integer formats are
> not filterable.
>
Oops. You're right. Too much copy+paste
>
> - Nanley
>
> > SF( Y, Y, x, 45, Y, Y, Y, x, x,x, R8_UNORM)
> > SF( Y, Y, x, x, Y, 60, Y, x, x,x, R8_SNORM)
> > SF( Y, x, x, x, Y, x, Y, x, x,x, R8_SINT)
> > @@ -237,10 +237,10 @@ static const struct surface_format_info
> format_info[] = {
> > SF(45, 45, x, x, x, x, x, x, x,x, P4A4_UNORM_PALETTE1)
> > SF(45, 45, x, x, x, x, x, x, x,x, A4P4_UNORM_PALETTE1)
> > SF( x, x, x, x, x, x, x, x, x,x, Y8_UNORM)
> > - SF( x, x, x, x, x, x, x, x, x,x, L8_UINT)
> > - SF( x, x, x, x, x, x, x, x, x,x, L8_SINT)
> > - SF( x, x, x, x, x, x, x, x, x,x, I8_UINT)
> > - SF( x, x, x, x, x, x, x, x, x,x, I8_SINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, L8_UINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, L8_SINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, I8_UINT)
> > + SF(90, 90, x, x, x, x, x, x, x,x, I8_SINT)
> > SF(45, 45, x, x, x, x, x, x, x,x, DXT1_RGB_SRGB)
> > SF( Y, Y, x, x, x, x, x, x, x,x, R1_UNORM)
> > SF( Y, Y, x, Y, Y, x, x, x, 60,x, YCRCB_NORMAL)
> > @@ -261,8 +261,8 @@ static const struct surface_format_info
> format_info[] = {
> > SF( Y, Y, x, x, x, x, x, x, x,x, DXT1_RGB)
> > /* smpl filt shad CK RT AB VB SO color ccs_e */
> > SF( Y, Y, x, x, x, x, x, x, x,x, FXT1)
> > - SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_UNORM)
> > - SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_SNORM)
> > + SF(75, 75, x, x, x, x, Y, x, x,x, R8G8B8_UNORM)
> > + SF(75, 75, x, x, x, x, Y, x, x,x, R8G8B8_SNORM)
> > SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_SSCALED)
> > SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_USCALED)
> > SF( x, x, x, x, x, x, Y, x, x,x, R64G64B64A64_FLOAT)
> > @@ -270,8 +270,8 @@ static const struct surface_format_info
> format_info[] = {
> > SF( Y, Y, x, x, x, x, x, x, x,x, BC4_SNORM)
> > SF( Y, Y, x, x, x, x, x, x, x,x, BC5_SNORM)
> > SF(50, 50, x, x, x, x, 60, x, x,x, R16G16B16_FLOAT)
> > - SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_UNORM)
> > - SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_SNORM)
> > + SF(75, 75, x, x, x, x, Y, x, x,x, R16G16B16_UNORM)
> > + SF(75, 75, x, x, x, x, Y, x, x,x, R16G16B16_SNORM)
> > SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_SSCALED)
> > SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_USCALED)
> > SF(70, 70, x, x, x, x, x, x, x,x, BC6H_SF16)
> > @@ -279,7 +279,7 @@ static const struct surface_format_info
> format_info[] = {
> > SF(70, 70, x, x, x, x, x, x, x,x, BC7_UNORM_SRGB)
> > SF(70, 70, x, x, x, x, x, x, x,x, BC6H_UF16)
> > SF( x, x, x, x, x, x, x, x, x,x, PLANAR_420_8)
> > - SF( x, x, x, x, x, x, x, x, x,x, R8G8B8_UNORM_SRGB)
> > + SF(75, 75, x, x, x, x, x, x, x,x, R8G8B8_UNORM_SRGB)
> > SF(80, 80, x, x, x, x, x, x, x,x, ETC1_RGB8)
> > SF(80, 80, x, x, x, x, x, x, x,x, ETC2_RGB8)
> > SF(80, 80, x, x, x, x, x, x, x,x, EAC_R11)
> > @@ -287,8 +287,8 @@ static const struct surface_format_info
> format_info[] = {
> > SF(80, 80, x, x, x, x, x, x, x,x, EAC_SIGNED_R11)
> > SF(80, 80, x, x, x, x, x, x, x,x, EAC_SIGNED_RG11)
> > SF(80, 80, x,
Re: [Mesa-dev] [PATCH 1/5] i965/surface_formats: Don't advertise 8 or 16-bit RGB formats
On Thu, Aug 11, 2016 at 11:26 AM, Nanley Chery wrote: > On Tue, Jul 26, 2016 at 10:04:22PM -0700, Jason Ekstrand wrote: > > We have implicitly been not advertising these formats since we had them > > turned off in the format capabilities table. We are about to update that > > table and this prevents a change in behavior. The only change in > behavior > > created by this patch is that we no longer advertise support for > > R16G16B16_FLOAT which means that it's now renderable which seems like a > > bonus. Maybe someday we'll want to change things to start supporting > > I don't understand this sentence. Assuming "renderable" means that we can > render to a texture with such a format, why does preventing the user from > creating an R16G16B16_FLOAT texture mean that it's now renderable? > Because mesa will fall back to R16G16B16A16_FLOAT and fake RGB. That format is renderable. > > - Nanley > > > 16-bit RGB formats natively but, at the moment, there's no need. > > --- > > src/mesa/drivers/dri/i965/brw_surface_formats.c | 10 ++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c > b/src/mesa/drivers/dri/i965/brw_surface_formats.c > > index 2543f4b..69d3bd4 100644 > > --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c > > +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c > > @@ -311,6 +311,16 @@ brw_init_surface_formats(struct brw_context *brw) > >if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32) > >continue; > > > > + /* Don't advertisel 8 and 16-bit RGB formats to core mesa. This > ensures > > + * that they are renderable from an API perspective since core > mesa will > > + * fall back to RGBA or RGBX (we can't render to non-power-of-two > > + * formats). For 8-bit, formats, this also keeps us from hitting > some > > + * nasty corners in intel_miptree_map_blit if you ever try to map > one. > > + */ > > + int format_size = _mesa_get_format_bytes(format); > > + if (format_size == 3 || format_size == 6) > > + continue; > > + > >if (isl_format_supports_sampling(devinfo, texture) && > >(isl_format_supports_filtering(devinfo, texture) || > is_integer)) > >ctx->TextureFormatSupported[format] = true; > > -- > > 2.5.0.400.gff86faf > > > > ___ > > mesa-dev mailing list > > mesa-dev@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 02/16] st_glsl_to_tgsi: use calloc the way it's meant to be used
Reviewed-by: Marek Olšák
Marek
On Wed, Aug 10, 2016 at 9:23 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> ---
> src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 362559f..89e5c4d 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -6031,21 +6031,21 @@ st_translate_program(
>goto out;
> }
>
> t->procType = procType;
> t->inputMapping = inputMapping;
> t->outputMapping = outputMapping;
> t->ureg = ureg;
> t->num_temp_arrays = program->next_array;
> if (t->num_temp_arrays)
>t->arrays = (struct ureg_dst*)
> - calloc(1, sizeof(t->arrays[0]) * t->num_temp_arrays);
> + calloc(t->num_temp_arrays, sizeof(t->arrays[0]));
>
> /*
> * Declare input attributes.
> */
> switch (procType) {
> case PIPE_SHADER_FRAGMENT:
>for (i = 0; i < numInputs; i++) {
> unsigned array_id = 0;
> unsigned array_size;
>
> --
> 2.7.4
>
> ___
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Re: [Mesa-dev] [PATCH 01/16] tgsi/scan: add tgsi_scan_arrays
This patch:
Reviewed-by: Marek Olšák
Marek
On Wed, Aug 10, 2016 at 9:23 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> ---
> src/gallium/auxiliary/tgsi/tgsi_scan.c | 76
> ++
> src/gallium/auxiliary/tgsi/tgsi_scan.h | 17
> 2 files changed, 93 insertions(+)
>
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c
> b/src/gallium/auxiliary/tgsi/tgsi_scan.c
> index 98d86fc..0167e22 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
> @@ -628,20 +628,96 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
>info->file_max[TGSI_FILE_INPUT] =
> MAX2(info->file_max[TGSI_FILE_INPUT], num_verts - 1);
>for (j = 0; j < num_verts; ++j) {
> info->file_mask[TGSI_FILE_INPUT] |= (1 << j);
>}
> }
>
> tgsi_parse_free(&parse);
> }
>
> +/**
> + * Collect information about the arrays of a given register file.
> + *
> + * @param tokens TGSI shader
> + * @param file the register file to scan through
> + * @param max_array_id number of entries in @p arrays; should be equal to the
> + * highest array id, i.e.
> tgsi_shader_info::array_max[file].
> + * @param arrays info for array of each ID will be written to arrays[ID - 1].
> + */
> +void
> +tgsi_scan_arrays(const struct tgsi_token *tokens,
> + unsigned file,
> + unsigned max_array_id,
> + struct tgsi_array_info *arrays)
> +{
> + struct tgsi_parse_context parse;
> +
> + if (tgsi_parse_init(&parse, tokens) != TGSI_PARSE_OK) {
> + debug_printf("tgsi_parse_init() failed in tgsi_scan_arrays()!\n");
> + return;
> + }
> +
> + memset(arrays, 0, sizeof(arrays[0]) * max_array_id);
> +
> + while (!tgsi_parse_end_of_tokens(&parse)) {
> + struct tgsi_full_instruction *inst;
> +
> + tgsi_parse_token(&parse);
> +
> + if (parse.FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
> + struct tgsi_full_declaration *decl =
> &parse.FullToken.FullDeclaration;
> +
> + if (decl->Declaration.Array && decl->Declaration.File == file &&
> + decl->Array.ArrayID > 0 && decl->Array.ArrayID <= max_array_id)
> {
> +struct tgsi_array_info *array = &arrays[decl->Array.ArrayID - 1];
> +assert(!array->declared);
> +array->declared = true;
> +array->range = decl->Range;
> + }
> + }
> +
> + if (parse.FullToken.Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
> + continue;
> +
> + inst = &parse.FullToken.FullInstruction;
> + for (unsigned i = 0; i < inst->Instruction.NumDstRegs; i++) {
> + const struct tgsi_full_dst_register *dst = &inst->Dst[i];
> + if (dst->Register.File != file)
> +continue;
> +
> + if (dst->Register.Indirect) {
> +if (dst->Indirect.ArrayID > 0 &&
> +dst->Indirect.ArrayID <= max_array_id) {
> + arrays[dst->Indirect.ArrayID - 1].writemask |=
> dst->Register.WriteMask;
> +} else {
> + /* Indirect writes without an ArrayID can write anywhere. */
> + for (unsigned j = 0; j < max_array_id; ++j)
> + arrays[j].writemask |= dst->Register.WriteMask;
> +}
> + } else {
> +/* Check whether the write falls into any of the arrays anyway.
> */
> +for (unsigned j = 0; j < max_array_id; ++j) {
> + struct tgsi_array_info *array = &arrays[j];
> + if (array->declared &&
> + dst->Register.Index >= array->range.First &&
> + dst->Register.Index <= array->range.Last)
> + array->writemask |= dst->Register.WriteMask;
> +}
> + }
> + }
> + }
> +
> + tgsi_parse_free(&parse);
> +
> + return;
> +}
>
>
> /**
> * Check if the given shader is a "passthrough" shader consisting of only
> * MOV instructions of the form: MOV OUT[n], IN[n]
> *
> */
> boolean
> tgsi_is_passthrough_shader(const struct tgsi_token *tokens)
> {
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.h
> b/src/gallium/auxiliary/tgsi/tgsi_scan.h
> index f7eefa4..30d0146 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_scan.h
> +++ b/src/gallium/auxiliary/tgsi/tgsi_scan.h
> @@ -142,23 +142,40 @@ struct tgsi_shader_info
> unsigned indirect_files_written;
>
> unsigned properties[TGSI_PROPERTY_COUNT]; /* index with TGSI_PROPERTY_ */
>
> /**
> * Max nesting limit of loops/if's
> */
> unsigned max_depth;
> };
>
> +struct tgsi_array_info
> +{
> + /** Whether an array with this ID was declared. */
> + bool declared;
> +
> + /** The OR of all writemasks used to write to this array. */
> + ubyte writemask;
> +
> + /** The range with which the array was declared. */
> + struct tgsi_declaration_range range;
> +};
> +
> extern void
> tgsi_scan_shader(const struct tgsi
Re: [Mesa-dev] [PATCH 0/5] isl: Update the format table and add asserts
On Thu, Aug 11, 2016 at 12:55 PM, Nanley Chery wrote: > On Tue, Jul 26, 2016 at 10:04:21PM -0700, Jason Ekstrand wrote: > > The real objective of this series is patch 5 which prevents us from > > accidentally creating a surface state with a format unsupported by the > > hardware. This turns some of the new Vulkan CTS tests from a hang into > an > > informative crash. In order to get there, however, we needed to update > the > > format table in isl with some of the new formats added on Haswell and > later > > generations. In order to do that, we had to fix up the dri driver, and > own > > the rabbit hole we go! > > > > Contrary to your introduction, I cannot see how patches 4 and 5 are > dependent > on patches 1-3. Could you please explain this further? > 4 doesn't depend on 1-3 because it's only render and 1-3 are only for sampling. I'm not sure about 5. It may not depend on 2-3 because if those formats aren't returning sampling support, applications shouldn't be creating surfaces with them. I'm not 100% sure though. :/ --Jason > - Nanley > > > At the end of the series, the hangs in the latest CTS are gone (they came > > from trying to clear an unsupported image format). > > > > Jason Ekstrand (5): > > i965/surface_formats: Don't advertise 8 or 16-bit RGB formats > > isl/formats: Report ETC as being samplable on Bay Trail > > isl/formats: Update the table with more samplable formats > > anv/image: Don't create invalid render target surfaces > > isl/state: Add some asserts about format capabilities > > > > src/intel/isl/isl_format.c | 48 > + > > src/intel/isl/isl_surface_state.c | 5 +++ > > src/intel/vulkan/anv_image.c| 13 ++- > > src/mesa/drivers/dri/i965/brw_surface_formats.c | 10 ++ > > 4 files changed, 60 insertions(+), 16 deletions(-) > > > > -- > > 2.5.0.400.gff86faf > > > > ___ > > mesa-dev mailing list > > mesa-dev@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] anv: Use macro to avoid code duplication for sample positions
Thanks!
Reviewed-by: Jason Ekstrand
On Thu, Aug 11, 2016 at 10:39 AM, Anuj Phogat wrote:
> Suggested-by: Jason Ekstrand
> Signed-off-by: Anuj Phogat
> ---
> src/intel/vulkan/genX_multisample.h | 95 ++
> +
> src/intel/vulkan/genX_pipeline_util.h | 35 ++---
> src/intel/vulkan/genX_state.c | 68 +++--
> 3 files changed, 106 insertions(+), 92 deletions(-)
> create mode 100644 src/intel/vulkan/genX_multisample.h
>
> diff --git a/src/intel/vulkan/genX_multisample.h b/src/intel/vulkan/genX_
> multisample.h
> new file mode 100644
> index 000..0deb48f
> --- /dev/null
> +++ b/src/intel/vulkan/genX_multisample.h
> @@ -0,0 +1,95 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> next
> + * paragraph) shall be included in all copies or substantial portions of
> the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +#pragma once
> +
> +#define SAMPLE_POS_1X(prefix) \
> +prefix##0XOffset = 0.5; \
> +prefix##0YOffset = 0.5;
> +
> +#define SAMPLE_POS_2X(prefix) \
> +prefix##0XOffset = 0.25; \
>
If I were to write the patch, I would probably make it
"prefix##Sample0Offset = 0.25" but this is totally fine and you don't need
to rework it.
> +prefix##0YOffset = 0.25; \
> +prefix##1XOffset = 0.75; \
> +prefix##1YOffset = 0.75;
> +
> +#define SAMPLE_POS_4X(prefix) \
> +prefix##0XOffset = 0.375; \
> +prefix##0YOffset = 0.125; \
> +prefix##1XOffset = 0.875; \
> +prefix##1YOffset = 0.375; \
> +prefix##2XOffset = 0.125; \
> +prefix##2YOffset = 0.625; \
> +prefix##3XOffset = 0.625; \
> +prefix##3YOffset = 0.875;
> +
> +#define SAMPLE_POS_8X(prefix) \
> +prefix##0XOffset = 0.5625; \
> +prefix##0YOffset = 0.3125; \
> +prefix##1XOffset = 0.4375; \
> +prefix##1YOffset = 0.6875; \
> +prefix##2XOffset = 0.8125; \
> +prefix##2YOffset = 0.5625; \
> +prefix##3XOffset = 0.3125; \
> +prefix##3YOffset = 0.1875; \
> +prefix##4XOffset = 0.1875; \
> +prefix##4YOffset = 0.8125; \
> +prefix##5XOffset = 0.0625; \
> +prefix##5YOffset = 0.4375; \
> +prefix##6XOffset = 0.6875; \
> +prefix##6YOffset = 0.9375; \
> +prefix##7XOffset = 0.9375; \
> +prefix##7YOffset = 0.0625;
> +
> +#define SAMPLE_POS_16X(prefix) \
> +prefix##0XOffset = 0.5625; \
> +prefix##0YOffset = 0.5625; \
> +prefix##1XOffset = 0.4375; \
> +prefix##1YOffset = 0.3125; \
> +prefix##2XOffset = 0.3125; \
> +prefix##2YOffset = 0.6250; \
> +prefix##3XOffset = 0.7500; \
> +prefix##3YOffset = 0.4375; \
> +prefix##4XOffset = 0.1875; \
> +prefix##4YOffset = 0.3750; \
> +prefix##5XOffset = 0.6250; \
> +prefix##5YOffset = 0.8125; \
> +prefix##6XOffset = 0.8125; \
> +prefix##6YOffset = 0.6875; \
> +prefix##7XOffset = 0.6875; \
> +prefix##7YOffset = 0.1875; \
> +prefix##8XOffset = 0.3750; \
> +prefix##8YOffset = 0.8750; \
> +prefix##9XOffset = 0.5000; \
> +prefix##9YOffset = 0.0625; \
> +prefix##10XOffset = 0.2500; \
> +prefix##10YOffset = 0.1250; \
> +prefix##11XOffset = 0.1250; \
> +prefix##11YOffset = 0.7500; \
> +prefix##12XOffset = 0.; \
> +prefix##12YOffset = 0.5000; \
> +prefix##13XOffset = 0.9375; \
> +prefix##13YOffset = 0.2500; \
> +prefix##14XOffset = 0.8750; \
> +prefix##14YOffset = 0.9375; \
> +prefix##15XOffset = 0.0625; \
> +prefix##15YOffset = 0.;
> diff --git a/src/intel/vulkan/genX_pipeline_util.h
> b/src/intel/vulkan/genX_pipeline_util.h
> index 64b89cd..cf2adb0 100644
> --- a/src/intel/vulkan/genX_pipeline_util.h
> +++ b/src/intel/vulkan/genX_pipeline_util.h
> @@ -22,6 +22,7 @@
> */
>
> #include "vk_format_info.h"
> +#include "genX_multisample.h"
>
> static uint32_t
> vertex_element_comp_control(enum isl_format format, unsigned comp)
> @@ -488,42 +489,16 @@ emit_ms_state(struct anv_pipeline *pipeline,
>
>switch (samples) {
>case 1:
> - ms.Sample0XOffset = 0.5;
> - ms.Sample0YOffset = 0.
Re: [Mesa-dev] [PATCH v2 3/4] gallium/winsys/kms: Move display target handle lookup to separate function (v2)
On 2016-08-08 01:55:18, Tomasz Figa wrote: >On Fri, Aug 5, 2016 at 2:37 AM, Jordan Justen >wrote: > > On 2016-08-02 03:46:27, Tomasz Figa wrote: > > +kms_sw_displaytarget_lookup(struct kms_sw_winsys *kms_sw, > > +unsigned int kms_handle) > > I don't think the 'lookup' name is appropriate, since it has the > ref-count side effect. Instead of 'lookup', how about import, or > find_and_import or something similar? > >How about "get_by_handle"? IMHO "import" is kind of confusing, because the >function doesn't end up creating any new objects, but instead just looks >through already known ones. How about find_and_ref? >"Get" seems to be a reasonably common word for >getting a reference on an object (together with "put" for dropping the >reference). ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH V2 2/2] i965: Change 8X MSAA sample mapping
This looks good. Thanks! I think we should probably squash it in to the
other one because there's technically a regression between the two. Both
are
Reviewed-by: Jason Ekstrand
On Thu, Aug 11, 2016 at 12:28 PM, Anuj Phogat wrote:
> This is required following the change in 8X sample positions.
> Fixes the recently modified multisample-scaled-blit piglit tests.
>
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
> src/mesa/drivers/dri/i965/gen6_multisample_state.c | 2 +-
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> index b903de1..f7f685b 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
> @@ -1094,13 +1094,13 @@ blorp_nir_manual_blend_bilinear(nir_builder *b,
> nir_ssa_def *pos,
> *
> * In case of 8x MSAA the two layouts don't match.
> * sample index layout : -sample number layout :
> -
> - *| 0 | 1 || 5
> | 2 |
> + *| 0 | 1 || 3
> | 7 |
> *-
> -
> - *| 2 | 3 || 4
> | 6 |
> + *| 2 | 3 || 5
> | 0 |
> *-
> -
> - *| 4 | 5 || 0
> | 3 |
> + *| 4 | 5 || 1
> | 2 |
> *-
> -
> - *| 6 | 7 || 7
> | 1 |
> + *| 6 | 7 || 4
> | 6 |
> *-
> -
> *
> * Fortunately, this can be done fairly easily as:
> @@ -1128,7 +1128,7 @@ blorp_nir_manual_blend_bilinear(nir_builder *b,
> nir_ssa_def *pos,
>sample = nir_f2i(b, sample);
>
>if (tex_samples == 8) {
> - sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x17306425),
> + sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x64210573),
> nir_ishl(b, sample, nir_imm_int(b,
> 2))),
> nir_imm_int(b, 0xf));
>} else if (tex_samples == 16) {
> diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> index a47e323..a59ffec 100644
> --- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
> @@ -109,7 +109,7 @@ gen6_set_sample_maps(struct gl_context *ctx)
> {
> uint8_t map_2x[2] = {0, 1};
> uint8_t map_4x[4] = {0, 1, 2, 3};
> - uint8_t map_8x[8] = {5, 2, 4, 6, 0, 3, 7, 1};
> + uint8_t map_8x[8] = {3, 7, 5, 0, 1, 2, 4, 6};
> uint8_t map_16x[16] = { 15, 10, 9, 7, 4, 1, 3, 13,
> 12, 2, 0, 6, 11, 8, 5, 14 };
>
> --
> 2.5.5
>
> ___
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> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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Re: [Mesa-dev] [PATCH] anv/x11: Add support for Xlib platform
On Thu, Aug 11, 2016 at 3:26 PM, Kevin Strasser
wrote:
> Some applications continue to use the Xlib client library and expect that
> VK_KHR_xlib_surface will be available in the driver. Service these
> applications by converting the Display pointer to xcb_connection_t and use
> the existing xcb code in the driver.
>
> Signed-off-by: Kevin Strasser
> Cc: Jason Ekstrand
> ---
> src/intel/vulkan/Makefile.am | 7 ++--
> src/intel/vulkan/anv_device.c | 6 +++
> src/intel/vulkan/anv_wsi_x11.c | 87 ++
> ++--
> 3 files changed, 86 insertions(+), 14 deletions(-)
>
> diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
> index fe7371e..73db8f5 100644
> --- a/src/intel/vulkan/Makefile.am
> +++ b/src/intel/vulkan/Makefile.am
> @@ -85,7 +85,8 @@ VULKAN_LIB_DEPS =
> if HAVE_PLATFORM_X11
> AM_CPPFLAGS += \
> $(XCB_DRI3_CFLAGS) \
> - -DVK_USE_PLATFORM_XCB_KHR
> + -DVK_USE_PLATFORM_XCB_KHR \
> + -DVK_USE_PLATFORM_XLIB_KHR
>
> VULKAN_SOURCES += $(VULKAN_WSI_X11_FILES)
> VULKAN_LIB_DEPS += $(XCB_DRI3_LIBS)
> @@ -145,7 +146,7 @@ EXTRA_DIST = \
> dev_icd.json.in \
> intel_icd.json
>
> -libvulkan_intel_la_LIBADD = $(VULKAN_LIB_DEPS)
> +libvulkan_intel_la_LIBADD = $(VULKAN_LIB_DEPS) -lX11-xcb
>
> libvulkan_intel_la_LDFLAGS = \
> -shared \
> @@ -168,7 +169,7 @@ dev_icd.json : dev_icd.json.in
>
> # Libvulkan with dummy gem. Used for unit tests.
> libvulkan_test_la_SOURCES = $(VULKAN_GEM_STUB_FILES)
> -libvulkan_test_la_LIBADD = $(VULKAN_LIB_DEPS)
> +libvulkan_test_la_LIBADD = $(VULKAN_LIB_DEPS) -lX11-xcb
>
> include $(top_srcdir)/install-lib-links.mk
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index aae925d..3546682 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -182,6 +182,12 @@ static const VkExtensionProperties
> global_extensions[] = {
>.specVersion = 5,
> },
> #endif
> +#ifdef VK_USE_PLATFORM_XLIB_KHR
> + {
> + .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
> + .specVersion = 5,
> + },
> +#endif
> #ifdef VK_USE_PLATFORM_WAYLAND_KHR
> {
>.extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
> diff --git a/src/intel/vulkan/anv_wsi_x11.c b/src/intel/vulkan/anv_wsi_
> x11.c
> index 2895d6b..2d50fff 100644
> --- a/src/intel/vulkan/anv_wsi_x11.c
> +++ b/src/intel/vulkan/anv_wsi_x11.c
> @@ -21,6 +21,7 @@
> * IN THE SOFTWARE.
> */
>
> +#include
> #include
> #include
> #include
> @@ -256,18 +257,52 @@ VkBool32 anv_GetPhysicalDeviceXcbPresentati
> onSupportKHR(
> return true;
> }
>
> +#ifdef VK_USE_PLATFORM_XLIB_KHR
> +VkBool32 anv_GetPhysicalDeviceXlibPresentationSupportKHR(
> +VkPhysicalDevicephysicalDevice,
> +uint32_tqueueFamilyIndex,
> +Display*dpy,
> +VisualIDvisualID)
> +{
> + return anv_GetPhysicalDeviceXcbPresentationSupportKHR(physicalDevice,
> + queueFamilyIndex,
> +
> XGetXCBConnection(dpy),
> + visualID);
> +}
> +#endif
>
I don't think we need to #ifdef things inside anv_wsi_x11.c since we're not
supporting XCB without Xlib
> +
> +static xcb_connection_t*
> +x11_surface_get_connection(VkIcdSurfaceBase *icd_surface)
> +{
> + if (icd_surface->platform == VK_ICD_WSI_PLATFORM_XLIB)
> + return XGetXCBConnection(((VkIcdSurfaceXlib *)icd_surface)->dpy);
> + else
> + return ((VkIcdSurfaceXcb *)icd_surface)->connection;
> +}
> +
> +static xcb_window_t
> +x11_surface_get_window(VkIcdSurfaceBase *icd_surface)
> +{
> + if (icd_surface->platform == VK_ICD_WSI_PLATFORM_XLIB)
> + return ((VkIcdSurfaceXlib *)icd_surface)->window;
> + else
> + return ((VkIcdSurfaceXcb *)icd_surface)->window;
> +}
> +
> static VkResult
> x11_surface_get_support(VkIcdSurfaceBase *icd_surface,
> struct anv_physical_device *device,
> uint32_t queueFamilyIndex,
> VkBool32* pSupported)
> {
> - VkIcdSurfaceXcb *surface = (VkIcdSurfaceXcb *)icd_surface;
> + xcb_connection_t *conn = x11_surface_get_connection(icd_surface);
> + xcb_window_t window = x11_surface_get_window(icd_surface);
>
> struct wsi_x11_connection *wsi_conn =
> - wsi_x11_get_connection(device, surface->connection);
> - if (!wsi_conn)
> + wsi_x11_get_connection(device, conn);
> + if (!wsi_conn) {
>return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
> + }
>
> if (!wsi_conn->has_dri3) {
>fprintf(stderr, "vulkan: No DRI3 support\n");
> @@ -276,7 +311,7 @@ x11_surface_get_support(VkIcdSurfaceBase *icd_surface,
> }
>
> unsigned visual_depth;
> - if (!get_visualtype_for_window(surface->connection, surface->window,
> + if (!
[Mesa-dev] [PATCH] anv/x11: Add support for Xlib platform
Some applications continue to use the Xlib client library and expect that
VK_KHR_xlib_surface will be available in the driver. Service these
applications by converting the Display pointer to xcb_connection_t and use
the existing xcb code in the driver.
Signed-off-by: Kevin Strasser
Cc: Jason Ekstrand
---
src/intel/vulkan/Makefile.am | 7 ++--
src/intel/vulkan/anv_device.c | 6 +++
src/intel/vulkan/anv_wsi_x11.c | 87 --
3 files changed, 86 insertions(+), 14 deletions(-)
diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
index fe7371e..73db8f5 100644
--- a/src/intel/vulkan/Makefile.am
+++ b/src/intel/vulkan/Makefile.am
@@ -85,7 +85,8 @@ VULKAN_LIB_DEPS =
if HAVE_PLATFORM_X11
AM_CPPFLAGS += \
$(XCB_DRI3_CFLAGS) \
- -DVK_USE_PLATFORM_XCB_KHR
+ -DVK_USE_PLATFORM_XCB_KHR \
+ -DVK_USE_PLATFORM_XLIB_KHR
VULKAN_SOURCES += $(VULKAN_WSI_X11_FILES)
VULKAN_LIB_DEPS += $(XCB_DRI3_LIBS)
@@ -145,7 +146,7 @@ EXTRA_DIST = \
dev_icd.json.in \
intel_icd.json
-libvulkan_intel_la_LIBADD = $(VULKAN_LIB_DEPS)
+libvulkan_intel_la_LIBADD = $(VULKAN_LIB_DEPS) -lX11-xcb
libvulkan_intel_la_LDFLAGS = \
-shared \
@@ -168,7 +169,7 @@ dev_icd.json : dev_icd.json.in
# Libvulkan with dummy gem. Used for unit tests.
libvulkan_test_la_SOURCES = $(VULKAN_GEM_STUB_FILES)
-libvulkan_test_la_LIBADD = $(VULKAN_LIB_DEPS)
+libvulkan_test_la_LIBADD = $(VULKAN_LIB_DEPS) -lX11-xcb
include $(top_srcdir)/install-lib-links.mk
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index aae925d..3546682 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -182,6 +182,12 @@ static const VkExtensionProperties global_extensions[] = {
.specVersion = 5,
},
#endif
+#ifdef VK_USE_PLATFORM_XLIB_KHR
+ {
+ .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
+ .specVersion = 5,
+ },
+#endif
#ifdef VK_USE_PLATFORM_WAYLAND_KHR
{
.extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
diff --git a/src/intel/vulkan/anv_wsi_x11.c b/src/intel/vulkan/anv_wsi_x11.c
index 2895d6b..2d50fff 100644
--- a/src/intel/vulkan/anv_wsi_x11.c
+++ b/src/intel/vulkan/anv_wsi_x11.c
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
+#include
#include
#include
#include
@@ -256,18 +257,52 @@ VkBool32 anv_GetPhysicalDeviceXcbPresentationSupportKHR(
return true;
}
+#ifdef VK_USE_PLATFORM_XLIB_KHR
+VkBool32 anv_GetPhysicalDeviceXlibPresentationSupportKHR(
+VkPhysicalDevicephysicalDevice,
+uint32_tqueueFamilyIndex,
+Display*dpy,
+VisualIDvisualID)
+{
+ return anv_GetPhysicalDeviceXcbPresentationSupportKHR(physicalDevice,
+ queueFamilyIndex,
+
XGetXCBConnection(dpy),
+ visualID);
+}
+#endif
+
+static xcb_connection_t*
+x11_surface_get_connection(VkIcdSurfaceBase *icd_surface)
+{
+ if (icd_surface->platform == VK_ICD_WSI_PLATFORM_XLIB)
+ return XGetXCBConnection(((VkIcdSurfaceXlib *)icd_surface)->dpy);
+ else
+ return ((VkIcdSurfaceXcb *)icd_surface)->connection;
+}
+
+static xcb_window_t
+x11_surface_get_window(VkIcdSurfaceBase *icd_surface)
+{
+ if (icd_surface->platform == VK_ICD_WSI_PLATFORM_XLIB)
+ return ((VkIcdSurfaceXlib *)icd_surface)->window;
+ else
+ return ((VkIcdSurfaceXcb *)icd_surface)->window;
+}
+
static VkResult
x11_surface_get_support(VkIcdSurfaceBase *icd_surface,
struct anv_physical_device *device,
uint32_t queueFamilyIndex,
VkBool32* pSupported)
{
- VkIcdSurfaceXcb *surface = (VkIcdSurfaceXcb *)icd_surface;
+ xcb_connection_t *conn = x11_surface_get_connection(icd_surface);
+ xcb_window_t window = x11_surface_get_window(icd_surface);
struct wsi_x11_connection *wsi_conn =
- wsi_x11_get_connection(device, surface->connection);
- if (!wsi_conn)
+ wsi_x11_get_connection(device, conn);
+ if (!wsi_conn) {
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ }
if (!wsi_conn->has_dri3) {
fprintf(stderr, "vulkan: No DRI3 support\n");
@@ -276,7 +311,7 @@ x11_surface_get_support(VkIcdSurfaceBase *icd_surface,
}
unsigned visual_depth;
- if (!get_visualtype_for_window(surface->connection, surface->window,
+ if (!get_visualtype_for_window(conn, window,
&visual_depth)) {
*pSupported = false;
return VK_SUCCESS;
@@ -296,22 +331,23 @@ x11_surface_get_capabilities(VkIcdSurfaceBase
*icd_surface,
struct anv_physical_device *device,
VkSurfaceCapabilitiesKHR *caps)
{
- VkIcdS
Re: [Mesa-dev] [PATCH 1/2] anv: pipeline: gen7: fix assert in debug mode
Reviewed-by: Jason Ekstrand
On Thu, Aug 11, 2016 at 10:25 AM, Lionel Landwerlin
wrote:
> SampleMask is only 8bits long on gen7.
>
> Signed-off-by: Lionel Landwerlin
> Cc: Jason Ekstrand
> ---
> src/intel/vulkan/genX_pipeline_util.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/src/intel/vulkan/genX_pipeline_util.h
> b/src/intel/vulkan/genX_pipeline_util.h
> index 64b89cd..d56eeb8 100644
> --- a/src/intel/vulkan/genX_pipeline_util.h
> +++ b/src/intel/vulkan/genX_pipeline_util.h
> @@ -462,7 +462,11 @@ emit_ms_state(struct anv_pipeline *pipeline,
> *
> * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
> */
> +#if GEN_GEN >= 8
> uint32_t sample_mask = 0x;
> +#else
> + uint32_t sample_mask = 0xff;
> +#endif
>
> if (info) {
>samples = info->rasterizationSamples;
> --
> 2.8.1
>
>
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[Mesa-dev] [PATCH 19/32] i965/blorp/gen7-8: Emit depth stencil state with CC and BLEND
All three go together on SNB so let's keep them together for gen7+ as well.
---
src/mesa/drivers/dri/i965/gen7_blorp.c | 4 ++--
src/mesa/drivers/dri/i965/gen8_blorp.c | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c
b/src/mesa/drivers/dri/i965/gen7_blorp.c
index ce7047b..122f37f 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -481,6 +481,8 @@ gen7_blorp_exec(struct brw_context *brw,
gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
}
+ depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
+ gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
gen7_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_VS);
gen7_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_HS);
@@ -488,8 +490,6 @@ gen7_blorp_exec(struct brw_context *brw,
gen7_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_GS);
gen7_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_PS);
- depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
- gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
if (brw->use_resource_streamer)
gen7_disable_hw_binding_tables(brw);
if (params->wm_prog_data) {
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c
b/src/mesa/drivers/dri/i965/gen8_blorp.c
index d8860be..5085923 100644
--- a/src/mesa/drivers/dri/i965/gen8_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.c
@@ -521,6 +521,8 @@ gen8_blorp_exec(struct brw_context *brw, const struct
brw_blorp_params *params)
const uint32_t cc_state_offset = gen6_blorp_emit_cc_state(brw);
gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
+ gen8_blorp_emit_depth_stencil_state(brw, params);
+
gen8_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_VS);
gen8_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_HS);
gen8_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_DS);
@@ -560,7 +562,6 @@ gen8_blorp_exec(struct brw_context *brw, const struct
brw_blorp_params *params)
gen8_blorp_emit_ps_config(brw, params);
- gen8_blorp_emit_depth_stencil_state(brw, params);
gen8_blorp_emit_wm_state(brw);
gen8_blorp_emit_depth_disable(brw);
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 28/32] i965/blorp: Add a helper for emitting surface states
The new helper emits surface states and the binding table in one go. It's
nice to have it pulled out of the main blorp_exec function.
---
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 52 -
1 file changed, 28 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 156d8ac..922da45 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -306,6 +306,32 @@ blorp_emit_depth_stencil_state(struct brw_context *brw,
}
static void
+blorp_emit_surface_states(struct brw_context *brw,
+ const struct brw_blorp_params *params)
+{
+ uint32_t bind_offset;
+ uint32_t *bind =
+ brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
+ sizeof(uint32_t) * BRW_BLORP_NUM_BINDING_TABLE_ENTRIES,
+ 32, /* alignment */ &bind_offset);
+
+ bind[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX] =
+ brw_blorp_emit_surface_state(brw, ¶ms->dst,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER, true);
+ if (params->src.bo) {
+ bind[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX] =
+ brw_blorp_emit_surface_state(brw, ¶ms->src,
+ I915_GEM_DOMAIN_SAMPLER, 0, false);
+ }
+
+ blorp_emit(brw, GENX(3DSTATE_BINDING_TABLE_POINTERS), bt) {
+ bt.PSBindingTableChange = true;
+ bt.PointertoPSBindingTable = bind_offset;
+ }
+}
+
+static void
blorp_emit_sampler_state(struct brw_context *brw,
const struct brw_blorp_params *params)
{
@@ -381,7 +407,6 @@ genX(blorp_exec)(struct brw_context *brw,
uint32_t blend_state_offset = 0;
uint32_t color_calc_state_offset = 0;
uint32_t depth_stencil_state_offset;
- uint32_t wm_bind_bo_offset = 0;
/* Emit workaround flushes when we switch from drawing to blorping. */
brw_emit_post_sync_nonzero_flush(brw);
@@ -413,29 +438,8 @@ genX(blorp_exec)(struct brw_context *brw,
blorp_emit(brw, GENX(3DSTATE_CONSTANT_GS), gs);
blorp_emit(brw, GENX(3DSTATE_CONSTANT_PS), ps);
- if (params->wm_prog_data) {
- uint32_t wm_surf_offset_renderbuffer;
- uint32_t wm_surf_offset_texture = 0;
-
- wm_surf_offset_renderbuffer =
- brw_blorp_emit_surface_state(brw, ¶ms->dst,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER, true);
- if (params->src.bo) {
- wm_surf_offset_texture =
-brw_blorp_emit_surface_state(brw, ¶ms->src,
- I915_GEM_DOMAIN_SAMPLER, 0, false);
- }
- wm_bind_bo_offset =
- gen6_blorp_emit_binding_table(brw,
- wm_surf_offset_renderbuffer,
- wm_surf_offset_texture);
-
- blorp_emit(brw, GENX(3DSTATE_BINDING_TABLE_POINTERS), bt) {
- bt.PSBindingTableChange = true;
- bt.PointertoPSBindingTable = wm_bind_bo_offset;
- }
- }
+ if (params->wm_prog_data)
+ blorp_emit_surface_states(brw, params);
if (params->src.bo)
blorp_emit_sampler_state(brw, params);
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 15/32] i965/blorp: Make gen6 VS and GS disable helpers static
---
src/mesa/drivers/dri/i965/blorp_priv.h | 8
src/mesa/drivers/dri/i965/gen6_blorp.c | 4 ++--
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/blorp_priv.h
b/src/mesa/drivers/dri/i965/blorp_priv.h
index 5fafe38..730665e 100644
--- a/src/mesa/drivers/dri/i965/blorp_priv.h
+++ b/src/mesa/drivers/dri/i965/blorp_priv.h
@@ -320,10 +320,6 @@ uint32_t
gen6_blorp_emit_wm_constants(struct brw_context *brw,
const struct brw_blorp_params *params);
-void
-gen6_blorp_emit_vs_disable(struct brw_context *brw,
- const struct brw_blorp_params *params);
-
uint32_t
gen6_blorp_emit_binding_table(struct brw_context *brw,
uint32_t wm_surf_offset_renderbuffer,
@@ -334,10 +330,6 @@ gen6_blorp_emit_depth_stencil_state(struct brw_context
*brw,
const struct brw_blorp_params *params);
void
-gen6_blorp_emit_gs_disable(struct brw_context *brw,
- const struct brw_blorp_params *params);
-
-void
gen6_blorp_emit_clip_disable(struct brw_context *brw);
void
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c
b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 344a40c..93ff8d1 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -443,7 +443,7 @@ gen6_blorp_emit_sampler_state_pointers(struct brw_context
*brw,
*
* Disable vertex shader.
*/
-void
+static void
gen6_blorp_emit_vs_disable(struct brw_context *brw,
const struct brw_blorp_params *params)
{
@@ -482,7 +482,7 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw,
*
* Disable the geometry shader.
*/
-void
+static void
gen6_blorp_emit_gs_disable(struct brw_context *brw,
const struct brw_blorp_params *params)
{
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 13/32] i965: Stop including brw_defines.h in brw_state.h
---
src/mesa/drivers/dri/i965/brw_meta_util.c | 1 +
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri/i965/gen6_blorp.c| 1 +
src/mesa/drivers/dri/i965/gen7_blorp.c| 1 +
4 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index c3af167..90f0345 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -22,6 +22,7 @@
*/
#include "brw_context.h"
+#include "brw_defines.h"
#include "intel_fbo.h"
#include "brw_meta_util.h"
#include "brw_state.h"
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 8990485..eb138b3 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -34,7 +34,6 @@
#define BRW_STATE_H
#include "brw_context.h"
-#include "brw_defines.h"
#ifdef __cplusplus
extern "C" {
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c
b/src/mesa/drivers/dri/i965/gen6_blorp.c
index abdcf17..344a40c 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -27,6 +27,7 @@
#include "intel_mipmap_tree.h"
#include "brw_context.h"
+#include "brw_defines.h"
#include "brw_state.h"
#include "blorp_priv.h"
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c
b/src/mesa/drivers/dri/i965/gen7_blorp.c
index d35d6c6..8fe293d 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -27,6 +27,7 @@
#include "intel_mipmap_tree.h"
#include "brw_context.h"
+#include "brw_defines.h"
#include "brw_state.h"
#include "blorp_priv.h"
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 26/32] i965/blorp: Add genxml-based dynamic state emit functions
---
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 82 +
1 file changed, 73 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 0652930..e512b95 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -240,6 +240,70 @@ blorp_emit_depth_stencil_config(struct brw_context *brw,
blorp_emit(brw, GENX(3DSTATE_STENCIL_BUFFER), sb);
}
+static uint32_t
+blorp_emit_blend_state(struct brw_context *brw,
+ const struct brw_blorp_params *params)
+{
+ struct GENX(BLEND_STATE) blend;
+ memset(&blend, 0, sizeof(blend));
+
+ for (unsigned i = 0; i < params->num_draw_buffers; ++i) {
+ blend.Entry[i].PreBlendColorClampEnable = true;
+ blend.Entry[i].PostBlendColorClampEnable = true;
+ blend.Entry[i].ColorClampRange = COLORCLAMP_RTFORMAT;
+
+ blend.Entry[i].WriteDisableRed = params->color_write_disable[0];
+ blend.Entry[i].WriteDisableGreen = params->color_write_disable[1];
+ blend.Entry[i].WriteDisableBlue = params->color_write_disable[2];
+ blend.Entry[i].WriteDisableAlpha = params->color_write_disable[3];
+ }
+
+ uint32_t offset;
+ void *state = brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
+ GENX(BLEND_STATE_length) * 4, 64, &offset);
+ GENX(BLEND_STATE_pack)(NULL, state, &blend);
+
+ return offset;
+}
+
+static uint32_t
+blorp_emit_color_calc_state(struct brw_context *brw,
+const struct brw_blorp_params *params)
+{
+ uint32_t offset;
+ void *state = brw_state_batch(brw, AUB_TRACE_CC_STATE,
+ GENX(COLOR_CALC_STATE_length) * 4, 64,
&offset);
+ memset(state, 0, GENX(COLOR_CALC_STATE_length) * 4);
+
+ return offset;
+}
+
+static uint32_t
+blorp_emit_depth_stencil_state(struct brw_context *brw,
+ const struct brw_blorp_params *params)
+{
+ /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
+* - 7.5.3.1 Depth Buffer Clear
+* - 7.5.3.2 Depth Buffer Resolve
+* - 7.5.3.3 Hierarchical Depth Buffer Resolve
+*/
+ struct GENX(DEPTH_STENCIL_STATE) ds = {
+ .DepthBufferWriteEnable = true,
+ };
+
+ if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) {
+ ds.DepthTestEnable = true;
+ ds.DepthTestFunction = COMPAREFUNCTION_NEVER;
+ }
+
+ uint32_t offset;
+ void *state = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
+ GENX(DEPTH_STENCIL_STATE_length) * 4, 64,
+ &offset);
+ GENX(DEPTH_STENCIL_STATE_pack)(NULL, state, &ds);
+
+ return offset;
+}
/* 3DSTATE_VIEWPORT_STATE_POINTERS */
static void
@@ -278,9 +342,9 @@ void
genX(blorp_exec)(struct brw_context *brw,
const struct brw_blorp_params *params)
{
- uint32_t cc_blend_state_offset = 0;
- uint32_t cc_state_offset = 0;
- uint32_t depthstencil_offset;
+ uint32_t blend_state_offset = 0;
+ uint32_t color_calc_state_offset = 0;
+ uint32_t depth_stencil_state_offset;
uint32_t wm_bind_bo_offset = 0;
/* Emit workaround flushes when we switch from drawing to blorping. */
@@ -295,18 +359,18 @@ genX(blorp_exec)(struct brw_context *brw,
}
if (params->wm_prog_data) {
- cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
- cc_state_offset = gen6_blorp_emit_cc_state(brw);
+ blend_state_offset = blorp_emit_blend_state(brw, params);
+ color_calc_state_offset = blorp_emit_color_calc_state(brw, params);
}
- depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
+ depth_stencil_state_offset = blorp_emit_depth_stencil_state(brw, params);
blorp_emit(brw, GENX(3DSTATE_CC_STATE_POINTERS), cc) {
cc.BLEND_STATEChange = true;
cc.COLOR_CALC_STATEChange = true;
cc.DEPTH_STENCIL_STATEChange = true;
- cc.PointertoBLEND_STATE = cc_blend_state_offset;
- cc.PointertoCOLOR_CALC_STATE = cc_state_offset;
- cc.PointertoDEPTH_STENCIL_STATE = depthstencil_offset;
+ cc.PointertoBLEND_STATE = blend_state_offset;
+ cc.PointertoCOLOR_CALC_STATE = color_calc_state_offset;
+ cc.PointertoDEPTH_STENCIL_STATE = depth_stencil_state_offset;
}
blorp_emit(brw, GENX(3DSTATE_CONSTANT_VS), vs);
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 12/32] i965/state: Move is_drawing_lines/points to gen6_clip_state.c
---
src/mesa/drivers/dri/i965/brw_state.h | 55 ++---
src/mesa/drivers/dri/i965/gen6_clip_state.c | 54 +++-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 4 +--
src/mesa/drivers/dri/i965/gen7_sf_state.c | 2 +-
4 files changed, 59 insertions(+), 56 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index fc66593..8990485 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -406,63 +406,14 @@ void brw_upload_clip_prog(struct brw_context *brw);
/* brw_sf.c */
void brw_upload_sf_prog(struct brw_context *brw);
+bool brw_is_drawing_points(const struct brw_context *brw);
+bool brw_is_drawing_lines(const struct brw_context *brw);
+
/* gen7_l3_state.c */
void
gen7_restore_default_l3_config(struct brw_context *brw);
static inline bool
-is_drawing_points(const struct brw_context *brw)
-{
- /* Determine if the primitives *reaching the SF* are points */
- /* _NEW_POLYGON */
- if (brw->ctx.Polygon.FrontMode == GL_POINT ||
- brw->ctx.Polygon.BackMode == GL_POINT) {
- return true;
- }
-
- if (brw->geometry_program) {
- /* BRW_NEW_GEOMETRY_PROGRAM */
- return brw->geometry_program->OutputType == GL_POINTS;
- } else if (brw->tes.prog_data) {
- /* BRW_NEW_TES_PROG_DATA */
- return brw->tes.prog_data->output_topology ==
- BRW_TESS_OUTPUT_TOPOLOGY_POINT;
- } else {
- /* BRW_NEW_PRIMITIVE */
- return brw->primitive == _3DPRIM_POINTLIST;
- }
-}
-
-static inline bool
-is_drawing_lines(const struct brw_context *brw)
-{
- /* Determine if the primitives *reaching the SF* are points */
- /* _NEW_POLYGON */
- if (brw->ctx.Polygon.FrontMode == GL_LINE ||
- brw->ctx.Polygon.BackMode == GL_LINE) {
- return true;
- }
-
- if (brw->geometry_program) {
- /* BRW_NEW_GEOMETRY_PROGRAM */
- return brw->geometry_program->OutputType == GL_LINE_STRIP;
- } else if (brw->tes.prog_data) {
- /* BRW_NEW_TES_PROG_DATA */
- return brw->tes.prog_data->output_topology ==
- BRW_TESS_OUTPUT_TOPOLOGY_LINE;
- } else {
- /* BRW_NEW_PRIMITIVE */
- switch (brw->primitive) {
- case _3DPRIM_LINELIST:
- case _3DPRIM_LINESTRIP:
- case _3DPRIM_LINELOOP:
- return true;
- }
- }
- return false;
-}
-
-static inline bool
use_state_point_size(const struct brw_context *brw)
{
const struct gl_context *ctx = &brw->ctx;
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c
b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index 8fa3e04..4a3f7f9 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -33,6 +33,58 @@
#include "main/fbobject.h"
#include "main/framebuffer.h"
+bool
+brw_is_drawing_points(const struct brw_context *brw)
+{
+ /* Determine if the primitives *reaching the SF* are points */
+ /* _NEW_POLYGON */
+ if (brw->ctx.Polygon.FrontMode == GL_POINT ||
+ brw->ctx.Polygon.BackMode == GL_POINT) {
+ return true;
+ }
+
+ if (brw->geometry_program) {
+ /* BRW_NEW_GEOMETRY_PROGRAM */
+ return brw->geometry_program->OutputType == GL_POINTS;
+ } else if (brw->tes.prog_data) {
+ /* BRW_NEW_TES_PROG_DATA */
+ return brw->tes.prog_data->output_topology ==
+ BRW_TESS_OUTPUT_TOPOLOGY_POINT;
+ } else {
+ /* BRW_NEW_PRIMITIVE */
+ return brw->primitive == _3DPRIM_POINTLIST;
+ }
+}
+
+bool
+brw_is_drawing_lines(const struct brw_context *brw)
+{
+ /* Determine if the primitives *reaching the SF* are points */
+ /* _NEW_POLYGON */
+ if (brw->ctx.Polygon.FrontMode == GL_LINE ||
+ brw->ctx.Polygon.BackMode == GL_LINE) {
+ return true;
+ }
+
+ if (brw->geometry_program) {
+ /* BRW_NEW_GEOMETRY_PROGRAM */
+ return brw->geometry_program->OutputType == GL_LINE_STRIP;
+ } else if (brw->tes.prog_data) {
+ /* BRW_NEW_TES_PROG_DATA */
+ return brw->tes.prog_data->output_topology ==
+ BRW_TESS_OUTPUT_TOPOLOGY_LINE;
+ } else {
+ /* BRW_NEW_PRIMITIVE */
+ switch (brw->primitive) {
+ case _3DPRIM_LINELIST:
+ case _3DPRIM_LINESTRIP:
+ case _3DPRIM_LINELOOP:
+ return true;
+ }
+ }
+ return false;
+}
+
static void
upload_clip_state(struct brw_context *brw)
{
@@ -178,7 +230,7 @@ upload_clip_state(struct brw_context *brw)
else
enable = GEN6_CLIP_ENABLE;
- if (!is_drawing_points(brw) && !is_drawing_lines(brw))
+ if (!brw_is_drawing_points(brw) && !brw_is_drawing_lines(brw))
dw2 |= GEN6_CLIP_XY_TEST;
/* BRW_NEW_VUE_MAP_GEOM_OUT */
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index f70305c..7cef17a 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -195,7 +195,7 @@ calculate_attr_overrides(const struct brw
[Mesa-dev] [PATCH 20/32] i965/blorp/gen6-7: Move surfaces and samplers closer together
This mimics what we do on gen8.
---
src/mesa/drivers/dri/i965/gen6_blorp.c | 4 ++--
src/mesa/drivers/dri/i965/gen7_blorp.c | 17 -
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c
b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 3fa8090..b252d78 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -550,6 +550,7 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_binding_table(brw,
wm_surf_offset_renderbuffer,
wm_surf_offset_texture);
+ gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset);
}
if (params->src.bo) {
@@ -557,13 +558,12 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset);
}
+
gen6_blorp_emit_vs_disable(brw, params);
gen6_blorp_emit_gs_disable(brw, params);
gen6_blorp_emit_clip_disable(brw);
gen6_blorp_emit_sf_config(brw, params);
gen6_blorp_emit_wm_config(brw, params);
- if (params->wm_prog_data)
- gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset);
gen6_blorp_emit_viewport_state(brw, params);
if (params->depth.bo)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c
b/src/mesa/drivers/dri/i965/gen7_blorp.c
index 122f37f..adbf909 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -511,7 +511,15 @@ gen7_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_binding_table(brw,
wm_surf_offset_renderbuffer,
wm_surf_offset_texture);
+ gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
}
+
+ if (params->src.bo) {
+ const uint32_t sampler_offset =
+ gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
+ gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
+ }
+
gen7_blorp_emit_vs_disable(brw);
gen7_blorp_emit_hs_disable(brw);
gen7_blorp_emit_te_disable(brw);
@@ -521,15 +529,6 @@ gen7_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_clip_disable(brw);
gen7_blorp_emit_sf_config(brw, params);
gen7_blorp_emit_wm_config(brw, params);
- if (params->wm_prog_data)
- gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
-
- if (params->src.bo) {
- const uint32_t sampler_offset =
- gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
- gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
- }
-
gen7_blorp_emit_ps_config(brw, params);
gen7_blorp_emit_cc_viewport(brw);
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 29/32] i965/blorp: Add genxml-based vertex setup helpers
---
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 213 +++-
1 file changed, 212 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 922da45..f345454 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -85,6 +85,7 @@ __gen_combine_address(struct brw_context *brw, void *location,
#include "genxml/genX_pack.h"
#define _blorp_cmd_length(cmd) cmd ## _length
+#define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
#define _blorp_cmd_header(cmd) cmd ## _header
#define _blorp_cmd_pack(cmd) cmd ## _pack
@@ -95,6 +96,215 @@ __gen_combine_address(struct brw_context *brw, void
*location,
_blorp_cmd_pack(cmd)(brw, (void *)_dst, &name), \
_dst = NULL)
+#define blorp_emitn(batch, cmd, n) ({\
+ uint32_t *_dw = blorp_emit_dwords(batch, n); \
+ struct cmd template = {\
+ _blorp_cmd_header(cmd), \
+ .DWordLength = n - _blorp_cmd_length_bias(cmd), \
+ }; \
+ _blorp_cmd_pack(cmd)(batch, _dw, &template); \
+ _dw + 1; /* Array starts at dw[1] */ \
+ })
+
+static void
+blorp_emit_vertex_data(struct brw_context *brw,
+ const struct brw_blorp_params *params,
+ struct blorp_address *addr,
+ uint32_t *size)
+{
+ const float vertices[] = {
+ /* v0 */ (float)params->x0, (float)params->y1,
+ /* v1 */ (float)params->x1, (float)params->y1,
+ /* v2 */ (float)params->x0, (float)params->y0,
+ };
+
+ uint32_t offset;
+ void *data = brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
+sizeof(vertices), 32, &offset);
+ memcpy(data, vertices, sizeof(vertices));
+
+ *addr = (struct blorp_address) {
+ .buffer = brw->batch.bo,
+ .read_domains = I915_GEM_DOMAIN_VERTEX,
+ .write_domain = 0,
+ .offset = offset,
+ };
+ *size = sizeof(vertices);
+}
+
+static void
+blorp_emit_input_varying_data(struct brw_context *brw,
+ const struct brw_blorp_params *params,
+ struct blorp_address *addr,
+ uint32_t *size)
+{
+ const unsigned vec4_size_in_bytes = 4 * sizeof(float);
+ const unsigned max_num_varyings =
+ DIV_ROUND_UP(sizeof(params->wm_inputs), vec4_size_in_bytes);
+ const unsigned num_varyings = params->wm_prog_data->num_varying_inputs;
+
+ *size = num_varyings * vec4_size_in_bytes;
+
+ const float *const inputs_src = (const float *)¶ms->wm_inputs;
+ uint32_t offset;
+ float *inputs = brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
+ *size, 32, &offset);
+
+ /* Walk over the attribute slots, determine if the attribute is used by
+* the program and when necessary copy the values from the input storage to
+* the vertex data buffer.
+*/
+ for (unsigned i = 0; i < max_num_varyings; i++) {
+ const gl_varying_slot attr = VARYING_SLOT_VAR0 + i;
+
+ if (!(params->wm_prog_data->inputs_read & BITFIELD64_BIT(attr)))
+ continue;
+
+ memcpy(inputs, inputs_src + i * 4, vec4_size_in_bytes);
+
+ inputs += 4;
+ }
+
+ *addr = (struct blorp_address) {
+ .buffer = brw->batch.bo,
+ .read_domains = I915_GEM_DOMAIN_VERTEX,
+ .write_domain = 0,
+ .offset = offset,
+ };
+}
+
+static void
+blorp_emit_vertex_buffers(struct brw_context *brw,
+ const struct brw_blorp_params *params)
+{
+ struct GENX(VERTEX_BUFFER_STATE) vb[2];
+ memset(vb, 0, sizeof(vb));
+
+ unsigned num_buffers = 1;
+
+ uint32_t size;
+ blorp_emit_vertex_data(brw, params, &vb[0].BufferStartingAddress, &size);
+ vb[0].VertexBufferIndex = 0;
+ vb[0].BufferPitch = 2 * sizeof(float);
+ vb[0].BufferAccessType = VERTEXDATA;
+ vb[0].EndAddress = vb[0].BufferStartingAddress;
+ vb[0].EndAddress.offset += size - 1;
+
+ if (params->wm_prog_data && params->wm_prog_data->num_varying_inputs) {
+ blorp_emit_input_varying_data(brw, params,
+&vb[1].BufferStartingAddress, &size);
+ vb[1].VertexBufferIndex = 1;
+ vb[1].BufferPitch = 0;
+ vb[1].BufferAccessType = INSTANCEDATA;
+ vb[1].EndAddress = vb[1].BufferStartingAddress;
+ vb[1].EndAddress.offset += size;
+ num_buffers++;
+ }
+
+ const unsigned num_dwords =
+ 1 + GENX(VERTEX_BUFFER_STATE_length) * num_buffers;
+ uint32_t *dw = blorp_emitn(brw, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords);
+
+ for (unsigned i = 0; i < num_buffers; i++) {
+ GENX(VERTEX_BUFFER_STATE_pack)(brw, dw, &vb[i]);
+ dw += GENX(VERTEX_BUFFER_STATE_length);
+ }
+}
+
+static void
+blorp_emit_vertex_elements(struct brw_context *brw,
+
[Mesa-dev] [PATCH 32/32] i965/blorp: Remove no longer used state setup helpers
Now that we're using genxml for everything, we no longer need the hand-rolled state emit helpers. --- src/mesa/drivers/dri/i965/Makefile.sources | 1 - src/mesa/drivers/dri/i965/blorp_priv.h | 79 src/mesa/drivers/dri/i965/brw_blorp_emit.c | 577 - 3 files changed, 657 deletions(-) delete mode 100644 src/mesa/drivers/dri/i965/brw_blorp_emit.c diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index 975f478..8f23223 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -102,7 +102,6 @@ i965_FILES = \ brw_binding_tables.c \ brw_blorp.c \ brw_blorp.h \ - brw_blorp_emit.c \ brw_cc.c \ brw_clear.c \ brw_clip.c \ diff --git a/src/mesa/drivers/dri/i965/blorp_priv.h b/src/mesa/drivers/dri/i965/blorp_priv.h index 3ca1c223..582677c 100644 --- a/src/mesa/drivers/dri/i965/blorp_priv.h +++ b/src/mesa/drivers/dri/i965/blorp_priv.h @@ -309,85 +309,6 @@ brw_blorp_emit_surface_state(struct brw_context *brw, uint32_t read_domains, uint32_t write_domain, bool is_render_target); -void -gen6_blorp_init(struct brw_context *brw); - -void -gen6_blorp_emit_vertices(struct brw_context *brw, - const struct brw_blorp_params *params); - -uint32_t -gen6_blorp_emit_blend_state(struct brw_context *brw, -const struct brw_blorp_params *params); - -uint32_t -gen6_blorp_emit_cc_state(struct brw_context *brw); - -uint32_t -gen6_blorp_emit_wm_constants(struct brw_context *brw, - const struct brw_blorp_params *params); - -uint32_t -gen6_blorp_emit_binding_table(struct brw_context *brw, - uint32_t wm_surf_offset_renderbuffer, - uint32_t wm_surf_offset_texture); - -uint32_t -gen6_blorp_emit_depth_stencil_state(struct brw_context *brw, -const struct brw_blorp_params *params); - -void -gen6_blorp_emit_clip_disable(struct brw_context *brw); - -void -gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, - const struct brw_blorp_params *params); - -uint32_t -gen6_blorp_emit_sampler_state(struct brw_context *brw, - unsigned tex_filter, unsigned max_lod, - bool non_normalized_coords); -void -gen7_blorp_emit_urb_config(struct brw_context *brw, - const struct brw_blorp_params *params); - -void -gen7_blorp_emit_blend_state_pointer(struct brw_context *brw, -uint32_t cc_blend_state_offset); - -void -gen7_blorp_emit_cc_state_pointer(struct brw_context *brw, - uint32_t cc_state_offset); - -void -gen7_blorp_emit_cc_viewport(struct brw_context *brw); - -void -gen7_blorp_emit_te_disable(struct brw_context *brw); - -void -gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw, - uint32_t wm_bind_bo_offset); - -void -gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw, - uint32_t sampler_offset); - -void -gen7_blorp_emit_clear_params(struct brw_context *brw, - const struct brw_blorp_params *params); - -void -gen7_blorp_emit_constant_ps(struct brw_context *brw, -uint32_t wm_push_const_offset); - -void -gen7_blorp_emit_constant_ps_disable(struct brw_context *brw); - -void -gen7_blorp_emit_primitive(struct brw_context *brw, - const struct brw_blorp_params *params); - /** \} */ #ifdef __cplusplus diff --git a/src/mesa/drivers/dri/i965/brw_blorp_emit.c b/src/mesa/drivers/dri/i965/brw_blorp_emit.c deleted file mode 100644 index c0a7e55..000 --- a/src/mesa/drivers/dri/i965/brw_blorp_emit.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright © 2011 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIAB
[Mesa-dev] [PATCH 18/32] i965/blorp/gen6: Move constant disables higher up
This is what gen7-8 do and it's a bit cleaner.
---
src/mesa/drivers/dri/i965/gen6_blorp.c | 29 +++--
1 file changed, 7 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c
b/src/mesa/drivers/dri/i965/gen6_blorp.c
index d27c550..3fa8090 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -124,15 +124,6 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw,
* We've already done one at the start of the BLORP operation.
*/
- /* Disable the push constant buffers. */
- BEGIN_BATCH(5);
- OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
-
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
OUT_BATCH(0);
@@ -152,15 +143,6 @@ static void
gen6_blorp_emit_gs_disable(struct brw_context *brw,
const struct brw_blorp_params *params)
{
- /* Disable all the constant buffers. */
- BEGIN_BATCH(5);
- OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
-
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
OUT_BATCH(0);
@@ -305,12 +287,11 @@ gen6_blorp_emit_wm_config(struct brw_context *brw,
}
static void
-gen6_blorp_emit_constant_ps_disable(struct brw_context *brw,
-const struct brw_blorp_params *params)
+gen6_blorp_emit_constant_disable(struct brw_context *brw, unsigned opcode)
{
/* Disable the push constant buffers. */
BEGIN_BATCH(5);
- OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
+ OUT_BATCH(opcode << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -547,6 +528,11 @@ gen6_blorp_exec(struct brw_context *brw,
depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset,
depthstencil_offset, cc_state_offset);
+
+ gen6_blorp_emit_constant_disable(brw, _3DSTATE_CONSTANT_VS);
+ gen6_blorp_emit_constant_disable(brw, _3DSTATE_CONSTANT_GS);
+ gen6_blorp_emit_constant_disable(brw, _3DSTATE_CONSTANT_PS);
+
if (params->wm_prog_data) {
uint32_t wm_surf_offset_renderbuffer;
uint32_t wm_surf_offset_texture = 0;
@@ -575,7 +561,6 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_gs_disable(brw, params);
gen6_blorp_emit_clip_disable(brw);
gen6_blorp_emit_sf_config(brw, params);
- gen6_blorp_emit_constant_ps_disable(brw, params);
gen6_blorp_emit_wm_config(brw, params);
if (params->wm_prog_data)
gen6_blorp_emit_binding_table_pointers(brw, wm_bind_bo_offset);
--
2.5.0.400.gff86faf
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 14/32] i965: Roll intel_reg.h into brw_defines.h
More than half of the stuff in intel_reg.h had nothing whatsoever to do
with registers and really belongs in brw_defines.h anyway.
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 -
src/mesa/drivers/dri/i965/brw_defines.h| 273 +++
src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +-
src/mesa/drivers/dri/i965/brw_queryobj.c | 1 -
src/mesa/drivers/dri/i965/gen6_queryobj.c | 1 -
src/mesa/drivers/dri/i965/hsw_queryobj.c | 1 -
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 1 -
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 1 -
src/mesa/drivers/dri/i965/intel_blit.c | 1 -
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
src/mesa/drivers/dri/i965/intel_fbo.c | 1 +
src/mesa/drivers/dri/i965/intel_pixel_bitmap.c | 1 -
src/mesa/drivers/dri/i965/intel_reg.h | 297 -
src/mesa/drivers/dri/i965/intel_syncobj.c | 1 -
src/mesa/drivers/dri/i965/intel_tex.c | 2 +-
15 files changed, 277 insertions(+), 308 deletions(-)
delete mode 100644 src/mesa/drivers/dri/i965/intel_reg.h
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 02705a1..8626c7d 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -87,7 +87,6 @@ i965_compiler_FILES = \
intel_asm_annotation.h \
intel_debug.c \
intel_debug.h \
- intel_reg.h \
intel_resolve_map.c \
intel_resolve_map.h
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 2814fa7..3d97fda 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2963,4 +2963,277 @@ enum brw_barycentric_mode {
# define GPGPU_WALKER_THREAD_WIDTH_MAX_SHIFT0
# define GPGPU_WALKER_THREAD_WIDTH_MAX_MASK INTEL_MASK(5, 0)
+#define CMD_MI (0x0 << 29)
+#define CMD_2D (0x2 << 29)
+#define CMD_3D (0x3 << 29)
+
+#define MI_NOOP(CMD_MI | 0)
+
+#define MI_BATCH_BUFFER_END(CMD_MI | 0xA << 23)
+
+#define MI_FLUSH (CMD_MI | (4 << 23))
+#define FLUSH_MAP_CACHE(1 << 0)
+#define INHIBIT_FLUSH_RENDER_CACHE (1 << 2)
+
+#define MI_STORE_DATA_IMM (CMD_MI | (0x20 << 23))
+#define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23))
+#define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23))
+
+#define MI_FLUSH_DW(CMD_MI | (0x26 << 23) | 2)
+
+#define MI_STORE_REGISTER_MEM (CMD_MI | (0x24 << 23))
+# define MI_STORE_REGISTER_MEM_USE_GGTT(1 << 22)
+# define MI_STORE_REGISTER_MEM_PREDICATE (1 << 21)
+
+/* Load a value from memory into a register. Only available on Gen7+. */
+#define GEN7_MI_LOAD_REGISTER_MEM (CMD_MI | (0x29 << 23))
+# define MI_LOAD_REGISTER_MEM_USE_GGTT (1 << 22)
+/* Haswell RS control */
+#define MI_RS_CONTROL (CMD_MI | (0x6 << 23))
+#define MI_RS_STORE_DATA_IMM(CMD_MI | (0x2b << 23))
+
+/* Manipulate the predicate bit based on some register values. Only on Gen7+ */
+#define GEN7_MI_PREDICATE (CMD_MI | (0xC << 23))
+# define MI_PREDICATE_LOADOP_KEEP (0 << 6)
+# define MI_PREDICATE_LOADOP_LOAD (2 << 6)
+# define MI_PREDICATE_LOADOP_LOADINV (3 << 6)
+# define MI_PREDICATE_COMBINEOP_SET(0 << 3)
+# define MI_PREDICATE_COMBINEOP_AND(1 << 3)
+# define MI_PREDICATE_COMBINEOP_OR (2 << 3)
+# define MI_PREDICATE_COMBINEOP_XOR(3 << 3)
+# define MI_PREDICATE_COMPAREOP_TRUE (0 << 0)
+# define MI_PREDICATE_COMPAREOP_FALSE (1 << 0)
+# define MI_PREDICATE_COMPAREOP_SRCS_EQUAL (2 << 0)
+# define MI_PREDICATE_COMPAREOP_DELTAS_EQUAL (3 << 0)
+
+#define HSW_MI_MATH(CMD_MI | (0x1a << 23))
+
+#define MI_MATH_ALU2(opcode, operand1, operand2) \
+ ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10)
| \
+ ((MI_MATH_OPERAND_##operand2) << 0) )
+
+#define MI_MATH_ALU1(opcode, operand1) \
+ ( ((MI_MATH_OPCODE_##opcode) << 20) | ((MI_MATH_OPERAND_##operand1) << 10) )
+
+#define MI_MATH_ALU0(opcode) \
+ ( ((MI_MATH_OPCODE_##opcode) << 20) )
+
+#define MI_MATH_OPCODE_NOOP 0x000
+#define MI_MATH_OPCODE_LOAD 0x080
+#define MI_MATH_OPCODE_LOADINV 0x480
+#define MI_MATH_OPCODE_LOAD0 0x081
+#define MI_MATH_OPCODE_LOAD1 0x481
+#define MI_MATH_OPCODE_ADD 0x100
+#define MI_MATH_OPCODE_SUB 0x101
+#define MI_MATH_OPCODE_AND 0x102
+#define MI_MATH_OPCODE_OR0x103
+#define MI_MATH_OPCODE_XOR 0x104
+#define MI_MATH_OPCODE_STORE 0x180
+#define MI_MATH_OPCODE_STOREINV 0x580
+
+#define MI_MATH_OPERAND_R0 0x00
+#define MI_MATH_OPERA
[Mesa-dev] [PATCH 31/32] i965/blorp: Use genxml for gen8-9 state setup
---
src/mesa/drivers/dri/i965/Makefile.am | 10 +-
src/mesa/drivers/dri/i965/Makefile.sources | 7 +-
src/mesa/drivers/dri/i965/blorp.c | 4 +-
src/mesa/drivers/dri/i965/blorp_priv.h | 3 +
src/mesa/drivers/dri/i965/gen8_blorp.c | 578
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 157 +++-
6 files changed, 172 insertions(+), 587 deletions(-)
delete mode 100644 src/mesa/drivers/dri/i965/gen8_blorp.c
diff --git a/src/mesa/drivers/dri/i965/Makefile.am
b/src/mesa/drivers/dri/i965/Makefile.am
index 31477ef..30201b2 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -51,7 +51,9 @@ brw_nir_trig_workarounds.c: brw_nir_trig_workarounds.py
$(top_srcdir)/src/compil
I965_PERGEN_LIBS = \
libi965_gen6.la \
libi965_gen7.la \
- libi965_gen75.la
+ libi965_gen75.la \
+ libi965_gen8.la \
+ libi965_gen9.la
libi965_gen6_la_SOURCES = $(i965_gen6_FILES)
libi965_gen6_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=60
@@ -62,6 +64,12 @@ libi965_gen7_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=70
libi965_gen75_la_SOURCES = $(i965_gen75_FILES)
libi965_gen75_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=75
+libi965_gen8_la_SOURCES = $(i965_gen8_FILES)
+libi965_gen8_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=80
+
+libi965_gen9_la_SOURCES = $(i965_gen9_FILES)
+libi965_gen9_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=90
+
noinst_LTLIBRARIES = \
libi965_dri.la \
libi965_compiler.la \
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index a7f8c40..975f478 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -206,7 +206,6 @@ i965_FILES = \
gen7_wm_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
- gen8_blorp.c \
gen8_depth_state.c \
gen8_disable.c \
gen8_draw_upload.c \
@@ -267,3 +266,9 @@ i965_gen7_FILES = \
i965_gen75_FILES = \
genX_blorp_exec.c
+
+i965_gen8_FILES = \
+ genX_blorp_exec.c
+
+i965_gen9_FILES = \
+ genX_blorp_exec.c
diff --git a/src/mesa/drivers/dri/i965/blorp.c
b/src/mesa/drivers/dri/i965/blorp.c
index 87cf2c9..3100615 100644
--- a/src/mesa/drivers/dri/i965/blorp.c
+++ b/src/mesa/drivers/dri/i965/blorp.c
@@ -321,9 +321,11 @@ retry:
gen7_blorp_exec(brw, params);
break;
case 8:
- case 9:
gen8_blorp_exec(brw, params);
break;
+ case 9:
+ gen9_blorp_exec(brw, params);
+ break;
default:
/* BLORP is not supported before Gen6. */
unreachable("not reached");
diff --git a/src/mesa/drivers/dri/i965/blorp_priv.h
b/src/mesa/drivers/dri/i965/blorp_priv.h
index ce6aaa7..3ca1c223 100644
--- a/src/mesa/drivers/dri/i965/blorp_priv.h
+++ b/src/mesa/drivers/dri/i965/blorp_priv.h
@@ -203,6 +203,9 @@ gen75_blorp_exec(struct brw_context *brw,
void
gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params
*params);
+void
+gen9_blorp_exec(struct brw_context *brw, const struct brw_blorp_params
*params);
+
struct brw_blorp_blit_prog_key
{
/* Number of samples per pixel that have been configured in the surface
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c
b/src/mesa/drivers/dri/i965/gen8_blorp.c
deleted file mode 100644
index 2223b23..000
--- a/src/mesa/drivers/dri/i965/gen8_blorp.c
+++ /dev/null
@@ -1,578 +0,0 @@
-/*
- * Copyright © 2016 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include
-
-#include "intel_batchbuffer.h"
-#include "intel_fbo.h"
-#include "intel_mipmap_tree.h"
-
-#include "brw_context.h"
-#include "brw_defines.h"
-#include "brw_state.h"
-
-#include "blorp_priv.h"
-
-static uint32_t
-gen8_blorp_emit_blend_state(struct brw_context *brw,
-const struct brw_b
[Mesa-dev] [PATCH 23/32] i965/blorp: Stop setting point and line rasterization rules
Blorp never uses points or lines and the default values of 0 are perfectly
fine. Explicitly setting them is just noise.
---
src/mesa/drivers/dri/i965/gen6_blorp.c | 2 --
src/mesa/drivers/dri/i965/gen7_blorp.c | 2 --
src/mesa/drivers/dri/i965/gen8_blorp.c | 4 +---
3 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c
b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 7d37ea3..78e9472 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -235,8 +235,6 @@ gen6_blorp_emit_wm_config(struct brw_context *brw,
default:
unreachable("not reached");
}
- dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
- dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
dw6 |= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
dw6 |= (params->wm_prog_data ? prog_data->num_varying_inputs : 0) <<
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c
b/src/mesa/drivers/dri/i965/gen7_blorp.c
index 1b9c853..1286b55 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -261,8 +261,6 @@ gen7_blorp_emit_wm_config(struct brw_context *brw,
default:
unreachable("not reached");
}
- dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
- dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
if (params->wm_prog_data)
diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c
b/src/mesa/drivers/dri/i965/gen8_blorp.c
index 2e90438..2223b23 100644
--- a/src/mesa/drivers/dri/i965/gen8_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen8_blorp.c
@@ -270,9 +270,7 @@ gen8_blorp_emit_wm_state(struct brw_context *brw)
{
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
- OUT_BATCH(GEN7_WM_LINE_AA_WIDTH_1_0 |
- GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5 |
- GEN7_WM_POINT_RASTRULE_UPPER_RIGHT);
+ OUT_BATCH(0);
ADVANCE_BATCH();
}
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 30/32] i965/blorp: Use genxml for gen7 state setup
--- src/mesa/drivers/dri/i965/Makefile.am | 10 +- src/mesa/drivers/dri/i965/Makefile.sources | 6 +- src/mesa/drivers/dri/i965/blorp.c | 5 +- src/mesa/drivers/dri/i965/blorp_priv.h | 4 + src/mesa/drivers/dri/i965/gen7_blorp.c | 540 src/mesa/drivers/dri/i965/genX_blorp_exec.c | 265 +- 6 files changed, 281 insertions(+), 549 deletions(-) delete mode 100644 src/mesa/drivers/dri/i965/gen7_blorp.c diff --git a/src/mesa/drivers/dri/i965/Makefile.am b/src/mesa/drivers/dri/i965/Makefile.am index 35de8f9..31477ef 100644 --- a/src/mesa/drivers/dri/i965/Makefile.am +++ b/src/mesa/drivers/dri/i965/Makefile.am @@ -49,11 +49,19 @@ brw_nir_trig_workarounds.c: brw_nir_trig_workarounds.py $(top_srcdir)/src/compil $(AM_V_GEN) PYTHONPATH=$(top_srcdir)/src/compiler/nir $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/brw_nir_trig_workarounds.py > $@ || ($(RM) $@; false) I965_PERGEN_LIBS = \ - libi965_gen6.la + libi965_gen6.la \ + libi965_gen7.la \ + libi965_gen75.la libi965_gen6_la_SOURCES = $(i965_gen6_FILES) libi965_gen6_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=60 +libi965_gen7_la_SOURCES = $(i965_gen7_FILES) +libi965_gen7_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=70 + +libi965_gen75_la_SOURCES = $(i965_gen75_FILES) +libi965_gen75_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=75 + noinst_LTLIBRARIES = \ libi965_dri.la \ libi965_compiler.la \ diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index fc3b5db..a7f8c40 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -191,7 +191,6 @@ i965_FILES = \ gen6_viewport_state.c \ gen6_vs_state.c \ gen6_wm_state.c \ - gen7_blorp.c \ gen7_cs_state.c \ gen7_ds_state.c \ gen7_gs_state.c \ @@ -263,3 +262,8 @@ i965_FILES = \ i965_gen6_FILES = \ genX_blorp_exec.c +i965_gen7_FILES = \ + genX_blorp_exec.c + +i965_gen75_FILES = \ + genX_blorp_exec.c diff --git a/src/mesa/drivers/dri/i965/blorp.c b/src/mesa/drivers/dri/i965/blorp.c index 9e53753..87cf2c9 100644 --- a/src/mesa/drivers/dri/i965/blorp.c +++ b/src/mesa/drivers/dri/i965/blorp.c @@ -315,7 +315,10 @@ retry: gen6_blorp_exec(brw, params); break; case 7: - gen7_blorp_exec(brw, params); + if (brw->is_haswell) + gen75_blorp_exec(brw, params); + else + gen7_blorp_exec(brw, params); break; case 8: case 9: diff --git a/src/mesa/drivers/dri/i965/blorp_priv.h b/src/mesa/drivers/dri/i965/blorp_priv.h index 730665e..ce6aaa7 100644 --- a/src/mesa/drivers/dri/i965/blorp_priv.h +++ b/src/mesa/drivers/dri/i965/blorp_priv.h @@ -197,6 +197,10 @@ gen7_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params); void +gen75_blorp_exec(struct brw_context *brw, + const struct brw_blorp_params *params); + +void gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params); struct brw_blorp_blit_prog_key diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c deleted file mode 100644 index 1286b55..000 --- a/src/mesa/drivers/dri/i965/gen7_blorp.c +++ /dev/null @@ -1,540 +0,0 @@ -/* - * Copyright © 2011 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include - -#include "intel_batchbuffer.h" -#include "intel_mipmap_tree.h" - -#include "brw_context.h" -#include "brw_defines.h" -#include "brw_state.h" - -#include "blorp_priv.h" - - -/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS - * - * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. - */ -static void -gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw, - uin
[Mesa-dev] [PATCH 27/32] i965/blorp: Add genxml-based sampler state emit function
---
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 49 ++---
1 file changed, 38 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index e512b95..156d8ac 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -305,6 +305,42 @@ blorp_emit_depth_stencil_state(struct brw_context *brw,
return offset;
}
+static void
+blorp_emit_sampler_state(struct brw_context *brw,
+ const struct brw_blorp_params *params)
+{
+ struct GENX(SAMPLER_STATE) sampler = {
+ .MipModeFilter = MIPFILTER_NONE,
+ .MagModeFilter = MAPFILTER_LINEAR,
+ .MinModeFilter = MAPFILTER_LINEAR,
+ .MinLOD = 0,
+ .MaxLOD = 0,
+ .TCXAddressControlMode = TCM_CLAMP,
+ .TCYAddressControlMode = TCM_CLAMP,
+ .TCZAddressControlMode = TCM_CLAMP,
+ .MaximumAnisotropy = RATIO21,
+ .RAddressMinFilterRoundingEnable = true,
+ .RAddressMagFilterRoundingEnable = true,
+ .VAddressMinFilterRoundingEnable = true,
+ .VAddressMagFilterRoundingEnable = true,
+ .UAddressMinFilterRoundingEnable = true,
+ .UAddressMagFilterRoundingEnable = true,
+ .NonnormalizedCoordinateEnable = true,
+ };
+
+ uint32_t offset;
+ void *state = brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
+ GENX(SAMPLER_STATE_length) * 4, 32, &offset);
+ GENX(SAMPLER_STATE_pack)(NULL, state, &sampler);
+
+ blorp_emit(brw, GENX(3DSTATE_SAMPLER_STATE_POINTERS), ssp) {
+ ssp.VSSamplerStateChange = true;
+ ssp.GSSamplerStateChange = true;
+ ssp.PSSamplerStateChange = true;
+ ssp.PointertoPSSamplerState = offset;
+ }
+}
+
/* 3DSTATE_VIEWPORT_STATE_POINTERS */
static void
blorp_emit_viewport_state(struct brw_context *brw,
@@ -401,17 +437,8 @@ genX(blorp_exec)(struct brw_context *brw,
}
}
- if (params->src.bo) {
- const uint32_t sampler_offset =
- gen6_blorp_emit_sampler_state(brw, MAPFILTER_LINEAR, 0, true);
-
- blorp_emit(brw, GENX(3DSTATE_SAMPLER_STATE_POINTERS), ssp) {
- ssp.VSSamplerStateChange = true;
- ssp.GSSamplerStateChange = true;
- ssp.PSSamplerStateChange = true;
- ssp.PointertoPSSamplerState = sampler_offset;
- }
- }
+ if (params->src.bo)
+ blorp_emit_sampler_state(brw, params);
gen6_emit_3dstate_multisample(brw, params->dst.surf.samples);
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 10/32] genxml: Add a uint MOCS field to VERTEX_BUFFER_STATE
--- src/intel/genxml/gen6.xml | 1 + src/intel/genxml/gen7.xml | 1 + src/intel/genxml/gen75.xml | 1 + src/intel/genxml/gen8.xml | 1 + src/intel/genxml/gen9.xml | 1 + 5 files changed, 5 insertions(+) diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 6241665..52d0ecb 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -11,6 +11,7 @@ + diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index adf764e..44bb2a7 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -24,6 +24,7 @@ + diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index b93e920..27112b6 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -34,6 +34,7 @@ + diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index d460c48..5b2290e 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -40,6 +40,7 @@ + diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 4837b3c..51a2420 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -28,6 +28,7 @@ + -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 25/32] i965: Move gen6_blorp.c to a file that gets recompiled per-gen
At the moment, it's only used for gen6 but that will change soon. We use
the genX prefix for recompiled things in the Vulkan driver. It isn't
great, but it seems to have worked ok.
---
src/mesa/drivers/dri/i965/Makefile.am | 14 +-
src/mesa/drivers/dri/i965/Makefile.sources | 5 +-
src/mesa/drivers/dri/i965/gen6_blorp.c | 400
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 399 +++
4 files changed, 416 insertions(+), 402 deletions(-)
delete mode 100644 src/mesa/drivers/dri/i965/gen6_blorp.c
create mode 100644 src/mesa/drivers/dri/i965/genX_blorp_exec.c
diff --git a/src/mesa/drivers/dri/i965/Makefile.am
b/src/mesa/drivers/dri/i965/Makefile.am
index 77ad1e8..35de8f9 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -48,11 +48,22 @@ brw_nir_trig_workarounds.c: brw_nir_trig_workarounds.py
$(top_srcdir)/src/compil
$(MKDIR_GEN)
$(AM_V_GEN) PYTHONPATH=$(top_srcdir)/src/compiler/nir $(PYTHON2)
$(PYTHON_FLAGS) $(srcdir)/brw_nir_trig_workarounds.py > $@ || ($(RM) $@; false)
-noinst_LTLIBRARIES = libi965_dri.la libi965_compiler.la
+I965_PERGEN_LIBS = \
+ libi965_gen6.la
+
+libi965_gen6_la_SOURCES = $(i965_gen6_FILES)
+libi965_gen6_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=60
+
+noinst_LTLIBRARIES = \
+ libi965_dri.la \
+ libi965_compiler.la \
+ $(I965_PERGEN_LIBS)
+
libi965_dri_la_SOURCES = $(i965_FILES)
libi965_dri_la_LIBADD = \
$(top_builddir)/src/intel/isl/libisl.la \
libi965_compiler.la \
+ $(I965_PERGEN_LIBS)
$(INTEL_LIBS)
libi965_compiler_la_SOURCES = \
@@ -67,6 +78,7 @@ EXTRA_DIST = \
TEST_LIBS = \
libi965_compiler.la \
+ $(I965_PERGEN_LIBS) \
$(top_builddir)/src/compiler/nir/libnir.la \
$(top_builddir)/src/util/libmesautil.la \
$(top_builddir)/src/intel/isl/libisl.la \
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index be6b1f9..fc3b5db 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -175,7 +175,6 @@ i965_FILES = \
brw_wm.h \
brw_wm_state.c \
brw_wm_surface_state.c \
- gen6_blorp.c \
gen6_cc.c \
gen6_clip_state.c \
gen6_constant_state.c \
@@ -260,3 +259,7 @@ i965_FILES = \
intel_tiled_memcpy.c \
intel_tiled_memcpy.h \
intel_upload.c
+
+i965_gen6_FILES = \
+ genX_blorp_exec.c
+
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c
b/src/mesa/drivers/dri/i965/gen6_blorp.c
deleted file mode 100644
index 875fdc9..000
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include
-
-#include "intel_batchbuffer.h"
-#include "intel_mipmap_tree.h"
-
-#include "brw_context.h"
-#include "brw_state.h"
-
-#include "blorp_priv.h"
-
-#define GEN_VERSIONx10 60
-#include "genxml/gen_macros.h"
-
-static void *
-blorp_emit_dwords(struct brw_context *brw, unsigned n)
-{
- intel_batchbuffer_begin(brw, n, RENDER_RING);
- uint32_t *map = brw->batch.map_next;
- brw->batch.map_next += n;
- intel_batchbuffer_advance(brw);
- return map;
-}
-
-struct blorp_address {
- drm_intel_bo *buffer;
- uint32_t read_domains;
- uint32_t write_domain;
- uint32_t offset;
-};
-
-static uint64_t
-blorp_emit_reloc(struct brw_context *brw, void *location,
- struct blorp_address address, uint32_t delta)
-{
- uint32_t offset = (char *)location - (char *)brw->batch.map;
- if (brw->gen >= 8) {
- return intel_batchbuffer_reloc64(brw, address.buffer, offset,
- address.read_domains,
- address.write_domain,
-
[Mesa-dev] [PATCH 22/32] i965/blorp/gen8: Move viewport setup to after wm state
This matches gen6 and gen7. --- src/mesa/drivers/dri/i965/gen8_blorp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/gen8_blorp.c b/src/mesa/drivers/dri/i965/gen8_blorp.c index 5085923..2e90438 100644 --- a/src/mesa/drivers/dri/i965/gen8_blorp.c +++ b/src/mesa/drivers/dri/i965/gen8_blorp.c @@ -509,7 +509,6 @@ gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params) brw_upload_state_base_address(brw); - gen7_blorp_emit_cc_viewport(brw); gen7_l3_state.emit(brw); gen7_blorp_emit_urb_config(brw, params); @@ -564,6 +563,8 @@ gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params) gen8_blorp_emit_wm_state(brw); + gen7_blorp_emit_cc_viewport(brw); + gen8_blorp_emit_depth_disable(brw); gen7_blorp_emit_clear_params(brw, params); gen6_blorp_emit_drawing_rectangle(brw, params); -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 16/32] i965/blorp: Move the non-static blorp state setup helpers to another file
We're about to start replacing blorp state setup code with packing structs
and we want to feel free to delete files as we go.
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_blorp_emit.c | 577 +
src/mesa/drivers/dri/i965/gen6_blorp.c | 375 ---
src/mesa/drivers/dri/i965/gen7_blorp.c | 166 -
4 files changed, 578 insertions(+), 541 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/brw_blorp_emit.c
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index 8626c7d..be6b1f9 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -102,6 +102,7 @@ i965_FILES = \
brw_binding_tables.c \
brw_blorp.c \
brw_blorp.h \
+ brw_blorp_emit.c \
brw_cc.c \
brw_clear.c \
brw_clip.c \
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_emit.c
b/src/mesa/drivers/dri/i965/brw_blorp_emit.c
new file mode 100644
index 000..c0a7e55
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_blorp_emit.c
@@ -0,0 +1,577 @@
+/*
+ * Copyright © 2011 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include
+
+#include "intel_batchbuffer.h"
+#include "intel_mipmap_tree.h"
+
+#include "brw_context.h"
+#include "brw_defines.h"
+#include "brw_state.h"
+
+#include "blorp_priv.h"
+#include "vbo/vbo.h"
+#include "brw_draw.h"
+
+static void
+gen6_blorp_emit_input_varying_data(struct brw_context *brw,
+ const struct brw_blorp_params *params,
+ unsigned *offset,
+ unsigned *size)
+{
+ const unsigned vec4_size_in_bytes = 4 * sizeof(float);
+ const unsigned max_num_varyings =
+ DIV_ROUND_UP(sizeof(params->wm_inputs), vec4_size_in_bytes);
+ const unsigned num_varyings = params->wm_prog_data->num_varying_inputs;
+
+ *size = num_varyings * vec4_size_in_bytes;
+
+ const float *const inputs_src = (const float *)¶ms->wm_inputs;
+ float *inputs = (float *)brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
+*size, 32, offset);
+
+ /* Walk over the attribute slots, determine if the attribute is used by
+* the program and when necessary copy the values from the input storage to
+* the vertex data buffer.
+*/
+ for (unsigned i = 0; i < max_num_varyings; i++) {
+ const gl_varying_slot attr = VARYING_SLOT_VAR0 + i;
+
+ if (!(params->wm_prog_data->inputs_read & BITFIELD64_BIT(attr)))
+ continue;
+
+ memcpy(inputs, inputs_src + i * 4, vec4_size_in_bytes);
+
+ inputs += 4;
+ }
+}
+
+static void
+gen6_blorp_emit_vertex_data(struct brw_context *brw,
+const struct brw_blorp_params *params)
+{
+ uint32_t vertex_offset;
+ uint32_t const_data_offset = 0;
+ unsigned const_data_size = 0;
+
+ /* Setup VBO for the rectangle primitive..
+*
+* A rectangle primitive (3DPRIM_RECTLIST) consists of only three
+* vertices. The vertices reside in screen space with DirectX coordinates
+* (that is, (0, 0) is the upper left corner).
+*
+* v2 -- implied
+*||
+*||
+* v0 - v1
+*
+* Since the VS is disabled, the clipper loads each VUE directly from
+* the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
+* 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
+* dw0: Reserved, MBZ.
+* dw1: Render Target Array Index. The HiZ op does not use indexed
+*vertices, so set the dword to 0.
+* dw2: Viewport Index. The HiZ op disables viewport mapping and
+*scissoring, so set the dword to 0.
+* dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
[Mesa-dev] [PATCH 17/32] i965/blorp: Don't clear an empty region
---
src/mesa/drivers/dri/i965/brw_blorp.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index f12c1f8..ccc7136 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -582,6 +582,10 @@ do_single_blorp_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
y1 = rb->Height - fb->_Ymin;
}
+ /* If the clear region is empty, just return. */
+ if (x0 == x1 || y0 == y1)
+ return true;
+
bool can_fast_clear = !partial_clear;
bool color_write_disable[4] = { false, false, false, false };
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 24/32] i965/blorp/gen6: Use genxml packing structs for state setup
---
src/mesa/drivers/dri/i965/Makefile.am | 1 +
src/mesa/drivers/dri/i965/gen6_blorp.c | 685 -
2 files changed, 256 insertions(+), 430 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/Makefile.am
b/src/mesa/drivers/dri/i965/Makefile.am
index 0a5222e..77ad1e8 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -36,6 +36,7 @@ AM_CFLAGS = \
-I$(top_srcdir)/src/compiler/nir \
-I$(top_srcdir)/src/intel \
-I$(top_builddir)/src/compiler/nir \
+ -I$(top_builddir)/src/intel \
-I$(top_builddir)/src/mesa/drivers/dri/common \
$(DEFINES) \
$(VISIBILITY_CFLAGS) \
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c
b/src/mesa/drivers/dri/i965/gen6_blorp.c
index 78e9472..875fdc9 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -27,469 +27,245 @@
#include "intel_mipmap_tree.h"
#include "brw_context.h"
-#include "brw_defines.h"
#include "brw_state.h"
#include "blorp_priv.h"
-#include "vbo/vbo.h"
-#include "brw_draw.h"
-/* 3DSTATE_URB
- *
- * Assign the entire URB to the VS. Even though the VS disabled, URB space
- * is still needed because the clipper loads the VUE's from the URB. From
- * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
- * Dword 1.15:0 "VS Number of URB Entries":
- * This field is always used (even if VS Function Enable is DISABLED).
- *
- * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
- * safely ignore it because this batch contains only one draw call.
- * Because of URB corruption caused by allocating a previous GS unit
- * URB entry to the VS unit, software is required to send a “GS NULL
- * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
- * plus a dummy DRAW call before any case where VS will be taking over
- * GS URB space.
- */
-static void
-gen6_blorp_emit_urb_config(struct brw_context *brw,
- const struct brw_blorp_params *params)
-{
- BEGIN_BATCH(3);
- OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
- OUT_BATCH(brw->urb.max_vs_entries << GEN6_URB_VS_ENTRIES_SHIFT);
- OUT_BATCH(0);
- ADVANCE_BATCH();
-}
+#define GEN_VERSIONx10 60
+#include "genxml/gen_macros.h"
-
-/* 3DSTATE_CC_STATE_POINTERS
- *
- * The pointer offsets are relative to
- * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
- *
- * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
- */
-static void
-gen6_blorp_emit_cc_state_pointers(struct brw_context *brw,
- const struct brw_blorp_params *params,
- uint32_t cc_blend_state_offset,
- uint32_t depthstencil_offset,
- uint32_t cc_state_offset)
+static void *
+blorp_emit_dwords(struct brw_context *brw, unsigned n)
{
- BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
- OUT_BATCH(cc_blend_state_offset | 1); /* BLEND_STATE offset */
- OUT_BATCH(depthstencil_offset | 1); /* DEPTH_STENCIL_STATE offset */
- OUT_BATCH(cc_state_offset | 1); /* COLOR_CALC_STATE offset */
- ADVANCE_BATCH();
+ intel_batchbuffer_begin(brw, n, RENDER_RING);
+ uint32_t *map = brw->batch.map_next;
+ brw->batch.map_next += n;
+ intel_batchbuffer_advance(brw);
+ return map;
}
+struct blorp_address {
+ drm_intel_bo *buffer;
+ uint32_t read_domains;
+ uint32_t write_domain;
+ uint32_t offset;
+};
-/**
- * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers().
- */
-static void
-gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw,
- uint32_t sampler_offset)
+static uint64_t
+blorp_emit_reloc(struct brw_context *brw, void *location,
+ struct blorp_address address, uint32_t delta)
{
- BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 |
- VS_SAMPLER_STATE_CHANGE |
- GS_SAMPLER_STATE_CHANGE |
- PS_SAMPLER_STATE_CHANGE |
- (4 - 2));
- OUT_BATCH(0); /* VS */
- OUT_BATCH(0); /* GS */
- OUT_BATCH(sampler_offset);
- ADVANCE_BATCH();
+ uint32_t offset = (char *)location - (char *)brw->batch.map;
+ if (brw->gen >= 8) {
+ return intel_batchbuffer_reloc64(brw, address.buffer, offset,
+ address.read_domains,
+ address.write_domain,
+ address.offset + delta);
+ } else {
+ return intel_batchbuffer_reloc(brw, address.buffer, offset,
+ address.read_domains,
+ address.write_domain,
+ address.offset + delta);
+ }
}
+#define __gen_address_type struct blorp_address
+#define __gen_user_data struct brw_context
-/* 3DSTATE_VS
- *
- * Disable vertex shader
[Mesa-dev] [PATCH 07/32] genxml/gen6: Make SAMPLER_STATE look a bit more like gen7
--- src/intel/genxml/gen6.xml | 45 ++--- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 3fe7377..2499b46 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -414,14 +414,7 @@ - - - - - - - - + @@ -434,17 +427,22 @@ - - - - - - - - - - - + + + + + + + + + + + + + + + + @@ -717,6 +715,15 @@ + + + + + + + + + -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 08/32] genxml: Make VERTEX_ELEMENT_STATE::Valid a bool
--- src/intel/genxml/gen6.xml | 2 +- src/intel/genxml/gen7.xml | 2 +- src/intel/genxml/gen75.xml | 2 +- src/intel/genxml/gen8.xml | 2 +- src/intel/genxml/gen9.xml | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 2499b46..a281a1a 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -21,7 +21,7 @@ - + diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 7e34fd6..3fe47c7 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -35,7 +35,7 @@ - + diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index f0ad177..63449a9 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -45,7 +45,7 @@ - + diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index 4ed23db..828ad90 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -49,7 +49,7 @@ - + diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 9361edf..b72f9bf 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -37,7 +37,7 @@ - + -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 21/32] i965/blorp/gen6-7: Move multisample setup to right after samplers
This mimics gen8 blorp
---
src/mesa/drivers/dri/i965/gen6_blorp.c | 9 +
src/mesa/drivers/dri/i965/gen7_blorp.c | 10 +-
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c
b/src/mesa/drivers/dri/i965/gen6_blorp.c
index b252d78..7d37ea3 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.c
@@ -515,10 +515,6 @@ gen6_blorp_exec(struct brw_context *brw,
brw_upload_state_base_address(brw);
- gen6_emit_3dstate_multisample(brw, params->dst.surf.samples);
- gen6_emit_3dstate_sample_mask(brw,
- params->dst.surf.samples > 1 ?
- (1 << params->dst.surf.samples) - 1 : 1);
gen6_blorp_emit_vertices(brw, params);
gen6_blorp_emit_urb_config(brw, params);
if (params->wm_prog_data) {
@@ -559,6 +555,11 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset);
}
+ gen6_emit_3dstate_multisample(brw, params->dst.surf.samples);
+ gen6_emit_3dstate_sample_mask(brw,
+ params->dst.surf.samples > 1 ?
+ (1 << params->dst.surf.samples) - 1 : 1);
+
gen6_blorp_emit_vs_disable(brw, params);
gen6_blorp_emit_gs_disable(brw, params);
gen6_blorp_emit_clip_disable(brw);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c
b/src/mesa/drivers/dri/i965/gen7_blorp.c
index adbf909..1b9c853 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.c
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.c
@@ -468,11 +468,6 @@ gen7_blorp_exec(struct brw_context *brw,
uint32_t wm_bind_bo_offset = 0;
brw_upload_state_base_address(brw);
-
- gen6_emit_3dstate_multisample(brw, params->dst.surf.samples);
- gen6_emit_3dstate_sample_mask(brw,
- params->dst.surf.samples > 1 ?
- (1 << params->dst.surf.samples) - 1 : 1);
gen6_blorp_emit_vertices(brw, params);
gen7_blorp_emit_urb_config(brw, params);
if (params->wm_prog_data) {
@@ -520,6 +515,11 @@ gen7_blorp_exec(struct brw_context *brw,
gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
}
+ gen6_emit_3dstate_multisample(brw, params->dst.surf.samples);
+ gen6_emit_3dstate_sample_mask(brw,
+ params->dst.surf.samples > 1 ?
+ (1 << params->dst.surf.samples) - 1 : 1);
+
gen7_blorp_emit_vs_disable(brw);
gen7_blorp_emit_hs_disable(brw);
gen7_blorp_emit_te_disable(brw);
--
2.5.0.400.gff86faf
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[Mesa-dev] [PATCH 09/32] genxml: Make a couple of VERTEX_BUFFER_STATE fields boolean
--- src/intel/genxml/gen6.xml | 2 +- src/intel/genxml/gen7.xml | 4 ++-- src/intel/genxml/gen75.xml | 4 ++-- src/intel/genxml/gen8.xml | 2 +- src/intel/genxml/gen9.xml | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index a281a1a..6241665 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -12,7 +12,7 @@ - + diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 3fe47c7..adf764e 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -24,9 +24,9 @@ - + - + diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index 63449a9..b93e920 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -34,9 +34,9 @@ - + - + diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index 828ad90..d460c48 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -40,7 +40,7 @@ - + diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index b72f9bf..4837b3c 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -28,7 +28,7 @@ - + -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 11/32] genxml/gen9: Make 3DSTATE_SBE::AttributeActiveComponentFormat an array
--- src/intel/genxml/gen9.xml | 35 +++- src/intel/vulkan/genX_pipeline_util.h | 38 +++ 2 files changed, 6 insertions(+), 67 deletions(-) diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 51a2420..547d47f 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -2097,38 +2097,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h index d3b15d9..0e6dcd1 100644 --- a/src/intel/vulkan/genX_pipeline_util.h +++ b/src/intel/vulkan/genX_pipeline_util.h @@ -236,44 +236,12 @@ emit_3dstate_sbe(struct anv_pipeline *pipeline) .PointSpriteTextureCoordinateOrigin = UPPERLEFT, .NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs, .ConstantInterpolationEnable = wm_prog_data->flat_inputs, + }; #if GEN_GEN >= 9 - .Attribute0ActiveComponentFormat = ACF_XYZW, - .Attribute1ActiveComponentFormat = ACF_XYZW, - .Attribute2ActiveComponentFormat = ACF_XYZW, - .Attribute3ActiveComponentFormat = ACF_XYZW, - .Attribute4ActiveComponentFormat = ACF_XYZW, - .Attribute5ActiveComponentFormat = ACF_XYZW, - .Attribute6ActiveComponentFormat = ACF_XYZW, - .Attribute7ActiveComponentFormat = ACF_XYZW, - .Attribute8ActiveComponentFormat = ACF_XYZW, - .Attribute9ActiveComponentFormat = ACF_XYZW, - .Attribute10ActiveComponentFormat = ACF_XYZW, - .Attribute11ActiveComponentFormat = ACF_XYZW, - .Attribute12ActiveComponentFormat = ACF_XYZW, - .Attribute13ActiveComponentFormat = ACF_XYZW, - .Attribute14ActiveComponentFormat = ACF_XYZW, - .Attribute15ActiveComponentFormat = ACF_XYZW, - /* wow, much field, very attribute */ - .Attribute16ActiveComponentFormat = ACF_XYZW, - .Attribute17ActiveComponentFormat = ACF_XYZW, - .Attribute18ActiveComponentFormat = ACF_XYZW, - .Attribute19ActiveComponentFormat = ACF_XYZW, - .Attribute20ActiveComponentFormat = ACF_XYZW, - .Attribute21ActiveComponentFormat = ACF_XYZW, - .Attribute22ActiveComponentFormat = ACF_XYZW, - .Attribute23ActiveComponentFormat = ACF_XYZW, - .Attribute24ActiveComponentFormat = ACF_XYZW, - .Attribute25ActiveComponentFormat = ACF_XYZW, - .Attribute26ActiveComponentFormat = ACF_XYZW, - .Attribute27ActiveComponentFormat = ACF_XYZW, - .Attribute28ActiveComponentFormat = ACF_XYZW, - .Attribute29ActiveComponentFormat = ACF_XYZW, - .Attribute28ActiveComponentFormat = ACF_XYZW, - .Attribute29ActiveComponentFormat = ACF_XYZW, - .Attribute30ActiveComponentFormat = ACF_XYZW, + for (unsigned i = 0; i < 32; i++) + sbe.AttributeActiveComponentFormat[i] = ACF_XYZW; #endif - }; #if GEN_GEN >= 8 /* On Broadwell, they broke 3DSTATE_SBE into two packets */ -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 03/32] genxml/gen6: Fix the length of 3DSTATE_WM
--- src/intel/genxml/gen6.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 6ece749..1be0ede 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -1365,12 +1365,12 @@ - + - + -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 00/32] i965/blorp: Use genxml for state setup
This patch series is the next on the way towards generalizing blorp for usin in Vulkan. At this point, I'd say the project is about 80% complete. This series only applies on top of the last two blorp isl series which are still undergoing review. Patches 1-11 make minor genxml improvements. Some of this is to make gen6 better and more like gen7-9. The others are just general improvements that made converting blorp easier. Patches 12-14 make a few minor changes to i965 so that we can include brw_state.h and brw_context.h without brw_defines.h. Patches 15-23 re-arrange the state setup code in blorp to make the different gens emit the packets more-or-less in the same order. This was very helpful when trying to debug problems when switching to genxml because there should not be substantial changes in the batch between patch 23 and the end of the series. Patches 24-32 convert all of the blorp state setup to using genxml in a single file that gets recompiled 5 times, one for each gen. I'm extremely happy with the end result where almost all of the code is shared across gens. The one exception is WM and SF setup which is so different that we really need different code for gen6, gen7, and gen8. This series can be found here: https://cgit.freedesktop.org/~jekstrand/mesa/log/?h=review/blorp-genxml Cc: Topi Pohjolainen Jason Ekstrand (32): genxml/gen6: Add uint MOCS fields for most things genxml/gen6: Add a Surface Base Address field to HIER_DEPTH_BUFFER genxml/gen6: Fix the length of 3DSTATE_WM genxml/gen6: Add the 3D_Prim_Topo_Type enum genxml/gen6: Make "Depth Clear Value" a uint genxml: Add a uint MOCS field to DEPTH_BUFFER packets genxml/gen6: Make SAMPLER_STATE look a bit more like gen7 genxml: Make VERTEX_ELEMENT_STATE::Valid a bool genxml: Make a couple of VERTEX_BUFFER_STATE fields boolean genxml: Add a uint MOCS field to VERTEX_BUFFER_STATE genxml/gen9: Make 3DSTATE_SBE::AttributeActiveComponentFormat an array i965/state: Move is_drawing_lines/points to gen6_clip_state.c i965: Stop including brw_defines.h in brw_state.h i965: Roll intel_reg.h into brw_defines.h i965/blorp: Make gen6 VS and GS disable helpers static i965/blorp: Move the non-static blorp state setup helpers to another file i965/blorp: Don't clear an empty region i965/blorp/gen6: Move constant disables higher up i965/blorp/gen7-8: Emit depth stencil state with CC and BLEND i965/blorp/gen6-7: Move surfaces and samplers closer together i965/blorp/gen6-7: Move multisample setup to right after samplers i965/blorp/gen8: Move viewport setup to after wm state i965/blorp: Stop setting point and line rasterization rules i965/blorp/gen6: Use genxml packing structs for state setup i965: Move gen6_blorp.c to a file that gets recompiled per-gen i965/blorp: Add genxml-based dynamic state emit functions i965/blorp: Add genxml-based sampler state emit function i965/blorp: Add a helper for emitting surface states i965/blorp: Add genxml-based vertex setup helpers i965/blorp: Use genxml for gen7 state setup i965/blorp: Use genxml for gen8-9 state setup i965/blorp: Remove no longer used state setup helpers src/intel/genxml/gen6.xml | 93 +- src/intel/genxml/gen7.xml |9 +- src/intel/genxml/gen75.xml |9 +- src/intel/genxml/gen8.xml |7 +- src/intel/genxml/gen9.xml | 42 +- src/intel/vulkan/genX_pipeline_util.h | 38 +- src/mesa/drivers/dri/i965/Makefile.am | 31 +- src/mesa/drivers/dri/i965/Makefile.sources | 19 +- src/mesa/drivers/dri/i965/blorp.c |9 +- src/mesa/drivers/dri/i965/blorp_priv.h | 94 +- src/mesa/drivers/dri/i965/brw_blorp.c |4 + src/mesa/drivers/dri/i965/brw_defines.h| 273 ++ src/mesa/drivers/dri/i965/brw_meta_util.c |1 + src/mesa/drivers/dri/i965/brw_pipe_control.c |2 +- src/mesa/drivers/dri/i965/brw_queryobj.c |1 - src/mesa/drivers/dri/i965/brw_state.h | 56 +- src/mesa/drivers/dri/i965/gen6_blorp.c | 965 - src/mesa/drivers/dri/i965/gen6_clip_state.c| 54 +- src/mesa/drivers/dri/i965/gen6_queryobj.c |1 - src/mesa/drivers/dri/i965/gen6_sf_state.c |4 +- src/mesa/drivers/dri/i965/gen7_blorp.c | 708 --- src/mesa/drivers/dri/i965/gen7_sf_state.c |2 +- src/mesa/drivers/dri/i965/gen8_blorp.c | 578 - src/mesa/drivers/dri/i965/genX_blorp_exec.c| 1103 src/mesa/drivers/dri/i965/hsw_queryobj.c |1 - src/mesa/drivers/dri/i965/intel_batchbuffer.c |1 - src/mesa/drivers/dri/i965/intel_batchbuffer.h |1 - src/mesa/drivers/dri/i965/intel_blit.c |1 - src/mesa/drivers/dri/i965/intel_extensions.c |1 + src/mesa/drivers/dri/i965/intel_fbo.c |1 + src/mesa/d
[Mesa-dev] [PATCH 05/32] genxml/gen6: Make "Depth Clear Value" a uint
The actual data storred is in float, UNORM24, or UNORM16 depending on the actual depth format. --- src/intel/genxml/gen6.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index ae317a13..06b441b 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -797,7 +797,7 @@ - + -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 02/32] genxml/gen6: Add a Surface Base Address field to HIER_DEPTH_BUFFER
--- src/intel/genxml/gen6.xml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 0f2be24..6ece749 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -1007,14 +1007,15 @@ - + - + + -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 01/32] genxml/gen6: Add uint MOCS fields for most things
--- src/intel/genxml/gen6.xml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index cf94efc..0f2be24 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -1883,20 +1883,26 @@ + + + + + + -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 06/32] genxml: Add a uint MOCS field to DEPTH_BUFFER packets
This is easier than dealing with structs all the time --- src/intel/genxml/gen6.xml | 2 ++ src/intel/genxml/gen7.xml | 2 ++ src/intel/genxml/gen75.xml | 2 ++ src/intel/genxml/gen8.xml | 2 ++ src/intel/genxml/gen9.xml | 2 ++ 5 files changed, 10 insertions(+) diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 06b441b..3fe7377 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -958,6 +958,7 @@ + @@ -1038,6 +1039,7 @@ + diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 5e82fab..7e34fd6 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -1068,6 +1068,7 @@ + @@ -1198,6 +1199,7 @@ + diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index f1be2f84..f0ad177 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -1177,6 +1177,7 @@ + @@ -1410,6 +1411,7 @@ + diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index 8145ddd..4ed23db 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -1216,6 +1216,7 @@ + @@ -1452,6 +1453,7 @@ + diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 1838d2c..9361edf 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -1266,6 +1266,7 @@ + @@ -1555,6 +1556,7 @@ + -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 04/32] genxml/gen6: Add the 3D_Prim_Topo_Type enum
--- src/intel/genxml/gen6.xml | 24 1 file changed, 24 insertions(+) diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 1be0ede..ae317a13 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -447,6 +447,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/3] glsl: Fix inout qualifier handling in GLSL 4.40.
inout variables have q.in and q.out set. We were trying to set
xfb_buffer = 1 for shader output variables (and inadvertantly setting
it on inout parameters, too). But input_layout_mask doesn't have
xfb_buffer set, so it was seen as in invalid input qualifier.
This meant that all 'inout' parameters were broken.
Caught by running a WebGL conformance test in Chromium:
https://www.khronos.org/registry/webgl/sdk/tests/deqp/data/gles3/shaders/qualification_order.html?webglVersion=2
Fixes Piglit's tests/spec/glsl-4.40/compiler/inout-parameter-qualifier.
Cc: Timothy Arceri
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/ast_type.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index ef573e7..248b647 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -242,7 +242,8 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
if (q.flags.q.xfb_buffer) {
this->flags.q.xfb_buffer = 1;
this->xfb_buffer = q.xfb_buffer;
- } else if (!this->flags.q.xfb_buffer && this->flags.q.out) {
+ } else if (!this->flags.q.xfb_buffer && this->flags.q.out &&
+!this->flags.q.in) {
/* Assign global xfb_buffer value */
this->flags.q.xfb_buffer = 1;
this->xfb_buffer = state->out_qualifier->xfb_buffer;
--
2.9.2
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[Mesa-dev] [PATCH 3/3] glsl: Fix invariant matching in GLSL 4.30 and GLSL ES 1.00.
Old languages (GLSL <= 4.20 and GLSL ES 1.00) require "invariant"
to be specified on both inputs and outputs, and match when linking.
New languages only allow outputs to be qualified as "invariant"
and remove the "invariant must match" restriction when linking
varyings (because no input can have that qualifier).
Commit 426a50e2089b12d33f5c075aa5622f64076914a3 introduced the new
behavior for ES 3.00. It also removed the "must match" restriction
for ES 1.00 shaders, which I believe is incorrect. This patch adds
that back, as well as making 4.30+ follow the new rules.
Thanks to Qiankun Miao for noticing this discrepancy.
Fixes a WebGL 2.0 conformance test when run in Chromium:
https://www.khronos.org/registry/webgl/sdk/tests/deqp/data/gles3/shaders/qualification_order.html?webglVersion=2
Cc: mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96971
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/glsl_parser.yy| 4 +++-
src/compiler/glsl/link_varyings.cpp | 20 +++-
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index 4ab9e14..4f4a83c 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -1774,8 +1774,10 @@ type_qualifier:
* variables. As only outputs can be declared as invariant, an invariant
* output from one shader stage will still match an input of a subsequent
* stage without the input being declared as invariant."
+ *
+ * On the desktop side, this text first appears in GLSL 4.30.
*/
- if (state->es_shader && state->language_version >= 300 && $$.flags.q.in)
+ if (state->is_version(430, 300) && $$.flags.q.in)
_mesa_glsl_error(&@1, state, "invariant qualifiers cannot be used
with shader inputs");
}
| interpolation_qualifier type_qualifier
diff --git a/src/compiler/glsl/link_varyings.cpp
b/src/compiler/glsl/link_varyings.cpp
index b4799d2..1bce3e0 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -308,7 +308,25 @@ cross_validate_types_and_qualifiers(struct
gl_shader_program *prog,
return;
}
- if (!prog->IsES && input->data.invariant != output->data.invariant) {
+ /* The GLSL 4.30 and GLSL ES 3.00 specifications say:
+*
+*"As only outputs need be declared with invariant, an output from
+* one shader stage will still match an input of a subsequent stage
+* without the input being declared as invariant."
+*
+* while GLSL 4.20 says:
+*
+*"For variables leaving one shader and coming into another shader,
+* the invariant keyword has to be used in both shaders, or a link
+* error will result."
+*
+* and GLSL ES 1.00 section 4.6.4 "Invariance and Linking" says:
+*
+*"The invariance of varyings that are declared in both the vertex
+* and fragment shaders must match."
+*/
+ if (input->data.invariant != output->data.invariant &&
+ prog->Version < (prog->IsES ? 300 : 430)) {
linker_error(prog,
"%s shader output `%s' %s invariant qualifier, "
"but %s shader input %s invariant qualifier\n",
--
2.9.2
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[Mesa-dev] [PATCH 2/3] glsl: Tidy stream handling in merge_qualifier().
The previous commit fixed xfb_buffer handling, which was largely copy
and pasted from the stream handling. The difference is that stream
was set in input_layout_mask, so it worked.
However, that's totally rubbish: stream is only valid on geometry shader
outputs. Presumably this was to hack around inout. Instead, apply the
solution I used in the previous fix.
Really, we just need to separate shader interface and parameter
qualifier handling so this isn't a mess, but this patch at least
tidies it slightly.
Cc: Timothy Arceri
Signed-off-by: Kenneth Graunke
---
src/compiler/glsl/ast_type.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 248b647..cabc698 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -178,8 +178,6 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
if (state->stage == MESA_SHADER_GEOMETRY) {
allowed_duplicates_mask.flags.i |=
stream_layout_mask.flags.i;
- input_layout_mask.flags.i |=
- stream_layout_mask.flags.i;
}
if (is_single_layout_merge && !state->has_enhanced_layouts() &&
@@ -229,7 +227,8 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
if (q.flags.q.stream) {
this->flags.q.stream = 1;
this->stream = q.stream;
- } else if (!this->flags.q.stream && this->flags.q.out) {
+ } else if (!this->flags.q.stream && this->flags.q.out &&
+!this->flags.q.in) {
/* Assign default global stream value */
this->flags.q.stream = 1;
this->stream = state->out_qualifier->stream;
--
2.9.2
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[Mesa-dev] [Bug 97307] glsl/glcpp/tests/glcpp-test regression
https://bugs.freedesktop.org/show_bug.cgi?id=97307 Bug ID: 97307 Summary: glsl/glcpp/tests/glcpp-test regression Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: All Status: NEW Keywords: bisected, regression Severity: normal Priority: medium Component: Mesa core Assignee: mesa-dev@lists.freedesktop.org Reporter: v...@freedesktop.org QA Contact: mesa-dev@lists.freedesktop.org CC: i...@freedesktop.org, t_arc...@yahoo.com.au mesa: 17f1c49b9ad05af4f6482f6fa950e5dcc1a779d1 (master 12.1.0-devel) Testing ./glsl/glcpp/tests/120-undef-builtin.c... > src/compiler/glsl/glcpp/tests/120-undef-builtin.c.out (./glsl/glcpp/tests/120-undef-builtin.c.expected) FAIL --- ./glsl/glcpp/tests/120-undef-builtin.c.expected 2016-01-26 09:59:33.017797268 -0800 +++ src/compiler/glsl/glcpp/tests/120-undef-builtin.c.out 2016-08-11 10:30:15.630875304 -0700 @@ -1,6 +1,3 @@ -0:1(1): preprocessor error: Built-in (pre-defined) macro names cannot be undefined. -0:2(1): preprocessor error: Built-in (pre-defined) macro names cannot be undefined. -0:3(1): preprocessor error: Built-in (pre-defined) macro names cannot be undefined. 50b49d242d702e4728329cc59f87d929963e7c53 is the first bad commit commit 50b49d242d702e4728329cc59f87d929963e7c53 Author: Ian Romanick Date: Tue Aug 9 14:32:24 2016 -0700 glcpp: Only disallow #undef of pre-defined macros on GLSL ES >= 3.00 shaders Section 3.4 (Preprocessor) of the GLSL ES 3.00 spec says: It is an error to undefine or to redefine a built-in (pre-defined) macro name. The GLSL ES 1.00 spec does not contain this text. Section 3.3 (Preprocessor) of the GLSL 1.30 spec says: #define and #undef functionality are defined as is standard for C++ preprocessors for macro definitions both with and without macro parameters. At least as far as I can tell GCC allow '#undef __FILE__'. Furthermore, there are desktop OpenGL conformance tests that expect '#undef __VERSION__' and '#undef GL_core_profile' to work. Fixes: GL45-CTS.shaders.preprocessor.definitions.undefine_version_vertex GL45-CTS.shaders.preprocessor.definitions.undefine_version_fragment GL45-CTS.shaders.preprocessor.definitions.undefine_core_profile_vertex GL45-CTS.shaders.preprocessor.definitions.undefine_core_profile_fragment Signed-off-by: Ian Romanick Reviewed-by: Timothy Arceri Cc: mesa-sta...@lists.freedesktop.org :04 04 fbe8d2e45f4f1e6755e70b6e6f8fa971701e3ae8 d7c77a29d8aa922a28948df34eca499077eaac45 M src bisect run success -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/4] gallium/winsys: re-number winsys priority flags
From: Marek Olšák
free 60..63, move CP_DMA up
---
src/gallium/drivers/radeon/radeon_winsys.h | 29 +
1 file changed, 13 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index e4d669f..8a98ebf 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -173,57 +173,54 @@ enum radeon_bo_priority {
RADEON_PRIO_FENCE = 0,
RADEON_PRIO_TRACE,
RADEON_PRIO_SO_FILLED_SIZE,
RADEON_PRIO_QUERY,
RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
RADEON_PRIO_DRAW_INDIRECT,
RADEON_PRIO_INDEX_BUFFER,
-RADEON_PRIO_CP_DMA = 8,
-
-RADEON_PRIO_VCE = 12,
+RADEON_PRIO_VCE = 8,
RADEON_PRIO_UVD,
RADEON_PRIO_SDMA_BUFFER,
RADEON_PRIO_SDMA_TEXTURE,
-RADEON_PRIO_USER_SHADER = 16,
+RADEON_PRIO_CP_DMA = 12,
+RADEON_PRIO_USER_SHADER,
RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
-/* gap: 20 */
-
-RADEON_PRIO_CONST_BUFFER = 24,
+RADEON_PRIO_CONST_BUFFER = 16,
RADEON_PRIO_DESCRIPTORS,
RADEON_PRIO_BORDER_COLORS,
-RADEON_PRIO_SAMPLER_BUFFER = 28,
+RADEON_PRIO_SAMPLER_BUFFER = 20,
RADEON_PRIO_VERTEX_BUFFER,
-RADEON_PRIO_SHADER_RW_BUFFER = 32,
+RADEON_PRIO_SHADER_RW_BUFFER = 24,
RADEON_PRIO_SCRATCH_BUFFER,
RADEON_PRIO_COMPUTE_GLOBAL,
-RADEON_PRIO_SAMPLER_TEXTURE = 36,
+RADEON_PRIO_SAMPLER_TEXTURE = 28,
RADEON_PRIO_SHADER_RW_IMAGE,
-RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
+RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
-RADEON_PRIO_COLOR_BUFFER = 44,
+RADEON_PRIO_COLOR_BUFFER = 36,
-RADEON_PRIO_DEPTH_BUFFER = 48,
+RADEON_PRIO_DEPTH_BUFFER = 40,
-RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
+RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
-RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
+RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
-RADEON_PRIO_CMASK = 60,
+RADEON_PRIO_CMASK = 52,
RADEON_PRIO_DCC,
RADEON_PRIO_HTILE,
RADEON_PRIO_SHADER_RINGS,
/* 63 is the maximum value */
};
struct winsys_handle;
struct radeon_winsys_ctx;
struct radeon_winsys_cs_chunk {
--
2.7.4
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[Mesa-dev] [PATCH 2/4] gallium/radeon: mark shader rings as highest-priority buffers
From: Marek Olšák
and rename the enum
---
src/gallium/drivers/r600/evergreen_state.c| 4 ++--
src/gallium/drivers/r600/r600_state.c | 4 ++--
src/gallium/drivers/radeon/radeon_winsys.h| 2 +-
src/gallium/drivers/radeonsi/si_debug.c | 2 +-
src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 463dc15..7611520 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2273,31 +2273,31 @@ static void evergreen_emit_gs_rings(struct r600_context
*rctx, struct r600_atom
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
if (state->enable) {
rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
rbuffer->gpu_address >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
-
RADEON_PRIO_RINGS_STREAMOUT));
+
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
state->esgs_ring.buffer_size >> 8);
rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
rbuffer->gpu_address >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
-
RADEON_PRIO_RINGS_STREAMOUT));
+
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
state->gsvs_ring.buffer_size >> 8);
} else {
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
}
radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
S_008040_WAIT_3D_IDLE(1));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 5b47089..046573f 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1956,30 +1956,30 @@ static void r600_emit_gs_rings(struct r600_context
*rctx, struct r600_atom *a)
radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
S_008040_WAIT_3D_IDLE(1));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
if (state->enable) {
rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
-
RADEON_PRIO_RINGS_STREAMOUT));
+
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
state->esgs_ring.buffer_size >> 8);
rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
-
RADEON_PRIO_RINGS_STREAMOUT));
+
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
state->gsvs_ring.buffer_size >> 8);
} else {
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
}
radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
S_008040_WAIT_3D_IDLE(1));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
diff --git a/src/gallium/dri
[Mesa-dev] [PATCH 4/4] gallium/radeon: assign the highest priority to scratch; make rings second
From: Marek Olšák
just FYI, the kernel receives priority/4
---
src/gallium/drivers/radeon/radeon_winsys.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 8a98ebf..c65b9a4 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -190,40 +190,42 @@ enum radeon_bo_priority {
RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
RADEON_PRIO_CONST_BUFFER = 16,
RADEON_PRIO_DESCRIPTORS,
RADEON_PRIO_BORDER_COLORS,
RADEON_PRIO_SAMPLER_BUFFER = 20,
RADEON_PRIO_VERTEX_BUFFER,
RADEON_PRIO_SHADER_RW_BUFFER = 24,
-RADEON_PRIO_SCRATCH_BUFFER,
RADEON_PRIO_COMPUTE_GLOBAL,
RADEON_PRIO_SAMPLER_TEXTURE = 28,
RADEON_PRIO_SHADER_RW_IMAGE,
RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
RADEON_PRIO_COLOR_BUFFER = 36,
RADEON_PRIO_DEPTH_BUFFER = 40,
RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
RADEON_PRIO_CMASK = 52,
RADEON_PRIO_DCC,
RADEON_PRIO_HTILE,
-RADEON_PRIO_SHADER_RINGS,
+
+RADEON_PRIO_SHADER_RINGS = 56,
+
+RADEON_PRIO_SCRATCH_BUFFER = 60,
/* 63 is the maximum value */
};
struct winsys_handle;
struct radeon_winsys_ctx;
struct radeon_winsys_cs_chunk {
unsigned cdw; /* Number of used dwords. */
unsigned max_dw; /* Maximum number of dwords. */
uint32_t *buf; /* The base pointer of the chunk. */
--
2.7.4
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[Mesa-dev] [PATCH 1/4] gallium/radeon: set SHADER_RW_BUFFER priority for streamout buffers
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_streamout.c | 4 ++--
src/gallium/drivers/radeonsi/si_descriptors.c | 6 --
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_streamout.c
b/src/gallium/drivers/radeon/r600_streamout.c
index 705eb13..b5296aa 100644
--- a/src/gallium/drivers/radeon/r600_streamout.c
+++ b/src/gallium/drivers/radeon/r600_streamout.c
@@ -211,31 +211,31 @@ static void r600_emit_streamout_begin(struct
r600_common_context *rctx, struct r
update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
radeon_set_context_reg_seq(cs,
R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
radeon_emit(cs, (t[i]->b.buffer_offset +
t[i]->b.buffer_size) >> 2);/*
BUFFER_SIZE (in DW) */
radeon_emit(cs, stride_in_dw[i]); /*
VTX_STRIDE (in DW) */
radeon_emit(cs, va >> 8); /*
BUFFER_BASE */
r600_emit_reloc(rctx, &rctx->gfx,
r600_resource(t[i]->b.buffer),
- RADEON_USAGE_WRITE,
RADEON_PRIO_RINGS_STREAMOUT);
+ RADEON_USAGE_WRITE,
RADEON_PRIO_SHADER_RW_BUFFER);
/* R7xx requires this packet after updating BUFFER_BASE.
* Without this, R7xx locks up. */
if (rctx->family >= CHIP_RS780 && rctx->family <=
CHIP_RV740) {
radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE,
1, 0));
radeon_emit(cs, i);
radeon_emit(cs, va >> 8);
r600_emit_reloc(rctx, &rctx->gfx,
r600_resource(t[i]->b.buffer),
- RADEON_USAGE_WRITE,
RADEON_PRIO_RINGS_STREAMOUT);
+ RADEON_USAGE_WRITE,
RADEON_PRIO_SHADER_RW_BUFFER);
}
}
if (rctx->streamout.append_bitmask & (1 << i) &&
t[i]->buf_filled_size_valid) {
uint64_t va = t[i]->buf_filled_size->gpu_address +
t[i]->buf_filled_size_offset;
/* Append. */
radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 1d04a9c..fcc8a32 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1304,21 +1304,22 @@ static void si_set_streamout_targets(struct
pipe_context *ctx,
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
/* Set the resource. */
pipe_resource_reference(&buffers->buffers[bufidx],
buffer);
radeon_add_to_buffer_list_check_mem(&sctx->b,
&sctx->b.gfx,
(struct
r600_resource*)buffer,
buffers->shader_usage,
- buffers->priority,
true);
+
RADEON_PRIO_SHADER_RW_BUFFER,
+ true);
buffers->enabled_mask |= 1u << bufidx;
} else {
/* Clear the descriptor and unset the resource. */
memset(descs->list + bufidx*4, 0,
sizeof(uint32_t) * 4);
pipe_resource_reference(&buffers->buffers[bufidx],
NULL);
buffers->enabled_mask &= ~(1u << bufidx);
}
descs->dirty_mask |= 1u << bufidx;
@@ -1467,21 +1468,22 @@ static void si_invalidate_buffer(struct pipe_context
*ctx, struct pipe_resource
if (buffers->buffers[i] != buf)
continue;
si_desc_reset_buffer_offset(ctx, descs->list + i*4,
old_va, buf);
descs->dirty_mask |= 1u << i;
sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
rbuffer,
buffers->shader_usage,
- buffers->priority, true);
Re: [Mesa-dev] [PATCH 0/5] isl: Update the format table and add asserts
On Tue, Jul 26, 2016 at 10:04:21PM -0700, Jason Ekstrand wrote: > The real objective of this series is patch 5 which prevents us from > accidentally creating a surface state with a format unsupported by the > hardware. This turns some of the new Vulkan CTS tests from a hang into an > informative crash. In order to get there, however, we needed to update the > format table in isl with some of the new formats added on Haswell and later > generations. In order to do that, we had to fix up the dri driver, and own > the rabbit hole we go! > Contrary to your introduction, I cannot see how patches 4 and 5 are dependent on patches 1-3. Could you please explain this further? - Nanley > At the end of the series, the hangs in the latest CTS are gone (they came > from trying to clear an unsupported image format). > > Jason Ekstrand (5): > i965/surface_formats: Don't advertise 8 or 16-bit RGB formats > isl/formats: Report ETC as being samplable on Bay Trail > isl/formats: Update the table with more samplable formats > anv/image: Don't create invalid render target surfaces > isl/state: Add some asserts about format capabilities > > src/intel/isl/isl_format.c | 48 > + > src/intel/isl/isl_surface_state.c | 5 +++ > src/intel/vulkan/anv_image.c| 13 ++- > src/mesa/drivers/dri/i965/brw_surface_formats.c | 10 ++ > 4 files changed, 60 insertions(+), 16 deletions(-) > > -- > 2.5.0.400.gff86faf > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 97291] Incorrect packing of struct
https://bugs.freedesktop.org/show_bug.cgi?id=97291 --- Comment #4 from Matias N. Goldberg --- OK I'm fully re-powered and thinking straight now: I've built Mesa from scratch. Tried commits git-edfc17a (current head of branch 12.0) and commit 17f1c49b9ad05af4f6482f6fa950e5dcc1a779d1 (current head of master branch) In both, I don't have compute shaders. Googling around it appears for Southern Island radeon it could be buggy so it was turned off. Not 100% sure but I think that's what's happening. Anyway, not a big deal on that. WIP. Move on. Like I said our Forward3D demo was glitching and I didn't know why. I've investigated the problem and located it: * glGetIntegerv w/ GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT is returning 4, should return 256 for my HW. * glGetIntegerv w/ GL_TEXTURE_BUFFER_OFFSET_ALIGNMENT is returning 4, should return 256 for my HW. This is clearly not a shader issue which is why I reported it in this ticket: https://bugs.freedesktop.org/show_bug.cgi?id=97305 Thanks for assistance, and I'm sorry for having bothered you earlier. Cheers -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH V2 1/2] i965: Change 8x multisample positions
There are no standard sample positions defined in OpenGL and OpenGL
ES specs. Implementations have the freedom to pick the positions
which give plausible results. But the Vulkan 1.0 spec does define
standard sample positions for different sample counts. Defined
positions in Vulkan for all the sample counts except 8X match with
the positions we set in i965. We have an upcoming plan to share the
blorp code between OpenGL and Vulkan driver in near future. Keeping
the 8X sample positions same on both the drivers will help us move
in that direction.
Here is an argument by Neil Roberts (from commit 20250e85) against
any advantage of current 8X sample positions over the new ones:
"The comment above for the 8x sample positions says that the hardware
implements centroid interpolation by picking the centre-most sample
that is inside the primitive. That implies that it might be worthwhile
to pick a pattern that includes 0.5,0.5. However by experimentation
this doesn't seem to actually be the case. With the sample positions
in this patch, if I modify the piglit test below so that it instead
reports the centroid position, it reports 0.492188,0.421875 which
doesn't match any of the positions. If I modify the sample positions
so that they include one at exactly 0.5,0.5 it doesn't help and it
reports another position which is even further from the center for
some reason.
arb_gpu_shader5-interpolateAtSample-different
Kenneth Graunke experimented with some other patterns that have a
higher standard deviation but I think after some discussion it was
decided that it would be better to pick the same pattern as the other
graphics API in case there are games that rely on this pattern."
Observed no regressions in jenkins testing.
Signed-off-by: Anuj Phogat
Cc: Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_multisample_state.h | 43 +++
1 file changed, 20 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_multisample_state.h
b/src/mesa/drivers/dri/i965/brw_multisample_state.h
index 42a7fd3..db59af2 100644
--- a/src/mesa/drivers/dri/i965/brw_multisample_state.h
+++ b/src/mesa/drivers/dri/i965/brw_multisample_state.h
@@ -24,6 +24,15 @@
#include
/**
+ * Note: There are no standard multisample positions defined in OpenGL
+ * specifications. Implementations have the freedom to pick the positions
+ * which give plausible results. But the Vulkan specification does define
+ * standard sample positions. So, we decided to pick the same pattern in
+ * OpenGL as in Vulkan to keep it uniform across drivers and also to avoid
+ * breaking applications which rely on this standard pattern.
+ */
+
+/**
* 1x MSAA has a single sample at the center: (0.5, 0.5) -> (0x8, 0x8).
*
* 2x MSAA sample positions are (0.25, 0.25) and (0.75, 0.75):
@@ -46,22 +55,10 @@ static const uint32_t
brw_multisample_positions_4x = 0xae2ae662;
/**
- * Sample positions are based on a solution to the "8 queens" puzzle.
- * Rationale: in a solution to the 8 queens puzzle, no two queens share
- * a row, column, or diagonal. This is a desirable property for samples
- * in a multisampling pattern, because it ensures that the samples are
- * relatively uniformly distributed through the pixel.
- *
- * There are several solutions to the 8 queens puzzle (see
- * http://en.wikipedia.org/wiki/Eight_queens_puzzle). This solution was
- * chosen because it has a queen close to the center; this should
- * improve the accuracy of centroid interpolation, since the hardware
- * implements centroid interpolation by choosing the centermost sample
- * that overlaps with the primitive being drawn.
+ * Sample positions:
*
- * Note: from the Ivy Bridge PRM, Vol2 Part1 p304 (3DSTATE_MULTISAMPLE:
+ * From the Ivy Bridge PRM, Vol2 Part1 p304 (3DSTATE_MULTISAMPLE:
* Programming Notes):
- *
* "When programming the sample offsets (for NUMSAMPLES_4 or _8 and
* MSRASTMODE_xxx_PATTERN), the order of the samples 0 to 3 (or 7
* for 8X) must have monotonically increasing distance from the
@@ -70,17 +67,17 @@ brw_multisample_positions_4x = 0xae2ae662;
*
* Sample positions:
* 1 3 5 7 9 b d f
- * 1 5
- * 3 2
- * 5 6
- * 7 4
- * 9 0
- * b 3
- * d 1
- * f 7
+ * 1 7
+ * 3 3
+ * 5 0
+ * 7 5
+ * 9 2
+ * b 1
+ * d 4
+ * f 6
*/
static const uint32_t
-brw_multisample_positions_8x[] = { 0xdbb39d79, 0x3ff55117 };
+brw_multisample_positions_8x[] = { 0x53d97b95, 0xf1bf173d };
/**
* Sample positions:
--
2.5.5
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[Mesa-dev] [PATCH V2 2/2] i965: Change 8X MSAA sample mapping
This is required following the change in 8X sample positions.
Fixes the recently modified multisample-scaled-blit piglit tests.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +-
src/mesa/drivers/dri/i965/gen6_multisample_state.c | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index b903de1..f7f685b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1094,13 +1094,13 @@ blorp_nir_manual_blend_bilinear(nir_builder *b,
nir_ssa_def *pos,
*
* In case of 8x MSAA the two layouts don't match.
* sample index layout : -sample number layout : -
- *| 0 | 1 || 5 | 2 |
+ *| 0 | 1 || 3 | 7 |
*--
- *| 2 | 3 || 4 | 6 |
+ *| 2 | 3 || 5 | 0 |
*--
- *| 4 | 5 || 0 | 3 |
+ *| 4 | 5 || 1 | 2 |
*--
- *| 6 | 7 || 7 | 1 |
+ *| 6 | 7 || 4 | 6 |
*--
*
* Fortunately, this can be done fairly easily as:
@@ -1128,7 +1128,7 @@ blorp_nir_manual_blend_bilinear(nir_builder *b,
nir_ssa_def *pos,
sample = nir_f2i(b, sample);
if (tex_samples == 8) {
- sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x17306425),
+ sample = nir_iand(b, nir_ishr(b, nir_imm_int(b, 0x64210573),
nir_ishl(b, sample, nir_imm_int(b, 2))),
nir_imm_int(b, 0xf));
} else if (tex_samples == 16) {
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index a47e323..a59ffec 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -109,7 +109,7 @@ gen6_set_sample_maps(struct gl_context *ctx)
{
uint8_t map_2x[2] = {0, 1};
uint8_t map_4x[4] = {0, 1, 2, 3};
- uint8_t map_8x[8] = {5, 2, 4, 6, 0, 3, 7, 1};
+ uint8_t map_8x[8] = {3, 7, 5, 0, 1, 2, 4, 6};
uint8_t map_16x[16] = { 15, 10, 9, 7, 4, 1, 3, 13,
12, 2, 0, 6, 11, 8, 5, 14 };
--
2.5.5
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Re: [Mesa-dev] [PATCH 3/5] isl/formats: Update the table with more samplable formats
On Tue, Jul 26, 2016 at 10:04:24PM -0700, Jason Ekstrand wrote:
> There were a lot of formats where support was added on Haswell or later but
> we never updated the format table.
> ---
> src/intel/isl/isl_format.c | 30 +++---
> 1 file changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
> index 366d32e..73688a7 100644
> --- a/src/intel/isl/isl_format.c
> +++ b/src/intel/isl/isl_format.c
> @@ -218,8 +218,8 @@ static const struct surface_format_info format_info[] = {
> SF(50, 50, x, x, x, x, x, x, x,x, P8A8_UNORM_PALETTE1)
> SF( x, x, x, x, x, x, x, x, x,x, A1B5G5R5_UNORM)
> SF(90, 90, x, x, 90, x, x, x, x,x, A4B4G4R4_UNORM)
> - SF( x, x, x, x, x, x, x, x, x,x, L8A8_UINT)
> - SF( x, x, x, x, x, x, x, x, x,x, L8A8_SINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, L8A8_UINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, L8A8_SINT)
How were you able to determine that these formats are filterable? In
this table, it generally seems to be the case that integer formats are
not filterable.
- Nanley
> SF( Y, Y, x, 45, Y, Y, Y, x, x,x, R8_UNORM)
> SF( Y, Y, x, x, Y, 60, Y, x, x,x, R8_SNORM)
> SF( Y, x, x, x, Y, x, Y, x, x,x, R8_SINT)
> @@ -237,10 +237,10 @@ static const struct surface_format_info format_info[] =
> {
> SF(45, 45, x, x, x, x, x, x, x,x, P4A4_UNORM_PALETTE1)
> SF(45, 45, x, x, x, x, x, x, x,x, A4P4_UNORM_PALETTE1)
> SF( x, x, x, x, x, x, x, x, x,x, Y8_UNORM)
> - SF( x, x, x, x, x, x, x, x, x,x, L8_UINT)
> - SF( x, x, x, x, x, x, x, x, x,x, L8_SINT)
> - SF( x, x, x, x, x, x, x, x, x,x, I8_UINT)
> - SF( x, x, x, x, x, x, x, x, x,x, I8_SINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, L8_UINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, L8_SINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, I8_UINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, I8_SINT)
> SF(45, 45, x, x, x, x, x, x, x,x, DXT1_RGB_SRGB)
> SF( Y, Y, x, x, x, x, x, x, x,x, R1_UNORM)
> SF( Y, Y, x, Y, Y, x, x, x, 60,x, YCRCB_NORMAL)
> @@ -261,8 +261,8 @@ static const struct surface_format_info format_info[] = {
> SF( Y, Y, x, x, x, x, x, x, x,x, DXT1_RGB)
> /* smpl filt shad CK RT AB VB SO color ccs_e */
> SF( Y, Y, x, x, x, x, x, x, x,x, FXT1)
> - SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_UNORM)
> - SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_SNORM)
> + SF(75, 75, x, x, x, x, Y, x, x,x, R8G8B8_UNORM)
> + SF(75, 75, x, x, x, x, Y, x, x,x, R8G8B8_SNORM)
> SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_SSCALED)
> SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_USCALED)
> SF( x, x, x, x, x, x, Y, x, x,x, R64G64B64A64_FLOAT)
> @@ -270,8 +270,8 @@ static const struct surface_format_info format_info[] = {
> SF( Y, Y, x, x, x, x, x, x, x,x, BC4_SNORM)
> SF( Y, Y, x, x, x, x, x, x, x,x, BC5_SNORM)
> SF(50, 50, x, x, x, x, 60, x, x,x, R16G16B16_FLOAT)
> - SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_UNORM)
> - SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_SNORM)
> + SF(75, 75, x, x, x, x, Y, x, x,x, R16G16B16_UNORM)
> + SF(75, 75, x, x, x, x, Y, x, x,x, R16G16B16_SNORM)
> SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_SSCALED)
> SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_USCALED)
> SF(70, 70, x, x, x, x, x, x, x,x, BC6H_SF16)
> @@ -279,7 +279,7 @@ static const struct surface_format_info format_info[] = {
> SF(70, 70, x, x, x, x, x, x, x,x, BC7_UNORM_SRGB)
> SF(70, 70, x, x, x, x, x, x, x,x, BC6H_UF16)
> SF( x, x, x, x, x, x, x, x, x,x, PLANAR_420_8)
> - SF( x, x, x, x, x, x, x, x, x,x, R8G8B8_UNORM_SRGB)
> + SF(75, 75, x, x, x, x, x, x, x,x, R8G8B8_UNORM_SRGB)
> SF(80, 80, x, x, x, x, x, x, x,x, ETC1_RGB8)
> SF(80, 80, x, x, x, x, x, x, x,x, ETC2_RGB8)
> SF(80, 80, x, x, x, x, x, x, x,x, EAC_R11)
> @@ -287,8 +287,8 @@ static const struct surface_format_info format_info[] = {
> SF(80, 80, x, x, x, x, x, x, x,x, EAC_SIGNED_R11)
> SF(80, 80, x, x, x, x, x, x, x,x, EAC_SIGNED_RG11)
> SF(80, 80, x, x, x, x, x, x, x,x, ETC2_SRGB8)
> - SF( x, x, x, x, x, x, 75, x, x,x, R16G16B16_UINT)
> - SF( x, x, x, x, x, x, 75, x, x,x, R16G16B16_SINT)
> + SF(90, 90, x, x, x, x, 75, x, x,x, R16G16B16_UINT)
> + SF(90, 90,
Re: [Mesa-dev] [PATCH 2/2] nir/algebraic: Optimize common array indexing sequence
2016-08-11 18:19 GMT+02:00 Ian Romanick :
> ping
>
> On 07/19/2016 10:37 PM, Ian Romanick wrote:
>> From: Ian Romanick
>>
>> Some shaders include code that looks like:
>>
>>uniform int i;
>>uniform vec4 bones[...];
>>
>>foo(bones[i * 3], bones[i * 3 + 1], bones[i * 3 + 2]);
>>
>> CSE would do some work on this:
>>
>>x = i * 3
>>foo(bones[x], bones[x + 1], bones[x + 2]);
>>
>> The compiler may then add '<< 4 + base' to the index calculations.
>> This results in expressions like
>>
>>x = i * 3
>>foo(bones[x << 4], bones[(x + 1) << 4], bones[(x + 2) << 4]);
>>
This may just be me being dense, but why is the compiler adding the shift?
It seems like this would be "un-optimizing" and so it shouldn't be added?
This patch is also a good argument for adding a constant reassociation pass.
At least the (a * #b) << #c--->a * (#b << #c) would be caught by that.
I was confused whether the optimization was preserving signed-ness correctly
but after a couple rounds with myself I believe it is correct.
The change looks good and is:
Reviewed-by: Thomas Helland
(Oh, and yes, I'm back to hobby mesa development after finally
securing a new job and a new apartment)
>> Just rearranging the math to produce (i * 48) + 16 saves an
>> instruction, and it allows CSE to do more work.
>>
>>x = i * 48;
>>foo(bones[x], bones[x + 16], bones[x + 32]);
>>
>> So, ~6 instructions becomes ~3.
>>
>> Some individual shader-db results look pretty bad. However, I have a
>> really, really hard time believing the change in estimated cycles in,
>> for example, 3dmmes-taiji/51.shader_test after looking that change in
>> the generated code.
>>
>> G45
>> total instructions in shared programs: 4020840 -> 4010070 (-0.27%)
>> instructions in affected programs: 177460 -> 166690 (-6.07%)
>> helped: 894
>> HURT: 0
>>
>> total cycles in shared programs: 98829000 -> 98784990 (-0.04%)
>> cycles in affected programs: 3936648 -> 3892638 (-1.12%)
>> helped: 894
>> HURT: 0
>>
>> Ironlake
>> total instructions in shared programs: 6418887 -> 6408117 (-0.17%)
>> instructions in affected programs: 177460 -> 166690 (-6.07%)
>> helped: 894
>> HURT: 0
>>
>> total cycles in shared programs: 143504542 -> 143460532 (-0.03%)
>> cycles in affected programs: 3936648 -> 3892638 (-1.12%)
>> helped: 894
>> HURT: 0
>>
>> Sandy Bridge
>> total instructions in shared programs: 8357887 -> 8339251 (-0.22%)
>> instructions in affected programs: 432715 -> 414079 (-4.31%)
>> helped: 2795
>> HURT: 0
>>
>> total cycles in shared programs: 118284184 -> 118207412 (-0.06%)
>> cycles in affected programs: 6114626 -> 6037854 (-1.26%)
>> helped: 2478
>> HURT: 317
>>
>> Ivy Bridge
>> total instructions in shared programs: 7669390 -> 7653822 (-0.20%)
>> instructions in affected programs: 388234 -> 372666 (-4.01%)
>> helped: 2795
>> HURT: 0
>>
>> total cycles in shared programs: 68381982 -> 68263684 (-0.17%)
>> cycles in affected programs: 1972658 -> 1854360 (-6.00%)
>> helped: 2458
>> HURT: 307
>>
>> Haswell
>> total instructions in shared programs: 7082636 -> 7067068 (-0.22%)
>> instructions in affected programs: 388234 -> 372666 (-4.01%)
>> helped: 2795
>> HURT: 0
>>
>> total cycles in shared programs: 68282020 -> 68164158 (-0.17%)
>> cycles in affected programs: 1891820 -> 1773958 (-6.23%)
>> helped: 2459
>> HURT: 261
>>
>> Broadwell
>> total instructions in shared programs: 9002466 -> 8985875 (-0.18%)
>> instructions in affected programs: 658784 -> 642193 (-2.52%)
>> helped: 2795
>> HURT: 5
>>
>> total cycles in shared programs: 78503092 -> 78450404 (-0.07%)
>> cycles in affected programs: 2873304 -> 2820616 (-1.83%)
>> helped: 2275
>> HURT: 415
>>
>> Skylake
>> total instructions in shared programs: 9156978 -> 9140387 (-0.18%)
>> instructions in affected programs: 682625 -> 666034 (-2.43%)
>> helped: 2795
>> HURT: 5
>>
>> total cycles in shared programs: 75591392 -> 75550574 (-0.05%)
>> cycles in affected programs: 3192120 -> 3151302 (-1.28%)
>> helped: 2271
>> HURT: 425
>>
>> Signed-off-by: Ian Romanick
>> ---
>> src/compiler/nir/nir_opt_algebraic.py | 11 +++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/src/compiler/nir/nir_opt_algebraic.py
>> b/src/compiler/nir/nir_opt_algebraic.py
>> index 0f0896b..37cb700 100644
>> --- a/src/compiler/nir/nir_opt_algebraic.py
>> +++ b/src/compiler/nir/nir_opt_algebraic.py
>> @@ -119,6 +119,17 @@ optimizations = [
>> (('~fadd@64', a, ('fmul', c , ('fadd', b, ('fneg', a,
>> ('flrp', a, b, c), '!options->lower_flrp64'),
>> (('ffma', a, b, c), ('fadd', ('fmul', a, b), c), 'options->lower_ffma'),
>> (('~fadd', ('fmul', a, b), c), ('ffma', a, b, c), 'options->fuse_ffma'),
>> +
>> + # (a * #b + #c) << #d
>> + # ((a * #b) << #d) + (#c << #d)
>> + # (a * (#b << #d)) + (#c << #d)
>> + (('ishl', ('iadd', ('imul', a, '#b'), '#c'), '#d'),
>> +('iadd', ('imul', a, ('ishl', b, d)), ('ishl', c, d))),
>> +
>> + # (a * #b) << #c
>> + # a * (#b << #c)
>> + (('
[Mesa-dev] [Bug 97285] Darkness in Dota 2 after Patch "Make Gallium's BlitFramebuffer follow the GL 4.4 sRGB rules"
https://bugs.freedesktop.org/show_bug.cgi?id=97285 --- Comment #11 from Marek Olšák --- The patch looks good to me. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Change 8x multisample positions
On Thu, Aug 11, 2016 at 10:53 AM, Jason Ekstrand wrote:
>
>
> On Thu, Aug 11, 2016 at 10:41 AM, Anuj Phogat wrote:
>>
>> There are no standard sample positions defined in OpenGL and OpenGL
>> ES specs. Implementations have the freedom to pick the positions
>> which give plausible results. But the Vulkan 1.0 spec does define
>> standard sample positions for different sample counts. Defined
>> positions in Vulkan for all the sample counts except 8X match with
>> the positions we set in i965. We have an upcoming plan to share the
>> blorp code between OpenGL and Vulkan driver in near future. Keeping
>> the 8X sample positions same on both the drivers will help us move
>> in that direction.
>>
>> Here is an argument by Neil Roberts (from commit 20250e85) against
>> any advantage of current 8X sample positions over the new ones:
>>
>> "The comment above for the 8x sample positions says that the hardware
>> implements centroid interpolation by picking the centre-most sample
>> that is inside the primitive. That implies that it might be worthwhile
>> to pick a pattern that includes 0.5,0.5. However by experimentation
>> this doesn't seem to actually be the case. With the sample positions
>> in this patch, if I modify the piglit test below so that it instead
>> reports the centroid position, it reports 0.492188,0.421875 which
>> doesn't match any of the positions. If I modify the sample positions
>> so that they include one at exactly 0.5,0.5 it doesn't help and it
>> reports another position which is even further from the center for
>> some reason.
>>
>> arb_gpu_shader5-interpolateAtSample-different
>>
>> Kenneth Graunke experimented with some other patterns that have a
>> higher standard deviation but I think after some discussion it was
>> decided that it would be better to pick the same pattern as the other
>> graphics API in case there are games that rely on this pattern."
>>
>> Observed no regressions in jenkins testing.
>
>
> Did you try the scaled blit tests? I bet we have to rework 8x scaled blit
> for the new positions.
>
They all passed because I missed changing sample mapping pattern
in blorp and the piglit tests. So, the incorrect test image perfectly matched
the incorrect reference image. I'll send out patches to fix these issues.
> Thanks for working on this! It's going to make the blorp transition way
> easier.
>
>>
>> Signed-off-by: Anuj Phogat
>> Cc: Jason Ekstrand
>> ---
>> src/mesa/drivers/dri/i965/brw_multisample_state.h | 33
>> ---
>> 1 file changed, 11 insertions(+), 22 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_multisample_state.h
>> b/src/mesa/drivers/dri/i965/brw_multisample_state.h
>> index 42a7fd3..78fb03a 100644
>> --- a/src/mesa/drivers/dri/i965/brw_multisample_state.h
>> +++ b/src/mesa/drivers/dri/i965/brw_multisample_state.h
>> @@ -46,20 +46,9 @@ static const uint32_t
>> brw_multisample_positions_4x = 0xae2ae662;
>>
>> /**
>> - * Sample positions are based on a solution to the "8 queens" puzzle.
>> - * Rationale: in a solution to the 8 queens puzzle, no two queens share
>> - * a row, column, or diagonal. This is a desirable property for samples
>> - * in a multisampling pattern, because it ensures that the samples are
>> - * relatively uniformly distributed through the pixel.
>> - *
>> - * There are several solutions to the 8 queens puzzle (see
>> - * http://en.wikipedia.org/wiki/Eight_queens_puzzle). This solution was
>> - * chosen because it has a queen close to the center; this should
>> - * improve the accuracy of centroid interpolation, since the hardware
>> - * implements centroid interpolation by choosing the centermost sample
>> - * that overlaps with the primitive being drawn.
>> + * Sample positions:
>
>
> Might be nice to reference the Vulkan spec here.
I'll add the Vulkan reference here.
>
>>
>> *
>> - * Note: from the Ivy Bridge PRM, Vol2 Part1 p304 (3DSTATE_MULTISAMPLE:
>> + * From the Ivy Bridge PRM, Vol2 Part1 p304 (3DSTATE_MULTISAMPLE:
>> * Programming Notes):
>> *
>> * "When programming the sample offsets (for NUMSAMPLES_4 or _8 and
>> @@ -70,17 +59,17 @@ brw_multisample_positions_4x = 0xae2ae662;
>> *
>> * Sample positions:
>> * 1 3 5 7 9 b d f
>> - * 1 5
>> - * 3 2
>> - * 5 6
>> - * 7 4
>> - * 9 0
>> - * b 3
>> - * d 1
>> - * f 7
>> + * 1 7
>> + * 3 3
>> + * 5 0
>> + * 7 5
>> + * 9 2
>> + * b 1
>> + * d 4
>> + * f 6
>> */
>> static const uint32_t
>> -brw_multisample_positions_8x[] = { 0xdbb39d79, 0x3ff55117 };
>> +brw_multisample_positions_8x[] = { 0x53d97b95, 0xf1bf173d };
>>
>> /**
>> * Sample positions:
>> --
>> 2.5.5
>>
>
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Re: [Mesa-dev] [PATCH 3/5] isl/formats: Update the table with more samplable formats
On Tue, Jul 26, 2016 at 10:04:24PM -0700, Jason Ekstrand wrote:
> There were a lot of formats where support was added on Haswell or later but
> we never updated the format table.
> ---
> src/intel/isl/isl_format.c | 30 +++---
> 1 file changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
> index 366d32e..73688a7 100644
> --- a/src/intel/isl/isl_format.c
> +++ b/src/intel/isl/isl_format.c
> @@ -218,8 +218,8 @@ static const struct surface_format_info format_info[] = {
> SF(50, 50, x, x, x, x, x, x, x,x, P8A8_UNORM_PALETTE1)
> SF( x, x, x, x, x, x, x, x, x,x, A1B5G5R5_UNORM)
> SF(90, 90, x, x, 90, x, x, x, x,x, A4B4G4R4_UNORM)
> - SF( x, x, x, x, x, x, x, x, x,x, L8A8_UINT)
> - SF( x, x, x, x, x, x, x, x, x,x, L8A8_SINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, L8A8_UINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, L8A8_SINT)
> SF( Y, Y, x, 45, Y, Y, Y, x, x,x, R8_UNORM)
> SF( Y, Y, x, x, Y, 60, Y, x, x,x, R8_SNORM)
> SF( Y, x, x, x, Y, x, Y, x, x,x, R8_SINT)
> @@ -237,10 +237,10 @@ static const struct surface_format_info format_info[] =
> {
> SF(45, 45, x, x, x, x, x, x, x,x, P4A4_UNORM_PALETTE1)
> SF(45, 45, x, x, x, x, x, x, x,x, A4P4_UNORM_PALETTE1)
> SF( x, x, x, x, x, x, x, x, x,x, Y8_UNORM)
> - SF( x, x, x, x, x, x, x, x, x,x, L8_UINT)
> - SF( x, x, x, x, x, x, x, x, x,x, L8_SINT)
> - SF( x, x, x, x, x, x, x, x, x,x, I8_UINT)
> - SF( x, x, x, x, x, x, x, x, x,x, I8_SINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, L8_UINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, L8_SINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, I8_UINT)
> + SF(90, 90, x, x, x, x, x, x, x,x, I8_SINT)
> SF(45, 45, x, x, x, x, x, x, x,x, DXT1_RGB_SRGB)
> SF( Y, Y, x, x, x, x, x, x, x,x, R1_UNORM)
> SF( Y, Y, x, Y, Y, x, x, x, 60,x, YCRCB_NORMAL)
> @@ -261,8 +261,8 @@ static const struct surface_format_info format_info[] = {
> SF( Y, Y, x, x, x, x, x, x, x,x, DXT1_RGB)
> /* smpl filt shad CK RT AB VB SO color ccs_e */
> SF( Y, Y, x, x, x, x, x, x, x,x, FXT1)
> - SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_UNORM)
> - SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_SNORM)
> + SF(75, 75, x, x, x, x, Y, x, x,x, R8G8B8_UNORM)
> + SF(75, 75, x, x, x, x, Y, x, x,x, R8G8B8_SNORM)
> SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_SSCALED)
> SF( x, x, x, x, x, x, Y, x, x,x, R8G8B8_USCALED)
> SF( x, x, x, x, x, x, Y, x, x,x, R64G64B64A64_FLOAT)
> @@ -270,8 +270,8 @@ static const struct surface_format_info format_info[] = {
> SF( Y, Y, x, x, x, x, x, x, x,x, BC4_SNORM)
> SF( Y, Y, x, x, x, x, x, x, x,x, BC5_SNORM)
> SF(50, 50, x, x, x, x, 60, x, x,x, R16G16B16_FLOAT)
> - SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_UNORM)
> - SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_SNORM)
> + SF(75, 75, x, x, x, x, Y, x, x,x, R16G16B16_UNORM)
> + SF(75, 75, x, x, x, x, Y, x, x,x, R16G16B16_SNORM)
> SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_SSCALED)
> SF( x, x, x, x, x, x, Y, x, x,x, R16G16B16_USCALED)
> SF(70, 70, x, x, x, x, x, x, x,x, BC6H_SF16)
> @@ -279,7 +279,7 @@ static const struct surface_format_info format_info[] = {
> SF(70, 70, x, x, x, x, x, x, x,x, BC7_UNORM_SRGB)
> SF(70, 70, x, x, x, x, x, x, x,x, BC6H_UF16)
> SF( x, x, x, x, x, x, x, x, x,x, PLANAR_420_8)
> - SF( x, x, x, x, x, x, x, x, x,x, R8G8B8_UNORM_SRGB)
> + SF(75, 75, x, x, x, x, x, x, x,x, R8G8B8_UNORM_SRGB)
I could not find support for this change in Vol7 of the HSW PRM. I did
find such support for BDW however.
- Nanley
> SF(80, 80, x, x, x, x, x, x, x,x, ETC1_RGB8)
> SF(80, 80, x, x, x, x, x, x, x,x, ETC2_RGB8)
> SF(80, 80, x, x, x, x, x, x, x,x, EAC_R11)
> @@ -287,8 +287,8 @@ static const struct surface_format_info format_info[] = {
> SF(80, 80, x, x, x, x, x, x, x,x, EAC_SIGNED_R11)
> SF(80, 80, x, x, x, x, x, x, x,x, EAC_SIGNED_RG11)
> SF(80, 80, x, x, x, x, x, x, x,x, ETC2_SRGB8)
> - SF( x, x, x, x, x, x, 75, x, x,x, R16G16B16_UINT)
> - SF( x, x, x, x, x, x, 75, x, x,x, R16G16B16_SINT)
> + SF(90, 90, x, x, x, x, 75, x, x,x, R16G16B16_UINT)
> + SF(90, 90, x, x, x, x, 75, x, x,x, R16G16B16_SINT
[Mesa-dev] [PATCH 1/2] mesa: Document that _mesa_enum_to_string() returns non-null
It always returns non-null, even if the number is an invalid enum.
Cc: Haixia Shi
Reviewed-by: Ian Romanick
Change-Id: I26e8843c96130be972e66f48a49e362442e1bf97
---
src/mapi/glapi/gen/gl_enums.py | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mapi/glapi/gen/gl_enums.py b/src/mapi/glapi/gen/gl_enums.py
index 62cc1b3..2eb9e16 100644
--- a/src/mapi/glapi/gen/gl_enums.py
+++ b/src/mapi/glapi/gen/gl_enums.py
@@ -83,7 +83,12 @@ static int compar_nr( const int *a, enum_elt *b )
static char token_tmp[20];
-const char *_mesa_enum_to_string( int nr )
+/**
+ * This function always returns a string. If the number is a valid enum, it
+ * returns the enum name. Otherwise, it returns a numeric string.
+ */
+const char *
+_mesa_enum_to_string(int nr)
{
enum_elt *elt;
--
2.9.2
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[Mesa-dev] [PATCH 0/3] mesa: Fix a dEQP test (v2)
Fixes test dEQP-GLES3.functional.negative_api.buffer.framebuffer_texture2d. I tested this patch for regressions on Skylake with: % ./deqp-gles3 --deqp-case= 'dEQP-GLES3.functional.negative_api.*' % ./deqp-gles3 --deqp-case='dEQP-GLES3.functional.fbo.color.texcube.*' This patch series lives at git://git.kiwitree.net/~chadv/mesa branch review/fix-deqp-framebuffertexture-error-v02 Chad Versace (3): mesa: Document that _mesa_enum_to_string() returns non-null mesa: Add _mesa_enum_to_string2() mesa: Fix glFramebufferTexture* error codes src/mapi/glapi/gen/gl_enums.py | 24 src/mesa/main/enums.h | 2 ++ src/mesa/main/fbobject.c | 32 +--- 3 files changed, 43 insertions(+), 15 deletions(-) -- 2.9.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] mesa: Fix glFramebufferTexture* error codes (v2)
If check_textarget() determined that textarget was incorrect, it emitted
GL_INVALID_OPERATION. This is the correct behavior when target and
textarget are mismatched but textarget is a valid textarget enum.
When textarget is not a valid textarget enum, the GL spec requires that
GL_INVALID_ENUM be emitted.
Fixes test dEQP-GLES3.functional.negative_api.buffer.framebuffer_texture2d.
v2:
- Continue emitting GL_INVALID_OPERATION when textarget is
a valid textarget enum mismatched with target. [idr and imirkin]
Cc: Ian Romanick
Cc: Ilia Mirkin
Cc: Haixia Shi
Change-Id: I86c492f228720ec8cf9939e741cfc99a5d9fa1bc
---
I'm now checking that textarget is a valid textarget enum with a switch
at the top of the function, which emits error GL_INVALID_ENUM. The
switch lists every textarget I know of, but I'm not confident that it's
correct.
Should some textargets not be in the switch?
src/mesa/main/fbobject.c | 33 ++---
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 2c01526..76adb29 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -2979,6 +2979,32 @@ check_textarget(struct gl_context *ctx, int dims, GLenum
target,
{
bool err = false;
+ /* Check that textarget is a valid textarget enum. */
+ switch (textarget) {
+ case GL_TEXTURE_1D:
+ case GL_TEXTURE_1D_ARRAY:
+ case GL_TEXTURE_2D:
+ case GL_TEXTURE_2D_ARRAY:
+ case GL_TEXTURE_2D_MULTISAMPLE:
+ case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
+ case GL_TEXTURE_CUBE_MAP:
+ case GL_TEXTURE_CUBE_MAP_ARRAY:
+ case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
+ case GL_TEXTURE_CUBE_MAP_NEGATIVE_X:
+ case GL_TEXTURE_CUBE_MAP_POSITIVE_Y:
+ case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y:
+ case GL_TEXTURE_CUBE_MAP_POSITIVE_Z:
+ case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z:
+ case GL_TEXTURE_RECTANGLE:
+ case GL_TEXTURE_3D:
+ break;
+ default:
+ _mesa_error(ctx, GL_INVALID_ENUM, "%s(invalid textarget %s)",
+ caller, _mesa_enum_to_string(textarget));
+ return false;
+ }
+
+ /* Check that target and textarget match. */
switch (dims) {
case 1:
switch (textarget) {
@@ -3029,13 +3055,6 @@ check_textarget(struct gl_context *ctx, int dims, GLenum
target,
err = true;
}
- if (err) {
- _mesa_error(ctx, GL_INVALID_OPERATION,
- "%s(invalid textarget %s)",
- caller, _mesa_enum_to_string(textarget));
- return false;
- }
-
/* Make sure textarget is consistent with the texture's type */
err = (target == GL_TEXTURE_CUBE_MAP) ?
!_mesa_is_cube_face(textarget): (target != textarget);
--
2.9.2
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Re: [Mesa-dev] [PATCH 1/5] i965/surface_formats: Don't advertise 8 or 16-bit RGB formats
On Tue, Jul 26, 2016 at 10:04:22PM -0700, Jason Ekstrand wrote: > We have implicitly been not advertising these formats since we had them > turned off in the format capabilities table. We are about to update that > table and this prevents a change in behavior. The only change in behavior > created by this patch is that we no longer advertise support for > R16G16B16_FLOAT which means that it's now renderable which seems like a > bonus. Maybe someday we'll want to change things to start supporting I don't understand this sentence. Assuming "renderable" means that we can render to a texture with such a format, why does preventing the user from creating an R16G16B16_FLOAT texture mean that it's now renderable? - Nanley > 16-bit RGB formats natively but, at the moment, there's no need. > --- > src/mesa/drivers/dri/i965/brw_surface_formats.c | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c > b/src/mesa/drivers/dri/i965/brw_surface_formats.c > index 2543f4b..69d3bd4 100644 > --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c > +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c > @@ -311,6 +311,16 @@ brw_init_surface_formats(struct brw_context *brw) >if (texture == 0 && format != MESA_FORMAT_RGBA_FLOAT32) >continue; > > + /* Don't advertisel 8 and 16-bit RGB formats to core mesa. This > ensures > + * that they are renderable from an API perspective since core mesa > will > + * fall back to RGBA or RGBX (we can't render to non-power-of-two > + * formats). For 8-bit, formats, this also keeps us from hitting some > + * nasty corners in intel_miptree_map_blit if you ever try to map one. > + */ > + int format_size = _mesa_get_format_bytes(format); > + if (format_size == 3 || format_size == 6) > + continue; > + >if (isl_format_supports_sampling(devinfo, texture) && >(isl_format_supports_filtering(devinfo, texture) || is_integer)) >ctx->TextureFormatSupported[format] = true; > -- > 2.5.0.400.gff86faf > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/3] mesa: Add _mesa_enum_to_string2()
On Thu, Aug 11, 2016 at 10:42 AM, Chad Versace wrote:
> On 08/11/2016 10:24 AM, Ian Romanick wrote:
>>
>> On 08/11/2016 10:11 AM, Chad Versace wrote:
>>>
>>> The new function is identical to _mesa_enum_to_string(), except that it
>>> returns false if the given number is an invalid enum. Bundling
>>> validation and lookup into a single function allows us to do both with
>>> a single lookup into the enum table.
>>>
>>> Cc: Haixia Shi
>>> Change-Id: I83d9a6e53223d1a971cf8dc22cb34b05b48d7889
>>> ---
>>> src/mapi/glapi/gen/gl_enums.py | 20
>>> src/mesa/main/enums.h | 2 ++
>>> 2 files changed, 18 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/src/mapi/glapi/gen/gl_enums.py
>>> b/src/mapi/glapi/gen/gl_enums.py
>>> index 4fc43ab..af21aaf 100644
>>> --- a/src/mapi/glapi/gen/gl_enums.py
>>> +++ b/src/mapi/glapi/gen/gl_enums.py
>>> @@ -89,6 +89,17 @@ static char token_tmp[20];
>>> */
>>> const char *_mesa_enum_to_string( int nr )
>>> {
>>> + const char *str;
>>> + _mesa_enum_to_string2(nr, &str);
>>> + return str;
>>> +}
>>> +
>>> +/**
>>> + * Identical to _mesa_enum_to_string(), except that this function
>>> returns false
>>> + * when the number is an invalid enum.
>>> + */
>>> +bool _mesa_enum_to_string2(int nr, const char **str)
>>> +{
>>> enum_elt *elt;
>>>
>>
>> Add an
>>
>>assert(str != NULL);
>>
>> and maybe document that in the function header.
>
>
> Done.
>
> The hunk now starts with this:
>
> /**
> * Identical to _mesa_enum_to_string(), except that this function returns
> false
> * when the number is an invalid enum. The out parameter \\a str must be
> non-null.
> */
> bool _mesa_enum_to_string2(int nr, const char **str)
Might as well make this BSD-style as well, with return type on its own line.
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Re: [Mesa-dev] [PATCH 3/3] mesa: Fix glFramebufferTexture* error codes
On 08/11/2016 10:22 AM, Ilia Mirkin wrote:
On Thu, Aug 11, 2016 at 1:11 PM, Chad Versace wrote:
If check_textarget() determined that textarget was incorrect, it emitted
GL_INVALID_OPERATION. This is the correct behavior when textarget is
a valid GLenum but an invalid parameter to the current variant of
glFramebufferTexture*().
However, when textarget is not a GLenum at all, then the GL spec
requires that GL_INVALID_ENUM be emitted.
Fixes test dEQP-GLES3.functional.negative_api.buffer.framebuffer_texture2d.
Cc: Haixia Shi
Change-Id: I86c492f228720ec8cf9939e741cfc99a5d9fa1bc
---
src/mesa/main/fbobject.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 2c01526..3360940 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -3029,20 +3029,30 @@ check_textarget(struct gl_context *ctx, int dims,
GLenum target,
err = true;
}
- if (err) {
- _mesa_error(ctx, GL_INVALID_OPERATION,
- "%s(invalid textarget %s)",
- caller, _mesa_enum_to_string(textarget));
- return false;
+ if (!err) {
+ /* Make sure textarget is consistent with the texture's type */
+ if (target == GL_TEXTURE_CUBE_MAP) {
+ err = !_mesa_is_cube_face(textarget);
+ } else {
+ err = (target != textarget);
+ }
}
- /* Make sure textarget is consistent with the texture's type */
- err = (target == GL_TEXTURE_CUBE_MAP) ?
- !_mesa_is_cube_face(textarget): (target != textarget);
-
if (err) {
- _mesa_error(ctx, GL_INVALID_OPERATION,
- "%s(mismatched texture target)", caller);
+ const char *enum_str;
+
+ if (_mesa_enum_to_string2(textarget, &enum_str)) {
so ... if I feed it, say, GL_CLIP_PLANE0 then it's INVALID_OPERATION
but if I feed it 0x then it's INVALID_ENUM?
Probably should just list out the valid enums here. I wouldn't be
surprised if such a list already existed elsewhere in the file.
I didn't find such a list. I'll resubmit the patch with those enums handled
by a switch at the top of the function.
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Re: [Mesa-dev] [PATCH] i965: Change 8x multisample positions
On Thu, Aug 11, 2016 at 10:41 AM, Anuj Phogat wrote:
> There are no standard sample positions defined in OpenGL and OpenGL
> ES specs. Implementations have the freedom to pick the positions
> which give plausible results. But the Vulkan 1.0 spec does define
> standard sample positions for different sample counts. Defined
> positions in Vulkan for all the sample counts except 8X match with
> the positions we set in i965. We have an upcoming plan to share the
> blorp code between OpenGL and Vulkan driver in near future. Keeping
> the 8X sample positions same on both the drivers will help us move
> in that direction.
>
> Here is an argument by Neil Roberts (from commit 20250e85) against
> any advantage of current 8X sample positions over the new ones:
>
> "The comment above for the 8x sample positions says that the hardware
> implements centroid interpolation by picking the centre-most sample
> that is inside the primitive. That implies that it might be worthwhile
> to pick a pattern that includes 0.5,0.5. However by experimentation
> this doesn't seem to actually be the case. With the sample positions
> in this patch, if I modify the piglit test below so that it instead
> reports the centroid position, it reports 0.492188,0.421875 which
> doesn't match any of the positions. If I modify the sample positions
> so that they include one at exactly 0.5,0.5 it doesn't help and it
> reports another position which is even further from the center for
> some reason.
>
> arb_gpu_shader5-interpolateAtSample-different
>
> Kenneth Graunke experimented with some other patterns that have a
> higher standard deviation but I think after some discussion it was
> decided that it would be better to pick the same pattern as the other
> graphics API in case there are games that rely on this pattern."
>
> Observed no regressions in jenkins testing.
>
Did you try the scaled blit tests? I bet we have to rework 8x scaled blit
for the new positions.
Thanks for working on this! It's going to make the blorp transition way
easier.
> Signed-off-by: Anuj Phogat
> Cc: Jason Ekstrand
> ---
> src/mesa/drivers/dri/i965/brw_multisample_state.h | 33
> ---
> 1 file changed, 11 insertions(+), 22 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_multisample_state.h
> b/src/mesa/drivers/dri/i965/brw_multisample_state.h
> index 42a7fd3..78fb03a 100644
> --- a/src/mesa/drivers/dri/i965/brw_multisample_state.h
> +++ b/src/mesa/drivers/dri/i965/brw_multisample_state.h
> @@ -46,20 +46,9 @@ static const uint32_t
> brw_multisample_positions_4x = 0xae2ae662;
>
> /**
> - * Sample positions are based on a solution to the "8 queens" puzzle.
> - * Rationale: in a solution to the 8 queens puzzle, no two queens share
> - * a row, column, or diagonal. This is a desirable property for samples
> - * in a multisampling pattern, because it ensures that the samples are
> - * relatively uniformly distributed through the pixel.
> - *
> - * There are several solutions to the 8 queens puzzle (see
> - * http://en.wikipedia.org/wiki/Eight_queens_puzzle). This solution was
> - * chosen because it has a queen close to the center; this should
> - * improve the accuracy of centroid interpolation, since the hardware
> - * implements centroid interpolation by choosing the centermost sample
> - * that overlaps with the primitive being drawn.
> + * Sample positions:
>
Might be nice to reference the Vulkan spec here.
> *
> - * Note: from the Ivy Bridge PRM, Vol2 Part1 p304 (3DSTATE_MULTISAMPLE:
> + * From the Ivy Bridge PRM, Vol2 Part1 p304 (3DSTATE_MULTISAMPLE:
> * Programming Notes):
> *
> * "When programming the sample offsets (for NUMSAMPLES_4 or _8 and
> @@ -70,17 +59,17 @@ brw_multisample_positions_4x = 0xae2ae662;
> *
> * Sample positions:
> * 1 3 5 7 9 b d f
> - * 1 5
> - * 3 2
> - * 5 6
> - * 7 4
> - * 9 0
> - * b 3
> - * d 1
> - * f 7
> + * 1 7
> + * 3 3
> + * 5 0
> + * 7 5
> + * 9 2
> + * b 1
> + * d 4
> + * f 6
> */
> static const uint32_t
> -brw_multisample_positions_8x[] = { 0xdbb39d79, 0x3ff55117 };
> +brw_multisample_positions_8x[] = { 0x53d97b95, 0xf1bf173d };
>
> /**
> * Sample positions:
> --
> 2.5.5
>
>
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Re: [Mesa-dev] [PATCH] anv/device: Add limits for InterpolationOffset
On Fri, Jul 29, 2016 at 2:30 PM, Anuj Phogat wrote: > > > On Fri, Jul 29, 2016 at 12:32 PM, Anuj Phogat wrote: >> >> >> >> On Thu, Jul 28, 2016 at 6:31 PM, Jason Ekstrand >> wrote: >>> >>> On Jul 28, 2016 7:37 PM, "Anuj Phogat" wrote: >>> > >>> > Fixes the vulkan cts regression in test >>> > dEQP-VK.api.info.device.properties >>> > >>> > Cc: Mark Janes >>> > Cc: Jason Ekstrand >>> > Signed-off-by: Anuj Phogat >>> > --- >>> > src/intel/vulkan/anv_device.c | 6 +++--- >>> > 1 file changed, 3 insertions(+), 3 deletions(-) >>> > >>> > diff --git a/src/intel/vulkan/anv_device.c >>> > b/src/intel/vulkan/anv_device.c >>> > index c2c5153..9fd9683 100644 >>> > --- a/src/intel/vulkan/anv_device.c >>> > +++ b/src/intel/vulkan/anv_device.c >>> > @@ -524,9 +524,9 @@ void anv_GetPhysicalDeviceProperties( >>> >.maxTexelOffset = 7, >>> >.minTexelGatherOffset = -8, >>> >.maxTexelGatherOffset = 7, >>> > - .minInterpolationOffset = 0, /* FIXME */ >>> > - .maxInterpolationOffset = 0, /* FIXME */ >>> > - .subPixelInterpolationOffsetBits = 0, /* FIXME */ >>> > + .minInterpolationOffset = -0.5, >>> > + .maxInterpolationOffset = 0.5, > > Correction: maxInterpolationOffset = 0.4375 > From Vulkan 1.0 spec: > " > If subPixelInterpolationOffsetBits is 4, this provides increments of (1/24) > = 0.0625, and thus the range of supported interpolation offsets would be > [-0.5, 0.4375]. > " Jason, other than above correction, is there anything else you want me to address in V2 of this patch ? >>> >>> > + .subPixelInterpolationOffsetBits = 4, >>> >>> I looked and neither gen7_pipeline.c nor gen8_pipeline.c set the subpixel >>> precision so we get a default of enum value 0 which is 8 bits. We should >>> probably be explicitly setting it to something. I think 4 is probably fine >>> but we should be seeing it. >> >> I think you're talking about "Vertex Sub Pixel Precision Select" in >> 3DSTATE_SF. Yes, we are setting a default value of zero which is 8 bits in >> both OpenGL and Vulkan. This meets the minimum requirement of 4 bits for >> GL_SUBPIXEL_BITS. Yes, it'll be nicer to make it more obvious what we are >> setting here. >> >> The value we are defining in this patch is subPixelInterpolationOffsetBits >> (GL_FRAGMENT_INTERPOLATION_OFFSET_BITS in OpenGL). I found no option of >> setting it on Intel Hardware. I just replicated what we do in i965 and made >> the CTS test happy again. >> >> Looks unrelated but there is this another thing 'viewportSubPixelBits' >> which is initialized to 13 in Vulkan but 0 (required min. value) in i965. >> Again found no option of setting on Intel hardware.So, a similar case to >> subPixelInterpolationOffsetBits. >>> >>> As a side note, I think we could probably combine 3DSTATE_SF and >>> 3DSTATE_RASTER setup between gen7 and gen8 (and move it to >>> genX_pipeline_until.h). We'd probably have to do some #define trick like we >>> did for 3DSTATE_SBE and 3DSTATE_SBE_SWIZ because the two packets are >>> combined on gen7 and split on gen8. >> >> I'll look in to it. >> >>> >>> >.maxFramebufferWidth = (1 << 14), >>> >.maxFramebufferHeight = (1 << 14), >>> >.maxFramebufferLayers = (1 << 10), >>> > -- >>> > 2.5.5 >>> > >> >> > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: look for frag data bindings with [0] tacked onto the end for arrays
I'll rebase and feed it through Jenkins (I was given a branch of late).
On Thu, Aug 11, 2016 at 1:38 PM, Ian Romanick wrote:
> Or not. :( The patch no longer applies, and I wasn't able to trivially
> make it apply. I suspect one of Timothy's recent patches is to blame.
>
> On 08/11/2016 10:06 AM, Ian Romanick wrote:
>> This seems okay... let me run it through our CI first. I should have
>> results later today. I'm going to step out for a bit.
>>
>> On 08/09/2016 05:43 PM, Ilia Mirkin wrote:
>>> ping? do we want this? should i drop it?
>>>
>>> On Wed, Jul 13, 2016 at 3:37 PM, Ilia Mirkin wrote:
Thanks for confirming, Corentin.
Ian, do you have any opinions on this? Seems like a fairly innocuous
thing to be doing...
On Fri, Jul 8, 2016 at 3:39 PM, Corentin Wallez
wrote:
> Not sure how reviews work in Mesa, but this patch LGTM. I also tested that
> it fixes the relevant tests failures it is supposed to address.
>
> On Wed, Jul 6, 2016 at 7:40 PM, Ilia Mirkin wrote:
>>
>> The GL spec is very unclear on this point. Apparently this is discussed
>> without resolution in the closed Khronos bugtracker at
>> https://cvs.khronos.org/bugzilla/show_bug.cgi?id=7829 . The
>> recommendation is to allow dropping the [0] for looking up the bindings.
>>
>> The approach taken in this patch is to instead tack on [0]'s for each
>> arrayness level of the output's type, and doing the lookup again. That
>> way, for
>>
>> out vec4 foo[2][2][2]
>>
>> we will end up looking for bindings for foo, foo[0], foo[0][0], and
>> foo[0][0][0], in that order of preference.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96765
>> Signed-off-by: Ilia Mirkin
>> ---
>> src/compiler/glsl/linker.cpp | 39
>> ---
>> 1 file changed, 28 insertions(+), 11 deletions(-)
>>
>> diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
>> index d963f54..9d54c2f 100644
>> --- a/src/compiler/glsl/linker.cpp
>> +++ b/src/compiler/glsl/linker.cpp
>> @@ -2566,6 +2566,7 @@ find_available_slots(unsigned used_mask, unsigned
>> needed_count)
>> /**
>> * Assign locations for either VS inputs or FS outputs
>> *
>> + * \param mem_ctx Temporary ralloc context used for linking
>> * \param prog Shader program whose variables need locations
>> assigned
>> * \param constants Driver specific constant values for the program.
>> * \param target_index Selector for the program target to receive
>> location
>> @@ -2577,7 +2578,8 @@ find_available_slots(unsigned used_mask, unsigned
>> needed_count)
>> * error is emitted to the shader link log and false is returned.
>> */
>> bool
>> -assign_attribute_or_color_locations(gl_shader_program *prog,
>> +assign_attribute_or_color_locations(void *mem_ctx,
>> +gl_shader_program *prog,
>> struct gl_constants *constants,
>> unsigned target_index)
>> {
>> @@ -2680,16 +2682,31 @@
>> assign_attribute_or_color_locations(gl_shader_program *prog,
>>} else if (target_index == MESA_SHADER_FRAGMENT) {
>> unsigned binding;
>> unsigned index;
>> + const char *name = var->name;
>> + const glsl_type *type = var->type;
>> +
>> + while (type) {
>> +/* Check if there's a binding for the variable name */
>> +if (prog->FragDataBindings->get(binding, name)) {
>> + assert(binding >= FRAG_RESULT_DATA0);
>> + var->data.location = binding;
>> + var->data.is_unmatched_generic_inout = 0;
>> +
>> + if (prog->FragDataIndexBindings->get(index, name)) {
>> + var->data.index = index;
>> + }
>> + break;
>> +}
>>
>> -if (prog->FragDataBindings->get(binding, var->name)) {
>> - assert(binding >= FRAG_RESULT_DATA0);
>> - var->data.location = binding;
>> -var->data.is_unmatched_generic_inout = 0;
>> +/* If not, but it's an array type, look for name[0] */
>> +if (type->is_array()) {
>> + name = ralloc_asprintf(mem_ctx, "%s[0]", name);
>> + type = type->fields.array;
>> + continue;
>> +}
>>
>> - if (prog->FragDataIndexBindings->get(index, var->name)) {
>> - var->data.index = index;
>> - }
>> -}
>> +break;
>> + }
>>}
>>
>>/* From GL4.5 core spec, section 15.2 (Shader Execution):
>> @@
Re: [Mesa-dev] [PATCH 2/3] mesa: Add _mesa_enum_to_string2()
On 08/11/2016 10:24 AM, Ian Romanick wrote:
On 08/11/2016 10:11 AM, Chad Versace wrote:
The new function is identical to _mesa_enum_to_string(), except that it
returns false if the given number is an invalid enum. Bundling
validation and lookup into a single function allows us to do both with
a single lookup into the enum table.
Cc: Haixia Shi
Change-Id: I83d9a6e53223d1a971cf8dc22cb34b05b48d7889
---
src/mapi/glapi/gen/gl_enums.py | 20
src/mesa/main/enums.h | 2 ++
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/src/mapi/glapi/gen/gl_enums.py b/src/mapi/glapi/gen/gl_enums.py
index 4fc43ab..af21aaf 100644
--- a/src/mapi/glapi/gen/gl_enums.py
+++ b/src/mapi/glapi/gen/gl_enums.py
@@ -89,6 +89,17 @@ static char token_tmp[20];
*/
const char *_mesa_enum_to_string( int nr )
{
+ const char *str;
+ _mesa_enum_to_string2(nr, &str);
+ return str;
+}
+
+/**
+ * Identical to _mesa_enum_to_string(), except that this function returns false
+ * when the number is an invalid enum.
+ */
+bool _mesa_enum_to_string2(int nr, const char **str)
+{
enum_elt *elt;
Add an
assert(str != NULL);
and maybe document that in the function header.
Done.
The hunk now starts with this:
/**
* Identical to _mesa_enum_to_string(), except that this function returns false
* when the number is an invalid enum. The out parameter \\a str must be
non-null.
*/
bool _mesa_enum_to_string2(int nr, const char **str)
{
enum_elt *elt;
assert(str != NULL);
elt = ...
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[Mesa-dev] [PATCH] i965: Change 8x multisample positions
There are no standard sample positions defined in OpenGL and OpenGL
ES specs. Implementations have the freedom to pick the positions
which give plausible results. But the Vulkan 1.0 spec does define
standard sample positions for different sample counts. Defined
positions in Vulkan for all the sample counts except 8X match with
the positions we set in i965. We have an upcoming plan to share the
blorp code between OpenGL and Vulkan driver in near future. Keeping
the 8X sample positions same on both the drivers will help us move
in that direction.
Here is an argument by Neil Roberts (from commit 20250e85) against
any advantage of current 8X sample positions over the new ones:
"The comment above for the 8x sample positions says that the hardware
implements centroid interpolation by picking the centre-most sample
that is inside the primitive. That implies that it might be worthwhile
to pick a pattern that includes 0.5,0.5. However by experimentation
this doesn't seem to actually be the case. With the sample positions
in this patch, if I modify the piglit test below so that it instead
reports the centroid position, it reports 0.492188,0.421875 which
doesn't match any of the positions. If I modify the sample positions
so that they include one at exactly 0.5,0.5 it doesn't help and it
reports another position which is even further from the center for
some reason.
arb_gpu_shader5-interpolateAtSample-different
Kenneth Graunke experimented with some other patterns that have a
higher standard deviation but I think after some discussion it was
decided that it would be better to pick the same pattern as the other
graphics API in case there are games that rely on this pattern."
Observed no regressions in jenkins testing.
Signed-off-by: Anuj Phogat
Cc: Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_multisample_state.h | 33 ---
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_multisample_state.h
b/src/mesa/drivers/dri/i965/brw_multisample_state.h
index 42a7fd3..78fb03a 100644
--- a/src/mesa/drivers/dri/i965/brw_multisample_state.h
+++ b/src/mesa/drivers/dri/i965/brw_multisample_state.h
@@ -46,20 +46,9 @@ static const uint32_t
brw_multisample_positions_4x = 0xae2ae662;
/**
- * Sample positions are based on a solution to the "8 queens" puzzle.
- * Rationale: in a solution to the 8 queens puzzle, no two queens share
- * a row, column, or diagonal. This is a desirable property for samples
- * in a multisampling pattern, because it ensures that the samples are
- * relatively uniformly distributed through the pixel.
- *
- * There are several solutions to the 8 queens puzzle (see
- * http://en.wikipedia.org/wiki/Eight_queens_puzzle). This solution was
- * chosen because it has a queen close to the center; this should
- * improve the accuracy of centroid interpolation, since the hardware
- * implements centroid interpolation by choosing the centermost sample
- * that overlaps with the primitive being drawn.
+ * Sample positions:
*
- * Note: from the Ivy Bridge PRM, Vol2 Part1 p304 (3DSTATE_MULTISAMPLE:
+ * From the Ivy Bridge PRM, Vol2 Part1 p304 (3DSTATE_MULTISAMPLE:
* Programming Notes):
*
* "When programming the sample offsets (for NUMSAMPLES_4 or _8 and
@@ -70,17 +59,17 @@ brw_multisample_positions_4x = 0xae2ae662;
*
* Sample positions:
* 1 3 5 7 9 b d f
- * 1 5
- * 3 2
- * 5 6
- * 7 4
- * 9 0
- * b 3
- * d 1
- * f 7
+ * 1 7
+ * 3 3
+ * 5 0
+ * 7 5
+ * 9 2
+ * b 1
+ * d 4
+ * f 6
*/
static const uint32_t
-brw_multisample_positions_8x[] = { 0xdbb39d79, 0x3ff55117 };
+brw_multisample_positions_8x[] = { 0x53d97b95, 0xf1bf173d };
/**
* Sample positions:
--
2.5.5
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[Mesa-dev] [PATCH] anv: Use macro to avoid code duplication for sample positions
Suggested-by: Jason Ekstrand
Signed-off-by: Anuj Phogat
---
src/intel/vulkan/genX_multisample.h | 95 +++
src/intel/vulkan/genX_pipeline_util.h | 35 ++---
src/intel/vulkan/genX_state.c | 68 +++--
3 files changed, 106 insertions(+), 92 deletions(-)
create mode 100644 src/intel/vulkan/genX_multisample.h
diff --git a/src/intel/vulkan/genX_multisample.h
b/src/intel/vulkan/genX_multisample.h
new file mode 100644
index 000..0deb48f
--- /dev/null
+++ b/src/intel/vulkan/genX_multisample.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#pragma once
+
+#define SAMPLE_POS_1X(prefix) \
+prefix##0XOffset = 0.5; \
+prefix##0YOffset = 0.5;
+
+#define SAMPLE_POS_2X(prefix) \
+prefix##0XOffset = 0.25; \
+prefix##0YOffset = 0.25; \
+prefix##1XOffset = 0.75; \
+prefix##1YOffset = 0.75;
+
+#define SAMPLE_POS_4X(prefix) \
+prefix##0XOffset = 0.375; \
+prefix##0YOffset = 0.125; \
+prefix##1XOffset = 0.875; \
+prefix##1YOffset = 0.375; \
+prefix##2XOffset = 0.125; \
+prefix##2YOffset = 0.625; \
+prefix##3XOffset = 0.625; \
+prefix##3YOffset = 0.875;
+
+#define SAMPLE_POS_8X(prefix) \
+prefix##0XOffset = 0.5625; \
+prefix##0YOffset = 0.3125; \
+prefix##1XOffset = 0.4375; \
+prefix##1YOffset = 0.6875; \
+prefix##2XOffset = 0.8125; \
+prefix##2YOffset = 0.5625; \
+prefix##3XOffset = 0.3125; \
+prefix##3YOffset = 0.1875; \
+prefix##4XOffset = 0.1875; \
+prefix##4YOffset = 0.8125; \
+prefix##5XOffset = 0.0625; \
+prefix##5YOffset = 0.4375; \
+prefix##6XOffset = 0.6875; \
+prefix##6YOffset = 0.9375; \
+prefix##7XOffset = 0.9375; \
+prefix##7YOffset = 0.0625;
+
+#define SAMPLE_POS_16X(prefix) \
+prefix##0XOffset = 0.5625; \
+prefix##0YOffset = 0.5625; \
+prefix##1XOffset = 0.4375; \
+prefix##1YOffset = 0.3125; \
+prefix##2XOffset = 0.3125; \
+prefix##2YOffset = 0.6250; \
+prefix##3XOffset = 0.7500; \
+prefix##3YOffset = 0.4375; \
+prefix##4XOffset = 0.1875; \
+prefix##4YOffset = 0.3750; \
+prefix##5XOffset = 0.6250; \
+prefix##5YOffset = 0.8125; \
+prefix##6XOffset = 0.8125; \
+prefix##6YOffset = 0.6875; \
+prefix##7XOffset = 0.6875; \
+prefix##7YOffset = 0.1875; \
+prefix##8XOffset = 0.3750; \
+prefix##8YOffset = 0.8750; \
+prefix##9XOffset = 0.5000; \
+prefix##9YOffset = 0.0625; \
+prefix##10XOffset = 0.2500; \
+prefix##10YOffset = 0.1250; \
+prefix##11XOffset = 0.1250; \
+prefix##11YOffset = 0.7500; \
+prefix##12XOffset = 0.; \
+prefix##12YOffset = 0.5000; \
+prefix##13XOffset = 0.9375; \
+prefix##13YOffset = 0.2500; \
+prefix##14XOffset = 0.8750; \
+prefix##14YOffset = 0.9375; \
+prefix##15XOffset = 0.0625; \
+prefix##15YOffset = 0.;
diff --git a/src/intel/vulkan/genX_pipeline_util.h
b/src/intel/vulkan/genX_pipeline_util.h
index 64b89cd..cf2adb0 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -22,6 +22,7 @@
*/
#include "vk_format_info.h"
+#include "genX_multisample.h"
static uint32_t
vertex_element_comp_control(enum isl_format format, unsigned comp)
@@ -488,42 +489,16 @@ emit_ms_state(struct anv_pipeline *pipeline,
switch (samples) {
case 1:
- ms.Sample0XOffset = 0.5;
- ms.Sample0YOffset = 0.5;
+ SAMPLE_POS_1X(ms.Sample);
break;
case 2:
- ms.Sample0XOffset = 0.25;
- ms.Sample0YOffset = 0.25;
- ms.Sample1XOffset = 0.75;
- ms.Sample1YOffset = 0.75;
+ SAMPLE_POS_2X(ms.Sample);
break;
case 4:
- ms.Sample0XOffset = 0.375;
- ms.Sample0YOffset = 0.125;
- ms.Sample1XOffset = 0.875;
- ms.Sample1YOffset = 0.375;
- ms.Sa
Re: [Mesa-dev] [PATCH] glsl: look for frag data bindings with [0] tacked onto the end for arrays
Or not. :( The patch no longer applies, and I wasn't able to trivially
make it apply. I suspect one of Timothy's recent patches is to blame.
On 08/11/2016 10:06 AM, Ian Romanick wrote:
> This seems okay... let me run it through our CI first. I should have
> results later today. I'm going to step out for a bit.
>
> On 08/09/2016 05:43 PM, Ilia Mirkin wrote:
>> ping? do we want this? should i drop it?
>>
>> On Wed, Jul 13, 2016 at 3:37 PM, Ilia Mirkin wrote:
>>> Thanks for confirming, Corentin.
>>>
>>> Ian, do you have any opinions on this? Seems like a fairly innocuous
>>> thing to be doing...
>>>
>>> On Fri, Jul 8, 2016 at 3:39 PM, Corentin Wallez wrote:
Not sure how reviews work in Mesa, but this patch LGTM. I also tested that
it fixes the relevant tests failures it is supposed to address.
On Wed, Jul 6, 2016 at 7:40 PM, Ilia Mirkin wrote:
>
> The GL spec is very unclear on this point. Apparently this is discussed
> without resolution in the closed Khronos bugtracker at
> https://cvs.khronos.org/bugzilla/show_bug.cgi?id=7829 . The
> recommendation is to allow dropping the [0] for looking up the bindings.
>
> The approach taken in this patch is to instead tack on [0]'s for each
> arrayness level of the output's type, and doing the lookup again. That
> way, for
>
> out vec4 foo[2][2][2]
>
> we will end up looking for bindings for foo, foo[0], foo[0][0], and
> foo[0][0][0], in that order of preference.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96765
> Signed-off-by: Ilia Mirkin
> ---
> src/compiler/glsl/linker.cpp | 39 ---
> 1 file changed, 28 insertions(+), 11 deletions(-)
>
> diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
> index d963f54..9d54c2f 100644
> --- a/src/compiler/glsl/linker.cpp
> +++ b/src/compiler/glsl/linker.cpp
> @@ -2566,6 +2566,7 @@ find_available_slots(unsigned used_mask, unsigned
> needed_count)
> /**
> * Assign locations for either VS inputs or FS outputs
> *
> + * \param mem_ctx Temporary ralloc context used for linking
> * \param prog Shader program whose variables need locations
> assigned
> * \param constants Driver specific constant values for the program.
> * \param target_index Selector for the program target to receive
> location
> @@ -2577,7 +2578,8 @@ find_available_slots(unsigned used_mask, unsigned
> needed_count)
> * error is emitted to the shader link log and false is returned.
> */
> bool
> -assign_attribute_or_color_locations(gl_shader_program *prog,
> +assign_attribute_or_color_locations(void *mem_ctx,
> +gl_shader_program *prog,
> struct gl_constants *constants,
> unsigned target_index)
> {
> @@ -2680,16 +2682,31 @@
> assign_attribute_or_color_locations(gl_shader_program *prog,
>} else if (target_index == MESA_SHADER_FRAGMENT) {
> unsigned binding;
> unsigned index;
> + const char *name = var->name;
> + const glsl_type *type = var->type;
> +
> + while (type) {
> +/* Check if there's a binding for the variable name */
> +if (prog->FragDataBindings->get(binding, name)) {
> + assert(binding >= FRAG_RESULT_DATA0);
> + var->data.location = binding;
> + var->data.is_unmatched_generic_inout = 0;
> +
> + if (prog->FragDataIndexBindings->get(index, name)) {
> + var->data.index = index;
> + }
> + break;
> +}
>
> -if (prog->FragDataBindings->get(binding, var->name)) {
> - assert(binding >= FRAG_RESULT_DATA0);
> - var->data.location = binding;
> -var->data.is_unmatched_generic_inout = 0;
> +/* If not, but it's an array type, look for name[0] */
> +if (type->is_array()) {
> + name = ralloc_asprintf(mem_ctx, "%s[0]", name);
> + type = type->fields.array;
> + continue;
> +}
>
> - if (prog->FragDataIndexBindings->get(index, var->name)) {
> - var->data.index = index;
> - }
> -}
> +break;
> + }
>}
>
>/* From GL4.5 core spec, section 15.2 (Shader Execution):
> @@ -4816,12 +4833,12 @@ link_shaders(struct gl_context *ctx, struct
> gl_shader_program *prog)
>prev = i;
> }
>
> - if (!assign_attribute_or_color_locations(prog, &ctx->Const,
> + if (!assign_attribute_or_color_loca
Re: [Mesa-dev] [PATCH 1/3] mesa: Document that _mesa_enum_to_string() returns non-null
On 08/11/2016 10:30 AM, Ian Romanick wrote: On 08/11/2016 10:22 AM, Ian Romanick wrote: On 08/11/2016 10:11 AM, Chad Versace wrote: It always returns non-null, even if the number is an invalid enum. Cc: Haixia Shi Change-Id: I26e8843c96130be972e66f48a49e362442e1bf97 --- src/mapi/glapi/gen/gl_enums.py | 4 1 file changed, 4 insertions(+) diff --git a/src/mapi/glapi/gen/gl_enums.py b/src/mapi/glapi/gen/gl_enums.py index 62cc1b3..4fc43ab 100644 --- a/src/mapi/glapi/gen/gl_enums.py +++ b/src/mapi/glapi/gen/gl_enums.py @@ -83,6 +83,10 @@ static int compar_nr( const int *a, enum_elt *b ) static char token_tmp[20]; +/** + * This function always returns a string. If the number is a valid enum, it + * returns the enum name. Otherwise, it returns a numeric string. + */ const char *_mesa_enum_to_string( int nr ) Maybe take this opportunity to fix the formatting of the function. I'll fix it before pushing. const char * _mesa_enum_to_string(int nr) With or without this change, this patch is Reviewed-by: Ian Romanick The R-b for the other two is contingent on being sure patch 3 is actually sufficient. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/3] mesa: Add _mesa_enum_to_string2()
On 08/11/2016 10:11 AM, Chad Versace wrote:
> The new function is identical to _mesa_enum_to_string(), except that it
> returns false if the given number is an invalid enum. Bundling
> validation and lookup into a single function allows us to do both with
> a single lookup into the enum table.
>
> Cc: Haixia Shi
> Change-Id: I83d9a6e53223d1a971cf8dc22cb34b05b48d7889
> ---
> src/mapi/glapi/gen/gl_enums.py | 20
> src/mesa/main/enums.h | 2 ++
> 2 files changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/src/mapi/glapi/gen/gl_enums.py b/src/mapi/glapi/gen/gl_enums.py
> index 4fc43ab..af21aaf 100644
> --- a/src/mapi/glapi/gen/gl_enums.py
> +++ b/src/mapi/glapi/gen/gl_enums.py
> @@ -89,6 +89,17 @@ static char token_tmp[20];
> */
> const char *_mesa_enum_to_string( int nr )
> {
> + const char *str;
> + _mesa_enum_to_string2(nr, &str);
> + return str;
> +}
> +
> +/**
> + * Identical to _mesa_enum_to_string(), except that this function returns
> false
> + * when the number is an invalid enum.
> + */
> +bool _mesa_enum_to_string2(int nr, const char **str)
> +{
> enum_elt *elt;
>
Add an
assert(str != NULL);
and maybe document that in the function header.
> elt = bsearch(& nr, enum_string_table_offsets,
> @@ -97,13 +108,14 @@ const char *_mesa_enum_to_string( int nr )
> (cfunc) compar_nr);
>
> if (elt != NULL) {
> - return &enum_string_table[elt->offset];
> - }
> - else {
> + *str = &enum_string_table[elt->offset];
> + return true;
> + } else {
>/* this is not re-entrant safe, no big deal here */
>_mesa_snprintf(token_tmp, sizeof(token_tmp) - 1, "0x%x", nr);
>token_tmp[sizeof(token_tmp) - 1] = '\\0';
> - return token_tmp;
> + *str = token_tmp;
> + return false;
> }
> }
>
> diff --git a/src/mesa/main/enums.h b/src/mesa/main/enums.h
> index 0e18cd4..ae804d6 100644
> --- a/src/mesa/main/enums.h
> +++ b/src/mesa/main/enums.h
> @@ -36,6 +36,7 @@
> #ifndef _ENUMS_H_
> #define _ENUMS_H_
>
> +#include
>
> #ifdef __cplusplus
> extern "C" {
> @@ -43,6 +44,7 @@ extern "C" {
>
>
> extern const char *_mesa_enum_to_string( int nr );
> +bool _mesa_enum_to_string2(int nr, const char **str);
>
> /* Get the name of an enum given that it is a primitive type. Avoids
> * GL_FALSE/GL_POINTS ambiguity and others.
>
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Re: [Mesa-dev] [PATCH 3/3] mesa: Fix glFramebufferTexture* error codes
On Thu, Aug 11, 2016 at 1:11 PM, Chad Versace wrote:
> If check_textarget() determined that textarget was incorrect, it emitted
> GL_INVALID_OPERATION. This is the correct behavior when textarget is
> a valid GLenum but an invalid parameter to the current variant of
> glFramebufferTexture*().
>
> However, when textarget is not a GLenum at all, then the GL spec
> requires that GL_INVALID_ENUM be emitted.
>
> Fixes test dEQP-GLES3.functional.negative_api.buffer.framebuffer_texture2d.
>
> Cc: Haixia Shi
> Change-Id: I86c492f228720ec8cf9939e741cfc99a5d9fa1bc
> ---
> src/mesa/main/fbobject.c | 32 +---
> 1 file changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
> index 2c01526..3360940 100644
> --- a/src/mesa/main/fbobject.c
> +++ b/src/mesa/main/fbobject.c
> @@ -3029,20 +3029,30 @@ check_textarget(struct gl_context *ctx, int dims,
> GLenum target,
>err = true;
> }
>
> - if (err) {
> - _mesa_error(ctx, GL_INVALID_OPERATION,
> - "%s(invalid textarget %s)",
> - caller, _mesa_enum_to_string(textarget));
> - return false;
> + if (!err) {
> + /* Make sure textarget is consistent with the texture's type */
> + if (target == GL_TEXTURE_CUBE_MAP) {
> + err = !_mesa_is_cube_face(textarget);
> + } else {
> + err = (target != textarget);
> + }
> }
>
> - /* Make sure textarget is consistent with the texture's type */
> - err = (target == GL_TEXTURE_CUBE_MAP) ?
> - !_mesa_is_cube_face(textarget): (target != textarget);
> -
> if (err) {
> - _mesa_error(ctx, GL_INVALID_OPERATION,
> - "%s(mismatched texture target)", caller);
> + const char *enum_str;
> +
> + if (_mesa_enum_to_string2(textarget, &enum_str)) {
so ... if I feed it, say, GL_CLIP_PLANE0 then it's INVALID_OPERATION
but if I feed it 0x then it's INVALID_ENUM?
Probably should just list out the valid enums here. I wouldn't be
surprised if such a list already existed elsewhere in the file.
> + /* The textarget is a valid GLenum, but is an invalid parameter to
> + * this variant of glFramebufferTexture*().
> + */
> + _mesa_error(ctx, GL_INVALID_OPERATION,
> + "%s(mismatched texture target %s)", caller, enum_str);
> + } else {
> + /* The textarget is not a GLenum value. */
> + _mesa_error(ctx, GL_INVALID_ENUM,
> + "%s(invalid textarget %s)", caller, enum_str);
> + }
> +
>return false;
> }
>
> --
> 2.9.2
>
> ___
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Re: [Mesa-dev] [PATCH 1/3] mesa: Document that _mesa_enum_to_string() returns non-null
On 08/11/2016 10:22 AM, Ian Romanick wrote:
> On 08/11/2016 10:11 AM, Chad Versace wrote:
>> It always returns non-null, even if the number is an invalid enum.
>>
>> Cc: Haixia Shi
>> Change-Id: I26e8843c96130be972e66f48a49e362442e1bf97
>> ---
>> src/mapi/glapi/gen/gl_enums.py | 4
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/src/mapi/glapi/gen/gl_enums.py b/src/mapi/glapi/gen/gl_enums.py
>> index 62cc1b3..4fc43ab 100644
>> --- a/src/mapi/glapi/gen/gl_enums.py
>> +++ b/src/mapi/glapi/gen/gl_enums.py
>> @@ -83,6 +83,10 @@ static int compar_nr( const int *a, enum_elt *b )
>>
>> static char token_tmp[20];
>>
>> +/**
>> + * This function always returns a string. If the number is a valid enum, it
>> + * returns the enum name. Otherwise, it returns a numeric string.
>> + */
>> const char *_mesa_enum_to_string( int nr )
>
> Maybe take this opportunity to fix the formatting of the function.
>
> const char *
> _mesa_enum_to_string(int nr)
With or without this change, this patch is
Reviewed-by: Ian Romanick
The R-b for the other two is contingent on being sure patch 3 is
actually sufficient.
>> {
>> enum_elt *elt;
>>
>
> ___
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Re: [Mesa-dev] [PATCH 3/3] mesa: Fix glFramebufferTexture* error codes
On 08/11/2016 10:11 AM, Chad Versace wrote:
> If check_textarget() determined that textarget was incorrect, it emitted
> GL_INVALID_OPERATION. This is the correct behavior when textarget is
> a valid GLenum but an invalid parameter to the current variant of
> glFramebufferTexture*().
>
> However, when textarget is not a GLenum at all, then the GL spec
> requires that GL_INVALID_ENUM be emitted.
>
> Fixes test dEQP-GLES3.functional.negative_api.buffer.framebuffer_texture2d.
>
> Cc: Haixia Shi
> Change-Id: I86c492f228720ec8cf9939e741cfc99a5d9fa1bc
> ---
> src/mesa/main/fbobject.c | 32 +---
> 1 file changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
> index 2c01526..3360940 100644
> --- a/src/mesa/main/fbobject.c
> +++ b/src/mesa/main/fbobject.c
> @@ -3029,20 +3029,30 @@ check_textarget(struct gl_context *ctx, int dims,
> GLenum target,
>err = true;
> }
>
> - if (err) {
> - _mesa_error(ctx, GL_INVALID_OPERATION,
> - "%s(invalid textarget %s)",
> - caller, _mesa_enum_to_string(textarget));
> - return false;
> + if (!err) {
> + /* Make sure textarget is consistent with the texture's type */
> + if (target == GL_TEXTURE_CUBE_MAP) {
> + err = !_mesa_is_cube_face(textarget);
> + } else {
> + err = (target != textarget);
> + }
> }
>
> - /* Make sure textarget is consistent with the texture's type */
> - err = (target == GL_TEXTURE_CUBE_MAP) ?
> - !_mesa_is_cube_face(textarget): (target != textarget);
> -
> if (err) {
> - _mesa_error(ctx, GL_INVALID_OPERATION,
> - "%s(mismatched texture target)", caller);
> + const char *enum_str;
> +
> + if (_mesa_enum_to_string2(textarget, &enum_str)) {
I'm not sure this is sufficient. What if I pass GL_RED? I'm reasonably
certain that should generate GL_INVALID_ENUM, but it will generate
GL_INVALID_OPERATION.
> + /* The textarget is a valid GLenum, but is an invalid parameter to
> + * this variant of glFramebufferTexture*().
> + */
> + _mesa_error(ctx, GL_INVALID_OPERATION,
> + "%s(mismatched texture target %s)", caller, enum_str);
> + } else {
> + /* The textarget is not a GLenum value. */
> + _mesa_error(ctx, GL_INVALID_ENUM,
> + "%s(invalid textarget %s)", caller, enum_str);
> + }
> +
>return false;
> }
>
>
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[Mesa-dev] [PATCH 2/2] anv: GetDeviceImageFormatProperties: fix TRANSFER formats
We let the user believe we support some transfer formats which we don't.
This can lead to crashes when actually trying to use those formats for
example on dEQP-VK.api.copy_and_blit.image_to_image.* tests.
Let all formats we can render to or sample from as meta implements transfers
using attachments.
Signed-off-by: Lionel Landwerlin
Cc: Jason Ekstrand
---
src/intel/vulkan/anv_formats.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index b26e48a..13bde90 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -509,23 +509,21 @@ VkResult anv_GetPhysicalDeviceImageFormatProperties(
if (usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
/* Meta implements transfers by sampling from the source image. */
- if (!(format_feature_flags & VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT)) {
+ if (!(format_feature_flags & (VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT |
+
VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT |
+VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT))) {
goto unsupported;
}
}
-#if 0
if (usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT) {
- if (anv_format_for_vk_format(format)->has_stencil) {
- /* Not yet implemented because copying to a W-tiled surface is crazy
- * hard.
- */
- anv_finishme("support VK_IMAGE_USAGE_TRANSFER_DST_BIT for "
- "stencil format");
+ /* Meta implements transfers by rendering to the attachment image. */
+ if (!(format_feature_flags & (VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT |
+
VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT |
+VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT))) {
goto unsupported;
}
}
-#endif
if (usage & VK_IMAGE_USAGE_SAMPLED_BIT) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT)) {
--
2.8.1
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[Mesa-dev] [PATCH 1/2] anv: pipeline: gen7: fix assert in debug mode
SampleMask is only 8bits long on gen7.
Signed-off-by: Lionel Landwerlin
Cc: Jason Ekstrand
---
src/intel/vulkan/genX_pipeline_util.h | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline_util.h
b/src/intel/vulkan/genX_pipeline_util.h
index 64b89cd..d56eeb8 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -462,7 +462,11 @@ emit_ms_state(struct anv_pipeline *pipeline,
*
* 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
*/
+#if GEN_GEN >= 8
uint32_t sample_mask = 0x;
+#else
+ uint32_t sample_mask = 0xff;
+#endif
if (info) {
samples = info->rasterizationSamples;
--
2.8.1
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Re: [Mesa-dev] [PATCH 1/3] mesa: Document that _mesa_enum_to_string() returns non-null
On 08/11/2016 10:11 AM, Chad Versace wrote:
> It always returns non-null, even if the number is an invalid enum.
>
> Cc: Haixia Shi
> Change-Id: I26e8843c96130be972e66f48a49e362442e1bf97
> ---
> src/mapi/glapi/gen/gl_enums.py | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/src/mapi/glapi/gen/gl_enums.py b/src/mapi/glapi/gen/gl_enums.py
> index 62cc1b3..4fc43ab 100644
> --- a/src/mapi/glapi/gen/gl_enums.py
> +++ b/src/mapi/glapi/gen/gl_enums.py
> @@ -83,6 +83,10 @@ static int compar_nr( const int *a, enum_elt *b )
>
> static char token_tmp[20];
>
> +/**
> + * This function always returns a string. If the number is a valid enum, it
> + * returns the enum name. Otherwise, it returns a numeric string.
> + */
> const char *_mesa_enum_to_string( int nr )
Maybe take this opportunity to fix the formatting of the function.
const char *
_mesa_enum_to_string(int nr)
> {
> enum_elt *elt;
>
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[Mesa-dev] [PATCH 3/3] mesa: Fix glFramebufferTexture* error codes
If check_textarget() determined that textarget was incorrect, it emitted
GL_INVALID_OPERATION. This is the correct behavior when textarget is
a valid GLenum but an invalid parameter to the current variant of
glFramebufferTexture*().
However, when textarget is not a GLenum at all, then the GL spec
requires that GL_INVALID_ENUM be emitted.
Fixes test dEQP-GLES3.functional.negative_api.buffer.framebuffer_texture2d.
Cc: Haixia Shi
Change-Id: I86c492f228720ec8cf9939e741cfc99a5d9fa1bc
---
src/mesa/main/fbobject.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 2c01526..3360940 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -3029,20 +3029,30 @@ check_textarget(struct gl_context *ctx, int dims,
GLenum target,
err = true;
}
- if (err) {
- _mesa_error(ctx, GL_INVALID_OPERATION,
- "%s(invalid textarget %s)",
- caller, _mesa_enum_to_string(textarget));
- return false;
+ if (!err) {
+ /* Make sure textarget is consistent with the texture's type */
+ if (target == GL_TEXTURE_CUBE_MAP) {
+ err = !_mesa_is_cube_face(textarget);
+ } else {
+ err = (target != textarget);
+ }
}
- /* Make sure textarget is consistent with the texture's type */
- err = (target == GL_TEXTURE_CUBE_MAP) ?
- !_mesa_is_cube_face(textarget): (target != textarget);
-
if (err) {
- _mesa_error(ctx, GL_INVALID_OPERATION,
- "%s(mismatched texture target)", caller);
+ const char *enum_str;
+
+ if (_mesa_enum_to_string2(textarget, &enum_str)) {
+ /* The textarget is a valid GLenum, but is an invalid parameter to
+ * this variant of glFramebufferTexture*().
+ */
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "%s(mismatched texture target %s)", caller, enum_str);
+ } else {
+ /* The textarget is not a GLenum value. */
+ _mesa_error(ctx, GL_INVALID_ENUM,
+ "%s(invalid textarget %s)", caller, enum_str);
+ }
+
return false;
}
--
2.9.2
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