Re: [Mesa-dev] [PATCH] radv/formats: add fast clear for 8-bit signed ints.

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Mon, Feb 27, 2017 at 3:15 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> These formats are used by some CTS tests, may as well fill them in.
>
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_formats.c | 16 
>  1 file changed, 16 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
> index 30a20db..7483b8d 100644
> --- a/src/amd/vulkan/radv_formats.c
> +++ b/src/amd/vulkan/radv_formats.c
> @@ -864,6 +864,10 @@ bool radv_format_pack_clear_color(VkFormat format,
> clear_vals[0] = value->uint32[0] & 0xff;
> clear_vals[1] = 0;
> break;
> +   case VK_FORMAT_R8_SINT:
> +   clear_vals[0] = value->int32[0] & 0xff;
> +   clear_vals[1] = 0;
> +   break;
> case VK_FORMAT_R16_UINT:
> clear_vals[0] = value->uint32[0] & 0x;
> clear_vals[1] = 0;
> @@ -873,6 +877,11 @@ bool radv_format_pack_clear_color(VkFormat format,
> clear_vals[0] |= (value->uint32[1] & 0xff) << 8;
> clear_vals[1] = 0;
> break;
> +   case VK_FORMAT_R8G8_SINT:
> +   clear_vals[0] = value->int32[0] & 0xff;
> +   clear_vals[0] |= (value->int32[1] & 0xff) << 8;
> +   clear_vals[1] = 0;
> +   break;
> case VK_FORMAT_R8G8B8A8_UINT:
> clear_vals[0] = value->uint32[0] & 0xff;
> clear_vals[0] |= (value->uint32[1] & 0xff) << 8;
> @@ -880,6 +889,13 @@ bool radv_format_pack_clear_color(VkFormat format,
> clear_vals[0] |= (value->uint32[3] & 0xff) << 24;
> clear_vals[1] = 0;
> break;
> +   case VK_FORMAT_R8G8B8A8_SINT:
> +   clear_vals[0] = value->int32[0] & 0xff;
> +   clear_vals[0] |= (value->int32[1] & 0xff) << 8;
> +   clear_vals[0] |= (value->int32[2] & 0xff) << 16;
> +   clear_vals[0] |= (value->int32[3] & 0xff) << 24;
> +   clear_vals[1] = 0;
> +   break;
> case VK_FORMAT_A8B8G8R8_UINT_PACK32:
> clear_vals[0] = value->uint32[0] & 0xff;
> clear_vals[0] |= (value->uint32[1] & 0xff) << 8;
> --
> 2.9.3
>
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Re: [Mesa-dev] [PATCH] radv: fix depth format in blit2d.

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Mon, Feb 27, 2017 at 8:00 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> For blitting we need to use the depth or stencil format, never
> the combined.
>
> This fixes:
> dEQP-VK.texture.shadow.2d.nearest.less_or_equal_d32_sfloat_s8_uint
> and a few others.
>
> Cc: "13.0 17.0" 
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_meta_blit2d.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta_blit2d.c 
> b/src/amd/vulkan/radv_meta_blit2d.c
> index 6b622e7..225b4b2 100644
> --- a/src/amd/vulkan/radv_meta_blit2d.c
> +++ b/src/amd/vulkan/radv_meta_blit2d.c
> @@ -26,6 +26,7 @@
>
>  #include "radv_meta.h"
>  #include "nir/nir_builder.h"
> +#include "vk_format.h"
>
>  enum blit2d_dst_type {
> /* We can bind this destination as a "normal" render target and render
> @@ -283,8 +284,10 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer 
> *cmd_buffer,
>
> for (unsigned r = 0; r < num_rects; ++r) {
> VkFormat depth_format = 0;
> -   if (dst->aspect_mask != VK_IMAGE_ASPECT_COLOR_BIT)
> -   depth_format = dst->image->vk_format;
> +   if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
> +   depth_format = 
> vk_format_stencil_only(dst->image->vk_format);
> +   else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
> +   depth_format = 
> vk_format_depth_only(dst->image->vk_format);
> struct blit2d_src_temps src_temps;
> blit2d_bind_src(cmd_buffer, src_img, src_buf, _temps, 
> src_type, depth_format);
>
> --
> 2.9.3
>
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[Mesa-dev] [v2 17/27] i965/gen6/hiz: Add direct buffer size resolver

[Topi Pohjolainen]

The apparent hack adding unconditionally two lines into cube
maps is taken directly from align_cube().

v2: Apply the cube map hack also for non-mipmapped. But apply
it only for cube-map, not for cube-map-array to keep things
as they were (use mt->target == GL_TEXTURE_CUBE_MAP instead
of _mesa_is_cube_map_texture(mt->target)).

Reviewed-by: Jason Ekstrand  (v1)
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 37 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 +++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  5 
 3 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 3db2857..1cca9a5 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -380,6 +380,43 @@ brw_hiz_all_slices_at_each_lod_offset(
return level_y * pitch + level_x / halign * 4096;
 }
 
+uint32_t
+gen6_get_hiz_total_height(const struct isl_extent4d *phys_level0_sa,
+  enum isl_surf_dim dim, isl_surf_usage_flags_t usage,
+  unsigned last_level)
+{
+   /* The 965's sampler lays cachelines out according to how accesses
+* in the texture surfaces run, so they may be "vertical" through
+* memory.  As a result, the docs say in Surface Padding Requirements:
+* Sampling Engine Surfaces that two extra rows of padding are required.
+*/
+   const unsigned extra_padding = usage & ISL_SURF_USAGE_CUBE_BIT ? 2 : 0;
+   const unsigned valign = 32;
+   const unsigned second_level_y = all_slices_at_each_lod_y_offset(
+  phys_level0_sa, dim, valign, 1);
+
+   /* Second level would be just below first, and its start position is equal
+* to the aligned size needed for the the first.
+*/
+   if (last_level == 0)
+  return second_level_y + extra_padding;
+
+   const unsigned last_level_y = all_slices_at_each_lod_y_offset(
+phys_level0_sa, dim, valign, last_level);
+   const unsigned second_level_h =
+  phys_level0_sa->array_len *
+  ALIGN(minify(phys_level0_sa->height, 1), valign);
+   const unsigned last_level_h =
+  phys_level0_sa->array_len *
+  ALIGN(minify(phys_level0_sa->height, last_level), valign);
+
+   /* Choose the taller of the two: end of the second or end of the last. */
+   const unsigned total_h = MAX2(second_level_y + second_level_h,
+ last_level_y + last_level_h);
+
+   return ALIGN(total_h, valign) + extra_padding;
+}
+
 static void
 brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
 {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b339f99..c20a3d4 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1900,9 +1900,28 @@ intel_hiz_miptree_buf_create(struct brw_context *brw,
   return NULL;
}
 
+   const uint32_t format = translate_tex_format(brw, mt->format, false);
+   const unsigned cpp = isl_format_get_layout(format)->bpb / 8;
+   const unsigned halign = 128 / cpp;
+   const enum isl_surf_dim dim = get_isl_surf_dim(mt->target);
+   const struct isl_extent4d phys_level0_sa = {
+ { mt->physical_width0 }, 
+ { mt->physical_height0 },  
+ { dim == ISL_SURF_DIM_3D ? mt->physical_depth0 : 1 },
+ { dim == ISL_SURF_DIM_3D ? 1 : mt->physical_depth0 } };
+   const isl_surf_usage_flags_t usage =
+  mt->target == GL_TEXTURE_CUBE_MAP ? ISL_SURF_USAGE_CUBE_BIT : 0;
+   const unsigned total_h = gen6_get_hiz_total_height(
+  _level0_sa, dim, usage, mt->last_level);
+   const unsigned total_w = brw_get_mipmap_total_width(
+  phys_level0_sa.width, mt->last_level + 1, halign);
+
buf->aux_base.bo = buf->mt->bo;
-   buf->aux_base.size = buf->mt->total_height * buf->mt->pitch;
-   buf->aux_base.pitch = buf->mt->pitch;
+   buf->aux_base.pitch = total_w * cpp;
+   buf->aux_base.size = total_h * buf->aux_base.pitch;
+
+   assert(buf->aux_base.pitch == buf->mt->pitch);
+   assert(buf->aux_base.size == buf->mt->total_height * buf->mt->pitch);
 
/* On gen6 hiz is unconditionally laid out packing all slices
 * at each level-of-detail (LOD). This means there is no valid qpitch
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index ae146d8..2a3438a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -996,6 +996,11 @@ brw_hiz_all_slices_at_each_lod_offset(
enum isl_surf_dim dim, unsigned num_levels,
enum isl_format format, unsigned level);
 
+uint32_t
+gen6_get_hiz_total_height(const struct isl_extent4d *phys_level0_sa, 
+  enum isl_surf_dim 

[Mesa-dev] [PATCH] radv: fix depth format in blit2d.

[Dave Airlie]

From: Dave Airlie 

For blitting we need to use the depth or stencil format, never
the combined.

This fixes:
dEQP-VK.texture.shadow.2d.nearest.less_or_equal_d32_sfloat_s8_uint
and a few others.

Cc: "13.0 17.0" 
Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_meta_blit2d.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_blit2d.c 
b/src/amd/vulkan/radv_meta_blit2d.c
index 6b622e7..225b4b2 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -26,6 +26,7 @@
 
 #include "radv_meta.h"
 #include "nir/nir_builder.h"
+#include "vk_format.h"
 
 enum blit2d_dst_type {
/* We can bind this destination as a "normal" render target and render
@@ -283,8 +284,10 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer 
*cmd_buffer,
 
for (unsigned r = 0; r < num_rects; ++r) {
VkFormat depth_format = 0;
-   if (dst->aspect_mask != VK_IMAGE_ASPECT_COLOR_BIT)
-   depth_format = dst->image->vk_format;
+   if (dst->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT)
+   depth_format = 
vk_format_stencil_only(dst->image->vk_format);
+   else if (dst->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT)
+   depth_format = 
vk_format_depth_only(dst->image->vk_format);
struct blit2d_src_temps src_temps;
blit2d_bind_src(cmd_buffer, src_img, src_buf, _temps, 
src_type, depth_format);
 
-- 
2.9.3

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Re: [Mesa-dev] [PATCH mesa] egl/dri3: implement query surface hook

[Tapani Pälli]

On 02/24/2017 05:55 PM, Brendan King wrote:

Hi,

On 20/02/17 07:57, Tapani Pälli wrote:

Hi;

On 02/17/2017 05:12 PM, Eric Engestrom wrote:

From: Brendan King 

This is a DRI3 version of a change made for DRI2
(4d6d4f939e0af4252e0b, "egl/dri2: implement query surface hook"),
that fixed failures in dEQP-EGL.functional.resize.surface_size.grow
and dEQP-EGL.functional.resize.surface_size.shrink.


Do these tests fail on some platform? When debugging the original
failures this failed for me only when using DRI2. It's nice to be
consistent but is it possible that this is not necessary because of
differences between DRI2 and DRI3?


The tests failed on the PowerVR driver. The tests resize the drawable
before calling eglSwapBuffers, and query the drawable width and height
after the call. The driver hasn't started drawing the next frame at this
point, and so hasn't requested the new buffers for the drawable yet,
hence the old width and height were being returned.


OK thanks for clarifying, these changes look good to me;

Reviewed-by: Tapani Pälli 





Cc: Tapani Pälli 
Cc: Mark Janes 
Cc: Chad Versace 
Signed-off-by: Brendan King 
---
 src/egl/drivers/dri2/platform_x11_dri3.c | 20 
 src/loader/loader_dri3_helper.c  | 23 +++
 src/loader/loader_dri3_helper.h  |  2 ++
 3 files changed, 45 insertions(+)

diff --git a/src/egl/drivers/dri2/platform_x11_dri3.c
b/src/egl/drivers/dri2/platform_x11_dri3.c
index c4747144d1..c4a54431cc 100644
--- a/src/egl/drivers/dri2/platform_x11_dri3.c
+++ b/src/egl/drivers/dri2/platform_x11_dri3.c
@@ -419,6 +419,25 @@ dri3_query_buffer_age(_EGLDriver *drv,
_EGLDisplay *dpy, _EGLSurface *surf)
return loader_dri3_query_buffer_age(_surf->loader_drawable);
 }

+static EGLBoolean
+dri3_query_surface(_EGLDriver *drv, _EGLDisplay *dpy,
+   _EGLSurface *surf, EGLint attribute,
+   EGLint *value)
+{
+   struct dri3_egl_surface *dri3_surf = dri3_egl_surface(surf);
+
+   switch (attribute) {
+   case EGL_WIDTH:
+   case EGL_HEIGHT:
+ loader_dri3_update_drawable_geometry(_surf->loader_drawable);
+  break;
+   default:
+  break;
+   }
+
+   return _eglQuerySurface(drv, dpy, surf, attribute, value);
+}
+
 static __DRIdrawable *
 dri3_get_dri_drawable(_EGLSurface *surf)
 {
@@ -441,6 +460,7 @@ struct dri2_egl_display_vtbl
dri3_x11_display_vtbl = {
.post_sub_buffer = dri2_fallback_post_sub_buffer,
.copy_buffers = dri3_copy_buffers,
.query_buffer_age = dri3_query_buffer_age,
+   .query_surface = dri3_query_surface,
.create_wayland_buffer_from_image =
dri2_fallback_create_wayland_buffer_from_image,
.get_sync_values = dri3_get_sync_values,
.get_dri_drawable = dri3_get_dri_drawable,
diff --git a/src/loader/loader_dri3_helper.c
b/src/loader/loader_dri3_helper.c
index 6e5d1b8843..493a7f5218 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -1408,3 +1408,26 @@ loader_dri3_get_buffers(__DRIdrawable
*driDrawable,

return true;
 }
+
+/** loader_dri3_update_drawable_geometry
+ *
+ * Get the current drawable geometry.
+ */
+void
+loader_dri3_update_drawable_geometry(struct loader_dri3_drawable *draw)
+{
+   xcb_get_geometry_cookie_t geom_cookie;
+   xcb_get_geometry_reply_t *geom_reply;
+
+   geom_cookie = xcb_get_geometry(draw->conn, draw->drawable);
+
+   geom_reply = xcb_get_geometry_reply(draw->conn, geom_cookie, NULL);
+
+   if (geom_reply) {
+  draw->width = geom_reply->width;
+  draw->height = geom_reply->height;
+  draw->vtable->set_drawable_size(draw, draw->width, draw->height);
+
+  free(geom_reply);
+   }
+}
diff --git a/src/loader/loader_dri3_helper.h
b/src/loader/loader_dri3_helper.h
index 1d1f15ebb9..a865e46355 100644
--- a/src/loader/loader_dri3_helper.h
+++ b/src/loader/loader_dri3_helper.h
@@ -239,4 +239,6 @@ loader_dri3_get_buffers(__DRIdrawable *driDrawable,
 uint32_t buffer_mask,
 struct __DRIimageList *buffers);

+void
+loader_dri3_update_drawable_geometry(struct loader_dri3_drawable
*draw);
 #endif




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[Mesa-dev] [Bug 99978] rotation causes undefined behavior after updating mesa (radeon, x11, kernel 4.10)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99978

xaxa...@gmail.com changed:

   What|Removed |Added

 CC||xaxa...@gmail.com

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[Mesa-dev] [Bug 99978] rotation causes undefined behavior after updating mesa (radeon, x11, kernel 4.10)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99978

Bug ID: 99978
   Summary: rotation causes undefined behavior after updating mesa
(radeon, x11, kernel 4.10)
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: major
  Priority: medium
 Component: Other
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: xaxa...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

Rotating one of my monitors makes it garbled and/or logs me out (causing
endless login loop).

Mesa 17.1 (padoka PPA).
Linux Kernel 4.10.
Xubuntu 16.10. (XFCE).
Radeon RX 480.

2 monitors:
A) Dell U2410 (1920x1080) via HDMI.
B) QNIX QX2710LED (2560x1440) via DVI.

Disabling #B doesn't help.

Not sure if this is a Mesa bug, but it's my best guess.
Note, this doesn't occur when using Unity, so it might be specific to X11?

I wonder if the unusual combo of HDMI + DVI might also be important - I did
find one related thread somewhere (lost it, sorry) mentioning they fixed
rotation issues by using different ports (Unfortunately, the QNIX only has
DVI).

This has been bugging me for a while, but I always rotated the monitor before
upgrading kernel/mesa etc so I didn't click that it was rotation until today.

Unfortunately I can't get a screenshot as it's too unstable. If it displays
anything before logging out it looks like strips of actual rotated desktop plus
strips of unintelligible data.

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[Mesa-dev] [PATCH 4/6] radeon/ac: make ac_shader_binary_config_start() available externally

[Timothy Arceri]

The read config functions are different for r600 and radeonsi so
we can't just share the one in amd common. So just share this
instead.
---
 src/amd/common/ac_binary.c | 1 -
 src/amd/common/ac_binary.h | 8 
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c
index 9c66a82..618b5cf 100644
--- a/src/amd/common/ac_binary.c
+++ b/src/amd/common/ac_binary.c
@@ -181,21 +181,20 @@ void ac_elf_read(const char *elf_data, unsigned elf_size,
/* Cache the config size per symbol */
if (binary->global_symbol_count) {
binary->config_size_per_symbol =
binary->config_size / binary->global_symbol_count;
} else {
binary->global_symbol_count = 1;
binary->config_size_per_symbol = binary->config_size;
}
 }
 
-static
 const unsigned char *ac_shader_binary_config_start(
const struct ac_shader_binary *binary,
uint64_t symbol_offset)
 {
unsigned i;
for (i = 0; i < binary->global_symbol_count; ++i) {
if (binary->global_symbol_offsets[i] == symbol_offset) {
unsigned offset = i * binary->config_size_per_symbol;
return binary->config + offset;
}
diff --git a/src/amd/common/ac_binary.h b/src/amd/common/ac_binary.h
index df945b2..0ece929 100644
--- a/src/amd/common/ac_binary.h
+++ b/src/amd/common/ac_binary.h
@@ -78,14 +78,22 @@ struct ac_shader_config {
unsigned scratch_bytes_per_wave;
 };
 
 /*
  * Parse the elf binary stored in \p elf_data and create a
  * ac_shader_binary object.
  */
 void ac_elf_read(const char *elf_data, unsigned elf_size,
 struct ac_shader_binary *binary);
 
+/**
+ * @returns A pointer to the start of the configuration information for
+ * the function starting at \p symbol_offset of the binary.
+ */
+const unsigned char *ac_shader_binary_config_start(
+   const struct ac_shader_binary *binary,
+   uint64_t symbol_offset);
+
 void ac_shader_binary_read_config(struct ac_shader_binary *binary,
  struct ac_shader_config *conf,
  unsigned symbol_offset,
  bool supports_spill);
-- 
2.9.3

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Re: [Mesa-dev] [PATCH v2] i965: Implement INTEL_performance_query backend

[Jonathan Gray]

On Thu, Feb 16, 2017 at 01:20:37PM +, Robert Bragg wrote:
> diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
> b/src/mesa/drivers/dri/i965/brw_performance_query.c
> new file mode 100644
> index 00..f1b6f583bf
> --- /dev/null
> +++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
> +/**
> + * \file brw_performance_query.c
> + *
> + * Implementation of the GL_INTEL_performance_query extension.
> + *
> + * Currently this driver only exposes the 64bit Pipeline Statistics
> + * Registers for Gen6+, with support for Observability Counters to be
> + * added later for Gen7.5+
> + */
> +
> +#include 
> +
> +#include 

Is this include needed on Linux?  It broke the Mesa build on OpenBSD
and builds fine with it removed here.

> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "main/hash.h"
> +#include "main/macros.h"
> +#include "main/mtypes.h"
> +#include "main/performance_query.h"
> +
> +#include "util/bitset.h"
> +#include "util/ralloc.h"
> +
> +#include "brw_context.h"
> +#include "brw_defines.h"
> +#include "brw_performance_query.h"
> +#include "intel_batchbuffer.h"
> +
> +#define FILE_DEBUG_FLAG DEBUG_PERFMON
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[Mesa-dev] [PATCH 1/2] radv/winsys: fix freeing imported memory.

[Dave Airlie]

From: Andres Rodriguez 

This bo->fd wasn't setting some stuff correctly that could
lead to crashes for anything using this path later.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index 7319a98..7f7fc7a 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -205,6 +205,8 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws,
bo->initial_domain = initial;
bo->size = result.alloc_size;
bo->is_shared = true;
+   bo->ws = ws;
+   radv_amdgpu_add_buffer_to_global_list(bo);
return (struct radeon_winsys_bo *)bo;
 error_va_map:
amdgpu_va_range_free(va_handle);
-- 
2.7.4

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[Mesa-dev] [PATCH 1/6] radeon/ac: add llvm_ir_string to ac_shader_binary struct

[Timothy Arceri]

---
 src/amd/common/ac_binary.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/common/ac_binary.h b/src/amd/common/ac_binary.h
index 06fd855..df945b2 100644
--- a/src/amd/common/ac_binary.h
+++ b/src/amd/common/ac_binary.h
@@ -56,20 +56,21 @@ struct ac_shader_binary {
 
/** List of symbol offsets for the shader */
uint64_t *global_symbol_offsets;
unsigned global_symbol_count;
 
struct ac_shader_reloc *relocs;
unsigned reloc_count;
 
/** Disassembled shader in a string. */
char *disasm_string;
+   char *llvm_ir_string;
 };
 
 struct ac_shader_config {
unsigned num_sgprs;
unsigned num_vgprs;
unsigned spilled_sgprs;
unsigned spilled_vgprs;
unsigned lds_size;
unsigned spi_ps_input_ena;
unsigned spi_ps_input_addr;
-- 
2.9.3

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Re: [Mesa-dev] [PATCH] mesa: Fix performance query id check

[Manolova, Plamena]

Looks good to me :)

Reviewed-by: Plamena Manolova 

On Fri, Feb 24, 2017 at 6:46 PM, Robert Bragg  wrote:

> In queryid_valid() index is unsigned so checking if it is less
> than zero is useless. On queryid_to_index() is comment
> saying 0 is reserved to be invalid thus rule it out.
>
> This is a v2 of a fix for an issue identified by Juha-Pekka (thanks)
> and the commit message is gratuitously stolen.
>
> Cc: Juha-Pekka Heikkila 
> Signed-off-by: Robert Bragg 
> ---
>  src/mesa/main/performance_query.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/main/performance_query.c
> b/src/mesa/main/performance_query.c
> index aa103516a5..56f6a7da8b 100644
> --- a/src/mesa/main/performance_query.c
> +++ b/src/mesa/main/performance_query.c
> @@ -90,8 +90,12 @@ index_to_queryid(unsigned index)
>  static inline bool
>  queryid_valid(const struct gl_context *ctx, unsigned numQueries, GLuint
> queryid)
>  {
> -   GLuint index = queryid_to_index(queryid);
> -   return index >= 0 && index < numQueries;
> +   /* The GL_INTEL_performance_query spec says:
> +*
> +*  "Performance counter ids values start with 1. Performance counter
> id 0
> +*  is reserved as an invalid counter."
> +*/
> +   return queryid != 0 && queryid_to_index(queryid) < numQueries;
>  }
>
>  static inline GLuint
> --
> 2.11.1
>
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>
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[Mesa-dev] [PATCH] radv/formats: add fast clear for 8-bit signed ints.

[Dave Airlie]

From: Dave Airlie 

These formats are used by some CTS tests, may as well fill them in.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_formats.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 30a20db..7483b8d 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -864,6 +864,10 @@ bool radv_format_pack_clear_color(VkFormat format,
clear_vals[0] = value->uint32[0] & 0xff;
clear_vals[1] = 0;
break;
+   case VK_FORMAT_R8_SINT:
+   clear_vals[0] = value->int32[0] & 0xff;
+   clear_vals[1] = 0;
+   break;
case VK_FORMAT_R16_UINT:
clear_vals[0] = value->uint32[0] & 0x;
clear_vals[1] = 0;
@@ -873,6 +877,11 @@ bool radv_format_pack_clear_color(VkFormat format,
clear_vals[0] |= (value->uint32[1] & 0xff) << 8;
clear_vals[1] = 0;
break;
+   case VK_FORMAT_R8G8_SINT:
+   clear_vals[0] = value->int32[0] & 0xff;
+   clear_vals[0] |= (value->int32[1] & 0xff) << 8;
+   clear_vals[1] = 0;
+   break;
case VK_FORMAT_R8G8B8A8_UINT:
clear_vals[0] = value->uint32[0] & 0xff;
clear_vals[0] |= (value->uint32[1] & 0xff) << 8;
@@ -880,6 +889,13 @@ bool radv_format_pack_clear_color(VkFormat format,
clear_vals[0] |= (value->uint32[3] & 0xff) << 24;
clear_vals[1] = 0;
break;
+   case VK_FORMAT_R8G8B8A8_SINT:
+   clear_vals[0] = value->int32[0] & 0xff;
+   clear_vals[0] |= (value->int32[1] & 0xff) << 8;
+   clear_vals[0] |= (value->int32[2] & 0xff) << 16;
+   clear_vals[0] |= (value->int32[3] & 0xff) << 24;
+   clear_vals[1] = 0;
+   break;
case VK_FORMAT_A8B8G8R8_UINT_PACK32:
clear_vals[0] = value->uint32[0] & 0xff;
clear_vals[0] |= (value->uint32[1] & 0xff) << 8;
-- 
2.9.3

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[Mesa-dev] [PATCH 2/2] radv: Use correct size for availability flag.

[Bas Nieuwenhuizen]

Per spec, VK_QUERY_RESULT_64_BIT specifies the integer size and the
availability flag is an integer. We apparently handled this correctly
already for the copy to buffer case.

Signed-off-by: Bas Nieuwenhuizen 
Cc: 13.0 17.0 
---
 src/amd/vulkan/radv_query.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index a2d0889fc03..288bd43a763 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -205,8 +205,11 @@ VkResult radv_GetQueryPoolResults(
}
 
if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
-   *(uint32_t*)dest = available;
-   dest += 4;
+   if (flags & VK_QUERY_RESULT_64_BIT) {
+   *(uint64_t*)dest = available;
+   } else {
+   *(uint32_t*)dest = available;
+   }
}
}
 
-- 
2.11.1

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[Mesa-dev] [PATCH 1/2] radv: Only use PKT3_OCCLUSION_QUERY when it doesn't hang.

[Bas Nieuwenhuizen]

PKT3_OCCLUSION_QUERY hangs when used in a nested IB. This only
calls it when in a primary command buffer and we change
GetQueryPoolResults to not need it. CmdCopyQueryPoolResults
still needs it so we break that behavior for secondary command buffers.
However, that would hang already and using an unitialized value is
better than a hang.

Signed-off-by: Bas Nieuwenhuizen 
Cc: 13.0 17.0 
---
 src/amd/vulkan/radv_query.c | 65 +++--
 1 file changed, 45 insertions(+), 20 deletions(-)

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index a29a05d4b84..a2d0889fc03 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -131,6 +131,7 @@ VkResult radv_GetQueryPoolResults(
VkDeviceSizestride,
VkQueryResultFlags  flags)
 {
+   RADV_FROM_HANDLE(radv_device, device, _device);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
char *data = pData;
VkResult result = VK_SUCCESS;
@@ -141,23 +142,20 @@ VkResult radv_GetQueryPoolResults(
char *src = pool->ptr + query * pool->stride;
uint32_t available;
 
-   if (flags & VK_QUERY_RESULT_WAIT_BIT) {
-   while(!*(volatile uint32_t*)(pool->ptr + 
pool->availability_offset + 4 * query))
-   ;
-   }
+   switch (pool->type) {
+   case VK_QUERY_TYPE_TIMESTAMP: {
+   if (flags & VK_QUERY_RESULT_WAIT_BIT) {
+   while(!*(volatile uint32_t*)(pool->ptr + 
pool->availability_offset + 4 * query))
+   ;
+   }
 
-   if (!*(uint32_t*)(pool->ptr + pool->availability_offset + 4 * 
query) &&
-   !(flags & VK_QUERY_RESULT_PARTIAL_BIT)) {
-   if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)
-   *(uint32_t*)dest = 0;
-   result = VK_NOT_READY;
-   continue;
+   available = *(uint32_t*)(pool->ptr + 
pool->availability_offset + 4 * query);
+   if (!available && !(flags & 
VK_QUERY_RESULT_PARTIAL_BIT)) {
+   result = VK_NOT_READY;
+   break;
 
-   }
+   }
 
-   available = *(uint32_t*)(pool->ptr + pool->availability_offset 
+ 4 * query);
-   switch (pool->type) {
-   case VK_QUERY_TYPE_TIMESTAMP:
if (flags & VK_QUERY_RESULT_64_BIT) {
*(uint64_t*)dest = *(uint64_t*)src;
dest += 8;
@@ -166,8 +164,32 @@ VkResult radv_GetQueryPoolResults(
dest += 4;
}
break;
+   }
case VK_QUERY_TYPE_OCCLUSION: {
-   uint64_t result = *(uint64_t*)(src + pool->stride - 16);
+   volatile uint64_t const *src64 = (volatile uint64_t 
const *)src;
+   uint64_t result = 0;
+   int db_count = get_max_db(device);
+   available = 1;
+
+   for (int i = 0; i < db_count; ++i) {
+   uint64_t start, end;
+   do {
+   start = src64[2 * i];
+   end = src64[2 * i + 1];
+   } while ((!(start & (1ull << 63)) || !(end & 
(1ull << 63))) && (flags & VK_QUERY_RESULT_WAIT_BIT));
+
+   if (!(start & (1ull << 63)) || !(end & (1ull << 
63)))
+   available = 0;
+   else {
+   result += end - start;
+   }
+   }
+
+   if (!available && !(flags & 
VK_QUERY_RESULT_PARTIAL_BIT)) {
+   result = VK_NOT_READY;
+   break;
+
+   }
 
if (flags & VK_QUERY_RESULT_64_BIT) {
*(uint64_t*)dest = result;
@@ -357,11 +379,14 @@ void radv_CmdEndQuery(
radeon_emit(cs, va + 8);
radeon_emit(cs, (va + 8) >> 32);
 
-   radeon_emit(cs, PKT3(PKT3_OCCLUSION_QUERY, 3, 0));
-   radeon_emit(cs, va);
-   radeon_emit(cs, va >> 32);
-   radeon_emit(cs, va + pool->stride - 16);
-   radeon_emit(cs, (va + pool->stride - 16) >> 32);
+   /* hangs for VK_COMMAND_BUFFER_LEVEL_SECONDARY. */
+   if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
+

[Mesa-dev] [PATCH 1/6] Get rid of trailing whitespace (trivial)

[Constantine Charlamov]

From: Hi-Angel 

Signed-off-by: Constantine Charlamov 
---
 src/gallium/drivers/r600/r600_shader.c | 44 +-
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 8cb3f8b2f4..46aa2c1abd 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -39,23 +39,23 @@
 #include 
 #include 
 
-/* CAYMAN notes 
+/* CAYMAN notes
 Why CAYMAN got loops for lots of instructions is explained here.
 
 -These 8xx t-slot only ops are implemented in all vector slots.
 MUL_LIT, FLT_TO_UINT, INT_TO_FLT, UINT_TO_FLT
-These 8xx t-slot only opcodes become vector ops, with all four 
-slots expecting the arguments on sources a and b. Result is 
+These 8xx t-slot only opcodes become vector ops, with all four
+slots expecting the arguments on sources a and b. Result is
 broadcast to all channels.
 MULLO_INT, MULHI_INT, MULLO_UINT, MULHI_UINT, MUL_64
-These 8xx t-slot only opcodes become vector ops in the z, y, and 
+These 8xx t-slot only opcodes become vector ops in the z, y, and
 x slots.
 EXP_IEEE, LOG_IEEE/CLAMPED, RECIP_IEEE/CLAMPED/FF/INT/UINT/_64/CLAMPED_64
 RECIPSQRT_IEEE/CLAMPED/FF/_64/CLAMPED_64
 SQRT_IEEE/_64
 SIN/COS
-The w slot may have an independent co-issued operation, or if the 
-result is required to be in the w slot, the opcode above may be 
+The w slot may have an independent co-issued operation, or if the
+result is required to be in the w slot, the opcode above may be
 issued in the w slot as well.
 The compiler must issue the source argument to slots z, y, and x
 */
@@ -3160,7 +3160,7 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
goto out_err;
}
}
-   
+
shader->ring_item_sizes[0] = ctx.next_ring_offset;
shader->ring_item_sizes[1] = 0;
shader->ring_item_sizes[2] = 0;
@@ -4272,7 +4272,7 @@ static int cayman_emit_float_instr(struct r600_shader_ctx 
*ctx)
int i, j, r;
struct r600_bytecode_alu alu;
int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
-   
+
for (i = 0 ; i < last_slot; i++) {
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = ctx->inst_info->op;
@@ -4799,7 +4799,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
alu.last = 1;
} else
alu.dst.write = 0;
-   
+
r = r600_bytecode_add_alu(ctx->bc, );
if (r)
return r;
@@ -5275,7 +5275,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int 
mod, int signed_op)
 
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP1_FLT_TO_UINT;
- 
+
alu.dst.sel = tmp0;
alu.dst.chan = 0;
alu.dst.write = 1;
@@ -5346,7 +5346,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int 
mod, int signed_op)
} else {
r600_bytecode_src([1], >src[1], i);
}
-   
+
alu.last = 1;
if ((r = r600_bytecode_add_alu(ctx->bc, )))
return r;
@@ -5612,7 +5612,7 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int 
mod, int signed_op)
} else {
r600_bytecode_src([0], >src[1], i);
}
-   
+
alu.src[1].sel = tmp0;
alu.src[1].chan = 2;
 
@@ -7014,7 +7014,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
r = r600_bytecode_add_alu(ctx->bc, );
if (r)
return r;
-   /* write initial compare value into Z component 
+   /* write initial compare value into Z component
  - W src 0 for shadow cube
  - X src 1 for shadow cube array */
if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
@@ -7092,7 +7092,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
r = r600_bytecode_add_alu(ctx->bc, );
if (r)
return r;
-   
+
r = r600_bytecode_add_tex(ctx->bc, );
if (r)
return r;
@@ -7419,7 +7419,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
/* does this shader want a num layers from TXQ for a cube array? */
if 

[Mesa-dev] [PATCH 4/6] Rename tgsi_last_instruction → tgsi_last_channel

[Constantine Charlamov]

From: Hi-Angel 

It's actually iterating through channels, checking whether they're
enabled

Signed-off-by: Constantine Charlamov 
---
 src/gallium/drivers/r600/r600_shader.c | 56 +-
 1 file changed, 28 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 905214f69b..972e013aef 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -377,7 +377,7 @@ static void r600_bytecode_src(struct r600_bytecode_alu_src 
*bc_src,
 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
   unsigned dst_reg);
 
-static int tgsi_last_instruction(unsigned writemask)
+static int tgsi_last_channel(unsigned writemask)
 {
int i, last_ch = 0;
 
@@ -2692,7 +2692,7 @@ static int r600_store_tcs_output(struct r600_shader_ctx 
*ctx)
return r;
 
/* LDS write */
-   lasti = tgsi_last_instruction(write_mask);
+   lasti = tgsi_last_channel(write_mask);
for (chan_index = 1; chan_index <= lasti; chan_index++) {
if(!TGSI_IS_DST0_CHANNEL_ENABLED(inst, chan_index))
continue;
@@ -3766,7 +3766,7 @@ static int tgsi_op2_64_params(struct r600_shader_ctx 
*ctx, bool singledest, bool
}
}
 
-   lasti = tgsi_last_instruction(write_mask);
+   lasti = tgsi_last_channel(write_mask);
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
memset(, 0, sizeof(struct r600_bytecode_alu));
 
@@ -3893,7 +3893,7 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int 
swap, int trans_only)
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
unsigned write_mask = inst->Dst[0].Register.WriteMask;
-   int chan_index, j, r, lasti = tgsi_last_instruction(write_mask);
+   int chan_index, j, r, lasti = tgsi_last_channel(write_mask);
/* use temp register if trans_only and more than one dst component */
int use_tmp = trans_only && (write_mask ^ (1 << lasti));
unsigned op = ctx->inst_info->op;
@@ -3966,7 +3966,7 @@ static int tgsi_ineg(struct r600_shader_ctx *ctx)
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
int chan_index, r;
-   int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+   int lasti = tgsi_last_channel(inst->Dst[0].Register.WriteMask);
 
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
memset(, 0, sizeof(struct r600_bytecode_alu));
@@ -3994,7 +3994,7 @@ static int tgsi_dneg(struct r600_shader_ctx *ctx)
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
int chan_index, r;
-   int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+   int lasti = tgsi_last_channel(inst->Dst[0].Register.WriteMask);
 
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
memset(, 0, sizeof(struct r600_bytecode_alu));
@@ -4084,7 +4084,7 @@ static int egcm_int_to_double(struct r600_shader_ctx *ctx)
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
int chan_index, r;
-   int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+   int lasti = tgsi_last_channel(inst->Dst[0].Register.WriteMask);
 
assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
inst->Instruction.Opcode == TGSI_OPCODE_U2D);
@@ -4131,7 +4131,7 @@ static int egcm_double_to_int(struct r600_shader_ctx *ctx)
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
int chan_index, r;
-   int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+   int lasti = tgsi_last_channel(inst->Dst[0].Register.WriteMask);
 
assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
inst->Instruction.Opcode == TGSI_OPCODE_D2U);
@@ -4208,7 +4208,7 @@ static int cayman_emit_double_instr(struct 
r600_shader_ctx *ctx)
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
int chan_index, r;
struct r600_bytecode_alu alu;
-   int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+   int lasti = tgsi_last_channel(inst->Dst[0].Register.WriteMask);
int t1 = ctx->temp_reg;
 
/* should only be one src regs */
@@ -4277,7 +4277,7 @@ static int cayman_mul_int_instr(struct r600_shader_ctx 
*ctx)
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
int chan_index, j, k, r;
struct r600_bytecode_alu alu;
-   int lasti = 

[Mesa-dev] [PATCH 3/6] Replace bit-shifts and cycles with helpers from tgsi_exec.h

[Constantine Charlamov]

From: Hi-Angel 

Changes turned out to be bigger than I expected, so I skipped over every
place where I was in doubts. Still, it looks better.


Signed-off-by: Constantine Charlamov 
---
 src/gallium/drivers/r600/r600_shader.c | 246 +
 1 file changed, 65 insertions(+), 181 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 8562678d0c..905214f69b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -30,6 +30,7 @@
 
 #include "pipe/p_shader_tokens.h"
 #include "tgsi/tgsi_info.h"
+#include "tgsi/tgsi_exec.h"
 #include "tgsi/tgsi_parse.h"
 #include "tgsi/tgsi_scan.h"
 #include "tgsi/tgsi_dump.h"
@@ -378,14 +379,14 @@ static int do_lds_fetch_values(struct r600_shader_ctx 
*ctx, unsigned temp_reg,
 
 static int tgsi_last_instruction(unsigned writemask)
 {
-   int i, lasti = 0;
+   int i, last_ch = 0;
 
-   for (i = 0; i < 4; i++) {
+   TGSI_FOR_EACH_CHANNEL (i) {
if (writemask & (1 << i)) {
-   lasti = i;
+   last_ch = i;
}
}
-   return lasti;
+   return last_ch;
 }
 
 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
@@ -2693,8 +2694,7 @@ static int r600_store_tcs_output(struct r600_shader_ctx 
*ctx)
/* LDS write */
lasti = tgsi_last_instruction(write_mask);
for (chan_index = 1; chan_index <= lasti; chan_index++) {
-
-   if (!(write_mask & (1 << chan_index)))
+   if(!TGSI_IS_DST0_CHANNEL_ENABLED(inst, chan_index))
continue;
r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
   temp_reg, chan_index,
@@ -2704,10 +2704,7 @@ static int r600_store_tcs_output(struct r600_shader_ctx 
*ctx)
return r;
}
 
-   for (chan_index = 0; chan_index <= lasti; chan_index++) {
-   if (!(write_mask & (1 << chan_index)))
-   continue;
-
+   TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
if ((chan_index == 0 && ((write_mask & 3) == 3)) ||
(chan_index == 2 && ((write_mask & 0xc) == 0xc))) {
memset(, 0, sizeof(struct r600_bytecode_alu));
@@ -3747,7 +3744,7 @@ static int tgsi_op2_64_params(struct r600_shader_ctx 
*ctx, bool singledest, bool
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
unsigned write_mask = inst->Dst[0].Register.WriteMask;
struct r600_bytecode_alu alu;
-   int chan_index, j, r, lasti = tgsi_last_instruction(write_mask);
+   int chan_index, j, r, lasti;
int use_tmp = 0;
 
if (singledest) {
@@ -3770,11 +3767,7 @@ static int tgsi_op2_64_params(struct r600_shader_ctx 
*ctx, bool singledest, bool
}
 
lasti = tgsi_last_instruction(write_mask);
-   for (chan_index = 0; chan_index <= lasti; chan_index++) {
-
-   if (!(write_mask & (1 << chan_index)))
-   continue;
-
+   TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
memset(, 0, sizeof(struct r600_bytecode_alu));
 
if (singledest) {
@@ -3823,10 +3816,7 @@ static int tgsi_op2_64_params(struct r600_shader_ctx 
*ctx, bool singledest, bool
write_mask = inst->Dst[0].Register.WriteMask;
 
/* move result from temp to dst */
-   for (chan_index = 0; chan_index <= lasti; chan_index++) {
-   if (!(write_mask & (1 << chan_index)))
-   continue;
-
+   TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP1_MOV;
tgsi_dst(ctx, >Dst[0], chan_index, );
@@ -3912,10 +3902,7 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int 
swap, int trans_only)
ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
op = ALU_OP2_MUL;
 
-   for (chan_index = 0; chan_index <= lasti; chan_index++) {
-   if (!(write_mask & (1 << chan_index)))
-   continue;
-
+   TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
memset(, 0, sizeof(struct r600_bytecode_alu));
if (use_tmp) {
alu.dst.sel = ctx->temp_reg;
@@ -3943,10 +3930,7 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int 
swap, int trans_only)
 
if (use_tmp) {
/* move result from temp to dst */
-   for (chan_index = 0; chan_index <= lasti; chan_index++) {
-   if (!(write_mask & (1 << chan_index)))
-   continue;
-
+   TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {

[Mesa-dev] [PATCH 2/6] radeon/ac: switch from radeon_shader_binary to ac_shader_binary

[Timothy Arceri]

---
 src/gallium/drivers/r600/evergreen_compute.c   |  4 +-
 .../drivers/r600/evergreen_compute_internal.h  |  2 +-
 src/gallium/drivers/radeon/r600_pipe_common.c  |  4 +-
 src/gallium/drivers/radeon/r600_pipe_common.h  | 43 ++
 src/gallium/drivers/radeon/radeon_elf_util.c   | 12 +++---
 src/gallium/drivers/radeon/radeon_elf_util.h   |  7 ++--
 src/gallium/drivers/radeonsi/si_debug.c|  2 +-
 src/gallium/drivers/radeonsi/si_pipe.h |  2 +-
 src/gallium/drivers/radeonsi/si_shader.c   | 16 
 src/gallium/drivers/radeonsi/si_shader.h   | 11 +++---
 src/gallium/drivers/radeonsi/si_shader_internal.h  |  4 +-
 .../drivers/radeonsi/si_shader_tgsi_setup.c|  2 +-
 12 files changed, 36 insertions(+), 73 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index f66c9f6..cf56d04 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -173,21 +173,21 @@ static void evergreen_cs_set_constant_buffer(struct 
r600_context *rctx,
 }
 
 /* We need to define these R600 registers here, because we can't include
  * evergreend.h and r600d.h.
  */
 #define R_028868_SQ_PGM_RESOURCES_VS 0x028868
 #define R_028850_SQ_PGM_RESOURCES_PS 0x028850
 
 #ifdef HAVE_OPENCL
 
-static void r600_shader_binary_read_config(const struct radeon_shader_binary 
*binary,
+static void r600_shader_binary_read_config(const struct ac_shader_binary 
*binary,
   struct r600_bytecode *bc,
   uint64_t symbol_offset,
   boolean *use_kill)
 {
unsigned i;
const unsigned char *config =
radeon_shader_binary_config_start(binary, symbol_offset);
 
for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
unsigned reg =
@@ -209,21 +209,21 @@ static void r600_shader_binary_read_config(const struct 
radeon_shader_binary *bi
*use_kill = G_02880C_KILL_ENABLE(value);
break;
case R_0288E8_SQ_LDS_ALLOC:
bc->nlds_dw = value;
break;
}
}
 }
 
 static unsigned r600_create_shader(struct r600_bytecode *bc,
-  const struct radeon_shader_binary *binary,
+  const struct ac_shader_binary *binary,
   boolean *use_kill)
 
 {
assert(binary->code_size % 4 == 0);
bc->bytecode = CALLOC(1, binary->code_size);
memcpy(bc->bytecode, binary->code, binary->code_size);
bc->ndw = binary->code_size / 4;
 
r600_shader_binary_read_config(binary, bc, 0, use_kill);
return 0;
diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.h 
b/src/gallium/drivers/r600/evergreen_compute_internal.h
index 34d96f6..6f4be3e 100644
--- a/src/gallium/drivers/r600/evergreen_compute_internal.h
+++ b/src/gallium/drivers/r600/evergreen_compute_internal.h
@@ -26,21 +26,21 @@
 #define EVERGREEN_COMPUTE_INTERNAL_H
 
 #include "r600_asm.h"
 #ifdef HAVE_OPENCL
 #include 
 #endif
 
 struct r600_pipe_compute {
struct r600_context *ctx;
 
-   struct radeon_shader_binary binary;
+   struct ac_shader_binary binary;
struct r600_resource *code_bo;
struct r600_bytecode bc;
 
unsigned local_size;
unsigned private_size;
unsigned input_size;
struct r600_resource *kernel_param;
 
 #ifdef HAVE_OPENCL
LLVMContextRef llvm_ctx;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 9a514e3..5a6f960 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -59,26 +59,26 @@ struct r600_multi_fence {
/* If the context wasn't flushed at fence creation, this is non-NULL. */
struct {
struct r600_common_context *ctx;
unsigned ib_index;
} gfx_unflushed;
 };
 
 /*
  * shader binary helpers.
  */
-void radeon_shader_binary_init(struct radeon_shader_binary *b)
+void radeon_shader_binary_init(struct ac_shader_binary *b)
 {
memset(b, 0, sizeof(*b));
 }
 
-void radeon_shader_binary_clean(struct radeon_shader_binary *b)
+void radeon_shader_binary_clean(struct ac_shader_binary *b)
 {
if (!b)
return;
FREE(b->code);
FREE(b->config);
FREE(b->rodata);
FREE(b->global_symbol_offsets);
FREE(b->relocs);
FREE(b->disasm_string);
FREE(b->llvm_ir_string);
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 94cf0fc..55d2d0b 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h

[Mesa-dev] [PATCH 5/6] radeon/ac: switch to ac_shader_binary_config_start()

[Timothy Arceri]

For radeonsi we could probably switch to
ac_shader_binary_read_config(). However the functions have
diverged so just share this helper for now.
---
 src/gallium/drivers/r600/evergreen_compute.c | 3 ++-
 src/gallium/drivers/radeonsi/si_shader.c | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index 2d5130f..2ddcbb3 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -19,20 +19,21 @@
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors:
  *  Adam Rak 
  */
 
 #include 
 #include 
+#include "ac_binary.h"
 #include "pipe/p_defines.h"
 #include "pipe/p_state.h"
 #include "pipe/p_context.h"
 #include "util/u_blitter.h"
 #include "util/list.h"
 #include "util/u_transfer.h"
 #include "util/u_surface.h"
 #include "util/u_pack_color.h"
 #include "util/u_memory.h"
 #include "util/u_inlines.h"
@@ -180,21 +181,21 @@ static void evergreen_cs_set_constant_buffer(struct 
r600_context *rctx,
 
 #ifdef HAVE_OPENCL
 
 static void r600_shader_binary_read_config(const struct ac_shader_binary 
*binary,
   struct r600_bytecode *bc,
   uint64_t symbol_offset,
   boolean *use_kill)
 {
unsigned i;
const unsigned char *config =
-   radeon_shader_binary_config_start(binary, symbol_offset);
+   ac_shader_binary_config_start(binary, symbol_offset);
 
for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
unsigned reg =
util_le32_to_cpu(*(uint32_t*)(config + i));
unsigned value =
util_le32_to_cpu(*(uint32_t*)(config + i + 4));
switch (reg) {
/* R600 / R700 */
case R_028850_SQ_PGM_RESOURCES_PS:
case R_028868_SQ_PGM_RESOURCES_VS:
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index e51b7c9..8e51ae8 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -26,27 +26,27 @@
  *  Christian König 
  */
 
 #include "gallivm/lp_bld_const.h"
 #include "gallivm/lp_bld_gather.h"
 #include "gallivm/lp_bld_intr.h"
 #include "gallivm/lp_bld_logic.h"
 #include "gallivm/lp_bld_arit.h"
 #include "gallivm/lp_bld_flow.h"
 #include "gallivm/lp_bld_misc.h"
-#include "radeon/radeon_elf_util.h"
 #include "util/u_memory.h"
 #include "util/u_string.h"
 #include "tgsi/tgsi_build.h"
 #include "tgsi/tgsi_util.h"
 #include "tgsi/tgsi_dump.h"
 
+#include "ac_binary.h"
 #include "ac_llvm_util.h"
 #include "si_shader_internal.h"
 #include "si_pipe.h"
 #include "sid.h"
 
 
 static const char *scratch_rsrc_dword0_symbol =
"SCRATCH_RSRC_DWORD0";
 
 static const char *scratch_rsrc_dword1_symbol =
@@ -5749,21 +5749,21 @@ static void si_llvm_emit_polygon_stipple(struct 
si_shader_context *ctx,
  LLVMConstReal(ctx->f32, -1), "");
lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, , 1, 0);
 }
 
 void si_shader_binary_read_config(struct ac_shader_binary *binary,
  struct si_shader_config *conf,
  unsigned symbol_offset)
 {
unsigned i;
const unsigned char *config =
-   radeon_shader_binary_config_start(binary, symbol_offset);
+   ac_shader_binary_config_start(binary, symbol_offset);
bool really_needs_scratch = false;
 
/* LLVM adds SGPR spills to the scratch size.
 * Find out if we really need the scratch buffer.
 */
for (i = 0; i < binary->reloc_count; i++) {
const struct ac_shader_reloc *reloc = >relocs[i];
 
if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
-- 
2.9.3

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[Mesa-dev] [PATCH 6/6] radeon: remove unused radeon_elf_util.{c, h}

[Timothy Arceri]

We now use the shared code in AMD common instead.
---
 src/gallium/drivers/r600/evergreen_compute.c   |   1 -
 src/gallium/drivers/radeon/Android.mk  |   1 -
 src/gallium/drivers/radeon/Makefile.am |   3 -
 src/gallium/drivers/radeon/Makefile.sources|   4 -
 src/gallium/drivers/radeon/radeon_elf_util.c   | 197 -
 src/gallium/drivers/radeon/radeon_elf_util.h   |  49 -
 .../drivers/radeonsi/si_shader_tgsi_setup.c|   1 -
 7 files changed, 256 deletions(-)
 delete mode 100644 src/gallium/drivers/radeon/radeon_elf_util.c
 delete mode 100644 src/gallium/drivers/radeon/radeon_elf_util.h

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index 2ddcbb3..ca2081a 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -40,21 +40,20 @@
 #include "util/u_framebuffer.h"
 #include "pipebuffer/pb_buffer.h"
 #include "evergreend.h"
 #include "r600_shader.h"
 #include "r600_pipe.h"
 #include "r600_formats.h"
 #include "evergreen_compute.h"
 #include "evergreen_compute_internal.h"
 #include "compute_memory_pool.h"
 #include "sb/sb_public.h"
-#include "radeon/radeon_elf_util.h"
 #include 
 
 /**
 RAT0 is for global binding write
 VTX1 is for global binding read
 
 for wrting images RAT1...
 for reading images TEX2...
   TEX2-RAT1 is paired
 
diff --git a/src/gallium/drivers/radeon/Android.mk 
b/src/gallium/drivers/radeon/Android.mk
index 31eaa16..2bddac8 100644
--- a/src/gallium/drivers/radeon/Android.mk
+++ b/src/gallium/drivers/radeon/Android.mk
@@ -24,19 +24,18 @@
 LOCAL_PATH := $(call my-dir)
 
 # get C_SOURCES
 include $(LOCAL_PATH)/Makefile.sources
 
 include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := $(C_SOURCES)
 
 ifeq ($(MESA_ENABLE_LLVM),true)
-LOCAL_SRC_FILES += $(LLVM_C_FILES)
 LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU   # instructs LLVM to declare 
LLVMInitializeAMDGPU* functions
 endif
 
 LOCAL_SHARED_LIBRARIES := libdrm_radeon
 LOCAL_MODULE := libmesa_pipe_radeon
 
 include $(GALLIUM_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
diff --git a/src/gallium/drivers/radeon/Makefile.am 
b/src/gallium/drivers/radeon/Makefile.am
index a6fc145..64c2799 100644
--- a/src/gallium/drivers/radeon/Makefile.am
+++ b/src/gallium/drivers/radeon/Makefile.am
@@ -12,23 +12,20 @@ noinst_LTLIBRARIES = libradeon.la
 
 libradeon_la_SOURCES = \
$(C_SOURCES)
 
 if NEED_RADEON_LLVM
 
 AM_CFLAGS += \
$(LLVM_CFLAGS) \
$(LIBELF_CFLAGS)
 
-libradeon_la_SOURCES += \
-   $(LLVM_C_FILES)
-
 libradeon_la_LIBADD = \
$(CLOCK_LIB) \
$(LLVM_LIBS) \
$(LIBELF_LIBS)
 
 libradeon_la_LDFLAGS = \
$(LLVM_LDFLAGS)
 
 endif
 
diff --git a/src/gallium/drivers/radeon/Makefile.sources 
b/src/gallium/drivers/radeon/Makefile.sources
index 3e13dae..9dd4e1a 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -15,14 +15,10 @@ C_SOURCES := \
radeon_uvd.c \
radeon_uvd.h \
radeon_vce_40_2_2.c \
radeon_vce_50.c \
radeon_vce_52.c \
radeon_vce.c \
radeon_vce.h \
radeon_video.c \
radeon_video.h \
radeon_winsys.h
-
-LLVM_C_FILES := \
-   radeon_elf_util.c \
-   radeon_elf_util.h
diff --git a/src/gallium/drivers/radeon/radeon_elf_util.c 
b/src/gallium/drivers/radeon/radeon_elf_util.c
deleted file mode 100644
index 21a7ed5..000
--- a/src/gallium/drivers/radeon/radeon_elf_util.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright 2014 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
THE
- * SOFTWARE.
- *
- * Authors: Tom Stellard 
- *
- */
-
-#include "radeon_elf_util.h"
-#include "r600_pipe_common.h"
-
-#include "util/u_memory.h"
-
-#include 
-#include 
-#include 
-
-static void 

Re: [Mesa-dev] [PATCH] doc: GL_ARB_buffer_storage is supported on llvmpipe/swr

[Gregory Hainaut]

On 2/25/17, Edward O'Callaghan  wrote:
> Acked-by: Edward O'Callaghan 
>
> On 02/25/2017 07:45 AM, Gregory Hainaut wrote:
>> At least, the extension is exported (gallium capability
>> PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT is 1)
>>
>> Signed-off-by: Gregory Hainaut 
>> ---
>>  docs/features.txt | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/docs/features.txt b/docs/features.txt
>> index d9528e9..9d3a460 100644
>> --- a/docs/features.txt
>> +++ b/docs/features.txt
>> @@ -191,7 +191,7 @@ GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0,
>> radeonsi
>>  GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, radeonsi
>>
>>GL_MAX_VERTEX_ATTRIB_STRIDE   DONE (all
>> drivers)
>> -  GL_ARB_buffer_storage DONE (i965, nv50,
>> r600)
>> +  GL_ARB_buffer_storage DONE (i965, nv50,
>> r600, llvmpipe, swr)
>>GL_ARB_clear_texture  DONE (i965, nv50,
>> r600, llvmpipe, softpipe)
>>GL_ARB_enhanced_layouts   DONE (i965, nv50,
>> llvmpipe, softpipe)
>>- compile-time constant expressions   DONE
>>
>
>

Hello,

I don't have git access. Could you push it too ?

Thanks you,
Gregory
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[Mesa-dev] [PATCH 2/2] radv: add support for NV_dedicated_allocation

[Dave Airlie]

From: Dave Airlie 

This adds initial support for NV_dedicated_allocation, then
uses it for the wsi image/memory allocation paths internally
in the driver.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_device.c   | 40 +-
 src/amd/vulkan/radv_entrypoints_gen.py |  1 +
 src/amd/vulkan/radv_private.h  |  7 +-
 src/amd/vulkan/radv_wsi.c  | 35 +++--
 4 files changed, 63 insertions(+), 20 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 7b81329..eaf610c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -33,7 +33,7 @@
 #include "radv_cs.h"
 #include "util/disk_cache.h"
 #include "util/strtod.h"
-
+#include "util/vk_util.h"
 #include 
 #include 
 #include 
@@ -111,6 +111,10 @@ static const VkExtensionProperties 
common_device_extensions[] = {
.extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
.specVersion = 1,
},
+   {
+   .extensionName = VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME,
+   .specVersion = 1,
+   },
 };
 
 static VkResult
@@ -1635,6 +1639,21 @@ PFN_vkVoidFunction radv_GetDeviceProcAddr(
return radv_lookup_entrypoint(pName);
 }
 
+bool radv_get_memory_fd(struct radv_device *device,
+   struct radv_device_memory *memory,
+   int *pFD)
+{
+   struct radeon_bo_metadata metadata;
+
+   if (memory->image) {
+   radv_init_metadata(device, memory->image, );
+   device->ws->buffer_set_metadata(memory->bo, );
+   }
+
+   return device->ws->buffer_get_fd(device->ws, memory->bo,
+pFD);
+}
+
 VkResult radv_AllocateMemory(
VkDevice_device,
const VkMemoryAllocateInfo* pAllocateInfo,
@@ -1646,6 +1665,7 @@ VkResult radv_AllocateMemory(
VkResult result;
enum radeon_bo_domain domain;
uint32_t flags = 0;
+   const VkDedicatedAllocationMemoryAllocateInfoNV *dedicate_info = NULL;
assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
 
if (pAllocateInfo->allocationSize == 0) {
@@ -1654,11 +1674,29 @@ VkResult radv_AllocateMemory(
return VK_SUCCESS;
}
 
+   vk_foreach_struct(ext, pAllocateInfo->pNext) {
+   switch (ext->sType) {
+   case 
VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV:
+   dedicate_info = (const 
VkDedicatedAllocationMemoryAllocateInfoNV *)ext;
+   break;
+   default:
+   break;
+   }
+   }
+
mem = vk_alloc2(>alloc, pAllocator, sizeof(*mem), 8,
  VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (mem == NULL)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 
+   if (dedicate_info) {
+   mem->image = radv_image_from_handle(dedicate_info->image);
+   mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
+   } else {
+   mem->image = NULL;
+   mem->buffer = NULL;
+   }
+
uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
diff --git a/src/amd/vulkan/radv_entrypoints_gen.py 
b/src/amd/vulkan/radv_entrypoints_gen.py
index 420de2c..b7b2bcf 100644
--- a/src/amd/vulkan/radv_entrypoints_gen.py
+++ b/src/amd/vulkan/radv_entrypoints_gen.py
@@ -29,6 +29,7 @@ max_api_version = 1.0
 
 supported_extensions = [
'VK_AMD_draw_indirect_count',
+   'VK_NV_dedicated_allocation',
'VK_KHR_get_physical_device_properties2',
'VK_KHR_maintenance1',
'VK_KHR_sampler_mirror_clamp_to_edge',
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 140bf8d..37549c5 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -523,6 +523,9 @@ struct radv_device {
 
 struct radv_device_memory {
struct radeon_winsys_bo  *bo;
+   /* for dedicated allocations */
+   struct radv_image*image;
+   struct radv_buffer   *buffer;
uint32_t type_index;
VkDeviceSize map_size;
void *   map;
@@ -814,7 +817,9 @@ void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
  struct radeon_winsys_bo *bo,
  uint64_t offset, uint64_t size, uint32_t value);
 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
-
+bool radv_get_memory_fd(struct radv_device 

[Mesa-dev] [PATCH mesa] docs: fix a few typos

[Eric Engestrom]

Noticed a couple, found the rest using vimspell.

Signed-off-by: Eric Engestrom 
---
 docs/autoconf.html  | 4 ++--
 docs/codingstyle.html   | 2 +-
 docs/egl.html   | 2 +-
 docs/envvars.html   | 2 +-
 docs/install.html   | 2 +-
 docs/llvmpipe.html  | 2 +-
 docs/releasing.html | 8 
 docs/sourcetree.html| 2 +-
 docs/submittingpatches.html | 2 +-
 9 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/docs/autoconf.html b/docs/autoconf.html
index 21ff8c11e4..df243c2c32 100644
--- a/docs/autoconf.html
+++ b/docs/autoconf.html
@@ -118,7 +118,7 @@ 1. Basic Usage
 
 PKG_CONFIG_PATH
 The
-pkg-config utility is a hard requirement for cofiguring and
+pkg-config utility is a hard requirement for configuring and
 building mesa. It is used to search for external libraries
 on the system. This environment variable is used to control the search
 path for pkg-config. For instance, setting
@@ -137,7 +137,7 @@ 1. Basic Usage
 hasn't already set them via the CFLAGS/CXXFLAGS) and macros to aid in
 debugging the Mesa libraries.
 
-Note that enabling this option can lead to noticable loss of 
performance.
+Note that enabling this option can lead to noticeable loss of 
performance.
 
 --disable-asm
 There are assembly routines
diff --git a/docs/codingstyle.html b/docs/codingstyle.html
index e5a92b0489..7e9f470a10 100644
--- a/docs/codingstyle.html
+++ b/docs/codingstyle.html
@@ -120,7 +120,7 @@
_mesa_foo_bar()  - an internal non-static Mesa function
 
 
-Constants, macros and enumerant names are ALL_UPPERCASE, with _ between
+Constants, macros and enum names are ALL_UPPERCASE, with _ between
 words.
 Mesa usually uses camel case for local variables (Ex: "localVarname")
 while gallium typically uses underscores (Ex: "local_var_name").
diff --git a/docs/egl.html b/docs/egl.html
index c22aa4a338..17823c2b0f 100644
--- a/docs/egl.html
+++ b/docs/egl.html
@@ -44,7 +44,7 @@
 
 The main library and OpenGL is enabled by default.  The first two options
 above enables OpenGL ES 1.x and 2.x.  The last two
-options enables the listed classic and and Gallium drivers respectively.
+options enables the listed classic and Gallium drivers respectively.
 
 
 
diff --git a/docs/envvars.html b/docs/envvars.html
index 2269f18564..9f1f70858d 100644
--- a/docs/envvars.html
+++ b/docs/envvars.html
@@ -119,7 +119,7 @@
 the on-disk cache of compiled GLSL programs. Should be set to a number
 optionally followed by 'K', 'M', or 'G' to specify a size in
 kilobytes, megabytes, or gigabytes. By default, gigabytes will be
-assumed. And if unset, a maxium size of 1GB will be used.
+assumed. And if unset, a maximum size of 1GB will be used.
 MESA_GLSL_CACHE_DIR - if set, determines the directory to be used
 for the on-disk cache of compiled GLSL programs. If this variable is
 not set, then the cache will be stored in $XDG_CACHE_HOME/mesa (if
diff --git a/docs/install.html b/docs/install.html
index 765ecea43d..08081944cf 100644
--- a/docs/install.html
+++ b/docs/install.html
@@ -178,7 +178,7 @@ 4. Building with AOSP (Android)
 
 
 In order to achieve that one should update their local manifest to point to the
-upstream repo, set the approapriate BOARD_GPU_DRIVERS and build the
+upstream repo, set the appropriate BOARD_GPU_DRIVERS and build the
 libGLES_mesa library.
 
 
diff --git a/docs/llvmpipe.html b/docs/llvmpipe.html
index 5fb3b7aa22..42272151c3 100644
--- a/docs/llvmpipe.html
+++ b/docs/llvmpipe.html
@@ -34,7 +34,7 @@
 
An x86 or amd64 processor; 64-bit mode recommended.

-   Support for SSE2 is strongly encouraged.  Support for SSSE3 and SSE4.1 will
+   Support for SSE2 is strongly encouraged.  Support for SSE3 and SSE4.1 will
yield the most efficient code.  The fewer features the CPU has the more
likely is that you run into underperforming, buggy, or incomplete code.

diff --git a/docs/releasing.html b/docs/releasing.html
index 242881a70b..07d459581c 100644
--- a/docs/releasing.html
+++ b/docs/releasing.html
@@ -57,11 +57,11 @@ Release schedule
 
 Feature releases
 
-Available approximatelly every three months.
+Available approximately every three months.
 Initial timeplan available 2-4 weeks before the planned branchpoint (rc1)
 on the mesa-announce@ mailing list.
 A pre-release announcement should be available
-approximatelly 24 hours before the final (non-rc) release.
+approximately 24 hours before the final (non-rc) release.
 
 
 Stable releases
@@ -69,7 +69,7 @@ Release schedule
 Normally available once every two weeks.
 Only the latest branch has releases. See note below.
 A pre-release announcement should be available
-approximatelly 48 hours before the actual release.
+approximately 48 hours before the actual release.
 
 
 
@@ -453,7 +453,7 @@ Making a new release
 Add the sha256sums to the release notes
 
 
-Edit docs/relnotes/X.Y.Z.html to add the sha256sums as availabe in the 
mesa-X.Y.Z.announce template. Commit this 

[Mesa-dev] [PATCH 3/6] radeon/ac: switch from radeon_elf_read() to ac_elf_read()

[Timothy Arceri]

---
 src/gallium/drivers/r600/evergreen_compute.c| 2 +-
 src/gallium/drivers/radeonsi/si_compute.c   | 3 +--
 src/gallium/drivers/radeonsi/si_debug.c | 3 +--
 src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 2 +-
 4 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index cf56d04..2d5130f 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -244,21 +244,21 @@ static void *evergreen_create_compute_state(struct 
pipe_context *ctx,
 #ifdef HAVE_OPENCL
const struct pipe_llvm_program_header *header;
const char *code;
void *p;
boolean use_kill;
 
COMPUTE_DBG(rctx->screen, "*** evergreen_create_compute_state\n");
header = cso->prog;
code = cso->prog + sizeof(struct pipe_llvm_program_header);
radeon_shader_binary_init(>binary);
-   radeon_elf_read(code, header->num_bytes, >binary);
+   ac_elf_read(code, header->num_bytes, >binary);
r600_create_shader(>bc, >binary, _kill);
 
/* Upload code + ROdata */
shader->code_bo = r600_compute_buffer_alloc_vram(rctx->screen,
shader->bc.ndw * 4);
p = r600_buffer_map_sync_with_rings(>b, shader->code_bo, 
PIPE_TRANSFER_WRITE);
//TODO: use util_memcpy_cpu_to_le32 ?
memcpy(p, shader->bc.bytecode, shader->bc.ndw * 4);
rctx->b.ws->buffer_unmap(shader->code_bo->buf);
 #endif
diff --git a/src/gallium/drivers/radeonsi/si_compute.c 
b/src/gallium/drivers/radeonsi/si_compute.c
index f4efb0d..5097c81 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -18,21 +18,20 @@
  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  */
 
 #include "tgsi/tgsi_parse.h"
 #include "util/u_memory.h"
 #include "util/u_upload_mgr.h"
-#include "radeon/radeon_elf_util.h"
 
 #include "amd_kernel_code_t.h"
 #include "radeon/r600_cs.h"
 #include "si_pipe.h"
 #include "sid.h"
 
 #define MAX_GLOBAL_BUFFERS 22
 
 struct si_compute {
unsigned ir_type;
@@ -153,21 +152,21 @@ static void *si_create_compute_state(
sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] 
== 0;
 
FREE(sel.tokens);
program->shader.selector = NULL;
} else {
const struct pipe_llvm_program_header *header;
const char *code;
header = cso->prog;
code = cso->prog + sizeof(struct pipe_llvm_program_header);
 
-   radeon_elf_read(code, header->num_bytes, 
>shader.binary);
+   ac_elf_read(code, header->num_bytes, >shader.binary);
if (program->use_code_object_v2) {
const amd_kernel_code_t *code_object =
si_compute_get_code_object(program, 0);
code_object_to_config(code_object, 
>shader.config);
} else {
si_shader_binary_read_config(>shader.binary,
 >shader.config, 0);
}
si_shader_dump(sctx->screen, >shader, >b.debug,
   PIPE_SHADER_COMPUTE, stderr, true);
diff --git a/src/gallium/drivers/radeonsi/si_debug.c 
b/src/gallium/drivers/radeonsi/si_debug.c
index f04b8fa..1092aa2 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -20,21 +20,20 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors:
  *  Marek Olšák 
  */
 
 #include "si_pipe.h"
 #include "sid.h"
 #include "sid_tables.h"
-#include "radeon/radeon_elf_util.h"
 #include "ddebug/dd_util.h"
 #include "util/u_memory.h"
 #include "ac_debug.h"
 
 DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL)
 
 static void si_dump_shader(struct si_screen *sscreen,
   struct si_shader_ctx_state *state, FILE *f)
 {
struct si_shader *current = state->current;
@@ -119,21 +118,21 @@ bool si_replace_shader(unsigned num, struct 
ac_shader_binary *binary)
buf = MALLOC(filesize);
if (!buf) {
fprintf(stderr, "out of memory\n");
goto out_close;
}
 
nread = fread(buf, 1, filesize, f);
if (nread != filesize)
goto file_error;
 
-   radeon_elf_read(buf, filesize, binary);
+   ac_elf_read(buf, filesize, binary);
replaced = true;
 
 out_close:
fclose(f);
 out_free:
FREE(buf);

[Mesa-dev] [PATCH] radv/ac: gather4 cube workaround integer

[Dave Airlie]

From: Dave Airlie 

This fix is extracted from amdgpu-pro shader traces.

It appears the gather4 workaround for integer types doesn't
work for cubes, so instead if forces a float scaled sample,
then converts to integer.

It modifies the descriptor before calling the gather.

This also produces some ugly asm code for reasons specified
in the patch, llvm could probably do better than dumping
sgprs to vgprs.

This fixes:
dEQP-VK.glsl.texture_gather.basic.cube.rgba8*

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 74 -
 1 file changed, 73 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 4f3d689..8cfe2fb 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1645,8 +1645,11 @@ static LLVMValueRef radv_lower_gather4_integer(struct 
nir_to_llvm_context *ctx,
   const char *intr_name,
   unsigned coord_vgpr_index)
 {
+   enum glsl_base_type stype = 
glsl_get_sampler_result_type(instr->texture->var->type);
LLVMValueRef coord = tinfo->args[0];
LLVMValueRef half_texel[2];
+   LLVMValueRef compare_cube_wa;
+   LLVMValueRef result;
int c;
 
//TODO Rect
@@ -1679,6 +1682,8 @@ static LLVMValueRef radv_lower_gather4_integer(struct 
nir_to_llvm_context *ctx,
}
}
 
+   LLVMValueRef orig_coords = tinfo->args[0];
+
for (c = 0; c < 2; c++) {
LLVMValueRef tmp;
LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + 
c, 0);
@@ -1689,10 +1694,77 @@ static LLVMValueRef radv_lower_gather4_integer(struct 
nir_to_llvm_context *ctx,
coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, 
"");
}
 
+   /*
+* Apparantly cube has issue with integer types that the workaround 
doesn't solve,
+* so this tests if the format is 8_8_8_8 and an integer type do an 
alternate
+* workaround by sampling using a scaled type and converting.
+* This is taken from amdgpu-pro shaders.
+*/
+   /* NOTE this produces some ugly code compared to amdgpu-pro,
+* LLVM ends up dumping SGPRs into VGPRs to deal with the 
compare/select,
+* and then reads them back. -pro generates two selects,
+* one s_cmp for the descriptor rewriting
+* one v_cmp for the coordinate and result changes.
+*/
+   if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
+   LLVMValueRef tmp, tmp2;
+
+   /* workaround 8/8/8/8 uint/sint cube gather bug */
+   /* first detect it then change to a scaled read and f2i */
+   tmp = LLVMBuildExtractElement(ctx->builder, tinfo->args[1], 
ctx->i32one, "");
+   tmp2 = tmp;
+
+   /* extract the DATA_FORMAT */
+   LLVMValueRef bfeargs[3];
+   bfeargs[0] = tmp;
+   bfeargs[1] = LLVMConstInt(ctx->i32, 20, false);
+   bfeargs[2] = LLVMConstInt(ctx->i32, 6, false);
+   tmp = ac_emit_llvm_intrinsic(>ac, "llvm.AMDGPU.bfe.u32", 
ctx->i32, bfeargs, 3, AC_FUNC_ATTR_READNONE);
+
+   /* is the DATA_FORMAT == 8_8_8_8 */
+   compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, 
LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
+
+   if (stype == GLSL_TYPE_UINT)
+   /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
+   tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, 
LLVMConstInt(ctx->i32, 0x800, false),
+ LLVMConstInt(ctx->i32, 
0x1000, false), "");
+   else
+   /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
+   tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, 
LLVMConstInt(ctx->i32, 0xc00, false),
+ LLVMConstInt(ctx->i32, 
0x1400, false), "");
+
+   /* replace the NUM FORMAT in the descriptor */
+   tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, 
C_008F14_NUM_FORMAT, false), "");
+   tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
+
+   tinfo->args[1] = LLVMBuildInsertElement(ctx->builder, 
tinfo->args[1], tmp2, ctx->i32one, "");
+
+   /* don't modify the coordinates for this case */
+   coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, 
orig_coords, coord, "");
+   }
tinfo->args[0] = coord;
-   return ac_emit_llvm_intrinsic(>ac, intr_name, tinfo->dst_type, 
tinfo->args, tinfo->arg_count,
+   result = ac_emit_llvm_intrinsic(>ac, intr_name, tinfo->dst_type, 
tinfo->args, tinfo->arg_count,
   

[Mesa-dev] [Bug 99959] egl-entrypoint-check fails

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99959

--- Comment #4 from Emil Velikov  ---
Yes, I was "right" only after I got it wrong - it was me who did suggested sh
:-\

-- 
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You are the QA Contact for the bug.
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[Mesa-dev] [PATCH] radv: Reset emitted compute pipeline when calling secondary cmd buffer.

[Bas Nieuwenhuizen]

Otherwise if the new compute pipeline is the same as the last used
pipeline before the call, we don't emit it again.

Signed-off-by: Bas Nieuwenhuizen 
Cc: 13.0 17.0 
---
 src/amd/vulkan/radv_cmd_buffer.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1e38cbe1251..709ae8bb560 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2114,6 +2114,7 @@ void radv_CmdExecuteCommands(
/* if we execute secondary we need to re-emit out pipelines */
if (commandBufferCount) {
primary->state.emitted_pipeline = NULL;
+   primary->state.emitted_compute_pipeline = NULL;
primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL;
}
-- 
2.11.1

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Re: [Mesa-dev] [PATCH] android: vulkan: add support for libmesa_vulkan_{util, wsi}

[Emil Velikov]

Hi Mauro,

On 25 February 2017 at 18:31, Mauro Rossi  wrote:
> The following commits require android porting:
>
> e9dcb17 "vulkan/util: Add generator for enum_to_str functions"
> 8e03250 "vulkan: Combine wsi and util makefiles"
>
Please add "Fixes: " before each one of these. See commit
5398d006de3d2bd668e3fc4b80a3de0c101a3e43


> +LOCAL_GENERATED_SOURCES := \
> +   $(intermediates)/util/vk_enum_to_str.c \
> +   $(intermediates)/util/vk_enum_to_str.h
> +
> +vulkan_api_xml = $(MESA_TOP)/src/vulkan/registry/vk.xml
> +
> +$(LOCAL_GENERATED_SOURCES): PRIVATE_PYTHON := $(MESA_PYTHON2)
> +$(LOCAL_GENERATED_SOURCES): PRIVATE_CUSTOM_TOOL := $(PRIVATE_PYTHON) 
> $(MESA_TOP)/src/vulkan/util/gen_enum_to_str.py -o $(intermediates)/util
> +$(LOCAL_GENERATED_SOURCES): $(MESA_TOP)/src/vulkan/util/gen_enum_to_str.py 
> $(vulkan_api_xml)
> +   $(transform-generated-source)
> +
I feel like a broken record:

Can we stop copying these/such generation rules, please ?



> +#
> +# libmesa_vulkan_wsi
> +#
> +
> +include $(CLEAR_VARS)
> +LOCAL_MODULE := libmesa_vulkan_wsi
> +
> +LOCAL_SRC_FILES := $(VULKAN_WSI_SOURCES)
> +
> +LOCAL_C_INCLUDES := \
> +   $(MESA_TOP)/include/vulkan
> +
> +include $(MESA_COMMON_MK)
> +include $(BUILD_STATIC_LIBRARY)
This part [libmesa_vulkan_wsi] is unused so I'll keep it out for now.



>  util/vk_enum_to_str.c util/vk_enum_to_str.h: util/gen_enum_to_str.py 
> $(vulkan_api_xml)
> $(MKDIR_GEN)
> -   $(PYTHON_GEN) $(srcdir)/util/gen_enum_to_str.py
> +   $(PYTHON_GEN) $(srcdir)/util/gen_enum_to_str.py -o 
> $(top_builddir)/src/vulkan/util
>
Nice one, thank you !


> @@ -30,6 +31,14 @@ from mako.template import Template
>
>  VK_XML = os.path.join(os.path.dirname(__file__), '..', 'registry', 'vk.xml')
>
> +parser = 
> argparse.ArgumentParser(formatter_class=argparse.RawTextHelpFormatter)
> +parser.add_argument('-o', '--output-path', help=textwrap.dedent('''\
> +   -o $(top_builddir)/src/vulkan/util for Linux builds
> +   -o $(intermediates)/util for Android builds'''),
Not sure if we need all this help string. Not to mention that we'll
forget to update as we move things around.

That aside things look fine from my POV but I'd appreciate an ack from
Dylan on the Python parts.


Thanks
Emil
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[Mesa-dev] [Bug 99856] OpenCL Hello world returns "unsupported call to function get_local_size"

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99856

--- Comment #16 from Henrique Dante de Almeida  ---
Weird ! So was this a bug in IR source code ?

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Re: [Mesa-dev] [PATCH v3 00/15] cleanup anv_entrpoints_gen.py

[Emil Velikov]

On 24 February 2017 at 18:21, Dylan Baker  wrote:
> There are a number of small style cleanups and simplifications in this series,
> but the main changes are:
>  - use a mako template to generate the header and code rather than prints
>  - be python 3.x ready (the goal isn't to write python 3 code, but to write 
> code
>that is easy to port or hybridize)
>  - generate the header and the code in one go
>
> I've put emphasis on the readability of the template rather than the 
> readability
> of the output code, it's relatively easy to pipe the code through 'indent' to
> make it more readable.
>
> Notable changes in Version 2:
> - Pass XML file via an argument
> - add flag to control output directory
> - Attempt to update android makefiles
>
> Notable changes in Version 3:
> - Fix "do not edit" message to have proper file name
> - More Android.mk changes

> - Don't write both files at the same time
> - Provide the file name to be written to as an argument
>
Not sure why you opted to rewrite this considering that we already
have such bugs in-tree and the fix was a 2-line change in the
makefile(s). Perhaps I should have made that clearer :-(

That aside - tried to pull/test your series, but patchwork has gone
crazy (doesn't like git series?). Do you have a branch somewhere ?

Thanks
Emil
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Re: [Mesa-dev] [PATCH] glx/tests: Fix bash-specific code in dispatch-index-check

[Emil Velikov]

On 26 February 2017 at 13:51, Eric Engestrom  wrote:
> On Friday, 2017-02-24 22:03:36 -0600, Aaron Watry wrote:
>> Using <<< for variable redirection is bash-specific behavior.
>> Ubuntu redirects sh -> dash, so this was erroring out.
>>
>> Also, the initial error that led me to this was that srcdir is null when 
>> running make check
>> so I just copied something similar to what the optimization-test script does.
>> ---
>>  src/glx/tests/dispatch-index-check | 21 ++---
>>  1 file changed, 14 insertions(+), 7 deletions(-)
>>
>> diff --git a/src/glx/tests/dispatch-index-check 
>> b/src/glx/tests/dispatch-index-check
>> index 78464b8..ee1b9ee 100755
>> --- a/src/glx/tests/dispatch-index-check
>> +++ b/src/glx/tests/dispatch-index-check
>> @@ -1,24 +1,31 @@
>>  #!/bin/sh
>>
>> +if [ -z "$srcdir" ]; then
>> +   scriptdir=`dirname "$0"`
>> +else
>> +   scriptdir=$srcdir
>> +fi
>> +
>> +
>>  # extract enum definition
>>  dispatch_list=$(sed '/__GLXdispatchIndex/,/__GLXdispatchIndex/!d' \
>> -  "$srcdir"/../g_glxglvnddispatchindices.h)
>> +  "$scriptdir"/../g_glxglvnddispatchindices.h)
>
> No need to create a new var that just copies the old one :)
>
>>
>>  # extract values inside of enum
>> -dispatch_list=$(sed '1d;$d' <<< "$dispatch_list")
>> +dispatch_list=$(printf "$dispatch_list" | sed '1d;$d')
>
> Never use a variable you have no control over as the format string for
> printf! Use `printf '%s' "$var"` instead.
>
> I just pushed a1e5e55989 ("check: mark two tests are requiring bash")
> which fixes this by simply asking for bash in the shebang, which was
> what my original patch did, and was changed just before pushing because
> of a review comment that turned out to be wrong :)
>
Yes, my bad on that one - guess I shouldn't trust checkbashisms/zsh that much.

I won't object if we can make these tests 'generic' sh - patches welcome ;-)
Emil
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Re: [Mesa-dev] [PATCH] glsl: remove unecessary flags.q.subroutine_def

[Timothy Arceri]

On 25/02/17 22:15, Samuel Pitoiset wrote:

This bit is definitely not necessary because subroutine_list
can be used instead. This frees one more bit in the flags.q
struct which is nice because arb_bindless_texture will need
4 bits for the new layout qualifiers.

No piglit regressions found (including compiler tests) with
"-t subroutine".

Signed-off-by: Samuel Pitoiset 
---
 src/compiler/glsl/ast.h  | 1 -
 src/compiler/glsl/ast_to_hir.cpp | 6 +++---
 src/compiler/glsl/ast_type.cpp   | 6 ++
 src/compiler/glsl/glsl_parser.yy | 1 -
 src/compiler/glsl/glsl_parser_extras.cpp | 2 +-
 5 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index 11a092e41c..d27b940744 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -607,7 +607,6 @@ struct ast_type_qualifier {
  /** \name Qualifiers for GL_ARB_shader_subroutine */
 /** \{ */
  unsigned subroutine:1;  /**< Is this marked 'subroutine' */
- unsigned subroutine_def:1; /**< Is this marked 'subroutine' with a 
list of types */
 /** \} */

  /** \name Qualifiers for GL_KHR_blend_equation_advanced */
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index f033d7df97..7e99faeaed 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -3510,7 +3510,7 @@ apply_layout_qualifier_to_variable(const struct 
ast_type_qualifier *qual,
  }
   }
} else if (qual->flags.q.explicit_index) {
-  if (!qual->flags.q.subroutine_def)
+  if (!qual->subroutine_list)
  _mesa_glsl_error(loc, state,
   "explicit index requires explicit location");
} else if (qual->flags.q.explicit_component) {
@@ -5568,7 +5568,7 @@ ast_function::hir(exec_list *instructions,
 *  "Subroutine declarations cannot be prototyped. It is an error to prepend
 *   subroutine(...) to a function declaration."
 */
-   if (this->return_type->qualifier.flags.q.subroutine_def && !is_definition) {
+   if (this->return_type->qualifier.subroutine_list && !is_definition) {
   YYLTYPE loc = this->get_location();
   _mesa_glsl_error(, state,
"function declaration `%s' cannot have subroutine 
prepended",
@@ -5716,7 +5716,7 @@ ast_function::hir(exec_list *instructions,
sig->replace_parameters(_parameters);
signature = sig;

-   if (this->return_type->qualifier.flags.q.subroutine_def) {
+   if (this->return_type->qualifier.subroutine_list) {
   int idx;

   if (this->return_type->qualifier.flags.q.explicit_index) {
diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
index 96d20c10af..5f868a81f2 100644
--- a/src/compiler/glsl/ast_type.cpp
+++ b/src/compiler/glsl/ast_type.cpp
@@ -44,7 +44,6 @@ 
ast_fully_specified_type::has_qualifiers(_mesa_glsl_parse_state *state) const
ast_type_qualifier subroutine_only;
subroutine_only.flags.i = 0;
subroutine_only.flags.q.subroutine = 1;
-   subroutine_only.flags.q.subroutine_def = 1;
if (state->has_explicit_uniform_location()) {
   subroutine_only.flags.q.explicit_index = 1;
}
@@ -285,8 +284,8 @@ ast_type_qualifier::merge_qualifier(YYLTYPE *loc,
   }
}

-   if (q.flags.q.subroutine_def) {
-  if (this->flags.q.subroutine_def) {
+   if (q.subroutine_list) {
+  if (this->subroutine_list) {
  _mesa_glsl_error(loc, state,
   "conflicting subroutine qualifiers used");
   } else {
@@ -772,7 +771,6 @@ ast_type_qualifier::validate_flags(YYLTYPE *loc,
 bad.flags.q.point_mode ? " point_mode" : "",
 bad.flags.q.vertices ? " vertices" : "",
 bad.flags.q.subroutine ? " subroutine" : "",
-bad.flags.q.subroutine_def ? " subroutine_def" : "",
 bad.flags.q.blend_support ? " blend_support" : "",
 bad.flags.q.inner_coverage ? " inner_coverage" : "",
 bad.flags.q.post_depth_coverage ? " post_depth_coverage" : 
"");
diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index d703f8..b79fcee550 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -1812,7 +1812,6 @@ subroutine_qualifier:
| SUBROUTINE '(' subroutine_type_list ')'
{
   memset(& $$, 0, sizeof($$));
-  $$.flags.q.subroutine_def = 1;


You need to change this to:

   $$.flags.q.subroutine = 1;

Otherwise we won't detect if the qualifier was added when it should have 
been etc.




   $$.subroutine_list = $3;
}
;
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index 375a99a49d..e88dd071b3 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -1075,7 +1075,7 @@ 

[Mesa-dev] [PATCH 6/6] Remove redudant comparisons

[Constantine Charlamov]

From: Hi-Angel 

Signed-off-by: Constantine Charlamov 
---
 src/gallium/drivers/r600/r600_shader.c | 64 --
 1 file changed, 14 insertions(+), 50 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 3616de572b..9afaaa57ba 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -745,10 +745,7 @@ static int single_alu_op2(struct r600_shader_ctx *ctx, int 
op,
alu.dst.chan = dst_chan;
alu.dst.write = 1;
alu.last = 1;
-   r = r600_bytecode_add_alu(ctx->bc, );
-   if (r)
-   return r;
-   return 0;
+   return r600_bytecode_add_alu(ctx->bc, );
 }
 
 /* execute a single slot ALU calculation */
@@ -759,7 +756,6 @@ static int single_alu_op3(struct r600_shader_ctx *ctx, int 
op,
  int src2_sel, unsigned src2_chan_val)
 {
struct r600_bytecode_alu alu;
-   int r;
 
/* validate this for other ops */
assert(op == ALU_OP3_MULADD_UINT24);
@@ -784,10 +780,7 @@ static int single_alu_op3(struct r600_shader_ctx *ctx, int 
op,
alu.dst.chan = dst_chan;
alu.is_op3 = 1;
alu.last = 1;
-   r = r600_bytecode_add_alu(ctx->bc, );
-   if (r)
-   return r;
-   return 0;
+   return r600_bytecode_add_alu(ctx->bc, );
 }
 
 /* put it in temp_reg.x */
@@ -795,21 +788,16 @@ static int get_lds_offset0(struct r600_shader_ctx *ctx,
   int rel_patch_chan,
   int temp_reg, bool is_patch_var)
 {
-   int r;
-
/* MUL temp.x, patch_stride (input_vals.x), rel_patch_id (r0.y (tcs)) */
/* ADD
   Dimension - patch0_offset (input_vals.z),
   Non-dim - patch0_data_offset (input_vals.w)
*/
-   r = single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
-  temp_reg, 0,
-  ctx->tess_output_info, 0,
-  0, rel_patch_chan,
-  ctx->tess_output_info, is_patch_var ? 3 : 2);
-   if (r)
-   return r;
-   return 0;
+   return single_alu_op3(ctx, ALU_OP3_MULADD_UINT24,
+ temp_reg, 0,
+ ctx->tess_output_info, 0,
+ 0, rel_patch_chan,
+ ctx->tess_output_info, is_patch_var ? 3 : 2);
 }
 
 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
@@ -839,16 +827,12 @@ static int vs_add_primid_output(struct r600_shader_ctx 
*ctx, int prim_id_sid)
 static int tgsi_barrier(struct r600_shader_ctx *ctx)
 {
struct r600_bytecode_alu alu;
-   int r;
 
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = ctx->inst_info->op;
alu.last = 1;
 
-   r = r600_bytecode_add_alu(ctx->bc, );
-   if (r)
-   return r;
-   return 0;
+   return r600_bytecode_add_alu(ctx->bc, );
 }
 
 static int tgsi_declaration(struct r600_shader_ctx *ctx)
@@ -1793,10 +1777,7 @@ static int fetch_tes_input(struct r600_shader_ctx *ctx, 
struct tgsi_full_src_reg
if (r)
return r;
 
-   r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
-   if (r)
-   return r;
-   return 0;
+   return do_lds_fetch_values(ctx, temp_reg, dst_reg);
 }
 
 static int fetch_tcs_input(struct r600_shader_ctx *ctx, struct 
tgsi_full_src_register *src, unsigned int dst_reg)
@@ -1819,10 +1800,7 @@ static int fetch_tcs_input(struct r600_shader_ctx *ctx, 
struct tgsi_full_src_reg
if (r)
return r;
 
-   r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
-   if (r)
-   return r;
-   return 0;
+   return do_lds_fetch_values(ctx, temp_reg, dst_reg);
 }
 
 static int fetch_tcs_output(struct r600_shader_ctx *ctx, struct 
tgsi_full_src_register *src, unsigned int dst_reg)
@@ -1841,10 +1819,7 @@ static int fetch_tcs_output(struct r600_shader_ctx *ctx, 
struct tgsi_full_src_re
if (r)
return r;
 
-   r = do_lds_fetch_values(ctx, temp_reg, dst_reg);
-   if (r)
-   return r;
-   return 0;
+   return do_lds_fetch_values(ctx, temp_reg, dst_reg);
 }
 
 static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx)
@@ -4493,10 +4468,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
}
 
alu.last = 1;
-   r = r600_bytecode_add_alu(ctx->bc, );
-   if (r)
-   return r;
-   return 0;
+   return r600_bytecode_add_alu(ctx->bc, );
 }
 
 static int cayman_trig(struct r600_shader_ctx *ctx)
@@ -6679,7 +6651,6 @@ static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
 {
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
-   int r;
int id = tgsi_tex_get_src_gpr(ctx, 1);
 

Re: [Mesa-dev] [PATCH] vulkan/wsi: Improve the DRI3 error message

[Jason Ekstrand]

On Feb 25, 2017 6:17 PM, "Jacob Lifshay"  wrote:

Just to double check, is there anything else I need to do to have this
patch committed?


The only thing I've been waiting for is someone to confirm that they've
tested it on a variety of configurations and that it actually does what it
claims to do.

--Jason

Jacob Lifshay

On Feb 19, 2017 02:08, "Kai Wasserbäch"  wrote:

> Jason Ekstrand wrote on 19.02.2017 06:01:
> > On Feb 18, 2017 12:37 PM, "Kai Wasserbäch" 
> > wrote:
> >
> > Hey Jacob,
> > sorry for not spotting this the first time, but I have an additional
> > comment.
> > Please see below.
> >
> > Jacob Lifshay wrote on 18.02.2017 18:48:> This commit improves the
> message
> > by
> > telling them that they could probably
> >> enable DRI3.  More importantly, it includes a little heuristic to check
> >> to see if we're running on AMD or NVIDIA's proprietary X11 drivers and,
> >> if we are, doesn't emit the warning.  This way, users with both a
> discrete
> >> card and Intel graphics don't get the warning when they're just running
> >> on the discrete card.
> >>
> >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99715
> >> Co-authored-by: Jason Ekstrand 
> >> ---
> >>  src/vulkan/wsi/wsi_common_x11.c | 47 ++
> > ++-
> >>  1 file changed, 37 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/src/vulkan/wsi/wsi_common_x11.c
> b/src/vulkan/wsi/wsi_common_
> > x11.c
> >> index 64ba921..b3a017a 100644
> >> --- a/src/vulkan/wsi/wsi_common_x11.c
> >> +++ b/src/vulkan/wsi/wsi_common_x11.c
> >> @@ -49,6 +49,7 @@
> >>  struct wsi_x11_connection {
> >> bool has_dri3;
> >> bool has_present;
> >> +   bool is_proprietary_x11;
> >>  };
> >>
> >>  struct wsi_x11 {
> >> @@ -63,8 +64,8 @@ static struct wsi_x11_connection *
> >>  wsi_x11_connection_create(const VkAllocationCallbacks *alloc,
> >>xcb_connection_t *conn)
> >>  {
> >> -   xcb_query_extension_cookie_t dri3_cookie, pres_cookie;
> >> -   xcb_query_extension_reply_t *dri3_reply, *pres_reply;
> >> +   xcb_query_extension_cookie_t dri3_cookie, pres_cookie, amd_cookie,
> > nv_cookie;
> >> +   xcb_query_extension_reply_t *dri3_reply, *pres_reply, *amd_reply,
> > *nv_reply;
> >>
> >> struct wsi_x11_connection *wsi_conn =
> >>vk_alloc(alloc, sizeof(*wsi_conn), 8,
> >> @@ -75,20 +76,39 @@ wsi_x11_connection_create(const
> VkAllocationCallbacks
> > *alloc,
> >> dri3_cookie = xcb_query_extension(conn, 4, "DRI3");
> >> pres_cookie = xcb_query_extension(conn, 7, "PRESENT");
> >>
> >> +   /* We try to be nice to users and emit a warning if they try to use
> a
> >> +* Vulkan application on a system without DRI3 enabled.  However,
> > this ends
> >> +* up spewing the warning when a user has, for example, both Intel
> >> +* integrated graphics and a discrete card with proprietary driers
> > and are
> >> +* running on the discrete card with the proprietary DDX.  In this
> > case, we
> >> +* really don't want to print the warning because it just confuses
> > users.
> >> +* As a heuristic to detect this case, we check for a couple of
> > proprietary
> >> +* X11 extensions.
> >> +*/
> >> +   amd_cookie = xcb_query_extension(conn, 11, "ATIFGLRXDRI");
> >> +   nv_cookie = xcb_query_extension(conn, 10, "NV-CONTROL");
> >> +
> >> dri3_reply = xcb_query_extension_reply(conn, dri3_cookie, NULL);
> >> pres_reply = xcb_query_extension_reply(conn, pres_cookie, NULL);
> >> -   if (dri3_reply == NULL || pres_reply == NULL) {
> >> +   amd_reply = xcb_query_extension_reply(conn, amd_cookie, NULL);
> >> +   nv_reply = xcb_query_extension_reply(conn, nv_cookie, NULL);
> >> +   if (!dri3_reply || !pres_reply || !amd_reply || !nv_reply) {
> >
> > I don't feel wsi_x11_connection_create should fail if there's no
> amd_reply
> > or
> > nv_reply. That should just lead to unconditionally warning, in case
> there's
> > no
> > DRI3 support.
> >
> >
> > Of there is no reply then we either lost our connection to the X server
> or
> > ran out of memory.  Either of those seem like a valid excuse to fail.
> The
> > chances of successfully connecting to X to create a swapchain at that
> point
> > is pretty close to zero.
>
> Fair enough.
>
> > With that fixed, this patch is
> >   Reviewed-by: Kai Wasserbäch 
> >
> > Cheers,
> > Kai
> >
> >>free(dri3_reply);
> >>free(pres_reply);
> >> +  free(amd_reply);
> >> +  free(nv_reply);
> >>vk_free(alloc, wsi_conn);
> >>return NULL;
> >> }
> >>
> >> wsi_conn->has_dri3 = dri3_reply->present != 0;
> >> wsi_conn->has_present = pres_reply->present != 0;
> >> +   wsi_conn->is_proprietary_x11 = amd_reply->present ||
> > nv_reply->present;
> >>
> >> free(dri3_reply);
> >> free(pres_reply);
> >> +   free(amd_reply);
> >> +   

Re: [Mesa-dev] [PATCH v2] dri: allow 16bit R/GR images to be exported via drm buffers

[Emil Velikov]

On 11 January 2017 at 15:43, Ben Widawsky  wrote:
> On 17-01-05 16:58:56, Rainer Hochecker wrote:
>>
>> From: Rainer Hochecker 
>>
>> This allows eglCreateImageKHR to access P010 surfaces created by vaapi
>>
>> Signed-off-by: Rainer Hochecker 
>
> Acked-by: Ben Widawky 
>
There was a request to get this in -stable. Personally I'm split with
a slight inclination towards rejecting it.
It's very nicely isolated [regression wise] but a new feature after all.

Looking at the kernel parts - just merged in 4.11 which will be out in
~2 months... around the same time mesa 17.1. Which makes me lean even
more towards no.

Do we have (m)any compelling reasons to have this in 17.0 ?

Thanks
Emil
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[Mesa-dev] [PATCH 5/6] Get rid of tgsi_last_channel() wherever possible, rename lasti → last_chan

[Constantine Charlamov]

From: Hi-Angel 

The diff might be confusing: the assignment of last_chan and comparison with
last_chan are actually in different cycles.

Signed-off-by: Constantine Charlamov 
---
 src/gallium/drivers/r600/r600_shader.c | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 972e013aef..3616de572b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2673,7 +2673,7 @@ static int r600_store_tcs_output(struct r600_shader_ctx 
*ctx)
 {
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
const struct tgsi_full_dst_register *dst = >Dst[0];
-   int chan_index, r, lasti;
+   int chan_index, r;
int temp_reg = r600_get_temp(ctx);
struct r600_bytecode_alu alu;
unsigned write_mask = dst->Register.WriteMask;
@@ -2692,8 +2692,7 @@ static int r600_store_tcs_output(struct r600_shader_ctx 
*ctx)
return r;
 
/* LDS write */
-   lasti = tgsi_last_channel(write_mask);
-   for (chan_index = 1; chan_index <= lasti; chan_index++) {
+   for (chan_index = 1; chan_index < TGSI_NUM_CHANNELS; chan_index++) {
if(!TGSI_IS_DST0_CHANNEL_ENABLED(inst, chan_index))
continue;
r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
@@ -4277,10 +4276,11 @@ static int cayman_mul_int_instr(struct r600_shader_ctx 
*ctx)
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
int chan_index, j, k, r;
struct r600_bytecode_alu alu;
-   int lasti = tgsi_last_channel(inst->Dst[0].Register.WriteMask);
+   int last_chan;
int t1 = ctx->temp_reg;
 
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, k) {
+   last_chan = k;
TGSI_FOR_EACH_CHANNEL(chan_index) {
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = ctx->inst_info->op;
@@ -4305,7 +4305,7 @@ static int cayman_mul_int_instr(struct r600_shader_ctx 
*ctx)
alu.src[0].chan = chan_index;
tgsi_dst(ctx, >Dst[0], chan_index, );
alu.dst.write = 1;
-   if (chan_index == lasti)
+   if (chan_index == last_chan)
alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, );
if (r)
@@ -4321,7 +4321,7 @@ static int cayman_mul_double_instr(struct r600_shader_ctx 
*ctx)
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
int chan_index, j, k, r;
struct r600_bytecode_alu alu;
-   int lasti = tgsi_last_channel(inst->Dst[0].Register.WriteMask);
+   int last_chan;
int t1 = ctx->temp_reg;
 
/* t1 would get overwritten below if we actually tried to
@@ -4332,6 +4332,8 @@ static int cayman_mul_double_instr(struct r600_shader_ctx 
*ctx)
k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
 
TGSI_FOR_EACH_CHANNEL (chan_index) {
+   if (TGSI_IS_DST0_CHANNEL_ENABLED(inst, chan_index))
+   last_chan = chan_index;
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = ctx->inst_info->op;
for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
@@ -4354,7 +4356,7 @@ static int cayman_mul_double_instr(struct r600_shader_ctx 
*ctx)
alu.src[0].chan = chan_index;
tgsi_dst(ctx, >Dst[0], chan_index, );
alu.dst.write = 1;
-   if (chan_index == lasti)
+   if (chan_index == last_chan)
alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, );
if (r)
@@ -8795,10 +8797,11 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
int chan_index, j, k, r;
-   int lasti = tgsi_last_channel(inst->Dst[0].Register.WriteMask);
+   int last_chan;
 
/* src0 * src1 */
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
+   last_chan = chan_index;
if (ctx->bc->chip_class == CAYMAN) {
for (j = 0 ; j < 4; j++) {
memset(, 0, sizeof(struct 
r600_bytecode_alu));
@@ -8846,7 +8849,7 @@ static int tgsi_umad(struct r600_shader_ctx *ctx)
alu.src[0].chan = chan_index;
 
r600_bytecode_src([1], >src[2], chan_index);
-   if (chan_index == lasti) {
+   if (chan_index == last_chan) {
alu.last = 1;
}
r = r600_bytecode_add_alu(ctx->bc, );
-- 
2.11.1

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[Mesa-dev] [PATCH 2/6] Rename i→chan_index

[Constantine Charlamov]

From: Hi-Angel 

I might have missed some more opportunities to rename, but oh well.

Signed-off-by: Constantine Charlamov 
---
 src/gallium/drivers/r600/r600_shader.c | 590 -
 1 file changed, 295 insertions(+), 295 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 46aa2c1abd..8562678d0c 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2672,7 +2672,7 @@ static int r600_store_tcs_output(struct r600_shader_ctx 
*ctx)
 {
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
const struct tgsi_full_dst_register *dst = >Dst[0];
-   int i, r, lasti;
+   int chan_index, r, lasti;
int temp_reg = r600_get_temp(ctx);
struct r600_bytecode_alu alu;
unsigned write_mask = dst->Register.WriteMask;
@@ -2692,36 +2692,36 @@ static int r600_store_tcs_output(struct r600_shader_ctx 
*ctx)
 
/* LDS write */
lasti = tgsi_last_instruction(write_mask);
-   for (i = 1; i <= lasti; i++) {
+   for (chan_index = 1; chan_index <= lasti; chan_index++) {
 
-   if (!(write_mask & (1 << i)))
+   if (!(write_mask & (1 << chan_index)))
continue;
r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
-  temp_reg, i,
+  temp_reg, chan_index,
   temp_reg, 0,
-  V_SQ_ALU_SRC_LITERAL, 4 * i);
+  V_SQ_ALU_SRC_LITERAL, 4 * chan_index);
if (r)
return r;
}
 
-   for (i = 0; i <= lasti; i++) {
-   if (!(write_mask & (1 << i)))
+   for (chan_index = 0; chan_index <= lasti; chan_index++) {
+   if (!(write_mask & (1 << chan_index)))
continue;
 
-   if ((i == 0 && ((write_mask & 3) == 3)) ||
-   (i == 2 && ((write_mask & 0xc) == 0xc))) {
+   if ((chan_index == 0 && ((write_mask & 3) == 3)) ||
+   (chan_index == 2 && ((write_mask & 0xc) == 0xc))) {
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = LDS_OP3_LDS_WRITE_REL;
alu.src[0].sel = temp_reg;
-   alu.src[0].chan = i;
+   alu.src[0].chan = chan_index;
 
alu.src[1].sel = dst->Register.Index;
alu.src[1].sel += ctx->file_offset[dst->Register.File];
-   alu.src[1].chan = i;
+   alu.src[1].chan = chan_index;
 
alu.src[2].sel = dst->Register.Index;
alu.src[2].sel += ctx->file_offset[dst->Register.File];
-   alu.src[2].chan = i + 1;
+   alu.src[2].chan = chan_index + 1;
alu.lds_idx = 1;
alu.dst.chan = 0;
alu.last = 1;
@@ -2729,17 +2729,17 @@ static int r600_store_tcs_output(struct r600_shader_ctx 
*ctx)
r = r600_bytecode_add_alu(ctx->bc, );
if (r)
return r;
-   i += 1;
+   chan_index += 1;
continue;
}
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = LDS_OP2_LDS_WRITE;
alu.src[0].sel = temp_reg;
-   alu.src[0].chan = i;
+   alu.src[0].chan = chan_index;
 
alu.src[1].sel = dst->Register.Index;
alu.src[1].sel += ctx->file_offset[dst->Register.File];
-   alu.src[1].chan = i;
+   alu.src[1].chan = chan_index;
 
alu.src[2].sel = V_SQ_ALU_SRC_0;
alu.dst.chan = 0;
@@ -3747,7 +3747,7 @@ static int tgsi_op2_64_params(struct r600_shader_ctx 
*ctx, bool singledest, bool
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
unsigned write_mask = inst->Dst[0].Register.WriteMask;
struct r600_bytecode_alu alu;
-   int i, j, r, lasti = tgsi_last_instruction(write_mask);
+   int chan_index, j, r, lasti = tgsi_last_instruction(write_mask);
int use_tmp = 0;
 
if (singledest) {
@@ -3770,39 +3770,39 @@ static int tgsi_op2_64_params(struct r600_shader_ctx 
*ctx, bool singledest, bool
}
 
lasti = tgsi_last_instruction(write_mask);
-   for (i = 0; i <= lasti; i++) {
+   for (chan_index = 0; chan_index <= lasti; chan_index++) {
 
-   if (!(write_mask & (1 << i)))
+   if (!(write_mask & (1 << chan_index)))
continue;
 
memset(, 0, sizeof(struct r600_bytecode_alu));
 
 

[Mesa-dev] [PATCH 0/6] r600g: r600_shader.c small cleanups

[Constantine Charlamov]

Initially I was trying to implement for r600 optimization like in the 
d633e23192ef17207f4a6acd3009da3126aab395 commit for radeonsi, but failed 
because I need to learn some more about GPUs internals. For another time. 
Anyway, accidentally it turned into a small cleanup of r600_shader.c, here it 
is.

Hi-Angel (6):
  Get rid of trailing whitespace (trivial)
  Rename i→chan_index
  Replace bit-shifts and cycles with helpers from tgsi_exec.h
  Rename tgsi_last_instruction → tgsi_last_channel
  Get rid of tgsi_last_channel() wherever possible, rename lasti →
last_chan
  Remove redudant comparisons

 src/gallium/drivers/r600/r600_shader.c | 815 ++---
 1 file changed, 333 insertions(+), 482 deletions(-)

-- 
2.11.1

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Re: [Mesa-dev] [PATCH] radv/ac: enable loop unrolling. (v2)

[Michael Schellenberger Costa]

Hi Dave,

-Ursprüngliche Nachricht-
Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag von 
Dave Airlie
Gesendet: Freitag, 24. Februar 2017 04:59
An: mesa-dev@lists.freedesktop.org
Betreff: [Mesa-dev] [PATCH] radv/ac: enable loop unrolling. (v2)

From: Dave Airlie 

This enables LLVM loop unrolling.

v2: limit unroll count to 32, don't fully unroll. (arsenm)

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_llvm_helper.cpp | 22 ++
 src/amd/common/ac_llvm_util.h |  1 +
 src/amd/common/ac_nir_to_llvm.c   | 26 --
 3 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_llvm_helper.cpp 
b/src/amd/common/ac_llvm_helper.cpp
index 594339e..85b0cbf 100644
--- a/src/amd/common/ac_llvm_helper.cpp
+++ b/src/amd/common/ac_llvm_helper.cpp
@@ -36,7 +36,9 @@
 #include 
 #include 
 #include 
+#include 
 
+using namespace llvm;

If you have to use the namespace you should  adopt the other lines below too

 void ac_add_attr_dereferenceable(LLVMValueRef val, uint64_t bytes)  {
llvm::Argument *A = llvm::unwrap(val);
@@ -53,3 +55,23 @@ bool ac_is_sgpr_param(LLVMValueRef arg)
return AS.hasAttribute(ArgNo + 1, llvm::Attribute::ByVal) ||
   AS.hasAttribute(ArgNo + 1, llvm::Attribute::InReg);  }
   
--Michael

+
+// MetadataAsValue uses a canonical format which strips the actual 
+MDNode for // MDNode with just a single constant value, storing just a 
+ConstantAsMetadata // This undoes this canonicalization, reconstructing the 
MDNode.
+static MDNode *extractMDNode(MetadataAsValue *MAV) {
+   Metadata *MD = MAV->getMetadata();
+   assert((isa(MD) || isa(MD)) &&
+  "Expected a metadata node or a canonicalized constant");
+
+   if (MDNode *N = dyn_cast(MD))
+   return N;
+   assert(0);
+   return MDNode::get(MAV->getContext(), MD); }
+
+void ac_metadata_point_op0_to_itself(LLVMValueRef v) {
+   MDNode *node = extractMDNode(unwrap(v));
+   node->replaceOperandWith(0, node);
+}
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h 
index 1f37a12..0d6c53c 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -48,6 +48,7 @@ LLVMTargetMachineRef ac_create_target_machine(enum 
radeon_family family, bool su
 
 void ac_add_attr_dereferenceable(LLVMValueRef val, uint64_t bytes);  bool 
ac_is_sgpr_param(LLVMValueRef param);
+void ac_metadata_point_op0_to_itself(LLVMValueRef v);
 
 void
 ac_add_function_attr(LLVMValueRef function, diff --git 
a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 
9778581..d7a9a7b 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3950,6 +3950,23 @@ static void visit_if(struct nir_to_llvm_context *ctx, 
nir_if *if_stmt)
LLVMPositionBuilderAtEnd(ctx->builder, merge_block);  }
 
+static void set_unroll_metadata(struct nir_to_llvm_context *ctx,
+  LLVMValueRef br)
+{
+   unsigned kind = LLVMGetMDKindIDInContext(ctx->context, "llvm.loop", 9);
+   LLVMValueRef md_unroll;
+   LLVMValueRef part_arg = LLVMMDStringInContext(ctx->context, 
"llvm.loop.unroll.count", 22);
+   LLVMValueRef count_arg = LLVMConstInt(ctx->i32, 32, false);
+   LLVMValueRef args[2] = {part_arg, count_arg};
+   LLVMValueRef count = LLVMMDNodeInContext(ctx->context, args, 2);
+
+   LLVMValueRef md_args[] = {NULL, count};
+   md_unroll = LLVMMDNodeInContext(ctx->context, md_args, 2);
+   ac_metadata_point_op0_to_itself(md_unroll);
+
+   LLVMSetMetadata(br, kind, md_unroll);
+}
+
 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)  {
LLVMBasicBlockRef continue_parent = ctx->continue_block; @@ -3964,8 
+3981,10 @@ static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop 
*loop)
LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
visit_cf_list(ctx, >body);
 
-   if (LLVMGetInsertBlock(ctx->builder))
-   LLVMBuildBr(ctx->builder, ctx->continue_block);
+   if (LLVMGetInsertBlock(ctx->builder)) {
+   LLVMValueRef loop = LLVMBuildBr(ctx->builder, 
ctx->continue_block);
+   set_unroll_metadata(ctx, loop);
+   }
LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
 
ctx->continue_block = continue_parent; @@ -4827,10 +4846,13 @@ static 
void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
 
/* Add some optimization passes */
LLVMAddScalarReplAggregatesPass(passmgr);
+   LLVMAddLoopRotatePass(passmgr);
LLVMAddLICMPass(passmgr);
LLVMAddAggressiveDCEPass(passmgr);
LLVMAddCFGSimplificationPass(passmgr);
LLVMAddInstructionCombiningPass(passmgr);
+   LLVMAddIndVarSimplifyPass(passmgr);
+   

Re: [Mesa-dev] [PATCH 8/8] r600/radeonsi: enableglsl/tgsion-diskcache

[Tobias Droste]

Mit freundlichen Grüßen
Am Freitag, 24. Februar 2017, 11:25:24 CET schrieb Marc Dietrich:
> Am Donnerstag, 23. Februar 2017, 11:50:07 CET schrieb Emil Velikov:
> > On 23 February 2017 at 10:20, Marc Dietrich  wrote:
> > > Am Donnerstag, 23. Februar 2017, 10:54:39 CET schrieb Michel Dänzer:
> > >> On 23/02/17 06:39 PM, Marc Dietrich wrote:
> > >> > Am Donnerstag, 23. Februar 2017, 04:10:23 CET schrieb Timothy Arceri:
> > >> >> I've pushed a fix for building with an old version of llvm.
> > >> >> Hopefully
> > >> >> this will resolve your problem.
> > >> > 
> > >> > I have a pretty current version of llvm (3.9.1), so the problem is
> > >> > not
> > >> > fixed by this patch :-) From the fact that it works for you and
> > >> > others,
> > >> > I
> > >> > guess it must be some distro packaging problem (suse thumbleweed
> > >> > here).
> > >> > llvm is using shared libs.
> > >> 
> > >> FWIW, this is broken packaging on SUSE's part — they need to build
> > >> LLVM
> > >> with LLVM_BUILD_LLVM_DYLIB=ON instead of BUILD_SHARED_LIBS=ON. The
> > >> latter is an unsupported developer only option. Please report this to
> > >> them.
> > > 
> > > does this mean that multiple shared libs are not supported by mesa? I
> > > read
> > > from the llvm website, that
> > > 
> > > "BUILD_SHARED_LIBS is only recommended for use by LLVM developers. If
> > > you
> > > want to build LLVM as a shared library, you should use the
> > > LLVM_BUILD_LLVM_DYLIB option."
> > > 
> > > I wonder why mesa tries to gather a list of required libs then (for
> > > static
> > > linking maybe?)
> > 
> > Yes, collecting the required libs is for static linking. Care to send
> > a patch which moves it within the correct section - 20-30 lines
> > further down ;-)
> 
> I can't test with static libs, but this patch here fixes it for me (tm)
> 
> --- a/configure.ac
> +++ b/configure.ac
> @@ -2297,6 +2297,11 @@ if test -n "$with_gallium_drivers"; then
>  HAVE_GALLIUM_R600=yes
>  PKG_CHECK_MODULES([RADEON], [libdrm >= $LIBDRM_RADEON_REQUIRED
> libdrm_radeon >= $LIBDRM_RADEON_REQUIRED])
>  require_libdrm "r600"
> +if test "x$enable_llvm" = xyes; then
> +radeon_llvm_check $LLVM_REQUIRED_R600 "r600"
> +
> +llvm_add_component "amdgpuinfo" "r600"
> +fi
>  if test "x$enable_opencl" = xyes; then
>  radeon_llvm_check $LLVM_REQUIRED_R600 "r600"

Could you put the "llvm_add_component "amdgpuinfo" "r600"" line into the 
function "radeon_llvm_check()" and send the result as a git patch?

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[Mesa-dev] [Bug 99959] egl-entrypoint-check fails

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99959

Eric Engestrom  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #3 from Eric Engestrom  ---
Emil is right, this was caused by changing bash to sh at the last minute.

This is fixed by:

commit a1e5e55989c70c5f58bdd8a797f9a035f068f580
Author: Eric Engestrom 
Date:   Sun Feb 26 13:35:25 2017 +

check: mark two tests are requiring bash

Requirement was removed just before pushing, but it's actually needed
for heredocs (`<<<`).

Signed-off-by: Eric Engestrom 

(And I just realized I forgot the Fixes: tag... oh well :)

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Re: [Mesa-dev] [PATCH] glx/tests: Fix bash-specific code in dispatch-index-check

[Eric Engestrom]

On Friday, 2017-02-24 22:03:36 -0600, Aaron Watry wrote:
> Using <<< for variable redirection is bash-specific behavior.
> Ubuntu redirects sh -> dash, so this was erroring out.
> 
> Also, the initial error that led me to this was that srcdir is null when 
> running make check
> so I just copied something similar to what the optimization-test script does.
> ---
>  src/glx/tests/dispatch-index-check | 21 ++---
>  1 file changed, 14 insertions(+), 7 deletions(-)
> 
> diff --git a/src/glx/tests/dispatch-index-check 
> b/src/glx/tests/dispatch-index-check
> index 78464b8..ee1b9ee 100755
> --- a/src/glx/tests/dispatch-index-check
> +++ b/src/glx/tests/dispatch-index-check
> @@ -1,24 +1,31 @@
>  #!/bin/sh
>  
> +if [ -z "$srcdir" ]; then
> +   scriptdir=`dirname "$0"`
> +else
> +   scriptdir=$srcdir
> +fi
> +
> +
>  # extract enum definition
>  dispatch_list=$(sed '/__GLXdispatchIndex/,/__GLXdispatchIndex/!d' \
> -  "$srcdir"/../g_glxglvnddispatchindices.h)
> +  "$scriptdir"/../g_glxglvnddispatchindices.h)

No need to create a new var that just copies the old one :)

>  
>  # extract values inside of enum
> -dispatch_list=$(sed '1d;$d' <<< "$dispatch_list")
> +dispatch_list=$(printf "$dispatch_list" | sed '1d;$d')

Never use a variable you have no control over as the format string for
printf! Use `printf '%s' "$var"` instead.

I just pushed a1e5e55989 ("check: mark two tests are requiring bash")
which fixes this by simply asking for bash in the shebang, which was
what my original patch did, and was changed just before pushing because
of a review comment that turned out to be wrong :)

Cheers,
  Eric

>  
>  # remove indentation
> -dispatch_list=$(sed 's/^\s\+//' <<< "$dispatch_list")
> +dispatch_list=$(printf "$dispatch_list" | sed 's/^\s\+//')
>  
>  # extract function names
> -dispatch_list=$(sed 's/DI_//;s/,//' <<< "$dispatch_list")
> +dispatch_list=$(printf "$dispatch_list" | sed 's/DI_//;s/,//')
>  
>  # same for commented functions, we want to keep them sorted too
> -dispatch_list=$(sed 's#// ##;s/ implemented by [a-z]\+//' <<< 
> "$dispatch_list")
> +dispatch_list=$(printf "$dispatch_list" | sed 's#// ##;s/ implemented by 
> [a-z]\+//')
>  
>  # remove LAST_INDEX, as it will not be in alphabetical order
> -dispatch_list=$(sed '/LAST_INDEX/d' <<< "$dispatch_list")
> +dispatch_list=$(printf "$dispatch_list" | sed '/LAST_INDEX/d')
>  
> -sorted=$(LC_ALL=C sort <<< "$dispatch_list")
> +sorted=$(LC_ALL=C printf "$dispatch_list" | sort)
>  
>  test "$dispatch_list" = "$sorted"
> -- 
> 2.9.3
> 
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[Mesa-dev] [Bug 73777] xf86drm.h:40:17: error: drm.h: No such file or directory

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=73777

--- Comment #5 from Joaquín Montero Salinas  ---
(In reply to Emil Velikov from comment #4)
> Joaquín please don't reopen 2+ year old fixed bugs but clearly describe your
> issue in a new one.
> 
> In there mention the following - which mesa version you're building, the
> configure (scons) line and include a snippet of the error message.
> 
> Thanks

Yeah, sorry about that. I didn't notice this bug was filed under Mesa, so I
thought filing a new bug would be making a duplicate.

Thanks for the heads-up, Emil.

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[Mesa-dev] [Bug 99856] OpenCL Hello world returns "unsupported call to function get_local_size"

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99856

--- Comment #15 from Jan Vesely  ---
Created attachment 129929
  --> https://bugs.freedesktop.org/attachment.cgi?id=129929=edit
size_t is 32bit in mesa3d

building libclc (commit 520743) with this patch applied should produce a
working library

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[Mesa-dev] [Bug 73777] xf86drm.h:40:17: error: drm.h: No such file or directory

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=73777

Emil Velikov  changed:

   What|Removed |Added

 Status|REOPENED|RESOLVED
 Resolution|--- |FIXED

--- Comment #4 from Emil Velikov  ---
Joaquín please don't reopen 2+ year old fixed bugs but clearly describe your
issue in a new one.

In there mention the following - which mesa version you're building, the
configure (scons) line and include a snippet of the error message.

Thanks

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Re: [Mesa-dev] [PATCH 02/24] gallivm, ac: add writeonly and inaccessiblememonly attributes

[Marek Olšák]

On Feb 26, 2017 1:09 AM, "Jan Vesely"  wrote:

On Sun, 2017-02-26 at 00:58 +0100, Marek Olšák wrote:
> From: Marek Olšák 
>
> ---
>  src/amd/common/ac_llvm_util.c   | 2 ++
>  src/amd/common/ac_llvm_util.h   | 2 ++
>  src/gallium/auxiliary/gallivm/lp_bld_intr.c | 2 ++
>  src/gallium/auxiliary/gallivm/lp_bld_intr.h | 2 ++
>  4 files changed, 8 insertions(+)
>
> diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
> index fb525dd..3cc06d4 100644
> --- a/src/amd/common/ac_llvm_util.c
> +++ b/src/amd/common/ac_llvm_util.c
> @@ -165,20 +165,22 @@ static LLVMAttribute ac_attr_to_llvm_attr(enum
ac_func_attr attr)
>  static const char *attr_to_str(enum ac_func_attr attr)
>  {
> switch (attr) {
> case AC_FUNC_ATTR_ALWAYSINLINE: return "alwaysinline";
> case AC_FUNC_ATTR_BYVAL: return "byval";
> case AC_FUNC_ATTR_INREG: return "inreg";
> case AC_FUNC_ATTR_NOALIAS: return "noalias";
> case AC_FUNC_ATTR_NOUNWIND: return "nounwind";
> case AC_FUNC_ATTR_READNONE: return "readnone";
> case AC_FUNC_ATTR_READONLY: return "readonly";
> +   case AC_FUNC_ATTR_WRITEONLY: return "writeonly";
> +   case AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY: return "inaccessiblememonly";

does this not give "error: duplicate case value" when compiled with
LLVM-3.9 ?


This code is not built with LLVM 3.9.

Marek


Jan

> default:
>  fprintf(stderr, "Unhandled function attribute: %x\n", attr);
>  return 0;
> }
>  }
>
>  #endif
>
>  static void
>  ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
> diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
> index 4fe4ab4..1cdee2e 100644
> --- a/src/amd/common/ac_llvm_util.h
> +++ b/src/amd/common/ac_llvm_util.h
> @@ -34,20 +34,22 @@ extern "C" {
>  #endif
>
>  enum ac_func_attr {
>   AC_FUNC_ATTR_ALWAYSINLINE = (1 << 0),
>   AC_FUNC_ATTR_BYVAL= (1 << 1),
>   AC_FUNC_ATTR_INREG= (1 << 2),
>   AC_FUNC_ATTR_NOALIAS  = (1 << 3),
>   AC_FUNC_ATTR_NOUNWIND = (1 << 4),
>   AC_FUNC_ATTR_READNONE = (1 << 5),
>   AC_FUNC_ATTR_READONLY = (1 << 6),
> + AC_FUNC_ATTR_WRITEONLY= HAVE_LLVM >= 0x0400 ? (1 << 7) : 0,
> + AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY = HAVE_LLVM >= 0x0400 ? (1 << 8)
: 0,
>
>   /* Legacy intrinsic that needs attributes on function declarations
>* and they must match the internal LLVM definition exactly,
otherwise
>* intrinsic selection fails.
>*/
>   AC_FUNC_ATTR_LEGACY   = (1u << 31),
>  };
>
>  LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
bool supports_spill);
>
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_intr.c
b/src/gallium/auxiliary/gallivm/lp_bld_intr.c
> index 1b50e68..0be57c9 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_intr.c
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_intr.c
> @@ -143,20 +143,22 @@ static LLVMAttribute lp_attr_to_llvm_attr(enum
lp_func_attr attr)
>  static const char *attr_to_str(enum lp_func_attr attr)
>  {
> switch (attr) {
> case LP_FUNC_ATTR_ALWAYSINLINE: return "alwaysinline";
> case LP_FUNC_ATTR_BYVAL: return "byval";
> case LP_FUNC_ATTR_INREG: return "inreg";
> case LP_FUNC_ATTR_NOALIAS: return "noalias";
> case LP_FUNC_ATTR_NOUNWIND: return "nounwind";
> case LP_FUNC_ATTR_READNONE: return "readnone";
> case LP_FUNC_ATTR_READONLY: return "readonly";
> +   case LP_FUNC_ATTR_WRITEONLY: return "writeonly";
> +   case LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY: return "inaccessiblememonly";
> default:
>_debug_printf("Unhandled function attribute: %x\n", attr);
>return 0;
> }
>  }
>
>  #endif
>
>  void
>  lp_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_intr.h
b/src/gallium/auxiliary/gallivm/lp_bld_intr.h
> index d279911..4d14725 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_intr.h
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_intr.h
> @@ -47,20 +47,22 @@
>  #define LP_MAX_FUNC_ARGS 32
>
>  enum lp_func_attr {
> LP_FUNC_ATTR_ALWAYSINLINE = (1 << 0),
> LP_FUNC_ATTR_BYVAL= (1 << 1),
> LP_FUNC_ATTR_INREG= (1 << 2),
> LP_FUNC_ATTR_NOALIAS  = (1 << 3),
> LP_FUNC_ATTR_NOUNWIND = (1 << 4),
> LP_FUNC_ATTR_READNONE = (1 << 5),
> LP_FUNC_ATTR_READONLY = (1 << 6),
> +   LP_FUNC_ATTR_WRITEONLY= HAVE_LLVM >= 0x0400 ? (1 << 7) : 0,
> +   LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY = HAVE_LLVM >= 0x0400 ? (1 << 8) :
0,
>
> /* Legacy intrinsic that needs attributes on function declarations
>  * and they must match the internal LLVM definition exactly, otherwise
>  * intrinsic selection fails.
>  */
> LP_FUNC_ATTR_LEGACY   = (1u << 31),
>  };
>
>  void
>  lp_format_intrinsic(char *name,
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Re: [Mesa-dev] [PATCH] vulkan/wsi: Improve the DRI3 error message

[Kai Wasserbäch]

Not from my side. But I can't commit the patch for you. Jason?

Jacob Lifshay wrote on 26.02.2017 03:17:
> Just to double check, is there anything else I need to do to have this
> patch committed?
> Jacob Lifshay
> 
> On Feb 19, 2017 02:08, "Kai Wasserbäch"  wrote:
> 
>> Jason Ekstrand wrote on 19.02.2017 06:01:
>>> On Feb 18, 2017 12:37 PM, "Kai Wasserbäch" 
>>> wrote:
>>>
>>> Hey Jacob,
>>> sorry for not spotting this the first time, but I have an additional
>>> comment.
>>> Please see below.
>>>
>>> Jacob Lifshay wrote on 18.02.2017 18:48:> This commit improves the
>> message
>>> by
>>> telling them that they could probably
 enable DRI3.  More importantly, it includes a little heuristic to check
 to see if we're running on AMD or NVIDIA's proprietary X11 drivers and,
 if we are, doesn't emit the warning.  This way, users with both a
>> discrete
 card and Intel graphics don't get the warning when they're just running
 on the discrete card.

 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99715
 Co-authored-by: Jason Ekstrand 
 ---
  src/vulkan/wsi/wsi_common_x11.c | 47 ++
>>> ++-
  1 file changed, 37 insertions(+), 10 deletions(-)

 diff --git a/src/vulkan/wsi/wsi_common_x11.c
>> b/src/vulkan/wsi/wsi_common_
>>> x11.c
 index 64ba921..b3a017a 100644
 --- a/src/vulkan/wsi/wsi_common_x11.c
 +++ b/src/vulkan/wsi/wsi_common_x11.c
 @@ -49,6 +49,7 @@
  struct wsi_x11_connection {
 bool has_dri3;
 bool has_present;
 +   bool is_proprietary_x11;
  };

  struct wsi_x11 {
 @@ -63,8 +64,8 @@ static struct wsi_x11_connection *
  wsi_x11_connection_create(const VkAllocationCallbacks *alloc,
xcb_connection_t *conn)
  {
 -   xcb_query_extension_cookie_t dri3_cookie, pres_cookie;
 -   xcb_query_extension_reply_t *dri3_reply, *pres_reply;
 +   xcb_query_extension_cookie_t dri3_cookie, pres_cookie, amd_cookie,
>>> nv_cookie;
 +   xcb_query_extension_reply_t *dri3_reply, *pres_reply, *amd_reply,
>>> *nv_reply;

 struct wsi_x11_connection *wsi_conn =
vk_alloc(alloc, sizeof(*wsi_conn), 8,
 @@ -75,20 +76,39 @@ wsi_x11_connection_create(const
>> VkAllocationCallbacks
>>> *alloc,
 dri3_cookie = xcb_query_extension(conn, 4, "DRI3");
 pres_cookie = xcb_query_extension(conn, 7, "PRESENT");

 +   /* We try to be nice to users and emit a warning if they try to use
>> a
 +* Vulkan application on a system without DRI3 enabled.  However,
>>> this ends
 +* up spewing the warning when a user has, for example, both Intel
 +* integrated graphics and a discrete card with proprietary driers
>>> and are
 +* running on the discrete card with the proprietary DDX.  In this
>>> case, we
 +* really don't want to print the warning because it just confuses
>>> users.
 +* As a heuristic to detect this case, we check for a couple of
>>> proprietary
 +* X11 extensions.
 +*/
 +   amd_cookie = xcb_query_extension(conn, 11, "ATIFGLRXDRI");
 +   nv_cookie = xcb_query_extension(conn, 10, "NV-CONTROL");
 +
 dri3_reply = xcb_query_extension_reply(conn, dri3_cookie, NULL);
 pres_reply = xcb_query_extension_reply(conn, pres_cookie, NULL);
 -   if (dri3_reply == NULL || pres_reply == NULL) {
 +   amd_reply = xcb_query_extension_reply(conn, amd_cookie, NULL);
 +   nv_reply = xcb_query_extension_reply(conn, nv_cookie, NULL);
 +   if (!dri3_reply || !pres_reply || !amd_reply || !nv_reply) {
>>>
>>> I don't feel wsi_x11_connection_create should fail if there's no
>> amd_reply
>>> or
>>> nv_reply. That should just lead to unconditionally warning, in case
>> there's
>>> no
>>> DRI3 support.
>>>
>>>
>>> Of there is no reply then we either lost our connection to the X server
>> or
>>> ran out of memory.  Either of those seem like a valid excuse to fail.
>> The
>>> chances of successfully connecting to X to create a swapchain at that
>> point
>>> is pretty close to zero.
>>
>> Fair enough.
>>
>>> With that fixed, this patch is
>>>   Reviewed-by: Kai Wasserbäch 
>>>
>>> Cheers,
>>> Kai
>>>
free(dri3_reply);
free(pres_reply);
 +  free(amd_reply);
 +  free(nv_reply);
vk_free(alloc, wsi_conn);
return NULL;
 }

 wsi_conn->has_dri3 = dri3_reply->present != 0;
 wsi_conn->has_present = pres_reply->present != 0;
 +   wsi_conn->is_proprietary_x11 = amd_reply->present ||
>>> nv_reply->present;

 free(dri3_reply);
 free(pres_reply);
 +   free(amd_reply);
 +   free(nv_reply);

 return wsi_conn;
  }
 @@ -100,6 +120,18 @@ wsi_x11_connection_destroy(const
>>>