Re: [Mesa-dev] [PATCH] st: Add cubeMapFace parameter to st_finalize_texture.

2017-04-01 Thread Nicolai Hähnle 

Pushed.

On 29.03.2017 21:58, Marek Olšák wrote:

I'm OK with this patch.

Marek

On Wed, Mar 29, 2017 at 12:57 PM, Nicolai Hähnle  wrote:

Hi Michal,

thanks for the patch. That piglit test actually fails on radeonsi as well.


On 28.03.2017 22:39, Michal Srb wrote:


st_finalize_texture always accesses image at face 0, but it may not be set
if we are working with cubemap that had other face set.

This fixes crash in piglit
same-attachment-glFramebufferTexture2D-GL_DEPTH_STENCIL_ATTACHMENT.



Please make sure commit messages are wrapped to <75 characters.

Also:

Cc: mesa-sta...@lists.freedesktop.org



---
Hi, this is my attempt to fix crash in piglit test
same-attachment-glFramebufferTexture2D-GL_DEPTH_STENCIL_ATTACHMENT ran with
LIBGL_ALWAYS_INDIRECT=1.
I am not sure if it is the right approach. From what I found online
rendering into a face of a cube texture that doesn't have all faces set
would be invalid, but the test passes with other drivers, so maybe it's ok.
This makes it pass with software rendering as well.



I actually don't see anything in the spec that would require texture
completeness. That makes sense, since rendering into one image of a texture
doesn't imply using sampler state. So allowing the test to pass is good.

The flip-side is that this means calling st_finalize_texture at all may not
be the right thing to do in the FBO code (except perhaps as an opportunistic
optimization). After all, we could have a messed up situation where there
are incompatible mip level in a texture, and we render to one of them
anyway.

Cleaning that up would be quite involved. I think this fix is fine for now,
since it does improve the situation:

Reviewed-by: Nicolai Hähnle 

Let's see if there are any other opinions...

Cheers,
Nicolai





 src/gallium/state_trackers/dri/dri2.c| 2 +-
 src/mesa/state_tracker/st_atom_image.c   | 2 +-
 src/mesa/state_tracker/st_atom_texture.c | 2 +-
 src/mesa/state_tracker/st_cb_fbo.c   | 2 +-
 src/mesa/state_tracker/st_cb_texture.c   | 5 +++--
 src/mesa/state_tracker/st_cb_texture.h   | 3 ++-
 src/mesa/state_tracker/st_gen_mipmap.c   | 2 +-
 7 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/gallium/state_trackers/dri/dri2.c
b/src/gallium/state_trackers/dri/dri2.c
index b50e096..ed6004f 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -1808,7 +1808,7 @@ dri2_interop_export_object(__DRIcontext *_ctx,
  return MESA_GLINTEROP_INVALID_MIP_LEVEL;
   }

-  if (!st_finalize_texture(ctx, st->pipe, obj)) {
+  if (!st_finalize_texture(ctx, st->pipe, obj, 0)) {
  mtx_unlock(&ctx->Shared->Mutex);
  return MESA_GLINTEROP_OUT_OF_RESOURCES;
   }
diff --git a/src/mesa/state_tracker/st_atom_image.c
b/src/mesa/state_tracker/st_atom_image.c
index 5dd2cd6..4101552 100644
--- a/src/mesa/state_tracker/st_atom_image.c
+++ b/src/mesa/state_tracker/st_atom_image.c
@@ -64,7 +64,7 @@ st_bind_images(struct st_context *st, struct gl_program
*prog,
   struct pipe_image_view *img = &images[i];

   if (!_mesa_is_image_unit_valid(st->ctx, u) ||
-  !st_finalize_texture(st->ctx, st->pipe, u->TexObj) ||
+  !st_finalize_texture(st->ctx, st->pipe, u->TexObj, 0) ||
   !stObj->pt) {
  memset(img, 0, sizeof(*img));
  continue;
diff --git a/src/mesa/state_tracker/st_atom_texture.c
b/src/mesa/state_tracker/st_atom_texture.c
index 92023e0..5b481ec 100644
--- a/src/mesa/state_tracker/st_atom_texture.c
+++ b/src/mesa/state_tracker/st_atom_texture.c
@@ -73,7 +73,7 @@ update_single_texture(struct st_context *st,
}
stObj = st_texture_object(texObj);

-   retval = st_finalize_texture(ctx, st->pipe, texObj);
+   retval = st_finalize_texture(ctx, st->pipe, texObj, 0);
if (!retval) {
   /* out of mem */
   return GL_FALSE;
diff --git a/src/mesa/state_tracker/st_cb_fbo.c
b/src/mesa/state_tracker/st_cb_fbo.c
index 78433bf..dce4239 100644
--- a/src/mesa/state_tracker/st_cb_fbo.c
+++ b/src/mesa/state_tracker/st_cb_fbo.c
@@ -488,7 +488,7 @@ st_render_texture(struct gl_context *ctx,
struct st_renderbuffer *strb = st_renderbuffer(rb);
struct pipe_resource *pt;

-   if (!st_finalize_texture(ctx, pipe, att->Texture))
+   if (!st_finalize_texture(ctx, pipe, att->Texture, att->CubeMapFace))
   return;

pt = st_get_texobj_resource(att->Texture);
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index bc6f108..1b486d7 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2434,7 +2434,8 @@ copy_image_data_to_texture(struct st_context *st,
 GLboolean
 st_finalize_texture(struct gl_context *ctx,
struct pipe_context *pipe,
-   struct gl_texture_object *tObj)
+   struct gl_texture_object *tObj,
+   GLuint cubeMapFace)
 {
struct st_context *st = st_context(ctx);
struct st_texture_o

Re: [Mesa-dev] [PATCH v3 1/2] st/mesa: add st_convert_image()

2017-04-01 Thread Nicolai Hähnle 

On 31.03.2017 12:48, Samuel Pitoiset wrote:

Should be used by the state tracker when glGetImageHandleARB()
is called in order to create a pipe_image_view template.

v3: - move the comment to *.c
v2: - make 'st' const
- describe the function

Signed-off-by: Samuel Pitoiset 


Reviewed-by: Nicolai Hähnle 



---
 src/mesa/state_tracker/st_atom_image.c | 106 ++---
 src/mesa/state_tracker/st_texture.h|   4 ++
 2 files changed, 63 insertions(+), 47 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_image.c 
b/src/mesa/state_tracker/st_atom_image.c
index 5dd2cd64f9..6295e8d2cd 100644
--- a/src/mesa/state_tracker/st_atom_image.c
+++ b/src/mesa/state_tracker/st_atom_image.c
@@ -44,6 +44,64 @@
 #include "st_program.h"
 #include "st_format.h"

+/**
+ * Convert a gl_image_unit object to a pipe_image_view object.
+ */
+void
+st_convert_image(const struct st_context *st, const struct gl_image_unit *u,
+ struct pipe_image_view *img)
+{
+   struct st_texture_object *stObj = st_texture_object(u->TexObj);
+
+   img->resource = stObj->pt;
+   img->format = st_mesa_format_to_pipe_format(st, u->_ActualFormat);
+
+   switch (u->Access) {
+   case GL_READ_ONLY:
+  img->access = PIPE_IMAGE_ACCESS_READ;
+  break;
+   case GL_WRITE_ONLY:
+  img->access = PIPE_IMAGE_ACCESS_WRITE;
+  break;
+   case GL_READ_WRITE:
+  img->access = PIPE_IMAGE_ACCESS_READ_WRITE;
+  break;
+   default:
+  unreachable("bad gl_image_unit::Access");
+   }
+
+   if (stObj->pt->target == PIPE_BUFFER) {
+  unsigned base, size;
+
+  base = stObj->base.BufferOffset;
+  assert(base < stObj->pt->width0);
+  size = MIN2(stObj->pt->width0 - base, (unsigned)stObj->base.BufferSize);
+
+  img->u.buf.offset = base;
+  img->u.buf.size = size;
+   } else {
+  img->u.tex.level = u->Level + stObj->base.MinLevel;
+  if (stObj->pt->target == PIPE_TEXTURE_3D) {
+ if (u->Layered) {
+img->u.tex.first_layer = 0;
+img->u.tex.last_layer = u_minify(stObj->pt->depth0, 
img->u.tex.level) - 1;
+ } else {
+img->u.tex.first_layer = u->_Layer;
+img->u.tex.last_layer = u->_Layer;
+ }
+  } else {
+ img->u.tex.first_layer = u->_Layer + stObj->base.MinLayer;
+ img->u.tex.last_layer = u->_Layer + stObj->base.MinLayer;
+ if (u->Layered && img->resource->array_size > 1) {
+if (stObj->base.Immutable)
+   img->u.tex.last_layer += stObj->base.NumLayers - 1;
+else
+   img->u.tex.last_layer += img->resource->array_size - 1;
+ }
+  }
+   }
+}
+
 static void
 st_bind_images(struct st_context *st, struct gl_program *prog,
enum pipe_shader_type shader_type)
@@ -70,53 +128,7 @@ st_bind_images(struct st_context *st, struct gl_program 
*prog,
  continue;
   }

-  img->resource = stObj->pt;
-  img->format = st_mesa_format_to_pipe_format(st, u->_ActualFormat);
-
-  switch (u->Access) {
-  case GL_READ_ONLY:
- img->access = PIPE_IMAGE_ACCESS_READ;
- break;
-  case GL_WRITE_ONLY:
- img->access = PIPE_IMAGE_ACCESS_WRITE;
- break;
-  case GL_READ_WRITE:
- img->access = PIPE_IMAGE_ACCESS_READ_WRITE;
- break;
-  default:
- unreachable("bad gl_image_unit::Access");
-  }
-
-  if (stObj->pt->target == PIPE_BUFFER) {
- unsigned base, size;
-
- base = stObj->base.BufferOffset;
- assert(base < stObj->pt->width0);
- size = MIN2(stObj->pt->width0 - base, 
(unsigned)stObj->base.BufferSize);
-
- img->u.buf.offset = base;
- img->u.buf.size = size;
-  } else {
- img->u.tex.level = u->Level + stObj->base.MinLevel;
- if (stObj->pt->target == PIPE_TEXTURE_3D) {
-if (u->Layered) {
-   img->u.tex.first_layer = 0;
-   img->u.tex.last_layer = u_minify(stObj->pt->depth0, 
img->u.tex.level) - 1;
-} else {
-   img->u.tex.first_layer = u->_Layer;
-   img->u.tex.last_layer = u->_Layer;
-}
- } else {
-img->u.tex.first_layer = u->_Layer + stObj->base.MinLayer;
-img->u.tex.last_layer = u->_Layer + stObj->base.MinLayer;
-if (u->Layered && img->resource->array_size > 1) {
-   if (stObj->base.Immutable)
-  img->u.tex.last_layer += stObj->base.NumLayers - 1;
-   else
-  img->u.tex.last_layer += img->resource->array_size - 1;
-}
- }
-  }
+  st_convert_image(st, u, img);
}
cso_set_shader_images(st->cso_context, shader_type, 0,
  prog->info.num_images, images);
diff --git a/src/mesa/state_tracker/st_texture.h 
b/src/mesa/state_tracker/st_texture.h
index 0ce7989562..00c30f06cf 100644
--- a/src/mesa/state_tracker/st_texture.h
+++ b/src/mesa/state_tr

Re: [Mesa-dev] [PATCH V3] mesa: disable glthread when DEBUG_OUTPUT_SYNCHRONOUS is enabled

2017-04-01 Thread Nicolai Hähnle 

On 31.03.2017 10:28, Timothy Arceri wrote:

We could re-enable it also but I haven't tested that yet, and I'm
not sure we care much anyway.

V2: don't disable it from with the call itself. We need a custom
marshalling function or we get stuck waiting for thread to
finish.

V3: tidy up redundant code copied from generated verion.


Reviewed-by: Nicolai Hähnle 



---
 src/mapi/glapi/gen/gl_API.xml |  2 +-
 src/mesa/main/marshal.c   | 37 +
 src/mesa/main/marshal.h   |  8 
 3 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index dfaeaaf..148387e 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -2354,21 +2354,21 @@
 
 
 
 

 
 
 
 

-
+

Re: [Mesa-dev] [PATCH] radeonsi: add si_init_descriptor_list() helper

2017-04-01 Thread Nicolai Hähnle 

On 31.03.2017 16:16, Samuel Pitoiset wrote:

This will be used by bindless to initialize the descriptor for
both samplers and images.

Signed-off-by: Samuel Pitoiset 


I'd prefer to see these patches in a larger context, to be honest.

As for this particular change, "init" to me implies also state/metadata 
initialization. As a stand-alone function, I think the new function 
should be called something else, perhaps si_fill_descriptors -- because 
that's what it does -- and the null_descriptor parameter should be 
renamed (to just descriptor) and made non-optional, so that the 
NULL-check happens in the caller.


This way, the function would make more sense to me as a stand-alone unit 
that does one thing.


Thanks,
Nicolai



---
 src/gallium/drivers/radeonsi/si_descriptors.c | 26 +-
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index d106351c85..84da830c11 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -96,6 +96,21 @@ static uint32_t null_image_descriptor[8] = {
 * descriptor */
 };

+static void si_init_descriptor_list(uint32_t *desc_list,
+   unsigned element_dw_size,
+   unsigned num_elements,
+   const uint32_t *null_descriptor)
+{
+   int i;
+
+   /* Initialize the array to NULL descriptors if the element size is 8. */
+   if (null_descriptor) {
+   assert(element_dw_size % 8 == 0);
+   for (i = 0; i < num_elements * element_dw_size / 8; i++)
+   memcpy(desc_list + i * 8, null_descriptor, 8 * 4);
+   }
+}
+
 static void si_init_descriptors(struct si_descriptors *desc,
unsigned shader_userdata_index,
unsigned element_dw_size,
@@ -103,8 +118,6 @@ static void si_init_descriptors(struct si_descriptors *desc,
const uint32_t *null_descriptor,
unsigned *ce_offset)
 {
-   int i;
-
assert(num_elements <= sizeof(desc->dirty_mask)*8);

desc->list = CALLOC(num_elements, element_dw_size * 4);
@@ -121,13 +134,8 @@ static void si_init_descriptors(struct si_descriptors 
*desc,
*ce_offset += align(element_dw_size * num_elements * 4, 32);
}

-   /* Initialize the array to NULL descriptors if the element size is 8. */
-   if (null_descriptor) {
-   assert(element_dw_size % 8 == 0);
-   for (i = 0; i < num_elements * element_dw_size / 8; i++)
-   memcpy(desc->list + i * 8, null_descriptor,
-  8 * 4);
-   }
+   si_init_descriptor_list(desc->list, element_dw_size, num_elements,
+   null_descriptor);
 }

 static void si_release_descriptors(struct si_descriptors *desc)




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Re: [Mesa-dev] Fwd: [PATCH 1/1] glsl/blob: handle copy of NULL ptr in blob_write_string

2017-04-01 Thread Nicolai Hähnle 

On 31.03.2017 21:05, gregory hainaut wrote:

On Fri, 31 Mar 2017 12:53:47 -0400
Ilia Mirkin  wrote:


On Fri, Mar 31, 2017 at 6:12 AM, Gregory Hainaut
 wrote:

Others have reported this crashing on Nouveau. I haven't seen the problem on 
radeonsi or i965.


Hello Timothy (sorry for the double mail, email is a complex tool:) )

Hum, tbh. I was quite surprised to hit this bug. I guess you save a
pre-optimized shader in the cache. So it could depends on optimization
passes.

From the top of my head, I think the "offending" line is this one
const ivec2 offsets[4] = {ivec2(...), ivec2(...), ivec2(...), ivec2(...)};

Strangely enough there are only 3 parameters without name in the
parameter list (signature is int, size 2 and CONTANT). Maybe one was
optimized away, I didn't look further.


Note that nouveau is unique in that it can process
textureGatherOffsets() directly, without lowering it to 4x
textureGatherOffset.

The relevant code is in st_glsl_to_tgsi.cpp

  if (!pscreen->get_param(pscreen, PIPE_CAP_TEXTURE_GATHER_OFFSETS))
 lower_offset_arrays(ir);

So I think with nouveau, you're seeing glsl ir that you wouldn't see otherwise.

  -ilia


Hello ilia

You're right. The issue appears in the texture gather 4 opcode.

I can see this path (st_glsl_to_tgsi.cpp) in GDB.
case ir_tg4:
   opcode = TGSI_OPCODE_TG4;


Thanks for the explanation!

So this definitely needs to be solved in the cache, but my concern with 
the current patch is that there might be code that behaves differently 
when the name is NULL vs. when the name is "". So I'd prefer if instead 
the caller of blob_write_string were changed accordingly (first write a 
flag of whether there is a string or not, etc.). Or maybe add a helper 
function blob_write_optional_string which does that.


Thanks,
Nicolai





Cheers,
Gregory




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Re: [Mesa-dev] [PATCH 4/5] r600g: use a clever alignment for index buffer uploads

2017-04-01 Thread Constantine Kharlamov 
Thank you, please, could you push them too? I don't have commit access.

On 28.03.2017 22:36, Marek Olšák wrote:
> Actually nevermind.
> 
> Patches 1-3:
> Reviewed-by: Marek Olšák 
> 
> Patches 4-5:
> These have no effect, because r600g hw doesn't use TC for index fetches.
> 
> Marek
> 
> 
> On Tue, Mar 28, 2017 at 9:33 PM, Marek Olšák  wrote:
>> BTW, I don't know if tcc_cache_line_size has the correct value for
>> pre-GCN chips.
>>
>> Marek
>>
>> On Sun, Mar 26, 2017 at 5:36 PM, Constantine Kharlamov
>>  wrote:
>>> Stolen from radeonsi
>>>
>>> Signed-off-by: Constantine Kharlamov 
>>> ---
>>>  src/gallium/drivers/r600/r600_state_common.c | 3 ++-
>>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/src/gallium/drivers/r600/r600_state_common.c 
>>> b/src/gallium/drivers/r600/r600_state_common.c
>>> index 961e04e9db..5293c4034f 100644
>>> --- a/src/gallium/drivers/r600/r600_state_common.c
>>> +++ b/src/gallium/drivers/r600/r600_state_common.c
>>> @@ -1766,7 +1766,8 @@ static void r600_draw_vbo(struct pipe_context *ctx, 
>>> const struct pipe_draw_info
>>>  info->instance_count > 1 ||
>>>  info->count*ib.index_size 
>>> > 20)) {
>>> u_upload_data(ctx->stream_uploader, 0,
>>> -  info->count * ib.index_size, 256,
>>> + info->count * ib.index_size,
>>> + 
>>> rctx->screen->b.info.tcc_cache_line_size,
>>>   ib.user_buffer, &ib.offset, 
>>> &ib.buffer);
>>> ib.user_buffer = NULL;
>>> }
>>> --
>>> 2.12.0
>>>
>>> ___
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[Mesa-dev] [PATCH] android: amd/addrlib: trivial fix for gfx9 support

2017-04-01 Thread Mauro Rossi 
Fixes the following build error:

external/mesa/src/amd/addrlib/gfx9/gfx9addrlib.cpp:36:10: fatal error: 
'gfx9_gb_reg.h' file not found
 ^
1 error generated.

Fixes: 7f160ef "amd/addrlib: import gfx9 support"
---
 src/amd/Android.addrlib.mk | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/amd/Android.addrlib.mk b/src/amd/Android.addrlib.mk
index d296ce0431c..540de5554bd 100644
--- a/src/amd/Android.addrlib.mk
+++ b/src/amd/Android.addrlib.mk
@@ -37,7 +37,9 @@ LOCAL_C_INCLUDES := \
$(MESA_TOP)/src/amd/common \
$(MESA_TOP)/src/amd/addrlib \
$(MESA_TOP)/src/amd/addrlib/core \
+   $(MESA_TOP)/src/amd/addrlib/inc/chip/gfx9 \
$(MESA_TOP)/src/amd/addrlib/inc/chip/r800 \
+   $(MESA_TOP)/src/amd/addrlib/gfx9/chip \
$(MESA_TOP)/src/amd/addrlib/r800/chip
 
 include $(MESA_COMMON_MK)
-- 
2.11.0

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[Mesa-dev] [PATCH] android: intel: genxml: fix genX_xml.h generation rules

2017-04-01 Thread Mauro Rossi 
Recent changes in Makefile.sources merged the aubinator files in
a unique list of generated files and genxml/genX_xml.h is now needed
to avoid the following building error:

ninja: error: '.../genxml/genX_xml.h', needed by '.../genxml/genX_xml.h',
missing and no known rule to make it
build/core/ninja.mk:148: recipe for target 'ninja_wrapper' failed

Fixes: 0f83c05 "intel: genxml: compress all gen files into one"
---
 src/intel/Android.genxml.mk | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/intel/Android.genxml.mk b/src/intel/Android.genxml.mk
index 842d0e13a33..4b0746c245b 100644
--- a/src/intel/Android.genxml.mk
+++ b/src/intel/Android.genxml.mk
@@ -96,6 +96,11 @@ $(intermediates)/genxml/gen9_pack.h: PRIVATE_XML := 
$(LOCAL_PATH)/genxml/gen9.xm
 $(intermediates)/genxml/gen9_pack.h: $(LOCAL_PATH)/genxml/gen9.xml 
$(LOCAL_PATH)/genxml/gen_pack_header.py
$(call header-gen)
 
+$(intermediates)/genxml/genX_xml.h: $(addprefix 
$(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) 
$(MESA_TOP)/src/intel/genxml/gen_zipped_file.py
+   @mkdir -p $(dir $@)
+   @echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
+   $(hide) $(MESA_PYTHON2) $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py 
$(addprefix $(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) > $@ || (rm -f $@; 
false)
+
 LOCAL_EXPORT_C_INCLUDE_DIRS := \
$(MESA_TOP)/src/intel \
$(intermediates)
-- 
2.11.0

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Re: [Mesa-dev] [PATCH 0/3] misc cleanups

2017-04-01 Thread Erik Faye-Lund 
Thanks, pushed.

On Fri, Mar 31, 2017 at 4:42 PM, Nicolai Hähnle  wrote:
> Series is
>
> Reviewed-by: Nicolai Hähnle 
>
> On 31.03.2017 12:57, Erik Faye-Lund wrote:
>>
>> Here's a few cleanup-patches I've had in my tree for a while, that
>> I thought I should send upstream soon.
>>
>> Erik Faye-Lund (3):
>>   st/mesa: avoid aliasing violation in st_cb_perfmon.c
>>   gallium/docs: remove documentation of removed arg
>>   glsl: ir_explog_to_explog2 is no more
>>
>>  src/gallium/docs/source/screen.rst | 2 --
>>  src/mesa/program/ir_to_mesa.cpp| 4 +++-
>>  src/mesa/state_tracker/st_cb_perfmon.c | 6 +++---
>>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 4 +++-
>>  4 files changed, 9 insertions(+), 7 deletions(-)
>>
>
>
> --
> Lerne, wie die Welt wirklich ist,
> Aber vergiss niemals, wie sie sein sollte.
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[Mesa-dev] [Bug 90264] [Regression, bisected] Tooltip corruption in Chrome

2017-04-01 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=90264

Sami Farin  changed:

   What|Removed |Added

 CC||hvtaifwkbgefb...@gmail.com

--- Comment #71 from Sami Farin  ---
I applied patches in #45 and #50, no more tooltip corruption in Chrome.

GL_VENDOR   Intel Open Source Technology Center
GL_RENDERER Mesa DRI Intel(R) Sandybridge Desktop
GL_VERSION  3.3 (Core Profile) Mesa 13.0.4

Graphics Feature Status
Canvas: Hardware accelerated
Flash: Hardware accelerated
Flash Stage3D: Hardware accelerated
Flash Stage3D Baseline profile: Hardware accelerated
Compositing: Hardware accelerated
Multiple Raster Threads: Enabled
Native GpuMemoryBuffers: Software only. Hardware acceleration disabled
Rasterization: Software only. Hardware acceleration disabled
Video Decode: Software only, hardware acceleration unavailable
Video Encode: Hardware accelerated
VPx Video Decode: Software only, hardware acceleration unavailable
WebGL: Hardware accelerated
WebGL2: Hardware accelerated

Driver Bug Workarounds
adjust_src_dst_region_for_blitframebuffer
clear_uniforms_before_first_program_use
count_all_in_varyings_packing
decode_encode_srgb_for_generatemipmap
disable_framebuffer_cmaa
disable_post_sub_buffers_for_onscreen_surfaces
msaa_is_slow
remove_invariant_and_centroid_for_essl3
scalarize_vec_and_mat_constructor_args

Problems Detected
Accelerated video decode is unavailable on Linux: 137247
 - Disabled Features: accelerated_video_decode
Clear uniforms before first program use on all platforms: 124764, 349137
 - Applied Workarounds: clear_uniforms_before_first_program_use
Mesa drivers in Linux handle varyings without static use incorrectly: 333885
 - Applied Workarounds: count_all_in_varyings_packing
Disable partial swaps on Mesa drivers (detected with GL_RENDERER): 339493
 - Applied Workarounds: disable_post_sub_buffers_for_onscreen_surfaces
Always rewrite vec/mat constructors to be consistent: 398694
 - Applied Workarounds: scalarize_vec_and_mat_constructor_args
On Intel GPUs MSAA performance is not acceptable for GPU rasterization: 527565
 - Applied Workarounds: msaa_is_slow
Timer queries crash on Intel GPUs on Linux: 540543, 576991
Limited enabling of Chromium GL_INTEL_framebuffer_CMAA: 535198
Applied Workarounds: disable_framebuffer_cmaa
 - Disable partial swaps on Mesa drivers (detected with GL_VERSION): 339493
Applied Workarounds: disable_post_sub_buffers_for_onscreen_surfaces
 - Decode and encode before generateMipmap for srgb format textures on os
except macosx: 634519
Applied Workarounds: decode_encode_srgb_for_generatemipmap
 - adjust src/dst region if blitting pixels outside read framebuffer on Linux
Intel: 664740
Applied Workarounds: adjust_src_dst_region_for_blitframebuffer
 - Mesa driver GL 3.3 requires invariant and centroid to match between shaders:
639760, 641129
Applied Workarounds: remove_invariant_and_centroid_for_essl3
Disable KHR_blend_equation_advanced until cc shaders are updated: 661715
Accelerated rasterization has been disabled, either via blacklist, about:flags
or the command line.
 - Disabled Features: rasterization
Native GpuMemoryBuffers have been disabled, either via about:flags or command
line.
 - Disabled Features: native_gpu_memory_buffers

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Re: [Mesa-dev] [PATCH] i965/fs: Gracefully handle TXS on multisampled textures with no LOD

2017-04-01 Thread Grazvydas Ignotas 
On Thu, Mar 30, 2017 at 1:22 AM, Jason Ekstrand 
wrote:

> This can happen for multisampled textures since they are never mipmapped
> and textureSize(gsampler2DMS*) does not take an LOD parameter.  This
> fixes a shader validation error in the new Sascha deferredmultisampling
> demo.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100391
> Cc: "13.0 17.0" 
> ---
>

Tested-by: Grazvydas Ignotas 
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Re: [Mesa-dev] [PATCH] android: intel: genxml: fix genX_xml.h generation rules

2017-04-01 Thread Lionel Landwerlin 

On 01/04/17 11:50, Mauro Rossi wrote:

Recent changes in Makefile.sources merged the aubinator files in
a unique list of generated files and genxml/genX_xml.h is now needed
to avoid the following building error:

ninja: error: '.../genxml/genX_xml.h', needed by '.../genxml/genX_xml.h',
missing and no known rule to make it
build/core/ninja.mk:148: recipe for target 'ninja_wrapper' failed

Fixes: 0f83c05 "intel: genxml: compress all gen files into one"
---
  src/intel/Android.genxml.mk | 5 +
  1 file changed, 5 insertions(+)

diff --git a/src/intel/Android.genxml.mk b/src/intel/Android.genxml.mk
index 842d0e13a33..4b0746c245b 100644
--- a/src/intel/Android.genxml.mk
+++ b/src/intel/Android.genxml.mk
@@ -96,6 +96,11 @@ $(intermediates)/genxml/gen9_pack.h: PRIVATE_XML := 
$(LOCAL_PATH)/genxml/gen9.xm
  $(intermediates)/genxml/gen9_pack.h: $(LOCAL_PATH)/genxml/gen9.xml 
$(LOCAL_PATH)/genxml/gen_pack_header.py
$(call header-gen)
  
+$(intermediates)/genxml/genX_xml.h: $(addprefix $(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py

+   @mkdir -p $(dir $@)
+   @echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
+   $(hide) $(MESA_PYTHON2) $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py 
$(addprefix $(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) > $@ || (rm -f $@; 
false)
+


The other files seems to use the header-gen macro, why not this one too?

Acked-by: Lionel Landwerlin 


  LOCAL_EXPORT_C_INCLUDE_DIRS := \
$(MESA_TOP)/src/intel \
$(intermediates)



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[Mesa-dev] [ANNOUNCE] mesa 17.0.3

2017-04-01 Thread Andres Gomez 
Mesa 17.0.3 is now available.

In this release we have:

Several patches addressing improvements in the API validation and the
GLSL compiler.

Some other bunch of patches for the Intel drivers (both GL and Vulkan),
including a fix for a hang with GfxBench 4.0 CarChase, several
improvements in the Vulkan driver and other crash fixes.

Galleon drivers have seen fixed an existing deadlock too.

For radeonsi, we now include the polaris12 pci id and a fix for a hang
after a shader compile failure.

nouveau is benefiting now from performance improvements, specially for
the Feral-ported games and some other fixes.

radv, freedreno and clover include some few fixes too.

On integration side - we had a swr build fix with llvm >= 5.0 and also
a fix for building with MSVC.


Alex Deucher (1):
  radeonsi: add new polaris12 pci id

Andres Gomez (6):
  glsl: on UBO/SSBOs link error reset the number of active blocks to 0
  cherry-ignore: add the Invalidate L2 for TRANSFER_WRITE barriers fix
  cherry-ignore: add the Flush after unmap in gbm/dri fix
  cherry-ignore: corrected typo in the Flush after unmap in gbm/dri fix
  Update version to 17.0.3
  docs: add release notes for 17.0.3

Axel Davy (2):
  st/nine: Resolve deadlock in surface/volume dtors when using csmt
  st/nine: Use atomics for available_texture_mem

Bas Nieuwenhuizen (1):
  radv: flush DB cache before and after HTILE decompress.

Dave Airlie (1):
  radv: fix primitive reset index emission

Emil Velikov (1):
  docs: add sha256 checksums for 17.0.2

Ilia Mirkin (1):
  st/mesa: set result writemask based on ir type

Jan Vesely (1):
  clover: use pipe_resource references

Jason Ekstrand (9):
  anv/query: Invalidate the correct range
  anv/GetQueryPoolResults: Actually implement the spec
  anv/image: Return early when unbinding an image
  anv/query: Fix the location of timestamp availability
  anv: Make anv_get_layerCount a macro
  anv/blorp: Use anv_get_layerCount everywhere
  anv/cmd_buffer: Apply flush operations prior to executing secondaries
  anv/cmd_buffer: Fix bad indentation
  anv: Flush caches prior to PIPELINE_SELECT on all gens

José Fonseca (1):
  c11/threads: Include thr/xtimec.h for xtime definition when building with 
MSVC.

Juan A. Suarez Romero (1):
  tests/cache_test: allow crossing mount points

Karol Herbst (1):
  nvc0/ir: treat FMA like MAD for operand propagation

Kenneth Graunke (1):
  i965: Fall back to GL 4.2/4.3 on Haswell if the kernel isn't new enough.

Marek Olšák (1):
  radeonsi: don't hang on shader compile failure

Matt Turner (1):
  i965/fs: Don't emit SEL instructions for type-converting MOVs.

Nanley Chery (1):
  intel: Correct the BDW surface state size

Nicolai Hähnle (1):
  mesa/main: fix MultiDrawElements[BaseVertex] validation of primcount

Rob Clark (1):
  freedreno: fix memory leak

Tim Rowley (1):
  swr: [rasterizer jitter] fix llvm >= 5.0 build break

Timothy Arceri (2):
  glsl: fix lower jumps for returns when loop is inside an if
  mesa: update lower_jumps tests after bug fix

Topi Pohjolainen (1):
  i965/gen8+: Do full stall when switching pipeline

Xu Randy (1):
  anv/blorp: Fix a crash in CmdClearColorImage

Xu,Randy (1):
  anv/genX: Solve the vkCreateGraphicsPipelines crash

git tag: mesa-17.0.3

https://mesa.freedesktop.org/archive/mesa-17.0.3.tar.gz
MD5:  6068a96bc478c1b97461153d518a77bf  mesa-17.0.3.tar.gz
SHA1: f4998e1074c54832ac6691495ecccfbb4d913e18  mesa-17.0.3.tar.gz
SHA256: 8253edf1bdd7b14ab63d5982349143a5c9ac3767f39a63257cc9d7e7d92f60f1  
mesa-17.0.3.tar.gz
SHA512: 
c2062299eac71026f073615aca931ff936a28445d253f41462b9a71b7b8178c301a225eed3e789704341b35cadab7c4f43ff8ceb552a84256d68d06268d5237c
  mesa-17.0.3.tar.gz
PGP:  https://mesa.freedesktop.org/archive/mesa-17.0.3.tar.gz.sig

https://mesa.freedesktop.org/archive/mesa-17.0.3.tar.xz
MD5:  003072c044b3fb5eca8be2037f15e4ec  mesa-17.0.3.tar.xz
SHA1: e2f2f719ebe8cd0932b077c5697342dfe8cd4f27  mesa-17.0.3.tar.xz
SHA256: ca646f5075a002d60ef9123c8a4331cede155c01712ef945a65c59a5e69fe7ed  
mesa-17.0.3.tar.xz
SHA512: 
0bcf1609b54fdabb30ec0a500b78e039bd50060c2c7f5a2e57fca29e1a311fb785dadc3cd311018ebe8020d1cc6320181ece2d2aa39d2f215b0ebf2cb0a55165
  mesa-17.0.3.tar.xz
PGP:  https://mesa.freedesktop.org/archive/mesa-17.0.3.tar.xz.sig


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Re: [Mesa-dev] [PATCH] android: intel: genxml: fix genX_xml.h generation rules

2017-04-01 Thread Mauro Rossi 
2017-04-01 17:18 GMT+02:00 Lionel Landwerlin 
:

> On 01/04/17 11:50, Mauro Rossi wrote:
>
>> Recent changes in Makefile.sources merged the aubinator files in
>> a unique list of generated files and genxml/genX_xml.h is now needed
>> to avoid the following building error:
>>
>> ninja: error: '.../genxml/genX_xml.h', needed by '.../genxml/genX_xml.h',
>> missing and no known rule to make it
>> build/core/ninja.mk:148: recipe for target 'ninja_wrapper' failed
>>
>> Fixes: 0f83c05 "intel: genxml: compress all gen files into one"
>> ---
>>   src/intel/Android.genxml.mk | 5 +
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/src/intel/Android.genxml.mk b/src/intel/Android.genxml.mk
>> index 842d0e13a33..4b0746c245b 100644
>> --- a/src/intel/Android.genxml.mk
>> +++ b/src/intel/Android.genxml.mk
>> @@ -96,6 +96,11 @@ $(intermediates)/genxml/gen9_pack.h: PRIVATE_XML :=
>> $(LOCAL_PATH)/genxml/gen9.xm
>>   $(intermediates)/genxml/gen9_pack.h: $(LOCAL_PATH)/genxml/gen9.xml
>> $(LOCAL_PATH)/genxml/gen_pack_header.py
>> $(call header-gen)
>>   +$(intermediates)/genxml/genX_xml.h: $(addprefix
>> $(MESA_TOP)/src/intel/,$(GENXML_XML_FILES))
>> $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py
>> +   @mkdir -p $(dir $@)
>> +   @echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
>> +   $(hide) $(MESA_PYTHON2) 
>> $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py
>> $(addprefix $(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) > $@ || (rm -f
>> $@; false)
>> +
>>
>
> The other files seems to use the header-gen macro, why not this one too?
>

Hi Lionel,

the header-gen macro could have be reused,
but additional '|| (rm -f $@; false)' would have required an hybrid
generation rule
or to define an additional macro.

In this way the exact automake generation rules have been ported and are
less cryptic,
as suggested by Emil in the last serie of similar cases.

Mauro



>
> Acked-by: Lionel Landwerlin 
>
>   LOCAL_EXPORT_C_INCLUDE_DIRS := \
>> $(MESA_TOP)/src/intel \
>> $(intermediates)
>>
>
>
>


Mail
priva di virus. www.avast.com

<#DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>
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Re: [Mesa-dev] [PATCH] i965/fs: Gracefully handle TXS on multisampled textures with no LOD

2017-04-01 Thread Jason Ekstrand 
On Sat, Apr 1, 2017 at 7:16 AM, Grazvydas Ignotas  wrote:

> On Thu, Mar 30, 2017 at 1:22 AM, Jason Ekstrand 
> wrote:
>
>> This can happen for multisampled textures since they are never mipmapped
>> and textureSize(gsampler2DMS*) does not take an LOD parameter.  This
>> fixes a shader validation error in the new Sascha deferredmultisampling
>> demo.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100391
>> Cc: "13.0 17.0" 
>> ---
>>
>
> Tested-by: Grazvydas Ignotas 
>
>
I sent a new patch yesterday that fixes the same bug but doesn't cause GL
to start crashing.
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[Mesa-dev] [Bug 100259] [EGL] [GBM] undefined reference to `gbm_bo_create_with_modifiers'

2017-04-01 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=100259

--- Comment #13 from ovarieg...@yahoo.com ---
Yes, it was 'make install' that failed and seems to have been a related issue
as above. I was instructed to reopen this issue report in #dri-devel after
asking about the build failure, but shortly after with the help of the pkgconf
devs I found out it was a bug in my own pkgconf build script that managed to
not cause any problems for 5 months...

I resolved it for myself here.
https://notabug.org/orbea/Slackbuilds/commit/56db318ceb1c093961cea2ba2bdd7dba17177367

As for why it why I ran into this now I'm not really sure, but I guess its not
important anymore. :)

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[Mesa-dev] [Bug 100424] X hang (in kernel) after some event in Serious Sam Fusion using radv. 4.9/amd-staging-4.9

2017-04-01 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=100424

John  changed:

   What|Removed |Added

 CC||john.etted...@gmail.com

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Re: [Mesa-dev] [PATCH 2/4] i916/blorp: Align vertex buffers to 64B

2017-04-01 Thread Jason Ekstrand 
Two people have independently pointed out the i916 typo.  I've fixed it
locally.

On Fri, Mar 31, 2017 at 4:17 PM, Jason Ekstrand 
wrote:

> Cc: "13.0 17.0" 
> ---
>  src/mesa/drivers/dri/i965/genX_blorp_exec.c | 13 -
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> index f9334ee..b6122a3 100644
> --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> @@ -122,8 +122,19 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch,
> uint32_t size,
> assert(batch->blorp->driver_ctx == batch->driver_batch);
> struct brw_context *brw = batch->driver_batch;
>
> +   /* From the Sky Lake PRM, 3DSTATE_VERTEX_BUFFERS:
> +*
> +*"The VF cache needs to be invalidated before binding and then
> using
> +*Vertex Buffers that overlap with any previously bound Vertex
> Buffer
> +*(at a 64B granularity) since the last invalidation.  A VF cache
> +*invalidate is performed by setting the "VF Cache Invalidation
> Enable"
> +*bit in PIPE_CONTROL."
> +*
> +* In order to avoid this problem, we align all vertex buffer
> allocations
> +* to 64 bytes.
> +*/
> uint32_t offset;
> -   void *data = brw_state_batch(brw, size, 32, &offset);
> +   void *data = brw_state_batch(brw, size, 64, &offset);
>
> *addr = (struct blorp_address) {
>.buffer = brw->batch.bo,
> --
> 2.5.0.400.gff86faf
>
>
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[Mesa-dev] [PATCH] radv: fix order of the guardband register emission.

2017-04-01 Thread Dave Airlie 
From: Dave Airlie 

y is vert, x is horiz.

Noticed in visual inspection compared to radeonsi.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/si_cmd_buffer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index e847dcf..e176abe 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -627,10 +627,10 @@ si_write_scissors(struct radeon_winsys_cs *cs, int first,
}
 
radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
-   radeon_emit(cs, fui(guardband_x));
-   radeon_emit(cs, fui(1.0));
radeon_emit(cs, fui(guardband_y));
radeon_emit(cs, fui(1.0));
+   radeon_emit(cs, fui(guardband_x));
+   radeon_emit(cs, fui(1.0));
 }
 
 static inline unsigned
-- 
2.9.3

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