Re: [Mesa-dev] [PATCH] mesa: don't crash in KHR_no_error uniform variants when location == -1

2017-05-12 Thread Timothy Arceri
My commit message seems to have gone missing. By -1 is allowed so that 
inactive uniforms don't cause the app to throw an error.


On 13/05/17 16:31, Timothy Arceri wrote:

---
  src/mesa/main/uniform_query.cpp | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 0e02a76..5f38aa5 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -904,20 +904,23 @@ validate_uniform(GLint location, GLsizei count, const 
GLvoid *values,
  extern "C" void
  _mesa_uniform(GLint location, GLsizei count, const GLvoid *values,
struct gl_context *ctx, struct gl_shader_program *shProg,
enum glsl_base_type basicType, unsigned src_components)
  {
 unsigned offset;
 int size_mul = glsl_base_type_is_64bit(basicType) ? 2 : 1;
  
 struct gl_uniform_storage *uni;

 if (_mesa_is_no_error_enabled(ctx)) {
+  if (location == -1)
+ return;
+
uni = shProg->UniformRemapTable[location];
  
/* The array index specified by the uniform location is just the

 * uniform location minus the base location of of the uniform.
 */
assert(uni->array_elements > 0 || location == (int)uni->remap_location);
offset = location - uni->remap_location;
 } else {
uni = validate_uniform(location, count, values, &offset, ctx, shProg,
   basicType, src_components);


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[Mesa-dev] [Bug 101028] Cannot run OpenGL applications on a remote XServer without +iglx

2017-05-12 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=101028

Bug ID: 101028
   Summary: Cannot run OpenGL applications on a remote XServer
without +iglx
   Product: Mesa
   Version: unspecified
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/swr
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: suic...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

When I try to run glxgears on a remote Cygwin / X server I get this error 

suici@HP-Pavilion-g7:~$ LIBGL_DEBUG=verbose DISPLAY=:0 glxgears
libGL: OpenDriver: trying /usr/lib/x86_64-linux-gnu/dri/tls/swrast_dri.so
libGL: OpenDriver: trying /usr/lib/x86_64-linux-gnu/dri/swrast_dri.so
libGL: Can't open configuration file /home/suici/.drirc: No such file or
directory.
libGL: Can't open configuration file /home/suici/.drirc: No such file or
directory.
libGL error: No matching fbConfigs or visuals found
libGL error: failed to load driver: swrast
X Error of failed request:  BadValue (integer parameter out of range for
operation)
  Major opcode of failed request:  149 (GLX)
  Minor opcode of failed request:  3 (X_GLXCreateContext)
  Value in failed request:  0x0
  Serial number of failed request:  28
  Current serial number in output stream:  30

I'm using Windows 10 WSL but the same error also occurs if I run it from a
remote Linux machine. If I use +iglx the error goes but it only supports GL
1.4.

GPU : Radeon HD 7640G

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[Mesa-dev] [PATCH] mesa: don't crash in KHR_no_error uniform variants when location == -1

2017-05-12 Thread Timothy Arceri
---
 src/mesa/main/uniform_query.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 0e02a76..5f38aa5 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -904,20 +904,23 @@ validate_uniform(GLint location, GLsizei count, const 
GLvoid *values,
 extern "C" void
 _mesa_uniform(GLint location, GLsizei count, const GLvoid *values,
   struct gl_context *ctx, struct gl_shader_program *shProg,
   enum glsl_base_type basicType, unsigned src_components)
 {
unsigned offset;
int size_mul = glsl_base_type_is_64bit(basicType) ? 2 : 1;
 
struct gl_uniform_storage *uni;
if (_mesa_is_no_error_enabled(ctx)) {
+  if (location == -1)
+ return;
+
   uni = shProg->UniformRemapTable[location];
 
   /* The array index specified by the uniform location is just the
* uniform location minus the base location of of the uniform.
*/
   assert(uni->array_elements > 0 || location == (int)uni->remap_location);
   offset = location - uni->remap_location;
} else {
   uni = validate_uniform(location, count, values, &offset, ctx, shProg,
  basicType, src_components);
-- 
2.9.3

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Re: [Mesa-dev] [PATCH 09/11] intel/tools: Refactor gen_disasm_disassemble() to use annotations

2017-05-12 Thread Pohjolainen, Topi
On Thu, May 04, 2017 at 11:27:57AM -0700, Matt Turner wrote:
> On Tue, May 2, 2017 at 6:03 AM, Iago Toral  wrote:
> > On Mon, 2017-05-01 at 13:54 -0700, Matt Turner wrote:
> >> Which will allow us to print validation errors found in shader
> >> assembly
> >> in GPU hang error states.
> >> ---
> >>  src/intel/tools/disasm.c | 71 +-
> >> --
> >>  1 file changed, 43 insertions(+), 28 deletions(-)
> >>
> >> diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
> >> index 62256d2..361885b 100644
> >> --- a/src/intel/tools/disasm.c
> >> +++ b/src/intel/tools/disasm.c
> >> @@ -43,52 +43,67 @@ is_send(uint32_t opcode)
> >> opcode == BRW_OPCODE_SENDSC );
> >>  }
> >>
> >> -void
> >> -gen_disasm_disassemble(struct gen_disasm *disasm, void *assembly,
> >> -   int start, FILE *out)
> >> +static int
> >> +gen_disasm_find_end(struct gen_disasm *disasm, void *assembly, int
> >> start)
> >>  {
> >> struct gen_device_info *devinfo = &disasm->devinfo;
> >> -   bool dump_hex = false;
> >> int offset = start;
> >>
> >> /* This loop exits when send-with-EOT or when opcode is 0 */
> >> while (true) {
> >>brw_inst *insn = assembly + offset;
> >> -  brw_inst uncompacted;
> >> -  bool compacted = brw_inst_cmpt_control(devinfo, insn);
> >> -  if (0)
> >> - fprintf(out, "0x%08x: ", offset);
> >> -
> >> -  if (compacted) {
> >> - brw_compact_inst *compacted = (void *)insn;
> >> - if (dump_hex) {
> >> -fprintf(out, "0x%08x 0x%08x   ",
> >> -   ((uint32_t *)insn)[1],
> >> -   ((uint32_t *)insn)[0]);
> >> - }
> >> -
> >> - brw_uncompact_instruction(devinfo, &uncompacted,
> >> compacted);
> >> - insn = &uncompacted;
> >> +
> >> +  if (brw_inst_cmpt_control(devinfo, insn)) {
> >>   offset += 8;
> >>} else {
> >> - if (dump_hex) {
> >> -fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
> >> -   ((uint32_t *)insn)[3],
> >> -   ((uint32_t *)insn)[2],
> >> -   ((uint32_t *)insn)[1],
> >> -   ((uint32_t *)insn)[0]);
> >> - }
> >>   offset += 16;
> >>}
> >>
> >> -  brw_disassemble_inst(out, devinfo, insn, compacted);
> >> -
> >>/* Simplistic, but efficient way to terminate disasm */
> >>uint32_t opcode = brw_inst_opcode(devinfo, insn);
> >>if (opcode == 0 || (is_send(opcode) && brw_inst_eot(devinfo,
> >> insn))) {
> >>   break;
> >>}
> >> }
> >> +
> >> +   return offset;
> >> +}
> >> +
> >> +void
> >> +gen_disasm_disassemble(struct gen_disasm *disasm, void *assembly,
> >> +   int start, FILE *out)
> >> +{
> >> +   struct gen_device_info *devinfo = &disasm->devinfo;
> >> +   int end = gen_disasm_find_end(disasm, assembly, start);
> >> +
> >> +   /* Make a dummy annotation structure that
> >> brw_validate_instructions
> >> +* can work from.
> >> +*/
> >> +   struct annotation_info annotation_info = {
> >> +  .ann_count = 1,
> >> +  .ann_size = 2,
> >> +   };
> >> +   annotation_info.mem_ctx = ralloc_context(NULL);
> >> +   annotation_info.ann = rzalloc_array(annotation_info.mem_ctx,
> >> +   struct annotation,
> >> +   annotation_info.ann_size);
> >> +   annotation_info.ann[0].offset = start;
> >> +   annotation_info.ann[1].offset = end;
> >> +   brw_validate_instructions(devinfo, assembly, start, end,
> >> &annotation_info);
> >> +   struct annotation *annotation = annotation_info.ann;
> >> +
> >> +   for (int i = 0; i < annotation_info.ann_count; i++) {
> >> +  int start_offset = annotation[i].offset;
> >> +  int end_offset = annotation[i + 1].offset;
> >
> > I was going to say that this code seems to overflow when i
> > == annotation_info.ann_count - 1, but then I noticed that there are
> > similar loops in other parts of the code and that you initialized
> > ann_count to just 1 even though you have two initial annotations, so I
> > guess this is how this is supposed to work, right?
> 
> Yeah, exactly. I'm not sure it's a good way to handle it though. To be
> honest, I had a hard time remembering how it was supposed to work and
> I wrote the annotation system.
> 
> I think a linked list would be a lot more natural than the array/count.

Sounds like it. While not ideal I think we can live with this for now:

Reviewed-by: Topi Pohjolainen 
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Re: [Mesa-dev] Fix __atomic* builtins detection for Clang

2017-05-12 Thread Jonathan Gray
On Sat, May 13, 2017 at 02:22:30AM +0200, Jan Beich wrote:
> "int" isn't large enough and lack of builtins only manifests at link time.
> This was breaking build on FreeBSD 11.0 i386 with Clang 3.8.0.

You should be building with -march=i586 on i386 for CX8.

The diff is wrong as it will break other architectures, ie powerpc.

commit a6a38a038bd62e6d9558905f00bef81b5e7e6fcc
Author: Grazvydas Ignotas 
Date:   Fri Mar 31 01:26:25 2017 +0300

util/u_atomic: provide 64bit atomics where they're missing

attempts to handle powerpc like situations, though not sync
builtins being missing entirely.

> 
> glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
> `disk_cache_remove':
> disk_cache.c:(.text+0x763): undefined reference to `__atomic_fetch_add_8'
> glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
> `cache_put':
> disk_cache.c:(.text+0xabc): undefined reference to `__atomic_fetch_add_8'
> disk_cache.c:(.text+0xec1): undefined reference to `__atomic_fetch_add_8'
> c++: error: linker command failed with exit code 1 (use -v to see invocation)
> ---
>  configure.ac | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index 957d15df8c..5b11941a0c 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -403,9 +403,10 @@ AM_CONDITIONAL([SSE41_SUPPORTED], [test 
> x$SSE41_SUPPORTED = x1])
>  AC_SUBST([SSE41_CFLAGS], $SSE41_CFLAGS)
>  
>  dnl Check for new-style atomic builtins
> -AC_COMPILE_IFELSE([AC_LANG_SOURCE([[
> +AC_LINK_IFELSE([AC_LANG_SOURCE([[
> +#include 
>  int main() {
> -int n;
> +uint64_t n;
>  return __atomic_load_n(&n, __ATOMIC_ACQUIRE);
>  }]])], GCC_ATOMIC_BUILTINS_SUPPORTED=1)
>  if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = x1; then
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Re: [Mesa-dev] [PATCH 01/11] i965: Mark shader programs for capture in the error state.

2017-05-12 Thread Pohjolainen, Topi
On Mon, May 01, 2017 at 01:54:45PM -0700, Matt Turner wrote:
> When the GPU hangs, the kernel saves some state for us. Until now it has
> not included the shader programs, which are very often the reason the
> GPU hang occurred. With the programs saved in the error state, we should
> be more capable of debugging hangs.
> 
> Thanks to Chris Wilson and Ben Widawsky who provided the kernel support
> for this feature ("drm/i915: Copy user requested buffers into the error
> state"), which will be in kernel v4.13.

Reviewed-by: Topi Pohjolainen 

> ---
>  src/mesa/drivers/dri/i965/brw_bufmgr.c| 1 +
>  src/mesa/drivers/dri/i965/brw_bufmgr.h| 5 +
>  src/mesa/drivers/dri/i965/brw_program_cache.c | 4 
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +-
>  src/mesa/drivers/dri/i965/intel_screen.c  | 8 
>  src/mesa/drivers/dri/i965/intel_screen.h  | 7 +++
>  6 files changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
> b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> index 4b64331..2f17934 100644
> --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> @@ -599,6 +599,7 @@ bo_unreference_final(struct brw_bo *bo, time_t time)
>bo->free_time = time;
>  
>bo->name = NULL;
> +  bo->kflags = 0;
>  
>list_addtail(&bo->head, &bucket->head);
> } else {
> diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
> b/src/mesa/drivers/dri/i965/brw_bufmgr.h
> index 1b1790a..56ec206 100644
> --- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
> +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
> @@ -97,6 +97,11 @@ struct brw_bo {
> int refcount;
> const char *name;
>  
> +#ifndef EXEC_OBJECT_CAPTURE
> +#define EXEC_OBJECT_CAPTURE(1<<7)
> +#endif
> +   uint64_t kflags;
> +
> /**
>  * Kenel-assigned global name for this object
>  *
> diff --git a/src/mesa/drivers/dri/i965/brw_program_cache.c 
> b/src/mesa/drivers/dri/i965/brw_program_cache.c
> index c06ee23..93eb119 100644
> --- a/src/mesa/drivers/dri/i965/brw_program_cache.c
> +++ b/src/mesa/drivers/dri/i965/brw_program_cache.c
> @@ -216,6 +216,8 @@ brw_cache_new_bo(struct brw_cache *cache, uint32_t 
> new_size)
> struct brw_bo *new_bo;
>  
> new_bo = brw_bo_alloc(brw->bufmgr, "program cache", new_size, 64);
> +   if (can_do_exec_capture(brw->screen))
> +  new_bo->kflags = EXEC_OBJECT_CAPTURE;
> if (brw->has_llc)
>brw_bo_map_unsynchronized(brw, new_bo);
>  
> @@ -407,6 +409,8 @@ brw_init_caches(struct brw_context *brw)
>calloc(cache->size, sizeof(struct brw_cache_item *));
>  
> cache->bo = brw_bo_alloc(brw->bufmgr, "program cache",  4096, 64);
> +   if (can_do_exec_capture(brw->screen))
> +  cache->bo->kflags = EXEC_OBJECT_CAPTURE;
> if (brw->has_llc)
>brw_bo_map_unsynchronized(brw, cache->bo);
>  }
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index 154c095..496b492 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -530,7 +530,7 @@ add_exec_bo(struct intel_batchbuffer *batch, struct 
> brw_bo *bo)
> }
> validation_entry->alignment = bo->align;
> validation_entry->offset = bo->offset64;
> -   validation_entry->flags = 0;
> +   validation_entry->flags = bo->kflags;
> validation_entry->rsvd1 = 0;
> validation_entry->rsvd2 = 0;
>  
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
> b/src/mesa/drivers/dri/i965/intel_screen.c
> index 34a5f18..514c17e 100644
> --- a/src/mesa/drivers/dri/i965/intel_screen.c
> +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> @@ -1994,6 +1994,14 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
>screen->cmd_parser_version = 0;
> }
>  
> +   /* Kernel 4.13 retuired for exec object capture */
> +#ifndef I915_PARAM_HAS_EXEC_CAPTURE
> +#define I915_PARAM_HAS_EXEC_CAPTURE 45
> +#endif
> +   if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_CAPTURE)) {
> +  screen->kernel_features |= KERNEL_ALLOWS_EXEC_CAPTURE;
> +   }
> +
> if (!intel_detect_pipelined_so(screen)) {
>/* We can't do anything, so the effective version is 0. */
>screen->cmd_parser_version = 0;
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.h 
> b/src/mesa/drivers/dri/i965/intel_screen.h
> index fe0e044..f9c1db6 100644
> --- a/src/mesa/drivers/dri/i965/intel_screen.h
> +++ b/src/mesa/drivers/dri/i965/intel_screen.h
> @@ -74,6 +74,7 @@ struct intel_screen
>  #define KERNEL_ALLOWS_MI_MATH_AND_LRR   (1<<2)
>  #define KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3 (1<<3)
>  #define KERNEL_ALLOWS_COMPUTE_DISPATCH  (1<<4)
> +#define KERNEL_ALLOWS_EXEC_CAPTURE  (1<<5)
>  
> struct brw_bufmgr *bufmgr;
>  
> @@ -155,6 +156,12 @@ can_do_predicate_writes(const struct intel_screen 
> *screen)
> return screen->kernel_features & KERN

Re: [Mesa-dev] [PATCH 03/11] i965: Allow brw_eu_validate to handle compact instructions

2017-05-12 Thread Pohjolainen, Topi
On Mon, May 01, 2017 at 01:54:47PM -0700, Matt Turner wrote:
> This will allow the validator to run on shader programs we find in the
> GPU hang error state.
> ---
>  src/intel/compiler/brw_eu_validate.c | 14 ++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/src/intel/compiler/brw_eu_validate.c 
> b/src/intel/compiler/brw_eu_validate.c
> index 39363e4..38564a4 100644
> --- a/src/intel/compiler/brw_eu_validate.c
> +++ b/src/intel/compiler/brw_eu_validate.c
> @@ -1051,6 +1051,14 @@ brw_validate_instructions(const struct gen_device_info 
> *devinfo,
> for (int src_offset = start_offset; src_offset < end_offset;) {
>struct string error_msg = { .str = NULL, .len = 0 };
>const brw_inst *inst = assembly + src_offset;
> +  bool is_compact = brw_inst_cmpt_control(devinfo, inst);

Could be const. Either way:

Reviewed-by: Topi Pohjolainen 

> +  brw_inst uncompacted;
> +
> +  if (is_compact) {
> + brw_compact_inst *compacted = (void *)inst;
> + brw_uncompact_instruction(devinfo, &uncompacted, compacted);
> + inst = &uncompacted;
> +  }
>  
>if (is_unsupported_inst(devinfo, inst)) {
>   ERROR("Instruction not supported on this Gen");
> @@ -1067,6 +1075,12 @@ brw_validate_instructions(const struct gen_device_info 
> *devinfo,
>}
>valid = valid && error_msg.len == 0;
>free(error_msg.str);
> +
> +  if (is_compact) {
> + src_offset += sizeof(brw_compact_inst);
> +  } else {
> + src_offset += sizeof(brw_inst);
> +  }
> }
>  
> return valid;
> -- 
> 2.10.2
> 
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Re: [Mesa-dev] [PATCH 0/2] Allow redeclaration of GLSL builtins; fixes Dying Light and Dead Island Definitive Edition

2017-05-12 Thread John Brooks
On Sat, May 13, 2017 at 10:47:17AM +1000, Timothy Arceri wrote:
> On 13/05/17 09:55, John Brooks wrote:
> >On Sat, May 13, 2017 at 09:04:05AM +1000, Timothy Arceri wrote:
> >>On 13/05/17 00:11, John Brooks wrote:
> >>>On Fri, May 12, 2017 at 03:56:26PM +0200, Samuel Pitoiset wrote:
> 
> 
> On 05/12/2017 03:39 PM, John Brooks wrote:
> >Since release, Dying Light and Dead Island Definitive Edition have been 
> >broken
> >on Mesa, producing at best only a black screen after loading. I found 
> >that the
> >root of the problem is that their vertex shaders redeclare the GLSL 
> >builtin
> >gl_VertexID, which Mesa's compiler considers to be an error:
> >
> > error: `gl_VertexID' redeclared
> >
> >These patches make the compiler more lenient so that the shaders compile.
> >Because such redeclarations are not explicitly valid in the spec, this
> >behaviour is selectively activated by the new 
> >allow_glsl_builtin_redeclaration
> >driconf option, which has been enabled for both games in the default 
> >drirc.
> >
> >With this change, both games work on Mesa and render correctly. Note 
> >that the
> >games require OpenGL 4.4+, and so it is necessary to launch them with
> >MESA_GL_VERSION_OVERRIDE and MESA_GLSL_VERSION_OVERRIDE set to OpenGL 
> >4.4 (GLSL
> >440) or higher.
> >
> >Contrary to popular belief, this problem actually had nothing whatsoever 
> >to do
> >with compatibility profiles. Forcing Mesa to create a higher version
> >compatibility profile with MESA_GL_VERSION_OVERRIDE=4.5COMPAT or
> >allow_higher_compat_version results in graphical glitches, so don't use 
> >that.
> 
> I wonder if there is multiple versions of Dying Light, but using
> MESA_GL_VERSION_OVERRIDE=4.4 and MESA_GLSL_VERSION_OVERRIDE=440 doesn't 
> work
> for me (game crash at launching). Also it requests some unsupported GL
> functions (compat?).
> 
> IIRC, Dying Light wants a GL 4.4 compat profile, I guess Timothy can
> confirm?
> 
> What's your steam app ID?
> 
> Btw, you probably don't need to override the GL/GLSL versions, it should 
> be
> backward compatible.
> 
> >>>
> >>>Steam App ID 239140. The use of legacy functions (such as glBegin) in 
> >>>frame 0
> >>>is SDL's doing:
> >>>
> >>>
> >>>I don't know why your game would crash on launch. My first thought would be
> >>>steam runtime issues though. Make sure Steam runtime is enabled and remove
> >>>~/.local/share/Steam/ubuntu12_32/steam-runtime/amd64/usr/lib/x86_64-linux-gnu/libstdc++.so.6
> >>>
> >>>The version override is necessary since the game will not render at all 
> >>>with a
> >>>3.0 compat profile, which is what it gets without an override.
> >>
> >>Right but isn't that is because the game is requesting a compat profile?
> >>
> >>How do you know that the rendering issues you see when using the compat
> >>override are not because of missing compat support for higher GL versions?
> >>
> >>For example a feature/behavior supported in an eariler GL version may have
> >>been changed to be more like core and it just happens that overriding to use
> >>core makes the rendering problems go away.
> >>
> >
> >Nope, it's not requesting a compat profile or anything specific at all. I
> >checked with ltrace and the game calls SDL_GL_CreateContext without calling
> >SDL_GL_SetAttribute to specify a version or type. Thus, SDL just calls
> >glXCreateContext:
> >https://hg.libsdl.org/SDL/file/tip/src/video/x11/SDL_x11opengl.c#l620 >
> >The spec says nothing of what version you're supposed to get with
> >glXCreateContext, but the result with Mesa is a 3.0 compatibility profile
> >unless you override it.
> 
> That's because glXCreateContext is from a time before there was such a thing
> as compat profiles. glXCreateContextAttribsARB was introduced to solve this
> problem.
> 
> Are you suggesting other drivers don't return a compat profile in this
> scenario?
> 

No, only that it's not explicitly defined by the spec and what Mesa does is not
necessarily the same as what other drivers do. However, it is a reasonable
assumption that they also would return a compatibility profile.

The difference would be that other drivers would return a real compatibility
profile because they support it. Much has changed between OpenGL 3.0 and 4.4,
and since Mesa's implementation of the compatibility spec is strictly limited
to 3.0 (before there even was a separate compatibility spec), it's anyone's
guess what we're doing differently when presenting a faux 4.4 compatibility
profile backed by a 3.0 implementation. Maybe they use a new feature that we
implement with existing code that has a different path for 3.0 compat, but that
path isn't supposed to be used for this feature and we don't account for it
because it didn't e

Re: [Mesa-dev] [PATCH 0/2] Allow redeclaration of GLSL builtins; fixes Dying Light and Dead Island Definitive Edition

2017-05-12 Thread Timothy Arceri

On 13/05/17 09:55, John Brooks wrote:

On Sat, May 13, 2017 at 09:04:05AM +1000, Timothy Arceri wrote:

On 13/05/17 00:11, John Brooks wrote:

On Fri, May 12, 2017 at 03:56:26PM +0200, Samuel Pitoiset wrote:



On 05/12/2017 03:39 PM, John Brooks wrote:

Since release, Dying Light and Dead Island Definitive Edition have been broken
on Mesa, producing at best only a black screen after loading. I found that the
root of the problem is that their vertex shaders redeclare the GLSL builtin
gl_VertexID, which Mesa's compiler considers to be an error:

 error: `gl_VertexID' redeclared

These patches make the compiler more lenient so that the shaders compile.
Because such redeclarations are not explicitly valid in the spec, this
behaviour is selectively activated by the new allow_glsl_builtin_redeclaration
driconf option, which has been enabled for both games in the default drirc.

With this change, both games work on Mesa and render correctly. Note that the
games require OpenGL 4.4+, and so it is necessary to launch them with
MESA_GL_VERSION_OVERRIDE and MESA_GLSL_VERSION_OVERRIDE set to OpenGL 4.4 (GLSL
440) or higher.

Contrary to popular belief, this problem actually had nothing whatsoever to do
with compatibility profiles. Forcing Mesa to create a higher version
compatibility profile with MESA_GL_VERSION_OVERRIDE=4.5COMPAT or
allow_higher_compat_version results in graphical glitches, so don't use that.


I wonder if there is multiple versions of Dying Light, but using
MESA_GL_VERSION_OVERRIDE=4.4 and MESA_GLSL_VERSION_OVERRIDE=440 doesn't work
for me (game crash at launching). Also it requests some unsupported GL
functions (compat?).

IIRC, Dying Light wants a GL 4.4 compat profile, I guess Timothy can
confirm?

What's your steam app ID?

Btw, you probably don't need to override the GL/GLSL versions, it should be
backward compatible.



Steam App ID 239140. The use of legacy functions (such as glBegin) in frame 0
is SDL's doing:


I don't know why your game would crash on launch. My first thought would be
steam runtime issues though. Make sure Steam runtime is enabled and remove
~/.local/share/Steam/ubuntu12_32/steam-runtime/amd64/usr/lib/x86_64-linux-gnu/libstdc++.so.6

The version override is necessary since the game will not render at all with a
3.0 compat profile, which is what it gets without an override.


Right but isn't that is because the game is requesting a compat profile?

How do you know that the rendering issues you see when using the compat
override are not because of missing compat support for higher GL versions?

For example a feature/behavior supported in an eariler GL version may have
been changed to be more like core and it just happens that overriding to use
core makes the rendering problems go away.



Nope, it's not requesting a compat profile or anything specific at all. I
checked with ltrace and the game calls SDL_GL_CreateContext without calling
SDL_GL_SetAttribute to specify a version or type. Thus, SDL just calls
glXCreateContext:
https://hg.libsdl.org/SDL/file/tip/src/video/x11/SDL_x11opengl.c#l620 >
The spec says nothing of what version you're supposed to get with
glXCreateContext, but the result with Mesa is a 3.0 compatibility profile
unless you override it.


That's because glXCreateContext is from a time before there was such a 
thing as compat profiles. glXCreateContextAttribsARB was introduced to 
solve this problem.


Are you suggesting other drivers don't return a compat profile in this 
scenario?





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[Mesa-dev] Fix __atomic* builtins detection for Clang

2017-05-12 Thread Jan Beich
"int" isn't large enough and lack of builtins only manifests at link time.
This was breaking build on FreeBSD 11.0 i386 with Clang 3.8.0.

glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
`disk_cache_remove':
disk_cache.c:(.text+0x763): undefined reference to `__atomic_fetch_add_8'
glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
`cache_put':
disk_cache.c:(.text+0xabc): undefined reference to `__atomic_fetch_add_8'
disk_cache.c:(.text+0xec1): undefined reference to `__atomic_fetch_add_8'
c++: error: linker command failed with exit code 1 (use -v to see invocation)
---
 configure.ac | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/configure.ac b/configure.ac
index 957d15df8c..5b11941a0c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -403,9 +403,10 @@ AM_CONDITIONAL([SSE41_SUPPORTED], [test x$SSE41_SUPPORTED 
= x1])
 AC_SUBST([SSE41_CFLAGS], $SSE41_CFLAGS)
 
 dnl Check for new-style atomic builtins
-AC_COMPILE_IFELSE([AC_LANG_SOURCE([[
+AC_LINK_IFELSE([AC_LANG_SOURCE([[
+#include 
 int main() {
-int n;
+uint64_t n;
 return __atomic_load_n(&n, __ATOMIC_ACQUIRE);
 }]])], GCC_ATOMIC_BUILTINS_SUPPORTED=1)
 if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = x1; then
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[Mesa-dev] [PATCH 1/2] bin/get-fixes-pick-list.sh: parse just the commit message

2017-05-12 Thread Andres Gomez
We were parsing the whole diff, although the candidates were
identified only by the commit message.

Now, we only use the commit message for parsing.

Signed-off-by: Andres Gomez 
---
 bin/get-fixes-pick-list.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/bin/get-fixes-pick-list.sh b/bin/get-fixes-pick-list.sh
index 81b78adc9c..f9afcc49ce 100755
--- a/bin/get-fixes-pick-list.sh
+++ b/bin/get-fixes-pick-list.sh
@@ -37,10 +37,10 @@ do
fi
 
# For each one try to extract the tag
-   fixes_count=`git show $sha | grep -i "fixes:" | wc -l`
+   fixes_count=`git show -s $sha | grep -i "fixes:" | wc -l`
warn=`(test $fixes_count -gt 1 && echo $fixes_count) || echo 0`
while [ $fixes_count -gt 0 ] ; do
-   fixes=`git show $sha | grep -i "fixes:" | tail -n $fixes_count`
+   fixes=`git show -s $sha | grep -i "fixes:" | tail -n 
$fixes_count`
fixes_count=$(($fixes_count-1))
# The following sed/cut combination is borrowed from GregKH
id=`echo ${fixes} | sed -e 's/^[ \t]*//' | cut -f 2 -d ':' | 
sed -e 's/^[ \t]*//' | cut -f 1 -d ' '`
-- 
2.11.0

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[Mesa-dev] [PATCH 2/2] bin/get-fixes-pick-list.sh: better identify multiple "fixes:" tags

2017-05-12 Thread Andres Gomez
We were not considering as multiple fixes lines with:
Fixes: $sha_1, Fixes: $sha_2

Now, we split the lines so we will consider them individually, as in:
Fixes: $sha_1,
Fixes: $sha_2

Additionally, we try to get the SHA from split lines so:
Fixes:
$sha_1

Will be considered as:
Fixes: $sha_1

Signed-off-by: Andres Gomez 
---
 bin/get-fixes-pick-list.sh | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/bin/get-fixes-pick-list.sh b/bin/get-fixes-pick-list.sh
index f9afcc49ce..32d830cda0 100755
--- a/bin/get-fixes-pick-list.sh
+++ b/bin/get-fixes-pick-list.sh
@@ -36,14 +36,18 @@ do
continue
fi
 
+   # Place every "fixes:" tag on its own line and join with the next word
+   # on its line or a later one.
+   fixes=`git show -s $sha | tr -d "\n" | sed -e 's/fixes:/\nfixes:/Ig' | 
grep "fixes:" | sed -e 's/\(fixes:\)[[:space:]]*\([a-zA-Z0-9]*\).*$/\1\2/g'`
+
# For each one try to extract the tag
-   fixes_count=`git show -s $sha | grep -i "fixes:" | wc -l`
+   fixes_count=`echo "$fixes" | wc -l`
warn=`(test $fixes_count -gt 1 && echo $fixes_count) || echo 0`
while [ $fixes_count -gt 0 ] ; do
-   fixes=`git show -s $sha | grep -i "fixes:" | tail -n 
$fixes_count`
+   # Treat only the current line
+   fix=`echo "$fixes" | tail -n $fixes_count | head -n 1`
fixes_count=$(($fixes_count-1))
-   # The following sed/cut combination is borrowed from GregKH
-   id=`echo ${fixes} | sed -e 's/^[ \t]*//' | cut -f 2 -d ':' | 
sed -e 's/^[ \t]*//' | cut -f 1 -d ' '`
+   id=`echo "$fix" | cut -d : -f 2`
 
# Bail out if we cannot find suitable id.
# Any specific validation the $id is valid and not some junk, is
-- 
2.11.0

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[Mesa-dev] [PATCH 0/2] Improve get-fixes-pick-list.sh

2017-05-12 Thread Andres Gomez
Some more improvements:
 - Only parse the commit messages.
 - Split "fixes:" tags on its own lines.
 - Join in a single line split lines like "fixes:\n$sha"

Andres Gomez (2):
  bin/get-fixes-pick-list.sh: parse just the commit message
  bin/get-fixes-pick-list.sh: better identify multiple "fixes:" tags

 bin/get-fixes-pick-list.sh | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

-- 
2.11.0

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Re: [Mesa-dev] [PATCH 0/2] Allow redeclaration of GLSL builtins; fixes Dying Light and Dead Island Definitive Edition

2017-05-12 Thread John Brooks
On Sat, May 13, 2017 at 09:04:05AM +1000, Timothy Arceri wrote:
> On 13/05/17 00:11, John Brooks wrote:
> >On Fri, May 12, 2017 at 03:56:26PM +0200, Samuel Pitoiset wrote:
> >>
> >>
> >>On 05/12/2017 03:39 PM, John Brooks wrote:
> >>>Since release, Dying Light and Dead Island Definitive Edition have been 
> >>>broken
> >>>on Mesa, producing at best only a black screen after loading. I found that 
> >>>the
> >>>root of the problem is that their vertex shaders redeclare the GLSL builtin
> >>>gl_VertexID, which Mesa's compiler considers to be an error:
> >>>
> >>> error: `gl_VertexID' redeclared
> >>>
> >>>These patches make the compiler more lenient so that the shaders compile.
> >>>Because such redeclarations are not explicitly valid in the spec, this
> >>>behaviour is selectively activated by the new 
> >>>allow_glsl_builtin_redeclaration
> >>>driconf option, which has been enabled for both games in the default drirc.
> >>>
> >>>With this change, both games work on Mesa and render correctly. Note that 
> >>>the
> >>>games require OpenGL 4.4+, and so it is necessary to launch them with
> >>>MESA_GL_VERSION_OVERRIDE and MESA_GLSL_VERSION_OVERRIDE set to OpenGL 4.4 
> >>>(GLSL
> >>>440) or higher.
> >>>
> >>>Contrary to popular belief, this problem actually had nothing whatsoever 
> >>>to do
> >>>with compatibility profiles. Forcing Mesa to create a higher version
> >>>compatibility profile with MESA_GL_VERSION_OVERRIDE=4.5COMPAT or
> >>>allow_higher_compat_version results in graphical glitches, so don't use 
> >>>that.
> >>
> >>I wonder if there is multiple versions of Dying Light, but using
> >>MESA_GL_VERSION_OVERRIDE=4.4 and MESA_GLSL_VERSION_OVERRIDE=440 doesn't work
> >>for me (game crash at launching). Also it requests some unsupported GL
> >>functions (compat?).
> >>
> >>IIRC, Dying Light wants a GL 4.4 compat profile, I guess Timothy can
> >>confirm?
> >>
> >>What's your steam app ID?
> >>
> >>Btw, you probably don't need to override the GL/GLSL versions, it should be
> >>backward compatible.
> >>
> >
> >Steam App ID 239140. The use of legacy functions (such as glBegin) in frame 0
> >is SDL's doing:
> >
> >
> >I don't know why your game would crash on launch. My first thought would be
> >steam runtime issues though. Make sure Steam runtime is enabled and remove
> >~/.local/share/Steam/ubuntu12_32/steam-runtime/amd64/usr/lib/x86_64-linux-gnu/libstdc++.so.6
> >
> >The version override is necessary since the game will not render at all with 
> >a
> >3.0 compat profile, which is what it gets without an override.
> 
> Right but isn't that is because the game is requesting a compat profile?
> 
> How do you know that the rendering issues you see when using the compat
> override are not because of missing compat support for higher GL versions?
> 
> For example a feature/behavior supported in an eariler GL version may have
> been changed to be more like core and it just happens that overriding to use
> core makes the rendering problems go away.
> 

Nope, it's not requesting a compat profile or anything specific at all. I
checked with ltrace and the game calls SDL_GL_CreateContext without calling
SDL_GL_SetAttribute to specify a version or type. Thus, SDL just calls
glXCreateContext:
https://hg.libsdl.org/SDL/file/tip/src/video/x11/SDL_x11opengl.c#l620

The spec says nothing of what version you're supposed to get with
glXCreateContext, but the result with Mesa is a 3.0 compatibility profile
unless you override it.

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[Mesa-dev] [PATCH 19/24] i965/cnl: Restore lossless compression for sRGB formats

2017-05-12 Thread Anuj Phogat
From: Ben Widawsky 

This support was removed on gen9 (it worked before then) and was brought back
for gen10.

Signed-off-by: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index db0a397..bf71efd 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -207,7 +207,7 @@ intel_miptree_supports_non_msrt_fast_clear(struct 
brw_context *brw,
if (!brw->format_supported_as_render_target[mt->format])
   return false;
 
-   if (brw->gen >= 9) {
+   if (brw->gen == 9) {
   mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
   const uint32_t brw_format = 
brw_isl_format_for_mesa_format(linear_format);
   return isl_format_supports_ccs_e(&brw->screen->devinfo, brw_format);
-- 
2.9.3

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[Mesa-dev] [PATCH 21/24] i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3

2017-05-12 Thread Anuj Phogat
v1: By Ben Widawsky 
v2: Add the restriction for GS, HS and DS and make sure
the allocated sizes are not multiple of 3.

Signed-off-by: Anuj Phogat 
Cc: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/gen7_urb.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c 
b/src/mesa/drivers/dri/i965/gen7_urb.c
index 028161d..dc6826a 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -194,6 +194,17 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
   entry_size[i] = prog_data[i] ? prog_data[i]->urb_entry_size : 1;
}
 
+   /* For Cannonlake:
+* Software shall not program an allocation size that specifies a size
+* that is a multiple of 3 64B (512-bit) cachelines.
+*/
+   if (brw->gen == 10) {
+  for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
+ if (entry_size[i] % 3 == 0)
+entry_size[i]++;
+  }
+   }
+
/* If we're just switching between programs with the same URB requirements,
 * skip the rest of the logic.
 */
@@ -224,6 +235,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
 
BEGIN_BATCH(8);
for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
+  assert(brw->gen != 10 || entry_size[i] % 3);
   OUT_BATCH((_3DSTATE_URB_VS + i) << 16 | (2 - 2));
   OUT_BATCH(entries[i] |
 ((entry_size[i] - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
-- 
2.9.3

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[Mesa-dev] [PATCH 23/24] i965/cnl: Enable CCS_E and RT support for few formats

2017-05-12 Thread Anuj Phogat
Suggested-by: Jason Ekstrand 
Signed-off-by: Anuj Phogat 
---
 src/intel/isl/isl_format.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index a26873b..e9ca7f1 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -95,7 +95,7 @@ static const struct surface_format_info format_info[] = {
SF(  x,   x,   x,   x,   x,   x,   Y,   x,   x,   x,   x,   x,   
R32G32B32A32_UNORM)
SF(  x,   x,   x,   x,   x,   x,   Y,   x,   x,   x,   x,   x,   
R32G32B32A32_SNORM)
SF(  x,   x,   x,   x,   x,   x,   Y,   x,   x,   x,   x,   x,   
R64G64_FLOAT)
-   SF(  Y,  50,   x,   x,   x,   x,   x,   x,   x,   x,   x,   x,   
R32G32B32X32_FLOAT)
+   SF(  Y,  50,   x,   x, 100, 100,   x,   x,   x,   x,   x, 100,   
R32G32B32X32_FLOAT)
SF(  x,   x,   x,   x,   x,   x,   Y,   x,   x,   x,   x,   x,   
R32G32B32A32_SSCALED)
SF(  x,   x,   x,   x,   x,   x,   Y,   x,   x,   x,   x,   x,   
R32G32B32A32_USCALED)
SF(  x,   x,   x,   x,   x,   x,  75,   x,   x,   x,   x,   x,   
R32G32B32A32_SFIXED)
@@ -135,14 +135,14 @@ static const struct surface_format_info format_info[] = {
SF(  x,   x,   x,   x,   x,   x,  75,   x,   x,   x,   x,   x,   
R32G32_SFIXED)
SF(  x,   x,   x,   x,   x,   x,  80,   x,   x,   x,   x,   x,   
R64_PASSTHRU)
SF(  Y,   Y,   x,   Y,   Y,   Y,   Y,   x,  60,  70,   x,  90,   
B8G8R8A8_UNORM)
-   SF(  Y,   Y,   x,   x,   Y,   Y,   x,   x,   x,   x,   x,   x,   
B8G8R8A8_UNORM_SRGB)
+   SF(  Y,   Y,   x,   x,   Y,   Y,   x,   x,   x,   x,   x, 100,   
B8G8R8A8_UNORM_SRGB)
 /*smpl filt  shad  CK   RT   AB   VB   SO color TW   TR  ccs_e */
-   SF(  Y,   Y,   x,   x,   Y,   Y,   Y,   x,  60,  70,   x,   x,   
R10G10B10A2_UNORM)
+   SF(  Y,   Y,   x,   x,   Y,   Y,   Y,   x,  60,  70,   x, 100,   
R10G10B10A2_UNORM)
SF(  Y,   Y,   x,   x,   x,   x,   x,   x,  60,   x,   x,   x,   
R10G10B10A2_UNORM_SRGB)
-   SF(  Y,   x,   x,   x,   Y,   x,   Y,   x,   x,  70,   x,   x,   
R10G10B10A2_UINT)
+   SF(  Y,   x,   x,   x,   Y,   x,   Y,   x,   x,  70,   x, 100,   
R10G10B10A2_UINT)
SF(  Y,   Y,   x,   x,   x,   x,   Y,   x,   x,   x,   x,   x,   
R10G10B10_SNORM_A2_UNORM)
SF(  Y,   Y,   x,   x,   Y,   Y,   Y,   x,  60,  70,   x,  90,   
R8G8B8A8_UNORM)
-   SF(  Y,   Y,   x,   x,   Y,   Y,   x,   x,  60,   x,   x,   x,   
R8G8B8A8_UNORM_SRGB)
+   SF(  Y,   Y,   x,   x,   Y,   Y,   x,   x,  60,   x,   x, 100,   
R8G8B8A8_UNORM_SRGB)
SF(  Y,   Y,   x,   x,   Y,  60,   Y,   x,   x,  70,   x,  90,   
R8G8B8A8_SNORM)
SF(  Y,   x,   x,   x,   Y,   x,   Y,   x,   x,  70,  90,  90,   
R8G8B8A8_SINT)
SF(  Y,   x,   x,   x,   Y,   x,   Y,   x,   x,  70,  75,  90,   
R8G8B8A8_UINT)
@@ -151,9 +151,9 @@ static const struct surface_format_info format_info[] = {
SF(  Y,   x,   x,   x,   Y,   x,   Y,   x,   x,  70,  90,  90,   
R16G16_SINT)
SF(  Y,   x,   x,   x,   Y,   x,   Y,   x,   x,  70,  75,  90,   
R16G16_UINT)
SF(  Y,   Y,   x,   x,   Y,   Y,   Y,   x,   x,  70,  90,  90,   
R16G16_FLOAT)
-   SF(  Y,   Y,   x,   x,   Y,   Y,  75,   x,  60,  70,   x,   x,   
B10G10R10A2_UNORM)
-   SF(  Y,   Y,   x,   x,   Y,   Y,   x,   x,  60,   x,   x,   x,   
B10G10R10A2_UNORM_SRGB)
-   SF(  Y,   Y,   x,   x,   Y,   Y,   Y,   x,   x,  70,   x,   x,   
R11G11B10_FLOAT)
+   SF(  Y,   Y,   x,   x,   Y,   Y,  75,   x,  60,  70,   x, 100,   
B10G10R10A2_UNORM)
+   SF(  Y,   Y,   x,   x,   Y,   Y,   x,   x,  60,   x,   x, 100,   
B10G10R10A2_UNORM_SRGB)
+   SF(  Y,   Y,   x,   x,   Y,   Y,   Y,   x,   x,  70,   x, 100,   
R11G11B10_FLOAT)
SF(  Y,   x,   x,   x,   Y,   x,   Y,   Y,   x,  70,  70,  90,   R32_SINT)
SF(  Y,   x,   x,   x,   Y,   x,   Y,   Y,   x,  70,  70,  90,   R32_UINT)
SF(  Y,  50,   Y,   x,   Y,   Y,   Y,   Y,   x,  70,  70,  90,   R32_FLOAT)
@@ -167,7 +167,7 @@ static const struct surface_format_info format_info[] = {
SF(  Y,  50,   Y,   x,   x,   x,   x,   x,   x,   x,   x,   x,   L32_FLOAT)
SF(  Y,  50,   Y,   x,   x,   x,   x,   x,   x,   x,   x,   x,   A32_FLOAT)
SF(  Y,   Y,   x,   Y,  80,  80,   x,   x,  60,   x,   x,  90,   
B8G8R8X8_UNORM)
-   SF(  Y,   Y,   x,   x,  80,  80,   x,   x,   x,   x,   x,   x,   
B8G8R8X8_UNORM_SRGB)
+   SF(  Y,   Y,   x,   x,  80,  80,   x,   x,   x,   x,   x, 100,   
B8G8R8X8_UNORM_SRGB)
SF(  Y,   Y,   x,   x,   x,   x,   x,   x,   x,   x,   x,   x,   
R8G8B8X8_UNORM)
SF(  Y,   Y,   x,   x,   x,   x,   x,   x,   x,   x,   x,   x,   
R8G8B8X8_UNORM_SRGB)
SF(  Y,   Y,   x,   x,   x,   x,   x,   x,   x,   x,   x,   x,   
R9G9B9E5_SHAREDEXP)
-- 
2.9.3

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[Mesa-dev] [PATCH 12/24] i965/cnl: Add cnl bits in aubinator

2017-05-12 Thread Anuj Phogat
Signed-off-by: Anuj Phogat 
---
 src/intel/tools/aubinator.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 53b2a27..d15476d 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -970,7 +970,8 @@ struct {
{ "bdw", MAKE_GEN(8, 0) },
{ "skl", MAKE_GEN(9, 0) },
{ "chv", MAKE_GEN(8, 0) },
-   { "bxt", MAKE_GEN(9, 0) }
+   { "bxt", MAKE_GEN(9, 0) },
+   { "cnl", MAKE_GEN(10, 0) }
 };
 
 enum {
@@ -1138,7 +1139,7 @@ print_help(const char *progname, FILE *file)
"Decode aub file contents from either FILE or the standard 
input.\n\n"
"A valid --gen option must be provided.\n\n"
"  --help  display this help and exit\n"
-   "  --gen=platform  decode for given platform (ivb, byt, hsw, 
bdw, chv, skl, kbl or bxt)\n"
+   "  --gen=platform  decode for given platform (ivb, byt, hsw, 
bdw, chv, skl, kbl, bxt or cnl)\n"
"  --headers   decode only command headers\n"
"  --color[=WHEN]  colorize the output; WHEN can be 'auto' 
(default\n"
"if omitted), 'always', or 'never'\n"
@@ -1166,7 +1167,8 @@ int main(int argc, char *argv[])
   { "chv", 0x22B3 }, /* Intel(R) HD Graphics (Cherryview) */
   { "skl", 0x1912 }, /* Intel(R) HD Graphics 530 (Skylake GT2) */
   { "kbl", 0x591D }, /* Intel(R) Kabylake GT2 */
-  { "bxt", 0x0A84 }  /* Intel(R) HD Graphics (Broxton) */
+  { "bxt", 0x0A84 },  /* Intel(R) HD Graphics (Broxton) */
+  { "cnl", 0x5A52 }  /* Intel(R) HD Graphics (Cannonlake) */
};
const struct option aubinator_opts[] = {
   { "help",   no_argument,   (int *) &help, true },
-- 
2.9.3

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[Mesa-dev] [PATCH 20/24] i965/cnl: Don't resolve single sampled color rb in case of sRGB formats

2017-05-12 Thread Anuj Phogat
As sRGB now supports lossless compression, don't we also need to stop
resolving single sampled color render buffers for sRGB formats in Gen 10.

Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 1247d03..9e19617 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -326,7 +326,7 @@ intel_update_state(struct gl_context * ctx, GLuint 
new_state)
 * enabled because otherwise the surface state will be programmed with the
 * linear equivalent format anyway.
 */
-   if (brw->gen >= 9 && ctx->Color.sRGBEnabled) {
+   if (brw->gen == 9 && ctx->Color.sRGBEnabled) {
   struct gl_framebuffer *fb = ctx->DrawBuffer;
   for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {
  struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[i];
-- 
2.9.3

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[Mesa-dev] [PATCH 13/24] i965/cnl: Update few assertions

2017-05-12 Thread Anuj Phogat
Signed-off-by: Anuj Phogat 
---
 src/intel/compiler/brw_compiler.h   | 2 +-
 src/mesa/drivers/dri/i965/brw_program.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_compiler.h 
b/src/intel/compiler/brw_compiler.h
index b5b1ee9..d6bbda1 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -1042,7 +1042,7 @@ brw_stage_has_packed_dispatch(const struct 
gen_device_info *devinfo,
 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
 * the NIR front-end before changing this assertion.
 */
-   assert(devinfo->gen <= 9);
+   assert(devinfo->gen <= 10);
 
switch (stage) {
case MESA_SHADER_FRAGMENT: {
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index d26dce0..f442d55 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -290,7 +290,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield 
barriers)
unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
 PIPE_CONTROL_NO_WRITE |
 PIPE_CONTROL_CS_STALL);
-   assert(brw->gen >= 7 && brw->gen <= 9);
+   assert(brw->gen >= 7 && brw->gen <= 10);
 
if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
GL_ELEMENT_ARRAY_BARRIER_BIT |
-- 
2.9.3

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[Mesa-dev] [PATCH 15/24] i965/cnl: Start using CNL MOCS defines

2017-05-12 Thread Anuj Phogat
They are the duplicates of SKL MOCS defines.

Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_blorp.c| 7 ++-
 src/mesa/drivers/dri/i965/brw_state.h| 8 
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 ++
 src/mesa/drivers/dri/i965/genX_state_upload.c| 4 +++-
 4 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 8a6cc66..eae925f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -94,12 +94,17 @@ brw_blorp_init(struct brw_context *brw)
   brw->blorp.exec = gen8_blorp_exec;
   break;
case 9:
-   case 10:
   brw->blorp.mocs.tex = SKL_MOCS_WB;
   brw->blorp.mocs.rb = SKL_MOCS_PTE;
   brw->blorp.mocs.vb = SKL_MOCS_WB;
   brw->blorp.exec = gen9_blorp_exec;
   break;
+   case 10:
+  brw->blorp.mocs.tex = CNL_MOCS_WB;
+  brw->blorp.mocs.rb = CNL_MOCS_PTE;
+  brw->blorp.mocs.vb = CNL_MOCS_WB;
+  brw->blorp.exec = gen9_blorp_exec;
+  break;
default:
   unreachable("Invalid gen");
}
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 4592e3e..4503946 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -410,6 +410,14 @@ void upload_gs_state_for_tf(struct brw_context *brw);
 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
 #define SKL_MOCS_PTE (1 << 1)
 
+/* Cannonlake: MOCS is now an index into an array of 62 different caching
+ * configurations programmed by the kernel.
+ */
+/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
+#define CNL_MOCS_WB  (2 << 1)
+/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
+#define CNL_MOCS_PTE (1 << 1)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c95fb37..c1003cd 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -64,12 +64,14 @@ uint32_t tex_mocs[] = {
[7] = GEN7_MOCS_L3,
[8] = BDW_MOCS_WB,
[9] = SKL_MOCS_WB,
+   [10] = CNL_MOCS_WB,
 };
 
 uint32_t rb_mocs[] = {
[7] = GEN7_MOCS_L3,
[8] = BDW_MOCS_PTE,
[9] = SKL_MOCS_PTE,
+   [10] = CNL_MOCS_PTE,
 };
 
 static void
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 6619d4d..5710878 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -333,7 +333,9 @@ genX(emit_vertex_buffer_state)(struct brw_context *brw,
 #endif
 #endif
 
-#if GEN_GEN == 9
+#if GEN_GEN == 10
+  .VertexBufferMOCS = CNL_MOCS_WB,
+#elif GEN_GEN == 9
   .VertexBufferMOCS = SKL_MOCS_WB,
 #elif GEN_GEN == 8
   .VertexBufferMOCS = BDW_MOCS_WB,
-- 
2.9.3

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[Mesa-dev] [PATCH 16/24] i965/cnl: Start using gen10 specific functions

2017-05-12 Thread Anuj Phogat
gen10 specific functions:
isl_gen10*()
gen10_blorp_exec()
gen10_init_atoms()

Signed-off-by: Anuj Phogat 
---
 src/intel/isl/isl.c  | 12 +---
 src/mesa/drivers/dri/i965/brw_blorp.c|  2 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c |  4 +++-
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 5dc41fa..0ae72a4 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1672,9 +1672,11 @@ isl_surf_fill_state_s(const struct isl_device *dev, void 
*state,
   isl_gen8_surf_fill_state_s(dev, state, info);
   break;
case 9:
-   case 10:
   isl_gen9_surf_fill_state_s(dev, state, info);
   break;
+   case 10:
+  isl_gen10_surf_fill_state_s(dev, state, info);
+  break;
default:
   assert(!"Cannot fill surface state for this gen");
}
@@ -1704,9 +1706,11 @@ isl_buffer_fill_state_s(const struct isl_device *dev, 
void *state,
   isl_gen8_buffer_fill_state_s(state, info);
   break;
case 9:
-   case 10:
   isl_gen9_buffer_fill_state_s(state, info);
   break;
+   case 10:
+  isl_gen10_buffer_fill_state_s(state, info);
+  break;
default:
   assert(!"Cannot fill surface state for this gen");
}
@@ -1772,9 +1776,11 @@ isl_emit_depth_stencil_hiz_s(const struct isl_device 
*dev, void *batch,
   isl_gen8_emit_depth_stencil_hiz_s(dev, batch, info);
   break;
case 9:
-   case 10:
   isl_gen9_emit_depth_stencil_hiz_s(dev, batch, info);
   break;
+   case 10:
+  isl_gen10_emit_depth_stencil_hiz_s(dev, batch, info);
+  break;
default:
   assert(!"Cannot fill surface state for this gen");
}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index eae925f..bcc72df 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -103,7 +103,7 @@ brw_blorp_init(struct brw_context *brw)
   brw->blorp.mocs.tex = CNL_MOCS_WB;
   brw->blorp.mocs.rb = CNL_MOCS_PTE;
   brw->blorp.mocs.vb = CNL_MOCS_WB;
-  brw->blorp.exec = gen9_blorp_exec;
+  brw->blorp.exec = gen10_blorp_exec;
   break;
default:
   unreachable("Invalid gen");
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index bcb7ff1..35962df 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -134,7 +134,9 @@ void brw_init_state( struct brw_context *brw )
 
brw_init_caches(brw);
 
-   if (brw->gen >= 9)
+   if (brw->gen >= 10)
+  gen10_init_atoms(brw);
+   else if (brw->gen >= 9)
   gen9_init_atoms(brw);
else if (brw->gen >= 8)
   gen8_init_atoms(brw);
-- 
2.9.3

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[Mesa-dev] [PATCH 04/24] i965/cnl: Define genX(x) and GENX(x) for gen10

2017-05-12 Thread Anuj Phogat
Signed-off-by: Anuj Phogat 
---
 src/intel/genxml/gen_macros.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/intel/genxml/gen_macros.h b/src/intel/genxml/gen_macros.h
index b4941b9..a85c082 100644
--- a/src/intel/genxml/gen_macros.h
+++ b/src/intel/genxml/gen_macros.h
@@ -85,6 +85,9 @@
 #elif (GEN_VERSIONx10 == 90)
 #  define GENX(X) GEN9_##X
 #  define genX(x) gen9_##x
+#elif (GEN_VERSIONx10 == 100)
+#  define GENX(X) GEN10_##X
+#  define genX(x) gen10_##x
 #else
 #  error "Need to add prefixing macros for this gen"
 #endif
-- 
2.9.3

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[Mesa-dev] [PATCH 22/24] i965/cnl: Reformat surface_format_info table to accomodate gen10+

2017-05-12 Thread Anuj Phogat
Signed-off-by: Anuj Phogat 
---
 src/intel/isl/isl_format.c | 498 ++---
 1 file changed, 249 insertions(+), 249 deletions(-)

diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 165c7e5..a26873b 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -88,259 +88,259 @@ struct surface_format_info {
  * - Render Target Surface Types [SKL+]
  */
 static const struct surface_format_info format_info[] = {
-/* smpl filt shad CK  RT  AB  VB  SO  color TW  TR  ccs_e */
-   SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x,   70, 90, 90,   R32G32B32A32_FLOAT)
-   SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x,   70, 90, 90,   R32G32B32A32_SINT)
-   SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x,   70, 90, 90,   R32G32B32A32_UINT)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32B32A32_UNORM)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32B32A32_SNORM)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R64G64_FLOAT)
-   SF( Y, 50,  x,  x,  x,  x,  x,  x,  x,x,  x,  x,   R32G32B32X32_FLOAT)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32B32A32_SSCALED)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32B32A32_USCALED)
-   SF( x,  x,  x,  x,  x,  x, 75,  x,  x,x,  x,  x,   R32G32B32A32_SFIXED)
-   SF( x,  x,  x,  x,  x,  x, 80,  x,  x,x,  x,  x,   R64G64_PASSTHRU)
-   SF( Y, 50,  x,  x,  x,  x,  Y,  Y,  x,x,  x,  x,   R32G32B32_FLOAT)
-   SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x,x,  x,  x,   R32G32B32_SINT)
-   SF( Y,  x,  x,  x,  x,  x,  Y,  Y,  x,x,  x,  x,   R32G32B32_UINT)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32B32_UNORM)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32B32_SNORM)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32B32_SSCALED)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32B32_USCALED)
-   SF( x,  x,  x,  x,  x,  x, 75,  x,  x,x,  x,  x,   R32G32B32_SFIXED)
-   SF( Y,  Y,  x,  x,  Y, 45,  Y,  x, 60,   70,  x, 90,   R16G16B16A16_UNORM)
-   SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x,   70,  x, 90,   R16G16B16A16_SNORM)
-   SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x,   70, 90, 90,   R16G16B16A16_SINT)
-   SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x,   70, 75, 90,   R16G16B16A16_UINT)
-   SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x,  x,   70, 90, 90,   R16G16B16A16_FLOAT)
-   SF( Y, 50,  x,  x,  Y,  Y,  Y,  Y,  x,   70, 90, 90,   R32G32_FLOAT)
-   SF( Y, 70,  x,  x,  Y,  Y,  Y,  Y,  x,x,  x,  x,   R32G32_FLOAT_LD)
-   SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x,   70, 90, 90,   R32G32_SINT)
-   SF( Y,  x,  x,  x,  Y,  x,  Y,  Y,  x,   70, 90, 90,   R32G32_UINT)
-   SF( Y, 50,  Y,  x,  x,  x,  x,  x,  x,x,  x,  x,   
R32_FLOAT_X8X24_TYPELESS)
-   SF( Y,  x,  x,  x,  x,  x,  x,  x,  x,x,  x,  x,   
X32_TYPELESS_G8X24_UINT)
-   SF( Y, 50,  x,  x,  x,  x,  x,  x,  x,x,  x,  x,   L32A32_FLOAT)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32_UNORM)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32_SNORM)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R64_FLOAT)
-   SF( Y,  Y,  x,  x,  x,  x,  x,  x,  x,x,  x,  x,   R16G16B16X16_UNORM)
-   SF( Y,  Y,  x,  x, 90, 90,  x,  x,  x,x,  x, 90,   R16G16B16X16_FLOAT)
-   SF( Y, 50,  x,  x,  x,  x,  x,  x,  x,x,  x,  x,   A32X32_FLOAT)
-   SF( Y, 50,  x,  x,  x,  x,  x,  x,  x,x,  x,  x,   L32X32_FLOAT)
-   SF( Y, 50,  x,  x,  x,  x,  x,  x,  x,x,  x,  x,   I32X32_FLOAT)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R16G16B16A16_SSCALED)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R16G16B16A16_USCALED)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32_SSCALED)
-   SF( x,  x,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   R32G32_USCALED)
-   SF( x,  x,  x,  x,  x,  x, 75,  x,  x,x,  x,  x,   R32G32_SFIXED)
-   SF( x,  x,  x,  x,  x,  x, 80,  x,  x,x,  x,  x,   R64_PASSTHRU)
-   SF( Y,  Y,  x,  Y,  Y,  Y,  Y,  x, 60,   70,  x, 90,   B8G8R8A8_UNORM)
-   SF( Y,  Y,  x,  x,  Y,  Y,  x,  x,  x,x,  x,  x,   B8G8R8A8_UNORM_SRGB)
-/* smpl filt shad CK  RT  AB  VB  SO  color TW  TR  ccs_e */
-   SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60,   70,  x,  x,   R10G10B10A2_UNORM)
-   SF( Y,  Y,  x,  x,  x,  x,  x,  x, 60,x,  x,  x,   
R10G10B10A2_UNORM_SRGB)
-   SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x,   70,  x,  x,   R10G10B10A2_UINT)
-   SF( Y,  Y,  x,  x,  x,  x,  Y,  x,  x,x,  x,  x,   
R10G10B10_SNORM_A2_UNORM)
-   SF( Y,  Y,  x,  x,  Y,  Y,  Y,  x, 60,   70,  x, 90,   R8G8B8A8_UNORM)
-   SF( Y,  Y,  x,  x,  Y,  Y,  x,  x, 60,x,  x,  x,   R8G8B8A8_UNORM_SRGB)
-   SF( Y,  Y,  x,  x,  Y, 60,  Y,  x,  x,   70,  x, 90,   R8G8B8A8_SNORM)
-   SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x,   70, 90, 90,   R8G8B8A8_SINT)
-   SF( Y,  x,  x,  x,  Y,  x,  Y,  x,  x,   70, 75, 90,   R8G8B8A8_UINT)
-   SF( Y,  Y,  x,  x,  Y, 45,  Y,  x,  x,   70,  x, 90,   R16G16_UNORM)
-

[Mesa-dev] [PATCH 07/24] i965/cnl: Update the script generating genX_bits.h

2017-05-12 Thread Anuj Phogat
Signed-off-by: Anuj Phogat 
Reviewed-by: Jason Ekstrand 
---
 src/intel/genxml/gen_bits_header.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/genxml/gen_bits_header.py 
b/src/intel/genxml/gen_bits_header.py
index ac8ec4c..2fb5f0c 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -80,6 +80,7 @@ static inline uint32_t ATTRIBUTE_PURE
 ${item.token_name}_${prop}(const struct gen_device_info *devinfo)
 {
switch (devinfo->gen) {
+   case 10: return ${item.get_prop(prop, 10)};
case 9: return ${item.get_prop(prop, 9)};
case 8: return ${item.get_prop(prop, 8)};
case 7:
@@ -168,9 +169,8 @@ class Gen(object):
 def __init__(self, z):
 # Convert potential "major.minor" string
 z = float(z)
-if z < 10:
-z *= 10
-self.tenx = int(z)
+z *= 10
+self.tenx = int(float(z) * 10)
 
 def __lt__(self, other):
 return self.tenx < other.tenx
-- 
2.9.3

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[Mesa-dev] [PATCH 24/24] i965: Simplify get_l3_way_size() function

2017-05-12 Thread Anuj Phogat
Cherryview and Broxton are always gt1. So, remove the redundant checks.

Signed-off-by: Anuj Phogat 
---
 src/intel/common/gen_l3_config.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 4fe3503..0720079 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -258,13 +258,11 @@ get_l3_way_size(const struct gen_device_info *devinfo)
if (devinfo->is_baytrail)
   return 2;
 
-   else if (devinfo->gt == 1 ||
-devinfo->is_cherryview ||
-devinfo->is_broxton)
-  return 4;
+   /* Cherryview and Broxton are always gt1 */
+   if (devinfo->gt == 1)
+   return 4;
 
-   else
-  return 8 * devinfo->num_slices;
+   return 8 * devinfo->num_slices;
 }
 
 /**
-- 
2.9.3

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[Mesa-dev] [PATCH 11/24] i965/cnl: Add pci id for INTEL_DEVID_OVERRIDE

2017-05-12 Thread Anuj Phogat
Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 3717728..65a0b5c 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1800,6 +1800,7 @@ parse_devid_override(const char *devid_override)
   { "bdw", 0x162e },
   { "skl", 0x1912 },
   { "kbl", 0x5912 },
+  { "cnl", 0x5a52 },
};
 
for (unsigned i = 0; i < ARRAY_SIZE(name_map); i++) {
-- 
2.9.3

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[Mesa-dev] [PATCH 09/24] i965/cnl: Wire up Mesa build files for gen10

2017-05-12 Thread Anuj Phogat
Signed-off-by: Anuj Phogat 
---
 src/intel/Makefile.isl.am  |  4 
 src/intel/Makefile.sources | 12 ++--
 src/intel/Makefile.vulkan.am   |  7 ++-
 src/mesa/drivers/dri/i965/Makefile.am  |  6 +-
 src/mesa/drivers/dri/i965/Makefile.sources |  4 
 5 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/src/intel/Makefile.isl.am b/src/intel/Makefile.isl.am
index ee2215d..31273af 100644
--- a/src/intel/Makefile.isl.am
+++ b/src/intel/Makefile.isl.am
@@ -27,6 +27,7 @@ ISL_GEN_LIBS =   \
isl/libisl-gen75.la  \
isl/libisl-gen8.la   \
isl/libisl-gen9.la   \
+   isl/libisl-gen10.la  \
$(NULL)
 
 noinst_LTLIBRARIES += $(ISL_GEN_LIBS) isl/libisl.la
@@ -55,6 +56,9 @@ isl_libisl_gen8_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=80
 isl_libisl_gen9_la_SOURCES = $(ISL_GEN9_FILES)
 isl_libisl_gen9_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=90
 
+isl_libisl_gen10_la_SOURCES = $(ISL_GEN10_FILES)
+isl_libisl_gen10_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=100
+
 BUILT_SOURCES += $(ISL_GENERATED_FILES)
 
 isl/isl_format_layout.c: isl/gen_format_layout.py \
diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 83200c3..6beea80 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -117,7 +117,8 @@ GENXML_XML_FILES = \
genxml/gen7.xml \
genxml/gen75.xml \
genxml/gen8.xml \
-   genxml/gen9.xml
+   genxml/gen9.xml \
+   genxml/gen10.xml
 
 GENXML_GENERATED_PACK_FILES = \
genxml/gen4_pack.h \
@@ -127,7 +128,8 @@ GENXML_GENERATED_PACK_FILES = \
genxml/gen7_pack.h \
genxml/gen75_pack.h \
genxml/gen8_pack.h \
-   genxml/gen9_pack.h
+   genxml/gen9_pack.h \
+   genxml/gen10_pack.h
 
 GENXML_GENERATED_FILES = \
$(GENXML_GENERATED_PACK_FILES) \
@@ -179,6 +181,12 @@ ISL_GEN9_FILES = \
isl/isl_emit_depth_stencil.c \
isl/isl_surface_state.c
 
+ISL_GEN10_FILES = \
+   isl/isl_gen10.c \
+   isl/isl_gen10.h \
+   isl/isl_emit_depth_stencil.c \
+   isl/isl_surface_state.c
+
 ISL_GENERATED_FILES = \
isl/isl_format_layout.c
 
diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index ba6ab4f..ae332d9 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -72,7 +72,8 @@ VULKAN_PER_GEN_LIBS = \
vulkan/libanv-gen7.la \
vulkan/libanv-gen75.la \
vulkan/libanv-gen8.la \
-   vulkan/libanv-gen9.la
+   vulkan/libanv-gen9.la \
+   vulkan/libanv-gen10.la
 
 noinst_LTLIBRARIES += $(VULKAN_PER_GEN_LIBS)
 
@@ -107,6 +108,10 @@ vulkan_libanv_gen9_la_CFLAGS = $(VULKAN_CFLAGS)
 vulkan_libanv_gen9_la_CPPFLAGS = $(VULKAN_CPPFLAGS) -DGEN_VERSIONx10=90
 vulkan_libanv_gen9_la_SOURCES = $(VULKAN_GEN9_FILES)
 
+vulkan_libanv_gen10_la_CFLAGS = $(VULKAN_CFLAGS)
+vulkan_libanv_gen10_la_CPPFLAGS = $(VULKAN_CPPFLAGS) -DGEN_VERSIONx10=100
+vulkan_libanv_gen10_la_SOURCES = $(VULKAN_GEN10_FILES)
+
 VULKAN_SOURCES = \
$(VULKAN_GENERATED_FILES) \
$(VULKAN_FILES)
diff --git a/src/mesa/drivers/dri/i965/Makefile.am 
b/src/mesa/drivers/dri/i965/Makefile.am
index 762aefc..c29cc59 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -53,7 +53,8 @@ I965_PERGEN_LIBS = \
libi965_gen7.la \
libi965_gen75.la \
libi965_gen8.la \
-   libi965_gen9.la
+   libi965_gen9.la \
+   libi965_gen10.la
 
 libi965_gen4_la_SOURCES = $(i965_gen4_FILES)
 libi965_gen4_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=40
@@ -79,6 +80,9 @@ libi965_gen8_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=80
 libi965_gen9_la_SOURCES = $(i965_gen9_FILES)
 libi965_gen9_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=90
 
+libi965_gen10_la_SOURCES = $(i965_gen10_FILES)
+libi965_gen10_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=100
+
 noinst_LTLIBRARIES = \
libi965_dri.la \
$(I965_PERGEN_LIBS)
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 9e567cb..e35a732 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -164,6 +164,10 @@ i965_gen9_FILES = \
genX_blorp_exec.c \
genX_state_upload.c
 
+i965_gen10_FILES = \
+   genX_blorp_exec.c \
+   genX_state_upload.c
+
 i965_oa_GENERATED_FILES = \
brw_oa_hsw.h \
brw_oa_hsw.c
-- 
2.9.3

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[Mesa-dev] [PATCH 17/24] i965/cnl: Implement new pipe control workaround

2017-05-12 Thread Anuj Phogat
From: Ben Widawsky 

GEN10 requires flushing all previous pipe controls before issuing a render
target cache flush. The docs seem to fairly explicitly say this is gen10 only.

V2 (by Anuj): Use flags & PIPE_CONTROL_RENDER_TARGET_FLUSH check. (Ilia)
  Use recursive call to brw_emit_pipe_control_flush().

Signed-off-by: Ben Widawsky 
Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_pipe_control.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index f4ede2d..ecf2fac 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -128,6 +128,17 @@ brw_emit_pipe_control_flush(struct brw_context *brw, 
uint32_t flags)
  brw_emit_pipe_control_flush(brw, 0);
   }
 
+  if (brw->gen == 10 && (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
+/* Hardware workaround: CNL
+ *
+ * "Before sending a PIPE_CONTROL command with bit 12 set, SW
+ * must issue another PIPE_CONTROL with Render Target Cache
+ * Flush Enable (bit 12) = 0 and Pipe Control Flush Enable
+ * (bit 7) = 1."
+ */
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
+  }
+
   BEGIN_BATCH(6);
   OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
   OUT_BATCH(flags);
-- 
2.9.3

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[Mesa-dev] [PATCH 08/24] i965/cnl: Add isl_gen10 header and source files

2017-05-12 Thread Anuj Phogat
Signed-off-by: Anuj Phogat 
---
 src/intel/isl/isl_gen10.c | 41 +
 src/intel/isl/isl_gen10.h | 45 +
 2 files changed, 86 insertions(+)
 create mode 100644 src/intel/isl/isl_gen10.c
 create mode 100644 src/intel/isl/isl_gen10.h

diff --git a/src/intel/isl/isl_gen10.c b/src/intel/isl/isl_gen10.c
new file mode 100644
index 000..3652d58
--- /dev/null
+++ b/src/intel/isl/isl_gen10.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2017 Intel Corporation
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining a
+ *  copy of this software and associated documentation files (the "Software"),
+ *  to deal in the Software without restriction, including without limitation
+ *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ *  Software is furnished to do so, subject to the following conditions:
+ *
+ *  The above copyright notice and this permission notice (including the next
+ *  paragraph) shall be included in all copies or substantial portions of the
+ *  Software.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
DEALINGS
+ *  IN THE SOFTWARE.
+ */
+
+#include "isl_gen9.h"
+#include "isl_gen10.h"
+#include "isl_priv.h"
+
+void
+isl_gen10_choose_image_alignment_el(const struct isl_device *dev,
+const struct isl_surf_init_info *restrict 
info,
+enum isl_tiling tiling,
+enum isl_dim_layout dim_layout,
+enum isl_msaa_layout msaa_layout,
+struct isl_extent3d *image_align_el)
+{
+   /* No changes in image alignment fields from gen9 to gen10. So, just use
+* the gen9 function.
+*/
+   isl_gen9_choose_image_alignment_el(dev, info, tiling, dim_layout,
+  msaa_layout, image_align_el);
+}
diff --git a/src/intel/isl/isl_gen10.h b/src/intel/isl/isl_gen10.h
new file mode 100644
index 000..35c12cf
--- /dev/null
+++ b/src/intel/isl/isl_gen10.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Intel Corporation
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining a
+ *  copy of this software and associated documentation files (the "Software"),
+ *  to deal in the Software without restriction, including without limitation
+ *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ *  Software is furnished to do so, subject to the following conditions:
+ *
+ *  The above copyright notice and this permission notice (including the next
+ *  paragraph) shall be included in all copies or substantial portions of the
+ *  Software.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
DEALINGS
+ *  IN THE SOFTWARE.
+ */
+
+#ifndef ISL_GEN10_H
+#define ISL_GEN10_H
+
+#include "isl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void
+isl_gen10_choose_image_alignment_el(const struct isl_device *dev,
+const struct isl_surf_init_info *restrict 
info,
+enum isl_tiling tiling,
+enum isl_dim_layout dim_layout,
+enum isl_msaa_layout msaa_layout,
+struct isl_extent3d *image_align_el);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ISL_GEN10_H */
-- 
2.9.3

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[Mesa-dev] [PATCH 18/24] i965/cnl: Implement depth count workaround

2017-05-12 Thread Anuj Phogat
From: Ben Widawsky 

Signed-off-by: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/brw_queryobj.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c 
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index de93b8b..0a830ae 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -111,6 +111,14 @@ brw_write_depth_count(struct brw_context *brw, struct 
brw_bo *query_bo, int idx)
if (brw->gen == 9 && brw->gt == 4)
   flags |= PIPE_CONTROL_CS_STALL;
 
+   if (brw->gen >= 10) {
+  /* "Driver must program PIPE_CONTROL with only Depth Stall Enable bit set
+   * prior to programming a PIPE_CONTROL with Write PS Depth Count Post 
sync
+   * operation."
+   */
+  brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
+   }
+
brw_emit_pipe_control_write(brw, flags,
query_bo, idx * sizeof(uint64_t),
0, 0);
-- 
2.9.3

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[Mesa-dev] [PATCH 06/24] i965/cnl: Add gen10 specific function declarations

2017-05-12 Thread Anuj Phogat
These declarations will help the code start compiling
once we wire up the makefiles for gen10. Later patches
will start using these functions for gen10.

Signed-off-by: Anuj Phogat 
---
 src/intel/isl/isl_priv.h  | 12 
 src/mesa/drivers/dri/i965/brw_blorp.h |  2 ++
 src/mesa/drivers/dri/i965/brw_state.h |  1 +
 3 files changed, 15 insertions(+)

diff --git a/src/intel/isl/isl_priv.h b/src/intel/isl/isl_priv.h
index 3c4cc1e..04adefa 100644
--- a/src/intel/isl/isl_priv.h
+++ b/src/intel/isl/isl_priv.h
@@ -178,6 +178,10 @@ isl_gen9_surf_fill_state_s(const struct isl_device *dev, 
void *state,
const struct isl_surf_fill_state_info *restrict 
info);
 
 void
+isl_gen10_surf_fill_state_s(const struct isl_device *dev, void *state,
+const struct isl_surf_fill_state_info *restrict 
info);
+
+void
 isl_gen4_buffer_fill_state_s(void *state,
  const struct isl_buffer_fill_state_info *restrict 
info);
 
@@ -206,6 +210,10 @@ isl_gen9_buffer_fill_state_s(void *state,
  const struct isl_buffer_fill_state_info *restrict 
info);
 
 void
+isl_gen10_buffer_fill_state_s(void *state,
+  const struct isl_buffer_fill_state_info 
*restrict info);
+
+void
 isl_gen4_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
   const struct isl_depth_stencil_hiz_emit_info 
*restrict info);
 
@@ -233,4 +241,8 @@ void
 isl_gen9_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
   const struct isl_depth_stencil_hiz_emit_info 
*restrict info);
 
+void
+isl_gen10_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
+   const struct 
isl_depth_stencil_hiz_emit_info *restrict info);
+
 #endif /* ISL_PRIV_H */
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index ee4bf3b..d635d79 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -82,6 +82,8 @@ void gen8_blorp_exec(struct blorp_batch *batch,
  const struct blorp_params *params);
 void gen9_blorp_exec(struct blorp_batch *batch,
  const struct blorp_params *params);
+void gen10_blorp_exec(struct blorp_batch *batch,
+  const struct blorp_params *params);
 
 #ifdef __cplusplus
 } /* extern "C" */
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 4727e2a..4592e3e 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -364,6 +364,7 @@ void gen7_init_atoms(struct brw_context *brw);
 void gen75_init_atoms(struct brw_context *brw);
 void gen8_init_atoms(struct brw_context *brw);
 void gen9_init_atoms(struct brw_context *brw);
+void gen10_init_atoms(struct brw_context *brw);
 
 void upload_gs_state_for_tf(struct brw_context *brw);
 
-- 
2.9.3

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[Mesa-dev] [PATCH 10/24] i965/cnl: Wire up android Mesa build files for gen10

2017-05-12 Thread Anuj Phogat
Note: This patch is untested.

Signed-off-by: Anuj Phogat 
---
 src/intel/Android.genxml.mk  |  5 +
 src/intel/Android.isl.mk | 20 
 src/intel/Android.vulkan.mk  | 21 +
 src/mesa/drivers/dri/i965/Android.mk | 24 +++-
 4 files changed, 69 insertions(+), 1 deletion(-)

diff --git a/src/intel/Android.genxml.mk b/src/intel/Android.genxml.mk
index 4b0746c..e4d8dd8 100644
--- a/src/intel/Android.genxml.mk
+++ b/src/intel/Android.genxml.mk
@@ -96,6 +96,11 @@ $(intermediates)/genxml/gen9_pack.h: PRIVATE_XML := 
$(LOCAL_PATH)/genxml/gen9.xm
 $(intermediates)/genxml/gen9_pack.h: $(LOCAL_PATH)/genxml/gen9.xml 
$(LOCAL_PATH)/genxml/gen_pack_header.py
$(call header-gen)
 
+$(intermediates)/genxml/gen10_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) 
$(LOCAL_PATH)/genxml/gen_pack_header.py
+$(intermediates)/genxml/gen10_pack.h: PRIVATE_XML := 
$(LOCAL_PATH)/genxml/gen10.xml
+$(intermediates)/genxml/gen10_pack.h: $(LOCAL_PATH)/genxml/gen10.xml 
$(LOCAL_PATH)/genxml/gen_pack_header.py
+   $(call header-gen)
+
 $(intermediates)/genxml/genX_xml.h: $(addprefix 
$(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) 
$(MESA_TOP)/src/intel/genxml/gen_zipped_file.py
@mkdir -p $(dir $@)
@echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))"
diff --git a/src/intel/Android.isl.mk b/src/intel/Android.isl.mk
index 67e6d2d..516ac3a 100644
--- a/src/intel/Android.isl.mk
+++ b/src/intel/Android.isl.mk
@@ -161,6 +161,25 @@ include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
 
 # ---
+# Build libmesa_isl_gen10
+# ---
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_isl_gen10
+
+LOCAL_SRC_FILES := $(ISL_GEN10_FILES)
+
+LOCAL_CFLAGS := -DGEN_VERSIONx10=100
+
+LOCAL_C_INCLUDES := $(LIBISL_GENX_COMMON_INCLUDES)
+
+LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_genxml
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+# ---
 # Build libmesa_isl
 # ---
 
@@ -187,6 +206,7 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
libmesa_isl_gen75 \
libmesa_isl_gen8 \
libmesa_isl_gen9 \
+   libmesa_isl_gen10 \
libmesa_genxml
 
 # Autogenerated sources
diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index 831b658..566db29 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -158,6 +158,26 @@ include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
 
 #
+# libanv for gen10
+#
+
+include $(CLEAR_VARS)
+LOCAL_MODULE := libmesa_anv_gen10
+LOCAL_MODULE_CLASS := STATIC_LIBRARIES
+
+LOCAL_SRC_FILES := $(VULKAN_GEN10_FILES)
+LOCAL_CFLAGS := -DGEN_VERSIONx10=100
+
+LOCAL_C_INCLUDES := $(ANV_INCLUDES)
+
+LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
+
+LOCAL_SHARED_LIBRARIES := libdrm
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+#
 # libmesa_vulkan_common
 #
 
@@ -228,6 +248,7 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
libmesa_anv_gen75 \
libmesa_anv_gen8 \
libmesa_anv_gen9 \
+   libmesa_anv_gen10 \
libmesa_intel_compiler \
libmesa_anv_entrypoints
 
diff --git a/src/mesa/drivers/dri/i965/Android.mk 
b/src/mesa/drivers/dri/i965/Android.mk
index 7c4fada..7ee9ab7 100644
--- a/src/mesa/drivers/dri/i965/Android.mk
+++ b/src/mesa/drivers/dri/i965/Android.mk
@@ -47,7 +47,8 @@ I965_PERGEN_LIBS := \
libmesa_i965_gen7 \
libmesa_i965_gen75 \
libmesa_i965_gen8 \
-   libmesa_i965_gen9
+   libmesa_i965_gen9 \
+   libmesa_i965_gen10
 
 # ---
 # Build libmesa_i965_gen4
@@ -218,6 +219,27 @@ include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
 
 # ---
+# Build libmesa_i965_gen10
+# ---
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_i965_gen10
+
+LOCAL_C_INCLUDES := $(I965_PERGEN_COMMON_INCLUDES)
+
+LOCAL_SRC_FILES := $(i965_gen10_FILES)
+
+LOCAL_SHARED_LIBRARIES := $(I965_PERGEN_SHARED_LIBRARIES)
+
+LOCAL_STATIC_LIBRARIES := $(I965_PERGEN_STATIC_LIBRARIES)
+
+LOCAL_CFLAGS := -DGEN_VERSIONx10=100
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
+
+# ---
 # Build i965_dri
 # ---
 
-- 
2.9.3

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[Mesa-dev] [PATCH 05/24] i965/cnl: Include gen10_pack.h

2017-05-12 Thread Anuj Phogat
Signed-off-by: Anuj Phogat 
---
 src/intel/genxml/genX_pack.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/genxml/genX_pack.h b/src/intel/genxml/genX_pack.h
index 2ec2226..187e75c 100644
--- a/src/intel/genxml/genX_pack.h
+++ b/src/intel/genxml/genX_pack.h
@@ -44,6 +44,8 @@
 #  include "genxml/gen8_pack.h"
 #elif (GEN_VERSIONx10 == 90)
 #  include "genxml/gen9_pack.h"
+#elif (GEN_VERSIONx10 == 100)
+#  include "genxml/gen10_pack.h"
 #else
 #  error "Need to add a pack header include for this gen"
 #endif
-- 
2.9.3

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[Mesa-dev] [PATCH 01/24] i965: Make feature macros gen8 based

2017-05-12 Thread Anuj Phogat
From: Ben Widawsky 

All the "features" of the hardware are similar starting with GEN8, so remove as
much of the GEN9 uniqueness as possible. This makes implementing future gen
platforms a bit easier.

Signed-off-by: Ben Widawsky 
Reviewed-by: Anuj Phogat 
---
 src/intel/common/gen_device_info.c | 13 +
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 209b293..47aed9d 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -378,15 +378,8 @@ static const struct gen_device_info gen_device_info_chv = {
}
 };
 
-#define GEN9_FEATURES   \
+#define GEN9_HW_INFO\
.gen = 9,\
-   .has_hiz_and_separate_stencil = true,\
-   .has_resource_streamer = true,   \
-   .must_use_separate_stencil = true,   \
-   .has_llc = true, \
-   .has_pln = true, \
-   .supports_simd16_3src = true,\
-   .has_surface_tile_offset = true, \
.max_vs_threads = 336,   \
.max_gs_threads = 336,   \
.max_tcs_threads = 336,  \
@@ -454,6 +447,10 @@ static const struct gen_device_info gen_device_info_chv = {
   },   \
}
 
+#define GEN9_FEATURES   \
+   GEN8_FEATURES,   \
+   GEN9_HW_INFO
+
 static const struct gen_device_info gen_device_info_skl_gt1 = {
GEN9_FEATURES, .gt = 1,
.num_slices = 1,
-- 
2.9.3

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[Mesa-dev] [PATCH 03/24] i965/cnl: Add gen10.xml

2017-05-12 Thread Anuj Phogat
From: Jason Ekstrand 

This patch is truncated due to the size. You can find the full
patch in my review branch.

V2(Anuj): Add default value for length of 3DPRIMITIVE command
  Add values for 'Attribute Active Component Format'
  Rename few fields to match gen9.xml

Signed-off-by: Anuj Phogat 
---
 src/intel/genxml/gen10.xml | 3563 
 1 file changed, 3563 insertions(+)
 create mode 100644 src/intel/genxml/gen10.xml

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
new file mode 100644
index 000..685bd89
--- /dev/null
+++ b/src/intel/genxml/gen10.xml
-- 
2.9.3

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[Mesa-dev] [PATCH 02/24] i965/cnl: Add a preliminary device for Cannonlake

2017-05-12 Thread Anuj Phogat
From: Ben Widawsky 

v2 (Anuj):
Rebased on master and updated pci ids
Remove redundant initialization of max_wm_threads to 64 * 12.
For gen9+ max_wm_threads are initialized in gen_get_device_info().

Signed-off-by: Anuj Phogat 
Signed-off-by: Ben Widawsky 
---
 include/pci_ids/i965_pci_ids.h | 12 
 src/intel/common/gen_device_info.c | 58 ++
 src/intel/common/gen_device_info.h |  1 +
 3 files changed, 71 insertions(+)

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 17504f5..b296359 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -165,3 +165,15 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 
(Kaby Lake GT3)")
 CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
 CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
 CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
+CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A42, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A44, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A59, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5A, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5C, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 47aed9d..87edb94 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -555,6 +555,64 @@ static const struct gen_device_info 
gen_device_info_glk_2x6 = {
GEN9_LP_FEATURES_2X6
 };
 
+#define GEN10_HW_INFO   \
+   .gen = 10,   \
+   .max_vs_threads = 728,   \
+   .max_gs_threads = 432,   \
+   .max_tcs_threads = 432,  \
+   .max_tes_threads = 624,  \
+   .max_cs_threads = 56,\
+   .urb = { \
+  .size = 256,  \
+  .min_entries = {  \
+ [MESA_SHADER_VERTEX]= 64,  \
+ [MESA_SHADER_TESS_EVAL] = 34,  \
+  },\
+  .max_entries = {  \
+  [MESA_SHADER_VERTEX]   = 3936,\
+  [MESA_SHADER_TESS_CTRL]= 896, \
+  [MESA_SHADER_TESS_EVAL]= 2064,\
+  [MESA_SHADER_GEOMETRY] = 832, \
+  },\
+   }
+
+#define GEN10_FEATURES(_gt, _slices, _l3)   \
+   GEN8_FEATURES,   \
+   GEN10_HW_INFO,   \
+   .gt = _gt, .num_slices = _slices, .l3_banks = _l3
+
+static const struct gen_device_info gen_device_info_cnl_2x8 = {
+   /* GT0.5 */
+   GEN10_FEATURES(1, 1, 2)
+};
+
+static const struct gen_device_info gen_device_info_cnl_3x8 = {
+   /* GT1 */
+   GEN10_FEATURES(1, 1, 3)
+};
+
+static const struct gen_device_info gen_device_info_cnl_4x8 = {
+   /* GT 1.5 */
+   GEN10_FEATURES(1, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_5x8 = {
+   /* GT2 */
+   GEN10_FEATURES(2, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_gt1 = {
+   GEN10_FEATURES(1, 1, 3)
+};
+
+static const struct gen_device_info gen_device_info_cnl_gt2 = {
+   GEN10_FEATURES(2, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_gt3 = {
+   GEN10_FEATURES(3, 4, 12)
+};
+
 bool
 gen_get_device_info(int devid, struct gen_device_info *devinfo)
 {
diff --git a/src/intel/common/gen_device_info.h 
b/src/intel/common/gen_device_info.h
index 80676d0..6207630 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -96,6 +96,7 @@ struct gen_device_info
 * to change, so we program @max_cs_threads as the lower maximum.
 */
unsigned num_slices;
+   unsigned l3_banks;
unsigned max_vs_threads;   /**< Maximum Vertex Shader threads */
unsigned max_tcs_threads;  /**< Maximum Hull Shader threads */
unsigned max_tes_threads;  /**< Maximum Domain Shader threads */
-- 
2.9.3

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[Mesa-dev] [PATCH V2 00/24] Add Cannonlake support

2017-05-12 Thread Anuj Phogat
This series adds support for Cannonlake.

Changes from V1 to V2:
- Incorporated the review comments from V1.
- Rebased 8 months old CNL branch on top of master
- Wired up Linux and Android build files for gen10
- Replaced the use of few gen9 functions with gen10 specific functions.
- Squashed few patches, dropped few and created new patches.

What's remaining:
- Add missing gen10 bits in Vulkan driver.
- Fix failing piglit, cts tests for GL and Vulkan.

You can also find this series at:
https://github.com/aphogat/mesa.git
branch: reviews

Anuj Phogat (18):
  i965/cnl: Define genX(x) and GENX(x) for gen10
  i965/cnl: Include gen10_pack.h
  i965/cnl: Add gen10 specific function declarations
  i965/cnl: Update the script generating genX_bits.h
  i965/cnl: Add isl_gen10 header and source files
  i965/cnl: Wire up Mesa build files for gen10
  i965/cnl: Wire up android Mesa build files for gen10
  i965/cnl: Add pci id for INTEL_DEVID_OVERRIDE
  i965/cnl: Add cnl bits in aubinator
  i965/cnl: Update few assertions
  i965/cnl: Handle gen10 in switch cases across the driver
  i965/cnl: Start using CNL MOCS defines
  i965/cnl: Start using gen10 specific functions
  i965/cnl: Don't resolve single sampled color rb in case of sRGB formats
  i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3
  i965/cnl: Reformat surface_format_info table to accomodate gen10+
  i965/cnl: Enable CCS_E and RT support for few formats
  i965: Simplify get_l3_way_size() function

Ben Widawsky (5):
  i965: Make feature macros gen8 based
  i965/cnl: Add a preliminary device for Cannonlake
  i965/cnl: Implement new pipe control workaround
  i965/cnl: Implement depth count workaround
  i965/cnl: Restore lossless compression for sRGB formats

Jason Ekstrand (1):
  i965/cnl: Add gen10.xml

 include/pci_ids/i965_pci_ids.h   |   12 +
 src/intel/Android.genxml.mk  |5 +
 src/intel/Android.isl.mk |   20 +
 src/intel/Android.vulkan.mk  |   21 +
 src/intel/Makefile.isl.am|4 +
 src/intel/Makefile.sources   |   12 +-
 src/intel/Makefile.vulkan.am |7 +-
 src/intel/common/gen_device_info.c   |   71 +-
 src/intel/common/gen_device_info.h   |1 +
 src/intel/common/gen_l3_config.c |   11 +-
 src/intel/compiler/brw_compiler.h|2 +-
 src/intel/compiler/brw_eu.c  |2 +
 src/intel/compiler/brw_eu_compact.c  |1 +
 src/intel/genxml/gen10.xml   | 3563 ++
 src/intel/genxml/genX_pack.h |2 +
 src/intel/genxml/gen_bits_header.py  |6 +-
 src/intel/genxml/gen_macros.h|3 +
 src/intel/isl/isl.c  |9 +
 src/intel/isl/isl_format.c   |  498 +--
 src/intel/isl/isl_gen10.c|   41 +
 src/intel/isl/isl_gen10.h|   45 +
 src/intel/isl/isl_priv.h |   12 +
 src/intel/tools/aubinator.c  |8 +-
 src/intel/vulkan/anv_cmd_buffer.c|1 +
 src/intel/vulkan/anv_device.c|1 +
 src/intel/vulkan/anv_entrypoints_gen.py  |1 +
 src/mesa/drivers/dri/i965/Android.mk |   24 +-
 src/mesa/drivers/dri/i965/Makefile.am|6 +-
 src/mesa/drivers/dri/i965/Makefile.sources   |4 +
 src/mesa/drivers/dri/i965/brw_blorp.c|6 +
 src/mesa/drivers/dri/i965/brw_blorp.h|2 +
 src/mesa/drivers/dri/i965/brw_context.c  |2 +-
 src/mesa/drivers/dri/i965/brw_formatquery.c  |1 +
 src/mesa/drivers/dri/i965/brw_pipe_control.c |   11 +
 src/mesa/drivers/dri/i965/brw_program.c  |2 +-
 src/mesa/drivers/dri/i965/brw_queryobj.c |8 +
 src/mesa/drivers/dri/i965/brw_state.h|9 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |4 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 +
 src/mesa/drivers/dri/i965/gen7_urb.c |   12 +
 src/mesa/drivers/dri/i965/genX_state_upload.c|4 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c|2 +-
 src/mesa/drivers/dri/i965/intel_screen.c |2 +
 43 files changed, 4180 insertions(+), 280 deletions(-)
 create mode 100644 src/intel/genxml/gen10.xml
 create mode 100644 src/intel/isl/isl_gen10.c
 create mode 100644 src/intel/isl/isl_gen10.h

-- 
2.9.3

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[Mesa-dev] [PATCH 14/24] i965/cnl: Handle gen10 in switch cases across the driver

2017-05-12 Thread Anuj Phogat
We are still using some gen9 functions for gen10 in this patch.
They will be replaced by gen10 functions in later patches.

Signed-off-by: Anuj Phogat 
---
 src/intel/common/gen_l3_config.c| 1 +
 src/intel/compiler/brw_eu.c | 2 ++
 src/intel/compiler/brw_eu_compact.c | 1 +
 src/intel/isl/isl.c | 3 +++
 src/intel/vulkan/anv_cmd_buffer.c   | 1 +
 src/intel/vulkan/anv_device.c   | 1 +
 src/intel/vulkan/anv_entrypoints_gen.py | 1 +
 src/mesa/drivers/dri/i965/brw_blorp.c   | 1 +
 src/mesa/drivers/dri/i965/brw_formatquery.c | 1 +
 src/mesa/drivers/dri/i965/intel_screen.c| 1 +
 10 files changed, 13 insertions(+)

diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 0783217..4fe3503 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -116,6 +116,7 @@ get_l3_configs(const struct gen_device_info *devinfo)
   return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
 
case 9:
+   case 10:
   return chv_l3_configs;
 
default:
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index 77400c1..2c0dc27 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -412,6 +412,7 @@ enum gen {
GEN75 = (1 << 5),
GEN8  = (1 << 6),
GEN9  = (1 << 7),
+   GEN10  = (1 << 8),
GEN_ALL = ~0
 };
 
@@ -688,6 +689,7 @@ gen_from_devinfo(const struct gen_device_info *devinfo)
case 7: return devinfo->is_haswell ? GEN75 : GEN7;
case 8: return GEN8;
case 9: return GEN9;
+   case 10: return GEN10;
default:
   unreachable("not reached");
}
diff --git a/src/intel/compiler/brw_eu_compact.c 
b/src/intel/compiler/brw_eu_compact.c
index b2af76d..740a395 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -1362,6 +1362,7 @@ brw_init_compaction_tables(const struct gen_device_info 
*devinfo)
assert(gen8_src_index_table[ARRAY_SIZE(gen8_src_index_table) - 1] != 0);
 
switch (devinfo->gen) {
+   case 10:
case 9:
case 8:
   control_index_table = gen8_control_index_table;
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f89f351..5dc41fa 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1672,6 +1672,7 @@ isl_surf_fill_state_s(const struct isl_device *dev, void 
*state,
   isl_gen8_surf_fill_state_s(dev, state, info);
   break;
case 9:
+   case 10:
   isl_gen9_surf_fill_state_s(dev, state, info);
   break;
default:
@@ -1703,6 +1704,7 @@ isl_buffer_fill_state_s(const struct isl_device *dev, 
void *state,
   isl_gen8_buffer_fill_state_s(state, info);
   break;
case 9:
+   case 10:
   isl_gen9_buffer_fill_state_s(state, info);
   break;
default:
@@ -1770,6 +1772,7 @@ isl_emit_depth_stencil_hiz_s(const struct isl_device 
*dev, void *batch,
   isl_gen8_emit_depth_stencil_hiz_s(dev, batch, info);
   break;
case 9:
+   case 10:
   isl_gen9_emit_depth_stencil_hiz_s(dev, batch, info);
   break;
default:
diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 120b864..d34f9f8 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -334,6 +334,7 @@ anv_cmd_buffer_emit_state_base_address(struct 
anv_cmd_buffer *cmd_buffer)
case 8:
   return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
case 9:
+   case 10:
   return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
default:
   unreachable("unsupported gen\n");
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 35e4030..455c5f9 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1141,6 +1141,7 @@ VkResult anv_CreateDevice(
   result = gen8_init_device_state(device);
   break;
case 9:
+   case 10:
   result = gen9_init_device_state(device);
   break;
default:
diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index a21228c..f293848 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -183,6 +183,7 @@ TEMPLATE_C = Template(textwrap.dedent(u"""\
}
 
switch (devinfo->gen) {
+   case 10:
case 9:
   if (gen9_layer.entrypoints[index])
  return gen9_layer.entrypoints[index];
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index b69cb4f..8a6cc66 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -94,6 +94,7 @@ brw_blorp_init(struct brw_context *brw)
   brw->blorp.exec = gen8_blorp_exec;
   break;
case 9:
+   case 10:
   brw->blorp.mocs.tex = SKL_MOCS_WB;
   brw->blorp.mocs.rb = SKL_MOCS_PTE;
   brw->blorp.mocs.vb = SKL_MOCS_WB;
diff --git a/src/mesa/drivers/dri/i965/brw_formatquer

[Mesa-dev] [ANNOUNCE] mesa 17.0.6

2017-05-12 Thread Andres Gomez
Mesa 17.0.6 is now available.

In this release we have:

Mesa Core includes a fix for validating that SSA references use the
same number of channels as there are in the SSA value and a minor fix
for the YUV color conversion matrix.

Gallivm has received a fix when setting bool values in Big Endian
architectures.

Several fixes, including some leak fixes and have been added to
renderonly.

radv has now support enabled for POLARIS12 and reports presentation
error per image request.

radeonsi has seen adjusted the ESGS ring buffer size computation on VI
while, on SI, it has gotten a fix for the gl_PrimitiveID in
tessellation with instanced draws. Additionally, a hang workaround has
been applied to POLARIS12 too.

L8A8_UNORM texture format has been added for etnaviv and freedreno got
a fix for a hang with large render targets on devices with small gmem.

Some more fixes have made it for Intel's Vulkan driver including some
corrections when returning error codes, while i965 has gotten several
fixes dealing with DF.

EGL has seen fixed a segfault and, now emits an error when EGLSurface
is lost. Also, in Android, there has been included a fix to prevent a
deadlock and yet another to ensure the emission of an error when
needed.

Finally, in the building front, DRI modules now always link against
shared glapi. The travis continuous integration has received many
updates to be able to follow the changes in the building of stable
branch closer and Scons has been updated for LLVM 4.0.



Adam Jackson (1):
  egl/platform/drm: Don't take display ownership until gbm is initialized

Andres Gomez (8):
  docs: add sha256 checksums for 17.0.5
  travis: replace Trusty-based LLVM toolchain apt-get with apt addon
  travis: add the possibility of using the txc-dxtn library
  cherry-ignore: 17.1 nominations only
  cherry-ignore: fix regression in descriptor set freeing.
  cherry-ignore: rejected commits
  Update version to 17.0.6
  docs: add release notes for 17.0.6

Ben Boeckel (1):
  scons: update for LLVM 4.0

Brian Paul (1):
  st/mesa: move duplicated st_ws_framebuffer() function into header file

Chad Versace (3):
  egl: Emit error when EGLSurface is lost
  egl/android: Cancel any outstanding ANativeBuffer in surface destructor
  egl/android: Mark surface as lost when dequeueBuffer fails

Christian Gmeiner (1):
  etnaviv: add L8A8_UNORM texture format

Dave Airlie (2):
  radv/wsi: report presentation error per image request
  radv: enable POLARIS12 support.

Emil Velikov (21):
  travis: correct libdrm required regex to also track libdrm itself
  travis: add nearly all gallium drivers to the list
  travis: use both cores for make/make check
  travis: bring the scons build on par with AppVeyor
  travis: explicitly LD_LIBRARY_PATH the local libraries
  travis: enable apt cache
  travis: automatically manage ccache caching
  travis: remove unused -dev packages
  travis: rework "if test" blocks in the script section
  travis: split out matrix from env
  travis: add separate "scons" and "scons llvm" targets
  travis: add "scons swr" to the build matrix
  travis: add "make swr" to the build matrix
  travis: split the make target to three separate ones
  travis: model scons check target like the make one
  travis: add Gallium state-tracker targets
  travis: enable wayland support
  travis: bump MAKEFLAGS to -j4
  gallium/dri: always link against shared glapi
  mesa/dri: always link against shared glapi
  glx: glX_proto_send.py: use correct compile guard GLX_INDIRECT_RENDERING

Eric Anholt (1):
  nir: Pick just the channels we want for bitmap and drawpixels lowering.

Ilia Mirkin (1):
  gallium/targets: fix bool setting on BE architectures

Jason Ekstrand (1):
  anv/cmd_buffer: Use the device allocator for QueueSubmit

Johnson Lin (1):
  nir/lower_tex: Fix minor error in YUV color conversion matrix

Marek Olšák (2):
  radeonsi: adjust ESGS ring buffer size computation on VI
  radeonsi: apply the tess+GS hang workaround to Polaris12 as well

Nicolai Hähnle (1):
  radeonsi: fix gl_PrimitiveID in tessellation with instanced draws on SI

Philipp Zabel (3):
  renderonly: close transfer prime_fd
  renderonly: drop resources on destroy
  renderonly: use drmIoctl

Rhys Kidd (3):
  travis: Support LLVM 3.8+ on Trusty-based Travis-CI via apt-get not apt 
addon
  travis: Add radv vulkan driver to continuous integration
  travis: Add radeonsi to continuous integration

Rob Clark (1):
  freedreno/a3xx: fix hang w/ large render targets and small gmem

Samuel Iglesias Gonsálvez (5):
  i965/vec4: fix vertical stride to avoid breaking region parameter rule
  i965/vec4: fix register width for DF VGRF and UNIFORM
  i965/vec4: don't modify regioning parameters to the sources of DF align1 
instructions
  anv: anv_gem_mmap() returns MAP

Re: [Mesa-dev] [PATCH 0/2] Allow redeclaration of GLSL builtins; fixes Dying Light and Dead Island Definitive Edition

2017-05-12 Thread Timothy Arceri

On 13/05/17 00:11, John Brooks wrote:

On Fri, May 12, 2017 at 03:56:26PM +0200, Samuel Pitoiset wrote:



On 05/12/2017 03:39 PM, John Brooks wrote:

Since release, Dying Light and Dead Island Definitive Edition have been broken
on Mesa, producing at best only a black screen after loading. I found that the
root of the problem is that their vertex shaders redeclare the GLSL builtin
gl_VertexID, which Mesa's compiler considers to be an error:

 error: `gl_VertexID' redeclared

These patches make the compiler more lenient so that the shaders compile.
Because such redeclarations are not explicitly valid in the spec, this
behaviour is selectively activated by the new allow_glsl_builtin_redeclaration
driconf option, which has been enabled for both games in the default drirc.

With this change, both games work on Mesa and render correctly. Note that the
games require OpenGL 4.4+, and so it is necessary to launch them with
MESA_GL_VERSION_OVERRIDE and MESA_GLSL_VERSION_OVERRIDE set to OpenGL 4.4 (GLSL
440) or higher.

Contrary to popular belief, this problem actually had nothing whatsoever to do
with compatibility profiles. Forcing Mesa to create a higher version
compatibility profile with MESA_GL_VERSION_OVERRIDE=4.5COMPAT or
allow_higher_compat_version results in graphical glitches, so don't use that.


I wonder if there is multiple versions of Dying Light, but using
MESA_GL_VERSION_OVERRIDE=4.4 and MESA_GLSL_VERSION_OVERRIDE=440 doesn't work
for me (game crash at launching). Also it requests some unsupported GL
functions (compat?).

IIRC, Dying Light wants a GL 4.4 compat profile, I guess Timothy can
confirm?

What's your steam app ID?

Btw, you probably don't need to override the GL/GLSL versions, it should be
backward compatible.



Steam App ID 239140. The use of legacy functions (such as glBegin) in frame 0
is SDL's doing:


I don't know why your game would crash on launch. My first thought would be
steam runtime issues though. Make sure Steam runtime is enabled and remove
~/.local/share/Steam/ubuntu12_32/steam-runtime/amd64/usr/lib/x86_64-linux-gnu/libstdc++.so.6

The version override is necessary since the game will not render at all with a
3.0 compat profile, which is what it gets without an override.


Right but isn't that is because the game is requesting a compat profile?

How do you know that the rendering issues you see when using the compat 
override are not because of missing compat support for higher GL versions?


For example a feature/behavior supported in an eariler GL version may 
have been changed to be more like core and it just happens that 
overriding to use core makes the rendering problems go away.




--
John Brooks
Frogging101 on IRC and elsewhere


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Re: [Mesa-dev] [PATCH v2 2/2] i965/formats: Update the three-channel DXT1 mappings

2017-05-12 Thread Nanley Chery
On Fri, May 12, 2017 at 01:33:54PM -0700, Nanley Chery wrote:
> The procedure for decompressing an opaque DXT1 OpenGL format is
> dependant on the comparison of two colors stored in the first 32 bits of
> the compressed block. Here's the specified OpenGL behavior for
> reference:
> 
>The RGB color for a texel at location (x,y) in the block is given by:
> 
>   RGB0,  if color0 > color1 and code(x,y) == 0
>   RGB1,  if color0 > color1 and code(x,y) == 1
>   (2*RGB0+RGB1)/3,   if color0 > color1 and code(x,y) == 2
>   (RGB0+2*RGB1)/3,   if color0 > color1 and code(x,y) == 3
> 
>   RGB0,  if color0 <= color1 and code(x,y) == 0
>   RGB1,  if color0 <= color1 and code(x,y) == 1
>   (RGB0+RGB1)/2, if color0 <= color1 and code(x,y) == 2
>   BLACK, if color0 <= color1 and code(x,y) == 3
> 
> The sampling operation performed on an opaque DXT1 Intel format essentially
> hard-codes the comparison result of the two colors as color0 > color1.
> This means that the behavior is incompatible with OpenGL. This is stated
> in the SKL PRM, Vol 5: Memory Views:
> 
>Opaque Textures (DXT1_RGB)
>   Texture format DXT1_RGB is identical to DXT1, with the exception that 
> the
>   One-bit Alpha encoding is removed. Color 0 and Color 1 are not 
> compared, and
>   the resulting texel color is derived strictly from the Opaque Color 
> Encoding.
>   The alpha channel defaults to 1.0.
> 
>   Programming Note
>   Context: Opaque Textures (DXT1_RGB)
>   The behavior of this format is not compliant with the OGL spec.
> 
> The opaque and non-opaque DXT1 OpenGL formats are specified to be
> decoded in exactly the same way except the BLACK value must have a
> transparent alpha channel in the latter. Use the four-channel BC1 Intel
> formats with the alpha set to 1 to provide the behavior required by the
> spec. Note that the alpha is already set to 1 for RGB formats in
> brw_get_texture_swizzle().

The last sentence actually turned out to be false. I plan to send out a
v3 of this patch along with the Piglit test used to find this issue.
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Re: [Mesa-dev] [PATCH 3/4] intel/isl: Refactor gen6_choose_image_alignment_el

2017-05-12 Thread Chad Versace
On Thu 11 May 2017, Jason Ekstrand wrote:
> On Thu, May 11, 2017 at 9:08 PM, Chad Versace 
> wrote:
> 
> > On Thu 11 May 2017, Jason Ekstrand wrote:
> > > On Thu, May 11, 2017 at 7:03 AM, Pohjolainen, Topi <
> > > topi.pohjolai...@gmail.com> wrote:
> > >
> > > > On Wed, May 10, 2017 at 02:30:31PM -0700, Jason Ekstrand wrote:
> > > > > ---
> > > > >  src/intel/isl/isl_gen6.c | 30 --
> > > > >  1 file changed, 12 insertions(+), 18 deletions(-)
> > > > >
> > > > > diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c
> > > > > index b746903..0de9620 100644
> > > > > --- a/src/intel/isl/isl_gen6.c
> > > > > +++ b/src/intel/isl/isl_gen6.c
> > > > > @@ -88,6 +88,8 @@ isl_gen6_choose_image_alignment_el(const struct
> > > > isl_device *dev,
> > > > >  *| format | halign | valign |
> > > > >  *++++
> > > > >  *| YUV 4:2:2 formats  |  4 |  * |
> > > > > +*| BC1-5  |  4 |  4 |
> > > > > +*| FXT1   |  8 |  4 |
> > > > >  *| uncompressed formats   |  4 |  * |
> > > > >  *++++
> > > > >  *
> > > > > @@ -110,29 +112,13 @@ isl_gen6_choose_image_alignment_el(const
> > struct
> > > > isl_device *dev,
> > > > >  */
> > > > >
> > > > > if (isl_format_is_compressed(info->format)) {
> > > > > +  /* Compressed formats have an alignment equal to their block
> > size
> > > > */
> > > > >*image_align_el = isl_extent3d(1, 1, 1);
> > > > >return;
> > > > > }
> > > > >
> > > > > -   if (isl_format_is_yuv(info->format)) {
> > > > > -  *image_align_el = isl_extent3d(4, 2, 1);
> > > > > -  return;
> > > > > -   }
> > > > > -
> > > > > -   if (info->samples > 1) {
> > > > > -  *image_align_el = isl_extent3d(4, 4, 1);
> > > > > -  return;
> > > > > -   }
> > > > > -
> > > > > -   if (isl_surf_usage_is_depth_or_stencil(info->usage) &&
> > > > > -   !ISL_DEV_USE_SEPARATE_STENCIL(dev)) {
> > > >
> > > > Maybe mention in the commit that we drop this as it is always false on
> > > > gen6+?
> > > > In isl.c: "dev->use_separate_stencil = ISL_DEV_GEN(dev) >= 6;"
> > > >
> > >
> > > No, I dropped it not because we always use separate stencil but because
> > > it's redundant with the regular depth case.  The PRM says to use a 4x4
> > > alignment for all depth buffers but 4x2 for separate stencil.  Combined
> > > depth-stencil falls under the "depth" case so I didn't think we needed to
> > > call it out explicitly.
> >
> > I admit that the condition I wrote
> >
> > if (isl_surf_usage_is_depth_or_stencil(info->usage) &&
> > !ISL_DEV_USE_SEPARATE_STENCIL(dev))
> >
> > was poorly chosen. I should've written it without relying on
> > ISL_DEV_USE_SEPARATE_STENCIL.
> >
> > Topi has a point because a surface with
> > format=ISL_FORMAT_X24_TYPELESS_G8_UINT will necessarily have
> > usage=ISL_SURF_USAGE_STENCIL_BIT (no depth bit). The hardware requires
> > the surface to have valign=4, and my badly written (but correct)
> > condition ensured valign=4 in this case. After this patch, the function
> > wrongly chooses valign=2.
> >
> 
> No it won't.  It's hard to see in patch form, but after this patch is
> applied we check for depth first and then stencil.  If it has ANY depth
> component, then it will get 4x4 aligned.  Only separate stencil gets 4x2.

This function, pre-patch and post-patch, does not inspect the format for
a depth component.  It checks if the depth usage flag is set. That's the
key difference.

On gen6, it's possible to create a usable surface with format
X24_TYPELESS_G8_UINT with ISL_SURF_USAGE_STENCIL_BIT and no depth bit.
And, if I understand this patch correctly, that surface does not satisfy
the depth check in this patch:

if (isl_surf_usage_is_depth(info->usage)) {
   /* depth buffer (possibly interleaved with stencil) */
   *image_align_el = isl_extent3d(4, 4, 1);
   return;
}

Instead, that surface eventually hits this at the bottom of the
function:

   *image_align_el = isl_extent3d(4, 2, 1);

Of course, such a surface is only usable as a stencil buffer if hiz is
disabled. So we'll probably never observe such a surface in real life.
But we should at least assert that's the case.

> > I suggest either
> >
> > a. Asserting that separate stencil is true in the neighborhood of
> >
> > if (isl_surf_usage_is_depth(info->usage)) {
> > /* depth buffer (possibly interleaved with stencil) */
> > *image_align_el = isl_extent3d(4, 4, 1);
> > return;
> > }
> >
> >   and dropping the reference to possible interleaved stencil.
> >
> > b. Or, better, rewrite the original logic to be clearer.
> >
> > if ((info->usage & ISL_SURF_USAGE_STENCIL_BIT)
> > && info->format == ISL_FORMAT_R8_UINT) {
> > /* separate

[Mesa-dev] [PATCH] radeonsi: bugfix in performance counters

2017-05-12 Thread Mauro Rossi
'if (regs->counters)' expression at line 623 is always true,
spotted because of an error when building android-x86.

'if (regs->counters[idx])' is used instead.

Fixes the following building error in Android:

external/mesa/src/gallium/drivers/radeonsi/si_perfcounter.c:617:14:
error: address of array 'regs->counters' will always evaluate to 'true' 
[-Werror,-Wpointer-bool-conversion]
if (regs->counters)
~~  ~~^~~~

Fixes: ad22006 "radeonsi: implement AMD_performance_monitor for CIK+"
---
 src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c 
b/src/gallium/drivers/radeonsi/si_perfcounter.c
index 41dd52edb1..85b6e5c55a 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -620,7 +620,7 @@ static void si_pc_emit_read(struct r600_common_context *ctx,
reg_delta = -reg_delta;
 
for (idx = 0; idx < count; ++idx) {
-   if (regs->counters)
+   if (regs->counters[idx])
reg = regs->counters[idx];
 
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
-- 
2.11.0

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[Mesa-dev] [PATCH] virgl: fix virgl_bo_transfer_{put, get} box struct copy

2017-05-12 Thread Rob Herring
Commit 3dfe61ed6ec6 ("gallium: decrease the size of pipe_box - 24 -> 16
bytes") changed the size of pipe_box, but the virgl code was relying on
pipe_box and drm_virtgpu_3d_box structs having the same size/layout doing
a struct copy. Copy the fields one by one instead.

Cc: Marek Olšák 
Cc: Dave Airlie 
Signed-off-by: Rob Herring 
---
 src/gallium/winsys/virgl/drm/virgl_drm_winsys.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c 
b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
index 4708126aed9d..0edae4767e6b 100644
--- a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
+++ b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
@@ -264,7 +264,12 @@ virgl_bo_transfer_put(struct virgl_winsys *vws,
 
memset(&tohostcmd, 0, sizeof(tohostcmd));
tohostcmd.bo_handle = res->bo_handle;
-   tohostcmd.box = *(struct drm_virtgpu_3d_box *)box;
+   tohostcmd.box.x = box->x;
+   tohostcmd.box.y = box->y;
+   tohostcmd.box.z = box->z;
+   tohostcmd.box.w = box->width;
+   tohostcmd.box.h = box->height;
+   tohostcmd.box.d = box->depth;
tohostcmd.offset = buf_offset;
tohostcmd.level = level;
   // tohostcmd.stride = stride;
@@ -288,7 +293,12 @@ virgl_bo_transfer_get(struct virgl_winsys *vws,
fromhostcmd.offset = buf_offset;
   // fromhostcmd.stride = stride;
   // fromhostcmd.layer_stride = layer_stride;
-   fromhostcmd.box = *(struct drm_virtgpu_3d_box *)box;
+   fromhostcmd.box.x = box->x;
+   fromhostcmd.box.y = box->y;
+   fromhostcmd.box.z = box->z;
+   fromhostcmd.box.w = box->width;
+   fromhostcmd.box.h = box->height;
+   fromhostcmd.box.d = box->depth;
return drmIoctl(vdws->fd, DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST, 
&fromhostcmd);
 }
 
-- 
2.11.0

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Re: [Mesa-dev] [PATCH v2] bin/get-fixes-pick-list.sh: bring back the warning

2017-05-12 Thread Andres Gomez
On Fri, 2017-05-12 at 13:54 +0100, Emil Velikov wrote:
> On 12 May 2017 at 09:33, Andres Gomez  wrote:
> > We warn again if there is more than one line with the "fixes:" tag.
> > 
> > The warning is only silenced when the commit has landed already or we
> > output another message for every "fixes:" tag.
> > 
> 
> Since "only silenced" is no longer true, use something like the following?
> 
> "The warning is silenced when the commit has already landed or each
> fixes tag reference a commit that is in branch."
> 
> > Signed-off-by: Andres Gomez 
> > ---
> >  bin/get-fixes-pick-list.sh | 19 +--
> >  1 file changed, 13 insertions(+), 6 deletions(-)
> > 
> > diff --git a/bin/get-fixes-pick-list.sh b/bin/get-fixes-pick-list.sh
> > index cf95f28377..3ea649a0a4 100755
> > --- a/bin/get-fixes-pick-list.sh
> > +++ b/bin/get-fixes-pick-list.sh
> > @@ -33,7 +33,14 @@ do
> > 
> > # For each one try to extract the tag
> > fixes_count=`git show $sha | grep -i "fixes:" | wc -l`
> > +   warn=`(test $fixes_count -gt 1 && echo $fixes_count) || echo 0`
> > while [ $fixes_count -gt 0 ] ; do
> > +   # Skip if it has been already landed.
> > +   if grep -q ^$sha already_picked ; then
> > +   warn=0
> > +   break
> > +   fi
> > +
> 
> Nit: please move this just after the cherry-ignore hunk.
> 
> > fixes=`git show $sha | grep -i "fixes:" | tail -n 
> > $fixes_count | head -n 1`
> 
> Are you sure we need the "tail -n $fixes_count | " here? Feel free to
> squash with this patch (+add small note in commit message) or address
> as follow-up.

It is needed, but your comment has made me realize that what it is
unnecessary is the " | head -n 1". I'll squash that in the patch and
add a note in the commit message before pushing.

> With the above
> Reviewed-by: Emil Velikov 

Thanks for the review!

-- 
Br,

Andres
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Re: [Mesa-dev] [PATCH 2/2] i965/formats: Update the RGB_DXT1 mappings

2017-05-12 Thread Kenneth Graunke
On Friday, May 12, 2017 1:31:56 PM PDT Nanley Chery wrote:
> On Fri, May 12, 2017 at 08:39:40AM -0700, Kenneth Graunke wrote:
> > On Thursday, May 11, 2017 4:46:27 PM PDT Nanley Chery wrote:
> > > The DXT1_RGB* format does not provide the correct behavior for OpenGL in
> > > the case where color_0 <= color_1. BC1_RGB_UNORM with a alpha set to 1
> > > provides the behavior which matches the spec.
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100925
> > > Cc: 
> > > Signed-off-by: Nanley Chery 
> > > ---
> > >  src/mesa/drivers/dri/i965/brw_surface_formats.c | 15 ++-
> > >  1 file changed, 2 insertions(+), 13 deletions(-)
> > 
> > Two things I was worried about:
> > 
> > 1. Where's the swizzling code in this patch?
> > 
> >   ->  it turns out that we already swizzle A -> 1 when the mesa format
> >   does not have alpha, but the hardware format does.  So, it's
> >   already there, we don't need any new code :)
> > 
> > 2. Will it impact performance?
> > 
> >   ->  Might be nice to check...but the compressed data is the same size
> >   for both formats, so it's just how it interprets it...doubtful.
> > 
> >   This will cause recompiles on Ivybridge and older hardware, due
> >   to the implicit texture swizzling.  Sad, but not sure we can do
> >   anything about it.  Could change the default to RGB1 if that's
> >   better...
> > 
> 
> Oh, I didn't know about about those recompiles. I'm not sure how they
> work.

Ivybridge and earlier don't have native support for texture swizzles
(aka the shader channel select / SCS fields).  So, we recompile the
program and emit MOVs to do the swizzling.  We guess XYZW for the
initial precompile.

Jason had an idea of how to do that without recompiles...perhaps
one of these days we'll finally bite the bullet and do that.


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[Mesa-dev] [PATCH v2 2/2] i965/formats: Update the three-channel DXT1 mappings

2017-05-12 Thread Nanley Chery
The procedure for decompressing an opaque DXT1 OpenGL format is
dependant on the comparison of two colors stored in the first 32 bits of
the compressed block. Here's the specified OpenGL behavior for
reference:

   The RGB color for a texel at location (x,y) in the block is given by:

  RGB0,  if color0 > color1 and code(x,y) == 0
  RGB1,  if color0 > color1 and code(x,y) == 1
  (2*RGB0+RGB1)/3,   if color0 > color1 and code(x,y) == 2
  (RGB0+2*RGB1)/3,   if color0 > color1 and code(x,y) == 3

  RGB0,  if color0 <= color1 and code(x,y) == 0
  RGB1,  if color0 <= color1 and code(x,y) == 1
  (RGB0+RGB1)/2, if color0 <= color1 and code(x,y) == 2
  BLACK, if color0 <= color1 and code(x,y) == 3

The sampling operation performed on an opaque DXT1 Intel format essentially
hard-codes the comparison result of the two colors as color0 > color1.
This means that the behavior is incompatible with OpenGL. This is stated
in the SKL PRM, Vol 5: Memory Views:

   Opaque Textures (DXT1_RGB)
  Texture format DXT1_RGB is identical to DXT1, with the exception that the
  One-bit Alpha encoding is removed. Color 0 and Color 1 are not compared, 
and
  the resulting texel color is derived strictly from the Opaque Color 
Encoding.
  The alpha channel defaults to 1.0.

  Programming Note
  Context: Opaque Textures (DXT1_RGB)
  The behavior of this format is not compliant with the OGL spec.

The opaque and non-opaque DXT1 OpenGL formats are specified to be
decoded in exactly the same way except the BLACK value must have a
transparent alpha channel in the latter. Use the four-channel BC1 Intel
formats with the alpha set to 1 to provide the behavior required by the
spec. Note that the alpha is already set to 1 for RGB formats in
brw_get_texture_swizzle().

v2 (Kenneth Graunke):
- Provide a more detailed commit message.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100925
Cc: 
Acked-by: Tapani Pälli  (v1)
Reviewed-by: Kenneth Graunke  (v1)
Signed-off-by: Nanley Chery 
---
 src/mesa/drivers/dri/i965/brw_surface_formats.c | 15 ++-
 1 file changed, 2 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c 
b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index 7b17e11125..b176a21c22 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -94,14 +94,14 @@ brw_isl_format_for_mesa_format(mesa_format mesa_format)
   [MESA_FORMAT_L_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
   [MESA_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
   [MESA_FORMAT_A8L8_SRGB] = 0,
-  [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_DXT1_RGB_SRGB,
+  [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
   [MESA_FORMAT_SRGBA_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
   [MESA_FORMAT_SRGBA_DXT3] = ISL_FORMAT_BC2_UNORM_SRGB,
   [MESA_FORMAT_SRGBA_DXT5] = ISL_FORMAT_BC3_UNORM_SRGB,
 
   [MESA_FORMAT_RGB_FXT1] = ISL_FORMAT_FXT1,
   [MESA_FORMAT_RGBA_FXT1] = ISL_FORMAT_FXT1,
-  [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_DXT1_RGB,
+  [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_BC1_UNORM,
   [MESA_FORMAT_RGBA_DXT1] = ISL_FORMAT_BC1_UNORM,
   [MESA_FORMAT_RGBA_DXT3] = ISL_FORMAT_BC2_UNORM,
   [MESA_FORMAT_RGBA_DXT5] = ISL_FORMAT_BC3_UNORM,
@@ -541,17 +541,6 @@ translate_tex_format(struct brw_context *brw,
*/
   return ISL_FORMAT_R32G32B32A32_FLOAT;
 
-   case MESA_FORMAT_SRGB_DXT1:
-  if (brw->gen == 4 && !brw->is_g4x) {
- /* Work around missing SRGB DXT1 support on original gen4 by just
-  * skipping SRGB decode.  It's not worth not supporting sRGB in
-  * general to prevent this.
-  */
- WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
- mesa_format = MESA_FORMAT_RGB_DXT1;
-  }
-  return brw_isl_format_for_mesa_format(mesa_format);
-
case MESA_FORMAT_RGBA_ASTC_4x4:
case MESA_FORMAT_RGBA_ASTC_5x4:
case MESA_FORMAT_RGBA_ASTC_5x5:
-- 
2.12.2

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[Mesa-dev] [PATCH v2 1/2] anv/formats: Update the three-channel BC1 mappings

2017-05-12 Thread Nanley Chery
The procedure for decompressing an opaque BC1 Vulkan format is dependant on the
comparison of two colors stored in the first 32 bits of the compressed block.
Here's the specified OpenGL (and Vulkan) behavior for reference:

   The RGB color for a texel at location (x,y) in the block is given by:

  RGB0,  if color0 > color1 and code(x,y) == 0
  RGB1,  if color0 > color1 and code(x,y) == 1
  (2*RGB0+RGB1)/3,   if color0 > color1 and code(x,y) == 2
  (RGB0+2*RGB1)/3,   if color0 > color1 and code(x,y) == 3

  RGB0,  if color0 <= color1 and code(x,y) == 0
  RGB1,  if color0 <= color1 and code(x,y) == 1
  (RGB0+RGB1)/2, if color0 <= color1 and code(x,y) == 2
  BLACK, if color0 <= color1 and code(x,y) == 3

The sampling operation performed on an opaque DXT1 Intel format essentially
hard-codes the comparison result of the two colors as color0 > color1. This
means that the behavior is incompatible with OpenGL and Vulkan. This is stated
in the SKL PRM, Vol 5: Memory Views:

   Opaque Textures (DXT1_RGB)
  Texture format DXT1_RGB is identical to DXT1, with the exception that the
  One-bit Alpha encoding is removed. Color 0 and Color 1 are not compared, 
and
  the resulting texel color is derived strictly from the Opaque Color 
Encoding.
  The alpha channel defaults to 1.0.

  Programming Note
  Context: Opaque Textures (DXT1_RGB)
  The behavior of this format is not compliant with the OGL spec.

The opaque and non-opaque BC1 Vulkan formats are specified to be decoded in
exactly the same way except the BLACK value must have a transparent alpha
channel in the latter. Use the four-channel BC1 Intel formats with the alpha
set to 1 to provide the behavior required by the spec.

v2 (Kenneth Graunke):
- Provide a more detailed commit message.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100925
Cc: 
Reviewed-by: Kenneth Graunke  (v1)
Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_formats.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index c39cec3800..25801e8b06 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -179,8 +179,8 @@ static const struct anv_format anv_formats[] = {
fmt(VK_FORMAT_D24_UNORM_S8_UINT,   ISL_FORMAT_R24_UNORM_X8_TYPELESS),
fmt(VK_FORMAT_D32_SFLOAT_S8_UINT,  ISL_FORMAT_R32_FLOAT),
 
-   fmt(VK_FORMAT_BC1_RGB_UNORM_BLOCK, ISL_FORMAT_DXT1_RGB),
-   fmt(VK_FORMAT_BC1_RGB_SRGB_BLOCK,  ISL_FORMAT_DXT1_RGB_SRGB),
+   swiz_fmt(VK_FORMAT_BC1_RGB_UNORM_BLOCK, ISL_FORMAT_BC1_UNORM, RGB1),
+   swiz_fmt(VK_FORMAT_BC1_RGB_SRGB_BLOCK,  ISL_FORMAT_BC1_UNORM_SRGB, 
RGB1),
fmt(VK_FORMAT_BC1_RGBA_UNORM_BLOCK,ISL_FORMAT_BC1_UNORM),
fmt(VK_FORMAT_BC1_RGBA_SRGB_BLOCK, ISL_FORMAT_BC1_UNORM_SRGB),
fmt(VK_FORMAT_BC2_UNORM_BLOCK, ISL_FORMAT_BC2_UNORM),
-- 
2.12.2

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Re: [Mesa-dev] [PATCH 2/2] i965/formats: Update the RGB_DXT1 mappings

2017-05-12 Thread Nanley Chery
On Fri, May 12, 2017 at 08:39:40AM -0700, Kenneth Graunke wrote:
> On Thursday, May 11, 2017 4:46:27 PM PDT Nanley Chery wrote:
> > The DXT1_RGB* format does not provide the correct behavior for OpenGL in
> > the case where color_0 <= color_1. BC1_RGB_UNORM with a alpha set to 1
> > provides the behavior which matches the spec.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100925
> > Cc: 
> > Signed-off-by: Nanley Chery 
> > ---
> >  src/mesa/drivers/dri/i965/brw_surface_formats.c | 15 ++-
> >  1 file changed, 2 insertions(+), 13 deletions(-)
> 
> Two things I was worried about:
> 
> 1. Where's the swizzling code in this patch?
> 
>   ->  it turns out that we already swizzle A -> 1 when the mesa format
>   does not have alpha, but the hardware format does.  So, it's
>   already there, we don't need any new code :)
> 
> 2. Will it impact performance?
> 
>   ->  Might be nice to check...but the compressed data is the same size
>   for both formats, so it's just how it interprets it...doubtful.
> 
>   This will cause recompiles on Ivybridge and older hardware, due
>   to the implicit texture swizzling.  Sad, but not sure we can do
>   anything about it.  Could change the default to RGB1 if that's
>   better...
> 

Oh, I didn't know about about those recompiles. I'm not sure how they
work.

> It might be nice to copy more of the findings you posted in bugzilla
> into the commit messages - people are more likely to find your commit
> message when blaming this code than to look at the bug.
> 

I added more detail to the commit messages and will send out a v2.

> It looks like Windows does this same workaround on Gen7.5+.  I'm not
> clear what they do on Gen7-.
> 
> Great find!  Both are:
> Reviewed-by: Kenneth Graunke 
> 

Thank you!

> > diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c 
> > b/src/mesa/drivers/dri/i965/brw_surface_formats.c
> > index 7b17e11125..b176a21c22 100644
> > --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
> > +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
> > @@ -94,14 +94,14 @@ brw_isl_format_for_mesa_format(mesa_format mesa_format)
> >[MESA_FORMAT_L_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
> >[MESA_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
> >[MESA_FORMAT_A8L8_SRGB] = 0,
> > -  [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_DXT1_RGB_SRGB,
> > +  [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
> >[MESA_FORMAT_SRGBA_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
> >[MESA_FORMAT_SRGBA_DXT3] = ISL_FORMAT_BC2_UNORM_SRGB,
> >[MESA_FORMAT_SRGBA_DXT5] = ISL_FORMAT_BC3_UNORM_SRGB,
> >  
> >[MESA_FORMAT_RGB_FXT1] = ISL_FORMAT_FXT1,
> >[MESA_FORMAT_RGBA_FXT1] = ISL_FORMAT_FXT1,
> > -  [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_DXT1_RGB,
> > +  [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_BC1_UNORM,
> >[MESA_FORMAT_RGBA_DXT1] = ISL_FORMAT_BC1_UNORM,
> >[MESA_FORMAT_RGBA_DXT3] = ISL_FORMAT_BC2_UNORM,
> >[MESA_FORMAT_RGBA_DXT5] = ISL_FORMAT_BC3_UNORM,
> > @@ -541,17 +541,6 @@ translate_tex_format(struct brw_context *brw,
> > */
> >return ISL_FORMAT_R32G32B32A32_FLOAT;
> >  
> > -   case MESA_FORMAT_SRGB_DXT1:
> > -  if (brw->gen == 4 && !brw->is_g4x) {
> > - /* Work around missing SRGB DXT1 support on original gen4 by just
> > -  * skipping SRGB decode.  It's not worth not supporting sRGB in
> > -  * general to prevent this.
> > -  */
> > - WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
> > - mesa_format = MESA_FORMAT_RGB_DXT1;
> > -  }
> > -  return brw_isl_format_for_mesa_format(mesa_format);
> > -
> > case MESA_FORMAT_RGBA_ASTC_4x4:
> > case MESA_FORMAT_RGBA_ASTC_5x4:
> > case MESA_FORMAT_RGBA_ASTC_5x5:
> > 
> 
> Nice to be rid of this!  Using an RGBA format and setting alpha to 1 is
> a lot better than not doing sRGB decode.

Agreed.
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Re: [Mesa-dev] [PATCH] gallium/u_threaded: drop and ignore all non-async debug callbacks

2017-05-12 Thread Nicolai Hähnle

On 12.05.2017 21:06, Marek Olšák wrote:

From: Marek Olšák 

This is necessary to comply with OpenGL.


Reviewed-by: Nicolai Hähnle 



---
 src/gallium/auxiliary/util/u_threaded_context.c | 7 +++
 src/gallium/auxiliary/util/u_threaded_context.h | 4 +---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_threaded_context.c 
b/src/gallium/auxiliary/util/u_threaded_context.c
index b44430f..50cb820 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -1585,20 +1585,27 @@ tc_dump_debug_state(struct pipe_context *_pipe, FILE 
*stream,
pipe->dump_debug_state(pipe, stream, flags);
 }

 static void
 tc_set_debug_callback(struct pipe_context *_pipe,
   const struct pipe_debug_callback *cb)
 {
struct threaded_context *tc = threaded_context(_pipe);
struct pipe_context *pipe = tc->pipe;

+   /* Drop all synchronous debug callbacks. Drivers are expected to be OK
+* with this. shader-db will use an environment variable to disable
+* the threaded context.
+*/
+   if (cb && cb->debug_message && !cb->async)
+  return;
+
tc_sync(tc);
pipe->set_debug_callback(pipe, cb);
 }

 static void
 tc_create_fence_fd(struct pipe_context *_pipe,
struct pipe_fence_handle **fence, int fd)
 {
struct threaded_context *tc = threaded_context(_pipe);
struct pipe_context *pipe = tc->pipe;
diff --git a/src/gallium/auxiliary/util/u_threaded_context.h 
b/src/gallium/auxiliary/util/u_threaded_context.h
index ea58d4c..f139230 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.h
+++ b/src/gallium/auxiliary/util/u_threaded_context.h
@@ -48,23 +48,21 @@
  *
  * 3) The threaded context must not be enabled for contexts that can use video
  *codecs.
  *
  * 4) Changes in driver behavior:
  *- begin_query and end_query always return true; return values from
  *  the driver are ignored.
  *- generate_mipmap uses is_format_supported to determine success;
  *  the return value from the driver is ignored.
  *- resource_commit always returns true; failures are ignored.
- *- If a non-async debug callback is set, the threaded context keeps using
- *  asynchronous execution. This is OK for shader-db, but the driver
- *  shouldn't use the debug callback in any other way.
+ *- set_debug_callback is skipped if the callback is synchronous.
  *
  *
  * Thread-safety requirements on context functions
  * ---
  *
  * These pipe_context functions are executed directly, so they shouldn't use
  * pipe_context in an unsafe way. They are de-facto screen functions now:
  * - create_query
  * - create_batch_query
  * - create_*_state (all CSOs and shaders)




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Re: [Mesa-dev] [PATCH 03/13] gallium/util: add threaded_context as a pipe_context wrapper

2017-05-12 Thread Nicolai Hähnle

On 12.05.2017 21:05, Marek Olšák wrote:

From: Marek Olšák 

v2: - rename num_calls -> num_call_slots (for tc_call)
- rename num_calls -> num_total_call_slots (for tc_batch)
- rename num_offloaded/direct_calls -> num_offloaded/direct_slots
- declare slot[0] instead of slot[1]
- remove no-op leftover code from tc_draw_vbo
- use tc_set_resource_reference to fill threaded_transfer
- fix map flags for sparse buffers
- cosmetic changes


Reviewed-by: Nicolai Hähnle 



---
 src/gallium/auxiliary/Makefile.sources |3 +
 src/gallium/auxiliary/util/u_threaded_context.c| 2305 
 src/gallium/auxiliary/util/u_threaded_context.h|  349 +++
 .../auxiliary/util/u_threaded_context_calls.h  |   66 +
 4 files changed, 2723 insertions(+)
 create mode 100644 src/gallium/auxiliary/util/u_threaded_context.c
 create mode 100644 src/gallium/auxiliary/util/u_threaded_context.h
 create mode 100644 src/gallium/auxiliary/util/u_threaded_context_calls.h

diff --git a/src/gallium/auxiliary/Makefile.sources 
b/src/gallium/auxiliary/Makefile.sources
index dbdb3ca..baebee6 100644
--- a/src/gallium/auxiliary/Makefile.sources
+++ b/src/gallium/auxiliary/Makefile.sources
@@ -294,20 +294,23 @@ C_SOURCES := \
util/u_surfaces.h \
util/u_tests.c \
util/u_tests.h \
util/u_texture.c \
util/u_texture.h \
util/u_tile.c \
util/u_tile.h \
util/u_time.h \
util/u_transfer.c \
util/u_transfer.h \
+   util/u_threaded_context.c \
+   util/u_threaded_context.h \
+   util/u_threaded_context_calls.h \
util/u_upload_mgr.c \
util/u_upload_mgr.h \
util/u_vbuf.c \
util/u_vbuf.h \
util/u_video.h \
util/u_viewport.h

 NIR_SOURCES := \
nir/tgsi_to_nir.c \
nir/tgsi_to_nir.h
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c 
b/src/gallium/auxiliary/util/u_threaded_context.c
new file mode 100644
index 000..b44430f
--- /dev/null
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -0,0 +1,2305 @@
+/**
+ *
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include "util/u_threaded_context.h"
+#include "util/u_cpu_detect.h"
+#include "util/u_format.h"
+#include "util/u_inlines.h"
+#include "util/u_memory.h"
+#include "util/u_upload_mgr.h"
+
+/* 0 = disabled, 1 = assertions, 2 = printfs */
+#define TC_DEBUG 0
+
+#if TC_DEBUG >= 1
+#define tc_assert assert
+#else
+#define tc_assert(x)
+#endif
+
+#if TC_DEBUG >= 2
+#define tc_printf printf
+#define tc_asprintf asprintf
+#define tc_strcmp strcmp
+#else
+#define tc_printf(...)
+#define tc_asprintf(...) 0
+#define tc_strcmp(...) 0
+#endif
+
+#define TC_SENTINEL 0x5ca1ab1e
+
+enum tc_call_id {
+#define CALL(name) TC_CALL_##name,
+#include "u_threaded_context_calls.h"
+#undef CALL
+   TC_NUM_CALLS,
+};
+
+typedef void (*tc_execute)(struct pipe_context *pipe, union tc_payload 
*payload);
+
+static const tc_execute execute_func[TC_NUM_CALLS];
+
+static void
+tc_batch_check(struct tc_batch *batch)
+{
+   tc_assert(batch->sentinel == TC_SENTINEL);
+   tc_assert(batch->sentinel2 == TC_SENTINEL);
+   tc_assert(batch->num_total_call_slots <= TC_CALLS_PER_BATCH);
+}
+
+static void
+tc_debug_check(struct threaded_context *tc)
+{
+   for (unsigned i = 0; i < TC_MAX_BATCHES; i++) {
+  tc_batch_check(&tc->batch_slots[i]);
+  tc_assert(tc->batch_slots[i].pipe == tc->pipe);
+   }
+}
+
+static void
+tc_batch_execute(void *job, int thread_index)
+{
+   struct tc_batch *batch = job;
+   struct pipe_context *pipe = batch->pipe;
+   struct tc_call *last = &batch->call[batch->num_total_call_slots];
+
+   

[Mesa-dev] [PATCH] gallium/u_threaded: drop and ignore all non-async debug callbacks

2017-05-12 Thread Marek Olšák
From: Marek Olšák 

This is necessary to comply with OpenGL.
---
 src/gallium/auxiliary/util/u_threaded_context.c | 7 +++
 src/gallium/auxiliary/util/u_threaded_context.h | 4 +---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_threaded_context.c 
b/src/gallium/auxiliary/util/u_threaded_context.c
index b44430f..50cb820 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -1585,20 +1585,27 @@ tc_dump_debug_state(struct pipe_context *_pipe, FILE 
*stream,
pipe->dump_debug_state(pipe, stream, flags);
 }
 
 static void
 tc_set_debug_callback(struct pipe_context *_pipe,
   const struct pipe_debug_callback *cb)
 {
struct threaded_context *tc = threaded_context(_pipe);
struct pipe_context *pipe = tc->pipe;
 
+   /* Drop all synchronous debug callbacks. Drivers are expected to be OK
+* with this. shader-db will use an environment variable to disable
+* the threaded context.
+*/
+   if (cb && cb->debug_message && !cb->async)
+  return;
+
tc_sync(tc);
pipe->set_debug_callback(pipe, cb);
 }
 
 static void
 tc_create_fence_fd(struct pipe_context *_pipe,
struct pipe_fence_handle **fence, int fd)
 {
struct threaded_context *tc = threaded_context(_pipe);
struct pipe_context *pipe = tc->pipe;
diff --git a/src/gallium/auxiliary/util/u_threaded_context.h 
b/src/gallium/auxiliary/util/u_threaded_context.h
index ea58d4c..f139230 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.h
+++ b/src/gallium/auxiliary/util/u_threaded_context.h
@@ -48,23 +48,21 @@
  *
  * 3) The threaded context must not be enabled for contexts that can use video
  *codecs.
  *
  * 4) Changes in driver behavior:
  *- begin_query and end_query always return true; return values from
  *  the driver are ignored.
  *- generate_mipmap uses is_format_supported to determine success;
  *  the return value from the driver is ignored.
  *- resource_commit always returns true; failures are ignored.
- *- If a non-async debug callback is set, the threaded context keeps using
- *  asynchronous execution. This is OK for shader-db, but the driver
- *  shouldn't use the debug callback in any other way.
+ *- set_debug_callback is skipped if the callback is synchronous.
  *
  *
  * Thread-safety requirements on context functions
  * ---
  *
  * These pipe_context functions are executed directly, so they shouldn't use
  * pipe_context in an unsafe way. They are de-facto screen functions now:
  * - create_query
  * - create_batch_query
  * - create_*_state (all CSOs and shaders)
-- 
2.7.4

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[Mesa-dev] [PATCH 03/13] gallium/util: add threaded_context as a pipe_context wrapper

2017-05-12 Thread Marek Olšák
From: Marek Olšák 

v2: - rename num_calls -> num_call_slots (for tc_call)
- rename num_calls -> num_total_call_slots (for tc_batch)
- rename num_offloaded/direct_calls -> num_offloaded/direct_slots
- declare slot[0] instead of slot[1]
- remove no-op leftover code from tc_draw_vbo
- use tc_set_resource_reference to fill threaded_transfer
- fix map flags for sparse buffers
- cosmetic changes
---
 src/gallium/auxiliary/Makefile.sources |3 +
 src/gallium/auxiliary/util/u_threaded_context.c| 2305 
 src/gallium/auxiliary/util/u_threaded_context.h|  349 +++
 .../auxiliary/util/u_threaded_context_calls.h  |   66 +
 4 files changed, 2723 insertions(+)
 create mode 100644 src/gallium/auxiliary/util/u_threaded_context.c
 create mode 100644 src/gallium/auxiliary/util/u_threaded_context.h
 create mode 100644 src/gallium/auxiliary/util/u_threaded_context_calls.h

diff --git a/src/gallium/auxiliary/Makefile.sources 
b/src/gallium/auxiliary/Makefile.sources
index dbdb3ca..baebee6 100644
--- a/src/gallium/auxiliary/Makefile.sources
+++ b/src/gallium/auxiliary/Makefile.sources
@@ -294,20 +294,23 @@ C_SOURCES := \
util/u_surfaces.h \
util/u_tests.c \
util/u_tests.h \
util/u_texture.c \
util/u_texture.h \
util/u_tile.c \
util/u_tile.h \
util/u_time.h \
util/u_transfer.c \
util/u_transfer.h \
+   util/u_threaded_context.c \
+   util/u_threaded_context.h \
+   util/u_threaded_context_calls.h \
util/u_upload_mgr.c \
util/u_upload_mgr.h \
util/u_vbuf.c \
util/u_vbuf.h \
util/u_video.h \
util/u_viewport.h
 
 NIR_SOURCES := \
nir/tgsi_to_nir.c \
nir/tgsi_to_nir.h
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c 
b/src/gallium/auxiliary/util/u_threaded_context.c
new file mode 100644
index 000..b44430f
--- /dev/null
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -0,0 +1,2305 @@
+/**
+ *
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include "util/u_threaded_context.h"
+#include "util/u_cpu_detect.h"
+#include "util/u_format.h"
+#include "util/u_inlines.h"
+#include "util/u_memory.h"
+#include "util/u_upload_mgr.h"
+
+/* 0 = disabled, 1 = assertions, 2 = printfs */
+#define TC_DEBUG 0
+
+#if TC_DEBUG >= 1
+#define tc_assert assert
+#else
+#define tc_assert(x)
+#endif
+
+#if TC_DEBUG >= 2
+#define tc_printf printf
+#define tc_asprintf asprintf
+#define tc_strcmp strcmp
+#else
+#define tc_printf(...)
+#define tc_asprintf(...) 0
+#define tc_strcmp(...) 0
+#endif
+
+#define TC_SENTINEL 0x5ca1ab1e
+
+enum tc_call_id {
+#define CALL(name) TC_CALL_##name,
+#include "u_threaded_context_calls.h"
+#undef CALL
+   TC_NUM_CALLS,
+};
+
+typedef void (*tc_execute)(struct pipe_context *pipe, union tc_payload 
*payload);
+
+static const tc_execute execute_func[TC_NUM_CALLS];
+
+static void
+tc_batch_check(struct tc_batch *batch)
+{
+   tc_assert(batch->sentinel == TC_SENTINEL);
+   tc_assert(batch->sentinel2 == TC_SENTINEL);
+   tc_assert(batch->num_total_call_slots <= TC_CALLS_PER_BATCH);
+}
+
+static void
+tc_debug_check(struct threaded_context *tc)
+{
+   for (unsigned i = 0; i < TC_MAX_BATCHES; i++) {
+  tc_batch_check(&tc->batch_slots[i]);
+  tc_assert(tc->batch_slots[i].pipe == tc->pipe);
+   }
+}
+
+static void
+tc_batch_execute(void *job, int thread_index)
+{
+   struct tc_batch *batch = job;
+   struct pipe_context *pipe = batch->pipe;
+   struct tc_call *last = &batch->call[batch->num_total_call_slots];
+
+   tc_batch_check(batch);
+
+   for (struct tc_call *iter = batch->call; iter 

Re: [Mesa-dev] [PATCH 03/13] gallium/util: add threaded_context as a pipe_context wrapper

2017-05-12 Thread Marek Olšák
[snip]
>> +static unsigned
>> +tc_improve_map_buffer_flags(struct threaded_context *tc,
>> +struct threaded_resource *tres, unsigned
>> usage,
>> +unsigned offset, unsigned size)
>> +{
>> +   /* Handle CPU reads trivially. */
>> +   if (usage & PIPE_TRANSFER_READ) {
>> +  /* Driver aren't allowed to do buffer invalidations. */
>> +  return (usage & ~PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) |
>> + TC_TRANSFER_MAP_NO_INVALIDATE |
>> + TC_TRANSFER_MAP_IGNORE_VALID_RANGE;
>> +   }
>> +
>> +   /* Sparse buffers can't be mapped directly. Use a staging buffer. */
>> +   if (tres->b.flags & PIPE_RESOURCE_FLAG_SPARSE) {
>> +  return (usage & ~(PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE |
>> +PIPE_TRANSFER_UNSYNCHRONIZED)) |
>> + PIPE_TRANSFER_DISCARD_RANGE |
>
>
> Why are we allowed to discard here? Even when a range is mapped only for
> writing, we can't just assume that the whole range will be written by the
> application.
>
> Also, why do we clear the unsynchronized flag? As I understand the code,
we
> do need to synchronize the threads because we're going to use a staging
> buffer. But theoretically, if the driver had a way to do the staging copy
> without waiting for previously submitted draws, it could do so. So... I
> don't think it has a visible effect right now, but I'd rather not remove
the
> unsynchronized flag here.
>
> This may need a bit of clarification in the big comment in the header
file.

That code was indeed completely wrong. I've changed it to this and I moved
this block to the beginning of the function (before the READ handling):

   /* Sparse buffers can't be mapped directly and can't be reallocated
* (fully invalidated). That may just be a radeonsi limitation, but
* the threaded context must obey it with radeonsi.
*/
   if (tres->b.flags & PIPE_RESOURCE_FLAG_SPARSE) {
  /* We can use DISCARD_RANGE instead of full discard. This is the only
   * fast path for sparse buffers that doesn't need thread
synchronization.
   */
  if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)
 usage |= PIPE_TRANSFER_DISCARD_RANGE;

  /* Allow DISCARD_WHOLE_RESOURCE and infering UNSYNCHRONIZED in
drivers.
   * The threaded context doesn't do unsychronized mappings and
invalida-
   * tions of sparse buffers, therefore a correct driver behavior won't
   * result in an incorrect behavior with the threaded context.
   */
  return usage;
   }



>
>
>
>> + TC_TRANSFER_MAP_NO_INVALIDATE |
>> + TC_TRANSFER_MAP_IGNORE_VALID_RANGE;
>> +   }

[snip]
>> + ttrans->b.level = 0;
>> + ttrans->b.usage = usage;
>> + ttrans->b.box = *box;
>> + ttrans->b.stride = 0;
>> + ttrans->b.layer_stride = 0;
>> + *transfer = &ttrans->b;
>> + return map + (box->x % tc->map_buffer_alignment);
>> +  }
>> +   }
>> +
>> +   /* Unsychronized buffer mappings don't have to synchronize the
thread.
>> */
>> +   if (!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC))
>> +  tc_sync_msg(tc, resource->target != PIPE_BUFFER ? "  texture" :
>> +  usage & PIPE_TRANSFER_DISCARD_RANGE ? "
>> discard_range" :
>> +  usage & PIPE_TRANSFER_READ ? "  read" : "  ??");
>> +
>> +   return pipe->transfer_map(pipe, tres->latest ? tres->latest :
>> resource,
>> + level, usage, box, transfer);
>
>
> The ternary operator here should be unnecessary -- tres->latest should
> always be non-NULL.

It's necessary because this codepath is also used by textures where
tres->latest == NULL because it's not initialized explicitly.

[snip]
>> +
>> +static boolean
>> +tc_generate_mipmap(struct pipe_context *_pipe,
>> +   struct pipe_resource *res,
>> +   enum pipe_format format,
>> +   unsigned base_level,
>> +   unsigned last_level,
>> +   unsigned first_layer,
>> +   unsigned last_layer)
>> +{
>> +   struct threaded_context *tc = threaded_context(_pipe);
>> +   struct pipe_context *pipe = tc->pipe;
>> +   struct pipe_screen *screen = pipe->screen;
>> +   unsigned bind = PIPE_BIND_SAMPLER_VIEW;
>> +
>> +   if (util_format_is_depth_or_stencil(format))
>> +  bind = PIPE_BIND_DEPTH_STENCIL;
>> +   else
>> +  bind = PIPE_BIND_RENDER_TARGET;
>> +
>> +   if (!screen->is_format_supported(screen, format, res->target,
>> +res->nr_samples, bind))
>> +  return false;
>
>
> This feels like the kind of thing the state tracker should be checking
> before it calls this function...

True, but the Gallium interface is currently defined such that drivers do
it.

Marek
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[Mesa-dev] [PATCH] Android: r600: fix build when LLVM is disabled

2017-05-12 Thread Rob Herring
There's still an error after my recent clean-up if LLVM is not patched to
enable AMDGPU target:

external/mesa3d/src/amd/common/ac_llvm_util.c:38:2: error: implicit declaration 
of function 'LLVMInitializeAMDGPUTargetInfo' is invalid in C99 
[-Werror,-Wimplicit-function-declaration]
LLVMInitializeAMDGPUTargetInfo();
^
external/mesa3d/src/amd/common/ac_llvm_util.c:39:2: error: implicit declaration 
of function 'LLVMInitializeAMDGPUTarget' is invalid in C99 
[-Werror,-Wimplicit-function-declaration]
LLVMInitializeAMDGPUTarget();
^
external/mesa3d/src/amd/common/ac_llvm_util.c:40:2: error: implicit declaration 
of function 'LLVMInitializeAMDGPUTargetMC' is invalid in C99 
[-Werror,-Wimplicit-function-declaration]
LLVMInitializeAMDGPUTargetMC();
^
external/mesa3d/src/amd/common/ac_llvm_util.c:41:2: error: implicit declaration 
of function 'LLVMInitializeAMDGPUAsmPrinter' is invalid in C99 
[-Werror,-Wimplicit-function-declaration]
LLVMInitializeAMDGPUAsmPrinter();
^

We need to drop libmesa_amd_common when LLVM is disabled, however there's
still a dependency on include paths for ac_binary.h. So explicitly add the
include path when LLVM is disabled.

Signed-off-by: Rob Herring 
---
 src/gallium/drivers/r600/Android.mk | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/r600/Android.mk 
b/src/gallium/drivers/r600/Android.mk
index 26c00f6ccd9c..87f433dbaeb9 100644
--- a/src/gallium/drivers/r600/Android.mk
+++ b/src/gallium/drivers/r600/Android.mk
@@ -30,7 +30,11 @@ include $(CLEAR_VARS)
 
 LOCAL_SRC_FILES := $(C_SOURCES) $(CXX_SOURCES)
 
+ifeq ($(MESA_ENABLE_LLVM),true)
 LOCAL_STATIC_LIBRARIES := libmesa_amd_common
+else
+LOCAL_C_INCLUDES += $(MESA_TOP)/src/amd/common
+endif
 
 LOCAL_SHARED_LIBRARIES := libdrm_radeon
 LOCAL_MODULE := libmesa_pipe_r600
-- 
2.11.0

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[Mesa-dev] [PATCH v2 2/2] i965: perf: fix pointer to integer cast

2017-05-12 Thread Lionel Landwerlin
v2: Just use cast to uintptr_t (Chris)

Reported-by: Mauro Rossi 
Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 95f112e99f0..d1c4b6514bc 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -833,7 +833,7 @@ open_i915_perf_oa_stream(struct brw_context *brw,
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
   .num_properties = ARRAY_SIZE(properties) / 2,
-  .properties_ptr = (uint64_t)properties
+  .properties_ptr = (uintptr_t) properties,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
if (fd == -1) {
--
2.11.0
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Re: [Mesa-dev] [PATCH 2/2] i965/formats: Update the RGB_DXT1 mappings

2017-05-12 Thread Kenneth Graunke
On Thursday, May 11, 2017 4:46:27 PM PDT Nanley Chery wrote:
> The DXT1_RGB* format does not provide the correct behavior for OpenGL in
> the case where color_0 <= color_1. BC1_RGB_UNORM with a alpha set to 1
> provides the behavior which matches the spec.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100925
> Cc: 
> Signed-off-by: Nanley Chery 
> ---
>  src/mesa/drivers/dri/i965/brw_surface_formats.c | 15 ++-
>  1 file changed, 2 insertions(+), 13 deletions(-)

Two things I was worried about:

1. Where's the swizzling code in this patch?

  ->  it turns out that we already swizzle A -> 1 when the mesa format
  does not have alpha, but the hardware format does.  So, it's
  already there, we don't need any new code :)

2. Will it impact performance?

  ->  Might be nice to check...but the compressed data is the same size
  for both formats, so it's just how it interprets it...doubtful.

  This will cause recompiles on Ivybridge and older hardware, due
  to the implicit texture swizzling.  Sad, but not sure we can do
  anything about it.  Could change the default to RGB1 if that's
  better...

It might be nice to copy more of the findings you posted in bugzilla
into the commit messages - people are more likely to find your commit
message when blaming this code than to look at the bug.

It looks like Windows does this same workaround on Gen7.5+.  I'm not
clear what they do on Gen7-.

Great find!  Both are:
Reviewed-by: Kenneth Graunke 

> diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c 
> b/src/mesa/drivers/dri/i965/brw_surface_formats.c
> index 7b17e11125..b176a21c22 100644
> --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
> +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
> @@ -94,14 +94,14 @@ brw_isl_format_for_mesa_format(mesa_format mesa_format)
>[MESA_FORMAT_L_SRGB8] = ISL_FORMAT_L8_UNORM_SRGB,
>[MESA_FORMAT_L8A8_SRGB] = ISL_FORMAT_L8A8_UNORM_SRGB,
>[MESA_FORMAT_A8L8_SRGB] = 0,
> -  [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_DXT1_RGB_SRGB,
> +  [MESA_FORMAT_SRGB_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
>[MESA_FORMAT_SRGBA_DXT1] = ISL_FORMAT_BC1_UNORM_SRGB,
>[MESA_FORMAT_SRGBA_DXT3] = ISL_FORMAT_BC2_UNORM_SRGB,
>[MESA_FORMAT_SRGBA_DXT5] = ISL_FORMAT_BC3_UNORM_SRGB,
>  
>[MESA_FORMAT_RGB_FXT1] = ISL_FORMAT_FXT1,
>[MESA_FORMAT_RGBA_FXT1] = ISL_FORMAT_FXT1,
> -  [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_DXT1_RGB,
> +  [MESA_FORMAT_RGB_DXT1] = ISL_FORMAT_BC1_UNORM,
>[MESA_FORMAT_RGBA_DXT1] = ISL_FORMAT_BC1_UNORM,
>[MESA_FORMAT_RGBA_DXT3] = ISL_FORMAT_BC2_UNORM,
>[MESA_FORMAT_RGBA_DXT5] = ISL_FORMAT_BC3_UNORM,
> @@ -541,17 +541,6 @@ translate_tex_format(struct brw_context *brw,
> */
>return ISL_FORMAT_R32G32B32A32_FLOAT;
>  
> -   case MESA_FORMAT_SRGB_DXT1:
> -  if (brw->gen == 4 && !brw->is_g4x) {
> - /* Work around missing SRGB DXT1 support on original gen4 by just
> -  * skipping SRGB decode.  It's not worth not supporting sRGB in
> -  * general to prevent this.
> -  */
> - WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
> - mesa_format = MESA_FORMAT_RGB_DXT1;
> -  }
> -  return brw_isl_format_for_mesa_format(mesa_format);
> -
> case MESA_FORMAT_RGBA_ASTC_4x4:
> case MESA_FORMAT_RGBA_ASTC_5x4:
> case MESA_FORMAT_RGBA_ASTC_5x5:
> 

Nice to be rid of this!  Using an RGBA format and setting alpha to 1 is
a lot better than not doing sRGB decode.


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Re: [Mesa-dev] [PATCH 0/6] Various fixes to integer GetUniform*()

2017-05-12 Thread Kenneth Graunke
On Friday, May 12, 2017 1:40:49 AM PDT Nicolai Hähnle wrote:
> On 11.05.2017 13:10, Iago Toral Quiroga wrote:
> > This series is an update on a previous patch by Ken that fixed
> > a CTS test but never got merged due to the mess with the CTS repositories
> > at that time, plus a number of additional fixes for recently added int64 
> > paths.
> >
> > Patch 1 fixes indentation.
> > Patch 2 is the original patch by Ken, only tha rebased and amended to 
> > support
> > conversions from 64-bit integer types.
> > Patch 3 is the same as patch 2, but for 64-bit integer.
> > Patches 4-6 are two fixes for 64-bit integer conversion paths.
> >
> > Ken: the release tarball in the khronos page still links to the old test 
> > suite
> > from 2016, however, it seems that it should be possible to send submissions 
> > from
> > the new repository as well (see [1]).
> 
> Certainly not from VK-GL-CTS, unfortunately, since it's missing the GTF 
> parts of the tests, and kc-cts hasn't been approved yet, either. On the 
> other hand, it should be possible to provide a submission package where 
> the change to the uniform test is backported, so patches 2 & 3 (modulo 
> comments) are probably fine.
> 
> Cheers,
> Nicolai

Yeah, I have no problem with merging these.  We can always backport the
test fix if it matters.

--Ken


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Re: [Mesa-dev] Requests for Proposal for hosting XDC 2018

2017-05-12 Thread Daniel Vetter
On Fri, May 12, 2017 at 12:08 AM, Daniel Vetter  wrote:
> The X.org board is soliciting proposals to host XDC in 2017

That's meant to read 2018 too of course, I missed one date ...
-Daniel
-- 
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+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Mesa-dev] [PATCH 0/2] Allow redeclaration of GLSL builtins; fixes Dying Light and Dead Island Definitive Edition

2017-05-12 Thread John Brooks
On Fri, May 12, 2017 at 03:56:26PM +0200, Samuel Pitoiset wrote:
> 
> 
> On 05/12/2017 03:39 PM, John Brooks wrote:
> >Since release, Dying Light and Dead Island Definitive Edition have been 
> >broken
> >on Mesa, producing at best only a black screen after loading. I found that 
> >the
> >root of the problem is that their vertex shaders redeclare the GLSL builtin
> >gl_VertexID, which Mesa's compiler considers to be an error:
> >
> > error: `gl_VertexID' redeclared
> >
> >These patches make the compiler more lenient so that the shaders compile.
> >Because such redeclarations are not explicitly valid in the spec, this
> >behaviour is selectively activated by the new 
> >allow_glsl_builtin_redeclaration
> >driconf option, which has been enabled for both games in the default drirc.
> >
> >With this change, both games work on Mesa and render correctly. Note that the
> >games require OpenGL 4.4+, and so it is necessary to launch them with
> >MESA_GL_VERSION_OVERRIDE and MESA_GLSL_VERSION_OVERRIDE set to OpenGL 4.4 
> >(GLSL
> >440) or higher.
> >
> >Contrary to popular belief, this problem actually had nothing whatsoever to 
> >do
> >with compatibility profiles. Forcing Mesa to create a higher version
> >compatibility profile with MESA_GL_VERSION_OVERRIDE=4.5COMPAT or
> >allow_higher_compat_version results in graphical glitches, so don't use that.
> 
> I wonder if there is multiple versions of Dying Light, but using
> MESA_GL_VERSION_OVERRIDE=4.4 and MESA_GLSL_VERSION_OVERRIDE=440 doesn't work
> for me (game crash at launching). Also it requests some unsupported GL
> functions (compat?).
> 
> IIRC, Dying Light wants a GL 4.4 compat profile, I guess Timothy can
> confirm?
> 
> What's your steam app ID?
> 
> Btw, you probably don't need to override the GL/GLSL versions, it should be
> backward compatible.
> 

Steam App ID 239140. The use of legacy functions (such as glBegin) in frame 0
is SDL's doing:


I don't know why your game would crash on launch. My first thought would be
steam runtime issues though. Make sure Steam runtime is enabled and remove
~/.local/share/Steam/ubuntu12_32/steam-runtime/amd64/usr/lib/x86_64-linux-gnu/libstdc++.so.6

The version override is necessary since the game will not render at all with a
3.0 compat profile, which is what it gets without an override.

--
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Re: [Mesa-dev] [PATCH 2/2] docs: extend until the end of August

2017-05-12 Thread Emil Velikov
On 12 May 2017 at 14:03, Emil Velikov  wrote:
> On 6 May 2017 at 16:46, Andres Gomez  wrote:
>> Completed the 17.1 cycle and added the beginning of the 17.2 one.
>>
>> Cc: Emil Velikov 
>> Cc: Juan A. Suarez Romero 
>> Signed-off-by: Andres Gomez 
>> ---
>>  docs/release-calendar.html | 62 
>> +-
>>  1 file changed, 61 insertions(+), 1 deletion(-)
>>
>> diff --git a/docs/release-calendar.html b/docs/release-calendar.html
>> index 897fb41ead..72dfdd2d07 100644
>> --- a/docs/release-calendar.html
>> +++ b/docs/release-calendar.html
>> @@ -58,7 +58,7 @@ if you'd like to nominate a patch in the next stable 
>> release.
>>  Final planned release for the 17.0 series
>>  
>>  
>> -17.1
>> +17.1
>>  2017-04-28
>>  17.1.0-rc3
>>  Emil Velikov
>> @@ -87,6 +87,66 @@ if you'd like to nominate a patch in the next stable 
>> release.
>>  Andres Gomez
>>  
>>  
>> +
>> +2017-06-30
>> +17.1.4
>> +Andres Gomez
>> +
>> +
>> +
>> +2017-07-14
>> +17.1.5
>> +Andres Gomez
>> +
>> +
>> +
>> +2017-07-28
>> +17.1.6
>> +Emil Velikov
>> +
>> +
>> +
>> +2017-08-11
>> +17.1.7
>> +Juan A. Suarez Romero
>> +
>> +
>> +
>> +2017-08-25
>> +17.1.8
>> +Andres Gomez
>> +Final planned release for the 17.1 series
> This seems off. The final 17.1 should be out around the same time as 17.2.1.
>
Thanks for the correction Andres - seems like I misread the dates.
Please ignore my comment.

-Emil
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Re: [Mesa-dev] [PATCH 0/2] Allow redeclaration of GLSL builtins; fixes Dying Light and Dead Island Definitive Edition

2017-05-12 Thread Samuel Pitoiset



On 05/12/2017 03:39 PM, John Brooks wrote:

Since release, Dying Light and Dead Island Definitive Edition have been broken
on Mesa, producing at best only a black screen after loading. I found that the
root of the problem is that their vertex shaders redeclare the GLSL builtin
gl_VertexID, which Mesa's compiler considers to be an error:

 error: `gl_VertexID' redeclared

These patches make the compiler more lenient so that the shaders compile.
Because such redeclarations are not explicitly valid in the spec, this
behaviour is selectively activated by the new allow_glsl_builtin_redeclaration
driconf option, which has been enabled for both games in the default drirc.

With this change, both games work on Mesa and render correctly. Note that the
games require OpenGL 4.4+, and so it is necessary to launch them with
MESA_GL_VERSION_OVERRIDE and MESA_GLSL_VERSION_OVERRIDE set to OpenGL 4.4 (GLSL
440) or higher.

Contrary to popular belief, this problem actually had nothing whatsoever to do
with compatibility profiles. Forcing Mesa to create a higher version
compatibility profile with MESA_GL_VERSION_OVERRIDE=4.5COMPAT or
allow_higher_compat_version results in graphical glitches, so don't use that.


I wonder if there is multiple versions of Dying Light, but using 
MESA_GL_VERSION_OVERRIDE=4.4 and MESA_GLSL_VERSION_OVERRIDE=440 doesn't 
work for me (game crash at launching). Also it requests some unsupported 
GL functions (compat?).


IIRC, Dying Light wants a GL 4.4 compat profile, I guess Timothy can 
confirm?


What's your steam app ID?

Btw, you probably don't need to override the GL/GLSL versions, it should 
be backward compatible.





A few extra notes for users reading this: I had terrible, unplayable
performance with Dying Light on a configuration with an R9 290, Mesa 17.1-rc3,
and the radeon kernel driver on kernel 4.10. Switching to the amdgpu driver
(enable CONFIG_DRM_AMDGPU_CIK, blacklist radeon, install amdgpu DDX and set
Driver "amdgpu" in xorg.conf) on kernel 4.11 made it playable.  With amdgpu it
hovers around 25-35fps except in select areas (such as the Tower lobby and near
Zere's trailer) near the start of the game where the framerate plummets for no
apparent reason. Dead Island Definitive Edition performs much better in general
than Dying Light, at least on amdgpu. I did not test DIDE on radeon. Ongoing
TTM optimization work may mitigate the performance problems in the future.


The main thing I'm unsure of is whether allowing GLSL builtin redeclarations
should be a driconf option or default behaviour. I looked through the GLSL spec
and initially thought that such redeclarations were permitted because of this
line from page 66 of 
:

 in vec4 gl_FragCoord; // redeclaration that changes nothing is allowed

But others on IRC interpreted it as referring only to gl_FragCoord, which I
agree would make sense given the context. So to be on the safe side I made it
conditional on a driconf option. I leave the final decision to the reviewers.
Let me know what you think.

Thank you to to funfunctor, notaz, and others from the #radeon IRC channel for
their suggestions and their help with analyzing the game binaries.

--
John Brooks
Frogging101 on IRC and elsewhere


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[Mesa-dev] [PATCH 2/3] glsl: Conditionally allow redeclaration of builtins

2017-05-12 Thread John Brooks
Conditional on allow_glsl_builtin_redeclaration driconf option.

Signed-off-by: John Brooks 
---
 src/compiler/glsl/ast_to_hir.cpp | 16 
 src/compiler/glsl/glsl_parser_extras.cpp |  2 ++
 src/compiler/glsl/glsl_parser_extras.h   |  1 +
 3 files changed, 19 insertions(+)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 0dc69ef..c743dfe 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -4276,6 +4276,22 @@ get_variable_being_redeclared(ir_variable *var, YYLTYPE 
loc,
*/
   earlier->data.precision = var->data.precision;
 
+   } else if(earlier->data.how_declared == ir_var_declared_implicitly &&
+ state->allow_builtin_redeclaration) {
+  /* Allow verbatim redeclarations of built-in variables. Not explicitly
+   * valid, but some applications do it.
+   */
+  if(earlier->data.mode != var->data.mode &&
+ !(earlier->data.mode == ir_var_system_value &&
+   var->data.mode == ir_var_shader_in)) {
+ _mesa_glsl_error(&loc, state,
+  "redeclaration of `%s' with incorrect qualifiers",
+  var->name);
+  } else if (earlier->type != var->type) {
+ _mesa_glsl_error(&loc, state,
+  "redeclaration of `%s' has incorrect type",
+  var->name);
+  }
} else if (allow_all_redeclarations) {
   if (earlier->data.mode != var->data.mode) {
  _mesa_glsl_error(&loc, state,
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index d731e35..1405a7e 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -305,6 +305,8 @@ _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct 
gl_context *_ctx,
   sizeof(this->atomic_counter_offsets));
this->allow_extension_directive_midshader =
   ctx->Const.AllowGLSLExtensionDirectiveMidShader;
+   this->allow_builtin_redeclaration =
+  ctx->Const.AllowGLSLBuiltinRedeclaration;
 
this->cs_input_local_size_variable_specified = false;
 
diff --git a/src/compiler/glsl/glsl_parser_extras.h 
b/src/compiler/glsl/glsl_parser_extras.h
index 3a84d65..3981994 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -842,6 +842,7 @@ struct _mesa_glsl_parse_state {
unsigned atomic_counter_offsets[MAX_COMBINED_ATOMIC_BUFFERS];
 
bool allow_extension_directive_midshader;
+   bool allow_builtin_redeclaration;
 
/**
 * Known subroutine type declarations.
-- 
2.7.4

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[Mesa-dev] [PATCH 1/3] driconf: Add allow_glsl_builtin_redeclaration option

2017-05-12 Thread John Brooks
This option will allow GLSL builtins to be redeclared verbatim (e.g.
redeclaring "in int gl_VertexID" in a vertex shader). This is not strictly
valid and would normally fail to compile, but some applications (such as
newer Techland ports) do it and need more leniency.

Signed-off-by: John Brooks 
---
 src/gallium/include/state_tracker/st_api.h  | 1 +
 src/gallium/state_trackers/dri/dri_screen.c | 3 +++
 src/mesa/drivers/dri/common/xmlpool/t_options.h | 5 +
 src/mesa/drivers/dri/i965/brw_context.c | 3 +++
 src/mesa/drivers/dri/i965/intel_screen.c| 1 +
 src/mesa/main/mtypes.h  | 5 +
 src/mesa/state_tracker/st_extensions.c  | 2 ++
 7 files changed, 20 insertions(+)

diff --git a/src/gallium/include/state_tracker/st_api.h 
b/src/gallium/include/state_tracker/st_api.h
index 9d0eb3a..8dda438 100644
--- a/src/gallium/include/state_tracker/st_api.h
+++ b/src/gallium/include/state_tracker/st_api.h
@@ -246,6 +246,7 @@ struct st_config_options
unsigned force_glsl_version;
boolean force_s3tc_enable;
boolean allow_glsl_extension_directive_midshader;
+   boolean allow_glsl_builtin_redeclaration;
boolean allow_higher_compat_version;
boolean glsl_zero_init;
boolean force_glsl_abs_sqrt;
diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
b/src/gallium/state_trackers/dri/dri_screen.c
index 998e8ef..2ea892d 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -75,6 +75,7 @@ const __DRIconfigOptionsExtension gallium_config_options = {
  DRI_CONF_DISABLE_SHADER_BIT_ENCODING("false")
  DRI_CONF_FORCE_GLSL_VERSION(0)
  DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
+ DRI_CONF_ALLOW_GLSL_BUILTIN_REDECLARATION("false")
  DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
  DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
   DRI_CONF_SECTION_END
@@ -108,6 +109,8 @@ dri_fill_st_options(struct dri_screen *screen)
   driQueryOptionb(optionCache, "force_s3tc_enable");
options->allow_glsl_extension_directive_midshader =
   driQueryOptionb(optionCache, "allow_glsl_extension_directive_midshader");
+   options->allow_glsl_builtin_redeclaration =
+  driQueryOptionb(optionCache, "allow_glsl_builtin_redeclaration");
options->allow_higher_compat_version =
   driQueryOptionb(optionCache, "allow_higher_compat_version");
options->glsl_zero_init = driQueryOptionb(optionCache, "glsl_zero_init");
diff --git a/src/mesa/drivers/dri/common/xmlpool/t_options.h 
b/src/mesa/drivers/dri/common/xmlpool/t_options.h
index cd4f025..c873f31 100644
--- a/src/mesa/drivers/dri/common/xmlpool/t_options.h
+++ b/src/mesa/drivers/dri/common/xmlpool/t_options.h
@@ -115,6 +115,11 @@ 
DRI_CONF_OPT_BEGIN_B(allow_glsl_extension_directive_midshader, def) \
 DRI_CONF_DESC(en,gettext("Allow GLSL #extension directives in the 
middle of shaders")) \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_ALLOW_GLSL_BUILTIN_REDECLARATION(def) \
+DRI_CONF_OPT_BEGIN_B(allow_glsl_builtin_redeclaration, def) \
+DRI_CONF_DESC(en,gettext("Allow GLSL built-in variables to be 
redeclared verbatim")) \
+DRI_CONF_OPT_END
+
 #define DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION(def) \
 DRI_CONF_OPT_BEGIN_B(allow_higher_compat_version, def) \
 DRI_CONF_DESC(en,gettext("Allow a higher compat profile (version 3.1+) 
for apps that request it")) \
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 5055dd7..f6bce4d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -934,6 +934,9 @@ brw_process_driconf_options(struct brw_context *brw)
ctx->Const.AllowGLSLExtensionDirectiveMidShader =
   driQueryOptionb(options, "allow_glsl_extension_directive_midshader");
 
+   ctx->Const.AllowGLSLBuiltinRedeclaration =
+  driQueryOptionb(options, "allow_glsl_builtin_redeclaration");
+
ctx->Const.AllowHigherCompatVersion =
   driQueryOptionb(options, "allow_higher_compat_version");
 
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 3717728..9f9cdc8 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -89,6 +89,7 @@ DRI_CONF_BEGIN
   DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
   DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
   DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
+  DRI_CONF_ALLOW_GLSL_BUILTIN_REDECLARATION("false")
   DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
   DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
 
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 28d3d948..47b8b8d 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3630,6 +3630,11 @@ struct gl_constants
GLboolean AllowGLSLExtensionDirectiveMidShader;
 
/**
+* Allow GLSL built-in variables to be redeclared verbatim
+  

[Mesa-dev] [PATCH 0/2] Allow redeclaration of GLSL builtins; fixes Dying Light and Dead Island Definitive Edition

2017-05-12 Thread John Brooks
Since release, Dying Light and Dead Island Definitive Edition have been broken
on Mesa, producing at best only a black screen after loading. I found that the
root of the problem is that their vertex shaders redeclare the GLSL builtin
gl_VertexID, which Mesa's compiler considers to be an error:

error: `gl_VertexID' redeclared

These patches make the compiler more lenient so that the shaders compile.
Because such redeclarations are not explicitly valid in the spec, this
behaviour is selectively activated by the new allow_glsl_builtin_redeclaration
driconf option, which has been enabled for both games in the default drirc.

With this change, both games work on Mesa and render correctly. Note that the
games require OpenGL 4.4+, and so it is necessary to launch them with
MESA_GL_VERSION_OVERRIDE and MESA_GLSL_VERSION_OVERRIDE set to OpenGL 4.4 (GLSL
440) or higher.

Contrary to popular belief, this problem actually had nothing whatsoever to do
with compatibility profiles. Forcing Mesa to create a higher version
compatibility profile with MESA_GL_VERSION_OVERRIDE=4.5COMPAT or
allow_higher_compat_version results in graphical glitches, so don't use that.


A few extra notes for users reading this: I had terrible, unplayable
performance with Dying Light on a configuration with an R9 290, Mesa 17.1-rc3,
and the radeon kernel driver on kernel 4.10. Switching to the amdgpu driver
(enable CONFIG_DRM_AMDGPU_CIK, blacklist radeon, install amdgpu DDX and set
Driver "amdgpu" in xorg.conf) on kernel 4.11 made it playable.  With amdgpu it
hovers around 25-35fps except in select areas (such as the Tower lobby and near
Zere's trailer) near the start of the game where the framerate plummets for no
apparent reason. Dead Island Definitive Edition performs much better in general
than Dying Light, at least on amdgpu. I did not test DIDE on radeon. Ongoing
TTM optimization work may mitigate the performance problems in the future.


The main thing I'm unsure of is whether allowing GLSL builtin redeclarations
should be a driconf option or default behaviour. I looked through the GLSL spec
and initially thought that such redeclarations were permitted because of this
line from page 66 of 
:

in vec4 gl_FragCoord; // redeclaration that changes nothing is allowed

But others on IRC interpreted it as referring only to gl_FragCoord, which I
agree would make sense given the context. So to be on the safe side I made it
conditional on a driconf option. I leave the final decision to the reviewers.
Let me know what you think.

Thank you to to funfunctor, notaz, and others from the #radeon IRC channel for
their suggestions and their help with analyzing the game binaries.

--
John Brooks
Frogging101 on IRC and elsewhere

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[Mesa-dev] [PATCH 3/3] drirc: Add allow_glsl_builtin_redeclaration for Dying Light and Dead Island Definitive Edition

2017-05-12 Thread John Brooks
This fixes the long-standing problem with Dying Light where the game would
produce a black screen when running under Mesa. This happened because the
game's vertex shaders redeclare gl_VertexID, which is a GLSL builtin.
Mesa's GLSL compiler is a little more strict than others, and would not
compile them:

error: `gl_VertexID' redeclared

The allow_glsl_builtin_redeclaration directive allows the shaders to
compile and the game to render. The game also requires OpenGL 4.4+ (GLSL
440), but does not request it explicitly. It must be forced with an
override, such as MESA_GL_VERSION_OVERRIDE=4.5 and
MESA_GLSL_VERSION_OVERRIDE=450. A compatibility context is *not* required
and forcing one with 4.5COMPAT or allow_higher_compat_version results in
graphical artifacts.

Dead Island Definitive Edition is another Techland port on the same engine
with the same problems, so we set the allow_glsl_builtin_redeclaration
option for that game as well.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96449
Signed-off-by: John Brooks 
---
 src/mesa/drivers/dri/common/drirc | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/common/drirc 
b/src/mesa/drivers/dri/common/drirc
index 14d7713..e1b3722 100644
--- a/src/mesa/drivers/dri/common/drirc
+++ b/src/mesa/drivers/dri/common/drirc
@@ -17,6 +17,10 @@ Application bugs worked around in this file:
   an #extension directive in the middle of its shaders, which is illegal
   in GLSL.
 
+* Dying Light and Dead Island Definitive Edition redeclare vertex shader
+  built-ins (specifically gl_VertexID), which causes the vertex shaders to fail
+  to compile.
+
 TODO: document the other workarounds.
 
 -->
@@ -81,8 +85,15 @@ TODO: document the other workarounds.
 
 
 
-
+
 
+
+
+
+
+
+
+
 
 
 
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 3/3] egl/wayland: use the image_driver alongside the image_loader

2017-05-12 Thread Emil Velikov
On 11 May 2017 at 23:22, Emil Velikov  wrote:
> From: Emil Velikov 
>
> Analogous to previous commit.
>
> Cc: Derek Foreman 
> Signed-off-by: Emil Velikov 
> ---
> Derek, afaict we should be able to revert commit 534ea2b5ba0 with this
> in place.
>
> Can you please apply this patch, revert 534ea2b5ba0 and give it a test?
> If things are still broken, please send me a backtrace while breaking
> in image_get_buffers().
>
The following hunk should be squashed with this patch


--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -148,7 +148,7 @@ dri2_wl_create_window_surface(_EGLDriver *drv,
_EGLDisplay *disp,
   if (!_eglInitSurface(&dri2_surf->base, disp, EGL_WINDOW_BIT, conf,
attrib_list))
  goto cleanup_surf;

-   if (dri2_dpy->dri2) {
+   if (dri2_dpy->image_driver || dri2_dpy->dri2) {
  if (conf->RedSize == 5)
 dri2_surf->format = WL_DRM_FORMAT_RGB565;
  else if (conf->AlphaSize == 0)

-Emil
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Re: [Mesa-dev] [PATCH 2/2] docs: extend until the end of August

2017-05-12 Thread Emil Velikov
On 6 May 2017 at 16:46, Andres Gomez  wrote:
> Completed the 17.1 cycle and added the beginning of the 17.2 one.
>
> Cc: Emil Velikov 
> Cc: Juan A. Suarez Romero 
> Signed-off-by: Andres Gomez 
> ---
>  docs/release-calendar.html | 62 
> +-
>  1 file changed, 61 insertions(+), 1 deletion(-)
>
> diff --git a/docs/release-calendar.html b/docs/release-calendar.html
> index 897fb41ead..72dfdd2d07 100644
> --- a/docs/release-calendar.html
> +++ b/docs/release-calendar.html
> @@ -58,7 +58,7 @@ if you'd like to nominate a patch in the next stable 
> release.
>  Final planned release for the 17.0 series
>  
>  
> -17.1
> +17.1
>  2017-04-28
>  17.1.0-rc3
>  Emil Velikov
> @@ -87,6 +87,66 @@ if you'd like to nominate a patch in the next stable 
> release.
>  Andres Gomez
>  
>  
> +
> +2017-06-30
> +17.1.4
> +Andres Gomez
> +
> +
> +
> +2017-07-14
> +17.1.5
> +Andres Gomez
> +
> +
> +
> +2017-07-28
> +17.1.6
> +Emil Velikov
> +
> +
> +
> +2017-08-11
> +17.1.7
> +Juan A. Suarez Romero
> +
> +
> +
> +2017-08-25
> +17.1.8
> +Andres Gomez
> +Final planned release for the 17.1 series
This seems off. The final 17.1 should be out around the same time as 17.2.1.

Other than those nitpicks the series is
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH 1/2] docs: update "Release manager" column

2017-05-12 Thread Emil Velikov
On 6 May 2017 at 16:46, Andres Gomez  wrote:
> Cc: Emil Velikov 
> Cc: Juan A. Suarez Romero 
> Signed-off-by: Andres Gomez 
> ---
>  docs/release-calendar.html | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/docs/release-calendar.html b/docs/release-calendar.html
> index fa67987da1..897fb41ead 100644
> --- a/docs/release-calendar.html
> +++ b/docs/release-calendar.html
> @@ -48,7 +48,7 @@ if you'd like to nominate a patch in the next stable 
> release.
>  
>  2017-05-12
>  17.0.6
> -Emil Velikov
> +Andres Gomez
>  
>  
>  
> @@ -73,18 +73,18 @@ if you'd like to nominate a patch in the next stable 
> release.
>  
>  2017-05-19
>  17.1.1
> -Emil Velikov
> +Juan A. Suarez Romero
>  
>  
>  2017-06-02
>  17.1.2
> -Emil Velikov
> +Juan A. Suarez Romero
>  
>  
>  
>  2017-06-16
>  17.1.3
> -Emil Velikov
> +Andres Gomez
I will be around to do 17.1.1 and 17.1.3

-Emil
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Re: [Mesa-dev] [PATCH v2] bin/get-fixes-pick-list.sh: bring back the warning

2017-05-12 Thread Emil Velikov
On 12 May 2017 at 09:33, Andres Gomez  wrote:
> We warn again if there is more than one line with the "fixes:" tag.
>
> The warning is only silenced when the commit has landed already or we
> output another message for every "fixes:" tag.
>
Since "only silenced" is no longer true, use something like the following?

"The warning is silenced when the commit has already landed or each
fixes tag reference a commit that is in branch."

> Signed-off-by: Andres Gomez 
> ---
>  bin/get-fixes-pick-list.sh | 19 +--
>  1 file changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/bin/get-fixes-pick-list.sh b/bin/get-fixes-pick-list.sh
> index cf95f28377..3ea649a0a4 100755
> --- a/bin/get-fixes-pick-list.sh
> +++ b/bin/get-fixes-pick-list.sh
> @@ -33,7 +33,14 @@ do
>
> # For each one try to extract the tag
> fixes_count=`git show $sha | grep -i "fixes:" | wc -l`
> +   warn=`(test $fixes_count -gt 1 && echo $fixes_count) || echo 0`
> while [ $fixes_count -gt 0 ] ; do
> +   # Skip if it has been already landed.
> +   if grep -q ^$sha already_picked ; then
> +   warn=0
> +   break
> +   fi
> +
Nit: please move this just after the cherry-ignore hunk.

> fixes=`git show $sha | grep -i "fixes:" | tail -n 
> $fixes_count | head -n 1`
Are you sure we need the "tail -n $fixes_count | " here? Feel free to
squash with this patch (+add small note in commit message) or address
as follow-up.

With the above
Reviewed-by: Emil Velikov 

Thanks
Emil
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Re: [Mesa-dev] [PATCH 10/13] egl/x11: make use of the dri2_display_destroy() helper

2017-05-12 Thread Emil Velikov
On 12 May 2017 at 09:20, Tapani Pälli  wrote:
> this patch causes a crash with egl-create-surface Piglit test
>
Seems like we have a bunch of missing NULL checks throughout.
Please ignore the patch dri2_display_destroy patches for the times being.

-Emil
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Re: [Mesa-dev] [PATCH 2/2] i965: perf: fix pointer to integer cast

2017-05-12 Thread Chris Wilson
On Fri, May 12, 2017 at 12:37:26PM +0100, Lionel Landwerlin wrote:
> Reported-by: Mauro Rossi 
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/mesa/drivers/dri/i965/brw_performance_query.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
> b/src/mesa/drivers/dri/i965/brw_performance_query.c
> index 95f112e99f0..fa601400cb5 100644
> --- a/src/mesa/drivers/dri/i965/brw_performance_query.c
> +++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
> @@ -833,7 +833,7 @@ open_i915_perf_oa_stream(struct brw_context *brw,
> I915_PERF_FLAG_FD_NONBLOCK |
> I915_PERF_FLAG_DISABLED,
>.num_properties = ARRAY_SIZE(properties) / 2,
> -  .properties_ptr = (uint64_t)properties
> +  .properties_ptr = (uint64_t) (uintptr_t) properties,

The final cast is implict. Just the cast to uintptr_t is required to
shut the compiler up for 32b builds.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Mesa-dev] [PATCH 2/2] i965: perf: fix pointer to integer cast

2017-05-12 Thread Lionel Landwerlin
Reported-by: Mauro Rossi 
Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 95f112e99f0..fa601400cb5 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -833,7 +833,7 @@ open_i915_perf_oa_stream(struct brw_context *brw,
I915_PERF_FLAG_FD_NONBLOCK |
I915_PERF_FLAG_DISABLED,
   .num_properties = ARRAY_SIZE(properties) / 2,
-  .properties_ptr = (uint64_t)properties
+  .properties_ptr = (uint64_t) (uintptr_t) properties,
};
int fd = drmIoctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, ¶m);
if (fd == -1) {
-- 
2.11.0

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[Mesa-dev] [PATCH 1/2] intel: gen-decoder: fix xml parser leak

2017-05-12 Thread Lionel Landwerlin
In the unlikely case the parsing of genxml files fails, we were
leaking an xml parser object.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/common/gen_decoder.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 24147340f58..35aa9f63ffa 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -650,9 +650,9 @@ gen_spec_load_from_path(const struct gen_device_info 
*devinfo,
   len = fread(buf, 1, XML_BUFFER_SIZE, input);
   if (len == 0) {
  fprintf(stderr, "fread: %m\n");
- fclose(input);
- free(filename);
- return NULL;
+ free(ctx.spec);
+ ctx.spec = NULL;
+ goto end;
   }
   if (XML_ParseBuffer(ctx.parser, len, len == 0) == 0) {
  fprintf(stderr,
@@ -660,12 +660,13 @@ gen_spec_load_from_path(const struct gen_device_info 
*devinfo,
  XML_GetCurrentLineNumber(ctx.parser),
  XML_GetCurrentColumnNumber(ctx.parser),
  XML_ErrorString(XML_GetErrorCode(ctx.parser)));
- fclose(input);
- free(filename);
- return NULL;
+ free(ctx.spec);
+ ctx.spec = NULL;
+ goto end;
   }
} while (len > 0);
 
+ end:
XML_ParserFree(ctx.parser);
 
fclose(input);
-- 
2.11.0

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Re: [Mesa-dev] [PATCH] i965: fix cast in OA performance query code

2017-05-12 Thread Mauro Rossi
2017-05-12 8:18 GMT+02:00 Tapani Pälli :
>
>
> On 05/11/2017 04:00 PM, Lionel Landwerlin wrote:
>>
>> On 11/05/17 13:58, Lionel Landwerlin wrote:
>>>
>>> On 11/05/17 12:27, Tapani Pälli wrote:



 On 05/11/2017 02:23 PM, Emil Velikov wrote:
>
> On 1 May 2017 at 12:09, Mauro Rossi  wrote:
>>
>> Fixes the following building error happening on marshmallow-x86
>> with Ubuntu 16.04 LTS stock build essentials package
>> and by the book Android build system.
>>
>> external/mesa/src/mesa/drivers/dri/i965/brw_performance_query.c: In
>> function 'open_i915_perf_oa_stream':
>>
>> external/mesa/src/mesa/drivers/dri/i965/brw_performance_query.c:836:25:
>> error: cast from pointer to integer of different size
>> [-Werror=pointer-to-int-cast]
>> .properties_ptr = (uint64_t)properties
>>   ^
>>
>> Fixes: 458468c "i965: Expose OA counters via INTEL_performance_query"
>> ---
>>   src/mesa/drivers/dri/i965/brw_performance_query.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c
>> b/src/mesa/drivers/dri/i965/brw_performance_query.c
>> index 95f112e..7436b39 100644
>> --- a/src/mesa/drivers/dri/i965/brw_performance_query.c
>> +++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
>> @@ -833,7 +833,7 @@ open_i915_perf_oa_stream(struct brw_context *brw,
>>  I915_PERF_FLAG_FD_NONBLOCK |
>>  I915_PERF_FLAG_DISABLED,
>> .num_properties = ARRAY_SIZE(properties) / 2,
>> -  .properties_ptr = (uint64_t)properties
>> +  .properties_ptr = (uint64_t *)properties
>
> Rob, others - do we still need this?


 I did brief look here but not 100% sure if this is right fix,
 properties_ptr is uint64_t so I guess you might end up with another
 warning/error here, should uintptr_t be used instead?
>>>
>>>
>>> Casting to uint64_t* doesn't seem right.
>>> Maybe do it like this :
>>>
>>>
>>> https://cgit.freedesktop.org/mesa/mesa/tree/src/mesa/drivers/dri/i965/brw_bufmgr.c#n687
>>
>>
>> Sorry, picked up the wrong line :
>>
>>
>> https://cgit.freedesktop.org/mesa/mesa/tree/src/mesa/drivers/dri/i965/brw_bufmgr.c#n862
>
>
> Yes, this looks the correct solution.

I propose that Lionel sends a patch, or in any case is considered as
the real author.
Mauro
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Re: [Mesa-dev] [RFC] st/dri: implement createImageWithModifiers

2017-05-12 Thread Lucas Stach
Hi Varad,

Am Freitag, den 12.05.2017, 15:11 +0530 schrieb Varad Gautam:
> gallium doesn't have a way to pass modifiers to the driver when creating
> resources. we require this to support
> dri2ImageExtension->createImageWithModifiers() to get
> gbm_bo_create_with_modifiers() to work.
> 
> this adds a pscreen->resource_create_with_modifier() to pass the modifier
> flags to the driver when allocating textures, and implements image creation
> with modifiers.
> 
> requires cherry-picking the following patches from the EGL modifiers series:
> https://patchwork.freedesktop.org/patch/155308/
> https://patchwork.freedesktop.org/patch/155309/
> https://patchwork.freedesktop.org/patch/155312/
> 
> complete tree, with the egl series:
> https://git.collabora.com/cgit/user/varad/mesa.git/log/?h=egl-modifiers-v4
> 
> Signed-off-by: Varad Gautam 
> ---
>  src/gallium/include/pipe/p_screen.h   | 13 ++
>  src/gallium/state_trackers/dri/dri2.c | 80 
> ---
>  2 files changed, 77 insertions(+), 16 deletions(-)
> 
> diff --git a/src/gallium/include/pipe/p_screen.h 
> b/src/gallium/include/pipe/p_screen.h
> index 8b4239c..7d248ec 100644
> --- a/src/gallium/include/pipe/p_screen.h
> +++ b/src/gallium/include/pipe/p_screen.h
> @@ -328,6 +328,19 @@ struct pipe_screen {
>  * driver doesn't support an on-disk shader cache.
>  */
> struct disk_cache *(*get_disk_shader_cache)(struct pipe_screen *screen);
> +
> +   /**
> +* Create a new texture object from the given template info, taking
> +* format modifier into account. \p modifier adheres to the format
> +* modifier tokens specified in drm_fourcc.h.
> +*
> +* Returns NULL if the \p modifier is unsupported by the driver.
> +*/
> +   struct pipe_resource * (*resource_create_with_modifier)(
> +   struct pipe_screen *,
> +   const struct pipe_resource *templat,
> +   uint64_t modifier);
> +
>  };
>  
> 
> diff --git a/src/gallium/state_trackers/dri/dri2.c 
> b/src/gallium/state_trackers/dri/dri2.c
> index 42fa155..54ca5fe 100644
> --- a/src/gallium/state_trackers/dri/dri2.c
> +++ b/src/gallium/state_trackers/dri/dri2.c
> @@ -977,9 +977,12 @@ dri2_create_image_from_renderbuffer(__DRIcontext 
> *context,
>  }
>  
>  static __DRIimage *
> -dri2_create_image(__DRIscreen *_screen,
> -   int width, int height, int format,
> -   unsigned int use, void *loaderPrivate)
> +dri2_create_image_common(__DRIscreen *_screen,
> + int width, int height,
> + int format, unsigned int use,
> + const uint64_t *modifiers,
> + const unsigned count,
> + void *loaderPrivate)
>  {
> struct dri_screen *screen = dri_screen(_screen);
> __DRIimage *img;
> @@ -987,17 +990,29 @@ dri2_create_image(__DRIscreen *_screen,
> unsigned tex_usage;
> enum pipe_format pf;
>  
> +   /* createImageWithModifiers does not take a usage flag, the caller can
> +* specify either modifiers or usage.
> +*/
> +   assert(!(use && (modifiers != NULL)));
> +
> +   /* XXX: it is probably a bad idea to assume that all drivers will support
> +* usage = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW with all of
> +* their modifiers. tex_usage must be determined in the driver instead
> +* when modifiers are present.
> +*/

I don't think we can push this to the driver, because what we want is
the driver to select a modifier, that is actually able to be used with a
least RENDER_TARGET. Probably even SCANOUT also. At least the current
use of the new entry point for GBM create_surface implies those 2
usages.

> tex_usage = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW;
> -   if (use & __DRI_IMAGE_USE_SCANOUT)
> -  tex_usage |= PIPE_BIND_SCANOUT;
> -   if (use & __DRI_IMAGE_USE_SHARE)
> -  tex_usage |= PIPE_BIND_SHARED;
> -   if (use & __DRI_IMAGE_USE_LINEAR)
> -  tex_usage |= PIPE_BIND_LINEAR;
> -   if (use & __DRI_IMAGE_USE_CURSOR) {
> -  if (width != 64 || height != 64)
> - return NULL;
> -  tex_usage |= PIPE_BIND_CURSOR;
> +   if (use) {
> +  if (use & __DRI_IMAGE_USE_SCANOUT)
> + tex_usage |= PIPE_BIND_SCANOUT;
> +  if (use & __DRI_IMAGE_USE_SHARE)
> + tex_usage |= PIPE_BIND_SHARED;
> +  if (use & __DRI_IMAGE_USE_LINEAR)
> + tex_usage |= PIPE_BIND_LINEAR;
> +  if (use & __DRI_IMAGE_USE_CURSOR) {
> + if (width != 64 || height != 64)
> +return NULL;
> + tex_usage |= PIPE_BIND_CURSOR;
> +  }
> }
>  
> pf = dri2_format_to_pipe_format (format);
> @@ -1018,7 +1033,18 @@ dri2_create_image(__DRIscreen *_screen,
> templ.depth0 = 1;
> templ.array_size = 1;
>  
> -   img->texture = screen->base.screen->resource_create(screen->base.screen, 
> &templ);
> +   if (modifiers && screen->base.screen->resource_cr

Re: [Mesa-dev] [PATCH v2 3/6] vulkan/wsi/wayland: Use per-display event queue

2017-05-12 Thread Lionel Landwerlin

On 05/05/17 17:47, Daniel Stone wrote:

Calling random callbacks on the display's event queue is hostile, as
we may call into client code when it least expects it. Create our own
event queue, one per wsi_wl_display, and use that for the registry.

Signed-off-by: Daniel Stone 
Cc: mesa-sta...@lists.freedesktop.org
---
  src/vulkan/wsi/wsi_common_wayland.c | 44 +++--
  1 file changed, 32 insertions(+), 12 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common_wayland.c 
b/src/vulkan/wsi/wsi_common_wayland.c
index 014ea13d65..c67ba089f9 100644
--- a/src/vulkan/wsi/wsi_common_wayland.c
+++ b/src/vulkan/wsi/wsi_common_wayland.c
@@ -45,7 +45,11 @@
  struct wsi_wayland;
  
  struct wsi_wl_display {

-   struct wl_display *  display;
+   /* The real wl_display */
+   struct wl_display *  wl_display;
+   /* Actually a proxy wrapper around the event queue */
+   struct wl_display *  wl_display_wrapper;
+   struct wl_event_queue *  queue;
 struct wl_drm *  drm;
  
 struct wsi_wayland *wsi_wl;

@@ -250,6 +254,10 @@ wsi_wl_display_destroy(struct wsi_wayland *wsi, struct 
wsi_wl_display *display)
 u_vector_finish(&display->formats);
 if (display->drm)
wl_drm_destroy(display->drm);
+   if (display->wl_display_wrapper)
+  wl_proxy_wrapper_destroy(display->wl_display_wrapper);
+   if (display->queue)
+  wl_event_queue_destroy(display->queue);
 vk_free(wsi->alloc, display);
  }
  
@@ -264,26 +272,38 @@ wsi_wl_display_create(struct wsi_wayland *wsi, struct wl_display *wl_display)
  
 memset(display, 0, sizeof(*display));
  
-   display->display = wl_display;

 display->wsi_wl = wsi;
+   display->wl_display = wl_display;
  
 if (!u_vector_init(&display->formats, sizeof(VkFormat), 8))

goto fail;
  
-   struct wl_registry *registry = wl_display_get_registry(wl_display);

+   display->queue = wl_display_create_queue(wl_display);
+   if (!display->queue)
+  goto fail;
+
+   display->wl_display_wrapper = wl_proxy_create_wrapper(wl_display);
+   if (!display->wl_display_wrapper)
+  goto fail;
+
+   wl_proxy_set_queue((struct wl_proxy *) display->wl_display_wrapper,
+  display->queue);
+
+   struct wl_registry *registry =
+  wl_display_get_registry(display->wl_display_wrapper);
 if (!registry)
goto fail;
  
 wl_registry_add_listener(registry, ®istry_listener, display);
  
-   /* Round-rip to get the wl_drm global */

-   wl_display_roundtrip(wl_display);
+   /* Round-trip to get the wl_drm global */
+   wl_display_roundtrip_queue(display->wl_display, display->queue);
  
 if (!display->drm)

goto fail_registry;
  
-   /* Round-rip to get wl_drm formats and capabilities */

-   wl_display_roundtrip(wl_display);
+   /* Round-trip to get wl_drm formats and capabilities */
+   wl_display_roundtrip_queue(display->wl_display, display->queue);
  
 /* We need prime support */

 if (!(display->capabilities & WL_DRM_CAPABILITY_PRIME))
@@ -535,7 +555,7 @@ wsi_wl_swapchain_acquire_next_image(struct wsi_swapchain 
*wsi_chain,
  {
 struct wsi_wl_swapchain *chain = (struct wsi_wl_swapchain *)wsi_chain;
  
-   int ret = wl_display_dispatch_queue_pending(chain->display->display,

+   int ret = wl_display_dispatch_queue_pending(chain->display->wl_display,
 chain->queue);


I'm not a wayland expert, so this might be a dumb question.
Why do you keep using chain->queue instead of chain->display->queue in a 
few places?



 /* XXX: I'm not sure if out-of-date is the right error here.  If
  * wl_display_dispatch_queue_pending fails it most likely means we got
@@ -557,7 +577,7 @@ wsi_wl_swapchain_acquire_next_image(struct wsi_swapchain 
*wsi_chain,
/* This time we do a blocking dispatch because we can't go
 * anywhere until we get an event.
 */
-  int ret = wl_display_roundtrip_queue(chain->display->display,
+  int ret = wl_display_roundtrip_queue(chain->display->wl_display,
 chain->queue);
if (ret < 0)
   return VK_ERROR_OUT_OF_DATE_KHR;
@@ -587,7 +607,7 @@ wsi_wl_swapchain_queue_present(struct wsi_swapchain 
*wsi_chain,
  
 if (chain->base.present_mode == VK_PRESENT_MODE_FIFO_KHR) {

while (!chain->fifo_ready) {
- int ret = wl_display_dispatch_queue(chain->display->display,
+ int ret = wl_display_dispatch_queue(chain->display->wl_display,
   chain->queue);
   if (ret < 0)
  return VK_ERROR_OUT_OF_DATE_KHR;
@@ -619,7 +639,7 @@ wsi_wl_swapchain_queue_present(struct wsi_swapchain 
*wsi_chain,
  
 chain->images[image_index].busy = true;

 wl_surface_commit(chain->surface);
-   wl_display_flush(chain->display->display);
+   wl_display_flush(c

[Mesa-dev] [RFC] st/dri: implement createImageWithModifiers

2017-05-12 Thread Varad Gautam
gallium doesn't have a way to pass modifiers to the driver when creating
resources. we require this to support
dri2ImageExtension->createImageWithModifiers() to get
gbm_bo_create_with_modifiers() to work.

this adds a pscreen->resource_create_with_modifier() to pass the modifier
flags to the driver when allocating textures, and implements image creation
with modifiers.

requires cherry-picking the following patches from the EGL modifiers series:
https://patchwork.freedesktop.org/patch/155308/
https://patchwork.freedesktop.org/patch/155309/
https://patchwork.freedesktop.org/patch/155312/

complete tree, with the egl series:
https://git.collabora.com/cgit/user/varad/mesa.git/log/?h=egl-modifiers-v4

Signed-off-by: Varad Gautam 
---
 src/gallium/include/pipe/p_screen.h   | 13 ++
 src/gallium/state_trackers/dri/dri2.c | 80 ---
 2 files changed, 77 insertions(+), 16 deletions(-)

diff --git a/src/gallium/include/pipe/p_screen.h 
b/src/gallium/include/pipe/p_screen.h
index 8b4239c..7d248ec 100644
--- a/src/gallium/include/pipe/p_screen.h
+++ b/src/gallium/include/pipe/p_screen.h
@@ -328,6 +328,19 @@ struct pipe_screen {
 * driver doesn't support an on-disk shader cache.
 */
struct disk_cache *(*get_disk_shader_cache)(struct pipe_screen *screen);
+
+   /**
+* Create a new texture object from the given template info, taking
+* format modifier into account. \p modifier adheres to the format
+* modifier tokens specified in drm_fourcc.h.
+*
+* Returns NULL if the \p modifier is unsupported by the driver.
+*/
+   struct pipe_resource * (*resource_create_with_modifier)(
+   struct pipe_screen *,
+   const struct pipe_resource *templat,
+   uint64_t modifier);
+
 };
 
 
diff --git a/src/gallium/state_trackers/dri/dri2.c 
b/src/gallium/state_trackers/dri/dri2.c
index 42fa155..54ca5fe 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -977,9 +977,12 @@ dri2_create_image_from_renderbuffer(__DRIcontext *context,
 }
 
 static __DRIimage *
-dri2_create_image(__DRIscreen *_screen,
-   int width, int height, int format,
-   unsigned int use, void *loaderPrivate)
+dri2_create_image_common(__DRIscreen *_screen,
+ int width, int height,
+ int format, unsigned int use,
+ const uint64_t *modifiers,
+ const unsigned count,
+ void *loaderPrivate)
 {
struct dri_screen *screen = dri_screen(_screen);
__DRIimage *img;
@@ -987,17 +990,29 @@ dri2_create_image(__DRIscreen *_screen,
unsigned tex_usage;
enum pipe_format pf;
 
+   /* createImageWithModifiers does not take a usage flag, the caller can
+* specify either modifiers or usage.
+*/
+   assert(!(use && (modifiers != NULL)));
+
+   /* XXX: it is probably a bad idea to assume that all drivers will support
+* usage = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW with all of
+* their modifiers. tex_usage must be determined in the driver instead
+* when modifiers are present.
+*/
tex_usage = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW;
-   if (use & __DRI_IMAGE_USE_SCANOUT)
-  tex_usage |= PIPE_BIND_SCANOUT;
-   if (use & __DRI_IMAGE_USE_SHARE)
-  tex_usage |= PIPE_BIND_SHARED;
-   if (use & __DRI_IMAGE_USE_LINEAR)
-  tex_usage |= PIPE_BIND_LINEAR;
-   if (use & __DRI_IMAGE_USE_CURSOR) {
-  if (width != 64 || height != 64)
- return NULL;
-  tex_usage |= PIPE_BIND_CURSOR;
+   if (use) {
+  if (use & __DRI_IMAGE_USE_SCANOUT)
+ tex_usage |= PIPE_BIND_SCANOUT;
+  if (use & __DRI_IMAGE_USE_SHARE)
+ tex_usage |= PIPE_BIND_SHARED;
+  if (use & __DRI_IMAGE_USE_LINEAR)
+ tex_usage |= PIPE_BIND_LINEAR;
+  if (use & __DRI_IMAGE_USE_CURSOR) {
+ if (width != 64 || height != 64)
+return NULL;
+ tex_usage |= PIPE_BIND_CURSOR;
+  }
}
 
pf = dri2_format_to_pipe_format (format);
@@ -1018,7 +1033,18 @@ dri2_create_image(__DRIscreen *_screen,
templ.depth0 = 1;
templ.array_size = 1;
 
-   img->texture = screen->base.screen->resource_create(screen->base.screen, 
&templ);
+   if (modifiers && screen->base.screen->resource_create_with_modifier)
+  /* pick the first modifier for alloc. */
+  img->texture = screen->base.screen
+->resource_create_with_modifier(screen->base.screen,
+&templ,
+modifiers[0]);
+   else if (modifiers)
+  /* the driver doesn't support tex creation with modifiers, return */
+  img->texture = NULL;
+   else
+  img->texture = screen->base.screen->resource_create(screen->base.screen,
+

Re: [Mesa-dev] [PATCH] nv50/ir: Report wrong prog types using proper var

2017-05-12 Thread Samuel Pitoiset

Reviewed-by: Samuel Pitoiset 

On 05/12/2017 11:01 AM, Pierre Moreau wrote:

Coverity caught the use of the uninitialised variable `type`.
However, it was `info->type`, which is initialised, which was meant to
be used.

CID: 1406000
Reported-by: Ilia Mirkin 
Fixes: b490ca9a387d ("nv50/ir: Fail if encountering unknown shader type")
Signed-off-by: Pierre Moreau 
---
  src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
index a000bcbd32..21641a4746 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
@@ -1214,7 +1214,7 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info)
 PROG_TYPE_CASE(FRAGMENT, FRAGMENT);
 PROG_TYPE_CASE(COMPUTE, COMPUTE);
 default:
-  INFO_DBG(info->dbgFlags, VERBOSE, "unsupported program type %u\n", type);
+  INFO_DBG(info->dbgFlags, VERBOSE, "unsupported program type %u\n", 
info->type);
return -1;
 }
 INFO_DBG(info->dbgFlags, VERBOSE, "translating program of type %u\n", 
type);


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[Mesa-dev] [PATCH] nv50/ir: Report wrong prog types using proper var

2017-05-12 Thread Pierre Moreau
Coverity caught the use of the uninitialised variable `type`.
However, it was `info->type`, which is initialised, which was meant to
be used.

CID: 1406000
Reported-by: Ilia Mirkin 
Fixes: b490ca9a387d ("nv50/ir: Fail if encountering unknown shader type")
Signed-off-by: Pierre Moreau 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
index a000bcbd32..21641a4746 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
@@ -1214,7 +1214,7 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info)
PROG_TYPE_CASE(FRAGMENT, FRAGMENT);
PROG_TYPE_CASE(COMPUTE, COMPUTE);
default:
-  INFO_DBG(info->dbgFlags, VERBOSE, "unsupported program type %u\n", type);
+  INFO_DBG(info->dbgFlags, VERBOSE, "unsupported program type %u\n", 
info->type);
   return -1;
}
INFO_DBG(info->dbgFlags, VERBOSE, "translating program of type %u\n", type);
-- 
2.13.0

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Re: [Mesa-dev] [PATCH 00/13] Threaded Gallium for RadeonSI

2017-05-12 Thread Nicolai Hähnle

On 11.05.2017 23:01, Marek Olšák wrote:

On Thu, May 11, 2017 at 9:02 PM, Nicolai Hähnle  >
Some general remarks:


Violating the "async" promise on debug callbacks is a problem. This breaks
the OpenGL API in a place where it wasn't broken before, and that's not
okay. I'm not sure what to do about this precisely, but the spec is very
explicit:

   "When DEBUG_OUTPUT_SYNCHRONOUS is enabled, the driver guarantees
synchronous calls to the callback routine by the context. When
synchronous callbacks are enabled, all calls to the callback
routine will be made by the thread that owns the current context;
all such calls will be made serially by the current context; and
each call will be made before the GL command that generated the
debug message is allowed to return."

The last part is the strictest and implies that sync-ing becomes mandatory.

Maybe this can be handled without a performance impact by swapping out
pipe_context function pointers when the debug callback changes to !async.


We can probably just drop !async set_debug_callback calls and handle
shader-db as a special case, e.g. set GALLIUM_THREAD=0 in
shader-db/run.


Yes, that works as well.

Cheers,
Nicolai



Marek




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Re: [Mesa-dev] [PATCH 09/13] gallium/radeon: subclass threaded_transfer

2017-05-12 Thread Nicolai Hähnle

Reviewed-by: Nicolai Hähnle 

On 12.05.2017 01:53, Marek Olšák wrote:

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_buffer_common.c | 22 ++---
 src/gallium/drivers/radeon/r600_pipe_common.h   |  2 +-
 src/gallium/drivers/radeon/r600_texture.c   | 26 -
 3 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index b57632e..8ded99e 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -293,30 +293,31 @@ static void *r600_buffer_get_transfer(struct pipe_context 
*ctx,
  unsigned offset)
 {
struct r600_common_context *rctx = (struct r600_common_context*)ctx;
struct r600_transfer *transfer;

if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
transfer = slab_alloc(&rctx->pool_transfers_unsync);
else
transfer = slab_alloc(&rctx->pool_transfers);

-   transfer->transfer.resource = NULL;
-   pipe_resource_reference(&transfer->transfer.resource, resource);
-   transfer->transfer.level = 0;
-   transfer->transfer.usage = usage;
-   transfer->transfer.box = *box;
-   transfer->transfer.stride = 0;
-   transfer->transfer.layer_stride = 0;
+   transfer->b.b.resource = NULL;
+   pipe_resource_reference(&transfer->b.b.resource, resource);
+   transfer->b.b.level = 0;
+   transfer->b.b.usage = usage;
+   transfer->b.b.box = *box;
+   transfer->b.b.stride = 0;
+   transfer->b.b.layer_stride = 0;
+   transfer->b.staging = NULL;
transfer->offset = offset;
transfer->staging = staging;
-   *ptransfer = &transfer->transfer;
+   *ptransfer = &transfer->b.b;
return data;
 }

 static bool r600_can_dma_copy_buffer(struct r600_common_context *rctx,
 unsigned dstx, unsigned srcx, unsigned 
size)
 {
bool dword_aligned = !(dstx % 4) && !(srcx % 4) && !(size % 4);

return rctx->screen->has_cp_dma ||
   (dword_aligned && (rctx->dma.cs ||
@@ -505,23 +506,22 @@ static void r600_buffer_flush_region(struct pipe_context 
*ctx,
 static void r600_buffer_transfer_unmap(struct pipe_context *ctx,
   struct pipe_transfer *transfer)
 {
struct r600_common_context *rctx = (struct r600_common_context*)ctx;
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;

if (transfer->usage & PIPE_TRANSFER_WRITE &&
!(transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
r600_buffer_do_flush_region(ctx, transfer, &transfer->box);

-   if (rtransfer->staging)
-   r600_resource_reference(&rtransfer->staging, NULL);
-
+   r600_resource_reference(&rtransfer->staging, NULL);
+   assert(rtransfer->b.staging == NULL); /* for threaded context only */
pipe_resource_reference(&transfer->resource, NULL);

/* Don't use pool_transfers_unsync. We are always in the driver
 * thread. */
slab_free(&rctx->pool_transfers, transfer);
 }

 void r600_buffer_subdata(struct pipe_context *ctx,
 struct pipe_resource *buffer,
 unsigned usage, unsigned offset,
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 3449786..a694b97 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -177,21 +177,21 @@ struct r600_resource {
 * an index buffer. The reason is that VGT DMA index fetching doesn't
 * use TC L2.
 */
boolTC_L2_dirty;

/* Whether the resource has been exported via resource_get_handle. */
unsignedexternal_usage; /* PIPE_HANDLE_USAGE_* 
*/
 };

 struct r600_transfer {
-   struct pipe_transfertransfer;
+   struct threaded_transferb;
struct r600_resource*staging;
unsignedoffset;
 };

 struct r600_fmask_info {
uint64_t offset;
uint64_t size;
unsigned alignment;
unsigned pitch_in_pixels;
unsigned bank_height;
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 3bcf966..4d72b86 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1641,24 +1641,24 @@ static void *r600_texture_transfer_map(struct 
pipe_context *ctx,
usage, box))
r600_texture_invalidate_storage(rctx, rtex);
else
use_staging_texture = true;
}
}

tran

Re: [Mesa-dev] [PATCH 3/6] mesa: Clamp GetUniformui64v values to be >= 0

2017-05-12 Thread Nicolai Hähnle

On 11.05.2017 13:10, Iago Toral Quiroga wrote:

Like we do for the 32-bit case.
---
 src/mesa/main/uniform_query.cpp | 45 -
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 315973a..42abd18 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -549,7 +549,6 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
break;

 case GLSL_TYPE_INT64:
-case GLSL_TYPE_UINT64:
switch (uni->type->base_type) {
case GLSL_TYPE_UINT: {
   uint64_t tmp = src[sidx].u;
@@ -568,6 +567,13 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
   memcpy(&dst[didx].u, &tmp, sizeof(tmp));
   break;
}
+   case GLSL_TYPE_UINT64: {
+  uint64_t u64;
+  memcpy(&u64, &src[sidx].u, sizeof(u64));
+  int64_t tmp = MIN2(u64, INT_MAX);
+  memcpy(&dst[didx].u, &tmp, sizeof(tmp));
+  break;
+   }
case GLSL_TYPE_FLOAT: {
   int64_t tmp = src[sidx].f;
   memcpy(&dst[didx].u, &tmp, sizeof(tmp));
@@ -579,6 +585,43 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
}
break;

+case GLSL_TYPE_UINT64:
+   switch (uni->type->base_type) {
+   case GLSL_TYPE_UINT: {
+  uint64_t tmp = src[sidx].u;
+  memcpy(&dst[didx].u, &tmp, sizeof(tmp));
+  break;
+   }
+   case GLSL_TYPE_INT:
+   case GLSL_TYPE_SAMPLER:
+   case GLSL_TYPE_IMAGE: {
+  int64_t tmp = MAX2(src[sidx].i, 0);
+  memcpy(&dst[didx].u, &tmp, sizeof(tmp));
+  break;
+   }
+   case GLSL_TYPE_BOOL: {
+  int64_t tmp = src[sidx].i ? 1.0f : 0.0f;
+  memcpy(&dst[didx].u, &tmp, sizeof(tmp));
+  break;
+   }
+   case GLSL_TYPE_INT64: {
+  uint64_t i64;
+  memcpy(&i64, &src[sidx].i, sizeof(i64));
+  uint64_t tmp = MAX2(i64, 0);
+  memcpy(&dst[didx].u, &tmp, sizeof(tmp));
+  break;
+   }
+   case GLSL_TYPE_FLOAT: {
+  int64_t tmp = src[sidx].f < 0.0f ? 0 : IROUND64(src[sidx].f);


Unsigned rounding.

Cheers,
Nicolai



+  memcpy(&dst[didx].u, &tmp, sizeof(tmp));
+  break;
+   }
+   default:
+  assert(!"Should not get here.");
+  break;
+   }
+   break;
+
 default:
assert(!"Should not get here.");
break;




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Re: [Mesa-dev] [PATCH 0/6] Various fixes to integer GetUniform*()

2017-05-12 Thread Nicolai Hähnle

On 11.05.2017 13:10, Iago Toral Quiroga wrote:

This series is an update on a previous patch by Ken that fixed
a CTS test but never got merged due to the mess with the CTS repositories
at that time, plus a number of additional fixes for recently added int64 paths.

Patch 1 fixes indentation.
Patch 2 is the original patch by Ken, only tha rebased and amended to support
conversions from 64-bit integer types.
Patch 3 is the same as patch 2, but for 64-bit integer.
Patches 4-6 are two fixes for 64-bit integer conversion paths.

Ken: the release tarball in the khronos page still links to the old test suite
from 2016, however, it seems that it should be possible to send submissions from
the new repository as well (see [1]).


Certainly not from VK-GL-CTS, unfortunately, since it's missing the GTF 
parts of the tests, and kc-cts hasn't been approved yet, either. On the 
other hand, it should be possible to provide a submission package where 
the change to the uniform test is backported, so patches 2 & 3 (modulo 
comments) are probably fine.


Cheers,
Nicolai



I think we only want to commit patches
2-3 if we intend to use the new repository for any future submissions and maybe
we are not ready to make that decision yet. In that case we can skip patches 2-3
for now, at least we would habe them updated in the list for future reference,
however, I think we want to land the other patche ( although they would need a
minor update to avoid any uint clamping in case that we decide against landing
patches 2-3; I could re-send the series with only those patches in that case).

[1] 
https://github.com/KhronosGroup/VK-GL-CTS/wiki/Creating-a-OpenGL-and-OpenGL-ES-Submission-Package

Iago Toral Quiroga (5):
  mesa/main: fix indentation in _mesa_get_uniform()
  mesa: Clamp GetUniformui64v values to be >= 0
  mesa/main: add IROUNDD64() helper
  mesa: Add conversion from double to uint64/int64 in GetUniform*i64v()
  mesa: conversion from float in GetUniformi64v require rounding to
nearest

Kenneth Graunke (1):
  mesa: Clamp GetUniformuiv values to be >= 0

 src/mesa/main/imports.h |   7 +
 src/mesa/main/uniform_query.cpp | 299 ++--
 2 files changed, 206 insertions(+), 100 deletions(-)




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Re: [Mesa-dev] [PATCH 2/6] mesa: Clamp GetUniformuiv values to be >= 0

2017-05-12 Thread Nicolai Hähnle

On 11.05.2017 13:10, Iago Toral Quiroga wrote:

From: Kenneth Graunke 

Section 2.2.2 (Data Conversions For State Query Commands) of the
OpenGL 4.5 October 24th 2016 specification says:

"If a command returning unsigned integer data is called, such as
 GetSamplerParameterIuiv, negative values are clamped to zero."

v2: uint to int conversion should clamp to INT_MAX (Nicolai)

v3 (Iago)
  - Add conversions conversions from 64-bit integer paths
  - Rebase on master

Fixes:
KHR-GL45.gpu_shader_fp64.state_query

Reviewed-by: Nicolai Hähnle  (v2)
---
 src/mesa/main/uniform_query.cpp | 64 -
 1 file changed, 51 insertions(+), 13 deletions(-)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index bd5b4c4..315973a 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -352,18 +352,9 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
* just memcpy the data.  If the types are not compatible, perform a
* slower convert-and-copy process.
*/
-  if (returnType == uni->type->base_type
-  || ((returnType == GLSL_TYPE_INT
-   || returnType == GLSL_TYPE_UINT)
-  &&
-  (uni->type->base_type == GLSL_TYPE_INT
-   || uni->type->base_type == GLSL_TYPE_UINT
-   || uni->type->is_sampler()
-   || uni->type->is_image()))
-   || ((returnType == GLSL_TYPE_UINT64 ||
-returnType == GLSL_TYPE_INT64) &&
-  (uni->type->base_type == GLSL_TYPE_UINT64 ||
-   uni->type->base_type == GLSL_TYPE_INT64))) {
+  if (returnType == uni->type->base_type ||
+  ((returnType == GLSL_TYPE_INT || returnType == GLSL_TYPE_UINT) &&
+   (uni->type->is_sampler() || uni->type->is_image( {
  memcpy(paramsOut, src, bytes);
   } else {
  union gl_constant_value *const dst =
@@ -461,7 +452,6 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
break;

 case GLSL_TYPE_INT:
-case GLSL_TYPE_UINT:
switch (uni->type->base_type) {
case GLSL_TYPE_FLOAT:
   /* While the GL 3.2 core spec doesn't explicitly
@@ -486,6 +476,9 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
case GLSL_TYPE_BOOL:
   dst[didx].i = src[sidx].i ? 1 : 0;
   break;
+   case GLSL_TYPE_UINT:
+  dst[didx].i = MIN2(src[sidx].i, INT_MAX);
+  break;
case GLSL_TYPE_DOUBLE: {
   double tmp;
   memcpy(&tmp, &src[sidx].f, sizeof(tmp));
@@ -510,6 +503,51 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
}
break;

+case GLSL_TYPE_UINT:
+   switch (uni->type->base_type) {
+   case GLSL_TYPE_FLOAT:
+  /* The spec isn't terribly clear how to handle negative
+   * values with an unsigned return type.
+   *
+   * GL 4.5 section 2.2.2 ("Data Conversions for State
+   * Query Commands") says:
+   *
+   * "If a value is so large in magnitude that it cannot be
+   *  represented by the returned data type, then the nearest
+   *  value representable using the requested type is
+   *  returned."
+   */
+  dst[didx].i = src[sidx].f < 0.0f ? 0 : IROUND(src[sidx].f);


This needs an unsigned rounding function, doesn't it?



+  break;
+   case GLSL_TYPE_BOOL:
+  dst[didx].i = src[sidx].i ? 1 : 0;
+  break;
+   case GLSL_TYPE_INT:
+  dst[didx].i = MAX2(src[sidx].i, 0);
+  break;
+   case GLSL_TYPE_DOUBLE: {
+  double tmp;
+  memcpy(&tmp, &src[sidx].f, sizeof(tmp));
+  dst[didx].i = tmp < 0.0 ? 0 : IROUNDD(tmp);
+  break;


Also, unsigned rounding.

Cheers,
Nicolai


+   }
+   case GLSL_TYPE_UINT64: {
+  uint64_t tmp;
+  memcpy(&tmp, &src[sidx].u, sizeof(tmp));
+  dst[didx].i = MIN2(tmp, INT_MAX);
+  break;
+   }
+   case GLSL_TYPE_INT64: {
+  int64_t tmp;
+  memcpy(&tmp, &src[sidx].i, sizeof(tmp));
+  dst[didx].i = MAX2(tmp, 0);
+  break;
+   }
+   default:
+  unreachable("invalid uniform type");
+   }
+   break;
+
 case GLSL_TYPE_INT64:
 case GLSL_TYPE_UINT64:
switch (uni->type->

Re: [Mesa-dev] [PATCH 5/6] mesa: Add conversion from double to uint64/int64 in GetUniform*i64v()

2017-05-12 Thread Nicolai Hähnle

On 11.05.2017 13:10, Iago Toral Quiroga wrote:

---
 src/mesa/main/uniform_query.cpp | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 42abd18..25acc31 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -579,6 +579,13 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
   memcpy(&dst[didx].u, &tmp, sizeof(tmp));
   break;
}
+   case GLSL_TYPE_DOUBLE: {
+  double d;
+  memcpy(&d, &src[sidx].f, sizeof(d));
+  int64_t tmp = IROUNDD64(d);
+  memcpy(&dst[didx].u, &tmp, sizeof(tmp));
+  break;
+   }
default:
   assert(!"Should not get here.");
   break;
@@ -616,6 +623,13 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
   memcpy(&dst[didx].u, &tmp, sizeof(tmp));
   break;
}
+   case GLSL_TYPE_DOUBLE: {
+  double d;
+  memcpy(&d, &src[sidx].f, sizeof(d));
+  uint64_t tmp = (d < 0.0) ? 0 : IROUNDD64(d);


This needs to use an unsigned rounding function, doesn't it?

Cheers,
Nicolai



+  memcpy(&dst[didx].u, &tmp, sizeof(tmp));
+  break;
+   }
default:
   assert(!"Should not get here.");
   break;




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[Mesa-dev] [PATCH v2] bin/get-fixes-pick-list.sh: bring back the warning

2017-05-12 Thread Andres Gomez
We warn again if there is more than one line with the "fixes:" tag.

The warning is only silenced when the commit has landed already or we
output another message for every "fixes:" tag.

Signed-off-by: Andres Gomez 
---
 bin/get-fixes-pick-list.sh | 19 +--
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/bin/get-fixes-pick-list.sh b/bin/get-fixes-pick-list.sh
index cf95f28377..3ea649a0a4 100755
--- a/bin/get-fixes-pick-list.sh
+++ b/bin/get-fixes-pick-list.sh
@@ -33,7 +33,14 @@ do
 
# For each one try to extract the tag
fixes_count=`git show $sha | grep -i "fixes:" | wc -l`
+   warn=`(test $fixes_count -gt 1 && echo $fixes_count) || echo 0`
while [ $fixes_count -gt 0 ] ; do
+   # Skip if it has been already landed.
+   if grep -q ^$sha already_picked ; then
+   warn=0
+   break
+   fi
+
fixes=`git show $sha | grep -i "fixes:" | tail -n $fixes_count 
| head -n 1`
fixes_count=$(($fixes_count-1))
# The following sed/cut combination is borrowed from GregKH
@@ -53,19 +60,19 @@ do
if grep -q ^$id already_picked ||
   grep -q ^$id already_landed ; then
 
-   # Finally nominate the fix if it hasn't landed yet.
-   if grep -q ^$sha already_picked ; then
-   continue
-   fi
-
printf "Commit \"%s\" fixes %s\n" \
   "`git log -n1 --pretty=oneline $sha`" \
   "$id"
-   fixes_count=0
+   warn=$(($warn-1))
fi
 
done
 
+   if [ $warn -gt 0 ] ; then
+   printf "WARNING: Commit \"%s\" has more than one Fixes tag\n" \
+  "`git log -n1 --pretty=oneline $sha`"
+   fi
+
 done
 
 rm -f already_picked
-- 
2.11.0

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Re: [Mesa-dev] [PATCH 4/6] mesa/main: add IROUNDD64() helper

2017-05-12 Thread Nicolai Hähnle

On 11.05.2017 13:10, Iago Toral Quiroga wrote:

---
 src/mesa/main/imports.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/mesa/main/imports.h b/src/mesa/main/imports.h
index ef7c378..416c59b 100644
--- a/src/mesa/main/imports.h
+++ b/src/mesa/main/imports.h
@@ -165,6 +165,13 @@ static inline GLint64 IROUND64(float f)
return (GLint64) ((f >= 0.0F) ? (f + 0.5F) : (f - 0.5F));
 }

+/**
+ * Convert double to int64 by rounding to nearest integer.
+ */
+static inline GLint64 IROUNDD64(double d)
+{
+   return (GLint64) ((d >= 0.0) ? (d + 0.5) : (d - 0.5));
+}


Out of curiosity, can't you use round()? But I see that this matches 
other code, so it's fine.


Cheers,
Nicolai




 /**
  * Convert positive float to int by rounding to nearest integer.




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Re: [Mesa-dev] [PATCH 1/6] mesa/main: fix indentation in _mesa_get_uniform()

2017-05-12 Thread Nicolai Hähnle

On 11.05.2017 13:10, Iago Toral Quiroga wrote:

---
 src/mesa/main/uniform_query.cpp | 194 
 1 file changed, 99 insertions(+), 95 deletions(-)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 0e02a76..bd5b4c4 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -333,7 +333,7 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
* account for the size of the user's buffer.
*/
   const union gl_constant_value *const src =
-&uni->storage[offset * elements * dmul];
+ &uni->storage[offset * elements * dmul];

   assert(returnType == GLSL_TYPE_FLOAT || returnType == GLSL_TYPE_INT ||
  returnType == GLSL_TYPE_UINT || returnType == GLSL_TYPE_DOUBLE ||
@@ -342,10 +342,10 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
   /* doubles have a different size than the other 3 types */
   unsigned bytes = sizeof(src[0]) * elements * rmul;
   if (bufSize < 0 || bytes > (unsigned) bufSize) {
-_mesa_error( ctx, GL_INVALID_OPERATION,
-"glGetnUniform*vARB(out of bounds: bufSize is %d,"
-" but %u bytes are required)", bufSize, bytes );
-return;
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "glGetnUniform*vARB(out of bounds: bufSize is %d,"
+ " but %u bytes are required)", bufSize, bytes);
+ return;
   }

   /* If the return type and the uniform's native type are "compatible,"
@@ -353,89 +353,90 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
* slower convert-and-copy process.
*/
   if (returnType == uni->type->base_type
- || ((returnType == GLSL_TYPE_INT
-  || returnType == GLSL_TYPE_UINT)
- &&
- (uni->type->base_type == GLSL_TYPE_INT
-  || uni->type->base_type == GLSL_TYPE_UINT
+  || ((returnType == GLSL_TYPE_INT
+   || returnType == GLSL_TYPE_UINT)
+  &&
+  (uni->type->base_type == GLSL_TYPE_INT
+   || uni->type->base_type == GLSL_TYPE_UINT
|| uni->type->is_sampler()
|| uni->type->is_image()))
-  || ((returnType == GLSL_TYPE_UINT64 ||
-   returnType == GLSL_TYPE_INT64 ) &&
-  (uni->type->base_type == GLSL_TYPE_UINT64 ||
-   uni->type->base_type == GLSL_TYPE_INT64))) {


While we're fixing indentation, could we perhaps change the style in 
general to putting the "dangling" operator at the end of the line, as is 
done in other parts of the code? I.e. like so:


  if (returnType == uni->type->base_type ||
  ((returnType == GLSL_TYPE_INT ||
returnType == GLSL_TYPE_UINT) &&
   (uni->type->base_type == GLSL_TYPE_INT ||
uni->type->base_type == GLSL_TYPE_UINT ||
uni->type->is_sampler() ||
uni->type->is_image())) ||
  ((returnType == GLSL_TYPE_UINT64 ||
returnType == GLSL_TYPE_INT64 ) &&
   (uni->type->base_type == GLSL_TYPE_UINT64 ||
uni->type->base_type == GLSL_TYPE_INT64))) {

At least, that's color of bikeshed I prefer...

Cheers,
Nicolai



-memcpy(paramsOut, src, bytes);
+   || ((returnType == GLSL_TYPE_UINT64 ||
+returnType == GLSL_TYPE_INT64) &&
+  (uni->type->base_type == GLSL_TYPE_UINT64 ||
+   uni->type->base_type == GLSL_TYPE_INT64))) {
+ memcpy(paramsOut, src, bytes);
   } else {
-union gl_constant_value *const dst =
-   (union gl_constant_value *) paramsOut;
-/* This code could be optimized by putting the loop inside the switch
- * statements.  However, this is not expected to be
- * performance-critical code.
- */
-for (unsigned i = 0; i < elements; i++) {
-  int sidx = i * dmul;
-  int didx = i * rmul;
-
-   switch (returnType) {
-   case GLSL_TYPE_FLOAT:
-  switch (uni->type->base_type) {
-  case GLSL_TYPE_UINT:
- dst[didx].f = (float) src[sidx].u;
- break;
-  case GLSL_TYPE_INT:
-  case GLSL_TYPE_SAMPLER:
+ union gl_constant_value *const dst =
+(union gl_constant_value *) paramsOut;
+ /* This code could be optimized by putting the loop inside the switch
+  * statements.  However, this is not expected to be
+  * performance-critical code.
+  */
+ for (unsigned i = 0; i < elements; i++) {
+int sidx = i * dmul;
+int didx = i * rmul;
+
+switch (returnType) {
+case GLSL_TYPE_FLOAT:
+   switch (uni->type->base_type) {
+   case GLSL_TYPE_UINT:
+  dst[di

Re: [Mesa-dev] [PATCH 10/13] egl/x11: make use of the dri2_display_destroy() helper

2017-05-12 Thread Tapani Pälli

this patch causes a crash with egl-create-surface Piglit test

On 05/11/2017 09:57 PM, Emil Velikov wrote:

From: Emil Velikov 

Signed-off-by: Emil Velikov 
---
  src/egl/drivers/dri2/platform_x11.c | 78 +++--
  1 file changed, 23 insertions(+), 55 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index 3bce0bb3f21..c512448952d 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -1235,25 +1235,25 @@ dri2_initialize_x11_swrast(_EGLDriver *drv, _EGLDisplay 
*disp)
 if (!dri2_dpy)
return _eglError(EGL_BAD_ALLOC, "eglInitialize");
  
+   dri2_dpy->fd = -1;

 if (!dri2_get_xcb_connection(drv, disp, dri2_dpy))
-  goto cleanup_dpy;
+  goto cleanup;
  
 /*

  * Every hardware driver_name is set using strdup. Doing the same in
  * here will allow is to simply free the memory at dri2_terminate().
  */
-   dri2_dpy->fd = -1;
 dri2_dpy->driver_name = strdup("swrast");
 if (!dri2_load_driver_swrast(disp))
-  goto cleanup_conn;
+  goto cleanup;
  
 dri2_dpy->loader_extensions = swrast_loader_extensions;
  
 if (!dri2_create_screen(disp))

-  goto cleanup_driver;
+  goto cleanup;
  
 if (!dri2_x11_add_configs_for_visuals(dri2_dpy, disp, true))

-  goto cleanup_configs;
+  goto cleanup;
  
 /* Fill vtbl last to prevent accidentally calling virtual function during

  * initialization.
@@ -1262,19 +1262,8 @@ dri2_initialize_x11_swrast(_EGLDriver *drv, _EGLDisplay 
*disp)
  
 return EGL_TRUE;
  
- cleanup_configs:

-   _eglCleanupDisplay(disp);
-   dri2_dpy->core->destroyScreen(dri2_dpy->dri_screen);
- cleanup_driver:
-   dlclose(dri2_dpy->driver);
- cleanup_conn:
-   free(dri2_dpy->driver_name);
-   if (disp->PlatformDisplay == NULL)
-  xcb_disconnect(dri2_dpy->conn);
- cleanup_dpy:
-   free(dri2_dpy);
-   disp->DriverData = NULL;
-
+ cleanup:
+   dri2_display_destroy(disp);
 return EGL_FALSE;
  }
  
@@ -1342,14 +1331,15 @@ dri2_initialize_x11_dri3(_EGLDriver *drv, _EGLDisplay *disp)

 if (!dri2_dpy)
return _eglError(EGL_BAD_ALLOC, "eglInitialize");
  
+   dri2_dpy->fd = -1;

 if (!dri2_get_xcb_connection(drv, disp, dri2_dpy))
-  goto cleanup_dpy;
+  goto cleanup;
  
 if (!dri3_x11_connect(dri2_dpy))

-  goto cleanup_conn;
+  goto cleanup;
  
 if (!dri2_load_driver_dri3(disp))

-  goto cleanup_conn;
+  goto cleanup;
  
 dri2_dpy->loader_extensions = dri3_image_loader_extensions;
  
@@ -1357,7 +1347,7 @@ dri2_initialize_x11_dri3(_EGLDriver *drv, _EGLDisplay *disp)

 dri2_dpy->invalidate_available = true;
  
 if (!dri2_create_screen(disp))

-  goto cleanup_fd;
+  goto cleanup;
  
 dri2_x11_setup_swap_interval(dri2_dpy);
  
@@ -1370,7 +1360,7 @@ dri2_initialize_x11_dri3(_EGLDriver *drv, _EGLDisplay *disp)

 dri2_set_WL_bind_wayland_display(drv, disp);
  
 if (!dri2_x11_add_configs_for_visuals(dri2_dpy, disp, false))

-  goto cleanup_configs;
+  goto cleanup;
  
 dri2_dpy->loader_dri3_ext.core = dri2_dpy->core;

 dri2_dpy->loader_dri3_ext.image_driver = dri2_dpy->image_driver;
@@ -1388,19 +1378,8 @@ dri2_initialize_x11_dri3(_EGLDriver *drv, _EGLDisplay 
*disp)
  
 return EGL_TRUE;
  
- cleanup_configs:

-   _eglCleanupDisplay(disp);
-   dri2_dpy->core->destroyScreen(dri2_dpy->dri_screen);
-   dlclose(dri2_dpy->driver);
- cleanup_fd:
-   close(dri2_dpy->fd);
- cleanup_conn:
-   if (disp->PlatformDisplay == NULL)
-  xcb_disconnect(dri2_dpy->conn);
- cleanup_dpy:
-   free(dri2_dpy);
-   disp->DriverData = NULL;
-
+ cleanup:
+   dri2_display_destroy(disp);
 return EGL_FALSE;
  }
  #endif
@@ -1444,14 +1423,15 @@ dri2_initialize_x11_dri2(_EGLDriver *drv, _EGLDisplay 
*disp)
 if (!dri2_dpy)
return _eglError(EGL_BAD_ALLOC, "eglInitialize");
  
+   dri2_dpy->fd = -1;

 if (!dri2_get_xcb_connection(drv, disp, dri2_dpy))
-  goto cleanup_dpy;
+  goto cleanup;
  
 if (!dri2_x11_connect(dri2_dpy))

-  goto cleanup_conn;
+  goto cleanup;
  
 if (!dri2_load_driver(disp))

-  goto cleanup_fd;
+  goto cleanup;
  
 if (dri2_dpy->dri2_minor >= 1)

dri2_dpy->loader_extensions = dri2_loader_extensions;
@@ -1462,7 +1442,7 @@ dri2_initialize_x11_dri2(_EGLDriver *drv, _EGLDisplay 
*disp)
 dri2_dpy->invalidate_available = (dri2_dpy->dri2_minor >= 3);
  
 if (!dri2_create_screen(disp))

-  goto cleanup_driver;
+  goto cleanup;
  
 dri2_x11_setup_swap_interval(dri2_dpy);
  
@@ -1475,7 +1455,7 @@ dri2_initialize_x11_dri2(_EGLDriver *drv, _EGLDisplay *disp)

 dri2_set_WL_bind_wayland_display(drv, disp);
  
 if (!dri2_x11_add_configs_for_visuals(dri2_dpy, disp, true))

-  goto cleanup_configs;
+  goto cleanup;
  
 /* Fill vtbl last to prevent accidentally calling virtual function during

  * initialization.
@@ -1486,20 +14

Re: [Mesa-dev] [PATCH 0/2] Extended the release calendar

2017-05-12 Thread Juan A. Suarez Romero
On Sat, 2017-05-06 at 18:46 +0300, Andres Gomez wrote:
> Calendar updated and extended until end of August.
> 

Both patches:

Reviewed-by: Juan A. Suarez Romero 

> Andres Gomez (2):
>   docs: update "Release manager" column
>   docs: extend until the end of August
> 
>  docs/release-calendar.html | 68 
> +++---
>  1 file changed, 64 insertions(+), 4 deletions(-)
> 
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Re: [Mesa-dev] [PATCH 06/13] egl/android: make use of dri2_display_destroy() helper

2017-05-12 Thread Tapani Pälli



On 05/11/2017 09:57 PM, Emil Velikov wrote:

From: Emil Velikov 

Cc: Tomasz Figa 
Cc: Tapani Pälli 
Signed-off-by: Emil Velikov 
---
  src/egl/drivers/dri2/platform_android.c | 27 +--
  1 file changed, 9 insertions(+), 18 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 49cbeb4698e..f1038957850 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -1107,11 +1107,12 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay 
*dpy)
 if (!dri2_dpy)
return _eglError(EGL_BAD_ALLOC, "eglInitialize");
  
+   dri2_dpy->fd = -1;

 ret = hw_get_module(GRALLOC_HARDWARE_MODULE_ID,
 (const hw_module_t **)&dri2_dpy->gralloc);
 if (ret) {
err = "DRI2: failed to get gralloc module";
-  goto cleanup_display;
+  goto cleanup;
 }
  
 dpy->DriverData = (void *) dri2_dpy;

@@ -1119,18 +1120,18 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay 
*dpy)
 dri2_dpy->fd = droid_open_device(dri2_dpy);
 if (dri2_dpy->fd < 0) {
err = "DRI2: failed to open device";
-  goto cleanup_display;
+  goto cleanup;
 }
  
 dri2_dpy->driver_name = loader_get_driver_for_fd(dri2_dpy->fd);

 if (dri2_dpy->driver_name == NULL) {
err = "DRI2: failed to get driver name";
-  goto cleanup_device;
+  goto cleanup;
 }
  
 if (!dri2_load_driver(dpy)) {

err = "DRI2: failed to load driver";
-  goto cleanup_driver_name;
+  goto cleanup;
 }
  
 dri2_dpy->is_render_node = drmGetNodeTypeFromFd(dri2_dpy->fd) == DRM_NODE_RENDER;

@@ -1144,12 +1145,12 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay 
*dpy)
  
 if (!dri2_create_screen(dpy)) {

err = "DRI2: failed to create screen";
-  goto cleanup_driver;
+  goto cleanup;
 }
  
 if (!droid_add_configs_for_visuals(drv, dpy)) {

err = "DRI2: failed to add configs";
-  goto cleanup_screen;
+  goto cleanup;
 }
  
 dpy->Extensions.ANDROID_framebuffer_target = EGL_TRUE;

@@ -1164,17 +1165,7 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay 
*dpy)
  
 return EGL_TRUE;
  
-cleanup_screen:

-   dri2_dpy->core->destroyScreen(dri2_dpy->dri_screen);
-cleanup_driver:
-   dlclose(dri2_dpy->driver);
-cleanup_driver_name:
-   free(dri2_dpy->driver_name);
-cleanup_device:
-   close(dri2_dpy->fd);
-cleanup_display:
-   free(dri2_dpy);
-   dpy->DriverData = NULL;
-
+cleanup:
+   dri2_display_destroy(disp);


disp -> dpy


 return _eglError(EGL_NOT_INITIALIZED, err);
  }


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Re: [Mesa-dev] [PATCH] mesa: fix KHR_no_error SSO support

2017-05-12 Thread Samuel Pitoiset

Reviewed-by: Samuel Pitoiset 

On 05/12/2017 07:29 AM, Timothy Arceri wrote:

Fixes: 00c5119a5e821 ("mesa: add KHR_no_error support for glUseProgramStages()")
---

  Found with the new no_error piglit profile [1]. Up until now my testing has 
been
  adhoc, selecting a few tests that take the new KHR_no_error path. Going 
forward
  testing should be more thorough once tests are enable in the new profile.

  [1] https://patchwork.freedesktop.org/series/24332/

   src/mesa/main/pipelineobj.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
index 67a8fc8..0d1d57c 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -258,21 +258,21 @@ void GLAPIENTRY
  _mesa_UseProgramStages_no_error(GLuint pipeline, GLbitfield stages,
  GLuint prog)
  {
 GET_CURRENT_CONTEXT(ctx);
  
 struct gl_pipeline_object *pipe =

_mesa_lookup_pipeline_object(ctx, pipeline);
 struct gl_shader_program *shProg = NULL;
  
 if (prog)

-  _mesa_lookup_shader_program(ctx, prog);
+  shProg = _mesa_lookup_shader_program(ctx, prog);
  
 /* Object is created by any Pipeline call but glGenProgramPipelines,

  * glIsProgramPipeline and GetProgramPipelineInfoLog
  */
 pipe->EverBound = GL_TRUE;
  
 use_program_stages(ctx, shProg, stages, pipe);

  }
  
  /**



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