[Mesa-dev] [PATCH v3 2/2] etnaviv: Add support for ETC2 texture compression

[laanwj]

From: "Wladimir J. van der Laan" 

Add support for ETC2 compressed textures in the etnaviv driver.

One step closer towards GL ES 3 support.

For now, treat SRGB and RGB formats the same. It looks like these are
distinguished using a different bit in sampler state, and not part of
the format, but I have not yet been able to confirm this for sure.

(Only enabled on GC3000+ for now, as the GC2000 ETC2 decoder
implementation is buggy and we don't work around that)

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/etnaviv/etnaviv_format.c | 11 +++
 src/gallium/drivers/etnaviv/etnaviv_screen.c | 12 +++-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/etnaviv/etnaviv_format.c 
b/src/gallium/drivers/etnaviv/etnaviv_format.c
index 354dc20..492499a 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_format.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_format.c
@@ -233,6 +233,17 @@ static struct etna_format formats[PIPE_FORMAT_COUNT] = {
_T(DXT3_RGBA, DXT2_DXT3, SWIZ(X, Y, Z, W), NONE),
_T(DXT5_RGBA, DXT4_DXT5, SWIZ(X, Y, Z, W), NONE),
 
+   _T(ETC2_RGB8,   EXT_NONE | EXT_FORMAT,  SWIZ(X, 
Y, Z, W), NONE), /* Extd. format NONE doubles as ETC2_RGB8 */
+   _T(ETC2_SRGB8,  EXT_NONE | EXT_FORMAT,  SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_RGB8A1, EXT_RGB8_PUNCHTHROUGH_ALPHA1_ETC2 | EXT_FORMAT, SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_SRGB8A1,EXT_RGB8_PUNCHTHROUGH_ALPHA1_ETC2 | EXT_FORMAT, SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_RGBA8,  EXT_RGBA8_ETC2_EAC | EXT_FORMAT,SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_SRGBA8, EXT_RGBA8_ETC2_EAC | EXT_FORMAT,SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_R11_UNORM,  EXT_R11_EAC | EXT_FORMAT,   SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_R11_SNORM,  EXT_SIGNED_R11_EAC | EXT_FORMAT,SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_RG11_UNORM, EXT_RG11_EAC | EXT_FORMAT,  SWIZ(X, 
Y, Z, W), NONE),
+   _T(ETC2_RG11_SNORM, EXT_SIGNED_RG11_EAC | EXT_FORMAT,   SWIZ(X, 
Y, Z, W), NONE),
+
/* YUV */
_T(YUYV, YUY2, SWIZ(X, Y, Z, W), YUY2),
_T(UYVY, UYVY, SWIZ(X, Y, Z, W), NONE),
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 96f9a8e..5dc436d 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -471,9 +471,19 @@ gpu_supports_texure_format(struct etna_screen *screen, 
uint32_t fmt,
if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
   supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
 
-   if (fmt & EXT_FORMAT)
+   if (fmt & EXT_FORMAT) {
   supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
 
+  /* ETC1 is checked above, as it has its own feature bit. ETC2 is
+   * supported with HALTI0, however that implementation is buggy in 
hardware.
+   * The blob driver does per-block patching to work around this. As this
+   * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000)
+   * only.
+   */
+  if (util_format_is_etc(format))
+ supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
+   }
+
if (!supported)
   return false;
 
-- 
2.7.4

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[Mesa-dev] [PATCH v3 1/2] gallium/util: Implement util_format_is_etc

[laanwj]

From: "Wladimir J. van der Laan" 

This is the equivalent of util_format_is_s3tc, but for
ETC.

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/auxiliary/util/u_format.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/gallium/auxiliary/util/u_format.h 
b/src/gallium/auxiliary/util/u_format.h
index d055778..2318e97 100644
--- a/src/gallium/auxiliary/util/u_format.h
+++ b/src/gallium/auxiliary/util/u_format.h
@@ -496,6 +496,19 @@ util_format_is_s3tc(enum pipe_format format)
 }
 
 static inline boolean 
+util_format_is_etc(enum pipe_format format)
+{
+   const struct util_format_description *desc = 
util_format_description(format);
+
+   assert(desc);
+   if (!desc) {
+  return FALSE;
+   }
+
+   return desc->layout == UTIL_FORMAT_LAYOUT_ETC ? TRUE : FALSE;
+}
+
+static inline boolean 
 util_format_is_srgb(enum pipe_format format)
 {
const struct util_format_description *desc = 
util_format_description(format);
-- 
2.7.4

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[Mesa-dev] [PATCH v3 0/2] etnaviv: Add support for ETC2 texture compression

[laanwj]

From: "Wladimir J. van der Laan" 

Add support for ETC2 compressed textures in the etnaviv driver.

One step closer towards GL ES 3 support.

For now, treat SRGB and RGB formats the same. It looks like these are
distinguished using a different bit in sampler state, and not part of
the format, but I have not yet been able to confirm this for sure.

(Only enabled on GC3000+ for now, as the GC2000 ETC2 decoder
implementation is buggy and we don't work around that)

Wladimir J. van der Laan (2):
  gallium/util: Implement util_format_is_etc
  etnaviv: Add support for ETC2 texture compression

 src/gallium/auxiliary/util/u_format.h| 13 +
 src/gallium/drivers/etnaviv/etnaviv_format.c | 11 +++
 src/gallium/drivers/etnaviv/etnaviv_screen.c | 12 +++-
 3 files changed, 35 insertions(+), 1 deletion(-)

-- 
2.7.4

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Re: [Mesa-dev] [PATCH 3/4] docs: avoid overwrite of LD_LIBRARY_PATH during basic testing

[Emil Velikov]

On 15 July 2017 at 17:01, Andres Gomez  wrote:
> On Mon, 2017-07-10 at 12:19 +0100, Emil Velikov wrote:
>> On 8 July 2017 at 20:59, Andres Gomez  wrote:
>> > The LD_LIBRARY_PATH environment variable could be already defined so
>> > we extend it and restore it rather than just overwriting it.
>> >
>>
>> Hmm, what are you doing to actually require LD_LIBRARY_PATH in the first 
>> place?
>> It makes it somewhat uneasy that one will have that in their setup.
>
> My everyday's work is done in a JHBuild env that already uses this
> variable for mesa dependencies. I would have assumed that this is
> actually quite normal for most of mesa developers, although maybe I'm
> wrong ...
>
This is the first time I hear anyone working on Mesa use JHBuild.
There could be some though ;-)

>>
>> > Signed-off-by: Andres Gomez 
>> > ---
>> >  docs/releasing.html | 4 +++-
>> >  1 file changed, 3 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/docs/releasing.html b/docs/releasing.html
>> > index 8e6e4d1a6d..99235d8412 100644
>> > --- a/docs/releasing.html
>> > +++ b/docs/releasing.html
>> > @@ -472,7 +472,8 @@ Here is one solution that I've been using.
>> > __glxgears_cmd='glxgears 2>&1 | grep -v "configuration file"'
>> > __es2info_cmd='es2_info 2>&1 | egrep 
>> > "GL_VERSION|GL_RENDERER|.*dri\.so"'
>> > __es2gears_cmd='es2gears_x11 2>&1 | grep -v "configuration 
>> > file"'
>> > -   export LD_LIBRARY_PATH=`pwd`/test/usr/local/lib/
>> > +   'x$LD_LIBRARY_PATH' -ne 'x' && __old_ld='$LD_LIBRARY_PATH' 
>> > && __token=':'
>> > +   export 
>> > LD_LIBRARY_PATH=`pwd`/test/usr/local/lib/'${__token}${__old_ld}'
>>
>> AFAICT you don't need __token.
>
> You do if you want to avoid adding ":" at the end when LD_LIBRARY_PATH
> is not defined previously. It can be done in other ways but I thought
> this to be the simplest/easiest to read.
>
I was thinking about adding the colon, unconditionally. AFAICT things
work perfectly fine with it. Even if one extends LD_LIBRARY_PATH at a
later stage.
But if you really want to avoid it this is the shortest way, indeed.

-Emil
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Re: [Mesa-dev] egl: propagate EGL_BAD_ATTRIBUTE during EGLImage attr parsing

[Eric Engestrom]

On Thursday, 2017-07-13 20:04:33 +0100, Emil Velikov wrote:
> From: Emil Velikov 
> 
> Earlier commit refactored/split the parsing into separate hunks.
> While no functional change was intended, it did not attribute that
> different error is set when the attrib. value is incorrect.
> 
> Fixes:  3ee2be4113d ("egl: split _eglParseImageAttribList into per
> extension functions")
> Cc: Michel Dänzer 
> Reported-by: Michel Dänzer 
> Signed-off-by: Emil Velikov 

Reviewed-by: Eric Engestrom 

> ---
> There's at least one other way (tad longer and more extensive) way to
> address this. Considering no other extensions bother with separate
> error, that may be an overkill... for now.
> ---
>  src/egl/main/eglimage.c | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/src/egl/main/eglimage.c b/src/egl/main/eglimage.c
> index a96075fe558..72a556e8dbd 100644
> --- a/src/egl/main/eglimage.c
> +++ b/src/egl/main/eglimage.c
> @@ -302,6 +302,13 @@ _eglParseImageAttribList(_EGLImageAttribs *attrs, 
> _EGLDisplay *dpy,
>if (err == EGL_SUCCESS)
>continue;
>  
> +  /* EXT_image_dma_buf_import states that if invalid value is provided 
> for
> +   * its attributes, we should return EGL_BAD_ATTRIBUTE.
> +   * Bail out ASAP, since follow-up calls can return another EGL_BAD 
> error.
> +   */
> +  if (err == EGL_BAD_ATTRIBUTE)
> +  return _eglError(err, __func__);
> +
>err = _eglParseEXTImageDmaBufImportModifiersAttribs(attrs, dpy, attr, 
> val);
>if (err == EGL_SUCCESS)
>continue;
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Re: [Mesa-dev] [PATCH] anv/image: Fix VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT

[Lionel Landwerlin]

On 18/07/17 05:07, Jason Ekstrand wrote:
On Mon, Jul 17, 2017 at 5:18 PM, Chad Versace 
mailto:chadvers...@chromium.org>> wrote:


On Tue 18 Jul 2017, Lionel Landwerlin wrote:
> Oh dear :/
>
> Reviewed-by: Lionel Landwerlin mailto:lionel.g.landwer...@intel.com>>
>
> On 17/07/17 23:32, Chad Versace wrote:
> > We incorrectly detected VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT.
We looked
> > for the bit in VkImageCreateInfo::usage, but it's actually in
> > VkImageCreateInfo::flags.
> >
> > Found by assertion failures while enabling
VK_ANDROID_native_buffer.
> >
> > Cc: mesa-sta...@lists.freedesktop.org

> > ---
> >
> > Can someone at Intel please confirm that this doesn't regress
Jenkins?
> > I pushed this to my 'jenkins' branch, but I don't know if Intel's
> > Jenkins still runs my branches.

Could someone at Intel please check my patch Jenkins? Thanks. I don't
want to push this if it makes Jenkins red.


I just kicked it off.  I'll let you know in the morning.


Did the same, it's all green.

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Re: [Mesa-dev] [PATCH v2] etnaviv: Add support for ETC2 texture compression

[Wladimir]

> h (format) {
>
> How about
>
> const struct util_format_description *desc = util_format_description(format);
> return desc->layout == UTIL_FORMAT_LAYOUT_ETC;

I intentionally exclude PIPE_FORMAT_ETC1_RGB8 here because it is
implemented on older hw and has its own feature bit
(ETC1_TEXTURE_COMPRESSION).
But yes that shortens the code at least, thanks.

> There's already a util_format_is_s3tc helper, I don't think it'd be
way out of line to add one for etc as well.

Ok, will add one.

Regards,
Wladimir
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[Mesa-dev] [PATCH 21/22] i965: Drop redundant check for non-tiled depth buffer

[Topi Pohjolainen]

Depth buffers are always Y-tiled. In brw_miptree_choose_tiling()
driver opts to use linear buffers for small and 1D but this does
not apply for depth - GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL_EXT
are considered first.

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_misc_state.c   | 3 +--
 src/mesa/drivers/dri/i965/gen6_depth_state.c | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 0c43d2b4b2..1e3be784c5 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -383,8 +383,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
  (depthbuffer_format << 18) |
  (BRW_TILEWALK_YMAJOR << 26) |
- ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
-  << 27) |
+ (1 << 27) |
  (depth_surface_type << 29));
 
if (depth_mt) {
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 8f05b4cc1a..3e3d2c629b 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -121,8 +121,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
  ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
  ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
  (BRW_TILEWALK_YMAJOR << 26) |
- ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
-  << 27) |
+ (1 << 27) |
  (surftype << 29));
 
/* 3DSTATE_DEPTH_BUFFER dw2 */
-- 
2.11.0

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[Mesa-dev] [PATCH 18/22] i965/miptree: Prepare aux state map for isl based

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d96f5c7938..fafd0c1e59 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -696,8 +696,14 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
const uint32_t levels = mt->last_level + 1;
 
uint32_t total_slices = 0;
-   for (uint32_t level = 0; level < levels; level++)
-  total_slices += mt->level[level].depth;
+   for (uint32_t level = 0; level < levels; level++) {
+  if (mt->surf.size > 0)
+ total_slices += (mt->surf.dim == ISL_SURF_DIM_3D ?
+ minify(mt->surf.phys_level0_sa.depth, level) :
+ mt->surf.phys_level0_sa.array_len);
+  else
+ total_slices += mt->level[level].depth;
+   }
 
const size_t per_level_array_size = levels * sizeof(enum isl_aux_state *);
 
@@ -715,7 +721,16 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
enum isl_aux_state *s = data + per_level_array_size;
for (uint32_t level = 0; level < levels; level++) {
   per_level_arr[level] = s;
-  for (uint32_t a = 0; a < mt->level[level].depth; a++)
+
+  unsigned level_depth;
+  if (mt->surf.size > 0)
+ level_depth = mt->surf.dim == ISL_SURF_DIM_3D ?
+  minify(mt->surf.phys_level0_sa.depth, level) :
+  mt->surf.phys_level0_sa.array_len;
+  else
+ level_depth = mt->level[level].depth;
+  
+  for (uint32_t a = 0; a < level_depth; a++)
  *(s++) = initial;
}
assert((void *)s == data + total_size);
-- 
2.11.0

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[Mesa-dev] [PATCH 16/22] i965/miptree: Represent w-tiled stencil surfaces with isl

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/gen7_misc_state.c   | 20 +-
 src/mesa/drivers/dri/i965/gen8_depth_state.c  | 26 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 38 ---
 3 files changed, 38 insertions(+), 46 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c 
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 43422900e2..c0cb7470bf 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -83,7 +83,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
   break;
case GL_TEXTURE_3D:
   assert(mt);
-  depth = MAX2(mt->logical_depth0, 1);
+  depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
+  MAX2(mt->logical_depth0, 1);
   /* fallthrough */
default:
   surftype = translate_tex_target(gl_target);
@@ -94,7 +95,10 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
 
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 
-   if (mt) {
+   if (mt && mt->surf.size > 0) {
+  width = mt->surf.logical_level0_px.width;
+  height = mt->surf.logical_level0_px.height;
+   } else if (mt) {
   width = mt->logical_width0;
   height = mt->logical_height0;
}
@@ -170,19 +174,9 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
 
   BEGIN_BATCH(3);
   OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
-  /* The stencil buffer has quirky pitch requirements.  From the
-   * Sandybridge PRM, Volume 2 Part 1, page 329 (3DSTATE_STENCIL_BUFFER
-   * dword 1 bits 16:0 - Surface Pitch):
-   *
-   *The pitch must be set to 2x the value computed based on width, as
-   *the stencil buffer is stored with two rows interleaved.
-   *
-   * While the Ivybridge PRM lacks this comment, the BSpec contains the
-   * same text, and experiments indicate that this is necessary.
-   */
   OUT_BATCH(enabled |
 mocs << 25 |
-   (2 * stencil_mt->surf.row_pitch - 1));
+   (stencil_mt->surf.row_pitch - 1));
   OUT_RELOC(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 9cb0d07688..c934d0d21a 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -111,25 +111,11 @@ emit_depth_packets(struct brw_context *brw,
} else {
   BEGIN_BATCH(5);
   OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
-  /* The stencil buffer has quirky pitch requirements.  From the Graphics
-   * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing
-   * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+],
-   * field "Surface Pitch":
-   *
-   *The pitch must be set to 2x the value computed based on width, as
-   *the stencil buffer is stored with two rows interleaved.
-   *
-   * (Note that it is not 100% clear whether this intended to apply to
-   * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would
-   * imply that it doesn't), however the comment appears on a "DevIVB+"
-   * page (which would imply that it does).  Experiments with the hardware
-   * indicate that it does.
-   */
   OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
-(2 * stencil_mt->surf.row_pitch - 1));
+(stencil_mt->surf.row_pitch - 1));
   OUT_RELOC64(stencil_mt->bo,
   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-  OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
+  OUT_BATCH(stencil_mt->surf.array_pitch_el_rows >> 2);
   ADVANCE_BATCH();
}
 
@@ -189,7 +175,8 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
   break;
case GL_TEXTURE_3D:
   assert(mt);
-  depth = MAX2(mt->logical_depth0, 1);
+  depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
+  MAX2(mt->logical_depth0, 1);
   surftype = translate_tex_target(gl_target);
   break;
case GL_TEXTURE_1D_ARRAY:
@@ -212,7 +199,10 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
 
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
 
-   if (mt) {
+   if (mt && mt->surf.size > 0) {
+  width = mt->surf.logical_level0_px.width;
+  height = mt->surf.logical_level0_px.height;
+   } else if (mt) {
   width = mt->logical_width0;
   height = mt->logical_height0;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 1b8c0da80d..adaa6a94ab 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -817,7 +817,7 @@ miptree_create(struct brw_context *brw

[Mesa-dev] [PATCH 19/22] i965/miptree: Prepare 3D surfaces with physical 2D layout

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 39 +++
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index fafd0c1e59..702dcd8635 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -668,6 +668,21 @@ intel_lower_compressed_format(struct brw_context *brw, 
mesa_format format)
}
 }
 
+static unsigned
+get_num_phys_layers(const struct isl_surf *surf, unsigned level)
+{
+   /* In case of physical dimensions one needs to consider also the layout.
+* See isl_calc_phys_level0_extent_sa().
+*/
+   if (surf->dim != ISL_SURF_DIM_3D)
+  return surf->phys_level0_sa.array_len;
+
+   if (surf->dim_layout == ISL_DIM_LAYOUT_GEN4_2D)
+  return minify(surf->phys_level0_sa.array_len, level);
+
+   return minify(surf->phys_level0_sa.depth, level);
+}
+
 /** \brief Assert that the level and layer are valid for the miptree. */
 void
 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
@@ -682,9 +697,7 @@ intel_miptree_check_level_layer(const struct 
intel_mipmap_tree *mt,
assert(level <= mt->last_level);
 
if (mt->surf.size > 0)
-  assert(layer < (mt->surf.dim == ISL_SURF_DIM_3D ?
- minify(mt->surf.phys_level0_sa.depth, level) :
- mt->surf.phys_level0_sa.array_len));
+  assert(layer < get_num_phys_layers(&mt->surf, level));
else
   assert(layer < mt->level[level].depth);
 }
@@ -698,9 +711,7 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
uint32_t total_slices = 0;
for (uint32_t level = 0; level < levels; level++) {
   if (mt->surf.size > 0)
- total_slices += (mt->surf.dim == ISL_SURF_DIM_3D ?
- minify(mt->surf.phys_level0_sa.depth, level) :
- mt->surf.phys_level0_sa.array_len);
+ total_slices += get_num_phys_layers(&mt->surf, level);
   else
  total_slices += mt->level[level].depth;
}
@@ -724,9 +735,7 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
 
   unsigned level_depth;
   if (mt->surf.size > 0)
- level_depth = mt->surf.dim == ISL_SURF_DIM_3D ?
-  minify(mt->surf.phys_level0_sa.depth, level) :
-  mt->surf.phys_level0_sa.array_len;
+ level_depth = get_num_phys_layers(&mt->surf, level);
   else
  level_depth = mt->level[level].depth;
   
@@ -1680,11 +1689,9 @@ intel_miptree_copy_slice(struct brw_context *brw,
   height = minify(src_mt->surf.phys_level0_sa.height,
   src_level - src_mt->first_level);
 
-  if (src_mt->surf.dim == ISL_SURF_DIM_3D)
- assert(src_layer < minify(src_mt->surf.phys_level0_sa.depth,
-   src_level - src_mt->first_level));
-  else
- assert(src_layer < src_mt->surf.phys_level0_sa.array_len);
+  assert(src_layer <
+ get_num_phys_layers(&src_mt->surf,
+ src_level - src_mt->first_level));
} else {
   width = minify(src_mt->physical_width0,
  src_level - src_mt->first_level);
@@ -2475,9 +2482,7 @@ miptree_layer_range_length(const struct intel_mipmap_tree 
*mt, uint32_t level,
uint32_t total_num_layers;
 
if (mt->surf.size > 0)
-  total_num_layers = mt->surf.dim == ISL_SURF_DIM_3D ?
- minify(mt->surf.phys_level0_sa.depth, level) :
- mt->surf.phys_level0_sa.array_len;
+  total_num_layers = get_num_phys_layers(&mt->surf, level);
else 
   total_num_layers = mt->level[level].depth;
 
-- 
2.11.0

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[Mesa-dev] [PATCH 20/22] intel/isl/gen4: Represent cube maps with 3D layout

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/intel/isl/isl.c | 40 +++-
 1 file changed, 35 insertions(+), 5 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 12ffe3bb51..90b36c33bc 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -548,7 +548,8 @@ isl_choose_image_alignment_el(const struct isl_device *dev,
 static enum isl_dim_layout
 isl_surf_choose_dim_layout(const struct isl_device *dev,
enum isl_surf_dim logical_dim,
-   enum isl_tiling tiling)
+   enum isl_tiling tiling,
+   isl_surf_usage_flags_t usage)
 {
/* Sandy bridge needs a special layout for HiZ and stencil. */
if (ISL_DEV_GEN(dev) == 6 &&
@@ -584,6 +585,16 @@ isl_surf_choose_dim_layout(const struct isl_device *dev,
   switch (logical_dim) {
   case ISL_SURF_DIM_1D:
   case ISL_SURF_DIM_2D:
+ /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
+  *
+  * The cube face textures are stored in the same way as 3D surfaces
+  * are stored (see section 6.17.5 for details).  For cube surfaces,
+  * however, the depth is equal to the number of faces (always 6) and 
+  * is not reduced for each MIP.
+  */
+ if (ISL_DEV_GEN(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
+return ISL_DIM_LAYOUT_GEN4_3D;
+
  return ISL_DIM_LAYOUT_GEN4_2D;
   case ISL_SURF_DIM_3D:
  return ISL_DIM_LAYOUT_GEN4_3D;
@@ -635,8 +646,11 @@ isl_calc_phys_level0_extent_sa(const struct isl_device 
*dev,
   break;
 
case ISL_SURF_DIM_2D:
-  assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
- dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
+  if (ISL_DEV_GEN(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT))
+ assert(dim_layout == ISL_DIM_LAYOUT_GEN4_3D);
+  else
+ assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
+dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
 
   if (tiling == ISL_TILING_Ys && info->samples > 1)
  isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__);
@@ -952,7 +966,11 @@ isl_calc_phys_total_extent_el_gen4_3d(
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
 
assert(info->samples == 1);
-   assert(phys_level0_sa->array_len == 1);
+
+   if (info->usage & ISL_SURF_USAGE_CUBE_BIT)
+  assert(phys_level0_sa->array_len == 6);
+   else
+  assert(phys_level0_sa->array_len == 1);
 
uint32_t total_w = 0;
uint32_t total_h = 0;
@@ -966,6 +984,18 @@ isl_calc_phys_total_extent_el_gen4_3d(
   uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h);
   uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa->d);
 
+  /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
+   *
+   * The cube face textures are stored in the same way as 3D surfaces
+   * are stored (see section 6.17.5 for details).  For cube surfaces,
+   * however, the depth is equal to the number of faces (always 6) and 
+   * is not reduced for each MIP.
+   */
+  if (info->usage & ISL_SURF_USAGE_CUBE_BIT) {
+ assert(ISL_DEV_GEN(dev) == 4);
+ level_d = 6;
+  }
+
   uint32_t max_layers_horiz = MIN(level_d, 1u << l);
   uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
 
@@ -1427,7 +1457,7 @@ isl_surf_init_s(const struct isl_device *dev,
isl_tiling_get_info(tiling, fmtl->bpb, &tile_info);
 
const enum isl_dim_layout dim_layout =
-  isl_surf_choose_dim_layout(dev, info->dim, tiling);
+  isl_surf_choose_dim_layout(dev, info->dim, tiling, info->usage);
 
enum isl_msaa_layout msaa_layout;
if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout))
-- 
2.11.0

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[Mesa-dev] [PATCH 17/22] i965/miptree: Represent y-tiled stencil copies with isl

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index adaa6a94ab..d96f5c7938 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2944,11 +2944,8 @@ intel_update_r8stencil(struct brw_context *brw,
assert(src->surf.size > 0);
 
if (!mt->r8stencil_mt) {
-  const uint32_t r8stencil_flags =
- MIPTREE_LAYOUT_ACCELERATED_UPLOAD | MIPTREE_LAYOUT_TILING_Y |
- MIPTREE_LAYOUT_DISABLE_AUX;
   assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
-  mt->r8stencil_mt = intel_miptree_create(
+  mt->r8stencil_mt = make_surface(
 brw,
 src->target,
 MESA_FORMAT_R_UINT8,
@@ -2959,7 +2956,9 @@ intel_update_r8stencil(struct brw_context *brw,
src->surf.logical_level0_px.depth :
src->surf.logical_level0_px.array_len,
 src->surf.samples,
-r8stencil_flags);
+ISL_TILING_Y0_BIT,
+ISL_SURF_USAGE_TEXTURE_BIT,
+BO_ALLOC_FOR_RENDER, 0, NULL);
   assert(mt->r8stencil_mt);
}
 
-- 
2.11.0

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[Mesa-dev] [PATCH 22/22] i965: Represent depth surfaces with isl

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_clear.c |   5 +-
 src/mesa/drivers/dri/i965/gen8_depth_state.c  |   3 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 136 +-
 3 files changed, 97 insertions(+), 47 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 7fbaa3a47d..c310d2547a 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -121,7 +121,8 @@ brw_fast_clear_depth(struct gl_context *ctx)
if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) {
   perf_debug("Failed to fast clear %dx%d depth because of scissors.  "
  "Possible 5%% performance win if avoided.\n",
- mt->logical_width0, mt->logical_height0);
+ mt->surf.logical_level0_px.width,
+ mt->surf.logical_level0_px.height);
   return false;
}
 
@@ -149,7 +150,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
*optimization must be disabled.
*/
   if (brw->gen == 6 &&
-  (minify(mt->physical_width0,
+  (minify(mt->surf.phys_level0_sa.width,
   depth_irb->mt_level - mt->first_level) % 16) != 0)
 return false;
   break;
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index c934d0d21a..5cee93ade0 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -78,7 +78,8 @@ emit_depth_packets(struct brw_context *brw,
OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
OUT_BATCH(0);
-   OUT_BATCH(((depth - 1) << 21) | (depth_mt ? depth_mt->qpitch >> 2 : 0));
+   OUT_BATCH(((depth - 1) << 21) |
+  (depth_mt ? depth_mt->surf.array_pitch_el_rows >> 2 : 0));
ADVANCE_BATCH();
 
if (!hiz) {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 702dcd8635..ea8b2662fd 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -520,43 +520,7 @@ intel_miptree_create_layout(struct brw_context *brw,
mt->physical_height0 = height0;
mt->physical_depth0 = depth0;
 
-   if (needs_separate_stencil(brw, mt, format, layout_flags)) {
-  uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
-  if (brw->gen == 6) {
- stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
-  }
-
-  mt->stencil_mt = intel_miptree_create(brw,
-mt->target,
-MESA_FORMAT_S_UINT8,
-mt->first_level,
-mt->last_level,
-mt->logical_width0,
-mt->logical_height0,
-mt->logical_depth0,
-num_samples,
-stencil_flags);
-
-  if (!mt->stencil_mt) {
-intel_miptree_release(&mt);
-return NULL;
-  }
-  mt->stencil_mt->r8stencil_needs_update = true;
-
-  /* Fix up the Z miptree format for how we're splitting out separate
-   * stencil.  Gen7 expects there to be no stencil bits in its depth 
buffer.
-   */
-  mt->format = intel_depth_format_for_depthstencil_format(mt->format);
-  mt->cpp = 4;
-
-  if (format == mt->format) {
- _mesa_problem(NULL, "Unknown format %s in separate stencil mt\n",
-   _mesa_get_format_name(mt->format));
-  }
-   }
-
-   if (layout_flags & MIPTREE_LAYOUT_GEN6_HIZ_STENCIL)
-  mt->array_layout = GEN6_HIZ_STENCIL;
+   assert(!needs_separate_stencil(brw, mt, format, layout_flags));
 
/*
 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
@@ -829,6 +793,40 @@ fail:
return NULL;
 }
 
+static bool
+separate_stencil_surface(struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+   mt->stencil_mt = make_surface(brw, mt->target, MESA_FORMAT_S_UINT8,
+ 0, mt->surf.levels - 1,
+ mt->surf.logical_level0_px.width,
+ mt->surf.logical_level0_px.height,
+ mt->surf.dim == ISL_SURF_DIM_3D ?
+mt->surf.logical_level0_px.depth :
+mt->surf.logical_level0_px.array_len,
+ mt->surf.samples, ISL_TILING_W_BIT,
+ ISL_SURF_USAGE_STENCIL_BIT |
+ ISL_SURF_USAGE_TEXTURE_BIT,
+ BO_ALLOC_FOR_RENDER, 0, NULL);

[Mesa-dev] [PATCH 14/22] i965/miptree: Add support for imported bo offsets for isl based

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 879036ce77..a0b129adb4 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1435,9 +1435,22 @@ intel_miptree_get_image_offset(const struct 
intel_mipmap_tree *mt,
   GLuint level, GLuint slice,
   GLuint *x, GLuint *y)
 {
+   if (level == 0 && slice == 0) {
+  *x = mt->level[0].level_x;
+  *y = mt->level[0].level_y;
+  return;
+   }
+
if (mt->surf.size > 0) {
   uint32_t x_offset_sa, y_offset_sa;
 
+  /* Miptree itself can have an offset only if it represents a single
+   * slice in an imported buffer object.
+   * See intel_miptree_create_for_dri_image().
+   */
+  assert(mt->level[0].level_x == 0);
+  assert(mt->level[0].level_y == 0);
+
   /* Given level is relative to level zero while the miptree may be
* represent just a subset of all levels starting from 'first_level'.
*/
-- 
2.11.0

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[Mesa-dev] [PATCH 10/22] i965: Refactor miptree to isl converter and adjustment

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 103 +--
 1 file changed, 57 insertions(+), 46 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a8c40d54d8..3f2ca82fdb 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -75,6 +75,62 @@ uint32_t rb_mocs[] = {
 };
 
 static void
+get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
+ GLenum target, struct isl_view *view,
+ uint32_t *tile_x, uint32_t *tile_y,
+ uint32_t *offset, struct isl_surf *surf)
+{
+   intel_miptree_get_isl_surf(brw, mt, surf);
+
+   surf->dim = get_isl_surf_dim(target);
+
+   const enum isl_dim_layout dim_layout =
+  get_isl_dim_layout(&brw->screen->devinfo, mt->surf.tiling, target,
+ mt->array_layout);
+
+   if (surf->dim_layout == dim_layout)
+  return;
+
+   /* The layout of the specified texture target is not compatible with the
+* actual layout of the miptree structure in memory -- You're entering
+* dangerous territory, this can only possibly work if you only intended
+* to access a single level and slice of the texture, and the hardware
+* supports the tile offset feature in order to allow non-tile-aligned
+* base offsets, since we'll have to point the hardware to the first
+* texel of the level instead of relying on the usual base level/layer
+* controls.
+*/
+   assert(brw->has_surface_tile_offset);
+   assert(view->levels == 1 && view->array_len == 1);
+   assert(*tile_x == 0 && *tile_y == 0);
+
+   offset += intel_miptree_get_tile_offsets(mt, view->base_level,
+view->base_array_layer,
+tile_x, tile_y);
+
+   /* Minify the logical dimensions of the texture. */
+   const unsigned l = view->base_level - mt->first_level;
+   surf->logical_level0_px.width = minify(surf->logical_level0_px.width, l);
+   surf->logical_level0_px.height = surf->dim <= ISL_SURF_DIM_1D ? 1 :
+  minify(surf->logical_level0_px.height, l);
+   surf->logical_level0_px.depth = surf->dim <= ISL_SURF_DIM_2D ? 1 :
+  minify(surf->logical_level0_px.depth, l);
+
+   /* Only the base level and layer can be addressed with the overridden
+* layout.
+*/
+   surf->logical_level0_px.array_len = 1;
+   surf->levels = 1;
+   surf->dim_layout = dim_layout;
+
+   /* The requested slice of the texture is now at the base level and
+* layer.
+*/
+   view->base_level = 0;
+   view->base_array_layer = 0;
+}
+
+static void
 brw_emit_surface_state(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t flags,
GLenum target, struct isl_view view,
@@ -86,53 +142,8 @@ brw_emit_surface_state(struct brw_context *brw,
uint32_t offset = mt->offset;
 
struct isl_surf surf;
-   intel_miptree_get_isl_surf(brw, mt, &surf);
-
-   surf.dim = get_isl_surf_dim(target);
 
-   const enum isl_dim_layout dim_layout =
-  get_isl_dim_layout(&brw->screen->devinfo, mt->surf.tiling, target,
- mt->array_layout);
-
-   if (surf.dim_layout != dim_layout) {
-  /* The layout of the specified texture target is not compatible with the
-   * actual layout of the miptree structure in memory -- You're entering
-   * dangerous territory, this can only possibly work if you only intended
-   * to access a single level and slice of the texture, and the hardware
-   * supports the tile offset feature in order to allow non-tile-aligned
-   * base offsets, since we'll have to point the hardware to the first
-   * texel of the level instead of relying on the usual base level/layer
-   * controls.
-   */
-  assert(brw->has_surface_tile_offset);
-  assert(view.levels == 1 && view.array_len == 1);
-  assert(tile_x == 0 && tile_y == 0);
-
-  offset += intel_miptree_get_tile_offsets(mt, view.base_level,
-   view.base_array_layer,
-   &tile_x, &tile_y);
-
-  /* Minify the logical dimensions of the texture. */
-  const unsigned l = view.base_level - mt->first_level;
-  surf.logical_level0_px.width = minify(surf.logical_level0_px.width, l);
-  surf.logical_level0_px.height = surf.dim <= ISL_SURF_DIM_1D ? 1 :
- minify(surf.logical_level0_px.height, l);
-  surf.logical_level0_px.depth = surf.dim <= ISL_SURF_DIM_2D ? 1 :
- minify(surf.logical_level0_px.depth, l);
-
-  /* Only the base level and layer can be addressed with the overridden
-   * layout.
-   */
-  surf.logical_level0_px.array_len = 1;
-  surf.levels = 1;
-  surf.dim_layout = dim_layout;
-
-  /* The requested slice of the texture is now at the base

[Mesa-dev] [PATCH 09/22] i965: Prepare tex (sub)image for isl based

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_tex_image.c| 20 
 src/mesa/drivers/dri/i965/intel_tex_subimage.c |  8 +++-
 2 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 2db5a34655..13692ddd95 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -198,9 +198,16 @@ intel_set_texture_image_mt(struct brw_context *brw,
struct intel_texture_object *intel_texobj = intel_texture_object(texobj);
struct intel_texture_image *intel_image = intel_texture_image(image);
 
-   _mesa_init_teximage_fields(&brw->ctx, image,
- mt->logical_width0, mt->logical_height0, 1,
- 0, internal_format, mt->format);
+   if (mt->surf.size > 0) {
+  _mesa_init_teximage_fields(&brw->ctx, image,
+ mt->surf.logical_level0_px.width,
+ mt->surf.logical_level0_px.height, 1,
+ 0, internal_format, mt->format);
+   } else {
+  _mesa_init_teximage_fields(&brw->ctx, image,
+ mt->logical_width0, mt->logical_height0, 1,
+ 0, internal_format, mt->format);
+   }
 
brw->ctx.Driver.FreeTextureImageBuffer(&brw->ctx, image);
 
@@ -455,7 +462,12 @@ intel_gettexsubimage_tiled_memcpy(struct gl_context *ctx,
/* Since we are going to write raw data to the miptree, we need to resolve
 * any pending fast color clears before we start.
 */
-   assert(image->mt->logical_depth0 == 1);
+   if (image->mt->surf.size > 0) {
+  assert(image->mt->surf.logical_level0_px.depth == 1);
+  assert(image->mt->surf.logical_level0_px.array_len == 1);
+   } else {
+  assert(image->mt->logical_depth0 == 1);
+   }
intel_miptree_access_raw(brw, image->mt, level, 0, true);
 
bo = image->mt->bo;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c 
b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index e686ba93d2..88cfa814a3 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -150,7 +150,13 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx,
/* Since we are going to write raw data to the miptree, we need to resolve
 * any pending fast color clears before we start.
 */
-   assert(image->mt->logical_depth0 == 1);
+   if (image->mt->surf.size > 0) {
+  assert(image->mt->surf.logical_level0_px.depth == 1);
+  assert(image->mt->surf.logical_level0_px.array_len == 1);
+   } else {
+  assert(image->mt->logical_depth0 == 1);
+   }
+
intel_miptree_access_raw(brw, image->mt, level, 0, true);
 
bo = image->mt->bo;
-- 
2.11.0

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[Mesa-dev] [PATCH 13/22] i965/fbo: Add support for isl-based miptrees in rb wrapper

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_fbo.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 1fa40bb5c9..fee4b6fa8c 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -540,6 +540,10 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
   irb->layer_count = 1;
} else if (mt->target != GL_TEXTURE_3D && image->TexObject->NumLayers > 0) {
   irb->layer_count = image->TexObject->NumLayers;
+   } else if (mt->surf.size > 0) {
+  irb->layer_count = mt->surf.dim == ISL_SURF_DIM_3D ?
+minify(mt->surf.logical_level0_px.depth, level) :
+mt->surf.logical_level0_px.array_len;
} else {
   irb->layer_count = mt->level[level].depth / layer_multiplier;
}
-- 
2.11.0

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[Mesa-dev] [PATCH 08/22] i965/wm: Prepare image surfaces for isl based

[Topi Pohjolainen]

There is a functional change: Before update_image_surface() didn't
shift the number of layers for 3D, now it does like
update_texture_image_param() did.

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 22 +++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index ab6b9cdd29..a8c40d54d8 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1632,6 +1632,23 @@ update_buffer_image_param(struct brw_context *brw,
param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
 }
 
+static unsigned
+get_image_num_layers(const struct intel_mipmap_tree *mt, GLenum target,
+ unsigned level)
+{
+   if (target == GL_TEXTURE_CUBE_MAP)
+  return 6;
+
+   if (mt->surf.size > 0) {
+  return target == GL_TEXTURE_3D ?
+ minify(mt->surf.logical_level0_px.depth, level) :
+ mt->surf.logical_level0_px.array_len;
+   }
+
+   return target == GL_TEXTURE_3D ?
+  minify(mt->logical_depth0, level) : mt->logical_depth0;
+}
+
 static void
 update_image_surface(struct brw_context *brw,
  struct gl_image_unit *u,
@@ -1660,9 +1677,8 @@ update_image_surface(struct brw_context *brw,
   } else {
  struct intel_texture_object *intel_obj = intel_texture_object(obj);
  struct intel_mipmap_tree *mt = intel_obj->mt;
- const unsigned num_layers = (!u->Layered ? 1 :
-  obj->Target == GL_TEXTURE_CUBE_MAP ? 6 :
-  mt->logical_depth0);
+ const unsigned num_layers = u->Layered ?
+get_image_num_layers(mt, obj->Target, u->Level) : 1;
 
  struct isl_view view = {
 .format = format,
-- 
2.11.0

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[Mesa-dev] [PATCH 15/22] i965/miptree: Prepare compressed offsets for isl based

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a0b129adb4..1b8c0da80d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1462,6 +1462,15 @@ intel_miptree_get_image_offset(const struct 
intel_mipmap_tree *mt,
   isl_surf_get_image_offset_sa(&mt->surf, level, slice, z,
&x_offset_sa, &y_offset_sa);
 
+  /* In case of compressed formats offsets are expected as blocks. */
+  if (mt->compressed) {
+ const struct isl_format_layout *fmtl =
+isl_format_get_layout(mt->surf.format);
+
+ x_offset_sa /= fmtl->bw;
+ y_offset_sa /= fmtl->bh;
+  }
+
   *x = x_offset_sa;
   *y = y_offset_sa;
   return;
-- 
2.11.0

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[Mesa-dev] [PATCH 04/22] i965/miptree: Switch to isl_surf::row_pitch

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_misc_state.c   |  2 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
 src/mesa/drivers/dri/i965/gen6_depth_state.c |  2 +-
 src/mesa/drivers/dri/i965/gen7_misc_state.c  |  4 +-
 src/mesa/drivers/dri/i965/gen8_depth_state.c |  4 +-
 src/mesa/drivers/dri/i965/intel_blit.c   | 13 +++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 54 +---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h| 11 -
 src/mesa/drivers/dri/i965/intel_pixel_bitmap.c   |  2 +-
 src/mesa/drivers/dri/i965/intel_pixel_read.c |  2 +-
 src/mesa/drivers/dri/i965/intel_screen.c |  4 +-
 src/mesa/drivers/dri/i965/intel_tex_image.c  |  8 ++--
 src/mesa/drivers/dri/i965/intel_tex_subimage.c   |  2 +-
 13 files changed, 52 insertions(+), 58 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index b0e63347ad..0c43d2b4b2 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -380,7 +380,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
 
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
-   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
+   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
  (depthbuffer_format << 18) |
  (BRW_TILEWALK_YMAJOR << 26) |
  ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 5e4b4d626e..ab6b9cdd29 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1034,7 +1034,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
  (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 
surf[3] = (brw_get_surface_tiling_bits(mt->surf.tiling) |
- (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
+ (mt->surf.row_pitch - 1) << BRW_SURFACE_PITCH_SHIFT);
 
surf[4] = brw_get_surface_num_multisamples(mt->surf.samples);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index e042fc747e..8f05b4cc1a 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -116,7 +116,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 
/* 3DSTATE_DEPTH_BUFFER dw1 */
-   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
+   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
  (depthbuffer_format << 18) |
  ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
  ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c 
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 6c69fa8ba5..43422900e2 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -105,7 +105,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 
/* 3DSTATE_DEPTH_BUFFER dw1 */
-   OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
+   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
  (depthbuffer_format << 18) |
  ((hiz ? 1 : 0) << 22) |
  ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) |
@@ -182,7 +182,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
*/
   OUT_BATCH(enabled |
 mocs << 25 |
-   (2 * stencil_mt->pitch - 1));
+   (2 * stencil_mt->surf.row_pitch - 1));
   OUT_RELOC(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c 
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 52c6dd0787..9cb0d07688 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -67,7 +67,7 @@ emit_depth_packets(struct brw_context *brw,
  (stencil_mt != NULL && stencil_writable) << 27 |
  (hiz ? 1 : 0) << 22 |
  depthbuffer_format << 18 |
- (depth_mt ? depth_mt->pitch - 1 : 0));
+ (depth_mt ? depth_mt->surf.row_pitch - 1 : 0));
if (depth_mt) {
   OUT_RELOC64(depth_mt->bo,
   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
@@ -126,7 +126,7 @@ emit_depth_packets(struct brw_context *brw,
* indicate that it does.
*/
   OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
-(2 * stencil_mt->pitch - 1));
+(2 * stencil_mt->surf.row_pitch - 1));
   OUT_RELOC64(stencil_mt->bo,
   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_REND

[Mesa-dev] [PATCH 03/22] i965/miptree: Switch to isl_surf::tiling

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_misc_state.c   |  8 +--
 src/mesa/drivers/dri/i965/brw_tex_layout.c   | 28 
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 10 +--
 src/mesa/drivers/dri/i965/gen6_depth_state.c |  2 +-
 src/mesa/drivers/dri/i965/intel_blit.c   | 54 +++---
 src/mesa/drivers/dri/i965/intel_blit.h   | 21 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 90 +++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h| 15 ++--
 src/mesa/drivers/dri/i965/intel_pixel_bitmap.c   |  2 +-
 src/mesa/drivers/dri/i965/intel_pixel_read.c |  8 +--
 src/mesa/drivers/dri/i965/intel_screen.c |  7 +-
 src/mesa/drivers/dri/i965/intel_tex_image.c  |  8 +--
 src/mesa/drivers/dri/i965/intel_tex_subimage.c   |  8 +--
 src/mesa/drivers/dri/i965/intel_tiled_memcpy.c   | 12 ++--
 src/mesa/drivers/dri/i965/intel_tiled_memcpy.h   |  4 +-
 15 files changed, 144 insertions(+), 133 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index e9b3b06421..b0e63347ad 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -143,7 +143,7 @@ rebase_depth_stencil(struct brw_context *brw, struct 
intel_renderbuffer *irb,
struct gl_context *ctx = &brw->ctx;
uint32_t tile_mask_x = 0, tile_mask_y = 0;
 
-   intel_get_tile_masks(irb->mt->tiling, irb->mt->cpp,
+   intel_get_tile_masks(irb->mt->surf.tiling, irb->mt->cpp,
 &tile_mask_x, &tile_mask_y);
assert(!intel_miptree_level_has_hiz(irb->mt, irb->mt_level));
 
@@ -306,8 +306,8 @@ brw_emit_depthbuffer(struct brw_context *brw)
   /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
   assert(brw->gen >= 7 || !separate_stencil || hiz);
 
-  assert(brw->gen < 6 || depth_mt->tiling == I915_TILING_Y);
-  assert(!hiz || depth_mt->tiling == I915_TILING_Y);
+  assert(brw->gen < 6 || depth_mt->surf.tiling == ISL_TILING_Y0);
+  assert(!hiz || depth_mt->surf.tiling == ISL_TILING_Y0);
 
   depthbuffer_format = brw_depthbuffer_format(brw);
   depth_surface_type = BRW_SURFACE_2D;
@@ -383,7 +383,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((depth_mt ? depth_mt->pitch - 1 : 0) |
  (depthbuffer_format << 18) |
  (BRW_TILEWALK_YMAJOR << 26) |
- ((depth_mt ? depth_mt->tiling != I915_TILING_NONE : 1)
+ ((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
   << 27) |
  (depth_surface_type << 29));
 
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 5be73282dc..f3b5a17c88 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -494,7 +494,7 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
 /**
  * \brief Helper function for intel_miptree_create().
  */
-static uint32_t
+static enum isl_tiling
 brw_miptree_choose_tiling(struct brw_context *brw,
   const struct intel_mipmap_tree *mt,
   uint32_t layout_flags)
@@ -503,7 +503,7 @@ brw_miptree_choose_tiling(struct brw_context *brw,
   /* The stencil buffer is W tiled. However, we request from the kernel a
* non-tiled buffer because the GTT is incapable of W fencing.
*/
-  return I915_TILING_NONE;
+  return ISL_TILING_LINEAR;
}
 
/* Do not support changing the tiling for miptrees with pre-allocated BOs. 
*/
@@ -516,9 +516,9 @@ brw_miptree_choose_tiling(struct brw_context *brw,
case MIPTREE_LAYOUT_TILING_ANY:
   break;
case MIPTREE_LAYOUT_TILING_Y:
-  return I915_TILING_Y;
+  return ISL_TILING_Y0;
case MIPTREE_LAYOUT_TILING_NONE:
-  return I915_TILING_NONE;
+  return ISL_TILING_LINEAR;
}
 
if (mt->surf.samples > 1) {
@@ -534,36 +534,36 @@ brw_miptree_choose_tiling(struct brw_context *brw,
* and another buffer, and the blitting engine doesn't support that.
* So use Y tiling, since it makes better use of the cache.
*/
-  return I915_TILING_Y;
+  return ISL_TILING_Y0;
}
 
GLenum base_format = _mesa_get_format_base_format(mt->format);
if (base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL_EXT)
-  return I915_TILING_Y;
+  return ISL_TILING_Y0;
 
/* 1D textures (and 1D array textures) don't get any benefit from tiling,
 * in fact it leads to a less efficient use of memory space and bandwidth
 * due to tile alignment.
 */
if (mt->logical_height0 == 1)
-  return I915_TILING_NONE;
+  return ISL_TILING_LINEAR;
 
int minimum_pitch = mt->total_width * mt->cpp;
 
/* If the width is much smaller than a tile, don't bother tiling. */
if (minimum_pitch < 64)
-  return I915_TILING_NONE;
+  return ISL

[Mesa-dev] [PATCH 06/22] i965: Prepare blit engine for isl based miptrees

[Topi Pohjolainen]

v2: Do not concern cpp, pitch and tiling which are already
transitioned.

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_blit.c | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index a6f7aee32f..476cc5 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -328,11 +328,17 @@ intel_miptree_blit(struct brw_context *brw,
intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
 
-   if (src_flip)
-  src_y = minify(src_mt->physical_height0, src_level - 
src_mt->first_level) - src_y - height;
-
-   if (dst_flip)
-  dst_y = minify(dst_mt->physical_height0, dst_level - 
dst_mt->first_level) - dst_y - height;
+   if (src_flip) {
+  const unsigned h0 = src_mt->surf.size > 0 ?
+ src_mt->surf.phys_level0_sa.height : src_mt->physical_height0;
+  src_y = minify(h0, src_level - src_mt->first_level) - src_y - height;
+   }
+ 
+   if (dst_flip) {
+  const unsigned h0 = dst_mt->surf.size > 0 ?
+ dst_mt->surf.phys_level0_sa.height : dst_mt->physical_height0;
+  dst_y = minify(h0, dst_level - dst_mt->first_level) - dst_y - height;
+   }
 
uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
intel_miptree_get_image_offset(src_mt, src_level, src_slice,
-- 
2.11.0

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[Mesa-dev] [PATCH 12/22] i965: Prepare image setup from miptree for isl based

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 7a92ef601b..9c74d2aa54 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -412,8 +412,15 @@ intel_setup_image_from_mipmap_tree(struct brw_context 
*brw, __DRIimage *image,
 
intel_miptree_check_level_layer(mt, level, zoffset);
 
-   image->width = minify(mt->physical_width0, level - mt->first_level);
-   image->height = minify(mt->physical_height0, level - mt->first_level);
+   if (mt->surf.size > 0) {
+  image->width = minify(mt->surf.phys_level0_sa.width,
+level - mt->first_level);
+  image->height = minify(mt->surf.phys_level0_sa.height,
+ level - mt->first_level);
+   } else {
+  image->width = minify(mt->physical_width0, level - mt->first_level);
+  image->height = minify(mt->physical_height0, level - mt->first_level);
+   }
image->pitch = mt->surf.row_pitch;
 
image->offset = intel_miptree_get_tile_offsets(mt, level, zoffset,
-- 
2.11.0

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[Mesa-dev] [PATCH 11/22] i965: Prepare tex, img and rt state emission for isl based miptrees

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 21 -
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 3f2ca82fdb..45ac106f3f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -80,9 +80,13 @@ get_isl_surf(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
  uint32_t *tile_x, uint32_t *tile_y,
  uint32_t *offset, struct isl_surf *surf)
 {
-   intel_miptree_get_isl_surf(brw, mt, surf);
+   if (mt->surf.size > 0) {
+  *surf = mt->surf;
+   } else {
+  intel_miptree_get_isl_surf(brw, mt, surf);
 
-   surf->dim = get_isl_surf_dim(target);
+  surf->dim = get_isl_surf_dim(target);
+   }
 
const enum isl_dim_layout dim_layout =
   get_isl_dim_layout(&brw->screen->devinfo, mt->surf.tiling, target,
@@ -553,9 +557,16 @@ brw_update_texture_surface(struct gl_context *ctx,
   /* If this is a view with restricted NumLayers, then our effective depth
* is not just the miptree depth.
*/
-  const unsigned view_num_layers =
- (obj->Immutable && obj->Target != GL_TEXTURE_3D) ? obj->NumLayers :
-mt->logical_depth0;
+  unsigned view_num_layers;
+  if (obj->Immutable && obj->Target != GL_TEXTURE_3D) {
+ view_num_layers = obj->NumLayers;
+  } else if (mt->surf.size > 0) {
+ view_num_layers = mt->surf.dim == ISL_SURF_DIM_3D ?
+  mt->surf.logical_level0_px.depth :
+  mt->surf.logical_level0_px.array_len;
+  } else {
+ view_num_layers = mt->logical_depth0;
+  }
 
   /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
* texturing functions that return a float, as our code generation always
-- 
2.11.0

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[Mesa-dev] i965: Transition depth and stencil surfaces to isl

[Topi Pohjolainen]

First four patches are mechanical replacing intel_mipmap_tree native
members with equivalent found in intel_mipmap_tree::surf. This helps
to reduce back and forth churn, i.e., helps to avoid number of
"if (mt->surf.size > 0)"-conditionals that would get dropped in the
end. Assumption is that this mixed used of intel_mipmap_tree::surf
and native would be short lived.

Patch number five is of the same nature - it helps to re-use current
logic without checks for isl. Once all surfaces are transitioned it
is pretty easy to drop intel_mipmap_tree::cpp (we might even decide
to keep it instead of calculating it on-demand).

Patches 6-15, 18 and 19 in turn introduce conditional
"if (mt->surf.size)" blocks that can't be trivially avoided. I
considered using isl_surf::logical_level0_px/phys_level0_sa instead
of native intel_mipmap_tree equivalent but that gets a lot more
complicated than simply introducing the conditional blocks that one
removes in the end.
These patches pave the way quite a bit also for color surfaces.

Patches 16 and 17 switch stencil surfaces to isl and finally the last
does the same for depth surfaces.

Topi Pohjolainen (22):
  i965/miptree: Switch to isl_surf::msaa_layout
  i965/miptree: Switch to isl_surf::samples
  i965/miptree: Switch to isl_surf::tiling
  i965/miptree: Switch to isl_surf::row_pitch
  i965/miptree: Store chars-per-pixel even for isl based
  i965: Prepare blit engine for isl based miptrees
  i965/miptree: Prepare intel_miptree_copy() for isl based
  i965/wm: Prepare image surfaces for isl based
  i965: Prepare tex (sub)image for isl based
  i965: Refactor miptree to isl converter and adjustment
  i965: Prepare tex, img and rt state emission for isl based miptrees
  i965: Prepare image setup from miptree for isl based
  i965/fbo: Add support for isl-based miptrees in rb wrapper
  i965/miptree: Add support for imported bo offsets for isl based
  i965/miptree: Prepare compressed offsets for isl based
  i965/miptree: Represent w-tiled stencil surfaces with isl
  i965/miptree: Represent y-tiled stencil copies with isl
  i965/miptree: Prepare aux state map for isl based
  i965/miptree: Prepare 3D surfaces with physical 2D layout
  intel/isl/gen4: Represent cube maps with 3D layout
  i965: Drop redundant check for non-tiled depth buffer
  i965: Represent depth surfaces with isl

 src/intel/isl/isl.c  |  40 +-
 src/mesa/drivers/dri/i965/brw_blorp.c|  19 +-
 src/mesa/drivers/dri/i965/brw_clear.c|   5 +-
 src/mesa/drivers/dri/i965/brw_context.c  |   2 +-
 src/mesa/drivers/dri/i965/brw_meta_util.c|   2 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c   |  11 +-
 src/mesa/drivers/dri/i965/brw_tex_layout.c   |  41 +-
 src/mesa/drivers/dri/i965/brw_wm.c   |   6 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 154 ---
 src/mesa/drivers/dri/i965/gen6_depth_state.c |   5 +-
 src/mesa/drivers/dri/i965/gen7_misc_state.c  |  22 +-
 src/mesa/drivers/dri/i965/gen8_depth_state.c |  31 +-
 src/mesa/drivers/dri/i965/intel_blit.c   | 107 +++--
 src/mesa/drivers/dri/i965/intel_blit.h   |  21 +-
 src/mesa/drivers/dri/i965/intel_fbo.c|  19 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 505 +--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  81 +---
 src/mesa/drivers/dri/i965/intel_pixel_bitmap.c   |   4 +-
 src/mesa/drivers/dri/i965/intel_pixel_copy.c |   2 +-
 src/mesa/drivers/dri/i965/intel_pixel_read.c |  10 +-
 src/mesa/drivers/dri/i965/intel_screen.c |  22 +-
 src/mesa/drivers/dri/i965/intel_tex_image.c  |  36 +-
 src/mesa/drivers/dri/i965/intel_tex_subimage.c   |  18 +-
 src/mesa/drivers/dri/i965/intel_tiled_memcpy.c   |  12 +-
 src/mesa/drivers/dri/i965/intel_tiled_memcpy.h   |   4 +-
 25 files changed, 637 insertions(+), 542 deletions(-)

-- 
2.11.0

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[Mesa-dev] [PATCH 07/22] i965/miptree: Prepare intel_miptree_copy() for isl based

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_blit.c | 20 
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 476cc5..68e9c1ad16 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -406,10 +406,22 @@ intel_miptree_copy(struct brw_context *brw,
*/
   assert(src_x % bw == 0);
   assert(src_y % bh == 0);
-  assert(src_width % bw == 0 ||
- src_x + src_width == minify(src_mt->logical_width0, src_level));
-  assert(src_height % bh == 0 ||
- src_y + src_height == minify(src_mt->logical_height0, src_level));
+
+  if (src_mt->surf.size > 0) {
+ assert(src_width % bw == 0 ||
+src_x + src_width ==
+minify(src_mt->surf.logical_level0_px.width, src_level));
+ assert(src_height % bh == 0 ||
+src_y + src_height ==
+minify(src_mt->surf.logical_level0_px.height, src_level));
+  } else {
+ assert(src_width % bw == 0 ||
+src_x + src_width ==
+minify(src_mt->logical_width0, src_level));
+ assert(src_height % bh == 0 ||
+src_y + src_height ==
+minify(src_mt->logical_height0, src_level));
+  }
 
   src_x /= (int)bw;
   src_y /= (int)bh;
-- 
2.11.0

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[Mesa-dev] [PATCH 01/22] i965/miptree: Switch to isl_surf::msaa_layout

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c |  3 +-
 src/mesa/drivers/dri/i965/brw_tex_layout.c|  9 ++-
 src/mesa/drivers/dri/i965/brw_wm.c|  2 +-
 src/mesa/drivers/dri/i965/intel_fbo.c | 13 +---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 85 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 49 ---
 6 files changed, 30 insertions(+), 131 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 11f2fae380..be310de85b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -134,8 +134,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
unsigned start_layer, unsigned num_layers,
struct isl_surf tmp_surfs[1])
 {
-   if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
-   mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+   if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
   const unsigned num_samples = MAX2(1, mt->num_samples);
   for (unsigned i = 0; i < num_layers; i++) {
  for (unsigned s = 0; s < num_samples; s++) {
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index c76e87bc06..91e94ee4a0 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -625,13 +625,12 @@ intel_miptree_set_total_width_height(struct brw_context 
*brw,
   break;
 
default:
-  switch (mt->msaa_layout) {
-  case INTEL_MSAA_LAYOUT_UMS:
-  case INTEL_MSAA_LAYOUT_CMS:
+  switch (mt->surf.msaa_layout) {
+  case ISL_MSAA_LAYOUT_ARRAY:
  brw_miptree_layout_texture_array(brw, mt);
  break;
-  case INTEL_MSAA_LAYOUT_NONE:
-  case INTEL_MSAA_LAYOUT_IMS:
+  case ISL_MSAA_LAYOUT_NONE:
+  case ISL_MSAA_LAYOUT_INTERLEAVED:
  if (gen9_use_linear_1d_layout(brw, mt))
 gen9_miptree_layout_1d(mt);
  else if (mt->array_layout == GEN6_HIZ_STENCIL)
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index 18056d51d0..9e1dcee8fd 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -400,7 +400,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
 assert(brw->gen >= 7);
 assert(intel_tex->mt->num_samples > 1);
 assert(intel_tex->mt->mcs_buf);
-assert(intel_tex->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS);
+assert(intel_tex->mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
 key->compressed_multisample_layout_mask |= 1 << s;
 
 if (intel_tex->mt->num_samples >= 16) {
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index a73ca59946..3ac6892ea0 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -532,16 +532,9 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
irb->mt_level = level;
irb->mt_layer = layer;
 
-   int layer_multiplier;
-   switch (mt->msaa_layout) {
-  case INTEL_MSAA_LAYOUT_UMS:
-  case INTEL_MSAA_LAYOUT_CMS:
- layer_multiplier = MAX2(mt->num_samples, 1);
- break;
-
-  default:
- layer_multiplier = 1;
-   }
+   const unsigned layer_multiplier = 
+  mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY ?
+  MAX2(mt->num_samples, 1) : 1;
 
if (!layered) {
   irb->layer_count = 1;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f292d71d38..8e241b8462 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -101,42 +101,22 @@ is_mcs_supported(const struct brw_context *brw, 
mesa_format format,
  * Determine which MSAA layout should be used by the MSAA surface being
  * created, based on the chip generation and the surface type.
  */
-static enum intel_msaa_layout
+static enum isl_msaa_layout
 compute_msaa_layout(struct brw_context *brw, mesa_format format,
 uint32_t layout_flags)
 {
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
-  return INTEL_MSAA_LAYOUT_IMS;
+  return ISL_MSAA_LAYOUT_INTERLEAVED;
 
/* In Gen7, IMS layout is only used for depth and stencil buffers. */
switch (_mesa_get_format_base_format(format)) {
case GL_DEPTH_COMPONENT:
case GL_STENCIL_INDEX:
case GL_DEPTH_STENCIL:
-  return INTEL_MSAA_LAYOUT_IMS;
+  return ISL_MSAA_LAYOUT_INTERLEAVED;
default:
-  /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
-   *
-   *   This field must be set to 0 for all SINT MSRTs when all RT channels
-   *   are not written
-   *
-   * In practice this means that we have to disable MCS for all signed
-   * integer MSAA buffers.  The alt

[Mesa-dev] [PATCH 02/22] i965/miptree: Switch to isl_surf::samples

[Topi Pohjolainen]

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c| 16 -
 src/mesa/drivers/dri/i965/brw_context.c  |  2 +-
 src/mesa/drivers/dri/i965/brw_meta_util.c|  2 +-
 src/mesa/drivers/dri/i965/brw_tex_layout.c   |  4 +--
 src/mesa/drivers/dri/i965/brw_wm.c   |  4 +--
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
 src/mesa/drivers/dri/i965/intel_blit.c   |  4 +--
 src/mesa/drivers/dri/i965/intel_fbo.c|  4 +--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 46 
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  6 
 src/mesa/drivers/dri/i965/intel_pixel_copy.c |  2 +-
 11 files changed, 43 insertions(+), 49 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index be310de85b..be0d41b04a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -135,7 +135,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
struct isl_surf tmp_surfs[1])
 {
if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
-  const unsigned num_samples = MAX2(1, mt->num_samples);
+  const unsigned num_samples = MAX2(1, mt->surf.samples);
   for (unsigned i = 0; i < num_layers; i++) {
  for (unsigned s = 0; s < num_samples; s++) {
 const unsigned phys_layer = (start_layer + i) * num_samples + s;
@@ -275,7 +275,7 @@ swizzle_to_scs(GLenum swizzle)
  * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
  * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
  * the physical layer holding sample 0.  So, for example, if
- * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
+ * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
  * 4*n.
  */
 void
@@ -296,9 +296,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
"to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
__func__,
-   src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
+   src_mt->surf.samples, _mesa_get_format_name(src_mt->format), src_mt,
src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
-   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
+   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format), dst_mt,
dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
mirror_x, mirror_y);
 
@@ -318,7 +318,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
 * R32_FLOAT, so only the contents of the red channel matters.
 */
if (brw->gen == 6 &&
-   src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
+   src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1 &&
src_mt->format == dst_mt->format &&
(dst_format == MESA_FORMAT_L_FLOAT32 ||
 dst_format == MESA_FORMAT_I_FLOAT32)) {
@@ -375,9 +375,9 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
"to %dx %s mt %p %d %d (%d,%d)\n",
__func__,
-   src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
+   src_mt->surf.samples, _mesa_get_format_name(src_mt->format), src_mt,
src_level, src_layer, src_x, src_y, src_width, src_height,
-   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
+   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format), dst_mt,
dst_level, dst_layer, dst_x, dst_y);
 
struct isl_surf tmp_surfs[2];
@@ -564,7 +564,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
struct intel_mipmap_tree *dst_mt = intel_image->mt;
 
/* There is support for only up to eight samples. */
-   if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
+   if (src_mt->surf.samples > 8 || dst_mt->surf.samples > 8)
   return false;
 
if (_mesa_get_format_base_format(src_rb->Format) !=
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index bd26e2332c..fffe310b97 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1218,7 +1218,7 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
   rb = intel_get_renderbuffer(fb, buffers[i]);
   if (rb == NULL || rb->mt == NULL)
  continue;
-  if (rb->mt->num_samples <= 1) {
+  if (rb->mt->surf.samples <= 1) {
  assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
 rb->layer_count == 1);
  intel_miptree_prepare_access(brw, rb->mt, 0, 1, 0, 1, false, false);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index f9fd350918..2d87885e90 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -298,7 +298,7 @@ brw_is_color_fast_clear_compatibl

[Mesa-dev] [PATCH 05/22] i965/miptree: Store chars-per-pixel even for isl based

[Topi Pohjolainen]

This will significantly reduce chrun when switching remaaining
surface types to isl. After the full transition it will be easier
to calculate on-demand and drop the helper member in miptree.

Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f113ded7cd..879036ce77 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -796,6 +796,7 @@ make_surface(struct brw_context *brw, GLenum target, 
mesa_format format,
mt->target = target;
mt->format = format;
mt->aux_state = NULL;
+   mt->cpp = isl_format_get_layout(mt->surf.format)->bpb / 8;
 
return mt;
 
-- 
2.11.0

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Re: [Mesa-dev] [PATCH 4/4] dri: Add KHR_no_error toggle to driconf

[Grigori Goronzy]

On 2017-07-17 19:21, Emil Velikov wrote:

On 13 July 2017 at 12:09, Grigori Goronzy  wrote:

On 2017-07-12 15:15, Emil Velikov wrote:


As mentioned in earlier commit no_error should be device agnostic.
Hence removing the st/dri bits and adding a DRI_CONF_MESA_NO_ERROR()
line next to DRI_CONF_VBLANK_MODE seems like the better solution.



Hm, driconf overrides are typically set per screen and/or driver, so 
that
won't work. The overrides will be ignored because of screen/driver 
mismatch.
So I think it needs to be implemented separately for each classic 
driver.

I'll keep this part to the Gallium state tracker for now.


Hmm my understanding was completely different. Have you tested my
suggestion or this is your assumption?



Sure, I have tested this. Check where driParseConfigFiles() is used in 
the code. Different parts of the stack have completely separate driconf 
databases, which are associated with different "driver names" (in 
quotes, because it's a rather confusing description, given the usage). 
The generic DRI layer that handles vblank_mode uses "dri2" as "driver 
name". Other parts have other different "driver names", all of which 
aren't obvious or documented, and most of the classic Mesa drivers also 
have separate driconf databases. So I added mesa_no_error to the generic 
DRI layer, but it only produced any result when an option is added to a 
"dri2" section of the driconf XML, which makes it somewhat strange and 
impractical to use. Of course vblank_mode has the same issue. I think 
this isn't really a good design and should be addressed at same point. 
Maybe it could be a good option to move to a single global database, or 
a hierarchical database (somewhat like LDAP). There are various possible 
options.


At this time, for practical reasons, I think it makes sense to add the 
mesa_no_error flag at the graphics driver layer only. That makes it easy 
to override this setting with the "driconf" GUI tool and there is no 
obscure "driver name" magic going on that users should not need to know 
about.


Grigori
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[Mesa-dev] [PATCH] egl/dri2: remove unused buffer_count variable

[Gwan-gyeong Mun]

It removes unused buffer_count variable from dri2_egl_surface.
And it polishes the assert of dri2_drm_get_buffers_with_format().

Signed-off-by: Mun Gwan-gyeong 
---
 src/egl/drivers/dri2/egl_dri2.h | 1 -
 src/egl/drivers/dri2/platform_android.c | 5 +
 src/egl/drivers/dri2/platform_drm.c | 3 +--
 src/egl/drivers/dri2/platform_x11.c | 1 -
 4 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index 5b3e93abe0..a8133e0e50 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -246,7 +246,6 @@ struct dri2_egl_surface
_EGLSurface  base;
__DRIdrawable   *dri_drawable;
__DRIbuffer  buffers[5];
-   int  buffer_count;
bool have_fake_front;
 
 #ifdef HAVE_X11_PLATFORM
diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 13006fee87..300e2d9dbf 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -1003,16 +1003,13 @@ droid_get_buffers_with_format(__DRIdrawable * 
driDrawable,
if (update_buffers(dri2_surf) < 0)
   return NULL;
 
-   dri2_surf->buffer_count =
-  droid_get_buffers_parse_attachments(dri2_surf, attachments, count);
+   *out_count = droid_get_buffers_parse_attachments(dri2_surf, attachments, 
count);
 
if (width)
   *width = dri2_surf->base.Width;
if (height)
   *height = dri2_surf->base.Height;
 
-   *out_count = dri2_surf->buffer_count;
-
return dri2_surf->buffers;
 }
 
diff --git a/src/egl/drivers/dri2/platform_drm.c 
b/src/egl/drivers/dri2/platform_drm.c
index 8e12aed0b3..aa3937581a 100644
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl/drivers/dri2/platform_drm.c
@@ -321,10 +321,9 @@ dri2_drm_get_buffers_with_format(__DRIdrawable 
*driDrawable,
struct dri2_egl_surface *dri2_surf = loaderPrivate;
int i, j;
 
-   dri2_surf->buffer_count = 0;
for (i = 0, j = 0; i < 2 * count; i += 2, j++) {
   assert(attachments[i] < __DRI_BUFFER_COUNT);
-  assert(dri2_surf->buffer_count < 5);
+  assert(j < ARRAY_SIZE(dri2_surf->buffers));
 
   switch (attachments[i]) {
   case __DRI_BUFFER_BACK_LEFT:
diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index c10cd84fce..b01f739010 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -445,7 +445,6 @@ dri2_x11_process_buffers(struct dri2_egl_surface *dri2_surf,
   dri2_egl_display(dri2_surf->base.Resource.Display);
xcb_rectangle_t rectangle;
 
-   dri2_surf->buffer_count = count;
dri2_surf->have_fake_front = false;
 
/* This assumes the DRI2 buffer attachment tokens matches the
-- 
2.13.3

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Re: [Mesa-dev] [PATCH] radeonsi: add back the USE_MININUM_PRIORITY flag to the low-prio compiler queue

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 07/17/2017 11:56 PM, Marek Olšák wrote:

From: Marek Olšák 

Accidentally removed in 9f320e0a387a1009c5218daf130b3b754a3c2800.
---
  src/gallium/drivers/radeonsi/si_pipe.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 4df60b6..0bc3002 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -964,21 +964,22 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
 32, num_compiler_threads,
 UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
si_destroy_shader_cache(sscreen);
FREE(sscreen);
return NULL;
}
  
  	if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,

 "si_shader_low",
 32, num_compiler_threads,
-UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
+UTIL_QUEUE_INIT_RESIZE_IF_FULL |
+UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
   si_destroy_shader_cache(sscreen);
   FREE(sscreen);
   return NULL;
}
  
  	si_handle_env_var_force_family(sscreen);
  
  	if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))

si_init_perfcounters(sscreen);
  


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[Mesa-dev] [v2 8/16] i965/wm: Use isl for filling tex image parameters

[Topi Pohjolainen]

This helps to drop dependency to miptree::total_height which is
used in brw_miptree_get_vertical_slice_pitch().

CC: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c   |   2 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 100 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|   9 --
 3 files changed, 19 insertions(+), 92 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index d06d654797..c76e87bc06 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -309,7 +309,7 @@ brw_miptree_get_horizontal_slice_pitch(const struct 
brw_context *brw,
}
 }
 
-unsigned
+static unsigned
 brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw,
  const struct intel_mipmap_tree *mt,
  unsigned level)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index da5c5128c1..d88a2fb2be 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1633,73 +1633,6 @@ update_buffer_image_param(struct brw_context *brw,
 }
 
 static void
-update_texture_image_param(struct brw_context *brw,
-   struct gl_image_unit *u,
-   unsigned surface_idx,
-   struct brw_image_param *param)
-{
-   struct intel_mipmap_tree *mt = intel_texture_object(u->TexObj)->mt;
-
-   update_default_image_param(brw, u, surface_idx, param);
-
-   param->size[0] = minify(mt->logical_width0, u->Level);
-   param->size[1] = minify(mt->logical_height0, u->Level);
-   param->size[2] = (!u->Layered ? 1 :
- u->TexObj->Target == GL_TEXTURE_CUBE_MAP ? 6 :
- u->TexObj->Target == GL_TEXTURE_3D ?
- minify(mt->logical_depth0, u->Level) :
- mt->logical_depth0);
-
-   intel_miptree_get_image_offset(mt, u->Level, u->_Layer,
-  ¶m->offset[0],
-  ¶m->offset[1]);
-
-   param->stride[0] = mt->cpp;
-   param->stride[1] = mt->pitch / mt->cpp;
-   param->stride[2] =
-  brw_miptree_get_horizontal_slice_pitch(brw, mt, u->Level);
-   param->stride[3] =
-  brw_miptree_get_vertical_slice_pitch(brw, mt, u->Level);
-
-   if (mt->tiling == I915_TILING_X) {
-  /* An X tile is a rectangular block of 512x8 bytes. */
-  param->tiling[0] = _mesa_logbase2(512 / mt->cpp);
-  param->tiling[1] = _mesa_logbase2(8);
-
-  if (brw->has_swizzling) {
- /* Right shifts required to swizzle bits 9 and 10 of the memory
-  * address with bit 6.
-  */
- param->swizzling[0] = 3;
- param->swizzling[1] = 4;
-  }
-   } else if (mt->tiling == I915_TILING_Y) {
-  /* The layout of a Y-tiled surface in memory isn't really fundamentally
-   * different to the layout of an X-tiled surface, we simply pretend that
-   * the surface is broken up in a number of smaller 16Bx32 tiles, each
-   * one arranged in X-major order just like is the case for X-tiling.
-   */
-  param->tiling[0] = _mesa_logbase2(16 / mt->cpp);
-  param->tiling[1] = _mesa_logbase2(32);
-
-  if (brw->has_swizzling) {
- /* Right shift required to swizzle bit 9 of the memory address with
-  * bit 6.
-  */
- param->swizzling[0] = 3;
-  }
-   }
-
-   /* 3D textures are arranged in 2D in memory with 2^lod slices per row.  The
-* address calculation algorithm (emit_address_calculation() in
-* brw_fs_surface_builder.cpp) handles this as a sort of tiling with
-* modulus equal to the LOD.
-*/
-   param->tiling[2] = (u->TexObj->Target == GL_TEXTURE_3D ? u->Level :
-   0);
-}
-
-static void
 update_image_surface(struct brw_context *brw,
  struct gl_image_unit *u,
  GLenum access,
@@ -1727,6 +1660,19 @@ update_image_surface(struct brw_context *brw,
   } else {
  struct intel_texture_object *intel_obj = intel_texture_object(obj);
  struct intel_mipmap_tree *mt = intel_obj->mt;
+ const unsigned num_layers = (!u->Layered ? 1 :
+  obj->Target == GL_TEXTURE_CUBE_MAP ? 6 :
+  mt->logical_depth0);
+
+ struct isl_view view = {
+.format = format,
+.base_level = obj->MinLevel + u->Level,
+.levels = 1,
+.base_array_layer = obj->MinLayer + u->_Layer,
+.array_len = num_layers,
+.swizzle = ISL_SWIZZLE_IDENTITY,
+.usage = ISL_SURF_USAGE_STORAGE_BIT,
+ };
 
  if (format == ISL_FORMAT_RAW) {
 brw_emit_buffer_surface_state(
@@ -1735,20 +1681,6 @@ 

[Mesa-dev] [7.5/16] intel/isl: Take 3D surfaces into account in image params

[Topi Pohjolainen]

CC: Jason Ekstrand 
Signed-off-by: Topi Pohjolainen 
---
 src/intel/isl/isl_storage_image.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl_storage_image.c 
b/src/intel/isl/isl_storage_image.c
index 4c56e787b5..a8aebce6d4 100644
--- a/src/intel/isl/isl_storage_image.c
+++ b/src/intel/isl/isl_storage_image.c
@@ -226,8 +226,12 @@ isl_surf_fill_image_param(const struct isl_device *dev,
view->base_array_layer;
}
 
-   isl_surf_get_image_offset_el(surf, view->base_level, view->base_array_layer,
-0, ¶m->offset[0],  ¶m->offset[1]);
+   isl_surf_get_image_offset_el(surf, view->base_level,
+surf->dim == ISL_SURF_DIM_3D ?
+   0 : view->base_array_layer,
+surf->dim == ISL_SURF_DIM_3D ?
+   view->base_array_layer : 0,
+¶m->offset[0],  ¶m->offset[1]);
 
const int cpp = isl_format_get_layout(surf->format)->bpb / 8;
param->stride[0] = cpp;
-- 
2.11.0

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[Mesa-dev] [PATCH] gallium: auxiliary: Fix standalone Android build of u_cpu_detect (v2)

[Tomasz Figa]

Commit 463b7d0332c5("gallium: Enable ARM NEON CPU detection.")
introduced CPU feature detection based Android cpufeatures library.
Unfortunately it also added an assumption that if PIPE_OS_ANDROID is
defined, the library is also available, which is not true for the
standalone build without using Android build system.

Fix it by defining HAS_ANDROID_CPUFEATURES in Android.mk and replacing
respective #ifdefs to use it instead.

v2:
 - Add a comment explaining why the separate flag is needed (Emil).

Signed-off-by: Tomasz Figa 
---
 src/gallium/auxiliary/Android.mk  |  1 +
 src/gallium/auxiliary/util/u_cpu_detect.c | 11 +--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/Android.mk b/src/gallium/auxiliary/Android.mk
index 356390dfde..26938384fb 100644
--- a/src/gallium/auxiliary/Android.mk
+++ b/src/gallium/auxiliary/Android.mk
@@ -50,6 +50,7 @@ LOCAL_MODULE := libmesa_gallium
 LOCAL_STATIC_LIBRARIES += libmesa_nir
 
 LOCAL_WHOLE_STATIC_LIBRARIES += cpufeatures
+LOCAL_CFLAGS += -DHAS_ANDROID_CPUFEATURES
 
 # generate sources
 LOCAL_MODULE_CLASS := STATIC_LIBRARIES
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c 
b/src/gallium/auxiliary/util/u_cpu_detect.c
index 76115bf8d5..3d6ccb5822 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.c
+++ b/src/gallium/auxiliary/util/u_cpu_detect.c
@@ -67,7 +67,7 @@
 #include 
 #endif
 
-#if defined(PIPE_OS_ANDROID)
+#if defined(HAS_ANDROID_CPUFEATURES)
 #include 
 #endif
 
@@ -304,7 +304,14 @@ PIPE_ALIGN_STACK static inline boolean sse2_has_daz(void)
 static void
 check_os_arm_support(void)
 {
-#if defined(PIPE_OS_ANDROID)
+   /*
+* On Android, the cpufeatures library is preferred way of checking
+* CPU capabilities. However, it is not available for standalone Mesa
+* builds, i.e. when Android build system (Android.mk-based) is not
+* used. Because of this we cannot use PIPE_OS_ANDROID here, but rather
+* have a separate macro that only gets enabled from respective Android.mk.
+*/
+#if defined(HAS_ANDROID_CPUFEATURES)
AndroidCpuFamily cpu_family = android_getCpuFamily();
uint64_t cpu_features = android_getCpuFeatures();
 
-- 
2.13.2.932.g7449e964c-goog

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