Re: [Mesa-dev] [PATCH 2/2] android: fix spirv_info generation

[Tapani Pälli]

On 07/19/2017 05:01 PM, Rob Herring wrote:

On Wed, Jul 19, 2017 at 8:56 AM, Emil Velikov  wrote:

On 19 July 2017 at 14:14, Tapani Pälli  wrote:

On 07/19/2017 03:29 PM, Emil Velikov wrote:


On 19 July 2017 at 08:12, Tapani Pälli  wrote:


Depending on build order, LOCAL_PATH maybe set or not (and can't
be trusted to have assumed path), change modifies all occurences
of LOCAL_PATH as locally defined COMPILER_PATH instead.


Sounds like a bug somewhere or a fundamental breakage in the Android
world.

$cat src/compiler/Android.mk
...
LOCAL_PATH := $(call my-dir)

include $(LOCAL_PATH)/Android.glsl.mk
include $(LOCAL_PATH)/Android.nir.mk
...

$cat src/compiler/Android.nir.mk
...
LOCAL_PATH := $(call my-dir)
...
include $(CLEAR_VARS) // is this one one causing problems?
...
include $(LOCAL_PATH)/Android.nir.gen.mk
...

Hence LOCAL_PATH should be set, and should point to the correct place.



Signed-off-by: Tapani Pälli 
---
   src/compiler/Android.nir.gen.mk | 38
--
   1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/src/compiler/Android.nir.gen.mk
b/src/compiler/Android.nir.gen.mk
index 4507ac4..81511de 100644
--- a/src/compiler/Android.nir.gen.mk
+++ b/src/compiler/Android.nir.gen.mk
@@ -27,6 +27,8 @@ ifeq ($(LOCAL_MODULE_CLASS),)
   LOCAL_MODULE_CLASS := STATIC_LIBRARIES
   endif

+COMPILER_PATH := $(MESA_TOP)/src/compiler
+


A define LOCAL_PATH at the top of the file should also work, right?



Right but this would override what LOCAL_PATH was before so did not want to
do that. I can try alternative approach. Maybe it is CLEAR_VARS that causes
this as in my case LOCAL_PATH had something like 'build/core' or
'core/build' and that did not work.


Not sure what causes the fallout here, but if LOCAL_PATH is off then
we should be fine with correcting it.


Agreed.


I've tried this and it does not work. Setting LOCAL_PATH in the file 
results in following (same as before) error:


--- 8< ---
FAILED: /bin/bash -c "python build/core/spirv/spirv_info_c.py 
build/core/spirv/spirv.core.grammar.json 
out/target/product/androidia_64/gen/STATIC_LIBRARIES/libmesa_nir_intermediates/spirv/spirv_info.c 
|| ( 
out/target/product/androidia_64/gen/STATIC_LIBRARIES/libmesa_nir_intermediates/spirv/spirv_info.c; 
false)"
python: can't open file 'build/core/spirv/spirv_info_c.py': [Errno 2] No 
such file or directory

--- 8< ---

Only using something else than LOCAL_PATH, like MY_LOCAL_PATH works.


Quick grep through my very limited checkout shows the following odd
bits. Seemingly unrelated, yet wrong.

system/core/liblog/Android.mk:LOCAL_PATH := $(my-dir)
system/core/Android.mk:LOCAL_PATH := $(my-dir)


"call" is not required when there are no parameters.

Rob


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[Mesa-dev] [PATCH] Revert "i965: Call intel_prepare_render() from intel_update_state()"

[Kenneth Graunke]

This reverts commit b7153c3e9f9d2d430b0338313587a00e531e4800.

The point of that commit was to ensure intel_prepare_render() occurred
before color resolves on the current framebuffer.  In 0673bbfd9ba16be8
(i965: Move surface resolves back to draw/dispatch time), Jason moved
brw_predraw_resolve_framebuffer back to draw time, which is already
after a intel_prepare_render() call.  So, this is no longer necessary.

Furthermore, it caused problems.  "mpv" would only display a small
corner of movies, and Android started failing camera CTS tests.

This is because intel_prepare_render() ended up handling DRI2 events
which caused the drawable to be resized at an inopportune time, flagging
ctx->NewState |= _NEW_BUFFERS, but at a point where we've already copied
ctx->NewState, and failed to notice the newly set flag.

The lack of _NEW_BUFFERS caused us to skip 3DSTATE_DRAWING_RECTANGLE,
so the drawing ended up being clipped to an outdated framebuffer size.

Just drop the hack and go back to handling this at the proper time.

Thanks to Matti Hämäläinen (ccr) and Tomasz Figa (tfiga) for reporting
these issues.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101558
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101704
---
 src/mesa/drivers/dri/i965/brw_context.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index bd26e2332c7..102d7223a93 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -194,8 +194,6 @@ intel_update_state(struct gl_context * ctx)
if (new_state & _NEW_POLYGON)
   brw->polygon_front_bit = _mesa_polygon_get_front_bit(ctx);
 
-   intel_prepare_render(brw);
-
if (new_state & _NEW_BUFFERS) {
   intel_update_framebuffer(ctx, ctx->DrawBuffer);
   if (ctx->DrawBuffer != ctx->ReadBuffer)
-- 
2.13.3

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Re: [Mesa-dev] [7.5/22] i965/wm: Fix number of layers in 3D images

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Wed, Jul 19, 2017 at 2:29 PM, Kenneth Graunke 
wrote:

> On Wednesday, July 19, 2017 12:53:45 PM PDT Topi Pohjolainen wrote:
> > CC: mesa-sta...@lists.freedesktop.org
> > CC: Kenneth Graunke 
> > Signed-off-by: Topi Pohjolainen 
> > ---
> >  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 +---
> >  1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > index ab6b9cdd29..bc06949116 100644
> > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > @@ -1632,6 +1632,17 @@ update_buffer_image_param(struct brw_context
> *brw,
> > param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
> >  }
> >
> > +static unsigned
> > +get_image_num_layers(const struct intel_mipmap_tree *mt, GLenum target,
> > + unsigned level)
> > +{
> > +   if (target == GL_TEXTURE_CUBE_MAP)
> > +  return 6;
> > +
> > +   return target == GL_TEXTURE_3D ?
> > +  minify(mt->logical_depth0, level) : mt->logical_depth0;
> > +}
> > +
> >  static void
> >  update_image_surface(struct brw_context *brw,
> >   struct gl_image_unit *u,
> > @@ -1660,9 +1671,8 @@ update_image_surface(struct brw_context *brw,
> >} else {
> >   struct intel_texture_object *intel_obj =
> intel_texture_object(obj);
> >   struct intel_mipmap_tree *mt = intel_obj->mt;
> > - const unsigned num_layers = (!u->Layered ? 1 :
> > -  obj->Target ==
> GL_TEXTURE_CUBE_MAP ? 6 :
> > -  mt->logical_depth0);
> > + const unsigned num_layers = u->Layered ?
> > +get_image_num_layers(mt, obj->Target, u->Level) : 1;
> >
> >   struct isl_view view = {
> >  .format = format,
> >
>
> Reviewed-by: Kenneth Graunke 
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>
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Re: [Mesa-dev] Mesa 17.2.0 release plan

[Jason Ekstrand]

On Mon, Jul 17, 2017 at 7:54 AM, Emil Velikov 
wrote:

> On 16 July 2017 at 06:35, Jason Ekstrand  wrote:
> > n Fri, Jul 7, 2017 at 11:07 AM, Emil Velikov 
> > wrote:
> >>
> >> Hi all,
> >>
> >> As you may have noticed, for a little while now we've had the release
> >> plan on the mesa3d.org website [1].
> >>
> >> Here is the current tentative schedule.
> >>
> >>  Jul 21 2017 - Feature freeze/Release candidate 1
> >>  Jul 28 2017 - Release candidate 2
> >>  Aug 04 2017 - Release candidate 3
> >>  Aug 11 2017 - Release candidate 4/final release
> >>
> >> This gives us approximately 2 weeks to get new features in.
> >>
> >> As always, please let me know of must have features that you'll like
> >> to merge before the branch point.
> >
> >
> > Here's my wishlist:
> >
> >  1) I'd like to land the rest of Topi's work to convert the i965 driver
> over
> > to ISL.  I really don't want to have a release where it's half old
> miptree
> > code and half ISL.  That's going to make back-porting a real pain.
>

The depth/stencil bits are basically ready to land and I think Topi will be
sending the color bits later today.


> >  2) I've got a bunch of fixes to the miptree code that are currently WIP
> > that I'd like to see go in.  If they don't make the branch point, I'll
> > probably just CC the lot to stable so it's not a huge deal.
>

These hit the list today.  I expect topi to review fairly quickly.


> >  3) As many of the new Vulkan extensions as we can land.  But don't block
> > the release on any of those.
>

I think everything I had any hope of landing here has landed.


> It's a bit lengthy list considering we have a bit less than a week.
>
> I've pushed my Vulkan fixes so you can merge the generator rework.
> I'll try to lend a hand for the rest.
>

If the branch got delayed by a couple of days to let the miptree churn
land, I wouldn't mind at all.  Otherwise, I think there's a decent chance
we'll be CCing the whole thing to stable because we really don't want 17.2
to be half ISL and half old code.

--Jason
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Re: [Mesa-dev] [PATCH 18/22] i965/miptree: Prepare aux state map for isl based

[Jason Ekstrand]

On Wed, Jul 19, 2017 at 6:57 AM, Pohjolainen, Topi <
topi.pohjolai...@gmail.com> wrote:

> On Tue, Jul 18, 2017 at 02:11:59PM -0700, Jason Ekstrand wrote:
> > On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
> > topi.pohjolai...@gmail.com> wrote:
> >
> > > Signed-off-by: Topi Pohjolainen 
> > > ---
> > >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 21
> ++---
> > >  1 file changed, 18 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > index d96f5c7938..fafd0c1e59 100644
> > > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > @@ -696,8 +696,14 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
> > > const uint32_t levels = mt->last_level + 1;
> > >
> > > uint32_t total_slices = 0;
> > > -   for (uint32_t level = 0; level < levels; level++)
> > > -  total_slices += mt->level[level].depth;
> > > +   for (uint32_t level = 0; level < levels; level++) {
> > > +  if (mt->surf.size > 0)
> > > + total_slices += (mt->surf.dim == ISL_SURF_DIM_3D ?
> > > + minify(mt->surf.phys_level0_sa.depth,
> > > level) :
> > > + mt->surf.phys_level0_sa.array_len);
> > > +  else
> > > + total_slices += mt->level[level].depth;
> > >
> >
> > The intention was always for the state map to use logical layers, not
> > physical.  There's no point in tracking fast-clear state for an
> individual
> > sample.  That said, that may not actually be quite correct with the
> current
> > implementation.
>
> Right, I was thinking the same. However, there are already quite a few
> things
> on the move and I thought leaving this for later. How would you feel
> addressing this after the transition to ISL?
>

One of the patches I sent fixes things so we start using logical layers for
everything.  I think I'd rather get this right up-front if that's ok with
you.


> >
> > --Jason
> >
> >
> > > +   }
> > >
> > > const size_t per_level_array_size = levels * sizeof(enum
> isl_aux_state
> > > *);
> > >
> > > @@ -715,7 +721,16 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
> > > enum isl_aux_state *s = data + per_level_array_size;
> > > for (uint32_t level = 0; level < levels; level++) {
> > >per_level_arr[level] = s;
> > > -  for (uint32_t a = 0; a < mt->level[level].depth; a++)
> > > +
> > > +  unsigned level_depth;
> > > +  if (mt->surf.size > 0)
> > > + level_depth = mt->surf.dim == ISL_SURF_DIM_3D ?
> > > +  minify(mt->surf.phys_level0_sa.depth,
> level) :
> > > +  mt->surf.phys_level0_sa.array_len;
> > > +  else
> > > + level_depth = mt->level[level].depth;
> > > +
> > > +  for (uint32_t a = 0; a < level_depth; a++)
> > >   *(s++) = initial;
> > > }
> > > assert((void *)s == data + total_size);
> > > --
> > > 2.11.0
> > >
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> > >
>
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Re: [Mesa-dev] [3.1/22] i965/miptree: Take interleaving into account in stencil pitch

[Jason Ekstrand]

On Wed, Jul 19, 2017 at 1:37 PM, Pohjolainen, Topi <
topi.pohjolai...@gmail.com> wrote:

> On Wed, Jul 19, 2017 at 01:27:16PM -0700, Jason Ekstrand wrote:
> > On Wed, Jul 19, 2017 at 12:51 PM, Topi Pohjolainen <
> > topi.pohjolai...@gmail.com> wrote:
> >
> > > This makes intel_mipmap_tree::pitch and isl_surf::row_pitch
> > > semantically equivalent.
> > >
> > > Signed-off-by: Topi Pohjolainen 
> > > ---
> > >  src/mesa/drivers/dri/i965/gen7_misc_state.c   | 12 +--
> > >  src/mesa/drivers/dri/i965/gen8_depth_state.c  | 16 +
> > >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 50
> > > ++-
> > >  3 files changed, 20 insertions(+), 58 deletions(-)
> > >
> > > diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> > > b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> > > index 6c69fa8ba5..e189788a88 100644
> > > --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
> > > +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
> > > @@ -170,19 +170,9 @@ gen7_emit_depth_stencil_hiz(struct brw_context
> *brw,
> > >
> > >BEGIN_BATCH(3);
> > >OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
> > > -  /* The stencil buffer has quirky pitch requirements.  From the
> > > -   * Sandybridge PRM, Volume 2 Part 1, page 329
> > > (3DSTATE_STENCIL_BUFFER
> > > -   * dword 1 bits 16:0 - Surface Pitch):
> > > -   *
> > > -   *The pitch must be set to 2x the value computed based on
> > > width, as
> > > -   *the stencil buffer is stored with two rows interleaved.
> > > -   *
> > > -   * While the Ivybridge PRM lacks this comment, the BSpec
> contains
> > > the
> > > -   * same text, and experiments indicate that this is necessary.
> > > -   */
> > >OUT_BATCH(enabled |
> > >  mocs << 25 |
> > > -   (2 * stencil_mt->pitch - 1));
> > > +   (stencil_mt->pitch - 1));
> > >OUT_RELOC(stencil_mt->bo,
> > > I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> > > 0);
> > > diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > > b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > > index 52c6dd0787..d05e1ba32e 100644
> > > --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > > +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > > @@ -111,22 +111,8 @@ emit_depth_packets(struct brw_context *brw,
> > > } else {
> > >BEGIN_BATCH(5);
> > >OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
> > > -  /* The stencil buffer has quirky pitch requirements.  From the
> > > Graphics
> > > -   * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil
> > > Processing
> > > -   * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER
> [DevIVB+],
> > > -   * field "Surface Pitch":
> > > -   *
> > > -   *The pitch must be set to 2x the value computed based on
> > > width, as
> > > -   *the stencil buffer is stored with two rows interleaved.
> > > -   *
> > > -   * (Note that it is not 100% clear whether this intended to
> apply to
> > > -   * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which
> > > would
> > > -   * imply that it doesn't), however the comment appears on a
> > > "DevIVB+"
> > > -   * page (which would imply that it does).  Experiments with the
> > > hardware
> > > -   * indicate that it does.
> > > -   */
> > >OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
> > > -(2 * stencil_mt->pitch - 1));
> > > +(stencil_mt->pitch - 1));
> > >OUT_RELOC64(stencil_mt->bo,
> > >I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
> > >OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
> > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > index 925c67fc50..9244a35d4f 100644
> > > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > @@ -858,6 +858,18 @@ miptree_create(struct brw_context *brw,
> > >  mt->surf.tiling),
> > >   &mt->pitch,
> > >   alloc_flags);
> > > +
> > > +  /* The stencil buffer has quirky pitch requirements.  From the
> > > +   * Sandybridge PRM, Volume 2 Part 1, page 329
> > > (3DSTATE_STENCIL_BUFFER
> > > +   * dword 1 bits 16:0 - Surface Pitch):
> > > +   *
> > > +   *The pitch must be set to 2x the value computed based on
> > > width, as
> > > +   *the stencil buffer is stored with two rows interleaved.
> > > +   *
> > > +   * While the Ivybridge PRM lacks this comment, the BSpec
> contains
> > > the
> > > +   * same text, and experiments indicate that this is necessary.
> > > +   */
> > > +  mt->pitch *= 2;
>
> Here we make it to what gpu wants.
>
> > > } else {
> > 

Re: [Mesa-dev] [PATCH 22/22] i965: Represent depth surfaces with isl

[Pohjolainen, Topi]

On Tue, Jul 18, 2017 at 02:42:21PM -0700, Jason Ekstrand wrote:
> On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
> topi.pohjolai...@gmail.com> wrote:
> 
> > Signed-off-by: Topi Pohjolainen 
> > ---
> >  src/mesa/drivers/dri/i965/brw_clear.c |   5 +-
> >  src/mesa/drivers/dri/i965/gen8_depth_state.c  |   3 +-
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 136
> > +-
> >  3 files changed, 97 insertions(+), 47 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
> > b/src/mesa/drivers/dri/i965/brw_clear.c
> > index 7fbaa3a47d..c310d2547a 100644
> > --- a/src/mesa/drivers/dri/i965/brw_clear.c
> > +++ b/src/mesa/drivers/dri/i965/brw_clear.c
> > @@ -121,7 +121,8 @@ brw_fast_clear_depth(struct gl_context *ctx)
> > if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) {
> >perf_debug("Failed to fast clear %dx%d depth because of scissors.  "
> >   "Possible 5%% performance win if avoided.\n",
> > - mt->logical_width0, mt->logical_height0);
> > + mt->surf.logical_level0_px.width,
> > + mt->surf.logical_level0_px.height);
> >return false;
> > }
> >
> > @@ -149,7 +150,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
> > *optimization must be disabled.
> > */
> >if (brw->gen == 6 &&
> > -  (minify(mt->physical_width0,
> > +  (minify(mt->surf.phys_level0_sa.width,
> >depth_irb->mt_level - mt->first_level) % 16) != 0)
> >  return false;
> >break;
> > diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > index c934d0d21a..5cee93ade0 100644
> > --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
> > @@ -78,7 +78,8 @@ emit_depth_packets(struct brw_context *brw,
> > OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
> > OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
> > OUT_BATCH(0);
> > -   OUT_BATCH(((depth - 1) << 21) | (depth_mt ? depth_mt->qpitch >> 2 :
> > 0));
> > +   OUT_BATCH(((depth - 1) << 21) |
> > +  (depth_mt ? depth_mt->surf.array_pitch_el_rows >> 2 : 0));
> > ADVANCE_BATCH();
> >
> > if (!hiz) {
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index 702dcd8635..ea8b2662fd 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -520,43 +520,7 @@ intel_miptree_create_layout(struct brw_context *brw,
> > mt->physical_height0 = height0;
> > mt->physical_depth0 = depth0;
> >
> > -   if (needs_separate_stencil(brw, mt, format, layout_flags)) {
> > -  uint32_t stencil_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD;
> > -  if (brw->gen == 6) {
> > - stencil_flags |= MIPTREE_LAYOUT_TILING_ANY;
> > -  }
> > -
> > -  mt->stencil_mt = intel_miptree_create(brw,
> > -mt->target,
> > -MESA_FORMAT_S_UINT8,
> > -mt->first_level,
> > -mt->last_level,
> > -mt->logical_width0,
> > -mt->logical_height0,
> > -mt->logical_depth0,
> > -num_samples,
> > -stencil_flags);
> > -
> > -  if (!mt->stencil_mt) {
> > -intel_miptree_release(&mt);
> > -return NULL;
> > -  }
> > -  mt->stencil_mt->r8stencil_needs_update = true;
> > -
> > -  /* Fix up the Z miptree format for how we're splitting out separate
> > -   * stencil.  Gen7 expects there to be no stencil bits in its depth
> > buffer.
> > -   */
> > -  mt->format = intel_depth_format_for_depthstencil_format(mt->
> > format);
> > -  mt->cpp = 4;
> > -
> > -  if (format == mt->format) {
> > - _mesa_problem(NULL, "Unknown format %s in separate stencil mt\n",
> > -   _mesa_get_format_name(mt->format));
> > -  }
> > -   }
> > -
> > -   if (layout_flags & MIPTREE_LAYOUT_GEN6_HIZ_STENCIL)
> > -  mt->array_layout = GEN6_HIZ_STENCIL;
> > +   assert(!needs_separate_stencil(brw, mt, format, layout_flags));
> >
> > /*
> >  * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
> > @@ -829,6 +793,40 @@ fail:
> > return NULL;
> >  }
> >
> > +static bool
> > +separate_stencil_surface(struct brw_context *brw,
> > + struct intel_mipmap_tree *mt)
> >
> 
> make_separate_stencil_surface?  Also, it seems perfectly reasonable for
> this to return the miptree rather than a bool.
> 
> 
> > +{
> > +   mt->stencil_mt = make

Re: [Mesa-dev] [v2 20/22] intel/isl/gen4: Represent cube maps with 3D layout

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Wed, Jul 19, 2017 at 9:45 PM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> v2 (Jason): Check for !ISL_SURF_DIM_3D instead of CUBE_BIT.
>
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/intel/isl/isl.c | 41 +++--
>  1 file changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index 12ffe3bb51..7d1356f0ac 100644
> --- a/src/intel/isl/isl.c
> +++ b/src/intel/isl/isl.c
> @@ -548,7 +548,8 @@ isl_choose_image_alignment_el(const struct isl_device
> *dev,
>  static enum isl_dim_layout
>  isl_surf_choose_dim_layout(const struct isl_device *dev,
> enum isl_surf_dim logical_dim,
> -   enum isl_tiling tiling)
> +   enum isl_tiling tiling,
> +   isl_surf_usage_flags_t usage)
>  {
> /* Sandy bridge needs a special layout for HiZ and stencil. */
> if (ISL_DEV_GEN(dev) == 6 &&
> @@ -584,6 +585,16 @@ isl_surf_choose_dim_layout(const struct isl_device
> *dev,
>switch (logical_dim) {
>case ISL_SURF_DIM_1D:
>case ISL_SURF_DIM_2D:
> + /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
> +  *
> +  * The cube face textures are stored in the same way as 3D
> surfaces
> +  * are stored (see section 6.17.5 for details).  For cube
> surfaces,
> +  * however, the depth is equal to the number of faces (always 6)
> and
> +  * is not reduced for each MIP.
> +  */
> + if (ISL_DEV_GEN(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
> +return ISL_DIM_LAYOUT_GEN4_3D;
> +
>   return ISL_DIM_LAYOUT_GEN4_2D;
>case ISL_SURF_DIM_3D:
>   return ISL_DIM_LAYOUT_GEN4_3D;
> @@ -635,8 +646,11 @@ isl_calc_phys_level0_extent_sa(const struct
> isl_device *dev,
>break;
>
> case ISL_SURF_DIM_2D:
> -  assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
> - dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
> +  if (ISL_DEV_GEN(dev) == 4 && (info->usage &
> ISL_SURF_USAGE_CUBE_BIT))
> + assert(dim_layout == ISL_DIM_LAYOUT_GEN4_3D);
> +  else
> + assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
> +dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
>
>if (tiling == ISL_TILING_Ys && info->samples > 1)
>   isl_finishme("%s:%s: multisample TileYs layout", __FILE__,
> __func__);
> @@ -952,7 +966,21 @@ isl_calc_phys_total_extent_el_gen4_3d(
> const struct isl_format_layout *fmtl = isl_format_get_layout(info->
> format);
>
> assert(info->samples == 1);
> -   assert(phys_level0_sa->array_len == 1);
> +
> +   if (info->dim != ISL_SURF_DIM_3D) {
> +  /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
> +   *
> +   * The cube face textures are stored in the same way as 3D surfaces
> +   * are stored (see section 6.17.5 for details).  For cube surfaces,
> +   * however, the depth is equal to the number of faces (always 6) and
> +   * is not reduced for each MIP.
> +   */
> +  assert(ISL_DEV_GEN(dev) == 4);
> +  assert(info->usage & ISL_SURF_USAGE_CUBE_BIT);
> +  assert(phys_level0_sa->array_len == 6);
> +   } else {
> +  assert(phys_level0_sa->array_len == 1);
> +   }
>
> uint32_t total_w = 0;
> uint32_t total_h = 0;
> @@ -960,11 +988,12 @@ isl_calc_phys_total_extent_el_gen4_3d(
> uint32_t W0 = phys_level0_sa->w;
> uint32_t H0 = phys_level0_sa->h;
> uint32_t D0 = phys_level0_sa->d;
> +   uint32_t A0 = phys_level0_sa->a;
>
> for (uint32_t l = 0; l < info->levels; ++l) {
>uint32_t level_w = isl_align_npot(isl_minify(W0, l),
> image_align_sa->w);
>uint32_t level_h = isl_align_npot(isl_minify(H0, l),
> image_align_sa->h);
> -  uint32_t level_d = isl_align_npot(isl_minify(D0, l),
> image_align_sa->d);
> +  uint32_t level_d = info->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l)
> : A0;
>
>uint32_t max_layers_horiz = MIN(level_d, 1u << l);
>uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
> @@ -1427,7 +1456,7 @@ isl_surf_init_s(const struct isl_device *dev,
> isl_tiling_get_info(tiling, fmtl->bpb, &tile_info);
>
> const enum isl_dim_layout dim_layout =
> -  isl_surf_choose_dim_layout(dev, info->dim, tiling);
> +  isl_surf_choose_dim_layout(dev, info->dim, tiling, info->usage);
>
> enum isl_msaa_layout msaa_layout;
> if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout))
> --
> 2.11.0
>
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[Mesa-dev] [v2 20/22] intel/isl/gen4: Represent cube maps with 3D layout

[Topi Pohjolainen]

v2 (Jason): Check for !ISL_SURF_DIM_3D instead of CUBE_BIT.

Signed-off-by: Topi Pohjolainen 
---
 src/intel/isl/isl.c | 41 +++--
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 12ffe3bb51..7d1356f0ac 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -548,7 +548,8 @@ isl_choose_image_alignment_el(const struct isl_device *dev,
 static enum isl_dim_layout
 isl_surf_choose_dim_layout(const struct isl_device *dev,
enum isl_surf_dim logical_dim,
-   enum isl_tiling tiling)
+   enum isl_tiling tiling,
+   isl_surf_usage_flags_t usage)
 {
/* Sandy bridge needs a special layout for HiZ and stencil. */
if (ISL_DEV_GEN(dev) == 6 &&
@@ -584,6 +585,16 @@ isl_surf_choose_dim_layout(const struct isl_device *dev,
   switch (logical_dim) {
   case ISL_SURF_DIM_1D:
   case ISL_SURF_DIM_2D:
+ /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
+  *
+  * The cube face textures are stored in the same way as 3D surfaces
+  * are stored (see section 6.17.5 for details).  For cube surfaces,
+  * however, the depth is equal to the number of faces (always 6) and 
+  * is not reduced for each MIP.
+  */
+ if (ISL_DEV_GEN(dev) == 4 && (usage & ISL_SURF_USAGE_CUBE_BIT))
+return ISL_DIM_LAYOUT_GEN4_3D;
+
  return ISL_DIM_LAYOUT_GEN4_2D;
   case ISL_SURF_DIM_3D:
  return ISL_DIM_LAYOUT_GEN4_3D;
@@ -635,8 +646,11 @@ isl_calc_phys_level0_extent_sa(const struct isl_device 
*dev,
   break;
 
case ISL_SURF_DIM_2D:
-  assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
- dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
+  if (ISL_DEV_GEN(dev) == 4 && (info->usage & ISL_SURF_USAGE_CUBE_BIT))
+ assert(dim_layout == ISL_DIM_LAYOUT_GEN4_3D);
+  else
+ assert(dim_layout == ISL_DIM_LAYOUT_GEN4_2D ||
+dim_layout == ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ);
 
   if (tiling == ISL_TILING_Ys && info->samples > 1)
  isl_finishme("%s:%s: multisample TileYs layout", __FILE__, __func__);
@@ -952,7 +966,21 @@ isl_calc_phys_total_extent_el_gen4_3d(
const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
 
assert(info->samples == 1);
-   assert(phys_level0_sa->array_len == 1);
+
+   if (info->dim != ISL_SURF_DIM_3D) {
+  /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
+   *
+   * The cube face textures are stored in the same way as 3D surfaces
+   * are stored (see section 6.17.5 for details).  For cube surfaces,
+   * however, the depth is equal to the number of faces (always 6) and
+   * is not reduced for each MIP.
+   */
+  assert(ISL_DEV_GEN(dev) == 4);
+  assert(info->usage & ISL_SURF_USAGE_CUBE_BIT);
+  assert(phys_level0_sa->array_len == 6);
+   } else {
+  assert(phys_level0_sa->array_len == 1);
+   }
 
uint32_t total_w = 0;
uint32_t total_h = 0;
@@ -960,11 +988,12 @@ isl_calc_phys_total_extent_el_gen4_3d(
uint32_t W0 = phys_level0_sa->w;
uint32_t H0 = phys_level0_sa->h;
uint32_t D0 = phys_level0_sa->d;
+   uint32_t A0 = phys_level0_sa->a;
 
for (uint32_t l = 0; l < info->levels; ++l) {
   uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w);
   uint32_t level_h = isl_align_npot(isl_minify(H0, l), image_align_sa->h);
-  uint32_t level_d = isl_align_npot(isl_minify(D0, l), image_align_sa->d);
+  uint32_t level_d = info->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : A0;
 
   uint32_t max_layers_horiz = MIN(level_d, 1u << l);
   uint32_t max_layers_vert = isl_align(level_d, 1u << l) / (1u << l);
@@ -1427,7 +1456,7 @@ isl_surf_init_s(const struct isl_device *dev,
isl_tiling_get_info(tiling, fmtl->bpb, &tile_info);
 
const enum isl_dim_layout dim_layout =
-  isl_surf_choose_dim_layout(dev, info->dim, tiling);
+  isl_surf_choose_dim_layout(dev, info->dim, tiling, info->usage);
 
enum isl_msaa_layout msaa_layout;
if (!isl_choose_msaa_layout(dev, info, tiling, &msaa_layout))
-- 
2.11.0

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[Mesa-dev] [PATCH 1/4] ac/gpu: add code to detect if kernel supports sync objects.

[Dave Airlie]

From: Dave Airlie 

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_gpu_info.c | 9 +
 src/amd/common/ac_gpu_info.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index ced7183..929dfd2 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -84,6 +84,14 @@ static unsigned cik_get_num_tile_pipes(struct 
amdgpu_gpu_info *info)
}
 }
 
+static bool has_syncobj(int fd)
+{
+   uint64_t value;
+   if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
+   return false;
+   return value ? true : false;
+}
+
 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
   struct radeon_info *info,
   struct amdgpu_gpu_info *amdinfo)
@@ -258,6 +266,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->vce_fw_version =
vce.available_rings ? vce_version : 0;
info->has_userptr = true;
+   info->has_syncobj = has_syncobj(fd);
info->num_render_backends = amdinfo->rb_pipes;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
if (!info->clock_crystal_freq) {
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 72a8506..20907c2 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -76,6 +76,7 @@ struct radeon_info {
uint32_tdrm_minor;
uint32_tdrm_patchlevel;
boolhas_userptr;
+   boolhas_syncobj;
 
/* Shader cores. */
uint32_tr600_max_quad_pipes; /* wave size / 16 */
-- 
2.9.4

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[Mesa-dev] radv shared semaphores

[Dave Airlie]

This set of patches adds support for the vulkan external semaphore
extensions on radv, when the kernel supports sync objects.

It currently only deals with permanent semaphore import semantics,
since that is all SteamVR requires so far, and the temporary stuff
might be a bit messier.

I'd like to land this for 17.2 if I can.

Dave.

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[Mesa-dev] [PATCH 3/4] radv/winsys: add syncobj hooks

[Dave Airlie]

From: Dave Airlie 

This just adds syncobj create/destroy/export/import paths into
the winsys interface.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_radeon_winsys.h   |  8 ++
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 36 +++
 2 files changed, 44 insertions(+)

diff --git a/src/amd/vulkan/radv_radeon_winsys.h 
b/src/amd/vulkan/radv_radeon_winsys.h
index cdcaeca..2f3990c 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -221,9 +221,17 @@ struct radeon_winsys {
   bool absolute,
   uint64_t timeout);
 
+   /* old semaphores - non shareable */
struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
void (*destroy_sem)(struct radeon_winsys_sem *sem);
 
+   /* new shareable sync objects */
+   int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
+   void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
+
+   int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int 
*fd);
+   int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t 
*syncobj);
+
 };
 
 static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 93243df..6ed8f32 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -1172,6 +1172,38 @@ error_out:
return r;
 }
 
+static int radv_amdgpu_create_syncobj(struct radeon_winsys *_ws,
+ uint32_t *handle)
+{
+   struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
+   return amdgpu_cs_create_syncobj(ws->dev, handle);
+}
+
+static void radv_amdgpu_destroy_syncobj(struct radeon_winsys *_ws,
+   uint32_t handle)
+{
+   struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
+   amdgpu_cs_destroy_syncobj(ws->dev, handle);
+}
+
+static int radv_amdgpu_export_syncobj(struct radeon_winsys *_ws,
+ uint32_t syncobj,
+ int *fd)
+{
+   struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
+
+   return amdgpu_cs_export_syncobj(ws->dev, syncobj, fd);
+}
+
+static int radv_amdgpu_import_syncobj(struct radeon_winsys *_ws,
+ int fd,
+ uint32_t *syncobj)
+{
+   struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
+
+   return amdgpu_cs_import_syncobj(ws->dev, fd, syncobj);
+}
+
 void radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
 {
ws->base.ctx_create = radv_amdgpu_ctx_create;
@@ -1190,5 +1222,9 @@ void radv_amdgpu_cs_init_functions(struct 
radv_amdgpu_winsys *ws)
ws->base.destroy_fence = radv_amdgpu_destroy_fence;
ws->base.create_sem = radv_amdgpu_create_sem;
ws->base.destroy_sem = radv_amdgpu_destroy_sem;
+   ws->base.create_syncobj = radv_amdgpu_create_syncobj;
+   ws->base.destroy_syncobj = radv_amdgpu_destroy_syncobj;
+   ws->base.export_syncobj = radv_amdgpu_export_syncobj;
+   ws->base.import_syncobj = radv_amdgpu_import_syncobj;
ws->base.fence_wait = radv_amdgpu_fence_wait;
 }
-- 
2.9.4

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[Mesa-dev] [PATCH 2/4] radv: handle signal semaphore on image acquire properly

[Dave Airlie]

From: Dave Airlie 

We haven't done anything with this before, and this seems to
lead to a slow down in deferred of about 40-50 fps, but we do
need to start signalling semaphores properly with syncobjs.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_wsi.c | 20 +---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index ab3dcd6..38338d2 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -425,17 +425,19 @@ VkResult radv_GetSwapchainImagesKHR(
 }
 
 VkResult radv_AcquireNextImageKHR(
-   VkDevice device,
+   VkDevice _device,
VkSwapchainKHR   _swapchain,
uint64_t timeout,
-   VkSemaphore  semaphore,
+   VkSemaphore  _semaphore,
VkFence  _fence,
uint32_t*pImageIndex)
 {
RADV_FROM_HANDLE(wsi_swapchain, swapchain, _swapchain);
RADV_FROM_HANDLE(radv_fence, fence, _fence);
+   RADV_FROM_HANDLE(radv_device, device, _device);
+   RADV_FROM_HANDLE(radeon_winsys_sem, semaphore, _semaphore);
 
-   VkResult result = swapchain->acquire_next_image(swapchain, timeout, 
semaphore,
+   VkResult result = swapchain->acquire_next_image(swapchain, timeout, 
_semaphore,
pImageIndex);
 
if (fence && (result == VK_SUCCESS || result == VK_SUBOPTIMAL_KHR)) {
@@ -443,6 +445,18 @@ VkResult radv_AcquireNextImageKHR(
fence->signalled = true;
}
 
+   if (semaphore && (result == VK_SUCCESS || result == VK_SUBOPTIMAL_KHR)) 
{
+   struct radv_queue *queue = device->queues[RADV_QUEUE_GENERAL];
+   struct radeon_winsys_cs *cs = 
queue->device->empty_cs[queue->queue_family_index];
+   struct radeon_winsys_ctx *ctx = queue->hw_ctx;
+
+   queue->device->ws->cs_submit(ctx, queue->queue_idx,
+&cs,
+1, NULL, NULL,
+NULL, 0,
+&semaphore, 1, false, NULL);
+   }
+
return result;
 }
 
-- 
2.9.4

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[Mesa-dev] [PATCH 4/4] radv: initial support for shared semaphores

[Dave Airlie]

From: Dave Airlie 

This adds support for permanent semaphore import/export only.

It ports all semaphores to using syncobjs when the kernel supports
them, and exposes the extensions to the user.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_device.c  | 174 --
 src/amd/vulkan/radv_entrypoints_gen.py|   3 +
 src/amd/vulkan/radv_private.h |  10 +-
 src/amd/vulkan/radv_radeon_winsys.h   |   6 +-
 src/amd/vulkan/radv_wsi.c |  24 +++-
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c |  54 ++--
 6 files changed, 245 insertions(+), 26 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a91b366..2dfac87 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -102,6 +102,10 @@ static const VkExtensionProperties instance_extensions[] = 
{
.extensionName = 
VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
.specVersion = 1,
},
+   {
+   .extensionName = 
VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
+   .specVersion = 1,
+   },
 };
 
 static const VkExtensionProperties common_device_extensions[] = {
@@ -154,6 +158,16 @@ static const VkExtensionProperties 
common_device_extensions[] = {
.specVersion = 1,
},
 };
+static const VkExtensionProperties ext_sema_device_extensions[] = {
+   {
+   .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
+   .specVersion = 1,
+   },
+   {
+   .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
+   .specVersion = 1,
+   },
+};
 
 static VkResult
 radv_extensions_register(struct radv_instance *instance,
@@ -304,6 +318,15 @@ radv_physical_device_init(struct radv_physical_device 
*device,
if (result != VK_SUCCESS)
goto fail;
 
+   if (device->rad_info.has_syncobj) {
+   result = radv_extensions_register(instance,
+ &device->extensions,
+ ext_sema_device_extensions,
+ 
ARRAY_SIZE(ext_sema_device_extensions));
+   if (result != VK_SUCCESS)
+   goto fail;
+   }
+
fprintf(stderr, "WARNING: radv is not a conformant vulkan 
implementation, testing use only.\n");
device->name = get_chip_name(device->rad_info.family);
 
@@ -1865,6 +1888,25 @@ fail:
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
 }
 
+void *radv_alloc_sem_array(int num_sems, const VkSemaphore *sems,
+  bool has_syncobj)
+{
+   const uint32_t sem_size = has_syncobj ? sizeof(uint32_t) : 
sizeof(struct radeon_winsys_sem *);
+   void *sem_array = malloc(sem_size * num_sems);
+   if (!sem_array)
+   return NULL;
+
+   for (uint32_t j = 0; j < num_sems; j++) {
+   RADV_FROM_HANDLE(radv_semaphore, sem, sems[j]);
+   if (has_syncobj)
+   ((uint32_t *)sem_array)[j] = sem->syncobj;
+   else
+   ((struct radeon_winsys_sem **)sem_array)[j] = sem->sem;
+   }
+
+   return sem_array;
+}
+
 VkResult radv_QueueSubmit(
VkQueue _queue,
uint32_tsubmitCount,
@@ -1885,6 +1927,7 @@ VkResult radv_QueueSubmit(
bool fence_emitted = false;
bool tess_rings_needed = false;
bool sample_positions_needed = false;
+   bool has_syncobj = queue->device->physical_device->rad_info.has_syncobj;
 
/* Do this first so failing to allocate scratch buffers can't result in
 * partially executed submissions. */
@@ -1915,15 +1958,32 @@ VkResult radv_QueueSubmit(
bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
bool can_patch = !do_flush;
uint32_t advance;
+   void *wait_sem_array = NULL, *signal_sem_array = NULL;
+
+   if (pSubmits[i].waitSemaphoreCount) {
+   wait_sem_array = 
radv_alloc_sem_array(pSubmits[i].waitSemaphoreCount,
+ 
pSubmits[i].pWaitSemaphores,
+ has_syncobj);
+   if (!wait_sem_array)
+   return VK_ERROR_OUT_OF_HOST_MEMORY;
+   }
+
+   if (pSubmits[i].signalSemaphoreCount) {
+   signal_sem_array = 
radv_alloc_sem_array(pSubmits[i].signalSemaphoreCount,
+ 
pSubmits[i].pSignalSemaphores,
+ has_syncobj);
+   if (!signal_sem_array)
+   return VK_ERROR_O

[Mesa-dev] [Bug 101843] Latest mesa git fails to compile in mesa/main/marshal.c

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101843

--- Comment #2 from Fabian Maurer  ---
Bisected to 95fb1c187a0ea8d13f401145282363228b91b246.

But I think I know the problem, did you try building out of tree? Because I
have the build folder on the same level as my mesa-git folder. And building
inside the git-folder itself doesn't lead to compile errors.

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Re: [Mesa-dev] [RFC PATCH] radeonsi: set a per-buffer flag that disables inter-process sharing (v2)

[zhoucm1]

On 2017年07月19日 23:34, Marek Olšák wrote:



On Jul 19, 2017 3:36 AM, "zhoucm1" > wrote:




On 2017年07月19日 04:08, Marek Olšák wrote:

From: Marek Olšák mailto:marek.ol...@amd.com>>

For lower overhead in the CS ioctl.
Winsys allocators are not used with interprocess-sharable
resources.

Hi Marek,

Could I know from how your this way reduces overhead in CS ioctl?
reusing BO to short bo list?


The kernel part of the work hasn't been done yet. The idea is that 
nonsharable buffers don't have to be revalidated by TTM,
OK, Maybe I only can see the whole picture of this idea when you 
complete kernel part.
Out of curious,  why/how can nonsharable buffers be revalidated by TTM 
without exposing like amdgpu_bo_make_resident api?


With mentioned in another thread, if we can expose make_resident api, we 
can remove bo_list, even we can remove reservation operation in CS ioctl.

And now, I think our bo list is a very bad design,
first, umd must create bo list for every command submission, this is a 
extra cpu overhead compared with traditional way.
second, kernel also have to iterate the list, when bo list is too long, 
like OpenCL program, they always throw several thousands BOs to bo list, 
reservation must keep these thousands ww_mutex safe, CPU overhead is too 
big.


So I strongly suggest we should expose make_resident api to user space. 
if cannot, I want to know any specific reason to see if we can solve it.



Regards,
David Zhou
so it should remove a lot of kernel overhead and the BO list remains 
the same.


Marek



Thanks,
David Zhou


v2: It shouldn't crash anymore, but the kernel will reject the
new flag.
---
  src/gallium/drivers/radeon/r600_buffer_common.c |  7 +
  src/gallium/drivers/radeon/radeon_winsys.h   | 20 +++---
  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c| 36
-
  src/gallium/winsys/radeon/drm/radeon_drm_bo.c  | 27
+++
  4 files changed, 62 insertions(+), 28 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
b/src/gallium/drivers/radeon/r600_buffer_common.c
index dd1c209..2747ac4 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -160,20 +160,27 @@ void r600_init_resource_fields(struct
r600_common_screen *rscreen,
}
/* Tiled textures are unmappable. Always put them in
VRAM. */
if ((res->b.b.target != PIPE_BUFFER &&
!rtex->surface.is_linear) ||
res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
res->domains = RADEON_DOMAIN_VRAM;
res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
 RADEON_FLAG_GTT_WC;
}
  + /* Only displayable single-sample textures can be
shared between
+* processes. */
+   if (res->b.b.target == PIPE_BUFFER ||
+   res->b.b.nr_samples >= 2 ||
+   rtex->surface.micro_tile_mode !=
RADEON_MICRO_MODE_DISPLAY)
+   res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
+
/* If VRAM is just stolen system memory, allow both
VRAM and
 * GTT, whichever has free space. If a buffer is
evicted from
 * VRAM to GTT, it will stay there.
 *
 * DRM 3.6.0 has good BO move throttling, so we can
allow VRAM-only
 * placements even with a low amount of stolen VRAM.
 */
if (!rscreen->info.has_dedicated_vram &&
(rscreen->info.drm_major < 3 ||
rscreen->info.drm_minor < 6) &&
res->domains == RADEON_DOMAIN_VRAM) {
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 351edcd..0abcb56 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -47,20 +47,21 @@ enum radeon_bo_domain { /* bitfield */
  RADEON_DOMAIN_GTT  = 2,
  RADEON_DOMAIN_VRAM = 4,
  RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM |
RADEON_DOMAIN_GTT
  };
enum radeon_bo_flag { /* bitfield */
  RADEON_FLAG_GTT_WC =(1 << 0),
  RADEON_FLAG_NO_CPU_ACCESS = (1 << 1),
  RADEON_FLAG_NO_SUBALLOC =   (1 << 2),
  RADEON_FLAG_SPARSE =(1 << 3),
+RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 4),
  };
enum radeon_bo_usage { /* bitfield */
  RADEON_USAGE_READ = 2,
  RADEON_USAGE_WRITE = 4,
  

[Mesa-dev] [Bug 101844] Artifacts in form of wrong pixels appearing on some surfaces

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101844

--- Comment #6 from Timothy Arceri  ---
(In reply to Timothy Arceri from comment #3)
> A quick look at the trace shows a bunch of errors messages due to the game
> expecting the GL_NV_fog_distance extensions functionality to be available.

Sorry this error message was happening on i965 which doesn't have the extension
enable for some reason, these errors are not reported on gallium drivers.

Also there are no artifacts when running on i965 so it would seem this is a
gallium issue rather than a core mesa problem.

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Re: [Mesa-dev] [PATCH] radv: rebase radv_entrypoints_gen.py on anv_entrypoints_gen.py

[Dave Airlie]

On 20 July 2017 at 11:06, Dylan Baker  wrote:
> The two generators forked from each other, and they remain basically the
> same. This rebases the radv version on the anv version, but with the
> radv changes ported over. The result is that we get rid of the "cat |"
> madness and gain mako, correct "generated by" attributions, and write
> files out directly.
>
> The only differences between the output is whitespace and comments.

Don't know enough python to do anything but say thanks and
Acked-by: Dave Airlie 

Dave.
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[Mesa-dev] [PATCH] radv: rebase radv_entrypoints_gen.py on anv_entrypoints_gen.py

[Dylan Baker]

The two generators forked from each other, and they remain basically the
same. This rebases the radv version on the anv version, but with the
radv changes ported over. The result is that we get rid of the "cat |"
madness and gain mako, correct "generated by" attributions, and write
files out directly.

The only differences between the output is whitespace and comments.

Signed-off-by: Dylan Baker 
---
 src/amd/vulkan/Makefile.am |  12 +-
 src/amd/vulkan/radv_entrypoints_gen.py | 540 +
 2 files changed, 282 insertions(+), 270 deletions(-)

diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index a645432e74..3350f54540 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -107,13 +107,11 @@ libvulkan_radeon_la_SOURCES = $(VULKAN_GEM_FILES)
 
 vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml
 
-radv_entrypoints.h : radv_entrypoints_gen.py $(vulkan_api_xml)
-   $(AM_V_GEN) cat $(vulkan_api_xml) |\
-   $(PYTHON2) $(srcdir)/radv_entrypoints_gen.py header > $@
-
-radv_entrypoints.c : radv_entrypoints_gen.py $(vulkan_api_xml)
-   $(AM_V_GEN) cat $(vulkan_api_xml) |\
-   $(PYTHON2) $(srcdir)/radv_entrypoints_gen.py code > $@
+radv_entrypoints.c: radv_entrypoints_gen.py $(vulkan_api_xml)
+   $(MKDIR_GEN)
+   $(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_entrypoints_gen.py \
+   --xml $(vulkan_api_xml) --outdir $(builddir)
+radv_entrypoints.h: radv_entrypoints.c
 
 vk_format_table.c: vk_format_table.py \
   vk_format_parse.py \
diff --git a/src/amd/vulkan/radv_entrypoints_gen.py 
b/src/amd/vulkan/radv_entrypoints_gen.py
index 22068a5b02..42f2077ae9 100644
--- a/src/amd/vulkan/radv_entrypoints_gen.py
+++ b/src/amd/vulkan/radv_entrypoints_gen.py
@@ -1,6 +1,6 @@
 # coding=utf-8
 #
-# Copyright ?? 2015 Intel Corporation
+# Copyright ?? 2015, 2017 Intel Corporation
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
@@ -22,31 +22,36 @@
 # IN THE SOFTWARE.
 #
 
-import sys
-import xml.etree.ElementTree as ET
-
-max_api_version = 1.0
-
-supported_extensions = [
-   'VK_AMD_draw_indirect_count',
-   'VK_NV_dedicated_allocation',
-   'VK_KHR_descriptor_update_template',
-   'VK_KHR_get_physical_device_properties2',
-   'VK_KHR_incremental_present',
-   'VK_KHR_maintenance1',
-   'VK_KHR_push_descriptor',
-   'VK_KHR_sampler_mirror_clamp_to_edge',
-   'VK_KHR_shader_draw_parameters',
-   'VK_KHR_surface',
-   'VK_KHR_swapchain',
-   'VK_KHR_wayland_surface',
-   'VK_KHR_xcb_surface',
-   'VK_KHR_xlib_surface',
-   'VK_KHR_get_memory_requirements2',
-   'VK_KHR_dedicated_allocation',
-   'VK_KHR_external_memory_capabilities',
-   'VK_KHR_external_memory',
-   'VK_KHR_external_memory_fd',
+import argparse
+import functools
+import os
+import textwrap
+import xml.etree.cElementTree as et
+
+from mako.template import Template
+
+MAX_API_VERSION = 1.0
+
+SUPPORTED_EXTENSIONS = [
+'VK_AMD_draw_indirect_count',
+'VK_NV_dedicated_allocation',
+'VK_KHR_descriptor_update_template',
+'VK_KHR_get_physical_device_properties2',
+'VK_KHR_incremental_present',
+'VK_KHR_maintenance1',
+'VK_KHR_push_descriptor',
+'VK_KHR_sampler_mirror_clamp_to_edge',
+'VK_KHR_shader_draw_parameters',
+'VK_KHR_surface',
+'VK_KHR_swapchain',
+'VK_KHR_wayland_surface',
+'VK_KHR_xcb_surface',
+'VK_KHR_xlib_surface',
+'VK_KHR_get_memory_requirements2',
+'VK_KHR_dedicated_allocation',
+'VK_KHR_external_memory_capabilities',
+'VK_KHR_external_memory',
+'VK_KHR_external_memory_fd',
 ]
 
 # We generate a static hash table for entry point lookup
@@ -54,54 +59,204 @@ supported_extensions = [
 # function and a power-of-two size table. The prime numbers are determined
 # experimentally.
 
-none = 0x
-hash_size = 256
-u32_mask = 2**32 - 1
-hash_mask = hash_size - 1
+TEMPLATE_H = Template(textwrap.dedent("""\
+/* This file generated from ${filename}, don't edit directly. */
+
+struct radv_dispatch_table {
+   union {
+  void *entrypoints[${len(entrypoints)}];
+  struct {
+  % for _, name, _, _, _, guard in entrypoints:
+% if guard is not None:
+#ifdef ${guard}
+  PFN_vk${name} ${name};
+#else
+  void *${name};
+# endif
+% else:
+  PFN_vk${name} ${name};
+% endif
+  % endfor
+  };
+   };
+};
+
+% for type_, name, args, num, h, guard in entrypoints:
+  % if guard is not None:
+#ifdef ${guard}
+  % endif
+  ${type_} radv_${name}(${args});
+  % if guard is not None:
+#endif // ${guard}
+  % endif
+% endfor
+"""), output_encoding='utf-8')
+
+TEMPLATE_C = Template(textwrap.dedent(u"""\
+/*
+ * Copyright ?? 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free

Re: [Mesa-dev] [PATCH mesa 5/5] wayland-egl: Update ABI checker

[Miguel Angel Vico]

On Wed, 19 Jul 2017 12:19:30 +0100
Emil Velikov  wrote:

> On 18 July 2017 at 21:49, Miguel A. Vico  wrote:
> > This change updates wayland-egl-abi-check.c with the latest changes to
> > wl_egl_window.
> >
> > Signed-off-by: Miguel A. Vico 
> > Reviewed-by: James Jones 
> > ---
> >  .../wayland/wayland-egl/wayland-egl-abi-check.c| 78 
> > ++
> >  1 file changed, 65 insertions(+), 13 deletions(-)
> >
> > diff --git a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c 
> > b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
> > index 1962f05850..6bdd71b6e0 100644
> > --- a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
> > +++ b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
> > @@ -31,7 +31,28 @@
> >   * DO NOT EVER CHANGE!
> >   */
> >
> > +/* From: a2ab5c2588 - Miguel A. Vico : wayland-egl: Make wl_egl_window a 
> > versioned struct */  
> Please keep the sha as XXX - we'll update it as the commit lands.
> 

Done.

> > +#define WL_EGL_WINDOW_VERSION_v3 3
> > +struct wl_egl_window_v3 {
> > +const intptr_t version;
> > +
> > +int width;
> > +int height;
> > +int dx;
> > +int dy;
> > +
> > +int attached_width;
> > +int attached_height;
> > +
> > +void *private;
> > +void (*resize_callback)(struct wl_egl_window *, void *);
> > +void (*destroy_window_callback)(void *);
> > +
> > +struct wl_surface *surface;
> > +};
> > +
> >  /* From: 690ead4a13 - Stencel, Joanna : egl/wayland-egl: Fix for segfault 
> > in dri2_wl_destroy_surface. */
> > +#define WL_EGL_WINDOW_VERSION_v2 2
> >  struct wl_egl_window_v2 {
> >  struct wl_surface *surface;
> >
> > @@ -123,6 +144,20 @@ struct wl_egl_window_v0 {
> >  }  
> >  \
> >  } while (0)
> >
> > +#define CHECK_VERSION(A_VER, B_VER, MATCH) 
> >  \
> > +do {   
> >  \
> > +if (((MATCH)  && (WL_EGL_WINDOW_VERSION ## A_VER) !=   
> >  \
> > + (WL_EGL_WINDOW_VERSION ## B_VER)) ||  
> >  \
> > +(!(MATCH) && (WL_EGL_WINDOW_VERSION ## A_VER) >=   
> >  \
> > + (WL_EGL_WINDOW_VERSION ## B_VER))) {  
> >  \
> > +printf("Backards incompatible change detected!\n   "   
> >  \
> > +   "WL_EGL_WINDOW_VERSION" #A_VER " %s "   
> >  \
> > +   "WL_EGL_WINDOW_VERSION" #B_VER "\n",
> >  \
> > +   ((MATCH) ? "!=" : ">="));   
> >  \
> > +return 1;  
> >  \
> > +}  
> >  \
> > +} while (0)
> > +  
> Same crazy idea as CHECK_SIZE - worth having separate macros?

Yup. Done.

> 
> >  int main(int argc, char **argv)
> >  {
> >  /* Check wl_egl_window_v1 ABI against wl_egl_window_v0 */
> > @@ -149,19 +184,36 @@ int main(int argc, char **argv)
> >
> >  CHECK_SIZE(_v1, _v2, FALSE);
> >
> > -/* Check wl_egl_window ABI against wl_egl_window_v2 */
> > -CHECK_MEMBER(_v2,, surface, surface);
> > -CHECK_MEMBER(_v2,, width,   width);
> > -CHECK_MEMBER(_v2,, height,  height);
> > -CHECK_MEMBER(_v2,, dx,  dx);
> > -CHECK_MEMBER(_v2,, dy,  dy);
> > -CHECK_MEMBER(_v2,, attached_width,  attached_width);
> > -CHECK_MEMBER(_v2,, attached_height, attached_height);
> > -CHECK_MEMBER(_v2,, private, private);
> > -CHECK_MEMBER(_v2,, resize_callback, resize_callback);
> > -CHECK_MEMBER(_v2,, destroy_window_callback, destroy_window_callback);
> > -
> > -CHECK_SIZE(_v2,, TRUE);
> > +/* Check wl_egl_window_v3 ABI against wl_egl_window_v2 */
> > +CHECK_MEMBER(_v2, _v3, surface, version);  
> Just hit me that with the current CHECK_MEMBER macro changes like the
> above will be easier to miss. Or someone will attempt to "correct" it.
> The following seem a bit more obvious, imho.
> 
> CHECK_RENAMED_MEMBER(_v2, _v3, surface, version);
> CHECK_MEMBER(_v2, _v3, width);

Sure. Done.

> 
> > +CHECK_MEMBER(_v2, _v3, width,   width);
> > +CHECK_MEMBER(_v2, _v3, height,  height);
> > +CHECK_MEMBER(_v2, _v3, dx,  dx);
> > +CHECK_MEMBER(_v2, _v3, dy,  dy);
> > +CHECK_MEMBER(_v2, _v3, attached_width,  attached_width);
> > +CHECK_MEMBER(_v2, _v3, attached_height, attached_height);
> > +CHECK_MEMBER(_v2, _v3, private, private);
> > +CHECK_MEMBER(_

[Mesa-dev] [Bug 101843] Latest mesa git fails to compile in mesa/main/marshal.c

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101843

--- Comment #1 from Timothy Arceri  ---
It's working for me, if you could use git bisect to identify the bad commit
that would be helpful.

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[Mesa-dev] [Bug 101844] Artifacts in form of wrong pixels appearing on some surfaces

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101844

--- Comment #5 from Timothy Arceri  ---
(In reply to Fabian Maurer from comment #4)
> Yes, the fog is buggy too. But is this relevant to the pixel errors? It used
> to work, after all.

Ok I see what you are talking about now. If it used to work it would be very
helpful if you could do a git bisect of a working commit vs master.

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Re: [Mesa-dev] [PATCH mesa 4/5] wayland-egl: Make wl_egl_window a versioned struct

[Miguel Angel Vico]

On Wed, 19 Jul 2017 12:06:06 +0100
Emil Velikov  wrote:

> On 18 July 2017 at 21:49, Miguel A. Vico  wrote:
> > We need wl_egl_window to be a versioned struct in order to keep track of
> > ABI changes.
> >
> > This change makes the first member of wl_egl_window the version number.
> >
> > An heuristic in the wayland driver is added so that we don't break
> > backwards compatibility:
> >
> >  - If the first field (version) is an actual pointer, it is an old
> >implementation of wl_egl_window, and version points to the wl_surface
> >proxy.
> >
> >  - Else, the first field is the version number, and we have
> >wl_egl_window::surface pointing to the wl_surface proxy.
> >
> > Signed-off-by: Miguel A. Vico 
> > Reviewed-by: James Jones   
> 
> This commit will cause a break in the ABI checker. Yet again, I'm
> short on ideas how to avoid that :-(

Yeah... The only think I can think of is pushing both this and 5/5 as a
single commit.

I usually like to keep things separate. Is it much of a deal given that
they'll go in at the same time?

> 
> > ---
> >  src/egl/drivers/dri2/platform_wayland.c| 13 -
> >  src/egl/wayland/wayland-egl/wayland-egl-priv.h |  6 +-
> >  src/egl/wayland/wayland-egl/wayland-egl.c  |  6 +-
> >  3 files changed, 22 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/egl/drivers/dri2/platform_wayland.c 
> > b/src/egl/drivers/dri2/platform_wayland.c
> > index ee68284217..0f0a12fd80 100644
> > --- a/src/egl/drivers/dri2/platform_wayland.c
> > +++ b/src/egl/drivers/dri2/platform_wayland.c
> > @@ -41,6 +41,7 @@
> >  #include "egl_dri2.h"
> >  #include "egl_dri2_fallbacks.h"
> >  #include "loader.h"
> > +#include "eglglobals.h"
> >
> >  #include 
> >  #include "wayland-drm-client-protocol.h"
> > @@ -100,6 +101,16 @@ destroy_window_callback(void *data)
> > dri2_surf->wl_win = NULL;
> >  }
> >
> > +static struct wl_surface *
> > +get_wl_surface_proxy(struct wl_egl_window *window)
> > +{
> > +   if (_eglPointerIsDereferencable((void *)(window->version))) {
> > +  /* window->version points to actual wl_surface data */
> > +  return wl_proxy_create_wrapper((void *)(window->version));
> > +   }  
> Please add a comment in there. I'm thinking about the following
> although use whatever you prefer.
> 
> Version 3 of wl_egl_window introduced a version field, at the same
> location where a pointer to wl_surface was stored.

Done. 

> 
> > +   return wl_proxy_create_wrapper(window->surface);
> > +}
> > +
> >  /**
> >   * Called via eglCreateWindowSurface(), drv->API.CreateWindowSurface().
> >   */
> > @@ -171,7 +182,7 @@ dri2_wl_create_window_surface(_EGLDriver *drv, 
> > _EGLDisplay *disp,
> > wl_proxy_set_queue((struct wl_proxy *)dri2_surf->wl_dpy_wrapper,
> >dri2_surf->wl_queue);
> >
> > -   dri2_surf->wl_surface_wrapper = 
> > wl_proxy_create_wrapper(window->surface);
> > +   dri2_surf->wl_surface_wrapper = get_wl_surface_proxy(window);
> > if (!dri2_surf->wl_surface_wrapper) {
> >_eglError(EGL_BAD_ALLOC, "dri2_create_surface");
> >goto cleanup_drm;
> > diff --git a/src/egl/wayland/wayland-egl/wayland-egl-priv.h 
> > b/src/egl/wayland/wayland-egl/wayland-egl-priv.h
> > index 92c31d9454..3b59908cc1 100644
> > --- a/src/egl/wayland/wayland-egl/wayland-egl-priv.h
> > +++ b/src/egl/wayland/wayland-egl/wayland-egl-priv.h
> > @@ -41,8 +41,10 @@
> >  extern "C" {
> >  #endif
> >
> > +#define WL_EGL_WINDOW_VERSION 3
> > +
> >  struct wl_egl_window {
> > -   struct wl_surface *surface;
> > +   const intptr_t version;
> >
> > int width;
> > int height;
> > @@ -55,6 +57,8 @@ struct wl_egl_window {
> > void *private;
> > void (*resize_callback)(struct wl_egl_window *, void *);
> > void (*destroy_window_callback)(void *);
> > +
> > +   struct wl_surface *surface;
> >  };
> >
> >  #ifdef  __cplusplus
> > diff --git a/src/egl/wayland/wayland-egl/wayland-egl.c 
> > b/src/egl/wayland/wayland-egl/wayland-egl.c
> > index 4a4701a2de..02645549e0 100644
> > --- a/src/egl/wayland/wayland-egl/wayland-egl.c
> > +++ b/src/egl/wayland/wayland-egl/wayland-egl.c
> > @@ -28,6 +28,7 @@
> >   */
> >
> >  #include 
> > +#include 
> >
> >  #include 
> >  #include "wayland-egl.h"
> > @@ -54,6 +55,7 @@ WL_EGL_EXPORT struct wl_egl_window *
> >  wl_egl_window_create(struct wl_surface *surface,
> >  int width, int height)
> >  {
> > +   struct wl_egl_window _INIT_ = { .version = WL_EGL_WINDOW_VERSION };
> > struct wl_egl_window *egl_window;
> >
> > if (width <= 0 || height <= 0)
> > @@ -63,6 +65,8 @@ wl_egl_window_create(struct wl_surface *surface,
> > if (!egl_window)
> > return NULL;
> >
> > +   memcpy(egl_window, &_INIT_, sizeof *egl_window);
> > +  
> The _INIT_ and memcpy seems like an overkill. At the same time the
> current malloc + init each member is not that robust.
> Something like the following seems reaso

Re: [Mesa-dev] [PATCH mesa 3/5] egl: Fix _eglPointerIsDereferencable() to ignore page residency

[Miguel Angel Vico]

On Wed, 19 Jul 2017 11:43:43 +0100
Emil Velikov  wrote:

> On 18 July 2017 at 21:49, Miguel A. Vico  wrote:
> > mincore() returns 0 on success, and -1 on failure.  The last parameter
> > is a vector of bytes with one entry for each page queried.  mincore
> > returns page residency information in the first bit of each byte in the
> > vector.
> >
> > Residency doesn't actually matter when determining whether a pointer is
> > dereferenceable, so the output vector can be ignored.  What matters is
> > whether mincore succeeds. See:
> >
> >   http://man7.org/linux/man-pages/man2/mincore.2.html
> >  
> Makes sense. Can you confirm that the BSD/Solaris manpages are on the same 
> page?

According to the man pages, they all seem to behave the same way in
that regard.

> 
> Considering they all agree
> Reviewed-by: Emil Velikov 
> 

Thanks. I sent the new rebased v2 version. Could you push on my behalf?

> -Emil

Thanks.

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Re: [Mesa-dev] [PATCH mesa 2/5] egl: Move _eglPointerIsDereferencable() to eglglobals.[ch]

[Miguel Angel Vico]

On Wed, 19 Jul 2017 11:36:59 +0100
Emil Velikov  wrote:

> On 18 July 2017 at 21:49, Miguel A. Vico  wrote:
> > More _eglPointerIsDereferencable() to eglglobals.[ch] and make it a
> > non-static function so it can be used out of egldisplay.c
> >  
> s/More/Move/

Done.

> 
> > Signed-off-by: Miguel A. Vico 
> > Reviewed-by: James Jones   
> Reviewed-by: Emil Velikov 

Thanks. I sent the new rebased v2 version. Could you push on my behalf?

> 
> -Emil

Thanks.

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[Mesa-dev] [Bug 101844] Artifacts in form of wrong pixels appearing on some surfaces

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101844

--- Comment #4 from Fabian Maurer  ---
Yes, the fog is buggy too. But is this relevant to the pixel errors? It used to
work, after all.

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Re: [Mesa-dev] [PATCH mesa 1/5] wayland-egl: Add wl_egl_window ABI checker

[Miguel Angel Vico]

Thanks for all the reviews, Emil.

Inline.

On Wed, 19 Jul 2017 11:35:04 +0100
Emil Velikov  wrote:

> Hi Miguel,
> 
> Thanks for looking into this. There's a couple of small nits below but
> it overall looks good.
> 
> On 18 July 2017 at 21:49, Miguel A. Vico  wrote:
> > Add a small ABI checker for wl_egl_window so that we can check for
> > backwards incompatible changes at 'make check' time.
> >
> > Signed-off-by: Miguel A. Vico 
> > Reviewed-by: James Jones 
> > ---
> >  src/egl/wayland/wayland-egl/Makefile.am|  10 +-
> >  .../wayland/wayland-egl/wayland-egl-abi-check.c| 167 
> > +
> >  2 files changed, 176 insertions(+), 1 deletion(-)
> >  create mode 100644 src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
> >
> > diff --git a/src/egl/wayland/wayland-egl/Makefile.am 
> > b/src/egl/wayland/wayland-egl/Makefile.am
> > index 8c45e8e26d..74a52027c6 100644
> > --- a/src/egl/wayland/wayland-egl/Makefile.am
> > +++ b/src/egl/wayland/wayland-egl/Makefile.am
> > @@ -14,7 +14,15 @@ libwayland_egl_la_LDFLAGS = \
> > $(GC_SECTIONS) \
> > $(LD_NO_UNDEFINED)
> >
> > -TESTS = wayland-egl-symbols-check
> > +TESTS =
> > +check_PROGRAMS =
> > +
> > +TESTS += wayland-egl-symbols-check
> >  EXTRA_DIST = wayland-egl-symbols-check
> >
> > +TESTS += wayland-egl-abi-check
> > +check_PROGRAMS += wayland-egl-abi-check
> > +  
> Please add into the respective variables directly.
> 
> TESTS = \
>foo \
>bar
> 
> check_PROGRAMS = wayland-egl-abi-check
> 
> > +wayland_egl_abi_check_SOURCES = wayland-egl-abi-check.c
> > +  
> Feel free to drop this - default extension is ".c" so this will be
> picked automatically.

Done.

> 
> >  include $(top_srcdir)/install-lib-links.mk
> > diff --git a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c 
> > b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
> > new file mode 100644
> > index 00..1962f05850
> > --- /dev/null
> > +++ b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
> > @@ -0,0 +1,167 @@
> > +/*
> > + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the 
> > "Software"),
> > + * to deal in the Software without restriction, including without 
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included 
> > in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
> > OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
> > OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> > + * DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +#include  // offsetof
> > +#include   // printf
> > +
> > +#include "wayland-egl-priv.h" // Current struct wl_egl_window 
> > implementation
> > +
> > +/*
> > + * Following are previous implementations of wl_egl_window.
> > + *
> > + * DO NOT EVER CHANGE!
> > + */
> > +
> > +/* From: 690ead4a13 - Stencel, Joanna : egl/wayland-egl: Fix for segfault 
> > in dri2_wl_destroy_surface. */
> > +struct wl_egl_window_v2 {  
> 
> > +/* From: ca3ed3e024 - Ander Conselvan de Oliveira : egl/wayland: Don't 
> > invalidate drawable on swap buffers */
> > +struct wl_egl_window_v1 {  
> 
> > +/* From: 214fc6e850 - Benjamin Franzke : egl: Implement libwayland-egl */
> > +struct wl_egl_window_v0 {  
> Hats off for digging all the commits and adding references!
> 
> Can we declare the structs in the same order to how they are used - 0...
> 

Done.

> 
> > +/* This program checks we keep a backwards-compatible struct wl_egl_window
> > + * definition whenever it is modified in wayland-egl-priv.h.
> > + *
> > + * The previous definition should be added above as a new struct
> > + * wl_egl_window_vN, and the appropriate checks should be added below
> > + */
> > +
> > +#define TRUE  1
> > +#define FALSE 0
> > +  
> Use stdbool.h's true/false if the suggestion, below seem too much?
> 
> > +#define MEMBER_SIZE(TYPE, MEMBER) sizeof(((TYPE *)0)->MEMBER)
> > +
> > +#define CHECK_MEMBER(A_VER, B_VER, A_MEMBER, B_MEMBER) 
> >  \
> > +do {   
> >  \
> > +if (offsetof(struct wl_egl_window ## A_VER, A_MEMBER) !=   
> >  \
> > +offsetof(struct wl_egl_windo

[Mesa-dev] [Bug 101844] Artifacts in form of wrong pixels appearing on some surfaces

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101844

--- Comment #3 from Timothy Arceri  ---
A quick look at the trace shows a bunch of errors messages due to the game
expecting the GL_NV_fog_distance extensions functionality to be available.

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[Mesa-dev] [PATCH mesa 5/5 v2] wayland-egl: Update ABI checker

[Miguel A. Vico]

This change updates wayland-egl-abi-check.c with the latest changes to
wl_egl_window.

Signed-off-by: Miguel A. Vico 
Reviewed-by: James Jones 
---
 .../wayland/wayland-egl/wayland-egl-abi-check.c| 90 ++
 1 file changed, 75 insertions(+), 15 deletions(-)

diff --git a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c 
b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
index 9701ea1453..40b54c678a 100644
--- a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
+++ b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
@@ -61,6 +61,7 @@ struct wl_egl_window_v1 {
 };
 
 /* From: 690ead4a13 - Stencel, Joanna : egl/wayland-egl: Fix for segfault in 
dri2_wl_destroy_surface. */
+#define WL_EGL_WINDOW_VERSION_v2 2
 struct wl_egl_window_v2 {
 struct wl_surface *surface;
 
@@ -77,6 +78,26 @@ struct wl_egl_window_v2 {
 void (*destroy_window_callback)(void *);
 };
 
+/* From: XXX - Miguel A. Vico : wayland-egl: Make wl_egl_window a versioned 
struct */
+#define WL_EGL_WINDOW_VERSION_v3 3
+struct wl_egl_window_v3 {
+const intptr_t version;
+
+int width;
+int height;
+int dx;
+int dy;
+
+int attached_width;
+int attached_height;
+
+void *private;
+void (*resize_callback)(struct wl_egl_window *, void *);
+void (*destroy_window_callback)(void *);
+
+struct wl_surface *surface;
+};
+
 
 /* This program checks we keep a backwards-compatible struct wl_egl_window
  * definition whenever it is modified in wayland-egl-priv.h.
@@ -87,7 +108,7 @@ struct wl_egl_window_v2 {
 
 #define MEMBER_SIZE(type, member) sizeof(((type *)0)->member)
 
-#define CHECK_MEMBERS(a_ver, b_ver, a_member, b_member)
 \
+#define CHECK_RENAMED_MEMBER(a_ver, b_ver, a_member, b_member) 
 \
 do {   
 \
 if (offsetof(struct wl_egl_window ## a_ver, a_member) !=   
 \
 offsetof(struct wl_egl_window ## b_ver, b_member)) {   
 \
@@ -106,7 +127,7 @@ struct wl_egl_window_v2 {
 }  
 \
 } while (0)
 
-#define CHECK_MEMBER(a_ver, b_ver, member) CHECK_MEMBERS(a_ver, b_ver, member, 
member)
+#define CHECK_MEMBER(a_ver, b_ver, member) CHECK_RENAMED_MEMBER(a_ver, b_ver, 
member, member)
 #define CHECK_MEMBER_CURRENT(a_ver, member) CHECK_MEMBER(a_ver,, member)
 
 #define CHECK_SIZE(a_ver, b_ver)   
 \
@@ -131,6 +152,28 @@ struct wl_egl_window_v2 {
 }  
 \
 } while (0)
 
+#define CHECK_VERSION(a_ver, b_ver)
 \
+do {   
 \
+if ((WL_EGL_WINDOW_VERSION ## a_ver) >=
 \
+(WL_EGL_WINDOW_VERSION ## b_ver)) {
 \
+printf("Backards incompatible change detected!\n   "   
 \
+   "WL_EGL_WINDOW_VERSION" #a_ver " >= "   
 \
+   "WL_EGL_WINDOW_VERSION" #b_ver "\n");   
 \
+return 1;  
 \
+}  
 \
+} while (0)
+
+#define CHECK_VERSION_CURRENT(a_ver)   
 \
+do {   
 \
+if ((WL_EGL_WINDOW_VERSION ## a_ver) !=
 \
+(WL_EGL_WINDOW_VERSION)) { 
 \
+printf("Backards incompatible change detected!\n   "   
 \
+   "WL_EGL_WINDOW_VERSION" #a_ver " != "   
 \
+   "WL_EGL_WINDOW_VERSION\n"); 
 \
+return 1;  
 \
+}  
 \
+} while (0)
+
 int main(int argc, char **argv)
 {
 /* Check wl_egl_window_v1 ABI against wl_egl_window_v0 */
@@ -157,19 +200,36 @@ int main(int argc, char **argv)
 
 CHECK_SIZE(_v1, _v2);
 
-/* Check current wl_egl_window ABI against wl_egl_window_v2 */
-CHECK_MEMBER_CURRENT(_v2, surface);
-CHECK_MEMBER_CURRENT(_v2, width);
-CHECK_MEMBER_CURRENT(_v2, height);
-CHECK_MEMBER_CURRENT(_v2, dx);
-CHECK_MEMBER_CURRENT(_v2, dy);
-CHECK_MEMBER_CURRENT(_v2, attached_width);
-CHECK_MEMBER_CURRENT(_v2, attached_height);
-CHECK_MEMBER_CURRENT(_v2, private);
-CHECK_MEMBER_CURRENT(_v2, resize_callback);
-CHECK_MEMBER_CURRENT(_v2

[Mesa-dev] [PATCH mesa 4/5 v2] wayland-egl: Make wl_egl_window a versioned struct

[Miguel A. Vico]

We need wl_egl_window to be a versioned struct in order to keep track of
ABI changes.

This change makes the first member of wl_egl_window the version number.

An heuristic in the wayland driver is added so that we don't break
backwards compatibility:

 - If the first field (version) is an actual pointer, it is an old
   implementation of wl_egl_window, and version points to the wl_surface
   proxy.

 - Else, the first field is the version number, and we have
   wl_egl_window::surface pointing to the wl_surface proxy.

Signed-off-by: Miguel A. Vico 
Reviewed-by: James Jones 
---
 src/egl/drivers/dri2/platform_wayland.c| 16 +++-
 src/egl/wayland/wayland-egl/wayland-egl-priv.h |  6 +-
 src/egl/wayland/wayland-egl/wayland-egl.c  |  4 
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 211036f45f..f4c09ac0bc 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -43,6 +43,7 @@
 #include "egl_dri2_fallbacks.h"
 #include "loader.h"
 #include "util/u_vector.h"
+#include "eglglobals.h"
 
 #include 
 #include "wayland-drm-client-protocol.h"
@@ -111,6 +112,19 @@ destroy_window_callback(void *data)
dri2_surf->wl_win = NULL;
 }
 
+static struct wl_surface *
+get_wl_surface_proxy(struct wl_egl_window *window)
+{
+/* Version 3 of wl_egl_window introduced a version field at the same
+ * location where a pointer to wl_surface was stored. Thus, if
+ * window->version is dereferencable, we've been given an older version of
+ * wl_egl_window, and window->version points to wl_surface */
+   if (_eglPointerIsDereferencable((void *)(window->version))) {
+  return wl_proxy_create_wrapper((void *)(window->version));
+   }
+   return wl_proxy_create_wrapper(window->surface);
+}
+
 /**
  * Called via eglCreateWindowSurface(), drv->API.CreateWindowSurface().
  */
@@ -182,7 +196,7 @@ dri2_wl_create_window_surface(_EGLDriver *drv, _EGLDisplay 
*disp,
wl_proxy_set_queue((struct wl_proxy *)dri2_surf->wl_dpy_wrapper,
   dri2_surf->wl_queue);
 
-   dri2_surf->wl_surface_wrapper = wl_proxy_create_wrapper(window->surface);
+   dri2_surf->wl_surface_wrapper = get_wl_surface_proxy(window);
if (!dri2_surf->wl_surface_wrapper) {
   _eglError(EGL_BAD_ALLOC, "dri2_create_surface");
   goto cleanup_drm;
diff --git a/src/egl/wayland/wayland-egl/wayland-egl-priv.h 
b/src/egl/wayland/wayland-egl/wayland-egl-priv.h
index 92c31d9454..3b59908cc1 100644
--- a/src/egl/wayland/wayland-egl/wayland-egl-priv.h
+++ b/src/egl/wayland/wayland-egl/wayland-egl-priv.h
@@ -41,8 +41,10 @@
 extern "C" {
 #endif
 
+#define WL_EGL_WINDOW_VERSION 3
+
 struct wl_egl_window {
-   struct wl_surface *surface;
+   const intptr_t version;
 
int width;
int height;
@@ -55,6 +57,8 @@ struct wl_egl_window {
void *private;
void (*resize_callback)(struct wl_egl_window *, void *);
void (*destroy_window_callback)(void *);
+
+   struct wl_surface *surface;
 };
 
 #ifdef  __cplusplus
diff --git a/src/egl/wayland/wayland-egl/wayland-egl.c 
b/src/egl/wayland/wayland-egl/wayland-egl.c
index 4a4701a2de..f16324c9f6 100644
--- a/src/egl/wayland/wayland-egl/wayland-egl.c
+++ b/src/egl/wayland/wayland-egl/wayland-egl.c
@@ -28,6 +28,7 @@
  */
 
 #include 
+#include 
 
 #include 
 #include "wayland-egl.h"
@@ -54,6 +55,7 @@ WL_EGL_EXPORT struct wl_egl_window *
 wl_egl_window_create(struct wl_surface *surface,
 int width, int height)
 {
+   struct wl_egl_window _INIT_ = { .version = WL_EGL_WINDOW_VERSION };
struct wl_egl_window *egl_window;
 
if (width <= 0 || height <= 0)
@@ -63,6 +65,8 @@ wl_egl_window_create(struct wl_surface *surface,
if (!egl_window)
return NULL;
 
+   memcpy(egl_window, &_INIT_, sizeof *egl_window);
+
egl_window->surface = surface;
egl_window->private = NULL;
egl_window->resize_callback = NULL;
-- 
2.12.2

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[Mesa-dev] [PATCH mesa 3/5 v2] egl: Fix _eglPointerIsDereferencable() to ignore page residency

[Miguel A. Vico]

mincore() returns 0 on success, and -1 on failure.  The last parameter
is a vector of bytes with one entry for each page queried.  mincore
returns page residency information in the first bit of each byte in the
vector.

Residency doesn't actually matter when determining whether a pointer is
dereferenceable, so the output vector can be ignored.  What matters is
whether mincore succeeds. See:

  http://man7.org/linux/man-pages/man2/mincore.2.html

Signed-off-by: Miguel A. Vico 
Reviewed-by: Emil Velikov 
---
 src/egl/main/eglglobals.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/egl/main/eglglobals.c b/src/egl/main/eglglobals.c
index 6fdc6c31ce..9071226618 100644
--- a/src/egl/main/eglglobals.c
+++ b/src/egl/main/eglglobals.c
@@ -168,7 +168,18 @@ _eglPointerIsDereferencable(void *p)
   return EGL_FALSE;
}
 
-   return (valid & 0x01) == 0x01;
+   /* mincore() returns 0 on success, and -1 on failure.  The last parameter
+* is a vector of bytes with one entry for each page queried.  mincore
+* returns page residency information in the first bit of each byte in the
+* vector.
+*
+* Residency doesn't actually matter when determining whether a pointer is
+* dereferenceable, so the output vector can be ignored.  What matters is
+* whether mincore succeeds. See:
+*
+*   http://man7.org/linux/man-pages/man2/mincore.2.html
+*/
+   return EGL_TRUE;
 #else
return p != NULL;
 #endif
-- 
2.12.2

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[Mesa-dev] [PATCH mesa 2/5 v2] egl: Move _eglPointerIsDereferencable() to eglglobals.[ch]

[Miguel A. Vico]

Move _eglPointerIsDereferencable() to eglglobals.[ch] and make it a
non-static function so it can be used out of egldisplay.c

Signed-off-by: Miguel A. Vico 
Reviewed-by: James Jones 
Reviewed-by: Emil Velikov 
---
 src/egl/main/egldisplay.c | 33 -
 src/egl/main/eglglobals.c | 31 +++
 src/egl/main/eglglobals.h |  6 ++
 3 files changed, 37 insertions(+), 33 deletions(-)

diff --git a/src/egl/main/egldisplay.c b/src/egl/main/egldisplay.c
index 7aaab3c2c9..690728d2f7 100644
--- a/src/egl/main/egldisplay.c
+++ b/src/egl/main/egldisplay.c
@@ -49,10 +49,6 @@
 #include "eglsync.h"
 
 /* Includes for _eglNativePlatformDetectNativeDisplay */
-#ifdef HAVE_MINCORE
-#include 
-#include 
-#endif
 #ifdef HAVE_WAYLAND_PLATFORM
 #include 
 #endif
@@ -106,35 +102,6 @@ _eglGetNativePlatformFromEnv(void)
 
 
 /**
- * Perform validity checks on a generic pointer.
- */
-static EGLBoolean
-_eglPointerIsDereferencable(void *p)
-{
-#ifdef HAVE_MINCORE
-   uintptr_t addr = (uintptr_t) p;
-   unsigned char valid = 0;
-   const long page_size = getpagesize();
-
-   if (p == NULL)
-  return EGL_FALSE;
-
-   /* align addr to page_size */
-   addr &= ~(page_size - 1);
-
-   if (mincore((void *) addr, page_size, &valid) < 0) {
-  _eglLog(_EGL_DEBUG, "mincore failed: %m");
-  return EGL_FALSE;
-   }
-
-   return (valid & 0x01) == 0x01;
-#else
-   return p != NULL;
-#endif
-}
-
-
-/**
  * Try detecting native platform with the help of native display 
characteristcs.
  */
 static _EGLPlatformType
diff --git a/src/egl/main/eglglobals.c b/src/egl/main/eglglobals.c
index baf96bb1ec..6fdc6c31ce 100644
--- a/src/egl/main/eglglobals.c
+++ b/src/egl/main/eglglobals.c
@@ -37,6 +37,12 @@
 #include "eglglobals.h"
 #include "egldisplay.h"
 #include "egldriver.h"
+#include "egllog.h"
+
+#ifdef HAVE_MINCORE
+#include 
+#include 
+#endif
 
 
 static mtx_t _eglGlobalMutex = _MTX_INITIALIZER_NP;
@@ -142,3 +148,28 @@ _eglGetClientExtensionString(void)
mtx_unlock(_eglGlobal.Mutex);
return ret;
 }
+
+EGLBoolean
+_eglPointerIsDereferencable(void *p)
+{
+#ifdef HAVE_MINCORE
+   uintptr_t addr = (uintptr_t) p;
+   unsigned char valid = 0;
+   const long page_size = getpagesize();
+
+   if (p == NULL)
+  return EGL_FALSE;
+
+   /* align addr to page_size */
+   addr &= ~(page_size - 1);
+
+   if (mincore((void *) addr, page_size, &valid) < 0) {
+  _eglLog(_EGL_DEBUG, "mincore failed: %m");
+  return EGL_FALSE;
+   }
+
+   return (valid & 0x01) == 0x01;
+#else
+   return p != NULL;
+#endif
+}
diff --git a/src/egl/main/eglglobals.h b/src/egl/main/eglglobals.h
index c6ef59d482..6655ccab65 100644
--- a/src/egl/main/eglglobals.h
+++ b/src/egl/main/eglglobals.h
@@ -87,4 +87,10 @@ static inline unsigned int DebugBitFromType(EGLenum type)
 extern const char *
 _eglGetClientExtensionString(void);
 
+/**
+ * Perform validity checks on a generic pointer.
+ */
+extern EGLBoolean
+_eglPointerIsDereferencable(void *p);
+
 #endif /* EGLGLOBALS_INCLUDED */
-- 
2.12.2

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[Mesa-dev] [PATCH mesa 1/5 v2] wayland-egl: Add wl_egl_window ABI checker

[Miguel A. Vico]

Add a small ABI checker for wl_egl_window so that we can check for
backwards incompatible changes at 'make check' time.

Signed-off-by: Miguel A. Vico 
Reviewed-by: James Jones 
---
 src/egl/wayland/wayland-egl/Makefile.am|   6 +-
 .../wayland/wayland-egl/wayland-egl-abi-check.c| 175 +
 2 files changed, 180 insertions(+), 1 deletion(-)
 create mode 100644 src/egl/wayland/wayland-egl/wayland-egl-abi-check.c

diff --git a/src/egl/wayland/wayland-egl/Makefile.am 
b/src/egl/wayland/wayland-egl/Makefile.am
index 8c45e8e26d..846fa6247b 100644
--- a/src/egl/wayland/wayland-egl/Makefile.am
+++ b/src/egl/wayland/wayland-egl/Makefile.am
@@ -14,7 +14,11 @@ libwayland_egl_la_LDFLAGS = \
$(GC_SECTIONS) \
$(LD_NO_UNDEFINED)
 
-TESTS = wayland-egl-symbols-check
+TESTS = wayland-egl-symbols-check \
+wayland-egl-abi-check
+
 EXTRA_DIST = wayland-egl-symbols-check
 
+check_PROGRAMS = wayland-egl-abi-check
+
 include $(top_srcdir)/install-lib-links.mk
diff --git a/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c 
b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
new file mode 100644
index 00..9701ea1453
--- /dev/null
+++ b/src/egl/wayland/wayland-egl/wayland-egl-abi-check.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include  // offsetof
+#include   // printf
+
+#include "wayland-egl-priv.h" // Current struct wl_egl_window implementation
+
+/*
+ * Following are previous implementations of wl_egl_window.
+ *
+ * DO NOT EVER CHANGE!
+ */
+
+/* From: 214fc6e850 - Benjamin Franzke : egl: Implement libwayland-egl */
+struct wl_egl_window_v0 {
+struct wl_surface *surface;
+
+int width;
+int height;
+int dx;
+int dy;
+
+int attached_width;
+int attached_height;
+};
+
+/* From: ca3ed3e024 - Ander Conselvan de Oliveira : egl/wayland: Don't 
invalidate drawable on swap buffers */
+struct wl_egl_window_v1 {
+struct wl_surface *surface;
+
+int width;
+int height;
+int dx;
+int dy;
+
+int attached_width;
+int attached_height;
+
+void *private;
+void (*resize_callback)(struct wl_egl_window *, void *);
+};
+
+/* From: 690ead4a13 - Stencel, Joanna : egl/wayland-egl: Fix for segfault in 
dri2_wl_destroy_surface. */
+struct wl_egl_window_v2 {
+struct wl_surface *surface;
+
+int width;
+int height;
+int dx;
+int dy;
+
+int attached_width;
+int attached_height;
+
+void *private;
+void (*resize_callback)(struct wl_egl_window *, void *);
+void (*destroy_window_callback)(void *);
+};
+
+
+/* This program checks we keep a backwards-compatible struct wl_egl_window
+ * definition whenever it is modified in wayland-egl-priv.h.
+ *
+ * The previous definition should be added above as a new struct
+ * wl_egl_window_vN, and the appropriate checks should be added below
+ */
+
+#define MEMBER_SIZE(type, member) sizeof(((type *)0)->member)
+
+#define CHECK_MEMBERS(a_ver, b_ver, a_member, b_member)
 \
+do {   
 \
+if (offsetof(struct wl_egl_window ## a_ver, a_member) !=   
 \
+offsetof(struct wl_egl_window ## b_ver, b_member)) {   
 \
+printf("Backards incompatible change detected!\n   "   
 \
+   "offsetof(struct wl_egl_window" #a_ver "::" #a_member ") != 
"\
+   "offsetof(struct wl_egl_window" #b_ver "::" #b_member 
")\n");\
+return 1;  
 \
+}  
 \
+   
 \
+if (MEMBER_SIZE(struct wl_egl_window ## a_ver

[Mesa-dev] [PATCH 2/3] mesa/st: move st_pipe_format_to_mesa_format() call to where its used

[Timothy Arceri]

---
 src/mesa/state_tracker/st_format.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_format.c 
b/src/mesa/state_tracker/st_format.c
index 012f1a4..64a3a81 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -1035,12 +1035,11 @@ test_format_conversion(struct st_context *st)
 
/* Test all Gallium formats */
for (i = 1; i < PIPE_FORMAT_COUNT; i++) {
-  mesa_format mf = st_pipe_format_to_mesa_format(i);
-
   /* ETC formats are translated differently, skip them. */
   if (i == PIPE_FORMAT_ETC1_RGB8 && !st->has_etc1)
  continue;
 
+  mesa_format mf = st_pipe_format_to_mesa_format(i);
   if (_mesa_is_format_etc2(mf) && !st->has_etc2)
  continue;
 
-- 
2.9.4

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[Mesa-dev] [PATCH 1/3] gallium/util: fix unused variable warning

[Timothy Arceri]

---
 src/gallium/auxiliary/util/u_threaded_context.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_threaded_context.c 
b/src/gallium/auxiliary/util/u_threaded_context.c
index cb9ea3a..a9fc670 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -1978,9 +1978,11 @@ static void
 tc_call_generate_mipmap(struct pipe_context *pipe, union tc_payload *payload)
 {
struct tc_generate_mipmap *p = (struct tc_generate_mipmap *)payload;
-   bool result = pipe->generate_mipmap(pipe, p->res, p->format, p->base_level,
-   p->last_level, p->first_layer,
-   p->last_layer);
+   bool MAYBE_UNUSED result = pipe->generate_mipmap(pipe, p->res, p->format,
+p->base_level,
+p->last_level,
+p->first_layer,
+p->last_layer);
assert(result);
pipe_resource_reference(&p->res, NULL);
 }
-- 
2.9.4

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[Mesa-dev] [PATCH 3/3] mesa/st: fix unused variable warnings

[Timothy Arceri]

---
 src/mesa/state_tracker/st_cb_bitmap.c | 5 +++--
 src/mesa/state_tracker/st_cb_drawpixels.c | 9 -
 src/mesa/state_tracker/st_cb_texture.c| 2 +-
 src/mesa/state_tracker/st_format.c| 5 +++--
 4 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_bitmap.c 
b/src/mesa/state_tracker/st_cb_bitmap.c
index 7ba6d82..a5c7ed0 100644
--- a/src/mesa/state_tracker/st_cb_bitmap.c
+++ b/src/mesa/state_tracker/st_cb_bitmap.c
@@ -301,8 +301,9 @@ draw_bitmap_quad(struct gl_context *ctx, GLint x, GLint y, 
GLfloat z,
   /* XXX if the bitmap is larger than the max texture size, break
* it up into chunks.
*/
-  GLuint maxSize = 1 << (pipe->screen->get_param(pipe->screen,
-PIPE_CAP_MAX_TEXTURE_2D_LEVELS) - 1);
+  GLuint MAYBE_UNUSED maxSize =
+ 1 << (pipe->screen->get_param(pipe->screen,
+   PIPE_CAP_MAX_TEXTURE_2D_LEVELS) - 1);
   assert(width <= (GLsizei) maxSize);
   assert(height <= (GLsizei) maxSize);
}
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c 
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 384f965..1d88976 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -464,7 +464,6 @@ make_texture(struct st_context *st,
 
{
   struct pipe_transfer *transfer;
-  GLboolean success;
   GLubyte *dest;
   const GLbitfield imageTransferStateSave = ctx->_ImageTransferState;
 
@@ -497,9 +496,9 @@ make_texture(struct st_context *st,
   format, type, /* src format/type */
   pixels,   /* data source */
   unpack);
- success = GL_TRUE;
   }
   else {
+ bool MAYBE_UNUSED success;
  success = _mesa_texstore(ctx, 2,   /* dims */
   baseInternalFormat, /* baseInternalFormat */
   mformat,  /* mesa_format */
@@ -509,13 +508,13 @@ make_texture(struct st_context *st,
   format, type, /* src format/type */
   pixels,   /* data source */
   unpack);
+
+ assert(success);
   }
 
   /* unmap */
   pipe_transfer_unmap(pipe, transfer);
 
-  assert(success);
-
   /* restore */
   ctx->_ImageTransferState = imageTransferStateSave;
}
@@ -570,7 +569,7 @@ draw_textured_quad(struct gl_context *ctx, GLint x, GLint 
y, GLfloat z,
const unsigned fb_width = _mesa_geometric_width(ctx->DrawBuffer);
const unsigned fb_height = _mesa_geometric_height(ctx->DrawBuffer);
GLfloat x0, y0, x1, y1;
-   GLsizei maxSize;
+   GLsizei MAYBE_UNUSED maxSize;
boolean normalized = sv[0]->texture->target == PIPE_TEXTURE_2D;
unsigned cso_state_mask;
 
diff --git a/src/mesa/state_tracker/st_cb_texture.c 
b/src/mesa/state_tracker/st_cb_texture.c
index c6a5e63..b1abef3 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2396,7 +2396,7 @@ copy_image_data_to_texture(struct st_context *st,
 {
/* debug checks */
{
-  const struct gl_texture_image *dstImage =
+  const struct gl_texture_image MAYBE_UNUSED *dstImage =
  stObj->base.Image[stImage->base.Face][dstLevel];
   assert(dstImage);
   assert(dstImage->Width == stImage->base.Width);
diff --git a/src/mesa/state_tracker/st_format.c 
b/src/mesa/state_tracker/st_format.c
index 64a3a81..348853a 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -1028,7 +1028,7 @@ test_format_conversion(struct st_context *st)
 
   pf = st_mesa_format_to_pipe_format(st, i);
   if (pf != PIPE_FORMAT_NONE) {
- mesa_format mf = st_pipe_format_to_mesa_format(pf);
+ mesa_format MAYBE_UNUSED mf = st_pipe_format_to_mesa_format(pf);
  assert(mf == i);
   }
}
@@ -1044,7 +1044,8 @@ test_format_conversion(struct st_context *st)
  continue;
 
   if (mf != MESA_FORMAT_NONE) {
- enum pipe_format pf = st_mesa_format_to_pipe_format(st, mf);
+ enum pipe_format MAYBE_UNUSED pf =
+st_mesa_format_to_pipe_format(st, mf);
  assert(pf == i);
   }
}
-- 
2.9.4

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[Mesa-dev] [Bug 101851] [regression] libEGL_common.a undefined reference to '__gxx_personality_v0'

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101851

Bug ID: 101851
   Summary: [regression] libEGL_common.a undefined reference to
'__gxx_personality_v0'
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: EGL
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: m...@fireburn.co.uk
QA Contact: mesa-dev@lists.freedesktop.org

Created attachment 132780
  --> https://bugs.freedesktop.org/attachment.cgi?id=132780&action=edit
Build log

Here's the error:

libtool: link: ( cd ".libs" && rm -f "libEGL_common.la" && ln -s
"../libEGL_common.la" "libEGL_common.la" )
/bin/sh ../../libtool  --tag=CC   --mode=link x86_64-pc-linux-gnu-gcc -m32
-I/var/tmp/portage/media-libs/mesa-/work/mesa-/include
-I/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/main
-I/var/tmp/portage/media-libs/mesa-/work/mesa-/src/gbm/main
-I/var/tmp/portage/media-libs/mesa-/work/mesa-/src
-D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS
-D_GNU_SOURCE -DUSE_SSE41 -DUSE_GCC_ATOMIC_BUILTINS -DNDEBUG
-DTEXTURE_FLOAT_ENABLED -DUSE_X86_ASM -DUSE_MMX_ASM -DUSE_3DNOW_ASM
-DUSE_SSE_ASM -DHAVE_XLOCALE_H -DHAVE_SYS_SYSCTL_H -DHAVE_STRTOF
-DHAVE_MKOSTEMP -DHAVE_DLOPEN -DHAVE_DL_ITERATE_PHDR -DHAVE_POSIX_MEMALIGN
-DHAVE_LIBDRM -DGLX_USE_DRM -DGLX_INDIRECT_RENDERING -DGLX_DIRECT_RENDERING
-DGLX_USE_TLS -DHAVE_X11_PLATFORM -DHAVE_SURFACELESS_PLATFORM
-DHAVE_WAYLAND_PLATFORM -DHAVE_DRM_PLATFORM -DHAVE_DRI3 -DENABLE_SHADER_CACHE
-DHAVE_MINCORE -DHAVE_ST_VDPAU -DHAVE_LLVM=0x0500 -DMESA_LLVM_VERSION_PATCH=0
-fvisibility=hidden -I/usr/include/libdrm 
-D_EGL_NATIVE_PLATFORM=_EGL_PLATFORM_X11   
-I/var/tmp/portage/media-libs/mesa-/work/mesa-/src/loader
-I../../src/egl/drivers/dri2
-I/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/drivers/dri2
-I/var/tmp/portage/media-libs/mesa-/work/mesa-/src/gbm/backends/dri
-I/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/wayland/wayland-egl
-I../../src/egl/wayland/wayland-drm
-I/var/tmp/portage/media-libs/mesa-/work/mesa-/src/egl/wayland/wayland-drm
-DDEFAULT_DRIVER_DIR=\"/usr/lib32/dri\" -D_EGL_BUILT_IN_DRIVER_DRI2  -O2
-march=native -pipe -Wall -std=c99 -Werror=implicit-function-declaration
-Werror=missing-prototypes -fno-math-errno -fno-trapping-math  -no-undefined
-version-number 1:0 -Wl,-Bsymbolic -Wl,--gc-sections -Wl,--no-undefined -Wl,-O1
-Wl,--hash-style=gnu -Wl,--as-needed -o libEGL.la -rpath /usr/lib32 
libEGL_common.la 
libtool: link: x86_64-pc-linux-gnu-gcc -m32 -shared  -fPIC -DPIC 
-Wl,--whole-archive ./.libs/libEGL_common.a -Wl,--no-whole-archive  -Wl,-rpath
-Wl,/var/tmp/portage/media-libs/mesa-/work/mesa--abi_x86_32.x86/src/gbm/.libs
-Wl,--as-needed -lpthread -lxcb-dri2 -lX11-xcb -lX11 -lxcb -lxcb-dri3
-lxcb-xfixes -lxcb-present -lxcb-sync -lxshmfence -lz
/var/tmp/portage/media-libs/mesa-/work/mesa--abi_x86_32.x86/src/gbm/.libs/libgbm.so
-lwayland-client -lwayland-server -lexpat -lm -ldl -ldrm  -m32 -O2
-march=native -Wl,-Bsymbolic -Wl,--gc-sections -Wl,--no-undefined -Wl,-O1
-Wl,--hash-style=gnu   -pthread -Wl,-soname -Wl,libEGL.so.1 -o
.libs/libEGL.so.1.0.0
./.libs/libEGL_common.a(libmesautil_la-string_to_uint_map.o):string_to_uint_map.cpp:DW.ref.__gxx_personality_v0:
error: undefined reference to '__gxx_personality_v0'
collect2: error: ld returned 1 exit status

I've attached the full log too

I think it should be using g++ or including -lstdc++

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[Mesa-dev] [PATCH 1/2] broadcom: correct header file in BROADCOM_FILES

[Andres Gomez]

This fixes `make distcheck`

> make[3]: *** No rule to make target 'common/v3d_devinfo.h', needed by 
> 'distdir'.  Stop.
> make[3]: Leaving directory '/home/local/mesa/src/broadcom'
> Makefile:945: recipe for target 'distdir' failed
> make[2]: Leaving directory '/home/local/mesa/src'
> make[2]: *** [distdir] Error 1
> make[1]: *** [distdir] Error 1

Fixes: 42799c ("broadcom: Introduce a header for talking about chip 
revisions.")
Cc: Emil Velikov 
Signed-off-by: Andres Gomez 
---
 src/broadcom/Makefile.sources | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/broadcom/Makefile.sources b/src/broadcom/Makefile.sources
index 09c8a9957d..4dadb68ee5 100644
--- a/src/broadcom/Makefile.sources
+++ b/src/broadcom/Makefile.sources
@@ -8,6 +8,6 @@ BROADCOM_GENXML_XML_FILES = \
 
 BROADCOM_FILES = \
cle/v3d_packet_helpers.h \
-   common/v3d_devinfo.h \
+   common/v3d_device_info.h \
$()
 
-- 
2.13.2

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[Mesa-dev] [PATCH 2/2] egl: add linux-dmabuf-unstable-v1-protocol.c to "nodist"

[Andres Gomez]

This fixes `make distcheck`

> make[3]: *** No rule to make target 
> 'drivers/dri2/linux-dmabuf-unstable-v1-protocol.c', needed by 'distdir'.  
> Stop.
> make[3]: Entering directory '/home/local/mesa/src/egl'
> make[3]: Leaving directory '/home/local/mesa/src/egl'
> make[2]: *** [distdir] Error 1
> make[1]: *** [distdir] Error 1
> make: *** [dist] Error 2

Fixes: 02cc359372 ("egl/wayland: Use linux-dmabuf interface for buffers")
Cc: Emil Velikov 
Signed-off-by: Andres Gomez 
---
 src/egl/Makefile.am | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
index 7c1a4929b8..6ee1fb9be8 100644
--- a/src/egl/Makefile.am
+++ b/src/egl/Makefile.am
@@ -44,10 +44,13 @@ noinst_LTLIBRARIES = libEGL_common.la
 libEGL_common_la_SOURCES = \
$(LIBEGL_C_FILES)
 
+nodist_libEGL_common_la_SOURCES =
+
 libEGL_common_la_LIBADD = \
$(EGL_LIB_DEPS)
 
 dri2_backend_FILES =
+nodist_dri2_backend_FILES =
 dri3_backend_FILES =
 
 if HAVE_PLATFORM_X11
@@ -84,8 +87,8 @@ libEGL_common_la_LIBADD += $(WAYLAND_LIBS)
 libEGL_common_la_LIBADD += $(LIBDRM_LIBS)
 libEGL_common_la_LIBADD += 
$(top_builddir)/src/egl/wayland/wayland-drm/libwayland-drm.la
 libEGL_common_la_LIBADD += $(top_builddir)/src/util/libmesautil.la
-dri2_backend_FILES += drivers/dri2/platform_wayland.c  \
-   drivers/dri2/linux-dmabuf-unstable-v1-protocol.c
+dri2_backend_FILES += drivers/dri2/platform_wayland.c
+nodist_dri2_backend_FILES += drivers/dri2/linux-dmabuf-unstable-v1-protocol.c
 endif
 
 if HAVE_PLATFORM_DRM
@@ -119,6 +122,9 @@ libEGL_common_la_SOURCES += \
$(dri2_backend_FILES) \
$(dri3_backend_FILES)
 
+nodist_libEGL_common_la_SOURCES += \
+   $(nodist_dri2_backend_FILES)
+
 libEGL_common_la_LIBADD += $(top_builddir)/src/loader/libloader.la
 libEGL_common_la_LIBADD += $(DLOPEN_LIBS) $(LIBDRM_LIBS) $(CLOCK_LIB)
 
-- 
2.13.2

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[Mesa-dev] [PATCH 0/2] Fix distcheck

[Andres Gomez]

A couple of patches to fix recent problems while running make
distcheck.

Andres Gomez (2):
  broadcom: correct header file in BROADCOM_FILES
  egl: add linux-dmabuf-unstable-v1-protocol.c to "nodist"

 src/broadcom/Makefile.sources |  2 +-
 src/egl/Makefile.am   | 10 --
 2 files changed, 9 insertions(+), 3 deletions(-)

-- 
2.13.2

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Re: [Mesa-dev] [PATCH 09/13] i965: Always create the batch with the batch object in the first execobject slot

[Kenneth Graunke]

On Wednesday, July 19, 2017 3:09:17 AM PDT Chris Wilson wrote:
> Even if we are using older kernels that do not accept the batch in the
> first slot, we can simplify our code by creating the batch with itself
> in the first slot and moving it to the end on execbuf submission.
> ---
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c | 70 
> ---
>  1 file changed, 31 insertions(+), 39 deletions(-)

Alternatively, instead of swapping them out, we could simply add_exec_bo the
batch at the end, and in execbuffer() do:

if (!use_batch_first) {
   execbuf.buffers_ptr++;
   execbuf.buffers_count--;
}

to skip over the batchbuffer entry at the beginning.  That seems easier...

It might make sense to just take this approach right away, effectively
squashing patches 8 and 9...

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Re: [Mesa-dev] [PATCH 08/13] i965: Convert reloc.target_handle into an index for I915_EXEC_HANDLE_LUT

[Kenneth Graunke]

On Wednesday, July 19, 2017 3:09:16 AM PDT Chris Wilson wrote:
> Passing the index of the target buffer via the reloc.target_handle is
> marginally more efficient for the kernel (it can avoid some allocations,
> and can use a direct lookup rather than a hash or search). It is also
> useful for ourselves as we can use the index into our exec_bos for other
> tasks.
> 
> v2: Only enable HANDLE_LUT if we can use BATCH_FIRST and thereby avoid
> a post-processing loop to fixup the relocations.
> v3: Move kernel probing from context creation to screen init.
> Use batch->use_exec_lut as it more descriptive of what's going on (Daniel)
> 
> Signed-off-by: Chris Wilson 
> Cc: Kenneth Graunke 
> Cc: Matt Turner 
> Cc: Jason Ekstrand 
> Cc: Daniel Vetter 
> ---
>  src/mesa/drivers/dri/i965/brw_context.h   |  1 +
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c | 60 
> +--
>  src/mesa/drivers/dri/i965/intel_screen.c  | 20 +
>  src/mesa/drivers/dri/i965/intel_screen.h  |  5 +++
>  4 files changed, 64 insertions(+), 22 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
> b/src/mesa/drivers/dri/i965/brw_context.h
> index ffe4792b73..62ce5e472c 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -452,6 +452,7 @@ struct intel_batchbuffer {
>  
> uint32_t state_batch_offset;
> enum brw_gpu_ring ring;
> +   bool use_exec_lut;
> bool needs_sol_reset;
> bool state_base_address_emitted;
>  
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index 065a9c1c0c..5f9639cd4d 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -62,8 +62,6 @@ intel_batchbuffer_init(struct intel_batchbuffer *batch,
> struct brw_bufmgr *bufmgr,
> bool has_llc)
>  {
> -   intel_batchbuffer_reset(batch, bufmgr, has_llc);
> -
> if (!has_llc) {
>batch->cpu_map = malloc(BATCH_SZ);
>batch->map = batch->cpu_map;
> @@ -85,6 +83,16 @@ intel_batchbuffer_init(struct intel_batchbuffer *batch,
>batch->state_batch_sizes =
>   _mesa_hash_table_create(NULL, uint_key_hash, uint_key_compare);
> }
> +
> +   struct brw_context *brw = container_of(batch, brw, batch);
> +   /* To use the LUT method for execbuf, we also require placing the batch
> +* first (to simplify our implementation). We require a kernel recent
> +* enough to always support EXEC_LUT_HANDLE, but we must check that
> +* the kernel supports EXEC_BATCH_FIRST.
> +*/
> +   batch->use_exec_lut = brw->screen->kerninfo.has_exec_batch_first;
> +
> +   intel_batchbuffer_reset(batch, bufmgr, has_llc);
>  }
>  
>  #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
> @@ -117,21 +125,12 @@ add_exec_bo(struct intel_batchbuffer *batch, struct 
> brw_bo *bo)
>   batch->exec_array_size * sizeof(batch->exec_objects[0]));
> }
>  
> -   struct drm_i915_gem_exec_object2 *validation_entry =
> -  &batch->exec_objects[batch->exec_count];
> -   validation_entry->handle = bo->gem_handle;
> -   if (bo == batch->bo) {
> -  validation_entry->relocation_count = batch->reloc_count;
> -  validation_entry->relocs_ptr = (uintptr_t) batch->relocs;
> -   } else {
> -  validation_entry->relocation_count = 0;
> -  validation_entry->relocs_ptr = 0;
> -   }
> -   validation_entry->alignment = bo->align;
> -   validation_entry->offset = bo->offset64;
> -   validation_entry->flags = bo->kflags;
> -   validation_entry->rsvd1 = 0;
> -   validation_entry->rsvd2 = 0;
> +   struct drm_i915_gem_exec_object2 *exec =
> +  memset(&batch->exec_objects[batch->exec_count], 0, sizeof(*exec));
> +   exec->handle = bo->gem_handle;
> +   exec->alignment = bo->align;
> +   exec->offset = bo->offset64;
> +   exec->flags = bo->kflags;

I liked the name "validation_entry" given that we call this the "validation
list"...exec matches the struct name better, but I think validation_entry
helps distinguish the two lists...

Moving the relocation count rubbish out to do_flush_locked is a good idea.

>  
> bo->index = batch->exec_count;
> batch->exec_bos[batch->exec_count] = bo;
> @@ -157,6 +156,11 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch,
> }
> batch->map_next = batch->map;
>  
> +   if (batch->use_exec_lut) {
> +  add_exec_bo(batch, batch->bo);
> +  assert(batch->bo->index == 0);
> +   }
> +
> batch->reserved_space = BATCH_RESERVED;
> batch->state_batch_offset = batch->bo->size;
> batch->needs_sol_reset = false;
> @@ -663,15 +667,25 @@ do_flush_locked(struct brw_context *brw, int 
> in_fence_fd, int *out_fence_fd)
>} else {
>   flags |= I915_EXEC_RENDER;
>}
> +
>if (batch->needs_sol_reset)
>flags |= I915_EXEC_GEN7_SOL_RESET;
>  
> +  unsigned int index;
> +  if (

Re: [Mesa-dev] [PATCH 2/2] radv: Add support for VK_KHR_variable_pointers.

[Connor Abbott]

For both:

Reviewed-by: Connor Abbott 

You beat me to it!

On Wed, Jul 19, 2017 at 3:29 PM, Bas Nieuwenhuizen
 wrote:
> Just a trivial enable.
>
> Signed-off-by: Bas Nieuwenhuizen 
> ---
>  src/amd/vulkan/radv_device.c   | 16 
>  src/amd/vulkan/radv_entrypoints_gen.py |  1 +
>  src/amd/vulkan/radv_pipeline.c |  1 +
>  3 files changed, 18 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index e3655dabe3a..d87be66da8b 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -157,6 +157,10 @@ static const VkExtensionProperties 
> common_device_extensions[] = {
> .extensionName = 
> VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
> .specVersion = 1,
> },
> +   {
> +   .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
> +   .specVersion = 1,
> +   },
>  };
>
>  static VkResult
> @@ -589,6 +593,18 @@ void radv_GetPhysicalDeviceFeatures2KHR(
> VkPhysicalDevicephysicalDevice,
> VkPhysicalDeviceFeatures2KHR   *pFeatures)
>  {
> +   vk_foreach_struct(ext, pFeatures->pNext) {
> +   switch (ext->sType) {
> +   case 
> VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
> +   VkPhysicalDeviceVariablePointerFeaturesKHR *features 
> = (void *)ext;
> +   features->variablePointersStorageBuffer = true;
> +   features->variablePointers = false;
> +   break;
> +   }
> +   default:
> +   break;
> +   }
> +   }
> return radv_GetPhysicalDeviceFeatures(physicalDevice, 
> &pFeatures->features);
>  }
>
> diff --git a/src/amd/vulkan/radv_entrypoints_gen.py 
> b/src/amd/vulkan/radv_entrypoints_gen.py
> index ec798157f94..61b23281501 100644
> --- a/src/amd/vulkan/radv_entrypoints_gen.py
> +++ b/src/amd/vulkan/radv_entrypoints_gen.py
> @@ -48,6 +48,7 @@ supported_extensions = [
> 'VK_KHR_external_memory',
> 'VK_KHR_external_memory_fd',
> 'VK_KHR_storage_buffer_storage_class',
> +   'VK_KHR_variable_pointers',
>  ]
>
>  # We generate a static hash table for entry point lookup
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index 90cd716047a..c920cc35be1 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -230,6 +230,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
> .image_write_without_format = true,
> .tessellation = true,
> .int64 = true,
> +   .variable_pointers = true,
> };
> entry_point = spirv_to_nir(spirv, module->size / 4,
>spec_entries, num_spec_entries,
> --
> 2.13.2
>
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[Mesa-dev] [PATCH 1/2] radv: Add VK_KHR_storage_buffer_storage_class support.

[Bas Nieuwenhuizen]

Signed-off-by: Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_device.c   | 4 
 src/amd/vulkan/radv_entrypoints_gen.py | 1 +
 2 files changed, 5 insertions(+)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a91b366721b..e3655dabe3a 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -153,6 +153,10 @@ static const VkExtensionProperties 
common_device_extensions[] = {
.extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
.specVersion = 1,
},
+   {
+   .extensionName = 
VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
+   .specVersion = 1,
+   },
 };
 
 static VkResult
diff --git a/src/amd/vulkan/radv_entrypoints_gen.py 
b/src/amd/vulkan/radv_entrypoints_gen.py
index 22068a5b02d..ec798157f94 100644
--- a/src/amd/vulkan/radv_entrypoints_gen.py
+++ b/src/amd/vulkan/radv_entrypoints_gen.py
@@ -47,6 +47,7 @@ supported_extensions = [
'VK_KHR_external_memory_capabilities',
'VK_KHR_external_memory',
'VK_KHR_external_memory_fd',
+   'VK_KHR_storage_buffer_storage_class',
 ]
 
 # We generate a static hash table for entry point lookup
-- 
2.13.2

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[Mesa-dev] [PATCH 2/2] radv: Add support for VK_KHR_variable_pointers.

[Bas Nieuwenhuizen]

Just a trivial enable.

Signed-off-by: Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_device.c   | 16 
 src/amd/vulkan/radv_entrypoints_gen.py |  1 +
 src/amd/vulkan/radv_pipeline.c |  1 +
 3 files changed, 18 insertions(+)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index e3655dabe3a..d87be66da8b 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -157,6 +157,10 @@ static const VkExtensionProperties 
common_device_extensions[] = {
.extensionName = 
VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
.specVersion = 1,
},
+   {
+   .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
+   .specVersion = 1,
+   },
 };
 
 static VkResult
@@ -589,6 +593,18 @@ void radv_GetPhysicalDeviceFeatures2KHR(
VkPhysicalDevicephysicalDevice,
VkPhysicalDeviceFeatures2KHR   *pFeatures)
 {
+   vk_foreach_struct(ext, pFeatures->pNext) {
+   switch (ext->sType) {
+   case 
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
+   VkPhysicalDeviceVariablePointerFeaturesKHR *features = 
(void *)ext;
+   features->variablePointersStorageBuffer = true;
+   features->variablePointers = false;
+   break;
+   }
+   default:
+   break;
+   }
+   }
return radv_GetPhysicalDeviceFeatures(physicalDevice, 
&pFeatures->features);
 }
 
diff --git a/src/amd/vulkan/radv_entrypoints_gen.py 
b/src/amd/vulkan/radv_entrypoints_gen.py
index ec798157f94..61b23281501 100644
--- a/src/amd/vulkan/radv_entrypoints_gen.py
+++ b/src/amd/vulkan/radv_entrypoints_gen.py
@@ -48,6 +48,7 @@ supported_extensions = [
'VK_KHR_external_memory',
'VK_KHR_external_memory_fd',
'VK_KHR_storage_buffer_storage_class',
+   'VK_KHR_variable_pointers',
 ]
 
 # We generate a static hash table for entry point lookup
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 90cd716047a..c920cc35be1 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -230,6 +230,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
.image_write_without_format = true,
.tessellation = true,
.int64 = true,
+   .variable_pointers = true,
};
entry_point = spirv_to_nir(spirv, module->size / 4,
   spec_entries, num_spec_entries,
-- 
2.13.2

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Re: [Mesa-dev] [PATCH 06/13] i965: Use I915_EXEC_NO_RELOC

[Kenneth Graunke]

On Wednesday, July 19, 2017 3:09:14 AM PDT Chris Wilson wrote:
> If we correctly fill the batch with the right relocation value, and that
> matches the expected location of the object, we can then tell the kernel
> it can forgo checking each individual relocation by only checking
> whether the object moved.
> 
> v2: Rebase to apply ahead of I915_EXEC_HANDLE_LUT
> 
> Signed-off-by: Chris Wilson 
> Cc: Kenneth Graunke 
> Cc: Matt Turner 
> Cc: Jason Ekstrand 
> ---
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c | 54 
> +--
>  1 file changed, 42 insertions(+), 12 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index a358269d9b..ac6fa080e1 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -517,19 +517,19 @@ throttle(struct brw_context *brw)
>  
>  #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
>  
> -static void
> +static unsigned int
>  add_exec_bo(struct intel_batchbuffer *batch, struct brw_bo *bo)
>  {
> if (bo != batch->bo) {
>unsigned int index = READ_ONCE(bo->index);
>  
>if (index < batch->exec_count && batch->exec_bos[index] == bo)
> - return;
> + return index;
>  
>/* May have been shared between multiple active batches */
>for (index = 0; index < batch->exec_count; index++) {
>   if (batch->exec_bos[index] == bo)
> -return;
> +return index;
>}
>  
>brw_bo_reference(bo);
> @@ -563,8 +563,9 @@ add_exec_bo(struct intel_batchbuffer *batch, struct 
> brw_bo *bo)
>  
> bo->index = batch->exec_count;
> batch->exec_bos[batch->exec_count] = bo;
> -   batch->exec_count++;
> batch->aperture_space += bo->size;
> +
> +   return batch->exec_count++;
>  }
>  
>  static int
> @@ -642,12 +643,25 @@ do_flush_locked(struct brw_context *brw, int 
> in_fence_fd, int *out_fence_fd)
> }
>  
> if (!brw->screen->no_hw) {
> -  int flags;
> -
> +  unsigned int flags;
> +
> +  /* The requirement for using I915_EXEC_NO_RELOC are:
> +   *
> +   *   The addresses written in the objects must match the corresponding
> +   *   reloc.presumed_offset which in turn must match the corresponding
> +   *   execobject.offset.
> +   *
> +   *   Any render targets written to in the batch must be flagged with
> +   *   EXEC_OBJECT_WRITE.
> +   *
> +   *   To avoid stalling, execobject.offset should match the current
> +   *   address of that object within the active context.
> +   */
> +  flags = I915_EXEC_NO_RELOC;
>if (brw->gen >= 6 && batch->ring == BLT_RING) {
> - flags = I915_EXEC_BLT;
> + flags |= I915_EXEC_BLT;
>} else {
> - flags = I915_EXEC_RENDER;
> + flags |= I915_EXEC_RENDER;
>}
>if (batch->needs_sol_reset)
>flags |= I915_EXEC_GEN7_SOL_RESET;
> @@ -783,16 +797,32 @@ __brw_emit_reloc(struct intel_batchbuffer *batch, 
> uint32_t batch_offset,
> assert(batch_offset <= BATCH_SZ - sizeof(uint32_t));
> assert(_mesa_bitcount(write_domain) <= 1);
>  
> -   if (target != batch->bo)
> -  add_exec_bo(batch, target);
> +   uint64_t offset64;
> +   if (target != batch->bo) {
> +  unsigned int index = add_exec_bo(batch, target);
> +  struct drm_i915_gem_exec_object2 *exec = &batch->exec_objects[index];
> +
> +  if (write_domain) {
> + exec->flags |= EXEC_OBJECT_WRITE;
> +
> + /* PIPECONTROL needs a w/a on gen6 */
> + if (write_domain == I915_GEM_DOMAIN_INSTRUCTION) {
> +struct brw_context *brw = container_of(batch, brw, batch);
> +if (brw->gen == 6)
> +   exec->flags |= EXEC_OBJECT_NEEDS_GTT;
> + }
> +  }
> +
> +  offset64 = exec->offset;
> +   } else {
> +  offset64 = target->offset64;
> +   }
>  
> struct drm_i915_gem_relocation_entry *reloc =
>&batch->relocs[batch->reloc_count];
>  
> batch->reloc_count++;
>  
> -   /* ensure gcc doesn't reload */
> -   uint64_t offset64 = *((volatile uint64_t *)&target->offset64);
> reloc->offset = batch_offset;
> reloc->delta = target_offset;
> reloc->target_handle = target->gem_handle;
> 

Looks solid - by pulling the presumed offset from the validation list,
you guarantee that the validation entry and reloc entries will always
match.  You can't do that for the batch, but there are no threading
issues with the batch BO because they're only used in one context.

Reviewed-by: Kenneth Graunke 

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Re: [Mesa-dev] [PATCH 01/13] i965: Assert that 64b immediate writes are correctly aligned

[Kenneth Graunke]

On Wednesday, July 19, 2017 3:09:09 AM PDT Chris Wilson wrote:
> The HW can only write a 64b immediate into a 64b aligned address, so
> add an assert.
> 
> Signed-off-by: Chris Wilson 
> ---
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index 28c2f474c0..7af7d9b0a3 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -1014,6 +1014,7 @@ brw_store_data_imm64(struct brw_context *brw, struct 
> brw_bo *bo,
>   uint32_t offset, uint64_t imm)
>  {
> assert(brw->gen >= 6);
> +   assert((offset & 7) == 0);
>  
> BEGIN_BATCH(5);
> OUT_BATCH(MI_STORE_DATA_IMM | (5 - 2));
> 

Reviewed-by: Kenneth Graunke 

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Re: [Mesa-dev] [PATCH] mesa: check API profile for GL_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION

[Ian Romanick]

On 07/19/2017 07:21 AM, Brian Paul wrote:
> On 07/18/2017 05:28 PM, Ian Romanick wrote:
>> On 07/18/2017 01:20 PM, Brian Paul wrote:
>>> If we have a compat profile context, it means that GL_QUADS[_STRIP] are
>>> supported so this query makes sense.  It's also legal for 3.2 core
>>> profile
>>> because of a spec bug.
>>
>> Do you know of any apps that depend on that spec bug?
> 
> No.  I was only trying to clear up the piglit
> arb_provoking_vertex/quads-follow-provoking-vertex.c failure.
> 
>>  In most similar
>> cases, we've taken the later spec as a clarification, and we've just
>> done what the later spec says.  That has happened a lot.  Table 6.45
>> seems to be the only place in the 3.2 core profile spec that mentions
>> it, and appendix section E.2.2. does say that QUADS and QUAD_STRIP are
>> removed.
> 
> I'd be OK with that.  But apparently, NVIDIA allows the query in 3.2
> core.  I was aligning with that.

I'd be inclined to only allow it in compat profiles, but I don't feel
that strongly about it.  Either way,

Reviewed-by: Ian Romanick 

> -Brian
> 
>>
>>> ---
>>>   src/mesa/main/get.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
>>> index 825ea34..68f520f 100644
>>> --- a/src/mesa/main/get.c
>>> +++ b/src/mesa/main/get.c
>>> @@ -1302,7 +1302,7 @@ check_extra(struct gl_context *ctx, const char
>>> *func, const struct value_desc *d
>>>break;
>>> case EXTRA_EXT_PROVOKING_VERTEX_32:
>>>api_check = TRUE;
>>> - if (version <= 32)
>>> + if (ctx->API == API_OPENGL_COMPAT || version == 32)
>>>   api_found = ctx->Extensions.EXT_provoking_vertex;
>>>break;
>>> case EXTRA_END:
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Re: [Mesa-dev] [PATCH] egl: Add MKDIR_GEN definition

[Nick Sarnie]

Hi all,

On Wed, Jul 19, 2017 at 4:57 AM, Daniel Stone  wrote:
> Adding linux-dmabuf Wayland protocol files as generated did the right
> thing, by prepending $(MKDIR_GEN) so autotools didn't try to write into
> a build directory which didn't yet exist.
>
> Unfortunately MKDIR_GEN needs to be defined in every Makefile it's used
> in, and src/egl/ didn't actually have it. As unset variables expand to
> NULL, it was silently being skipped.
>
> Copy & paste the defintion to make sure drivers/dri2/ exists before we
> try to generate files into it.
>
> Signed-off-by: Daniel Stone 
> Reported-by: Nick Sarnie 
> Reported-by: Mike Lothian 

Tested-by: Nick Sarnie 

> Fixes: 02cc35937277 ("egl/wayland: Use linux-dmabuf interface for buffers")
> ---
>  src/egl/Makefile.am | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
> index 19295de3ed..52ded15145 100644
> --- a/src/egl/Makefile.am
> +++ b/src/egl/Makefile.am
> @@ -21,6 +21,8 @@
>
>  include Makefile.sources
>
> +MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D)
> +
>  BUILT_SOURCES =
>
>  AM_CFLAGS = \
> --
> 2.13.2
>

Thanks for looking into it!

Sarnex
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[Mesa-dev] [PATCH] egl: fix check for KHR_no_error vs debug/robustness

[Grigori Goronzy]

The check is too aggressive and might also fail if context flags
appear after the no-error attribute in the context attribute list.

Delay the check to after attribute parsing to fix this.
---
This was found by the piglit test I just sent to the piglit ML. I promise,
next time I'll write tests before writing any code that touches public
interfaces. :)

 src/egl/main/eglcontext.c | 21 ++---
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index 1a8e9bd..1b03160 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -328,17 +328,6 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay 
*dpy,
 break;
  }
 
- /* The EGL_KHR_create_context_no_error spec says:
-  *
-  *"BAD_MATCH is generated if the EGL_CONTEXT_OPENGL_NO_ERROR_KHR 
is TRUE at
-  *the same time as a debug or robustness context is specified."
-  */
- if (ctx->Flags & EGL_CONTEXT_OPENGL_DEBUG_BIT_KHR ||
- ctx->Flags & EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR) {
-err = EGL_BAD_MATCH;
-break;
- }
-
  /* Canonicalize value to EGL_TRUE/EGL_FALSE definitions */
  ctx->NoError = !!val;
  break;
@@ -489,6 +478,16 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay 
*dpy,
   break;
}
 
+   /* The EGL_KHR_create_context_no_error spec says:
+*
+*"BAD_MATCH is generated if the EGL_CONTEXT_OPENGL_NO_ERROR_KHR is 
TRUE at
+*the same time as a debug or robustness context is specified."
+*/
+   if (ctx->NoError && (ctx->Flags & EGL_CONTEXT_OPENGL_DEBUG_BIT_KHR ||
+ctx->Flags & 
EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR)) {
+  err = EGL_BAD_MATCH;
+   }
+
if ((ctx->Flags & ~(EGL_CONTEXT_OPENGL_DEBUG_BIT_KHR
   | EGL_CONTEXT_OPENGL_FORWARD_COMPATIBLE_BIT_KHR
   | EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR)) != 0) {
-- 
2.7.4

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Re: [Mesa-dev] [7.5/22] i965/wm: Fix number of layers in 3D images

[Kenneth Graunke]

On Wednesday, July 19, 2017 12:53:45 PM PDT Topi Pohjolainen wrote:
> CC: mesa-sta...@lists.freedesktop.org
> CC: Kenneth Graunke 
> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 +---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index ab6b9cdd29..bc06949116 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -1632,6 +1632,17 @@ update_buffer_image_param(struct brw_context *brw,
> param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
>  }
>  
> +static unsigned
> +get_image_num_layers(const struct intel_mipmap_tree *mt, GLenum target,
> + unsigned level)
> +{
> +   if (target == GL_TEXTURE_CUBE_MAP)
> +  return 6;
> +
> +   return target == GL_TEXTURE_3D ?
> +  minify(mt->logical_depth0, level) : mt->logical_depth0;
> +}
> +
>  static void
>  update_image_surface(struct brw_context *brw,
>   struct gl_image_unit *u,
> @@ -1660,9 +1671,8 @@ update_image_surface(struct brw_context *brw,
>} else {
>   struct intel_texture_object *intel_obj = intel_texture_object(obj);
>   struct intel_mipmap_tree *mt = intel_obj->mt;
> - const unsigned num_layers = (!u->Layered ? 1 :
> -  obj->Target == GL_TEXTURE_CUBE_MAP ? 6 
> :
> -  mt->logical_depth0);
> + const unsigned num_layers = u->Layered ?
> +get_image_num_layers(mt, obj->Target, u->Level) : 1;
>  
>   struct isl_view view = {
>  .format = format,
> 

Reviewed-by: Kenneth Graunke 

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Re: [Mesa-dev] [PATCH v4 00/18] anv: Do CCS resolves at layout transitions

[Nanley Chery]

On Wed, Jul 19, 2017 at 02:21:52PM -0700, Nanley Chery wrote:
> In this revision:
> * review feedback is incorporated.
> * a couple of bugs caught by a new dEQP version are fixed: 
>   - image data could be lost if CCS_D wasn't enabled in render passes
> before we started doing explicit layout transitions on images with
> that auxiliary buffer.
>   - subpass resolves with multisampled images ignored CCS_D.
> * the Haswell boxes in jenkins start to GPU hang, but the don't do so
>   on my local machine.

To be more specific, hanging is observed sporadically but each run
returns failures. I'm not sure if the failure list is the same every
time. Here's the list of failures from my last run:

dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.a2b10g10r10_unorm_pack32.r16_unorm.optimal_optimal_nearest.hswm64
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.r16_unorm.r8g8b8a8_unorm.general_general_linear.hswm64
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.r16g16b16_snorm.a2b10g10r10_unorm_pack32.optimal_general_linear.hswm64
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.r16g16b16a16_sfloat.a2r10g10b10_unorm_pack32.optimal_optimal_linear.hswm64
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.r32g32_sfloat.r8_unorm.general_general_linear.hswm64
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.r8_snorm.b8g8r8a8_unorm.optimal_general_linear.hswm64
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.r8g8b8_unorm.r8g8b8a8_snorm.general_general_linear.hswm64
dEQP-VK.api.copy_and_blit.dedicated_allocation.image_to_image.all_formats.color.a8b8g8r8_srgb_pack32.r8g8b8a8_unorm.optimal_general.hswm64
dEQP-VK.api.image_clearing.core.clear_color_image.2d_r32_sint_multiple_layers.hswm64
dEQP-VK.api.image_clearing.core.clear_color_image.2d_r32g32b32_uint_multiple_layers.hswm64
dEQP-VK.api.image_clearing.dedicated_allocation.clear_color_image.2d_r32g32b32_uint_multiple_layers.hswm64

> 
> Nanley Chery (18):
>   anv: Transition MCS buffers from the undefined layout
>   intel/isl: Add surface state clear value information
>   anv/image: Disable CCS if the image doesn't support rendering
>   anv/image: Append CCS/MCS with a fast-clear state buffer
>   anv/cmd_buffer: Initialize the clear values buffer
>   anv/cmd_buffer: Don't partially fast clear image layers
>   anv/cmd_buffer: Restrict fast clears in the GENERAL layout
>   anv/gpu_memcpy: Add a lighter-weight GPU memcpy function
>   anv/cmd_buffer: Ensure fast-clear values are current
>   anv/cmd_buffer: Disable CCS on gen7 color attachments upfront
>   anv/cmd_buffer: Always enable CCS_D in render passes
>   anv/cmd_buffer: Move aux_usage assignment up
>   anv/cmd_buffer: Warn about not enabling CCS_E
>   anv: Transition more color buffer layouts
>   anv: Stop resolving CCS implicitly
>   anv/cmd_buffer: Skip some input attachment transitions
>   intel/blorp: Allow BLORP calls to be predicated
>   anv: Predicate fast-clear resolves
> 
>  src/intel/blorp/blorp.h|   3 +
>  src/intel/blorp/blorp_genX_exec.h  |   3 +
>  src/intel/isl/isl.c|   9 +
>  src/intel/isl/isl.h|   4 +
>  src/intel/vulkan/anv_blorp.c   | 183 ++-
>  src/intel/vulkan/anv_genX.h|   5 +
>  src/intel/vulkan/anv_image.c   |  93 ++
>  src/intel/vulkan/anv_pass.c|  36 ++-
>  src/intel/vulkan/anv_private.h |  37 ++-
>  src/intel/vulkan/genX_cmd_buffer.c | 626 
> -
>  src/intel/vulkan/genX_gpu_memcpy.c |  40 +++
>  11 files changed, 783 insertions(+), 256 deletions(-)
> 
> -- 
> 2.13.3
> 
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[Mesa-dev] [PATCH v4 18/18] anv: Predicate fast-clear resolves

[Nanley Chery]

Image layouts only let us know that an image *may* be fast-cleared. For
this reason we can end up with redundant resolves. Testing has shown
that such resolves can measurably hurt performance and that predicating
them can avoid the penalty.

v2:
- Introduce additional resolve state management function (Jason Ekstrand).
- Enable easy retrieval of fast clear state fields.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_blorp.c   |   3 +-
 src/intel/vulkan/anv_private.h |  13 ++--
 src/intel/vulkan/genX_cmd_buffer.c | 120 +
 3 files changed, 120 insertions(+), 16 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index e9b2ccbbdf..ba34cec0bd 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1628,7 +1628,8 @@ anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
   return;
 
struct blorp_batch batch;
-   blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
+   blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
+BLORP_BATCH_PREDICATE_ENABLE);
 
struct blorp_surf surf;
get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index e7b47ead36..588bf732df 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2090,11 +2090,16 @@ anv_fast_clear_state_entry_size(const struct anv_device 
*device)
 {
assert(device);
/* Entry contents:
-*   +--+
-*   | clear value dword(s) |
-*   +--+
+*   ++
+*   | clear value dword(s) | needs resolve dword |
+*   ++
 */
-   return device->isl_dev.ss.clear_value_size;
+
+   /* Ensure that the needs resolve dword is in fact dword-aligned to enable
+* GPU memcpy operations.
+*/
+   assert(device->isl_dev.ss.clear_value_size % 4 == 0);
+   return device->isl_dev.ss.clear_value_size + 4;
 }
 
 /* Returns true if a HiZ-enabled depth buffer can be sampled from. */
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 611e77bddb..c4d67fe8c1 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -407,21 +407,92 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
   anv_gen8_hiz_op_resolve(cmd_buffer, image, hiz_op);
 }
 
+enum fast_clear_state_field {
+   FAST_CLEAR_STATE_FIELD_CLEAR,
+   FAST_CLEAR_STATE_FIELD_RESOLVE,
+};
+
 static inline uint32_t
-get_fast_clear_state_entry_offset(const struct anv_device *device,
-  const struct anv_image *image,
-  unsigned level)
+get_fast_clear_state_offset(const struct anv_device *device,
+const struct anv_image *image,
+unsigned level, enum fast_clear_state_field field)
 {
assert(device && image);
assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
assert(level < anv_image_aux_levels(image));
-   const uint32_t offset = image->offset + image->aux_surface.offset +
-   image->aux_surface.isl.size +
-   anv_fast_clear_state_entry_size(device) * level;
+   uint32_t offset = image->offset + image->aux_surface.offset +
+ image->aux_surface.isl.size +
+ anv_fast_clear_state_entry_size(device) * level;
+
+   switch (field) {
+   case FAST_CLEAR_STATE_FIELD_RESOLVE:
+  offset += device->isl_dev.ss.clear_value_size;
+  /* Fall-through */
+   case FAST_CLEAR_STATE_FIELD_CLEAR:
+  break;
+   }
+
assert(offset < image->offset + image->size);
return offset;
 }
 
+#define MI_PREDICATE_SRC0  0x2400
+#define MI_PREDICATE_SRC1  0x2408
+
+/* Manages the state of an color image subresource to ensure resolves are
+ * performed properly.
+ */
+static void
+genX(set_image_needs_resolve)(struct anv_cmd_buffer *cmd_buffer,
+const struct anv_image *image,
+unsigned level, bool needs_resolve)
+{
+   assert(cmd_buffer && image);
+   assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
+   assert(level < anv_image_aux_levels(image));
+
+   const uint32_t resolve_flag_offset =
+  get_fast_clear_state_offset(cmd_buffer->device, image, level,
+  FAST_CLEAR_STATE_FIELD_RESOLVE);
+
+   /* The HW docs say that there is no way to guarantee the completion of
+* the following command. We use it nevertheless because it shows no
+* issues in testing is currently being used in the GL driver.
+*/
+   anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
+  sdi.Address = (struct anv_address) { image->bo, resolve_flag_offset };
+  sdi.ImmediateData = needs_resolve;
+   }
+}
+
+static void
+g

[Mesa-dev] [PATCH v4 17/18] intel/blorp: Allow BLORP calls to be predicated

[Nanley Chery]

Signed-off-by: Nanley Chery 
---
 src/intel/blorp/blorp.h   | 3 +++
 src/intel/blorp/blorp_genX_exec.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index d5226c2248..1e96fb42b0 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -75,6 +75,9 @@ enum blorp_batch_flags {
 * hardware.
 */
BLORP_BATCH_NO_EMIT_DEPTH_STENCIL = (1 << 0),
+
+   /* This flag indicates that the blorp call should be predicated. */
+   BLORP_BATCH_PREDICATE_ENABLE  = (1 << 1),
 };
 
 struct blorp_batch {
diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 91c0756bf3..93534169ef 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1543,6 +1543,9 @@ blorp_exec(struct blorp_batch *batch, const struct 
blorp_params *params)
blorp_emit(batch, GENX(3DPRIMITIVE), prim) {
   prim.VertexAccessType = SEQUENTIAL;
   prim.PrimitiveTopologyType = _3DPRIM_RECTLIST;
+#if GEN_GEN >= 7
+  prim.PredicateEnable = batch->flags & BLORP_BATCH_PREDICATE_ENABLE;
+#endif
   prim.VertexCountPerInstance = 3;
   prim.InstanceCount = params->num_layers;
}
-- 
2.13.3

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[Mesa-dev] [PATCH v4 11/18] anv/cmd_buffer: Always enable CCS_D in render passes

[Nanley Chery]

The lifespan of the fast-clear data will surpass the render pass scope.
We need CCS_D to be enabled in order to invalidate blocks previously
marked as cleared and to sample cleared data correctly.

v2: Avoid refactoring.
v3: Allow CCS_D for subpass resolves.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_blorp.c   | 26 +++---
 src/intel/vulkan/genX_cmd_buffer.c |  5 +
 2 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index d6cbc1c0cd..88dbba8a12 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1359,8 +1359,10 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer 
*cmd_buffer)
 static void
 resolve_image(struct blorp_batch *batch,
   const struct anv_image *src_image,
+  enum isl_aux_usage src_aux_usage,
   uint32_t src_level, uint32_t src_layer,
   const struct anv_image *dst_image,
+  enum isl_aux_usage dst_aux_usage,
   uint32_t dst_level, uint32_t dst_layer,
   VkImageAspectFlags aspect_mask,
   uint32_t src_x, uint32_t src_y, uint32_t dst_x, uint32_t dst_y,
@@ -1377,9 +1379,9 @@ resolve_image(struct blorp_batch *batch,
 
   struct blorp_surf src_surf, dst_surf;
   get_blorp_surf_for_anv_image(src_image, aspect,
-   src_image->aux_usage, &src_surf);
+   src_aux_usage, &src_surf);
   get_blorp_surf_for_anv_image(dst_image, aspect,
-   dst_image->aux_usage, &dst_surf);
+   dst_aux_usage, &dst_surf);
 
   blorp_blit(batch,
  &src_surf, src_level, src_layer,
@@ -1419,9 +1421,11 @@ void anv_CmdResolveImage(
 
   for (uint32_t layer = 0; layer < layer_count; layer++) {
  resolve_image(&batch,
-   src_image, pRegions[r].srcSubresource.mipLevel,
+   src_image, src_image->aux_usage,
+   pRegions[r].srcSubresource.mipLevel,
pRegions[r].srcSubresource.baseArrayLayer + layer,
-   dst_image, pRegions[r].dstSubresource.mipLevel,
+   dst_image, dst_image->aux_usage,
+   pRegions[r].dstSubresource.mipLevel,
pRegions[r].dstSubresource.baseArrayLayer + layer,
pRegions[r].dstSubresource.aspectMask,
pRegions[r].srcOffset.x, pRegions[r].srcOffset.y,
@@ -1606,8 +1610,11 @@ ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
cmd_buffer->state.pending_pipe_bits |=
   ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
 
+   const uint32_t aux_layers =
+  anv_image_aux_layers(image, iview->isl.base_level);
anv_ccs_resolve(cmd_buffer, att_state->color_rt_state, image,
-   iview->isl.base_level, fb->layers, resolve_op);
+   iview->isl.base_level, MIN2(fb->layers, aux_layers),
+   resolve_op);
 
cmd_buffer->state.pending_pipe_bits |=
   ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
@@ -1667,6 +1674,11 @@ anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer 
*cmd_buffer)
  struct anv_image_view *src_iview = fb->attachments[src_att];
  struct anv_image_view *dst_iview = fb->attachments[dst_att];
 
+ enum isl_aux_usage src_aux_usage =
+cmd_buffer->state.attachments[src_att].aux_usage;
+ enum isl_aux_usage dst_aux_usage =
+cmd_buffer->state.attachments[dst_att].aux_usage;
+
  const VkRect2D render_area = cmd_buffer->state.render_area;
 
  assert(src_iview->aspect_mask == dst_iview->aspect_mask);
@@ -1674,10 +1686,10 @@ anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer 
*cmd_buffer)
  struct blorp_batch batch;
  blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
 
- resolve_image(&batch, src_iview->image,
+ resolve_image(&batch, src_iview->image, src_aux_usage,
src_iview->isl.base_level,
src_iview->isl.base_array_layer,
-   dst_iview->image,
+   dst_iview->image, dst_aux_usage,
dst_iview->isl.base_level,
dst_iview->isl.base_array_layer,
src_iview->aspect_mask,
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 85938bd91b..42028e286d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -330,7 +330,7 @@ color_attachment_compute_aux_usage(struct anv_device * 
device,
if (iview->image->aux_usage == ISL_AUX_USAGE_CCS_E) {
   att_state->aux_usage = ISL_AUX_USAGE_CCS_E;
   att_state->input_aux_usage = ISL_AUX_USAGE_CCS_E;
-   } else if (att_state->fa

[Mesa-dev] [PATCH v4 16/18] anv/cmd_buffer: Skip some input attachment transitions

[Nanley Chery]

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/genX_cmd_buffer.c | 31 ++-
 1 file changed, 26 insertions(+), 5 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 7b2a3551b6..611e77bddb 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2763,14 +2763,12 @@ cmd_buffer_subpass_transition_layouts(struct 
anv_cmd_buffer * const cmd_buffer,
   * this is not the last use of the buffer. The layout should not have
   * changed from the first call and no transition is necessary.
   */
- assert(att_ref->layout == att_state->current_layout);
+ assert(att_state->current_layout == att_ref->layout ||
+att_state->current_layout ==
+VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL);
  continue;
   }
 
-  /* Get the appropriate target layout for this attachment. */
-  const VkImageLayout target_layout = subpass_end ?
- att_desc->final_layout : att_ref->layout;
-
   /* The attachment index must be less than the number of attachments
* within the framebuffer.
*/
@@ -2780,6 +2778,29 @@ cmd_buffer_subpass_transition_layouts(struct 
anv_cmd_buffer * const cmd_buffer,
  cmd_state->framebuffer->attachments[att_ref->attachment];
   const struct anv_image * const image = iview->image;
 
+  /* Get the appropriate target layout for this attachment. */
+  VkImageLayout target_layout;
+
+  /* A resolve is necessary before use as an input attachment if the clear
+   * color or auxiliary buffer usage isn't supported by the sampler.
+   */
+  const bool input_needs_resolve =
+(att_state->fast_clear && !att_state->clear_color_is_zero_one) ||
+att_state->input_aux_usage != att_state->aux_usage;
+  if (subpass_end) {
+ target_layout = att_desc->final_layout;
+  } else if (iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT &&
+ !input_needs_resolve) {
+ /* Layout transitions before the final only help to enable sampling as
+  * an input attachment. If the input attachment supports sampling
+  * using the auxiliary surface, we can skip such transitions by making
+  * the target layout one that is CCS-aware.
+  */
+ target_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
+  } else {
+ target_layout = att_ref->layout;
+  }
+
   /* Perform the layout transition. */
   if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
  transition_depth_buffer(cmd_buffer, image,
-- 
2.13.3

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[Mesa-dev] [PATCH v4 14/18] anv: Transition more color buffer layouts

[Nanley Chery]

v2: Expound on comment for the pipe controls (Jason Ekstrand).
v3:
- Cast base_layer to uint64_t to avoid overflow.
- Remove "seems" from the pipe control comment.
- Fix clamp of layer_count (Jason Ekstrand).

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_blorp.c   |   4 +-
 src/intel/vulkan/genX_cmd_buffer.c | 187 -
 2 files changed, 167 insertions(+), 24 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 88dbba8a12..5065f1fbc4 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1455,7 +1455,9 @@ anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
 
struct blorp_surf surf;
get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
-image->aux_usage, &surf);
+image->aux_usage == ISL_AUX_USAGE_NONE ?
+ISL_AUX_USAGE_CCS_D : image->aux_usage,
+&surf);
 
/* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
 *
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index e52ed74e29..7b2a3551b6 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -519,6 +519,17 @@ genX(copy_fast_clear_dwords)(struct anv_cmd_buffer 
*cmd_buffer,
}
 }
 
+/**
+ * @brief Transitions a color buffer from one layout to another.
+ *
+ * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
+ * more information.
+ *
+ * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
+ * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
+ *this represents the maximum layers to transition at each
+ *specified miplevel.
+ */
 static void
 transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
 const struct anv_image *image,
@@ -527,14 +538,27 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
 VkImageLayout initial_layout,
 VkImageLayout final_layout)
 {
-   assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
-
-   if (image->aux_surface.isl.size == 0 ||
-   base_level >= anv_image_aux_levels(image))
-  return;
-
-   if (initial_layout != VK_IMAGE_LAYOUT_UNDEFINED &&
-   initial_layout != VK_IMAGE_LAYOUT_PREINITIALIZED)
+   /* Validate the inputs. */
+   assert(cmd_buffer);
+   assert(image && image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
+   /* These values aren't supported for simplicity's sake. */
+   assert(level_count != VK_REMAINING_MIP_LEVELS &&
+  layer_count != VK_REMAINING_ARRAY_LAYERS);
+   /* Ensure the subresource range is valid. */
+   uint64_t last_level_num = base_level + level_count;
+   const uint32_t max_depth = anv_minify(image->extent.depth, base_level);
+   const uint32_t image_layers = MAX2(image->array_size, max_depth);
+   assert((uint64_t)base_layer + layer_count  <= image_layers);
+   assert(last_level_num <= image->levels);
+   /* The spec disallows these final layouts. */
+   assert(final_layout != VK_IMAGE_LAYOUT_UNDEFINED &&
+  final_layout != VK_IMAGE_LAYOUT_PREINITIALIZED);
+
+   /* No work is necessary if the layout stays the same or if this subresource
+* range lacks auxiliary data.
+*/
+   if (initial_layout == final_layout ||
+   base_layer >= anv_image_aux_layers(image, base_level))
   return;
 
/* A transition of a 3D subresource works on all slices at a time. */
@@ -545,25 +569,142 @@ transition_color_buffer(struct anv_cmd_buffer 
*cmd_buffer,
 
/* We're interested in the subresource range subset that has aux data. */
level_count = MIN2(level_count, anv_image_aux_levels(image) - base_level);
+   layer_count = MIN2(layer_count,
+  anv_image_aux_layers(image, base_level) - base_layer);
+   last_level_num = base_level + level_count;
 
-   /* We're transitioning from an undefined layout. We must ensure that the
-* clear values buffer is filled with valid data.
+   /* Record whether or not the layout is undefined. Pre-initialized images
+* with auxiliary buffers have a non-linear layout and are thus undefined.
 */
-   for (unsigned l = 0; l < level_count; l++)
-  init_fast_clear_state_entry(cmd_buffer, image, base_level + l);
-
-   if (image->aux_usage == ISL_AUX_USAGE_CCS_E ||
-   image->samples == 2 || image->samples == 8) {
-  /* We're transitioning from an undefined layout so it doesn't really
-   * matter what data ends up in the color buffer. We do, however, need to
-   * ensure that the auxiliary surface is not in an undefined state. This
-   * state is possible for CCS buffers SKL+ and MCS buffers with certain
-   * sample counts. One easy way to get to a valid state is to fast-clear
-   * the specified range.
+   assert(image->tiling == VK_IMAGE_TILING_OPTIMAL);
+  

[Mesa-dev] [PATCH v4 10/18] anv/cmd_buffer: Disable CCS on gen7 color attachments upfront

[Nanley Chery]

The next patch enables the use of CCS_D even when the color attachment
will not be fast-cleared. Catch the gen7 case early to simplify the
changes required.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/genX_cmd_buffer.c | 16 +---
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index bae1f00c02..85938bd91b 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -239,7 +239,11 @@ color_attachment_compute_aux_usage(struct anv_device * 
device,
struct anv_attachment_state *att_state = &cmd_state->attachments[att];
struct anv_image_view *iview = cmd_state->framebuffer->attachments[att];
 
-   if (iview->image->aux_surface.isl.size == 0) {
+   if (iview->isl.base_array_layer >=
+   anv_image_aux_layers(iview->image, iview->isl.base_level)) {
+  /* There is no aux buffer which corresponds to the level and layer(s)
+   * being accessed.
+   */
   att_state->aux_usage = ISL_AUX_USAGE_NONE;
   att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
   att_state->fast_clear = false;
@@ -275,16 +279,6 @@ color_attachment_compute_aux_usage(struct anv_device * 
device,
   render_area.extent.height != iview->extent.height)
  att_state->fast_clear = false;
 
-  if (GEN_GEN <= 7) {
- /* On gen7, we can't do multi-LOD or multi-layer fast-clears.  We
-  * technically can, but it comes with crazy restrictions that we
-  * don't want to deal with now.
-  */
- if (iview->isl.base_level > 0 ||
- iview->isl.base_array_layer > 0)
-att_state->fast_clear = false;
-  }
-
   /* On Broadwell and earlier, we can only handle 0/1 clear colors */
   if (GEN_GEN <= 8 && !att_state->clear_color_is_zero_one)
  att_state->fast_clear = false;
-- 
2.13.3

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[Mesa-dev] [PATCH v4 09/18] anv/cmd_buffer: Ensure fast-clear values are current

[Nanley Chery]

v2: Rewrite functions, change location of synchronization.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/genX_cmd_buffer.c | 114 +
 1 file changed, 114 insertions(+)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index d09b820d09..bae1f00c02 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -483,6 +483,51 @@ init_fast_clear_state_entry(struct anv_cmd_buffer 
*cmd_buffer,
}
 }
 
+/* Copy the fast-clear value dword(s) between a surface state object and an
+ * image's fast clear state buffer.
+ */
+static void
+genX(copy_fast_clear_dwords)(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_state surface_state,
+ const struct anv_image *image,
+ unsigned level,
+ bool copy_from_surface_state)
+{
+   assert(cmd_buffer && image);
+   assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
+   assert(level < anv_image_aux_levels(image));
+
+   struct anv_bo *ss_bo =
+  &cmd_buffer->device->surface_state_pool.block_pool.bo;
+   uint32_t ss_clear_offset = surface_state.offset +
+  cmd_buffer->device->isl_dev.ss.clear_value_offset;
+   uint32_t entry_offset =
+  get_fast_clear_state_entry_offset(cmd_buffer->device, image, level);
+   unsigned copy_size = cmd_buffer->device->isl_dev.ss.clear_value_size;
+
+   if (copy_from_surface_state) {
+  genX(cmd_buffer_mi_memcpy)(cmd_buffer, image->bo, entry_offset,
+ ss_bo, ss_clear_offset, copy_size);
+   } else {
+  genX(cmd_buffer_mi_memcpy)(cmd_buffer, ss_bo, ss_clear_offset,
+ image->bo, entry_offset, copy_size);
+
+  /* Updating a surface state object may require that the state cache be
+   * invalidated. From the SKL PRM, Shared Functions -> State -> State
+   * Caching:
+   *
+   *Whenever the RENDER_SURFACE_STATE object in memory pointed to by
+   *the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
+   *modified [...], the L1 state cache must be invalidated to ensure
+   *the new surface or sampler state is fetched from system memory.
+   *
+   * In testing, SKL doesn't actually seem to need this, but HSW does.
+   */
+  cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
+   }
+}
+
 static void
 transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
 const struct anv_image *image,
@@ -2622,6 +2667,66 @@ cmd_buffer_subpass_transition_layouts(struct 
anv_cmd_buffer * const cmd_buffer,
}
 }
 
+/* Update the clear value dword(s) in surface state objects or the fast clear
+ * state buffer entry for the color attachments used in this subpass.
+ */
+static void
+cmd_buffer_subpass_sync_fast_clear_values(struct anv_cmd_buffer *cmd_buffer)
+{
+   assert(cmd_buffer && cmd_buffer->state.subpass);
+
+   const struct anv_cmd_state *state = &cmd_buffer->state;
+
+   /* Iterate through every color attachment used in this subpass. */
+   for (uint32_t i = 0; i < state->subpass->color_count; ++i) {
+
+  /* The attachment should be one of the attachments described in the
+   * render pass and used in the subpass.
+   */
+  const uint32_t a = state->subpass->color_attachments[i].attachment;
+  assert(a < state->pass->attachment_count);
+  if (a == VK_ATTACHMENT_UNUSED)
+ continue;
+
+  /* Store some information regarding this attachment. */
+  const struct anv_attachment_state *att_state = &state->attachments[a];
+  const struct anv_image_view *iview = state->framebuffer->attachments[a];
+  const struct anv_render_pass_attachment *rp_att =
+ &state->pass->attachments[a];
+
+  if (att_state->aux_usage == ISL_AUX_USAGE_NONE)
+ continue;
+
+  /* The fast clear state entry must be updated if a fast clear is going to
+   * happen. The surface state must be updated if the clear value from a
+   * prior fast clear may be needed.
+   */
+  if (att_state->pending_clear_aspects && att_state->fast_clear) {
+ /* Update the fast clear state entry. */
+ genX(copy_fast_clear_dwords)(cmd_buffer, att_state->color_rt_state,
+  iview->image, iview->isl.base_level,
+  true /* copy from ss */);
+  } else if (rp_att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD) {
+ /* The attachment may have been fast-cleared in a previous render
+  * pass and the value is needed now. Update the surface state(s).
+  *
+  * TODO: Do this only once per render pass instead of every subpass.
+  */
+ genX(copy_fast_clear_dwords)(cmd_buffer, att_state->color_rt_state,
+  iview->image, iview->isl.base_level,
+   

[Mesa-dev] [PATCH v4 15/18] anv: Stop resolving CCS implicitly

[Nanley Chery]

With an earlier patch from this series, resolves are additionally
performed on layout transitions. Remove the now unnecessary implicit
resolves within render passes.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_blorp.c   | 150 ++---
 src/intel/vulkan/anv_pass.c|  14 
 src/intel/vulkan/anv_private.h |  10 ---
 3 files changed, 5 insertions(+), 169 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 5065f1fbc4..e9b2ccbbdf 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1500,150 +1500,16 @@ anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
   ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
 }
 
-static void
-ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
-   uint32_t att)
-{
-   struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
-   struct anv_attachment_state *att_state =
-  &cmd_buffer->state.attachments[att];
-
-   if (att_state->aux_usage == ISL_AUX_USAGE_NONE ||
-   att_state->aux_usage == ISL_AUX_USAGE_MCS)
-  return; /* Nothing to resolve */
-
-   assert(att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||
-  att_state->aux_usage == ISL_AUX_USAGE_CCS_D);
-
-   struct anv_render_pass *pass = cmd_buffer->state.pass;
-   const uint32_t subpass_idx = anv_get_subpass_id(&cmd_buffer->state);
-
-   /* Scan forward to see what all ways this attachment will be used.
-* Ideally, we would like to resolve in the same subpass as the last write
-* of a particular attachment.  That way we only resolve once but it's
-* still hot in the cache.
-*/
-   bool found_draw = false;
-   enum anv_subpass_usage usage = 0;
-   for (uint32_t s = subpass_idx + 1; s < pass->subpass_count; s++) {
-  usage |= pass->attachments[att].subpass_usage[s];
-
-  if (usage & (ANV_SUBPASS_USAGE_DRAW | ANV_SUBPASS_USAGE_RESOLVE_DST)) {
- /* We found another subpass that draws to this attachment.  We'll
-  * wait to resolve until then.
-  */
- found_draw = true;
- break;
-  }
-   }
-
-   struct anv_image_view *iview = fb->attachments[att];
-   const struct anv_image *image = iview->image;
-   assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
-
-   enum blorp_fast_clear_op resolve_op = BLORP_FAST_CLEAR_OP_NONE;
-   if (!found_draw) {
-  /* This is the last subpass that writes to this attachment so we need to
-   * resolve here.  Ideally, we would like to only resolve if the storeOp
-   * is set to VK_ATTACHMENT_STORE_OP_STORE.  However, we need to ensure
-   * that the CCS bits are set to "resolved" because there may be copy or
-   * blit operations (which may ignore CCS) between now and the next time
-   * we render and we need to ensure that anything they write will be
-   * respected in the next render.  Unfortunately, the hardware does not
-   * provide us with any sort of "invalidate" pass that sets the CCS to
-   * "resolved" without writing to the render target.
-   */
-  if (iview->image->aux_usage != ISL_AUX_USAGE_CCS_E) {
- /* The image destination surface doesn't support compression outside
-  * the render pass.  We need a full resolve.
-  */
- resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
-  } else if (att_state->fast_clear) {
- /* We don't know what to do with clear colors outside the render
-  * pass.  We need a partial resolve. Only transparent black is
-  * built into the surface state object and thus no resolve is
-  * required for this case.
-  */
- if (att_state->clear_value.color.uint32[0] ||
- att_state->clear_value.color.uint32[1] ||
- att_state->clear_value.color.uint32[2] ||
- att_state->clear_value.color.uint32[3])
-resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
-  } else {
- /* The image "natively" supports all the compression we care about
-  * and we don't need to resolve at all.  If this is the case, we also
-  * don't need to resolve for any of the input attachment cases below.
-  */
-  }
-   } else if (usage & ANV_SUBPASS_USAGE_INPUT) {
-  /* Input attachments are clear-color aware so, at least on Sky Lake, we
-   * can frequently sample from them with no resolves at all.
-   */
-  if (att_state->aux_usage != att_state->input_aux_usage) {
- assert(att_state->input_aux_usage == ISL_AUX_USAGE_NONE);
- resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
-  } else if (!att_state->clear_color_is_zero_one) {
- /* Sky Lake PRM, Vol. 2d, RENDER_SURFACE_STATE::Red Clear Color:
-  *
-  *"If Number of Multisamples is MULTISAMPLECOUNT_1 AND if this RT
-  *is fast cleared with non-0/1 clear value, this RT must be
-  *partially resolved (refer to Partial Res

[Mesa-dev] [PATCH v4 13/18] anv/cmd_buffer: Warn about not enabling CCS_E

[Nanley Chery]

Use the performance warning infrastructure to provide helpful
information when testing applications.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/genX_cmd_buffer.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index ac40d3c5b9..e52ed74e29 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -270,16 +270,18 @@ color_attachment_compute_aux_usage(struct anv_device * 
device,
* also supports color compression.
*/
   if (isl_format_supports_ccs_e(&device->info, iview->isl.format)) {
- /* TODO: Consider using a heuristic to determine if temporarily 
enabling
-  * CCS_E for this image view would be beneficial.
-  *
-  * While fast-clear resolves and partial resolves are fairly cheap in 
the
+ att_state->input_aux_usage = ISL_AUX_USAGE_CCS_D;
+
+ /* While fast-clear resolves and partial resolves are fairly cheap in 
the
   * case where you render to most of the pixels, full resolves are not
   * because they potentially involve reading and writing the entire
   * framebuffer.  If we can't texture with CCS_E, we should leave it 
off and
   * limit ourselves to fast clears.
   */
- att_state->input_aux_usage = ISL_AUX_USAGE_CCS_D;
+ if (cmd_state->pass->attachments[att].first_subpass_layout ==
+ VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
+anv_perf_warn("Not temporarily enabling CCS_E.");
+ }
   } else {
  att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
   }
-- 
2.13.3

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[Mesa-dev] [PATCH v4 12/18] anv/cmd_buffer: Move aux_usage assignment up

[Nanley Chery]

For readability, bring the assignment of CCS closer to the assignment of
NONE and MCS.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/genX_cmd_buffer.c | 62 ++
 1 file changed, 30 insertions(+), 32 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 42028e286d..ac40d3c5b9 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -253,6 +253,36 @@ color_attachment_compute_aux_usage(struct anv_device * 
device,
   att_state->input_aux_usage = ISL_AUX_USAGE_MCS;
   att_state->fast_clear = false;
   return;
+   } else if (iview->image->aux_usage == ISL_AUX_USAGE_CCS_E) {
+  att_state->aux_usage = ISL_AUX_USAGE_CCS_E;
+  att_state->input_aux_usage = ISL_AUX_USAGE_CCS_E;
+   } else {
+  att_state->aux_usage = ISL_AUX_USAGE_CCS_D;
+  /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
+   *
+   *"If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
+   *setting is only allowed if Surface Format supported for Fast
+   *Clear. In addition, if the surface is bound to the sampling
+   *engine, Surface Format must be supported for Render Target
+   *Compression for surfaces bound to the sampling engine."
+   *
+   * In other words, we can only sample from a fast-cleared image if it
+   * also supports color compression.
+   */
+  if (isl_format_supports_ccs_e(&device->info, iview->isl.format)) {
+ /* TODO: Consider using a heuristic to determine if temporarily 
enabling
+  * CCS_E for this image view would be beneficial.
+  *
+  * While fast-clear resolves and partial resolves are fairly cheap in 
the
+  * case where you render to most of the pixels, full resolves are not
+  * because they potentially involve reading and writing the entire
+  * framebuffer.  If we can't texture with CCS_E, we should leave it 
off and
+  * limit ourselves to fast clears.
+  */
+ att_state->input_aux_usage = ISL_AUX_USAGE_CCS_D;
+  } else {
+ att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
+  }
}
 
assert(iview->image->aux_surface.isl.usage & ISL_SURF_USAGE_CCS_BIT);
@@ -316,38 +346,6 @@ color_attachment_compute_aux_usage(struct anv_device * 
device,
} else {
   att_state->fast_clear = false;
}
-
-   /**
-* TODO: Consider using a heuristic to determine if temporarily enabling
-* CCS_E for this image view would be beneficial.
-*
-* While fast-clear resolves and partial resolves are fairly cheap in the
-* case where you render to most of the pixels, full resolves are not
-* because they potentially involve reading and writing the entire
-* framebuffer.  If we can't texture with CCS_E, we should leave it off and
-* limit ourselves to fast clears.
-*/
-   if (iview->image->aux_usage == ISL_AUX_USAGE_CCS_E) {
-  att_state->aux_usage = ISL_AUX_USAGE_CCS_E;
-  att_state->input_aux_usage = ISL_AUX_USAGE_CCS_E;
-   } else {
-  att_state->aux_usage = ISL_AUX_USAGE_CCS_D;
-  /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
-   *
-   *"If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
-   *setting is only allowed if Surface Format supported for Fast
-   *Clear. In addition, if the surface is bound to the sampling
-   *engine, Surface Format must be supported for Render Target
-   *Compression for surfaces bound to the sampling engine."
-   *
-   * In other words, we can only sample from a fast-cleared image if it
-   * also supports color compression.
-   */
-  if (isl_format_supports_ccs_e(&device->info, iview->isl.format))
- att_state->input_aux_usage = ISL_AUX_USAGE_CCS_D;
-  else
- att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
-   }
 }
 
 static bool
-- 
2.13.3

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[Mesa-dev] [PATCH v4 07/18] anv/cmd_buffer: Restrict fast clears in the GENERAL layout

[Nanley Chery]

v2: Remove ::first_subpass_layout assertion (Jason Ekstrand).
v3: Allow some fast clears in the GENERAL layout.
v4: Remove extra '||' and adjust line break (Jason Ekstrand).

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_pass.c| 22 ++
 src/intel/vulkan/anv_private.h |  2 ++
 src/intel/vulkan/genX_cmd_buffer.c | 16 
 3 files changed, 40 insertions(+)

diff --git a/src/intel/vulkan/anv_pass.c b/src/intel/vulkan/anv_pass.c
index 1b30c1409d..ab0733fc10 100644
--- a/src/intel/vulkan/anv_pass.c
+++ b/src/intel/vulkan/anv_pass.c
@@ -34,6 +34,16 @@ num_subpass_attachments(const VkSubpassDescription *desc)
   (desc->pDepthStencilAttachment != NULL);
 }
 
+static void
+init_first_subpass_layout(struct anv_render_pass_attachment * const att,
+  const VkAttachmentReference att_ref)
+{
+   if (att->first_subpass_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
+  att->first_subpass_layout = att_ref.layout;
+  assert(att->first_subpass_layout != VK_IMAGE_LAYOUT_UNDEFINED);
+   }
+}
+
 VkResult anv_CreateRenderPass(
 VkDevice_device,
 const VkRenderPassCreateInfo*   pCreateInfo,
@@ -91,6 +101,7 @@ VkResult anv_CreateRenderPass(
   att->stencil_load_op = pCreateInfo->pAttachments[i].stencilLoadOp;
   att->initial_layout = pCreateInfo->pAttachments[i].initialLayout;
   att->final_layout = pCreateInfo->pAttachments[i].finalLayout;
+  att->first_subpass_layout = VK_IMAGE_LAYOUT_UNDEFINED;
   att->subpass_usage = subpass_usages;
   subpass_usages += pass->subpass_count;
}
@@ -119,6 +130,8 @@ VkResult anv_CreateRenderPass(
pass->attachments[a].subpass_usage[i] |= 
ANV_SUBPASS_USAGE_INPUT;
pass->attachments[a].last_subpass_idx = i;
 
+   init_first_subpass_layout(&pass->attachments[a],
+ desc->pInputAttachments[j]);
if (desc->pDepthStencilAttachment &&
a == desc->pDepthStencilAttachment->attachment)
   subpass->has_ds_self_dep = true;
@@ -138,6 +151,9 @@ VkResult anv_CreateRenderPass(
pass->attachments[a].usage |= 
VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
pass->attachments[a].subpass_usage[i] |= ANV_SUBPASS_USAGE_DRAW;
pass->attachments[a].last_subpass_idx = i;
+
+   init_first_subpass_layout(&pass->attachments[a],
+ desc->pColorAttachments[j]);
 }
  }
   }
@@ -162,6 +178,9 @@ VkResult anv_CreateRenderPass(
pass->attachments[a].subpass_usage[i] |=
   ANV_SUBPASS_USAGE_RESOLVE_DST;
pass->attachments[a].last_subpass_idx = i;
+
+   init_first_subpass_layout(&pass->attachments[a],
+ desc->pResolveAttachments[j]);
 }
  }
   }
@@ -176,6 +195,9 @@ VkResult anv_CreateRenderPass(
VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT;
 pass->attachments[a].subpass_usage[i] |= ANV_SUBPASS_USAGE_DRAW;
 pass->attachments[a].last_subpass_idx = i;
+
+init_first_subpass_layout(&pass->attachments[a],
+  *desc->pDepthStencilAttachment);
  }
   } else {
  subpass->depth_stencil_attachment.attachment = VK_ATTACHMENT_UNUSED;
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 3635bc8a1a..70eb3d8760 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1490,6 +1490,7 @@ struct anv_attachment_state {
bool fast_clear;
VkClearValue clear_value;
bool clear_color_is_zero_one;
+   bool clear_color_is_zero;
 };
 
 /** State required while building cmd buffer */
@@ -2308,6 +2309,7 @@ struct anv_render_pass_attachment {
VkAttachmentLoadOp   stencil_load_op;
VkImageLayoutinitial_layout;
VkImageLayoutfinal_layout;
+   VkImageLayoutfirst_subpass_layout;
 
/* An array, indexed by subpass id, of how the attachment will be used. */
enum anv_subpass_usage * subpass_usage;
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 3eef008e97..d09b820d09 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -255,6 +255,11 @@ color_attachment_compute_aux_usage(struct anv_device * 
device,
 
att_state->clear_color_is_zero_one =
   color_is_zero_one(att_state->clear_value.color, iview->isl.format);
+   att_state->clear_color_is_zero =
+  att_state->clear_value.color.uint32[

[Mesa-dev] [PATCH v4 05/18] anv/cmd_buffer: Initialize the clear values buffer

[Nanley Chery]

v2: Rewrite functions.
v3 (Jason Ekstrand):
- Don't set ResourceMinLOD.
- Fix clamp of level_count.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/genX_cmd_buffer.c | 79 +-
 1 file changed, 78 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 81972821d1..f180d7892d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -384,6 +384,73 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
   anv_gen8_hiz_op_resolve(cmd_buffer, image, hiz_op);
 }
 
+static inline uint32_t
+get_fast_clear_state_entry_offset(const struct anv_device *device,
+  const struct anv_image *image,
+  unsigned level)
+{
+   assert(device && image);
+   assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
+   assert(level < anv_image_aux_levels(image));
+   const uint32_t offset = image->offset + image->aux_surface.offset +
+   image->aux_surface.isl.size +
+   anv_fast_clear_state_entry_size(device) * level;
+   assert(offset < image->offset + image->size);
+   return offset;
+}
+
+static void
+init_fast_clear_state_entry(struct anv_cmd_buffer *cmd_buffer,
+const struct anv_image *image,
+unsigned level)
+{
+   assert(cmd_buffer && image);
+   assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
+   assert(level < anv_image_aux_levels(image));
+
+   /* The fast clear value dword(s) will be copied into a surface state object.
+* Ensure that the restrictions of the fields in the dword(s) are followed.
+*
+* CCS buffers on SKL+ can have any value set for the clear colors.
+*/
+   if (image->samples == 1 && GEN_GEN >= 9)
+  return;
+
+   /* Other combinations of auxiliary buffers and platforms require specific
+* values in the clear value dword(s).
+*/
+   unsigned i = 0;
+   for (; i < cmd_buffer->device->isl_dev.ss.clear_value_size; i += 4) {
+  anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
+ const uint32_t entry_offset =
+get_fast_clear_state_entry_offset(cmd_buffer->device, image, 
level);
+ sdi.Address = (struct anv_address) { image->bo, entry_offset + i };
+
+ if (GEN_GEN >= 9) {
+/* MCS buffers on SKL+ can only have 1/0 clear colors. */
+assert(image->aux_usage == ISL_AUX_USAGE_MCS);
+sdi.ImmediateData = 0;
+ } else if (GEN_VERSIONx10 >= 75) {
+/* Pre-SKL, the dword containing the clear values also contains
+ * other fields, so we need to initialize those fields to match the
+ * values that would be in a color attachment.
+ */
+assert(i == 0);
+sdi.ImmediateData = ISL_CHANNEL_SELECT_RED   << 25 |
+ISL_CHANNEL_SELECT_GREEN << 22 |
+ISL_CHANNEL_SELECT_BLUE  << 19 |
+ISL_CHANNEL_SELECT_ALPHA << 16;
+ }  else if (GEN_VERSIONx10 == 70) {
+/* On IVB, the dword containing the clear values also contains
+ * other fields that must be zero or can be zero.
+ */
+assert(i == 0);
+sdi.ImmediateData = 0;
+ }
+  }
+   }
+}
+
 static void
 transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
 const struct anv_image *image,
@@ -394,7 +461,8 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
 {
assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
 
-   if (image->aux_usage == ISL_AUX_USAGE_NONE)
+   if (image->aux_surface.isl.size == 0 ||
+   base_level >= anv_image_aux_levels(image))
   return;
 
if (initial_layout != VK_IMAGE_LAYOUT_UNDEFINED &&
@@ -407,6 +475,15 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
   layer_count = anv_minify(image->extent.depth, base_level);
}
 
+   /* We're interested in the subresource range subset that has aux data. */
+   level_count = MIN2(level_count, anv_image_aux_levels(image) - base_level);
+
+   /* We're transitioning from an undefined layout. We must ensure that the
+* clear values buffer is filled with valid data.
+*/
+   for (unsigned l = 0; l < level_count; l++)
+  init_fast_clear_state_entry(cmd_buffer, image, base_level + l);
+
if (image->aux_usage == ISL_AUX_USAGE_CCS_E ||
image->samples == 2 || image->samples == 8) {
   /* We're transitioning from an undefined layout so it doesn't really
-- 
2.13.3

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[Mesa-dev] [PATCH v4 08/18] anv/gpu_memcpy: Add a lighter-weight GPU memcpy function

[Nanley Chery]

We'll be performing a GPU memcpy in more places to copy small amounts of
data. Add an alternate function that thrashes less state.

v2:
- Make a new function (Jason Ekstrand).
- Move the #define into the function.
v3:
- Update the function name (Jason).
- Update comments.
v4: Use an indirect drawing register as TEMP_REG (Jason Ekstrand).

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_genX.h|  5 +
 src/intel/vulkan/genX_gpu_memcpy.c | 40 ++
 2 files changed, 45 insertions(+)

diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h
index 8da5e075dc..0b7322e281 100644
--- a/src/intel/vulkan/anv_genX.h
+++ b/src/intel/vulkan/anv_genX.h
@@ -69,5 +69,10 @@ void genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer 
*cmd_buffer,
 struct anv_bo *src, uint32_t src_offset,
 uint32_t size);
 
+void genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer *cmd_buffer,
+struct anv_bo *dst, uint32_t dst_offset,
+struct anv_bo *src, uint32_t src_offset,
+uint32_t size);
+
 void genX(blorp_exec)(struct blorp_batch *batch,
   const struct blorp_params *params);
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c 
b/src/intel/vulkan/genX_gpu_memcpy.c
index 5ef35e6283..db723d4a52 100644
--- a/src/intel/vulkan/genX_gpu_memcpy.c
+++ b/src/intel/vulkan/genX_gpu_memcpy.c
@@ -52,6 +52,46 @@ gcd_pow2_u64(uint64_t a, uint64_t b)
 }
 
 void
+genX(cmd_buffer_mi_memcpy)(struct anv_cmd_buffer *cmd_buffer,
+   struct anv_bo *dst, uint32_t dst_offset,
+   struct anv_bo *src, uint32_t src_offset,
+   uint32_t size)
+{
+   /* This memcpy operates in units of dwords. */
+   assert(size % 4 == 0);
+   assert(dst_offset % 4 == 0);
+   assert(src_offset % 4 == 0);
+
+   for (uint32_t i = 0; i < size; i += 4) {
+  const struct anv_address src_addr =
+ (struct anv_address) { src, src_offset + i};
+  const struct anv_address dst_addr =
+ (struct anv_address) { dst, dst_offset + i};
+#if GEN_GEN >= 8
+  anv_batch_emit(&cmd_buffer->batch, GENX(MI_COPY_MEM_MEM), cp) {
+ cp.DestinationMemoryAddress = dst_addr;
+ cp.SourceMemoryAddress = src_addr;
+  }
+#else
+  /* IVB does not have a general purpose register for command streamer
+   * commands. Therefore, we use an alternate temporary register.
+   */
+#define TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
+  anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), load) {
+ load.RegisterAddress = TEMP_REG;
+ load.MemoryAddress = src_addr;
+  }
+  anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), store) {
+ store.RegisterAddress = TEMP_REG;
+ store.MemoryAddress = dst_addr;
+  }
+#undef TEMP_REG
+#endif
+   }
+   return;
+}
+
+void
 genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
struct anv_bo *dst, uint32_t dst_offset,
struct anv_bo *src, uint32_t src_offset,
-- 
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[Mesa-dev] [PATCH v4 02/18] intel/isl: Add surface state clear value information

[Nanley Chery]

This will be used to load and store clear values from surface state
objects.

Signed-off-by: Nanley Chery 
---
 src/intel/isl/isl.c | 9 +
 src/intel/isl/isl.h | 4 
 2 files changed, 13 insertions(+)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 12ffe3bb51..cad736dd56 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -73,6 +73,15 @@ isl_device_init(struct isl_device *dev,
dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
dev->ss.align = isl_align(dev->ss.size, 32);
 
+   dev->ss.clear_value_size =
+  isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info) +
+RENDER_SURFACE_STATE_GreenClearColor_bits(info) +
+RENDER_SURFACE_STATE_BlueClearColor_bits(info) +
+RENDER_SURFACE_STATE_AlphaClearColor_bits(info), 32) / 8;
+
+   dev->ss.clear_value_offset =
+  RENDER_SURFACE_STATE_RedClearColor_start(info) / 32 * 4;
+
assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) % 8 == 0);
dev->ss.addr_offset =
   RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) / 8;
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index d81df31a37..c1605914dc 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -919,6 +919,10 @@ struct isl_device {
   uint8_t align;
   uint8_t addr_offset;
   uint8_t aux_addr_offset;
+
+  /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
+  uint8_t clear_value_size;
+  uint8_t clear_value_offset;
} ss;
 
/**
-- 
2.13.3

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[Mesa-dev] [PATCH v4 04/18] anv/image: Append CCS/MCS with a fast-clear state buffer

[Nanley Chery]

v2: Update comments, function signatures, and add assertions.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_image.c   | 78 ++
 src/intel/vulkan/anv_private.h | 12 +++
 2 files changed, 90 insertions(+)

diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index f33a445d1d..70a8c28bac 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -117,6 +117,82 @@ add_surface(struct anv_image *image, struct anv_surface 
*surf)
 }
 
 /**
+ * For color images that have an auxiliary surface, request allocation for an
+ * additional buffer that mainly stores fast-clear values. Use of this buffer
+ * allows us to access the image's subresources while being aware of their
+ * fast-clear values in non-trivial cases (e.g., outside of a render pass in
+ * which a fast clear has occurred).
+ *
+ * For the purpose of discoverability, the algorithm used to manage this buffer
+ * is described here. A clear value in this buffer is updated when a fast clear
+ * is performed on a subresource. One of two synchronization operations is
+ * performed in order for a following memory access to use the fast-clear
+ * value:
+ *a. Copy the value from the buffer to the surface state object used for
+ *   reading. This is done implicitly when the value is the clear value
+ *   predetermined to be the default in other surface state objects. This
+ *   is currently only done explicitly for the operation below.
+ *b. Do (a) and use the surface state object to resolve the subresource.
+ *   This is only done during layout transitions for decent performance.
+ *
+ * With the above scheme, we can fast-clear whenever the hardware allows except
+ * for two cases in which synchronization becomes impossible or undesirable:
+ ** The subresource is in the GENERAL layout and is cleared to a value
+ *  other than the special default value.
+ *
+ *  Performing a synchronization operation in order to read from the
+ *  subresource is undesirable in this case. Firstly, b) is not an option
+ *  because a layout transition isn't required between a write and read of
+ *  an image in the GENERAL layout. Secondly, it's undesirable to do a)
+ *  explicitly because it would require large infrastructural changes. The
+ *  Vulkan API supports us in deciding not to optimize this layout by
+ *  stating that using this layout may cause suboptimal performance. NOTE:
+ *  the auxiliary buffer must always be enabled to support a) implicitly.
+ *
+ *
+ ** For the given miplevel, only some of the layers are cleared at once.
+ *
+ *  If the user clears each layer to a different value, then tries to
+ *  render to multiple layers at once, we have no ability to perform a
+ *  synchronization operation in between. a) is not helpful because the
+ *  object can only hold one clear value. b) is not an option because a
+ *  layout transition isn't required in this case.
+ */
+static void
+add_fast_clear_state_buffer(struct anv_image *image,
+const struct anv_device *device)
+{
+   assert(image && device);
+   assert(image->aux_surface.isl.size > 0 &&
+  image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
+
+   /* The offset to the buffer of clear values must be dword-aligned for GPU
+* memcpy operations. It is located immediately after the auxiliary surface.
+*/
+
+   /* Tiled images are guaranteed to be 4K aligned, so the image alignment
+* should also be dword-aligned.
+*/
+   assert(image->alignment % 4 == 0);
+
+   /* Auxiliary buffers should be a multiple of 4K, so the start of the clear
+* values buffer should already be dword-aligned.
+*/
+   assert(image->aux_surface.isl.size % 4 == 0);
+
+   /* This buffer should be at the very end of the image. */
+   assert(image->size ==
+  image->aux_surface.offset + image->aux_surface.isl.size);
+
+   const unsigned entry_size = anv_fast_clear_state_entry_size(device);
+   /* There's no padding between entries, so ensure that they're always a
+* multiple of 32 bits in order to enable GPU memcpy operations.
+*/
+   assert(entry_size % 4 == 0);
+   image->size += entry_size * anv_image_aux_levels(image);
+}
+
+/**
  * Initialize the anv_image::*_surface selected by \a aspect. Then update the
  * image's memory requirements (that is, the image's size and alignment).
  *
@@ -230,6 +306,7 @@ make_surface(const struct anv_device *dev,
 }
 
 add_surface(image, &image->aux_surface);
+add_fast_clear_state_buffer(image, dev);
 
 /* For images created without MUTABLE_FORMAT_BIT set, we know that
  * they will always be used with the original format.  In
@@ -253,6 +330,7 @@ make_surface(const struct anv_device *dev,
  &image->aux_surface.isl);
   if (ok) {
  add_surface(image, &image->aux_sur

[Mesa-dev] [PATCH v4 03/18] anv/image: Disable CCS if the image doesn't support rendering

[Nanley Chery]

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_image.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 4f0057c952..f33a445d1d 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -214,6 +214,21 @@ make_surface(const struct anv_device *dev,
  ok = isl_surf_get_ccs_surf(&dev->isl_dev, &anv_surf->isl,
 &image->aux_surface.isl, 0);
  if (ok) {
+
+/* Disable CCS when it is not useful (i.e., when you can't render
+ * to the image with CCS enabled).
+ */
+if (!isl_format_supports_rendering(&dev->info, format)) {
+   /* While it may be technically possible to enable CCS for this
+* image, we currently don't have things hooked up to get it
+* working.
+*/
+   anv_perf_warn("This image format doesn't support rendering. "
+ "Not allocating an CCS buffer.");
+   image->aux_surface.isl.size = 0;
+   return VK_SUCCESS;
+}
+
 add_surface(image, &image->aux_surface);
 
 /* For images created without MUTABLE_FORMAT_BIT set, we know that
-- 
2.13.3

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[Mesa-dev] [PATCH v4 06/18] anv/cmd_buffer: Don't partially fast clear image layers

[Nanley Chery]

v2: Don't pass in the command buffer (Jason Ekstrand).
v3: Remove an incorrect assertion and an if condition for gen7.

Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/genX_cmd_buffer.c | 31 +++
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index f180d7892d..3eef008e97 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -231,12 +231,14 @@ color_is_zero_one(VkClearColorValue value, enum 
isl_format format)
 }
 
 static void
-color_attachment_compute_aux_usage(struct anv_device *device,
-   struct anv_attachment_state *att_state,
-   struct anv_image_view *iview,
-   VkRect2D render_area,
+color_attachment_compute_aux_usage(struct anv_device * device,
+   struct anv_cmd_state * cmd_state,
+   uint32_t att, VkRect2D render_area,
union isl_color_value *fast_clear_color)
 {
+   struct anv_attachment_state *att_state = &cmd_state->attachments[att];
+   struct anv_image_view *iview = cmd_state->framebuffer->attachments[att];
+
if (iview->image->aux_surface.isl.size == 0) {
   att_state->aux_usage = ISL_AUX_USAGE_NONE;
   att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
@@ -274,8 +276,7 @@ color_attachment_compute_aux_usage(struct anv_device 
*device,
   * don't want to deal with now.
   */
  if (iview->isl.base_level > 0 ||
- iview->isl.base_array_layer > 0 ||
- iview->isl.array_len > 1)
+ iview->isl.base_array_layer > 0)
 att_state->fast_clear = false;
   }
 
@@ -283,6 +284,21 @@ color_attachment_compute_aux_usage(struct anv_device 
*device,
   if (GEN_GEN <= 8 && !att_state->clear_color_is_zero_one)
  att_state->fast_clear = false;
 
+  /* We allow fast clears when all aux layers of the miplevel are targeted.
+   * See add_fast_clear_state_buffer() for more information. Also, because
+   * we only either do a fast clear or a normal clear and not both, this
+   * complies with the gen7 restriction of not fast-clearing multiple
+   * layers.
+   */
+  if (cmd_state->framebuffer->layers !=
+  anv_image_aux_layers(iview->image, iview->isl.base_level)) {
+ att_state->fast_clear = false;
+ if (GEN_GEN == 7) {
+anv_perf_warn("Not fast-clearing the first layer in "
+  "a multi-layer fast clear.");
+ }
+  }
+
   if (att_state->fast_clear) {
  memcpy(fast_clear_color->u32, att_state->clear_value.color.uint32,
 sizeof(fast_clear_color->u32));
@@ -617,8 +633,7 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer 
*cmd_buffer,
  union isl_color_value clear_color = { .u32 = { 0, } };
  if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
 color_attachment_compute_aux_usage(cmd_buffer->device,
-   &state->attachments[i],
-   iview, begin->renderArea,
+   state, i, begin->renderArea,
&clear_color);
 
 struct isl_view view = iview->isl;
-- 
2.13.3

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[Mesa-dev] [PATCH v4 01/18] anv: Transition MCS buffers from the undefined layout

[Nanley Chery]

Cc: 
Suggested-by: Jason Ekstrand 
Signed-off-by: Nanley Chery 
---
 src/intel/vulkan/anv_blorp.c   |  8 
 src/intel/vulkan/anv_private.h |  8 
 src/intel/vulkan/genX_cmd_buffer.c | 25 +++--
 3 files changed, 23 insertions(+), 18 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 459d57ec57..d6cbc1c0cd 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1434,10 +1434,10 @@ void anv_CmdResolveImage(
 }
 
 void
-anv_image_ccs_clear(struct anv_cmd_buffer *cmd_buffer,
-const struct anv_image *image,
-const uint32_t base_level, const uint32_t level_count,
-const uint32_t base_layer, uint32_t layer_count)
+anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ const uint32_t base_level, const uint32_t level_count,
+ const uint32_t base_layer, uint32_t layer_count)
 {
assert(image->type == VK_IMAGE_TYPE_3D || image->extent.depth == 1);
 
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 4dce360c76..9a5d2d6fa4 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2108,10 +2108,10 @@ anv_ccs_resolve(struct anv_cmd_buffer * const 
cmd_buffer,
 const enum blorp_fast_clear_op op);
 
 void
-anv_image_ccs_clear(struct anv_cmd_buffer *cmd_buffer,
-const struct anv_image *image,
-const uint32_t base_level, const uint32_t level_count,
-const uint32_t base_layer, uint32_t layer_count);
+anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ const uint32_t base_level, const uint32_t level_count,
+ const uint32_t base_layer, uint32_t layer_count);
 
 enum isl_aux_usage
 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 9b3bb10164..81972821d1 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -392,7 +392,9 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
 VkImageLayout initial_layout,
 VkImageLayout final_layout)
 {
-   if (image->aux_usage != ISL_AUX_USAGE_CCS_E)
+   assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
+
+   if (image->aux_usage == ISL_AUX_USAGE_NONE)
   return;
 
if (initial_layout != VK_IMAGE_LAYOUT_UNDEFINED &&
@@ -405,15 +407,18 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
   layer_count = anv_minify(image->extent.depth, base_level);
}
 
-#if GEN_GEN >= 9
-   /* We're transitioning from an undefined layout so it doesn't really matter
-* what data ends up in the color buffer.  We do, however, need to ensure
-* that the CCS has valid data in it.  One easy way to do that is to
-* fast-clear the specified range.
-*/
-   anv_image_ccs_clear(cmd_buffer, image, base_level, level_count,
-   base_layer, layer_count);
-#endif
+   if (image->aux_usage == ISL_AUX_USAGE_CCS_E ||
+   image->samples == 2 || image->samples == 8) {
+  /* We're transitioning from an undefined layout so it doesn't really
+   * matter what data ends up in the color buffer. We do, however, need to
+   * ensure that the auxiliary surface is not in an undefined state. This
+   * state is possible for CCS buffers SKL+ and MCS buffers with certain
+   * sample counts. One easy way to get to a valid state is to fast-clear
+   * the specified range.
+   */
+  anv_image_fast_clear(cmd_buffer, image, base_level, level_count,
+   base_layer, layer_count);
+   }
 }
 
 /**
-- 
2.13.3

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[Mesa-dev] [PATCH v4 00/18] anv: Do CCS resolves at layout transitions

[Nanley Chery]

In this revision:
* review feedback is incorporated.
* a couple of bugs caught by a new dEQP version are fixed: 
  - image data could be lost if CCS_D wasn't enabled in render passes
before we started doing explicit layout transitions on images with
that auxiliary buffer.
  - subpass resolves with multisampled images ignored CCS_D.
* the Haswell boxes in jenkins start to GPU hang, but the don't do so
  on my local machine.

Nanley Chery (18):
  anv: Transition MCS buffers from the undefined layout
  intel/isl: Add surface state clear value information
  anv/image: Disable CCS if the image doesn't support rendering
  anv/image: Append CCS/MCS with a fast-clear state buffer
  anv/cmd_buffer: Initialize the clear values buffer
  anv/cmd_buffer: Don't partially fast clear image layers
  anv/cmd_buffer: Restrict fast clears in the GENERAL layout
  anv/gpu_memcpy: Add a lighter-weight GPU memcpy function
  anv/cmd_buffer: Ensure fast-clear values are current
  anv/cmd_buffer: Disable CCS on gen7 color attachments upfront
  anv/cmd_buffer: Always enable CCS_D in render passes
  anv/cmd_buffer: Move aux_usage assignment up
  anv/cmd_buffer: Warn about not enabling CCS_E
  anv: Transition more color buffer layouts
  anv: Stop resolving CCS implicitly
  anv/cmd_buffer: Skip some input attachment transitions
  intel/blorp: Allow BLORP calls to be predicated
  anv: Predicate fast-clear resolves

 src/intel/blorp/blorp.h|   3 +
 src/intel/blorp/blorp_genX_exec.h  |   3 +
 src/intel/isl/isl.c|   9 +
 src/intel/isl/isl.h|   4 +
 src/intel/vulkan/anv_blorp.c   | 183 ++-
 src/intel/vulkan/anv_genX.h|   5 +
 src/intel/vulkan/anv_image.c   |  93 ++
 src/intel/vulkan/anv_pass.c|  36 ++-
 src/intel/vulkan/anv_private.h |  37 ++-
 src/intel/vulkan/genX_cmd_buffer.c | 626 -
 src/intel/vulkan/genX_gpu_memcpy.c |  40 +++
 11 files changed, 783 insertions(+), 256 deletions(-)

-- 
2.13.3

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[Mesa-dev] [PATCH 00/32] i965: Enabale CCS_E for sRGB render buffers

[Jason Ekstrand]

Gen9 hardware has this annoying little corner where CCS_E is not allowed
for any sRGB formats.  This is fixed on gen10 but on gen9 there's nothing
we can do; it just doesn't work.  The old approach to working around this
was to just disable CCS_E the moment we saw sRGB.  This is bad because GLX
gives out sRGB-capable visuals by default and you can easily get one
through EGL as well even if you never enable sRGB encode.  This means that
users who have sRGB visuals and don't care about sRGB encode are getting
unnecessarily punished.  This isn't a huge problem today because you also
can't do CCS_E on X-tiled images but it will be a problem the moment we
start seeing the Y-tiling modifier through the window system.

Also, I think sRGB + CCS was plain broken for the less likely case of
rendering to a texture-backed framebuffer.  Our tracking for sRGB was based
on piles of sRGBEnabled checks that I'm not at all sure added up to correct
code.  When trying to better test the CCS_E modifier, I patched waffle to
start using modifiers whenever the GBM back-end was in-use.  When I ran
piglit with these waffle patches and my old CCS_E series, our pass rate was
under 50%.  I think part of that was due to bugs with sRGB and part of it
was due to not having a plan for falling back to CCS_D once the CCS_E
modifier gets used.  This series is that plan.

The first 5 patches are a couple of bugfixes and the removal of a couple of
bogus restrictions.  In particular, we were disabling CCS_E on all
renderbuffers for no good reason.  Patch 3 fixes bugs exposed by patch 2
related to glBlitFramebuffers with both color and depth bits specified.

The next 5 add a partial resolve pass for MCS and hook it up so that we can
handle clear colors with texture views correctly.

The last 22 patches rework things so that we can properly fall back to
CCS_D whenever we can't render with CCS_E.  This requires adding a seventh
value to the isl_aux_state enum to describe a "partial clear" state which
is the state a CCS_E image is in when it's been fast-cleared and then
rendered to using CCS_D.  Tracking this additional state allows us to turn
on CCS_E even when we have an sRGB visual and then just silently resolve if
we ever need to render with sRGB encode enabled.  If they just turn on sRGB
encode and leave it on, then they don't get a resolve because our tracking
code knows that you can do CCS_D rendering on a CCS_E surface that is in
the CLEAR state and the end result is the PARTIAL_CLEAR state.

We need to land this series before we flip on the CCS_E modifier and I'd
like to land it in time for the 17.2 release if we can.

Happy Reviewing!

Jason Ekstrand (32):
  i965/surface_state: Use the minified depth for number of image layers
  i965/blorp: Use the renderbuffer format for clears
  i965/blorp: Do flushes around depth resolves
  i965/miptree: Stop setting FOR_SCANOUT for renderbuffers
  i965/miptree: Remove some unneeded restrictions
  intel/blorp: Add a partial resolve pass for MCS
  i965/miptree: Make layer_range_length return locical layers
  i965/miptree: Tighten up finish_mcs_write
  i965/miptree: Add support for partially resolving MCS
  i965/miptree: Partially resolve MCS for texture views
  i965/miptree: Add a helper for getting the aux usage for texturing
  i965/miptree: Rework prepare/finish_render to be in terms of aux_usage
  i965/blorp: Do prepare/finsh manually
  i965/blorp: Use texture/render_aux_usage for blits
  i965/blorp: Be more accurate about aux usage in blorp_copy
  i965/blorp: Use render_aux_usage for color clears
  i965/blorp: Use prepare/finish_depth for depth clears
  i965/miptree: Refactor some things to use mt->aux_usage
  i965/miptree: Take an aux_usage in prepare/finish
  intel/isl: Add an aux state for "partial clear"
  i965/miptree: Use ISL_AUX_STATE_PARTIAL_CLEAR for CCS_D
  i965/miptree: Allow for accessing a CCS_E image as CCS_D
  i965/miptree: Use miptree range helpers in has_color_unresolved
  i965/miptree: Take an isl_format in prepare_texture
  i965/surface_state: Take an isl_aux_usage in emit_surface_state
  i965/surface_state: Get the aux usage from the miptree code
  intel/isl/format: Dedent the template in gen_format_layout.py
  intel/isl/format: Add an srgb_to_linear helper
  i965: Weaken the texture view rules for formats slightly
  intel/blorp: Allow blorp_copy on sRGB formats
  intel/isl: Add a helper for determining if a color is 0/1
  i965: Enable regular fast-clears (CCS_D) on gen9+

 src/intel/blorp/blorp.h  |   6 +
 src/intel/blorp/blorp_blit.c |  18 +-
 src/intel/blorp/blorp_clear.c| 105 -
 src/intel/blorp/blorp_nir_builder.h  | 102 +
 src/intel/blorp/blorp_priv.h |   1 +
 src/intel/isl/gen_format_layout.py   | 161 +---
 src/intel/isl/isl.c  |  27 ++
 src/intel/isl/isl.h  |  99 +++--
 src/mesa/drivers/dri/i965/brw_

Re: [Mesa-dev] [2.2/22] intel/isl: Add i915 to isl_tiling converter

[Daniel Stone]

On 19 July 2017 at 21:24, Jason Ekstrand  wrote:
> I don't really like the lack of isl_ prefix.  We could call it
> isl_tiling_from_i915_tiling().  I don't care all that much though.

That works for me, but equally I don't really mind, so either way:
Reviewed-by: Daniel Stone 

Cheers,
Daniel
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[Mesa-dev] [PATCH 31/32] intel/isl: Add a helper for determining if a color is 0/1

[Jason Ekstrand]

---
 src/intel/isl/isl.c | 27 +++
 src/intel/isl/isl.h |  3 +++
 2 files changed, 30 insertions(+)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 12ffe3b..2976e32 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -259,6 +259,33 @@ isl_tiling_get_info(enum isl_tiling tiling,
};
 }
 
+bool
+isl_color_value_is_zero_one(union isl_color_value value,
+enum isl_format format)
+{
+   const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+
+#define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
+   if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
+  return false
+
+   if (isl_format_has_int_channel(format)) {
+  RETURN_FALSE_IF_NOT_0_1(r, 0, u32);
+  RETURN_FALSE_IF_NOT_0_1(g, 1, u32);
+  RETURN_FALSE_IF_NOT_0_1(b, 2, u32);
+  RETURN_FALSE_IF_NOT_0_1(a, 3, u32);
+   } else {
+  RETURN_FALSE_IF_NOT_0_1(r, 0, f32);
+  RETURN_FALSE_IF_NOT_0_1(g, 1, f32);
+  RETURN_FALSE_IF_NOT_0_1(b, 2, f32);
+  RETURN_FALSE_IF_NOT_0_1(a, 3, f32);
+   }
+
+#undef RETURN_FALSE_IF_NOT_0_1
+
+   return true;
+}
+
 /**
  * @param[out] tiling is set only on success
  */
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index bc68e58..b2f5d39 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1630,6 +1630,9 @@ isl_extent4d(uint32_t width, uint32_t height, uint32_t 
depth,
return e;
 }
 
+bool isl_color_value_is_zero_one(union isl_color_value value,
+ enum isl_format format);
+
 #define isl_surf_init(dev, surf, ...) \
isl_surf_init_s((dev), (surf), \
&(struct isl_surf_init_info) {  __VA_ARGS__ });
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 30/32] intel/blorp: Allow blorp_copy on sRGB formats

[Jason Ekstrand]

---
 src/intel/blorp/blorp_blit.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 973e3ef..91d2a22 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2459,16 +2459,30 @@ blorp_copy(struct blorp_batch *batch,
}
 
if (params.src.aux_usage == ISL_AUX_USAGE_CCS_E) {
+  /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
+   * enabled even though CCS_E doesn't technically do sRGB on SKL because
+   * we stomp everything to UINT anyway.  The one thing we have to be
+   * careful of is clear colors.  Because fast clear colors for sRGB on
+   * gen9 are encoded as the float values between format conversion and
+   * sRGB curve application, a given clear color float will convert to the
+   * same bits regardless of whether the format is UNORM or sRGB.
+   * Therefore, we can handle sRGB without any special cases.
+   */
+  UNUSED enum isl_format linear_src_format =
+ isl_format_srgb_to_linear(src_surf->surf->format);
   assert(isl_formats_are_ccs_e_compatible(batch->blorp->isl_dev->info,
-  src_surf->surf->format,
+  linear_src_format,
   params.src.view.format));
   params.src.clear_color =
  bitcast_color_value_to_uint(params.src.clear_color, src_fmtl);
}
 
if (params.dst.aux_usage == ISL_AUX_USAGE_CCS_E) {
+  /* See above where we handle linear_src_format */
+  UNUSED enum isl_format linear_dst_format =
+ isl_format_srgb_to_linear(dst_surf->surf->format);
   assert(isl_formats_are_ccs_e_compatible(batch->blorp->isl_dev->info,
-  dst_surf->surf->format,
+  linear_dst_format,
   params.dst.view.format));
   params.dst.clear_color =
  bitcast_color_value_to_uint(params.dst.clear_color, dst_fmtl);
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 26/32] i965/surface_state: Get the aux usage from the miptree code

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 108 +++
 1 file changed, 13 insertions(+), 95 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 30b5e61..2fefba5 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -207,9 +207,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
 
-   enum isl_aux_usage aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
-   if (!mt->mcs_buf)
-  aux_usage = ISL_AUX_USAGE_NONE;
+   enum isl_aux_usage aux_usage =
+  intel_miptree_render_aux_usage(brw, mt, ctx->Color.sRGBEnabled);
 
if (flags & INTEL_AUX_BUFFER_DISABLED) {
   assert(brw->gen >= 9);
@@ -433,95 +432,21 @@ swizzle_to_scs(GLenum swizzle, bool need_green_to_blue)
return (need_green_to_blue && scs == HSW_SCS_GREEN) ? HSW_SCS_BLUE : scs;
 }
 
-static unsigned
-brw_find_matching_rb(const struct gl_framebuffer *fb,
- const struct intel_mipmap_tree *mt)
+static bool
+brw_aux_surface_disabled(const struct brw_context *brw,
+ const struct intel_mipmap_tree *mt)
 {
+   const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
+
for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
   const struct intel_renderbuffer *irb =
  intel_renderbuffer(fb->_ColorDrawBuffers[i]);
 
   if (irb && irb->mt == mt)
- return i;
+ return brw->draw_aux_buffer_disabled[i];
}
 
-   return fb->_NumColorDrawBuffers;
-}
-
-static inline bool
-brw_texture_view_sane(const struct brw_context *brw,
-  const struct intel_mipmap_tree *mt,
-  const struct isl_view *view)
-{
-   /* There are special cases only for lossless compression. */
-   if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
-  return true;
-
-   if (isl_format_supports_ccs_e(&brw->screen->devinfo, view->format))
-  return true;
-
-   /* Logic elsewhere needs to take care to resolve the color buffer prior
-* to sampling it as non-compressed.
-*/
-   if (intel_miptree_has_color_unresolved(mt, view->base_level, view->levels,
-  view->base_array_layer,
-  view->array_len))
-  return false;
-
-   const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
-   const unsigned rb_index = brw_find_matching_rb(fb, mt);
-
-   if (rb_index == fb->_NumColorDrawBuffers)
-  return true;
-
-   /* Underlying surface is compressed but it is sampled using a format that
-* the sampling engine doesn't support as compressed. Compression must be
-* disabled for both sampling engine and data port in case the same surface
-* is used also as render target.
-*/
-   return brw->draw_aux_buffer_disabled[rb_index];
-}
-
-static bool
-brw_disable_aux_surface(const struct brw_context *brw,
-const struct intel_mipmap_tree *mt,
-const struct isl_view *view)
-{
-   /* Nothing to disable. */
-   if (!mt->mcs_buf)
-  return false;
-
-   const bool is_unresolved = intel_miptree_has_color_unresolved(
- mt, view->base_level, view->levels,
- view->base_array_layer, view->array_len);
-
-   /* There are special cases only for lossless compression. */
-   if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
-  return !is_unresolved;
-
-   const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
-   const unsigned rb_index = brw_find_matching_rb(fb, mt);
-
-   /* If we are drawing into this with compression enabled, then we must also
-* enable compression when texturing from it regardless of
-* fast_clear_state.  If we don't then, after the first draw call with
-* this setup, there will be data in the CCS which won't get picked up by
-* subsequent texturing operations as required by ARB_texture_barrier.
-* Since we don't want to re-emit the binding table or do a resolve
-* operation every draw call, the easiest thing to do is just enable
-* compression on the texturing side.  This is completely safe to do
-* since, if compressed texturing weren't allowed, we would have disabled
-* compression of render targets in whatever_that_function_is_called().
-*/
-   if (rb_index < fb->_NumColorDrawBuffers) {
-  if (brw->draw_aux_buffer_disabled[rb_index]) {
- assert(!is_unresolved);
-  }
-
-  return brw->draw_aux_buffer_disabled[rb_index];
-   }
-
-   return !is_unresolved;
+   return false;
 }
 
 void
@@ -643,13 +568,10 @@ brw_update_texture_surface(struct gl_context *ctx,
   obj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
  view.usage |= ISL_SURF_USAGE_CUBE_BIT;
 
-  assert(brw_texture_view_sane(brw, mt, &view));
+  enum

[Mesa-dev] [PATCH 22/32] i965/miptree: Allow for accessing a CCS_E image as CCS_D

[Jason Ekstrand]

This requires us to start using the partial clear state.  It makes
things quite a bit more complicated but it's still a fairly
straightforward exercise in diagram following.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 +--
 1 file changed, 28 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 68e0246..1bbf9a5 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2196,12 +2196,26 @@ get_ccs_e_resolve_op(enum isl_aux_state aux_state,
  enum isl_aux_usage aux_usage,
  bool fast_clear_supported)
 {
-   const bool ccs_supported = aux_usage != ISL_AUX_USAGE_NONE;
+   /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
+   assert(aux_usage == ISL_AUX_USAGE_NONE ||
+  aux_usage == ISL_AUX_USAGE_CCS_D ||
+  aux_usage == ISL_AUX_USAGE_CCS_E);
+
+   if (aux_usage == ISL_AUX_USAGE_CCS_D)
+  assert(fast_clear_supported);
 
switch (aux_state) {
case ISL_AUX_STATE_CLEAR:
+   case ISL_AUX_STATE_PARTIAL_CLEAR:
+  if (fast_clear_supported)
+ return BLORP_FAST_CLEAR_OP_NONE;
+  else if (aux_usage == ISL_AUX_USAGE_CCS_E)
+ return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
+  else
+ return BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
+
case ISL_AUX_STATE_COMPRESSED_CLEAR:
-  if (!ccs_supported)
+  if (aux_usage != ISL_AUX_USAGE_CCS_E)
  return BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
   else if (!fast_clear_supported)
  return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
@@ -2209,7 +2223,7 @@ get_ccs_e_resolve_op(enum isl_aux_state aux_state,
  return BLORP_FAST_CLEAR_OP_NONE;
 
case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
-  if (!ccs_supported)
+  if (aux_usage != ISL_AUX_USAGE_CCS_E)
  return BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
   else
  return BLORP_FAST_CLEAR_OP_NONE;
@@ -2217,7 +2231,6 @@ get_ccs_e_resolve_op(enum isl_aux_state aux_state,
case ISL_AUX_STATE_PASS_THROUGH:
   return BLORP_FAST_CLEAR_OP_NONE;
 
-   case ISL_AUX_STATE_PARTIAL_CLEAR:
case ISL_AUX_STATE_RESOLVED:
case ISL_AUX_STATE_AUX_INVALID:
   break;
@@ -2282,9 +2295,17 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
   switch (aux_state) {
   case ISL_AUX_STATE_CLEAR:
- assert(written_with_ccs);
- intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_COMPRESSED_CLEAR);
+  case ISL_AUX_STATE_PARTIAL_CLEAR:
+ assert(aux_usage == ISL_AUX_USAGE_CCS_E ||
+aux_usage == ISL_AUX_USAGE_CCS_D);
+
+ if (aux_usage == ISL_AUX_USAGE_CCS_E) {
+intel_miptree_set_aux_state(brw, mt, level, layer, 1,
+ISL_AUX_STATE_COMPRESSED_CLEAR);
+ } else if (aux_state != ISL_AUX_STATE_PARTIAL_CLEAR) {
+intel_miptree_set_aux_state(brw, mt, level, layer, 1,
+ISL_AUX_STATE_PARTIAL_CLEAR);
+ }
  break;
 
   case ISL_AUX_STATE_COMPRESSED_CLEAR:
@@ -2301,7 +2322,6 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
  }
  break;
 
-  case ISL_AUX_STATE_PARTIAL_CLEAR:
   case ISL_AUX_STATE_RESOLVED:
   case ISL_AUX_STATE_AUX_INVALID:
  unreachable("Invalid aux state for CCS_E");
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 27/32] intel/isl/format: Dedent the template in gen_format_layout.py

[Jason Ekstrand]

This makes it much easier to edit the template and doesn't really dirty
the python all that much.
---
 src/intel/isl/gen_format_layout.py | 115 ++---
 1 file changed, 57 insertions(+), 58 deletions(-)

diff --git a/src/intel/isl/gen_format_layout.py 
b/src/intel/isl/gen_format_layout.py
index f52e454..aa4e2d8 100644
--- a/src/intel/isl/gen_format_layout.py
+++ b/src/intel/isl/gen_format_layout.py
@@ -32,64 +32,63 @@ from mako import template
 # Load the template, ensure that __future__.division is imported, and set the
 # bytes encoding to be utf-8. This last bit is important to getting simple
 # consistent behavior for python 3 when we get there.
-TEMPLATE = template.Template(
-text=textwrap.dedent("""\
-/* This file is autogenerated by gen_format_layout.py. DO NOT EDIT! */
-
-/*
- * Copyright 2015 Intel Corporation
- *
- *  Permission is hereby granted, free of charge, to any person 
obtaining a
- *  copy of this software and associated documentation files (the 
"Software"),
- *  to deal in the Software without restriction, including without 
limitation
- *  the rights to use, copy, modify, merge, publish, distribute, 
sublicense,
- *  and/or sell copies of the Software, and to permit persons to whom 
the
- *  Software is furnished to do so, subject to the following 
conditions:
- *
- *  The above copyright notice and this permission notice (including 
the next
- *  paragraph) shall be included in all copies or substantial portions 
of the
- *  Software.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
EXPRESS OR
- *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
MERCHANTABILITY,
- *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT 
SHALL
- *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES 
OR OTHER
- *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 
ARISING
- *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 
OTHER DEALINGS
- *  IN THE SOFTWARE.
- */
-
-#include "isl/isl.h"
-
-const struct isl_format_layout
-isl_format_layouts[] = {
-% for format in formats:
-  [ISL_FORMAT_${format.name}] = {
-.format = ISL_FORMAT_${format.name},
-.name = "ISL_FORMAT_${format.name}",
-.bpb = ${format.bpb},
-.bw = ${format.bw},
-.bh = ${format.bh},
-.bd = ${format.bd},
-.channels = {
-% for mask in ['r', 'g', 'b', 'a', 'l', 'i', 'p']:
-  <% channel = getattr(format, mask, None) %>\\
-  % if channel.type is not None:
-.${mask} = { ISL_${channel.type}, ${channel.size} },
-  % else:
-.${mask} = {},
-  % endif
-% endfor
-},
-.colorspace = ISL_COLORSPACE_${format.colorspace},
-.txc = ISL_TXC_${format.txc},
-  },
-
-% endfor
-};
-"""),
-future_imports=['division'],
-output_encoding='utf-8')
+TEMPLATE = template.Template(future_imports=['division'],
+ output_encoding='utf-8',
+ text="""\
+/* This file is autogenerated by gen_format_layout.py. DO NOT EDIT! */
+
+/*
+ * Copyright 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "isl/isl.h"
+
+const struct isl_format_layout
+isl_format_layouts[] = {
+% for format in formats:
+  [ISL_FORMAT_${format.name}] = {
+.format = ISL_FORMAT_${format.name},
+.name = "ISL_FORMAT_${format.name}",
+.bpb = ${format.bpb},
+.bw = ${format.bw},
+.bh = ${format.bh},
+.bd = ${format.bd},
+.channels = {
+ 

[Mesa-dev] [PATCH 32/32] i965: Enable regular fast-clears (CCS_D) on gen9+

[Jason Ekstrand]

The set of formats which supports CCS_E is actually fairly small on
gen9.  However, everything that supports fast-clears on gen8 also
supports fast-clears on gen9+.  The one very annoying exception is
that blending is broken for non-0/1 clear colors with sRGB formats.
In order to solve that problem, we do a resolve to get rid of the
clear color.  Another option would be to just not fast-clear with
non-0/1 clear colors however non-0/1 + blending + sRGB is uncommon
enough that this shouldn't be a significant performance problem.
---
 src/mesa/drivers/dri/i965/brw_blorp.c| 10 ++--
 src/mesa/drivers/dri/i965/brw_draw.c |  6 ++-
 src/mesa/drivers/dri/i965/brw_meta_util.c| 11 
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  5 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 66 +++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  6 +--
 6 files changed, 45 insertions(+), 59 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 43745d2..b799972 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -324,7 +324,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
 src_aux_usage, src_clear_supported);
 
enum isl_aux_usage dst_aux_usage =
-  intel_miptree_render_aux_usage(brw, dst_mt, encode_srgb);
+  intel_miptree_render_aux_usage(brw, dst_mt, encode_srgb, false);
const bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
 dst_aux_usage, dst_clear_supported);
@@ -885,9 +885,9 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   irb->mt, irb->mt_level, irb->mt_layer, num_layers);
 
   enum isl_aux_usage aux_usage =
- intel_miptree_render_aux_usage(brw, irb->mt, encode_srgb);
+ intel_miptree_render_aux_usage(brw, irb->mt, encode_srgb, false);
   intel_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer,
-   num_layers, encode_srgb);
+   num_layers, encode_srgb, false);
 
   struct isl_surf isl_tmp[2];
   struct blorp_surf surf;
@@ -907,8 +907,8 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   clear_color, color_write_disable);
   blorp_batch_finish(&batch);
 
-  intel_miptree_finish_render(brw, irb->mt, level,
-  irb->mt_layer, num_layers, encode_srgb);
+  intel_miptree_finish_render(brw, irb->mt, level, irb->mt_layer,
+  num_layers, encode_srgb, false);
}
 
return;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 01b618c..8e0a4ae 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -474,7 +474,8 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw)
 
   intel_miptree_prepare_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,
-   ctx->Color.sRGBEnabled);
+   ctx->Color.sRGBEnabled,
+   ctx->Color.BlendEnabled & (1 << i));
}
 }
 
@@ -542,7 +543,8 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context 
*brw)
   brw_render_cache_set_add_bo(brw, irb->mt->bo);
   intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
   irb->mt_layer, irb->layer_count,
-  ctx->Color.sRGBEnabled);
+  ctx->Color.sRGBEnabled,
+  ctx->Color.BlendEnabled & (1 << i));
}
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index f9fd350..7ce1fd1 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -292,17 +292,6 @@ brw_is_color_fast_clear_compatible(struct brw_context *brw,
brw->mesa_to_isl_render_format[mt->format])
   return false;
 
-   /* Gen9 doesn't support fast clear on single-sampled SRGB buffers. When
-* GL_FRAMEBUFFER_SRGB is enabled any color renderbuffers will be
-* resolved in intel_update_state. In that case it's pointless to do a
-* fast clear because it's very likely to be immediately resolved.
-*/
-   if (brw->gen >= 9 &&
-   mt->num_samples <= 1 &&
-   ctx->Color.sRGBEnabled &&
-   _mesa_get_srgb_format_linear(mt->format) != mt->format)
-  return false;
-
const mesa_format format = _mesa_get_render_format(ctx, mt->format);
if (_mesa_is_format_integer_color(format)) {
   if (brw->gen >= 8) {
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH 21/32] i965/miptree: Use ISL_AUX_STATE_PARTIAL_CLEAR for CCS_D

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 91fcd0b..68e0246 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2172,7 +2172,7 @@ get_ccs_d_resolve_op(enum isl_aux_state aux_state,
 
switch (aux_state) {
case ISL_AUX_STATE_CLEAR:
-   case ISL_AUX_STATE_COMPRESSED_CLEAR:
+   case ISL_AUX_STATE_PARTIAL_CLEAR:
   if (!ccs_supported)
  return BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
   else
@@ -2181,9 +2181,9 @@ get_ccs_d_resolve_op(enum isl_aux_state aux_state,
case ISL_AUX_STATE_PASS_THROUGH:
   return BLORP_FAST_CLEAR_OP_NONE;
 
-   case ISL_AUX_STATE_PARTIAL_CLEAR:
case ISL_AUX_STATE_RESOLVED:
case ISL_AUX_STATE_AUX_INVALID:
+   case ISL_AUX_STATE_COMPRESSED_CLEAR:
case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
   break;
}
@@ -2313,10 +2313,10 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
   case ISL_AUX_STATE_CLEAR:
  assert(written_with_ccs);
  intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_COMPRESSED_CLEAR);
+ ISL_AUX_STATE_PARTIAL_CLEAR);
  break;
 
-  case ISL_AUX_STATE_COMPRESSED_CLEAR:
+  case ISL_AUX_STATE_PARTIAL_CLEAR:
  assert(written_with_ccs);
  break; /* Nothing to do */
 
@@ -2324,7 +2324,7 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
  /* Nothing to do */
  break;
 
-  case ISL_AUX_STATE_PARTIAL_CLEAR:
+  case ISL_AUX_STATE_COMPRESSED_CLEAR:
   case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
   case ISL_AUX_STATE_RESOLVED:
   case ISL_AUX_STATE_AUX_INVALID:
@@ -2384,6 +2384,7 @@ intel_miptree_finish_mcs_write(struct brw_context *brw,
case ISL_AUX_STATE_RESOLVED:
case ISL_AUX_STATE_PASS_THROUGH:
case ISL_AUX_STATE_AUX_INVALID:
+   case ISL_AUX_STATE_PARTIAL_CLEAR:
   unreachable("Invalid aux state for MCS");
}
 }
-- 
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[Mesa-dev] [PATCH 29/32] i965: Weaken the texture view rules for formats slightly

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 801d830..ebc414c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2760,6 +2760,23 @@ intel_miptree_texture_aux_usage(struct brw_context *brw,
return ISL_AUX_USAGE_NONE;
 }
 
+static bool
+isl_formats_are_fast_clear_compatible(enum isl_format a, enum isl_format b)
+{
+   /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
+* values so sRGB curve application was a no-op for all fast-clearable
+* formats.
+*
+* On gen9+, the hardware supports arbitrary clear values.  For sRGB clear
+* values, the hardware interprets the floats, not as what would be
+* returned from the sampler (or written by the shader), but as being
+* between format conversion and sRGB curve application.  This means that
+* we can switch between sRGB and UNORM without having to whack the clear
+* color.
+*/
+   return isl_format_srgb_to_linear(a) == isl_format_srgb_to_linear(b);
+}
+
 static void
 intel_miptree_prepare_texture_slices(struct brw_context *brw,
  struct intel_mipmap_tree *mt,
@@ -2776,7 +2793,8 @@ intel_miptree_prepare_texture_slices(struct brw_context 
*brw,
 * the sampler.  If we have a texture view, we would have to perform the
 * clear color conversion manually.  Just disable clear color.
 */
-   if (mt->format != view_format)
+   enum isl_format isl_mt_format = translate_tex_format(brw, mt->format, 
false);
+   if (!isl_formats_are_fast_clear_compatible(isl_mt_format, view_format))
   clear_supported = false;
 
intel_miptree_prepare_access(brw, mt, start_level, num_levels,
-- 
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[Mesa-dev] [PATCH 28/32] intel/isl/format: Add an srgb_to_linear helper

[Jason Ekstrand]

---
 src/intel/isl/gen_format_layout.py | 46 +-
 src/intel/isl/isl.h|  8 +++
 2 files changed, 53 insertions(+), 1 deletion(-)

diff --git a/src/intel/isl/gen_format_layout.py 
b/src/intel/isl/gen_format_layout.py
index aa4e2d8..0ca42db 100644
--- a/src/intel/isl/gen_format_layout.py
+++ b/src/intel/isl/gen_format_layout.py
@@ -88,6 +88,19 @@ isl_format_layouts[] = {
 
 % endfor
 };
+
+enum isl_format
+isl_format_srgb_to_linear(enum isl_format format)
+{
+switch (format) {
+% for srgb, rgb in srgb_to_linear_map:
+case ISL_FORMAT_${srgb}:
+return ISL_FORMAT_${rgb};
+%endfor
+default:
+return format;
+}
+}
 """)
 
 
@@ -167,6 +180,34 @@ def reader(csvfile):
 if line and not line[0].startswith('#'):
 yield line
 
+def get_srgb_to_linear_map(formats):
+"""Compute a map from sRGB to linear formats.
+
+This function uses some probably somewhat fragile string munging to do
+the conversion.  However, we do assert that, if it's SRGB, the munging
+succeeded so that gives some safety.
+"""
+names = {f.name for f in formats}
+for fmt in formats:
+if fmt.colorspace != 'SRGB':
+continue
+
+replacements = [
+('_SRGB',   ''),
+('SRGB','RGB'),
+('U8SRGB',  'FLT16'),
+]
+
+found = False;
+for rep in replacements:
+rgb_name = fmt.name.replace(rep[0], rep[1])
+if rgb_name in names:
+found = True
+yield fmt.name, rgb_name
+break;
+
+# We should have found a format name
+assert found
 
 def main():
 """Main function."""
@@ -183,11 +224,14 @@ def main():
 # problem: Unicode can be rendered even if the shell calling this script
 # doesn't.
 with open(args.out, 'wb') as f:
+formats = [Format(l) for l in reader(args.csv)]
 try:
 # This basically does lazy evaluation and initialization, which
 # saves on memory and startup overhead.
 f.write(TEMPLATE.render(
-formats=(Format(l) for l in reader(args.csv
+formats = formats,
+srgb_to_linear_map  = list(get_srgb_to_linear_map(formats)),
+))
 except Exception:
 # In the even there's an error this imports some helpers from mako
 # to print a useful stack trace and prints it, then exits with
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 68bfcee..bc68e58 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1495,6 +1495,14 @@ isl_format_block_is_1x1x1(enum isl_format fmt)
 }
 
 static inline bool
+isl_format_is_srgb(enum isl_format fmt)
+{
+   return isl_format_layouts[fmt].colorspace == ISL_COLORSPACE_SRGB;
+}
+
+enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
+
+static inline bool
 isl_format_is_rgb(enum isl_format fmt)
 {
return isl_format_layouts[fmt].channels.r.bits > 0 &&
-- 
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[Mesa-dev] [PATCH 24/32] i965/miptree: Take an isl_format in prepare_texture

[Jason Ekstrand]

This will be a bit more convenient momentarily.  It's also more correct
because it makes prepare_texture take sRGB into account.
---
 src/mesa/drivers/dri/i965/brw_draw.c  |  7 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  2 +-
 3 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index b77b44e..01b618c 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -383,8 +383,13 @@ brw_predraw_resolve_inputs(struct brw_context *brw)
   if (!tex_obj || !tex_obj->mt)
 continue;
 
+
+  struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, i);
+  enum isl_format view_format =
+ translate_tex_format(brw, tex_obj->_Format, sampler->sRGBDecode);
+
   bool aux_supported;
-  intel_miptree_prepare_texture(brw, tex_obj->mt, tex_obj->_Format,
+  intel_miptree_prepare_texture(brw, tex_obj->mt, view_format,
 &aux_supported);
 
   if (!aux_supported && brw->gen >= 9 &&
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 5696886..801d830 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2716,18 +2716,16 @@ intel_miptree_set_aux_state(struct brw_context *brw,
 static bool
 can_texture_with_ccs(struct brw_context *brw,
  struct intel_mipmap_tree *mt,
- mesa_format view_format)
+ enum isl_format view_format)
 {
if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
   return false;
 
enum isl_format isl_mt_format = brw_isl_format_for_mesa_format(mt->format);
-   enum isl_format isl_view_format = 
brw_isl_format_for_mesa_format(view_format);
-
if (!isl_formats_are_ccs_e_compatible(&brw->screen->devinfo,
- isl_mt_format, isl_view_format)) {
+ isl_mt_format, view_format)) {
   perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
- _mesa_get_format_name(view_format),
+ isl_format_get_layout(view_format)->name,
  _mesa_get_format_name(mt->format));
   return false;
}
@@ -2765,7 +2763,7 @@ intel_miptree_texture_aux_usage(struct brw_context *brw,
 static void
 intel_miptree_prepare_texture_slices(struct brw_context *brw,
  struct intel_mipmap_tree *mt,
- mesa_format view_format,
+ enum isl_format view_format,
  uint32_t start_level, uint32_t num_levels,
  uint32_t start_layer, uint32_t num_layers,
  bool *aux_supported_out)
@@ -2791,7 +2789,7 @@ intel_miptree_prepare_texture_slices(struct brw_context 
*brw,
 void
 intel_miptree_prepare_texture(struct brw_context *brw,
   struct intel_mipmap_tree *mt,
-  mesa_format view_format,
+  enum isl_format view_format,
   bool *aux_supported_out)
 {
intel_miptree_prepare_texture_slices(brw, mt, view_format,
@@ -2815,7 +2813,8 @@ intel_miptree_prepare_fb_fetch(struct brw_context *brw,
struct intel_mipmap_tree *mt, uint32_t level,
uint32_t start_layer, uint32_t num_layers)
 {
-   intel_miptree_prepare_texture_slices(brw, mt, mt->format, level, 1,
+   enum isl_format format = translate_tex_format(brw, mt->format, false);
+   intel_miptree_prepare_texture_slices(brw, mt, format, level, 1,
 start_layer, num_layers, NULL);
 }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 239791f..df413b1 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -931,7 +931,7 @@ intel_miptree_texture_aux_usage(struct brw_context *brw,
 void
 intel_miptree_prepare_texture(struct brw_context *brw,
   struct intel_mipmap_tree *mt,
-  mesa_format view_format,
+  enum isl_format view_format,
   bool *aux_supported_out);
 void
 intel_miptree_prepare_image(struct brw_context *brw,
-- 
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[Mesa-dev] [PATCH 25/32] i965/surface_state: Take an isl_aux_usage in emit_surface_state

[Jason Ekstrand]

This commit replaces the generic "flags" parameter with a more explicit
aux usage parameter.  This leads to a lot of duplicated code at the
moment but this will all get cleaned up directly.
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 73 +++-
 1 file changed, 47 insertions(+), 26 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index e878613..30b5e61 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -76,8 +76,9 @@ uint32_t rb_mocs[] = {
 
 static void
 brw_emit_surface_state(struct brw_context *brw,
-   struct intel_mipmap_tree *mt, uint32_t flags,
+   struct intel_mipmap_tree *mt,
GLenum target, struct isl_view view,
+   enum isl_aux_usage aux_usage,
uint32_t mocs, uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains)
 {
@@ -139,23 +140,26 @@ brw_emit_surface_state(struct brw_context *brw,
struct brw_bo *aux_bo;
struct isl_surf *aux_surf = NULL;
uint64_t aux_offset = 0;
-   enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
-   if ((mt->mcs_buf || intel_miptree_sample_with_hiz(brw, mt)) &&
-   !(flags & INTEL_AUX_BUFFER_DISABLED)) {
-  aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
-
-  if (mt->mcs_buf) {
- aux_surf = &mt->mcs_buf->surf;
+   switch (aux_usage) {
+   case ISL_AUX_USAGE_MCS:
+   case ISL_AUX_USAGE_CCS_D:
+   case ISL_AUX_USAGE_CCS_E:
+  aux_surf = &mt->mcs_buf->surf;
+  aux_bo = mt->mcs_buf->bo;
+  aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
+  break;
 
- aux_bo = mt->mcs_buf->bo;
- aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset;
-  } else {
- aux_surf = &mt->hiz_buf->surf;
+   case ISL_AUX_USAGE_HIZ:
+  aux_surf = &mt->hiz_buf->surf;
+  aux_bo = mt->hiz_buf->bo;
+  aux_offset = mt->hiz_buf->bo->offset64;
+  break;
 
- aux_bo = mt->hiz_buf->bo;
- aux_offset = mt->hiz_buf->bo->offset64;
-  }
+   case ISL_AUX_USAGE_NONE:
+  break;
+   }
 
+   if (aux_usage != ISL_AUX_USAGE_NONE) {
   /* We only really need a clear color if we also have an auxiliary
* surface.  Without one, it does nothing.
*/
@@ -203,8 +207,13 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
 
-   if (brw->gen < 9) {
-  assert(!(flags & INTEL_AUX_BUFFER_DISABLED));
+   enum isl_aux_usage aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
+   if (!mt->mcs_buf)
+  aux_usage = ISL_AUX_USAGE_NONE;
+
+   if (flags & INTEL_AUX_BUFFER_DISABLED) {
+  assert(brw->gen >= 9);
+  aux_usage = ISL_AUX_USAGE_NONE;
}
 
assert(brw_render_target_supported(brw, rb));
@@ -226,7 +235,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
};
 
uint32_t offset;
-   brw_emit_surface_state(brw, mt, flags, mt->target, view,
+   brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
   rb_mocs[brw->gen],
   &offset, surf_index,
   I915_GEM_DOMAIN_RENDER,
@@ -636,9 +645,14 @@ brw_update_texture_surface(struct gl_context *ctx,
 
   assert(brw_texture_view_sane(brw, mt, &view));
 
-  const int flags = brw_disable_aux_surface(brw, mt, &view) ?
-   INTEL_AUX_BUFFER_DISABLED : 0;
-  brw_emit_surface_state(brw, mt, flags, mt->target, view,
+  enum isl_aux_usage aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
+  if (!mt->mcs_buf && !intel_miptree_sample_with_hiz(brw, mt))
+ aux_usage = ISL_AUX_USAGE_NONE;
+
+  if (brw_disable_aux_surface(brw, mt, &view))
+ aux_usage = ISL_AUX_USAGE_NONE;
+
+  brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
  tex_mocs[brw->gen],
  surf_offset, surf_index,
  I915_GEM_DOMAIN_SAMPLER, 0);
@@ -1206,9 +1220,16 @@ update_renderbuffer_read_surfaces(struct brw_context 
*brw)
.usage = ISL_SURF_USAGE_TEXTURE_BIT,
 };
 
-const int flags = brw->draw_aux_buffer_disabled[i] ?
- INTEL_AUX_BUFFER_DISABLED : 0;
-brw_emit_surface_state(brw, irb->mt, flags, target, view,
+enum isl_aux_usage aux_usage =
+   intel_miptree_get_aux_isl_usage(brw, irb->mt);
+if (!irb->mt->mcs_buf &&
+!intel_miptree_sample_with_hiz(brw, irb->mt))
+   aux_usage = ISL_AUX_USAGE_NONE;
+
+if (brw->draw_aux_buffer_disabled[i])
+   aux_usage = ISL_AUX_USAGE_NONE;
+
+brw_emit_surface_sta

[Mesa-dev] [PATCH 23/32] i965/miptree: Use miptree range helpers in has_color_unresolved

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 104 +-
 1 file changed, 51 insertions(+), 53 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 1bbf9a5..5696886 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2106,6 +2106,52 @@ intel_miptree_level_has_hiz(const struct 
intel_mipmap_tree *mt, uint32_t level)
return mt->level[level].has_hiz;
 }
 
+static inline uint32_t
+miptree_level_range_length(const struct intel_mipmap_tree *mt,
+   uint32_t start_level, uint32_t num_levels)
+{
+   assert(start_level >= mt->first_level);
+   assert(start_level <= mt->last_level);
+
+   if (num_levels == INTEL_REMAINING_LAYERS)
+  num_levels = mt->last_level - start_level + 1;
+   /* Check for overflow */
+   assert(start_level + num_levels >= start_level);
+   assert(start_level + num_levels <= mt->last_level + 1);
+
+   return num_levels;
+}
+
+static inline uint32_t
+miptree_layer_range_length(const struct intel_mipmap_tree *mt, uint32_t level,
+   uint32_t start_layer, uint32_t num_layers)
+{
+   assert(level <= mt->last_level);
+   uint32_t total_num_layers;
+
+   if (mt->surf.size > 0) {
+  total_num_layers = mt->surf.dim == ISL_SURF_DIM_3D ?
+ minify(mt->surf.logical_level0_px.depth, level) :
+ mt->surf.logical_level0_px.array_len;
+   } else {
+  total_num_layers = mt->level[level].depth;
+  if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
+  mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ assert(total_num_layers % mt->num_samples == 0);
+ total_num_layers /= mt->num_samples;
+  }
+   }
+
+   assert(start_layer < total_num_layers);
+   if (num_layers == INTEL_REMAINING_LAYERS)
+  num_layers = total_num_layers - start_layer;
+   /* Check for overflow */
+   assert(start_layer + num_layers >= start_layer);
+   assert(start_layer + num_layers <= total_num_layers);
+
+   return num_layers;
+}
+
 bool
 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree *mt,
unsigned start_level, unsigned num_levels,
@@ -2117,14 +2163,12 @@ intel_miptree_has_color_unresolved(const struct 
intel_mipmap_tree *mt,
   return false;
 
/* Clamp the level range to fit the miptree */
-   assert(start_level + num_levels >= start_level);
-   const uint32_t last_level =
-  MIN2(mt->last_level, start_level + num_levels - 1);
-   start_level = MAX2(mt->first_level, start_level);
-   num_levels = last_level - start_level + 1;
+   num_levels = miptree_level_range_length(mt, start_level, num_levels);
 
-   for (uint32_t level = start_level; level <= last_level; level++) {
-  const uint32_t level_layers = MIN2(num_layers, mt->level[level].depth);
+   for (uint32_t l = 0; l < num_levels; l++) {
+  const uint32_t level = start_level + l;
+  const uint32_t level_layers =
+ miptree_layer_range_length(mt, level, start_layer, num_layers);
   for (unsigned a = 0; a < level_layers; a++) {
  enum isl_aux_state aux_state =
 intel_miptree_get_aux_state(mt, level, start_layer + a);
@@ -2506,52 +2550,6 @@ intel_miptree_finish_hiz_write(struct brw_context *brw,
}
 }
 
-static inline uint32_t
-miptree_level_range_length(const struct intel_mipmap_tree *mt,
-   uint32_t start_level, uint32_t num_levels)
-{
-   assert(start_level >= mt->first_level);
-   assert(start_level <= mt->last_level);
-
-   if (num_levels == INTEL_REMAINING_LAYERS)
-  num_levels = mt->last_level - start_level + 1;
-   /* Check for overflow */
-   assert(start_level + num_levels >= start_level);
-   assert(start_level + num_levels <= mt->last_level + 1);
-
-   return num_levels;
-}
-
-static inline uint32_t
-miptree_layer_range_length(const struct intel_mipmap_tree *mt, uint32_t level,
-   uint32_t start_layer, uint32_t num_layers)
-{
-   assert(level <= mt->last_level);
-   uint32_t total_num_layers;
-
-   if (mt->surf.size > 0) {
-  total_num_layers = mt->surf.dim == ISL_SURF_DIM_3D ?
- minify(mt->surf.logical_level0_px.depth, level) :
- mt->surf.logical_level0_px.array_len;
-   } else {
-  total_num_layers = mt->level[level].depth;
-  if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
-  mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
- assert(total_num_layers % mt->num_samples == 0);
- total_num_layers /= mt->num_samples;
-  }
-   }
-
-   assert(start_layer < total_num_layers);
-   if (num_layers == INTEL_REMAINING_LAYERS)
-  num_layers = total_num_layers - start_layer;
-   /* Check for overflow */
-   assert(start_layer + num_layers >= start_layer);
-   assert(start_layer + num_layers <= total_num_layers);
-
-   return num_layers;
-}
-
 void
 intel_miptree_prepare_access(struct brw_context *brw,

[Mesa-dev] [PATCH 20/32] intel/isl: Add an aux state for "partial clear"

[Jason Ekstrand]

---
 src/intel/isl/isl.h   | 88 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 11 
 2 files changed, 64 insertions(+), 35 deletions(-)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index d81df31..68bfcee 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -618,7 +618,11 @@ enum isl_aux_usage {
  *   color by simply changing the clear color without modifying either
  *   surface.
  *
- *2) Compressed w/ Clear:  In this state, neither the auxiliary surface
+ *2) Partial Clear:  In this state, each block in the auxiliary surface
+ *   contains either the magic clear or pass-through value.  See Clear and
+ *   Pass-through for more details.
+ *
+ *3) Compressed w/ Clear:  In this state, neither the auxiliary surface
  *   nor the primary surface has a complete representation of the data.
  *   Instead, both surfaces must be used together or else rendering
  *   corruption may occur.  Depending on the auxiliary compression format
@@ -627,19 +631,19 @@ enum isl_aux_usage {
  *   values.  Blocks may also be in the clear state (see Clear) and have
  *   their value taken from outside the surface.
  *
- *3) Compressed w/o Clear:  This state is identical to the state above
+ *4) Compressed w/o Clear:  This state is identical to the state above
  *   except that no blocks are in the clear state.  In this state, all of
  *   the data required to reconstruct the final sample values is contained
  *   in the auxiliary and primary surface and the clear value is not
  *   considered.
  *
- *4) Resolved:  In this state, the primary surface contains 100% of the
+ *5) Resolved:  In this state, the primary surface contains 100% of the
  *   data.  The auxiliary surface is also valid so the surface can be
  *   validly used with or without aux enabled.  The auxiliary surface may,
  *   however, contain non-trivial data and any update to the primary
  *   surface with aux disabled will cause the two to get out of sync.
  *
- *5) Pass-through:  In this state, the primary surface contains 100% of the
+ *6) Pass-through:  In this state, the primary surface contains 100% of the
  *   data and every block in the auxiliary surface contains a magic value
  *   which indicates that the auxiliary surface should be ignored and the
  *   only the primary surface should be considered.  Updating the primary
@@ -648,7 +652,7 @@ enum isl_aux_usage {
  *   cause the auxiliary buffer to contain non-trivial data and no longer
  *   be in the pass-through state.
  *
- *5) Aux Invalid:  In this state, the primary surface contains 100% of the
+ *7) Aux Invalid:  In this state, the primary surface contains 100% of the
  *   data and the auxiliary surface is completely bogus.  Any attempt to
  *   use the auxiliary surface is liable to result in rendering
  *   corruption.  The only thing that one can do to re-enable aux once
@@ -662,7 +666,8 @@ enum isl_aux_usage {
  *1) Fast Clear:  This operation writes the magic "clear" value to the
  *   auxiliary surface.  This operation will safely transition any slice
  *   of a surface from any state to the clear state so long as the entire
- *   slice is fast cleared at once.
+ *   slice is fast cleared at once.  A fast clear that only covers part of
+ *   a slice of a surface is called a partial fast clear.
  *
  *2) Full Resolve:  This operation combines the auxiliary surface data
  *   with the primary surface data and writes the result to the primary.
@@ -689,34 +694,46 @@ enum isl_aux_usage {
  *   Draw w/ Aux
  *   +--+
  *   |  |
- *   |   +-+ Draw w/ Aux  +-+
- *   +-->| Compressed  |<-|Clear|
- *   |  w/ Clear   |  | |
- *   +-+  +-+
- *  |   ||
- *  Partial |   ||
- *  Resolve |   |Full Resolve|
- *  |   ++   |  Full
- *  ||   | Resolve
- *   Draw w/ aux||   |
- *   +--+   ||   |
- *   |  |  \|/  \|/ \|/
- *   |   +-+ Full Resolve +-+
- *   +-->| Compressed  |->|  Resolved   |
- *   |  w/o Clear  |<-| |
- *   +-+ Draw w/ Aux  +-+
- * /|\   |   |
- *  |  Draw  |   |  Draw
- *  | w/ Aux |   | w/o Aux
- * 

[Mesa-dev] [PATCH 19/32] i965/miptree: Take an aux_usage in prepare/finish

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.c | 25 ++---
 src/mesa/drivers/dri/i965/brw_clear.c |  3 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 53 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  5 ++-
 4 files changed, 48 insertions(+), 38 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 04451b4..43745d2 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -318,17 +318,16 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
 */
if (src_aux_usage == ISL_AUX_USAGE_HIZ)
   src_aux_usage = ISL_AUX_USAGE_NONE;
-   const bool src_aux_supported = src_aux_usage != ISL_AUX_USAGE_NONE;
const bool src_clear_supported =
-  src_aux_supported && (src_mt->format == src_format);
+  src_aux_usage != ISL_AUX_USAGE_NONE && (src_mt->format == src_format);
intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
-src_aux_supported, src_clear_supported);
+src_aux_usage, src_clear_supported);
 
enum isl_aux_usage dst_aux_usage =
   intel_miptree_render_aux_usage(brw, dst_mt, encode_srgb);
-   const bool dst_aux_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
+   const bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
-dst_aux_supported, dst_aux_supported);
+dst_aux_usage, dst_clear_supported);
 
struct isl_surf tmp_surfs[2];
struct blorp_surf src_surf, dst_surf;
@@ -357,7 +356,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
blorp_batch_finish(&batch);
 
intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
-  dst_aux_supported);
+  dst_aux_usage);
 }
 
 void
@@ -418,11 +417,9 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
}
 
intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
-src_aux_usage != ISL_AUX_USAGE_NONE,
-src_clear_supported);
+src_aux_usage, src_clear_supported);
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
-dst_aux_usage != ISL_AUX_USAGE_NONE,
-dst_clear_supported);
+dst_aux_usage, dst_clear_supported);
 
struct isl_surf tmp_surfs[2];
struct blorp_surf src_surf, dst_surf;
@@ -439,7 +436,7 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
blorp_batch_finish(&batch);
 
intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
-  dst_aux_usage != ISL_AUX_USAGE_NONE);
+  dst_aux_usage);
 }
 
 static struct intel_mipmap_tree *
@@ -1033,7 +1030,8 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
   stencil_mask = ctx->Stencil.WriteMask[0] & 0xff;
 
   intel_miptree_prepare_access(brw, stencil_mt, level, 1,
-   start_layer, num_layers, false, false);
+   start_layer, num_layers,
+   ISL_AUX_USAGE_NONE, false);
 
   unsigned stencil_level = level;
   blorp_surf_for_miptree(brw, &stencil_surf, stencil_mt,
@@ -1060,7 +1058,8 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
 
if (stencil_mask) {
   intel_miptree_finish_write(brw, stencil_mt, level,
- start_layer, num_layers, false);
+ start_layer, num_layers,
+ ISL_AUX_USAGE_NONE);
}
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 7fbaa3a..dfb9739 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -163,7 +163,8 @@ brw_fast_clear_depth(struct gl_context *ctx)
 */
if (mt->fast_clear_color.f32[0] != ctx->Depth.Clear) {
   intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
-   0, INTEL_REMAINING_LAYERS, true, false);
+   0, INTEL_REMAINING_LAYERS,
+   ISL_AUX_USAGE_HIZ, false);
   mt->fast_clear_color.f32[0] = ctx->Depth.Clear;
}
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 097b304..b284af9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2163,8 +2163,11 @@ intel_miptree_check_color_resolve(const struct 
brw_context *brw,
 
 static enum blorp_fast_clear_op
 get_ccs_d_resolve_op(enum isl_aux_state aux_state,
- bool ccs_supported, 

[Mesa-dev] [PATCH 17/32] i965/blorp: Use prepare/finish_depth for depth clears

[Jason Ekstrand]

We also simplify the way we handle stencil since we know a priori that
it will have ISL_AUX_USAGE_NONE.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 57 +--
 1 file changed, 21 insertions(+), 36 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 9bad366..04451b4 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -209,17 +209,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
*level -= mt->first_level;
 }
 
-static enum isl_aux_usage
-blorp_get_aux_usage(struct brw_context *brw,
-struct intel_mipmap_tree *mt,
-uint32_t safe_aux_usage)
-{
-   enum isl_aux_usage aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
-   if (!(safe_aux_usage & (1 << aux_usage)))
-  aux_usage = ISL_AUX_USAGE_NONE;
-   return aux_usage;
-}
-
 static enum isl_format
 brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
 bool is_render_target)
@@ -1006,38 +995,30 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
struct isl_surf isl_tmp[4];
struct blorp_surf depth_surf, stencil_surf;
 
+   struct intel_mipmap_tree *depth_mt = NULL;
if (mask & BUFFER_BIT_DEPTH) {
   struct intel_renderbuffer *irb = intel_renderbuffer(depth_rb);
-  struct intel_mipmap_tree *depth_mt =
- find_miptree(GL_DEPTH_BUFFER_BIT, irb);
+  depth_mt = find_miptree(GL_DEPTH_BUFFER_BIT, irb);
 
   level = irb->mt_level;
   start_layer = irb->mt_layer;
   num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
 
-
-  enum isl_aux_usage aux_usage =
- blorp_get_aux_usage(brw, depth_mt, (1 << ISL_AUX_USAGE_HIZ));
-  intel_miptree_prepare_access(brw, depth_mt, level, 1,
-   start_layer, num_layers,
-   aux_usage != ISL_AUX_USAGE_NONE,
-   aux_usage != ISL_AUX_USAGE_NONE);
-  intel_miptree_finish_write(brw, depth_mt, level,
- start_layer, num_layers,
- aux_usage != ISL_AUX_USAGE_NONE);
+  intel_miptree_prepare_depth(brw, depth_mt, level,
+  start_layer, num_layers);
 
   unsigned depth_level = level;
-  blorp_surf_for_miptree(brw, &depth_surf, depth_mt, aux_usage, true,
- &depth_level, start_layer, num_layers,
+  blorp_surf_for_miptree(brw, &depth_surf, depth_mt, depth_mt->aux_usage,
+ true, &depth_level, start_layer, num_layers,
  &isl_tmp[0]);
   assert(depth_level == level);
}
 
uint8_t stencil_mask = 0;
+   struct intel_mipmap_tree *stencil_mt = NULL;
if (mask & BUFFER_BIT_STENCIL) {
   struct intel_renderbuffer *irb = intel_renderbuffer(stencil_rb);
-  struct intel_mipmap_tree *stencil_mt =
- find_miptree(GL_STENCIL_BUFFER_BIT, irb);
+  stencil_mt = find_miptree(GL_STENCIL_BUFFER_BIT, irb);
 
   if (mask & BUFFER_BIT_DEPTH) {
  assert(level == irb->mt_level);
@@ -1051,18 +1032,12 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
 
   stencil_mask = ctx->Stencil.WriteMask[0] & 0xff;
 
-  enum isl_aux_usage aux_usage =
- blorp_get_aux_usage(brw, stencil_mt, 0);
   intel_miptree_prepare_access(brw, stencil_mt, level, 1,
-   start_layer, num_layers,
-   aux_usage != ISL_AUX_USAGE_NONE,
-   aux_usage != ISL_AUX_USAGE_NONE);
-  intel_miptree_finish_write(brw, stencil_mt, level,
- start_layer, num_layers,
- aux_usage != ISL_AUX_USAGE_NONE);
+   start_layer, num_layers, false, false);
 
   unsigned stencil_level = level;
-  blorp_surf_for_miptree(brw, &stencil_surf, stencil_mt, aux_usage, true,
+  blorp_surf_for_miptree(brw, &stencil_surf, stencil_mt,
+ ISL_AUX_USAGE_NONE, true,
  &stencil_level, start_layer, num_layers,
  &isl_tmp[2]);
}
@@ -1077,6 +1052,16 @@ brw_blorp_clear_depth_stencil(struct brw_context *brw,
  (mask & BUFFER_BIT_DEPTH), ctx->Depth.Clear,
  stencil_mask, ctx->Stencil.Clear);
blorp_batch_finish(&batch);
+
+   if (mask & BUFFER_BIT_DEPTH) {
+  intel_miptree_finish_depth(brw, depth_mt, level,
+ start_layer, num_layers, true);
+   }
+
+   if (stencil_mask) {
+  intel_miptree_finish_write(brw, stencil_mt, level,
+ start_layer, num_layers, false);
+   }
 }
 
 void
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 15/32] i965/blorp: Be more accurate about aux usage in blorp_copy

[Jason Ekstrand]

The only real change here is that we now reject clear colors for MCS
with certain formats on gen < 9 because we can't trust that the
reinterpretation will work.  This may cause some MCS partial resolves.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 57 +++
 1 file changed, 44 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 5b5b4bc..4c61afc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -389,23 +389,51 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
dst_level, dst_layer, dst_x, dst_y);
 
-   enum isl_aux_usage src_aux_usage =
-  blorp_get_aux_usage(brw, src_mt,
-  (1 << ISL_AUX_USAGE_MCS) |
-  (1 << ISL_AUX_USAGE_CCS_E));
+   enum isl_aux_usage src_aux_usage, dst_aux_usage;
+   bool src_clear_supported, dst_clear_supported;
+
+   switch (src_mt->aux_usage) {
+   case ISL_AUX_USAGE_MCS:
+   case ISL_AUX_USAGE_CCS_E:
+  src_aux_usage = src_mt->aux_usage;
+  /* Prior to gen9, fast-clear only supported 0/1 clear colors.  Since
+   * we're going to re-interpret the format as an integer format, a 0/1 in
+   * a non-integer format would end up not being 0/1 so we can't handle it
+   * until gen9.
+   */
+  src_clear_supported =
+ brw->gen >= 9 && !_mesa_is_format_integer(src_mt->format);
+  break;
+   default:
+  src_aux_usage = ISL_AUX_USAGE_NONE;
+  src_clear_supported = false;
+  break;
+   }
+
+   switch (dst_mt->aux_usage) {
+   case ISL_AUX_USAGE_MCS:
+   case ISL_AUX_USAGE_CCS_E:
+  dst_aux_usage = dst_mt->aux_usage;
+  /* Prior to gen9, fast-clear only supported 0/1 clear colors.  Since
+   * we're going to re-interpret the format as an integer format, a 0/1 in
+   * a non-integer format would end up not being 0/1 so we can't handle it
+   * until gen9.
+   */
+  dst_clear_supported =
+ brw->gen >= 9 && !_mesa_is_format_integer(dst_mt->format);
+  break;
+   default:
+  dst_aux_usage = ISL_AUX_USAGE_NONE;
+  dst_clear_supported = false;
+  break;
+   }
+
intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
 src_aux_usage != ISL_AUX_USAGE_NONE,
-src_aux_usage != ISL_AUX_USAGE_NONE);
-
-   enum isl_aux_usage dst_aux_usage =
-  blorp_get_aux_usage(brw, dst_mt,
-  (1 << ISL_AUX_USAGE_MCS) |
-  (1 << ISL_AUX_USAGE_CCS_E));
+src_clear_supported);
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
 dst_aux_usage != ISL_AUX_USAGE_NONE,
-dst_aux_usage != ISL_AUX_USAGE_NONE);
-   intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
-  dst_aux_usage != ISL_AUX_USAGE_NONE);
+dst_clear_supported);
 
struct isl_surf tmp_surfs[2];
struct blorp_surf src_surf, dst_surf;
@@ -420,6 +448,9 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
   &dst_surf, dst_level, dst_layer,
   src_x, src_y, dst_x, dst_y, src_width, src_height);
blorp_batch_finish(&batch);
+
+   intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
+  dst_aux_usage != ISL_AUX_USAGE_NONE);
 }
 
 static struct intel_mipmap_tree *
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 18/32] i965/miptree: Refactor some things to use mt->aux_usage

[Jason Ekstrand]

Now that we have this field, it's much easier to switch on it than to
walk an if ladder that checks different things.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 94 ---
 1 file changed, 56 insertions(+), 38 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index e4849ec..097b304 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2522,38 +2522,42 @@ intel_miptree_prepare_access(struct brw_context *brw,
 {
num_levels = miptree_level_range_length(mt, start_level, num_levels);
 
-   if (_mesa_is_format_color_format(mt->format)) {
+   switch (mt->aux_usage) {
+   case ISL_AUX_USAGE_NONE:
+  /* Nothing to do */
+  break;
+
+   case ISL_AUX_USAGE_MCS:
+  assert(mt->mcs_buf);
+  assert(start_level == 0 && num_levels == 1);
+  const uint32_t level_layers =
+ miptree_layer_range_length(mt, 0, start_layer, num_layers);
+  for (uint32_t a = 0; a < level_layers; a++) {
+ intel_miptree_prepare_mcs_access(brw, mt, start_layer + a,
+  aux_supported,
+  fast_clear_supported);
+  }
+  break;
+
+   case ISL_AUX_USAGE_CCS_D:
+   case ISL_AUX_USAGE_CCS_E:
   if (!mt->mcs_buf)
  return;
 
-  if (mt->num_samples > 1) {
- /* Nothing to do for MSAA */
- assert(start_level == 0 && num_levels == 1);
+  for (uint32_t l = 0; l < num_levels; l++) {
+ const uint32_t level = start_level + l;
  const uint32_t level_layers =
-miptree_layer_range_length(mt, 0, start_layer, num_layers);
+miptree_layer_range_length(mt, level, start_layer, num_layers);
  for (uint32_t a = 0; a < level_layers; a++) {
-intel_miptree_prepare_mcs_access(brw, mt, start_layer + a,
- aux_supported,
+intel_miptree_prepare_ccs_access(brw, mt, level,
+ start_layer + a, aux_supported,
  fast_clear_supported);
  }
-  } else {
- for (uint32_t l = 0; l < num_levels; l++) {
-const uint32_t level = start_level + l;
-const uint32_t level_layers =
-   miptree_layer_range_length(mt, level, start_layer, num_layers);
-for (uint32_t a = 0; a < level_layers; a++) {
-   intel_miptree_prepare_ccs_access(brw, mt, level,
-start_layer + a, aux_supported,
-fast_clear_supported);
-}
- }
   }
-   } else if (mt->format == MESA_FORMAT_S_UINT8) {
-  /* Nothing to do for stencil */
-   } else {
-  if (!mt->hiz_buf)
- return;
+  break;
 
+   case ISL_AUX_USAGE_HIZ:
+  assert(mt->hiz_buf);
   for (uint32_t l = 0; l < num_levels; l++) {
  const uint32_t level = start_level + l;
  if (!intel_miptree_level_has_hiz(mt, level))
@@ -2567,6 +2571,10 @@ intel_miptree_prepare_access(struct brw_context *brw,
  fast_clear_supported);
  }
   }
+  break;
+
+   default:
+  unreachable("Invalid aux usage");
}
 }
 
@@ -2578,25 +2586,31 @@ intel_miptree_finish_write(struct brw_context *brw,
 {
num_layers = miptree_layer_range_length(mt, level, start_layer, num_layers);
 
-   if (_mesa_is_format_color_format(mt->format)) {
+   switch (mt->aux_usage) {
+   case ISL_AUX_USAGE_NONE:
+  /* Nothing to do */
+  break;
+
+   case ISL_AUX_USAGE_MCS:
+  assert(mt->mcs_buf);
+  for (uint32_t a = 0; a < num_layers; a++) {
+ intel_miptree_finish_mcs_write(brw, mt, start_layer + a,
+written_with_aux);
+  }
+  break;
+
+   case ISL_AUX_USAGE_CCS_D:
+   case ISL_AUX_USAGE_CCS_E:
   if (!mt->mcs_buf)
  return;
 
-  if (mt->num_samples > 1) {
- assert(level == 0);
- for (uint32_t a = 0; a < num_layers; a++) {
-intel_miptree_finish_mcs_write(brw, mt, start_layer + a,
-   written_with_aux);
- }
-  } else {
- for (uint32_t a = 0; a < num_layers; a++) {
-intel_miptree_finish_ccs_write(brw, mt, level, start_layer + a,
-   written_with_aux);
- }
+  for (uint32_t a = 0; a < num_layers; a++) {
+ intel_miptree_finish_ccs_write(brw, mt, level, start_layer + a,
+written_with_aux);
   }
-   } else if (mt->format == MESA_FORMAT_S_UINT8) {
-  /* Nothing to do for stencil */
-   } else {
+  break;
+
+   case ISL_AUX_USAGE_HIZ:
   if (!intel_miptree_level_has_hiz(mt, level))
  return;
 
@@ -2604,6 +2

[Mesa-dev] [PATCH 16/32] i965/blorp: Use render_aux_usage for color clears

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.c | 18 ++
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 4c61afc..9bad366 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -898,19 +898,10 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__,
   irb->mt, irb->mt_level, irb->mt_layer, num_layers);
 
-
   enum isl_aux_usage aux_usage =
- blorp_get_aux_usage(brw, irb->mt,
- (1 << ISL_AUX_USAGE_MCS) |
- (1 << ISL_AUX_USAGE_CCS_E) |
- (1 << ISL_AUX_USAGE_CCS_D));
-  intel_miptree_prepare_access(brw, irb->mt, level, 1,
-   irb->mt_layer, num_layers,
-   aux_usage != ISL_AUX_USAGE_NONE,
-   aux_usage != ISL_AUX_USAGE_NONE);
-  intel_miptree_finish_write(brw, irb->mt, level,
- irb->mt_layer, num_layers,
- aux_usage != ISL_AUX_USAGE_NONE);
+ intel_miptree_render_aux_usage(brw, irb->mt, encode_srgb);
+  intel_miptree_prepare_render(brw, irb->mt, level, irb->mt_layer,
+   num_layers, encode_srgb);
 
   struct isl_surf isl_tmp[2];
   struct blorp_surf surf;
@@ -929,6 +920,9 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   x0, y0, x1, y1,
   clear_color, color_write_disable);
   blorp_batch_finish(&batch);
+
+  intel_miptree_finish_render(brw, irb->mt, level,
+  irb->mt_layer, num_layers, encode_srgb);
}
 
return;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 11/32] i965/miptree: Add a helper for getting the aux usage for texturing

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 59 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  4 ++
 2 files changed, 43 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 2d2a813..0a63178 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2679,6 +2679,33 @@ can_texture_with_ccs(struct brw_context *brw,
return true;
 }
 
+enum isl_aux_usage
+intel_miptree_texture_aux_usage(struct brw_context *brw,
+struct intel_mipmap_tree *mt,
+enum isl_format view_format)
+{
+   switch (mt->aux_usage) {
+   case ISL_AUX_USAGE_HIZ:
+  if (intel_miptree_sample_with_hiz(brw, mt))
+ return ISL_AUX_USAGE_HIZ;
+  break;
+
+   case ISL_AUX_USAGE_MCS:
+  return ISL_AUX_USAGE_MCS;
+
+   case ISL_AUX_USAGE_CCS_D:
+   case ISL_AUX_USAGE_CCS_E:
+  if (mt->mcs_buf && can_texture_with_ccs(brw, mt, view_format))
+ return ISL_AUX_USAGE_CCS_E;
+  break;
+
+   default:
+  break;
+   }
+
+   return ISL_AUX_USAGE_NONE;
+}
+
 static void
 intel_miptree_prepare_texture_slices(struct brw_context *brw,
  struct intel_mipmap_tree *mt,
@@ -2687,31 +2714,23 @@ intel_miptree_prepare_texture_slices(struct brw_context 
*brw,
  uint32_t start_layer, uint32_t num_layers,
  bool *aux_supported_out)
 {
-   bool aux_supported, clear_supported;
-   if (_mesa_is_format_color_format(mt->format)) {
-  if (mt->num_samples > 1) {
- aux_supported = clear_supported = true;
-  } else {
- aux_supported = can_texture_with_ccs(brw, mt, view_format);
-  }
+   enum isl_aux_usage aux_usage =
+  intel_miptree_texture_aux_usage(brw, mt, view_format);
+   bool clear_supported = aux_usage != ISL_AUX_USAGE_NONE;
 
-  /* Clear color is specified as ints or floats and the conversion is
-   * done by the sampler.  If we have a texture view, we would have to
-   * perform the clear color conversion manually.  Just disable clear
-   * color.
-   */
-  clear_supported = aux_supported && (mt->format == view_format);
-   } else if (mt->format == MESA_FORMAT_S_UINT8) {
-  aux_supported = clear_supported = false;
-   } else {
-  aux_supported = clear_supported = intel_miptree_sample_with_hiz(brw, mt);
-   }
+   /* Clear color is specified as ints or floats and the conversion is done by
+* the sampler.  If we have a texture view, we would have to perform the
+* clear color conversion manually.  Just disable clear color.
+*/
+   if (mt->format != view_format)
+  clear_supported = false;
 
intel_miptree_prepare_access(brw, mt, start_level, num_levels,
 start_layer, num_layers,
-aux_supported, clear_supported);
+aux_usage != ISL_AUX_USAGE_NONE,
+clear_supported);
if (aux_supported_out)
-  *aux_supported_out = aux_supported;
+  *aux_supported_out = aux_usage != ISL_AUX_USAGE_NONE;
 }
 
 void
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 45ac5df..64ea413 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -923,6 +923,10 @@ intel_miptree_access_raw(struct brw_context *brw,
   intel_miptree_finish_write(brw, mt, level, layer, 1, false);
 }
 
+enum isl_aux_usage
+intel_miptree_texture_aux_usage(struct brw_context *brw,
+struct intel_mipmap_tree *mt,
+enum isl_format view_format);
 void
 intel_miptree_prepare_texture(struct brw_context *brw,
   struct intel_mipmap_tree *mt,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 13/32] i965/blorp: Do prepare/finsh manually

[Jason Ekstrand]

Our attempts to do it automatically are problematic at best.  In order
to really be precise, we need to know both the desired aux usage and
whether or not clear is supported.  The current automatic mechanism
doesn't cover this.  This commit itself is not a functional change since
it just reworks everything to be in terms of a silly helper.  Later
commits will switch things over to more sensible ways of choosing usage.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 130 --
 1 file changed, 92 insertions(+), 38 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index ac47f31..f62484f 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -127,9 +127,8 @@ static void
 blorp_surf_for_miptree(struct brw_context *brw,
struct blorp_surf *surf,
struct intel_mipmap_tree *mt,
+   enum isl_aux_usage aux_usage,
bool is_render_target,
-   bool wants_resolve,
-   uint32_t safe_aux_usage,
unsigned *level,
unsigned start_layer, unsigned num_layers,
struct isl_surf tmp_surfs[1])
@@ -163,7 +162,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
   .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
};
 
-   surf->aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
+   surf->aux_usage = aux_usage;
 
struct isl_surf *aux_surf = NULL;
if (mt->mcs_buf)
@@ -171,20 +170,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
else if (mt->hiz_buf)
   aux_surf = &mt->hiz_buf->surf;
 
-   if (wants_resolve) {
-  bool supports_aux = surf->aux_usage != ISL_AUX_USAGE_NONE &&
-  (safe_aux_usage & (1 << surf->aux_usage));
-  intel_miptree_prepare_access(brw, mt, *level, 1, start_layer, num_layers,
-   supports_aux, supports_aux);
-  if (!supports_aux)
- surf->aux_usage = ISL_AUX_USAGE_NONE;
-
-  if (is_render_target) {
- intel_miptree_finish_write(brw, mt, *level, start_layer, num_layers,
-supports_aux);
-  }
-   }
-
if (surf->aux_usage == ISL_AUX_USAGE_HIZ &&
!intel_miptree_level_has_hiz(mt, *level))
   surf->aux_usage = ISL_AUX_USAGE_NONE;
@@ -224,6 +209,17 @@ blorp_surf_for_miptree(struct brw_context *brw,
*level -= mt->first_level;
 }
 
+static enum isl_aux_usage
+blorp_get_aux_usage(struct brw_context *brw,
+struct intel_mipmap_tree *mt,
+uint32_t safe_aux_usage)
+{
+   enum isl_aux_usage aux_usage = intel_miptree_get_aux_isl_usage(brw, mt);
+   if (!(safe_aux_usage & (1 << aux_usage)))
+  aux_usage = ISL_AUX_USAGE_NONE;
+   return aux_usage;
+}
+
 static enum isl_format
 brw_blorp_to_isl_format(struct brw_context *brw, mesa_format format,
 bool is_render_target)
@@ -329,18 +325,30 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
uint32_t src_usage_flags = (1 << ISL_AUX_USAGE_MCS);
if (src_format == src_mt->format)
   src_usage_flags |= (1 << ISL_AUX_USAGE_CCS_E);
+   enum isl_aux_usage src_aux_usage =
+  blorp_get_aux_usage(brw, src_mt, src_usage_flags);
+   intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
+src_aux_usage != ISL_AUX_USAGE_NONE,
+src_aux_usage != ISL_AUX_USAGE_NONE);
 
uint32_t dst_usage_flags = (1 << ISL_AUX_USAGE_MCS);
if (dst_format == dst_mt->format) {
   dst_usage_flags |= (1 << ISL_AUX_USAGE_CCS_E) |
  (1 << ISL_AUX_USAGE_CCS_D);
}
+   enum isl_aux_usage dst_aux_usage =
+  blorp_get_aux_usage(brw, dst_mt, dst_usage_flags);
+   intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
+dst_aux_usage != ISL_AUX_USAGE_NONE,
+dst_aux_usage != ISL_AUX_USAGE_NONE);
+   intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
+  dst_aux_usage != ISL_AUX_USAGE_NONE);
 
struct isl_surf tmp_surfs[2];
struct blorp_surf src_surf, dst_surf;
-   blorp_surf_for_miptree(brw, &src_surf, src_mt, false, true, src_usage_flags,
+   blorp_surf_for_miptree(brw, &src_surf, src_mt, src_aux_usage, false,
   &src_level, src_layer, 1, &tmp_surfs[0]);
-   blorp_surf_for_miptree(brw, &dst_surf, dst_mt, true, true, dst_usage_flags,
+   blorp_surf_for_miptree(brw, &dst_surf, dst_mt, dst_aux_usage, true,
   &dst_level, dst_layer, 1, &tmp_surfs[1]);
 
struct isl_swizzle src_isl_swizzle = {
@@ -381,15 +389,29 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
dst_level, dst_la

[Mesa-dev] [PATCH 05/32] i965/miptree: Remove some unneeded restrictions

[Jason Ekstrand]

intel_miptree_supports_ccs_e should handle the gen >= 9 requirement and
there's no reason why we can't do CCS_E on window system buffers so long
as we resolve.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 415da21..3eac077 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -283,6 +283,9 @@ static bool
 intel_miptree_supports_ccs_e(struct brw_context *brw,
  const struct intel_mipmap_tree *mt)
 {
+   if (brw->gen < 9)
+  return false;
+
/* For now compression is only enabled for integer formats even though
 * there exist supported floating point formats also. This is a heuristic
 * decision based on current public benchmarks. In none of the cases these
@@ -629,7 +632,6 @@ intel_miptree_choose_aux_usage(struct brw_context *brw,
} else if (intel_tiling_supports_ccs(brw, mt->tiling) &&
   intel_miptree_supports_ccs(brw, mt)) {
   if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC) &&
-  brw->gen >= 9 && !mt->is_scanout &&
   intel_miptree_supports_ccs_e(brw, mt)) {
  mt->aux_usage = ISL_AUX_USAGE_CCS_E;
   } else {
-- 
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[Mesa-dev] [PATCH 09/32] i965/miptree: Add support for partially resolving MCS

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.c | 24 
 src/mesa/drivers/dri/i965/brw_blorp.h |  5 
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 40 +--
 3 files changed, 67 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index efa3b39..ac47f31 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1042,6 +1042,30 @@ brw_blorp_resolve_color(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
 }
 
+void
+brw_blorp_mcs_partial_resolve(struct brw_context *brw,
+  struct intel_mipmap_tree *mt,
+  uint32_t start_layer, uint32_t num_layers)
+{
+   DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
+   start_layer, start_layer + num_layers - 1);
+
+   const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
+   enum isl_format isl_format = brw_blorp_to_isl_format(brw, format, true);
+
+   struct isl_surf isl_tmp[1];
+   struct blorp_surf surf;
+   uint32_t level = 0;
+   blorp_surf_for_miptree(brw, &surf, mt, true, false, 0,
+  &level, start_layer, num_layers, isl_tmp);
+
+   struct blorp_batch batch;
+   blorp_batch_init(&brw->blorp, &batch, brw, 0);
+   blorp_mcs_partial_resolve(&batch, &surf, isl_format,
+ start_layer, num_layers);
+   blorp_batch_finish(&batch);
+}
+
 /**
  * Perform a HiZ or depth resolve operation.
  *
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 29d5788..c65a68a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -74,6 +74,11 @@ brw_blorp_resolve_color(struct brw_context *brw,
 enum blorp_fast_clear_op resolve_op);
 
 void
+brw_blorp_mcs_partial_resolve(struct brw_context *brw,
+  struct intel_mipmap_tree *mt,
+  uint32_t start_layer, uint32_t num_layers);
+
+void
 intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
unsigned int level, unsigned int start_layer,
unsigned int num_layers, enum blorp_hiz_op op);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 2521190..1fd39a1 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2323,6 +2323,35 @@ intel_miptree_finish_ccs_write(struct brw_context *brw,
 }
 
 static void
+intel_miptree_prepare_mcs_access(struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t layer,
+ bool mcs_supported,
+ bool fast_clear_supported)
+{
+   switch (intel_miptree_get_aux_state(mt, 0, layer)) {
+   case ISL_AUX_STATE_CLEAR:
+   case ISL_AUX_STATE_COMPRESSED_CLEAR:
+  assert(mcs_supported);
+  if (!fast_clear_supported) {
+ brw_blorp_mcs_partial_resolve(brw, mt, layer, 1);
+ intel_miptree_set_aux_state(brw, mt, 0, layer, 1,
+ ISL_AUX_STATE_COMPRESSED_NO_CLEAR);
+  }
+  break;
+
+   case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
+  assert(mcs_supported);
+  break; /* Nothing to do */
+
+   case ISL_AUX_STATE_RESOLVED:
+   case ISL_AUX_STATE_PASS_THROUGH:
+   case ISL_AUX_STATE_AUX_INVALID:
+  unreachable("Invalid aux state for MCS");
+   }
+}
+
+static void
 intel_miptree_finish_mcs_write(struct brw_context *brw,
struct intel_mipmap_tree *mt,
uint32_t layer,
@@ -2336,10 +2365,10 @@ intel_miptree_finish_mcs_write(struct brw_context *brw,
   break;
 
case ISL_AUX_STATE_COMPRESSED_CLEAR:
+   case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
   assert(written_with_mcs);
   break; /* Nothing to do */
 
-   case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
case ISL_AUX_STATE_RESOLVED:
case ISL_AUX_STATE_PASS_THROUGH:
case ISL_AUX_STATE_AUX_INVALID:
@@ -2499,7 +2528,14 @@ intel_miptree_prepare_access(struct brw_context *brw,
 
   if (mt->num_samples > 1) {
  /* Nothing to do for MSAA */
- assert(aux_supported && fast_clear_supported);
+ assert(start_level == 0 && num_levels == 1);
+ const uint32_t level_layers =
+miptree_layer_range_length(mt, 0, start_layer, num_layers);
+ for (uint32_t a = 0; a < level_layers; a++) {
+intel_miptree_prepare_mcs_access(brw, mt, start_layer + a,
+ aux_supported,
+ fast_clear_supported);
+ }
   } else {
  for (uint32_t l = 0; l < num_levels; l++) {
 const uint3

[Mesa-dev] [PATCH 14/32] i965/blorp: Use texture/render_aux_usage for blits

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_blorp.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index f62484f..5b5b4bc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -322,27 +322,24 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   src_format = dst_format = MESA_FORMAT_R_FLOAT32;
}
 
-   uint32_t src_usage_flags = (1 << ISL_AUX_USAGE_MCS);
-   if (src_format == src_mt->format)
-  src_usage_flags |= (1 << ISL_AUX_USAGE_CCS_E);
enum isl_aux_usage src_aux_usage =
-  blorp_get_aux_usage(brw, src_mt, src_usage_flags);
+  intel_miptree_texture_aux_usage(brw, src_mt, src_format);
+   /* We do format workarounds for some depth formats so we can't reliably
+* sample with HiZ.  One of these days, we should fix that.
+*/
+   if (src_aux_usage == ISL_AUX_USAGE_HIZ)
+  src_aux_usage = ISL_AUX_USAGE_NONE;
+   const bool src_aux_supported = src_aux_usage != ISL_AUX_USAGE_NONE;
+   const bool src_clear_supported =
+  src_aux_supported && (src_mt->format == src_format);
intel_miptree_prepare_access(brw, src_mt, src_level, 1, src_layer, 1,
-src_aux_usage != ISL_AUX_USAGE_NONE,
-src_aux_usage != ISL_AUX_USAGE_NONE);
+src_aux_supported, src_clear_supported);
 
-   uint32_t dst_usage_flags = (1 << ISL_AUX_USAGE_MCS);
-   if (dst_format == dst_mt->format) {
-  dst_usage_flags |= (1 << ISL_AUX_USAGE_CCS_E) |
- (1 << ISL_AUX_USAGE_CCS_D);
-   }
enum isl_aux_usage dst_aux_usage =
-  blorp_get_aux_usage(brw, dst_mt, dst_usage_flags);
+  intel_miptree_render_aux_usage(brw, dst_mt, encode_srgb);
+   const bool dst_aux_supported = dst_aux_usage != ISL_AUX_USAGE_NONE;
intel_miptree_prepare_access(brw, dst_mt, dst_level, 1, dst_layer, 1,
-dst_aux_usage != ISL_AUX_USAGE_NONE,
-dst_aux_usage != ISL_AUX_USAGE_NONE);
-   intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
-  dst_aux_usage != ISL_AUX_USAGE_NONE);
+dst_aux_supported, dst_aux_supported);
 
struct isl_surf tmp_surfs[2];
struct blorp_surf src_surf, dst_surf;
@@ -369,6 +366,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
   dst_x0, dst_y0, dst_x1, dst_y1,
   filter, mirror_x, mirror_y);
blorp_batch_finish(&batch);
+
+   intel_miptree_finish_write(brw, dst_mt, dst_level, dst_layer, 1,
+  dst_aux_supported);
 }
 
 void
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 07/32] i965/miptree: Make layer_range_length return locical layers

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3eac077..8d8ea43 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2461,12 +2461,18 @@ miptree_layer_range_length(const struct 
intel_mipmap_tree *mt, uint32_t level,
assert(level <= mt->last_level);
uint32_t total_num_layers;
 
-   if (mt->surf.size > 0)
+   if (mt->surf.size > 0) {
   total_num_layers = mt->surf.dim == ISL_SURF_DIM_3D ?
- minify(mt->surf.phys_level0_sa.depth, level) :
- mt->surf.phys_level0_sa.array_len;
-   else 
+ minify(mt->surf.logical_level0_px.depth, level) :
+ mt->surf.logical_level0_px.array_len;
+   } else {
   total_num_layers = mt->level[level].depth;
+  if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
+  mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ assert(total_num_layers % mt->num_samples == 0);
+ total_num_layers /= mt->num_samples;
+  }
+   }
 
assert(start_layer < total_num_layers);
if (num_layers == INTEL_REMAINING_LAYERS)
-- 
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[Mesa-dev] [PATCH 12/32] i965/miptree: Rework prepare/finish_render to be in terms of aux_usage

[Jason Ekstrand]

We keep the old and possibly broken method of determining aux usage
intact for now.  Therefore, the only functional change here is that we
may call finish_render a bit more accurately.
---
 src/mesa/drivers/dri/i965/brw_draw.c  |  3 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 69 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  7 ++-
 3 files changed, 59 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 8e01877..b77b44e 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -536,7 +536,8 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context 
*brw)
  
   brw_render_cache_set_add_bo(brw, irb->mt->bo);
   intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
-  irb->mt_layer, irb->layer_count);
+  irb->mt_layer, irb->layer_count,
+  ctx->Color.sRGBEnabled);
}
 }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0a63178..e4849ec 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2763,38 +2763,71 @@ intel_miptree_prepare_fb_fetch(struct brw_context *brw,
 start_layer, num_layers, NULL);
 }
 
-void
-intel_miptree_prepare_render(struct brw_context *brw,
- struct intel_mipmap_tree *mt, uint32_t level,
- uint32_t start_layer, uint32_t layer_count,
- bool srgb_enabled)
+enum isl_aux_usage
+intel_miptree_render_aux_usage(struct brw_context *brw,
+   struct intel_mipmap_tree *mt,
+   bool srgb_enabled)
 {
-   /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
-* the single-sampled color renderbuffers because the CCS buffer isn't
-* supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
-* enabled because otherwise the surface state will be programmed with
-* the linear equivalent format anyway.
-*/
-   if (brw->gen == 9 && srgb_enabled && mt->num_samples <= 1 &&
-   _mesa_get_srgb_format_linear(mt->format) != mt->format) {
+   switch (mt->aux_usage) {
+   case ISL_AUX_USAGE_MCS:
+  assert(mt->mcs_buf);
+  return ISL_AUX_USAGE_MCS;
+
+   case ISL_AUX_USAGE_CCS_D:
+  /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
+   * the single-sampled color renderbuffers because the CCS buffer isn't
+   * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
+   * enabled because otherwise the surface state will be programmed with
+   * the linear equivalent format anyway.
+   */
+  if (srgb_enabled &&
+  _mesa_get_srgb_format_linear(mt->format) != mt->format) {
+ return ISL_AUX_USAGE_NONE;
+  } else if (!mt->mcs_buf) {
+ return ISL_AUX_USAGE_NONE;
+  } else {
+ return ISL_AUX_USAGE_CCS_D;
+  }
 
+   case ISL_AUX_USAGE_CCS_E: {
   /* Lossless compression is not supported for SRGB formats, it
* should be impossible to get here with such surfaces.
*/
-  assert(mt->aux_usage != ISL_AUX_USAGE_CCS_E);
-  intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
-   false, false);
+  assert(!srgb_enabled ||
+ _mesa_get_srgb_format_linear(mt->format) == mt->format);
+
+  return ISL_AUX_USAGE_CCS_E;
+   }
+
+   default:
+  return ISL_AUX_USAGE_NONE;
}
 }
 
 void
+intel_miptree_prepare_render(struct brw_context *brw,
+ struct intel_mipmap_tree *mt, uint32_t level,
+ uint32_t start_layer, uint32_t layer_count,
+ bool srgb_enabled)
+{
+   enum isl_aux_usage aux_usage =
+  intel_miptree_render_aux_usage(brw, mt, srgb_enabled);
+   intel_miptree_prepare_access(brw, mt, level, 1, start_layer, layer_count,
+aux_usage, aux_usage != ISL_AUX_USAGE_NONE);
+}
+
+void
 intel_miptree_finish_render(struct brw_context *brw,
 struct intel_mipmap_tree *mt, uint32_t level,
-uint32_t start_layer, uint32_t layer_count)
+uint32_t start_layer, uint32_t layer_count,
+bool srgb_enabled)
 {
assert(_mesa_is_format_color_format(mt->format));
+
+   enum isl_aux_usage aux_usage =
+  intel_miptree_render_aux_usage(brw, mt, srgb_enabled);
intel_miptree_finish_write(brw, mt, level, start_layer, layer_count,
-  mt->mcs_buf != NULL);
+  aux_usage != ISL_AUX_USAGE_NONE);
 }
 
 void
diff --git a/src/mesa/drivers/dri/i965/inte

[Mesa-dev] [PATCH 10/32] i965/miptree: Partially resolve MCS for texture views

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 1fd39a1..2d2a813 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2693,14 +2693,14 @@ intel_miptree_prepare_texture_slices(struct brw_context 
*brw,
  aux_supported = clear_supported = true;
   } else {
  aux_supported = can_texture_with_ccs(brw, mt, view_format);
-
- /* Clear color is specified as ints or floats and the conversion is
-  * done by the sampler.  If we have a texture view, we would have to
-  * perform the clear color conversion manually.  Just disable clear
-  * color.
-  */
- clear_supported = aux_supported && (mt->format == view_format);
   }
+
+  /* Clear color is specified as ints or floats and the conversion is
+   * done by the sampler.  If we have a texture view, we would have to
+   * perform the clear color conversion manually.  Just disable clear
+   * color.
+   */
+  clear_supported = aux_supported && (mt->format == view_format);
} else if (mt->format == MESA_FORMAT_S_UINT8) {
   aux_supported = clear_supported = false;
} else {
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 04/32] i965/miptree: Stop setting FOR_SCANOUT for renderbuffers

[Jason Ekstrand]

Nothing created through intel_miptree_create_for_renderbuffer will ever
be exposed externally so there's no need to set FOR_SCANOUT.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f292d71..415da21 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1224,8 +1224,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context 
*brw,
uint32_t depth = 1;
GLenum target = num_samples > 1 ? GL_TEXTURE_2D_MULTISAMPLE : GL_TEXTURE_2D;
const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
- MIPTREE_LAYOUT_TILING_ANY |
- MIPTREE_LAYOUT_FOR_SCANOUT;
+ MIPTREE_LAYOUT_TILING_ANY;
 
mt = intel_miptree_create(brw, target, format, 0, 0,
  width, height, depth, num_samples,
-- 
2.5.0.400.gff86faf

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