Re: [Mesa-dev] [PATCH v2 2/2] glsl/linker: location aliasing requires types to have the same width

[Iago Toral]

That was my intent, although it seems my patch doesn't actually
effectively prevent this for types that are not structs since the way
the code is structured we need to mark non-numerical types as consuming
all location slots to ensure that we catch aliasing attempts (which is
what is being done for structs).

At any rate, thinking a bit more about this, I think it makes sense to
allow these on contexts with bindless support enabled. I think in that
case we want to handle images, samplers and regular 64-bit ints as
variables with a numerical type of 64-bit integer and let them share
location space.

I'll send a v3 to allow this and also fix my patch to more effectively
prevent location aliasing of non-numerical types.

Thanks ilia!

Iago

On Mon, 2017-11-06 at 09:51 -0500, Ilia Mirkin wrote:
> So are we saying that you can't have explicit components on a
> bindless
> sampler/image varying, which are defined as 64-bit integer types?
> 
> On Mon, Nov 6, 2017 at 7:22 AM, Iago Toral Quiroga  > wrote:
> > Regarding location aliasing requirements, the OpenGL spec says:
> > 
> >   "Further, when location aliasing, the aliases sharing the
> > location
> >    must have the same underlying numerical type  (floating-point or
> >    integer)."
> > 
> > Khronos has further clarified that this also requires the
> > underlying
> > types to have the same width, so we can't put a float and a double
> > in the same location slot for example. Future versions of the spec
> > will
> > be corrected to make this clear.
> > 
> > This patch amends our implementation to account for this
> > restriction.
> > 
> > In the process of doing this, I also noticed that we would attempt
> > to check aliasing requirements for record variables (including the
> > test
> > for the numerical type) which is not allowed, instead, we should be
> > producing a linker error as soon as we see any attempt to do
> > location
> > aliasing on non-numerical variables. For the particular case of
> > structs,
> > we were producing a linker error in this case, but only because we
> > assumed that struct fields use all components in each location, so
> > any attempt to alias locations consumed by struct fields would
> > produce
> > a link error due to component aliasing, which is not accurate of
> > the
> > actual problem. This patch would make it produce an error for
> > attempting
> > to alias a non-numerical variable instead, which is always
> > accurate.
> > 
> > v2:
> >   - Do not assert if we see invalid numerical types. These come
> > straight from shader code, so we should produce linker errors
> > if
> > shaders attempt to do location aliasing on variables that are
> > not
> > numerical (this includes records, images, etc).
> >   - While we are at it, improve error reporting for the case of
> > numerical type mismatch to include the shader stage.
> > ---
> >  src/compiler/glsl/link_varyings.cpp | 52
> > +++--
> >  1 file changed, 38 insertions(+), 14 deletions(-)
> > 
> > diff --git a/src/compiler/glsl/link_varyings.cpp
> > b/src/compiler/glsl/link_varyings.cpp
> > index 1a9894baab..f284134c90 100644
> > --- a/src/compiler/glsl/link_varyings.cpp
> > +++ b/src/compiler/glsl/link_varyings.cpp
> > @@ -405,15 +405,15 @@ compute_variable_location_slot(ir_variable
> > *var, gl_shader_stage stage)
> > 
> >  struct explicit_location_info {
> > ir_variable *var;
> > -   unsigned numerical_type;
> > +   int numerical_type;
> > unsigned interpolation;
> > bool centroid;
> > bool sample;
> > bool patch;
> >  };
> > 
> > -static inline unsigned
> > -get_numerical_type(const glsl_type *type)
> > +static inline int
> > +get_numerical_sized_type(const glsl_type *type)
> >  {
> > /* From the OpenGL 4.6 spec, section 4.4.1 Input Layout
> > Qualifiers, Page 68,
> >  * (Location aliasing):
> > @@ -421,10 +421,22 @@ get_numerical_type(const glsl_type *type)
> >  *"Further, when location aliasing, the aliases sharing the
> > location
> >  * must have the same underlying numerical type  (floating-
> > point or
> >  * integer)
> > +*
> > +* Khronos has further clarified that this also requires the
> > underlying
> > +* types to have the same width, so we can't put a float and a
> > double
> > +* in the same location slot for example. Future versions of
> > the spec will
> > +* be corrected to make this clear.
> >  */
> > -   if (type->is_float() || type->is_double())
> > +   if (type->is_float())
> >    return GLSL_TYPE_FLOAT;
> > -   return GLSL_TYPE_INT;
> > +   else if (type->is_integer())
> > +  return GLSL_TYPE_INT;
> > +   else if (type->is_double())
> > +  return GLSL_TYPE_DOUBLE;
> > +   else if (type->is_integer_64())
> > +  return GLSL_TYPE_INT64;
> > +   else
> > +  return -1; /* Not a numerical type */
> >  }
> > 
> >  static bool
> > @@ -442,7 +454,8 @@ check_location_aliasing(struct
> > 

[Mesa-dev] [PATCH 7/8] st/mesa: add support for hw atomics to glsl->tgsi. (v3)

[Dave Airlie]

From: Dave Airlie 

This adds support for creating the hw atomic tgsi from
the glsl codepaths.

v2: drop the atomic index and move to backend.
v3: drop buffer decls. (Marek)

Signed-off-by: Dave Airlie 
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 101 -
 1 file changed, 86 insertions(+), 15 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 54e1961..6256f1c 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -152,6 +152,13 @@ find_array_type(struct inout_decl *decls, unsigned count, 
unsigned array_id)
return GLSL_TYPE_ERROR;
 }
 
+struct hwatomic_decl {
+   unsigned location;
+   unsigned binding;
+   unsigned size;
+   unsigned array_id;
+};
+
 struct glsl_to_tgsi_visitor : public ir_visitor {
 public:
glsl_to_tgsi_visitor();
@@ -176,6 +183,9 @@ public:
unsigned num_outputs;
unsigned num_output_arrays;
 
+   struct hwatomic_decl atomic_info[PIPE_MAX_HW_ATOMIC_BUFFERS];
+   unsigned num_atomics;
+   unsigned num_atomic_arrays;
int num_address_regs;
uint32_t samplers_used;
glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
@@ -3206,24 +3216,64 @@ 
glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
exec_node *param = ir->actual_parameters.get_head();
ir_dereference *deref = static_cast(param);
ir_variable *location = deref->variable_referenced();
-
-   st_src_reg buffer(
- PROGRAM_BUFFER, location->data.binding, GLSL_TYPE_ATOMIC_UINT);
-
+   bool has_hw_atomics = st_context(ctx)->has_hw_atomics;
/* Calculate the surface offset */
st_src_reg offset;
unsigned array_size = 0, base = 0;
uint16_t index = 0;
+   st_src_reg resource;
 
get_deref_offsets(deref, _size, , , , false);
 
-   if (offset.file != PROGRAM_UNDEFINED) {
-  emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
-   offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
-  emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
-   offset, st_src_reg_for_int(location->data.offset + index * 
ATOMIC_COUNTER_SIZE));
+   if (has_hw_atomics) {
+  variable_storage *entry = find_variable_storage(location);
+  st_src_reg buffer(PROGRAM_HW_ATOMIC, 0, GLSL_TYPE_ATOMIC_UINT, 
location->data.binding);
+
+  if (!entry) {
+ entry = new(mem_ctx) variable_storage(location, PROGRAM_HW_ATOMIC,
+   num_atomics);
+ _mesa_hash_table_insert(this->variables, location, entry);
+
+ atomic_info[num_atomics].location = location->data.location;
+ atomic_info[num_atomics].binding = location->data.binding;
+ atomic_info[num_atomics].size = 
location->type->arrays_of_arrays_size();
+ atomic_info[num_atomics].array_id = 0;
+ num_atomics++;
+  }
+
+  if (offset.file != PROGRAM_UNDEFINED) {
+ if (atomic_info[entry->index].array_id == 0) {
+num_atomic_arrays++;
+atomic_info[entry->index].array_id = num_atomic_arrays;
+ }
+ buffer.array_id = atomic_info[entry->index].array_id;
+  }
+
+  buffer.index = index;
+  buffer.index += location->data.offset / ATOMIC_COUNTER_SIZE;
+  buffer.has_index2 = true;
+
+  if (offset.file != PROGRAM_UNDEFINED) {
+ buffer.reladdr = ralloc(mem_ctx, st_src_reg);
+ *buffer.reladdr = offset;
+ emit_arl(ir, sampler_reladdr, offset);
+  }
+  offset = st_src_reg_for_int(0);
+
+  resource = buffer;
} else {
-  offset = st_src_reg_for_int(location->data.offset + index * 
ATOMIC_COUNTER_SIZE);
+  st_src_reg buffer(PROGRAM_BUFFER, location->data.binding,
+GLSL_TYPE_ATOMIC_UINT);
+
+  if (offset.file != PROGRAM_UNDEFINED) {
+ emit_asm(ir, TGSI_OPCODE_MUL, st_dst_reg(offset),
+  offset, st_src_reg_for_int(ATOMIC_COUNTER_SIZE));
+ emit_asm(ir, TGSI_OPCODE_ADD, st_dst_reg(offset),
+  offset, st_src_reg_for_int(location->data.offset + index * 
ATOMIC_COUNTER_SIZE));
+  } else {
+ offset = st_src_reg_for_int(location->data.offset + index * 
ATOMIC_COUNTER_SIZE);
+  }
+  resource = buffer;
}
 
ir->return_deref->accept(this);
@@ -3286,7 +3336,7 @@ 
glsl_to_tgsi_visitor::visit_atomic_counter_intrinsic(ir_call *ir)
   inst = emit_asm(ir, opcode, dst, offset, data, data2);
}
 
-   inst->resource = buffer;
+   inst->resource = resource;
 }
 
 void
@@ -4384,10 +4434,13 @@ glsl_to_tgsi_visitor::glsl_to_tgsi_visitor()
array_sizes = NULL;
max_num_arrays = 0;
next_array = 0;
+   num_atomic_arrays = 0;
num_inputs = 0;
num_outputs = 0;
num_input_arrays = 0;
num_output_arrays = 0;
+   num_atomics = 0;
+   num_atomic_arrays = 0;
num_immediates = 0;
num_address_regs = 0;
samplers_used = 0;
@@ -5305,6 +5358,7 

[Mesa-dev] [PATCH 3/8] gallium: add hw atomic buffer binding API.

[Dave Airlie]

From: Dave Airlie 

This API binds atomic buffers for all bound shaders (as per the
GL semantics).

This is needed to support cross shader hw atomic counters.

Signed-off-by: Dave Airlie 
---
 src/gallium/docs/source/context.rst  |  8 
 src/gallium/include/pipe/p_context.h | 16 
 2 files changed, 24 insertions(+)

diff --git a/src/gallium/docs/source/context.rst 
b/src/gallium/docs/source/context.rst
index ba7fef8..5898157 100644
--- a/src/gallium/docs/source/context.rst
+++ b/src/gallium/docs/source/context.rst
@@ -145,6 +145,14 @@ to the array index which is used for sampling.
 * ``sampler_view_destroy`` destroys a sampler view and releases its reference
   to associated texture.
 
+Hardware Atomic buffers
+^^^
+
+Buffers containing hw atomics are required to support the feature
+on some drivers.
+
+Drivers that require this need to fill the ``set_hw_atomic_buffers`` method.
+
 Shader Resources
 
 
diff --git a/src/gallium/include/pipe/p_context.h 
b/src/gallium/include/pipe/p_context.h
index 4609d4d..c2153f7 100644
--- a/src/gallium/include/pipe/p_context.h
+++ b/src/gallium/include/pipe/p_context.h
@@ -332,6 +332,22 @@ struct pipe_context {
   const struct pipe_shader_buffer *buffers);
 
/**
+* Bind an array of hw atomic buffers for use by all shaders.
+* And buffers that were previously bound to the specified range
+* will be unbound.
+*
+* \param start_slot first buffer slot to bind.
+* \param count  number of consecutive buffers to bind.
+* \param buffersarray of pointers to the buffers to bind, it
+*   should contain at least \a count elements
+*   unless it's NULL, in which case no buffers will
+*   be bound.
+*/
+   void (*set_hw_atomic_buffers)(struct pipe_context *,
+ unsigned start_slot, unsigned count,
+ const struct pipe_shader_buffer *buffers);
+
+   /**
 * Bind an array of images that will be used by a shader.
 * Any images that were previously bound to the specified range
 * will be unbound.
-- 
2.9.5

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[Mesa-dev] [PATCH 6/8] st/mesa: setup hw atomic limits. (v1.1)

[Dave Airlie]

From: Dave Airlie 

HW atomics need to use caps to set some limits, and some
other limits may also need limiting.

This fixes things up to work for evergreen hw, it may need
more changes in the future if other hw wants to use this path.

v1.1: fix indent.

Reviewed-by: Nicolai Hähnle 
Signed-off-by: Dave Airlie 
---
 src/mesa/state_tracker/st_extensions.c | 45 ++
 1 file changed, 35 insertions(+), 10 deletions(-)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index fa2d002..d4b8dc9 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -79,6 +79,7 @@ void st_init_limits(struct pipe_screen *screen,
unsigned sh;
boolean can_ubo = TRUE;
int temp;
+   bool ssbo_atomic = true;
 
c->MaxTextureLevels
   = _min(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
@@ -243,11 +244,21 @@ void st_init_limits(struct pipe_screen *screen,
   c->MaxUniformBlockSize / 4 *
   pc->MaxUniformBlocks);
 
-  pc->MaxAtomicCounters = MAX_ATOMIC_COUNTERS;
-  pc->MaxAtomicBuffers = screen->get_shader_param(
-screen, sh, PIPE_SHADER_CAP_MAX_SHADER_BUFFERS) / 2;
-  pc->MaxShaderStorageBlocks = pc->MaxAtomicBuffers;
-
+  temp = screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS);
+  if (temp) {
+ /*
+  * for separate atomic counters get the actual hw limits
+  * per stage on atomic counters and buffers
+  */
+ ssbo_atomic = false;
+ pc->MaxAtomicCounters = temp;
+ pc->MaxAtomicBuffers = screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS);
+ pc->MaxShaderStorageBlocks = screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_SHADER_BUFFERS);
+  } else {
+ pc->MaxAtomicCounters = MAX_ATOMIC_COUNTERS;
+ pc->MaxAtomicBuffers = screen->get_shader_param(screen, sh, 
PIPE_SHADER_CAP_MAX_SHADER_BUFFERS) / 2;
+ pc->MaxShaderStorageBlocks = pc->MaxAtomicBuffers;
+  }
   pc->MaxImageUniforms = screen->get_shader_param(
 screen, sh, PIPE_SHADER_CAP_MAX_SHADER_IMAGES);
 
@@ -407,14 +418,26 @@ void st_init_limits(struct pipe_screen *screen,
   screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
 
c->MaxAtomicBufferBindings =
- c->Program[MESA_SHADER_FRAGMENT].MaxAtomicBuffers;
-   c->MaxCombinedAtomicBuffers =
+  c->Program[MESA_SHADER_FRAGMENT].MaxAtomicBuffers;
+
+   if (!ssbo_atomic) {
+  /* for separate atomic buffers - there atomic buffer size will be
+ limited */
+  c->MaxAtomicBufferSize = 
c->Program[MESA_SHADER_FRAGMENT].MaxAtomicCounters * ATOMIC_COUNTER_SIZE;
+  /* on all HW with separate atomic (evergreen) the following
+ lines are true. not sure it's worth adding CAPs for this at this
+ stage. */
+  c->MaxCombinedAtomicCounters = 
c->Program[MESA_SHADER_FRAGMENT].MaxAtomicCounters;
+  c->MaxCombinedAtomicBuffers = 
c->Program[MESA_SHADER_FRAGMENT].MaxAtomicBuffers;
+   } else {
+  c->MaxCombinedAtomicBuffers =
  c->Program[MESA_SHADER_VERTEX].MaxAtomicBuffers +
  c->Program[MESA_SHADER_TESS_CTRL].MaxAtomicBuffers +
  c->Program[MESA_SHADER_TESS_EVAL].MaxAtomicBuffers +
  c->Program[MESA_SHADER_GEOMETRY].MaxAtomicBuffers +
  c->Program[MESA_SHADER_FRAGMENT].MaxAtomicBuffers;
-   assert(c->MaxCombinedAtomicBuffers <= MAX_COMBINED_ATOMIC_BUFFERS);
+  assert(c->MaxCombinedAtomicBuffers <= MAX_COMBINED_ATOMIC_BUFFERS);
+   }
 
if (c->MaxCombinedAtomicBuffers > 0) {
   extensions->ARB_shader_atomic_counters = GL_TRUE;
@@ -425,8 +448,10 @@ void st_init_limits(struct pipe_screen *screen,
c->ShaderStorageBufferOffsetAlignment =
   screen->get_param(screen, PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT);
if (c->ShaderStorageBufferOffsetAlignment) {
-  c->MaxCombinedShaderStorageBlocks = c->MaxShaderStorageBufferBindings =
- c->MaxCombinedAtomicBuffers;
+  /* for hw atomic counters leaves these at default for now */
+  if (ssbo_atomic)
+ c->MaxCombinedShaderStorageBlocks = c->MaxShaderStorageBufferBindings 
=
+c->MaxCombinedAtomicBuffers;
   c->MaxCombinedShaderOutputResources +=
  c->MaxCombinedShaderStorageBlocks;
   c->MaxShaderStorageBlockSize = 1 << 27;
-- 
2.9.5

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[Mesa-dev] [PATCH 1/8] gallium: add CAPs to support HW atomic counters. (v3)

[Dave Airlie]

From: Dave Airlie 

This looks like an evergreen specific feature, but with atomic
counters AMD have hw specific counters they use instead of operating
on buffers directly. These are separate to the buffer atomics,
so require different limits and code paths.

I've left the CAP for atomic type extensible in case someone
else has a variant on this sort of thing (freedreno maybe?)
and needs to change it.

This adds all the CAPs required to add support for those atomic
counters, along with a related CAP for limiting the number of
output resources.

I'd like to land this and the st patch then I can start to
upstream the evergreen support for these and other GL4.x features.

v2: drop the ATOMIC_COUNTER_MODE cap, just use the return
from the HW counters. If 0 we use the current mode.
v3: fix some rebase errors (Gert Wollny)

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/gallivm/lp_bld_limits.h| 2 ++
 src/gallium/auxiliary/tgsi/tgsi_exec.h   | 2 ++
 src/gallium/docs/source/screen.rst   | 5 -
 src/gallium/drivers/etnaviv/etnaviv_screen.c | 2 ++
 src/gallium/drivers/freedreno/freedreno_screen.c | 2 ++
 src/gallium/drivers/nouveau/nv30/nv30_screen.c   | 2 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.c   | 2 ++
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   | 2 ++
 src/gallium/drivers/r300/r300_screen.c   | 2 ++
 src/gallium/drivers/r600/r600_pipe.c | 2 ++
 src/gallium/drivers/radeonsi/si_pipe.c   | 2 ++
 src/gallium/drivers/svga/svga_screen.c   | 4 
 src/gallium/drivers/vc4/vc4_screen.c | 2 ++
 src/gallium/drivers/virgl/virgl_screen.c | 2 ++
 src/gallium/include/pipe/p_defines.h | 2 ++
 15 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h 
b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
index ea320bb..c7755bf 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h
@@ -140,6 +140,8 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
   return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
   return 32;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h 
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index 514c69e..ad920dc 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -541,6 +541,8 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
   return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
   return PIPE_MAX_SHADER_BUFFERS;
diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index 9f00059..519728f 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -519,7 +519,10 @@ MOV OUT[0], CONST[0][3]  # copy vector 3 of constbuf 0
 * ``PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS``: Whether the merge registers
   TGSI pass is skipped. This might reduce code size and register pressure if
   the underlying driver has a real backend compiler.
-
+* ``PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS``: If atomic counters are separate,
+  how many HW counters are available for this stage. (0 uses SSBO atomics).
+* ``PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS``: If atomic counters are
+  separate, how many atomic counter buffers are available for this stage.
 
 .. _pipe_compute_cap:
 
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index b0c4b7b..e3de442 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -459,6 +459,8 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
   return 0;
}
 
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
b/src/gallium/drivers/freedreno/freedreno_screen.c
index e5504b6..bc66dab 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -554,6 +554,8 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
return 32;
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+   case 

[Mesa-dev] [PATCH 5/8] st/mesa: start adding support for hw atomics atom.

[Dave Airlie]

From: Dave Airlie 

This adds a new atom that calls the new driver API to
bind buffers containing hw atomics.

Signed-off-by: Dave Airlie 
---
 src/mesa/state_tracker/st_atom_atomicbuf.c   | 37 
 src/mesa/state_tracker/st_atom_list.h|  2 ++
 src/mesa/state_tracker/st_cb_bufferobjects.c |  2 +-
 src/mesa/state_tracker/st_context.c  |  9 ++-
 src/mesa/state_tracker/st_context.h  |  1 +
 5 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_atomicbuf.c 
b/src/mesa/state_tracker/st_atom_atomicbuf.c
index ee5944f..9c518a0 100644
--- a/src/mesa/state_tracker/st_atom_atomicbuf.c
+++ b/src/mesa/state_tracker/st_atom_atomicbuf.c
@@ -128,3 +128,40 @@ st_bind_cs_atomics(struct st_context *st)
 
st_bind_atomics(st, prog, PIPE_SHADER_COMPUTE);
 }
+
+void
+st_bind_hw_atomic_buffers(struct st_context *st)
+{
+   struct pipe_shader_buffer buffers[PIPE_MAX_HW_ATOMIC_BUFFERS];
+   int i;
+   int num_buffers = 0;
+
+   if (!st->has_hw_atomics)
+  return;
+
+   for (i = 0; i < MAX_COMBINED_ATOMIC_BUFFERS; i++) {
+  struct gl_buffer_binding *binding = >ctx->AtomicBufferBindings[i];
+  struct st_buffer_object *st_obj = 
st_buffer_object(binding->BufferObject);
+  struct pipe_shader_buffer *sb = [num_buffers];
+
+  if (st_obj && st_obj->buffer) {
+sb->buffer = st_obj->buffer;
+sb->buffer_offset = binding->Offset;
+sb->buffer_size = st_obj->buffer->width0 - binding->Offset;
+
+/* AutomaticSize is FALSE if the buffer was set with BindBufferRange.
+ * Take the minimum just to be sure.
+ */
+if (!binding->AutomaticSize)
+  sb->buffer_size = MIN2(sb->buffer_size, (unsigned) binding->Size);
+num_buffers++;
+  } else {
+sb->buffer = NULL;
+sb->buffer_offset = 0;
+sb->buffer_size = 0;
+  }
+   }
+
+   st->pipe->set_hw_atomic_buffers(st->pipe, 0, num_buffers,
+   buffers);
+}
diff --git a/src/mesa/state_tracker/st_atom_list.h 
b/src/mesa/state_tracker/st_atom_list.h
index b76854e..8f50a72 100644
--- a/src/mesa/state_tracker/st_atom_list.h
+++ b/src/mesa/state_tracker/st_atom_list.h
@@ -66,6 +66,8 @@ ST_STATE(ST_NEW_GS_SSBOS, st_bind_gs_ssbos)
 ST_STATE(ST_NEW_PIXEL_TRANSFER, st_update_pixel_transfer)
 ST_STATE(ST_NEW_TESS_STATE, st_update_tess)
 
+ST_STATE(ST_NEW_HW_ATOMICS, st_bind_hw_atomic_buffers)
+
 /* this must be done after the vertex program update */
 ST_STATE(ST_NEW_VERTEX_ARRAYS, st_update_array)
 
diff --git a/src/mesa/state_tracker/st_cb_bufferobjects.c 
b/src/mesa/state_tracker/st_cb_bufferobjects.c
index 86ebfc6..03fae95 100644
--- a/src/mesa/state_tracker/st_cb_bufferobjects.c
+++ b/src/mesa/state_tracker/st_cb_bufferobjects.c
@@ -348,7 +348,7 @@ bufferobj_data(struct gl_context *ctx,
if (st_obj->Base.UsageHistory & USAGE_TEXTURE_BUFFER)
   ctx->NewDriverState |= ST_NEW_SAMPLER_VIEWS | ST_NEW_IMAGE_UNITS;
if (st_obj->Base.UsageHistory & USAGE_ATOMIC_COUNTER_BUFFER)
-  ctx->NewDriverState |= ST_NEW_ATOMIC_BUFFER;
+  ctx->NewDriverState |= st->has_hw_atomics ? ST_NEW_HW_ATOMICS : 
ST_NEW_ATOMIC_BUFFER;
 
return GL_TRUE;
 }
diff --git a/src/mesa/state_tracker/st_context.c 
b/src/mesa/state_tracker/st_context.c
index 5d8dd8b..e82090b 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -405,6 +405,10 @@ st_create_context_priv( struct gl_context *ctx, struct 
pipe_context *pipe,
st->has_multi_draw_indirect =
   screen->get_param(screen, PIPE_CAP_MULTI_DRAW_INDIRECT);
 
+   st->has_hw_atomics =
+  screen->get_shader_param(screen, PIPE_SHADER_FRAGMENT,
+   PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS) ? true 
: false;
+
/* GL limits and extensions */
st_init_limits(pipe->screen, >Const, >Extensions);
st_init_extensions(pipe->screen, >Const,
@@ -497,7 +501,10 @@ static void st_init_driver_flags(struct st_context *st)
 
/* Shader resources */
f->NewTextureBuffer = ST_NEW_SAMPLER_VIEWS;
-   f->NewAtomicBuffer = ST_NEW_ATOMIC_BUFFER;
+   if (st->has_hw_atomics)
+  f->NewAtomicBuffer = ST_NEW_HW_ATOMICS;
+   else
+  f->NewAtomicBuffer = ST_NEW_ATOMIC_BUFFER;
f->NewShaderStorageBuffer = ST_NEW_STORAGE_BUFFER;
f->NewImageUnits = ST_NEW_IMAGE_UNITS;
 
diff --git a/src/mesa/state_tracker/st_context.h 
b/src/mesa/state_tracker/st_context.h
index ced915e..9f33eed 100644
--- a/src/mesa/state_tracker/st_context.h
+++ b/src/mesa/state_tracker/st_context.h
@@ -129,6 +129,7 @@ struct st_context
boolean invalidate_on_gl_viewport;
boolean draw_needs_minmax_index;
boolean vertex_array_out_of_memory;
+   boolean has_hw_atomics;
 
/* Some state is contained in constant objects.
 * Other state is just parameter values.
-- 
2.9.5

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[Mesa-dev] [PATCH 2/8] gallium/tgsi: start adding hw atomics (v3)

[Dave Airlie]

From: Dave Airlie 

This adds support for a hw atomic counters to TGSI.

A new register file for storing atomic counters is added,
along with a new atomic counter semantic, along with docs
for both.

v2: drop semantic, move hw counter to backend,
Ilia pointed out SSO would have busted my plan, and he
was right.
v3: drop BUFFER decls. (Marek)

Signed-off-by: Dave Airlie 
---
 src/gallium/auxiliary/tgsi/tgsi_strings.c  |  1 +
 src/gallium/auxiliary/tgsi/tgsi_ureg.c | 79 ++
 src/gallium/auxiliary/tgsi/tgsi_ureg.h |  7 +++
 src/gallium/docs/source/tgsi.rst   | 34 +++--
 src/gallium/include/pipe/p_shader_tokens.h |  1 +
 src/gallium/include/pipe/p_state.h |  1 +
 6 files changed, 119 insertions(+), 4 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c 
b/src/gallium/auxiliary/tgsi/tgsi_strings.c
index 0872db9..4f28b49 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c
@@ -58,6 +58,7 @@ static const char *tgsi_file_names[] =
"BUFFER",
"MEMORY",
"CONSTBUF",
+   "HWATOMIC",
 };
 
 const char *tgsi_semantic_names[TGSI_SEMANTIC_COUNT] =
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c 
b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index b26434c..7e88f9b 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -80,6 +80,7 @@ struct ureg_tokens {
 #define UREG_MAX_SYSTEM_VALUE PIPE_MAX_ATTRIBS
 #define UREG_MAX_OUTPUT (4 * PIPE_MAX_SHADER_OUTPUTS)
 #define UREG_MAX_CONSTANT_RANGE 32
+#define UREG_MAX_HW_ATOMIC_RANGE 32
 #define UREG_MAX_IMMEDIATE 4096
 #define UREG_MAX_ADDR 3
 #define UREG_MAX_ARRAY_TEMPS 256
@@ -92,6 +93,15 @@ struct const_decl {
unsigned nr_constant_ranges;
 };
 
+struct hw_atomic_decl {
+   struct {
+  unsigned first;
+  unsigned last;
+  unsigned array_id;
+   } hw_atomic_range[UREG_MAX_HW_ATOMIC_RANGE];
+   unsigned nr_hw_atomic_ranges;
+};
+
 #define DOMAIN_DECL 0
 #define DOMAIN_INSN 1
 
@@ -182,6 +192,8 @@ struct ureg_program
 
struct const_decl const_decls[PIPE_MAX_CONSTANT_BUFFERS];
 
+   struct hw_atomic_decl hw_atomic_decls[PIPE_MAX_HW_ATOMIC_BUFFERS];
+
unsigned properties[TGSI_PROPERTY_COUNT];
 
unsigned nr_addrs;
@@ -583,6 +595,28 @@ out:
return ureg_src_dimension(src, 0);
 }
 
+
+/* Returns a new hw atomic register.  Keep track of which have been
+ * referred to so that we can emit decls later.
+ */
+void
+ureg_DECL_hw_atomic(struct ureg_program *ureg,
+   unsigned first,
+   unsigned last,
+   unsigned buffer_id,
+unsigned array_id)
+{
+   struct hw_atomic_decl *decl = >hw_atomic_decls[buffer_id];
+
+   if (decl->nr_hw_atomic_ranges < UREG_MAX_HW_ATOMIC_RANGE) {
+  uint i = decl->nr_hw_atomic_ranges++;
+
+  decl->hw_atomic_range[i].first = first;
+  decl->hw_atomic_range[i].last = last;
+  decl->hw_atomic_range[i].array_id = array_id;
+   }
+}
+
 static struct ureg_dst alloc_temporary( struct ureg_program *ureg,
 boolean local )
 {
@@ -1501,6 +1535,35 @@ emit_decl_semantic(struct ureg_program *ureg,
}
 }
 
+static void
+emit_decl_atomic_2d(struct ureg_program *ureg,
+   unsigned first,
+   unsigned last,
+   unsigned index2D,
+   unsigned array_id)
+{
+   union tgsi_any_token *out = get_tokens(ureg, DOMAIN_DECL, array_id ? 4 : 3);
+
+   out[0].value = 0;
+   out[0].decl.Type = TGSI_TOKEN_TYPE_DECLARATION;
+   out[0].decl.NrTokens = 3;
+   out[0].decl.File = TGSI_FILE_HW_ATOMIC;
+   out[0].decl.UsageMask = TGSI_WRITEMASK_XYZW;
+   out[0].decl.Dimension = 1;
+   out[0].decl.Array = array_id != 0;
+
+   out[1].value = 0;
+   out[1].decl_range.First = first;
+   out[1].decl_range.Last = last;
+
+   out[2].value = 0;
+   out[2].decl_dim.Index2D = index2D;
+
+   if (array_id) {
+  out[3].value = 0;
+  out[3].array.ArrayID = array_id;
+   }
+}
 
 static void
 emit_decl_fs(struct ureg_program *ureg,
@@ -1908,6 +1971,22 @@ static void emit_decls( struct ureg_program *ureg )
   }
}
 
+   for (i = 0; i < PIPE_MAX_HW_ATOMIC_BUFFERS; i++) {
+  struct hw_atomic_decl *decl = >hw_atomic_decls[i];
+
+  if (decl->nr_hw_atomic_ranges) {
+ uint j;
+
+ for (j = 0; j < decl->nr_hw_atomic_ranges; j++) {
+emit_decl_atomic_2d(ureg,
+   decl->hw_atomic_range[j].first,
+   decl->hw_atomic_range[j].last,
+   i,
+   decl->hw_atomic_range[j].array_id);
+ }
+  }
+   }
+
if (ureg->nr_temps) {
   unsigned array = 0;
   for (i = 0; i < ureg->nr_temps;) {
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.h 
b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
index e88c2c1..96aef25 100644
--- 

[Mesa-dev] [PATCH 8/8] r600: add support for hw atomic counters. (v3)

[Dave Airlie]

From: Dave Airlie 

This adds support for the evergreen/cayman atomic counters.

These are implemented using GDS append/consume counters. The values
for each counter are loaded before drawing and saved after each draw
using special CP packets.

v2: move hw atomic assignment into driver.
v3: fix messing up caps (Gert Wollny), only store ranges in driver,
drop buffers.

Signed-off-by: Dave Airlie 
---
 src/gallium/drivers/r600/evergreen_state.c   | 159 ++
 src/gallium/drivers/r600/r600_pipe.c |  15 ++
 src/gallium/drivers/r600/r600_pipe.h |  22 +++
 src/gallium/drivers/r600/r600_shader.c   | 239 ---
 src/gallium/drivers/r600/r600_shader.h   |  19 +++
 src/gallium/drivers/r600/r600_state_common.c |  46 ++
 src/gallium/drivers/r600/r600d_common.h  |   2 +
 7 files changed, 480 insertions(+), 22 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 96eb35a..634cd96 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3716,6 +3716,38 @@ static void evergreen_set_tess_state(struct pipe_context 
*ctx,
rctx->tess_state_dirty = true;
 }
 
+static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
+   unsigned start_slot,
+   unsigned count,
+   const struct pipe_shader_buffer 
*buffers)
+{
+   struct r600_context *rctx = (struct r600_context *)ctx;
+   struct r600_atomic_buffer_state *astate;
+   int i, idx;
+
+   astate = >atomic_buffer_state;
+
+   /* we'd probably like to expand this to 8 later so put the logic in */
+   for (i = start_slot, idx = 0; i < start_slot + count; i++, idx++) {
+   const struct pipe_shader_buffer *buf;
+   struct pipe_shader_buffer *abuf;
+
+   abuf = >buffer[i];
+
+   if (!buffers || !buffers[idx].buffer) {
+   pipe_resource_reference(>buffer, NULL);
+   astate->enabled_mask &= ~(1 << i);
+   continue;
+   }
+   buf = [idx];
+
+   pipe_resource_reference(>buffer, buf->buffer);
+   abuf->buffer_offset = buf->buffer_offset;
+   abuf->buffer_size = buf->buffer_size;
+   astate->enabled_mask |= (1 << i);
+   }
+}
+
 void evergreen_init_state_functions(struct r600_context *rctx)
 {
unsigned id = 1;
@@ -3801,6 +3833,7 @@ void evergreen_init_state_functions(struct r600_context 
*rctx)
rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
rctx->b.b.set_min_samples = evergreen_set_min_samples;
rctx->b.b.set_tess_state = evergreen_set_tess_state;
+   rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
if (rctx->b.chip_class == EVERGREEN)
 rctx->b.b.get_sample_position = evergreen_get_sample_position;
 else
@@ -4107,3 +4140,129 @@ void eg_trace_emit(struct r600_context *rctx)
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
 }
+
+bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
+   struct r600_shader_atomic 
*combined_atomics,
+   uint8_t *atomic_used_mask_p)
+{
+   struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
+   struct r600_atomic_buffer_state *astate = >atomic_buffer_state;
+   unsigned pkt_flags = 0;
+   uint8_t atomic_used_mask = 0;
+   int i, j, k;
+
+   for (i = 0; i < EG_NUM_HW_STAGES; i++) {
+   uint8_t num_atomic_stage;
+   struct r600_pipe_shader *pshader;
+
+   pshader = rctx->hw_shader_stages[i].shader;
+   if (!pshader)
+   continue;
+
+   num_atomic_stage = pshader->shader.nhwatomic_ranges;
+   if (!num_atomic_stage)
+   continue;
+
+   for (j = 0; j < num_atomic_stage; j++) {
+   struct r600_shader_atomic *atomic = 
>shader.atomics[j];
+   int natomics = atomic->end - atomic->start + 1;
+
+   for (k = 0; k < natomics; k++) {
+   /* seen this in a previous stage */
+   if (atomic_used_mask & (1u << (atomic->hw_idx + 
k)))
+   continue;
+
+   combined_atomics[atomic->hw_idx + k].hw_idx = 
atomic->hw_idx + k;
+   combined_atomics[atomic->hw_idx + k].buffer_id 
= atomic->buffer_id;
+   combined_atomics[atomic->hw_idx + k].start = 
atomic->start + k;
+   

[Mesa-dev] gallium/r600 hw atomic support (v3)

[Dave Airlie]

This is the 3rd submission of the gallium/r600 hw atomic counter support.

This is fixes some rebase artifacts, removes the BUFFER decls from the
TGSI, and fixes some indirect crashes in the r600 backend,

Dave.

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[Mesa-dev] [PATCH 4/8] mesa/program: add hw atomic counter file

[Dave Airlie]

From: Dave Airlie 

This is needed for the GLSL->TGSI translation for hw atomic counters.

Signed-off-by: Dave Airlie 
---
 src/mesa/main/mtypes.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2acf64e..60f06aa 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2059,6 +2059,7 @@ typedef enum
PROGRAM_BUFFER,  /**< for shader buffers, compile-time only */
PROGRAM_MEMORY,  /**< for shared, global and local memory */
PROGRAM_IMAGE,   /**< for shader images, compile-time only */
+   PROGRAM_HW_ATOMIC,   /**< for hw atomic counters, compile-time only */
PROGRAM_FILE_MAX
 } gl_register_file;
 
-- 
2.9.5

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Re: [Mesa-dev] [PATCH 00/12] anv: Add support for the variablePointers feature

[Jason Ekstrand]

On Mon, Nov 6, 2017 at 7:26 PM, Jason Ekstrand  wrote:

> On Mon, Nov 6, 2017 at 6:33 PM, Chad Versace 
> wrote:
>
>> On Mon 06 Nov 2017, Jason Ekstrand wrote:
>> > On Mon, Nov 6, 2017 at 12:18 PM, Chad Versace <[1]
>> chadvers...@chromium.org>
>> > wrote:
>> >
>> > Jason, I tested this series against the khronos-internal vk-gl-cts
>> and
>> > found an assertion failure in src/compiler/spirv. Any thoughts?
>> >
>> > I haven't debugged yet because I don't grok these parts of Mesa.
>> >
>> > vk-gl-cts
>> >
>> > commit a24448cdd72ffdbd8f7f571886625b8a53100979
>> >
>> > mesa
>> >
>> > refs/tags/chadv/test/anv-variable-pointers-2017-11-06-r1
>> > cgit: [2]http://git.kiwitree.net/cgi
>> t/~chadv/mesa/tag/?h=chadv/test/
>> > anv-variable-pointers-2017-11-06-r1
>> > base: master 4bcb48b "radv: add initial copy descriptor
>> support. (v2)"
>> >
>> > error
>> >
>> > Test case 'dEQP-VK.spirv_assembly.instruction.compute.variable_
>> > pointers.complex_types_compute.opptraccesschain_
>> > matrices_two_buffers_second_input'..
>> > INTEL-MESA: debug: anv_GetPhysicalDeviceFeatures2KHR: ignored
>> > VkStructureType VK_STRUCTURE_TYPE_PHYSICAL_DEV
>> ICE_16BIT_STORAGE_FEATURES_
>> > KHR(183000)
>> > deqp-vk: ../../../../../src/mesa/src/co
>> mpiler/spirv/vtn_variables.
>> > c:174: vtn_ssa_offset_pointer_dereference: Assertion `offset'
>> failed.
>> >
>> >
>> > That looks very much like a test bug that I fixed.  The CLs have been
>> merged
>> > into vulkan-gl-cts-1.0.2 but I don't know if that's been merged forward
>> yet.
>> > Try that CTS version and see if it still fails.  It's CLs #1864 and
>> #1863 in
>> > gerrit if you're interested.
>>
>> Weird. I'm testing with vk-gl-cts master a24448c, which contains both of
>> those CLs.
>>
>> To be safe, I did a clean build of libdrm, mesa, and vk-gl-cts (with
>> external/fetch_sources.py, of course). The failure remained.
>>
>> Maybe it's a toolchain problem?
>>
>
> No, it's because I failed at finding 100% of the broken tests.  New CL
> incoming.
>

The tests are fixed in CL #1915.  I feel like a dork now...
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[Mesa-dev] [PATCH v3] i965 : optimized bucket index calculation

[aravindan . muthukumar]

From: Aravindan Muthukumar 

Now the complexity has been reduced to O(1)

Algorithm calculates the index using matrix method.
Matrix arrangement is as below:
Assuming PAGE_SIZE is 4096.

  1*4096   2*40963*40964*4096
  5*4096   6*40967*40968*4096
  10*4096  12*4096   14*4096   16*4096
  20*4096  24*4096   28*4096   32*4096
   ...  ...   ...   ...
   ...  ...   ...   ...
   ...  ...   ...   max_cache_size

From this matrix its clearly seen that every row
follows the below way:
  ...   ...   ...n
n+(1/4)n  n+(1/2)n  n+(3/4)n2n

Row is calculated as log2(size/PAGE_SIZE)
Column is calculated as converting the difference
between the elements to fit into power size of two
and indexing it.

Final Index is (row*4)+(col-1)

Tested with Intel Mesa CI.

Improves performance of 3DMark on BXT by 0.705966% +/- 0.229767% (n=20)

v3: review comments implemented (Ian).
v2: review comments implemented (Jason).
 
Signed-off-by: Aravindan Muthukumar 
Signed-off-by: Kedar Karanje 
Reviewed-by: Yogesh Marathe 
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c | 38 +++---
 1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 17036b5..9a423da 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -86,6 +86,8 @@
 
 #define memclear(s) memset(, 0, sizeof(s))
 
+#define PAGE_SIZE 4096
+
 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
 
 static inline int
@@ -180,19 +182,35 @@ bo_tile_pitch(struct brw_bufmgr *bufmgr, uint32_t pitch, 
uint32_t tiling)
return ALIGN(pitch, tile_width);
 }
 
+/*
+ * This function finds the correct bucket fit for the input size.
+ * The function works with O(1) complexity when the requested size
+ * was queried instead of iterating the size through all the buckets.
+ */
 static struct bo_cache_bucket *
 bucket_for_size(struct brw_bufmgr *bufmgr, uint64_t size)
 {
-   int i;
+   /* Calculating the pages and rounding up to the page size. */
+   const unsigned int pages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
 
-   for (i = 0; i < bufmgr->num_buckets; i++) {
-  struct bo_cache_bucket *bucket = >cache_bucket[i];
-  if (bucket->size >= size) {
- return bucket;
-  }
-   }
+   /* Finding the row number based on the calculated pages. */
+   const unsigned int rows = 30 - __builtin_clz((pages - 1) | 3);
 
-   return NULL;
+   const unsigned int row_max_pages = 4 << rows;
+   const unsigned int prev_row_max_pages = (row_max_pages / 2) & ~2;
+
+   /* Finding the column number using column interval. */
+   int col_size_log2 = rows - 1;
+   col_size_log2 += (col_size_log2 < 0);
+
+   const unsigned int col = ( (pages - prev_row_max_pages +
+( (1 << col_size_log2) - 1) ) >> col_size_log2 );
+
+   /* Calculating the index based on the row and column. */
+   const unsigned int index = (rows * 4) + (col - 1);
+
+   return (index < bufmgr->num_buckets) ?
+  >cache_bucket[index] : NULL;
 }
 
 int
@@ -1254,6 +1272,10 @@ add_bucket(struct brw_bufmgr *bufmgr, int size)
list_inithead(>cache_bucket[i].head);
bufmgr->cache_bucket[i].size = size;
bufmgr->num_buckets++;
+
+   assert(bucket_for_size(bufmgr, size) == >cache_bucket[i]);
+   assert(bucket_for_size(bufmgr, size - 2048) == >cache_bucket[i]);
+   assert(bucket_for_size(bufmgr, size + 1) != >cache_bucket[i]);
 }
 
 static void
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] glsl: Allow precision mismatch on dead uniform with GLSL ES 1.00 (v3)

[Tomasz Figa]

Hi Kenneth,

On Tue, Nov 7, 2017 at 8:18 AM, Kenneth Graunke  wrote:
> On Thursday, October 19, 2017 9:02:20 PM PST Tomasz Figa wrote:
>> Hi Ian, Kenneth,
>>
>> On Wed, Sep 27, 2017 at 2:57 AM, Tomasz Figa  wrote:
>> > Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for
>> > mismatching uniform precision, as required by GLES 3.0 specification and
>> > conformance test-suite.
>> >
>> > Several Android applications, including Forge of Empires, have shaders
>> > which violate this rule, on uniforms that are declared but not used
>> > further in shader code. The problem affects a big number of Android
>> > games, including ones built on top of one of the common 2D graphics
>> > engines and other GLES implementations accept this, which poses a serious
>> > application compatibility issue.
>> >
>> > Starting from GLSL ES 3.0, declarations with conflicting precision
>> > qualifiers are explicitly prohibited. However GLSL ES 1.00 does not
>> > clearly specify the behavior, except that
>> >
>> >   "Uniforms are defined to behave as if they are using the same storage in
>> >   the vertex and fragment processors and may be implemented this way.
>> >   If uniforms are used in both the vertex and fragment shaders, developers
>> >   should be warned if the precisions are different. Conversion of
>> >   precision should never be implicit."
>> >
>> > The word "used" is not clear in this context and might refer to
>> >  1) declared (same as GLES 3.x)
>> >  2) referred after post-processing, or
>> >  3) linked after all optimizations are done.
>> >
>> > Looking at existing applications, 2) or 3) seems to be widely adopted.
>> > To avoid compatibility issues, turn the error into a warning if GLSL ES
>> > version is lower than 3.0 and the data is dead in at least one of the
>> > shaders.
>> >
>> > v3:
>> >  - Add a comment explaining the behavior.
>> >  - Fix bad copy/paste in commit message (s/varyings/uniforms).
>>
>> Would you be able to take a look?
>>
>> Ian, I believe your previous NAK was due to the confusing erroneous
>> copy/paste from the freedesktop bug I made in commit message. Looking
>> at last comment from Kenneth there, we were going to go with my patch,
>> but things remained quiet after that.
>>
>> Thanks,
>> Tomasz
>
> Sorry, this completely fell off my radar.  I've gone ahead and pushed
> your patch.  Dylan also sent out Piglit tests for this case today, which
> I've reviewed.

No worries, thanks a lot!

Best regards,
Tomasz
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Re: [Mesa-dev] [PATCH 00/12] anv: Add support for the variablePointers feature

[Jason Ekstrand]

On Mon, Nov 6, 2017 at 6:33 PM, Chad Versace 
wrote:

> On Mon 06 Nov 2017, Jason Ekstrand wrote:
> > On Mon, Nov 6, 2017 at 12:18 PM, Chad Versace <[1]
> chadvers...@chromium.org>
> > wrote:
> >
> > Jason, I tested this series against the khronos-internal vk-gl-cts
> and
> > found an assertion failure in src/compiler/spirv. Any thoughts?
> >
> > I haven't debugged yet because I don't grok these parts of Mesa.
> >
> > vk-gl-cts
> >
> > commit a24448cdd72ffdbd8f7f571886625b8a53100979
> >
> > mesa
> >
> > refs/tags/chadv/test/anv-variable-pointers-2017-11-06-r1
> > cgit: [2]http://git.kiwitree.net/cgit/~chadv/mesa/tag/?h=chadv/
> test/
> > anv-variable-pointers-2017-11-06-r1
> > base: master 4bcb48b "radv: add initial copy descriptor support.
> (v2)"
> >
> > error
> >
> > Test case 'dEQP-VK.spirv_assembly.instruction.compute.variable_
> > pointers.complex_types_compute.opptraccesschain_
> > matrices_two_buffers_second_input'..
> > INTEL-MESA: debug: anv_GetPhysicalDeviceFeatures2KHR: ignored
> > VkStructureType VK_STRUCTURE_TYPE_PHYSICAL_
> DEVICE_16BIT_STORAGE_FEATURES_
> > KHR(183000)
> > deqp-vk: ../../../../../src/mesa/src/
> compiler/spirv/vtn_variables.
> > c:174: vtn_ssa_offset_pointer_dereference: Assertion `offset'
> failed.
> >
> >
> > That looks very much like a test bug that I fixed.  The CLs have been
> merged
> > into vulkan-gl-cts-1.0.2 but I don't know if that's been merged forward
> yet.
> > Try that CTS version and see if it still fails.  It's CLs #1864 and
> #1863 in
> > gerrit if you're interested.
>
> Weird. I'm testing with vk-gl-cts master a24448c, which contains both of
> those CLs.
>
> To be safe, I did a clean build of libdrm, mesa, and vk-gl-cts (with
> external/fetch_sources.py, of course). The failure remained.
>
> Maybe it's a toolchain problem?
>

No, it's because I failed at finding 100% of the broken tests.  New CL
incoming.
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[Mesa-dev] [PATCH 4/4] radeonsi: add si_screen::has_ls_vgpr_init_bug

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_pipe.c   | 2 ++
 src/gallium/drivers/radeonsi/si_pipe.h   | 1 +
 src/gallium/drivers/radeonsi/si_shader.c | 3 +--
 src/gallium/drivers/radeonsi/si_state_draw.c | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 1ca5ca3..391997d 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1067,20 +1067,22 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
sscreen->assume_no_z_fights =
driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
sscreen->commutative_blend_add =
driQueryOptionb(config->options, 
"radeonsi_commutative_blend_add");
sscreen->clear_db_cache_before_clear =
driQueryOptionb(config->options, 
"radeonsi_clear_db_cache_before_clear");
sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 
&&
sscreen->b.family <= 
CHIP_POLARIS12) ||
   sscreen->b.family == CHIP_VEGA10 ||
   sscreen->b.family == CHIP_RAVEN;
+   sscreen->has_ls_vgpr_init_bug = sscreen->b.family == CHIP_VEGA10 ||
+   sscreen->b.family == CHIP_RAVEN;
 
if (sscreen->b.debug_flags & DBG(DPBB)) {
sscreen->dpbb_allowed = true;
} else {
/* Only enable primitive binning on Raven by default. */
sscreen->dpbb_allowed = sscreen->b.family == CHIP_RAVEN &&
!(sscreen->b.debug_flags & 
DBG(NO_DPBB));
}
 
if (sscreen->b.debug_flags & DBG(DFSM)) {
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index ab82064..6be51bb 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -90,20 +90,21 @@ struct si_screen {
unsignedgs_table_depth;
unsignedtess_offchip_block_dw_size;
boolhas_clear_state;
boolhas_distributed_tess;
boolhas_draw_indirect_multi;
boolhas_out_of_order_rast;
boolassume_no_z_fights;
boolcommutative_blend_add;
boolclear_db_cache_before_clear;
boolhas_msaa_sample_loc_bug;
+   boolhas_ls_vgpr_init_bug;
booldpbb_allowed;
booldfsm_allowed;
boolllvm_has_working_vgpr_indexing;
 
/* Whether shaders are monolithic (1-part) or separate (3-part). */
booluse_monolithic_shaders;
boolrecord_llvm_ir;
 
mtx_t   shader_parts_mutex;
struct si_shader_part   *vs_prologs;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 6bc08dd..c95f8d7 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -6875,22 +6875,21 @@ static void si_build_vs_prolog_function(struct 
si_shader_context *ctx,
 
/* Create the function. */
si_create_function(ctx, "vs_prolog", returns, num_returns, , 0);
func = ctx->main_fn;
 
if (key->vs_prolog.num_merged_next_stage_vgprs) {
if (!key->vs_prolog.is_monolithic)
si_init_exec_from_input(ctx, 3, 0);
 
if (key->vs_prolog.as_ls &&
-   (ctx->screen->b.family == CHIP_VEGA10 ||
-ctx->screen->b.family == CHIP_RAVEN)) {
+   ctx->screen->has_ls_vgpr_init_bug) {
/* If there are no HS threads, SPI loads the LS VGPRs
 * starting at VGPR 0. Shift them back to where they
 * belong.
 */
LLVMValueRef has_hs_threads =
LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
unpack_param(ctx, 3, 8, 8),
ctx->i32_0, "");
 
for (i = 4; i > 0; --i) {
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index b17828e..2d9fcfe 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1275,21 +1275,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct 

[Mesa-dev] [PATCH 1/4] radeonsi/gfx9: don't set gs_table_depth

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_pipe.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index d39e412..649a72e 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -859,20 +859,24 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
FREE(part);
}
}
mtx_destroy(>shader_parts_mutex);
si_destroy_shader_cache(sscreen);
si_destroy_common_screen(>b);
 }
 
 static bool si_init_gs_info(struct si_screen *sscreen)
 {
+   /* gs_table_depth is not used by GFX9 */
+   if (sscreen->b.chip_class >= GFX9)
+   return true;
+
switch (sscreen->b.family) {
case CHIP_OLAND:
case CHIP_HAINAN:
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_MULLINS:
case CHIP_ICELAND:
case CHIP_CARRIZO:
case CHIP_STONEY:
sscreen->gs_table_depth = 16;
@@ -880,22 +884,20 @@ static bool si_init_gs_info(struct si_screen *sscreen)
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_TONGA:
case CHIP_FIJI:
case CHIP_POLARIS10:
case CHIP_POLARIS11:
case CHIP_POLARIS12:
-   case CHIP_VEGA10:
-   case CHIP_RAVEN:
sscreen->gs_table_depth = 32;
return true;
default:
return false;
}
 }
 
 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 {
const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
-- 
2.7.4

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[Mesa-dev] [PATCH 3/4] radeonsi: use ac_create_target_machine

[Marek Olšák]

From: Marek Olšák 

---
 src/amd/common/ac_llvm_util.c  |  7 +--
 src/amd/common/ac_llvm_util.h  |  3 +++
 src/gallium/drivers/radeonsi/si_pipe.c | 22 +++---
 3 files changed, 15 insertions(+), 17 deletions(-)

diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index fb2bc11..429904c 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -121,22 +121,25 @@ const char *ac_get_llvm_processor_name(enum radeon_family 
family)
 }
 
 LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum 
ac_target_machine_options tm_options)
 {
assert(family >= CHIP_TAHITI);
char features[256];
const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? 
"amdgcn-mesa-mesa3d" : "amdgcn--";
LLVMTargetRef target = ac_get_llvm_target(triple);
 
snprintf(features, sizeof(features),
-"+DumpCode,+vgpr-spilling,-fp32-denormals%s",
-tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "");
+
"+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s",
+tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
+tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
+tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
+tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? 
",-promote-alloca" : "");

LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
 target,
 triple,
 ac_get_llvm_processor_name(family),
 features,
 LLVMCodeGenLevelDefault,
 LLVMRelocDefault,
 LLVMCodeModelDefault);
 
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
index d4b3915..7c8b6b0 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -50,20 +50,23 @@ enum ac_func_attr {
/* Legacy intrinsic that needs attributes on function declarations
 * and they must match the internal LLVM definition exactly, otherwise
 * intrinsic selection fails.
 */
AC_FUNC_ATTR_LEGACY   = (1u << 31),
 };
 
 enum ac_target_machine_options {
AC_TM_SUPPORTS_SPILL = (1 << 0),
AC_TM_SISCHED = (1 << 1),
+   AC_TM_FORCE_ENABLE_XNACK = (1 << 2),
+   AC_TM_FORCE_DISABLE_XNACK = (1 << 3),
+   AC_TM_PROMOTE_ALLOCA_TO_SCRATCH = (1 << 4),
 };
 
 const char *ac_get_llvm_processor_name(enum radeon_family family);
 LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum 
ac_target_machine_options tm_options);
 
 LLVMTargetRef ac_get_llvm_target(const char *triple);
 void ac_add_attr_dereferenceable(LLVMValueRef val, uint64_t bytes);
 bool ac_is_sgpr_param(LLVMValueRef param);
 void ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
   int attr_idx, enum ac_func_attr attr);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index e96380c..1ca5ca3 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -138,35 +138,27 @@ static void si_emit_string_marker(struct pipe_context 
*ctx,
 
dd_parse_apitrace_marker(string, len, >apitrace_call_number);
 
if (sctx->b.log)
u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, 
string);
 }
 
 static LLVMTargetMachineRef
 si_create_llvm_target_machine(struct si_screen *sscreen)
 {
-   const char *triple = "amdgcn--";
-   char features[256];
-
-   snprintf(features, sizeof(features),
-
"+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s",
-sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
-sscreen->llvm_has_working_vgpr_indexing ? "" : 
",-promote-alloca",
-sscreen->b.debug_flags & DBG(SI_SCHED) ? ",+si-scheduler" : 
"");
-
-   return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple,
-  
ac_get_llvm_processor_name(sscreen->b.family),
-  features,
-  LLVMCodeGenLevelDefault,
-  LLVMRelocDefault,
-  LLVMCodeModelDefault);
+   enum ac_target_machine_options tm_options =
+   (sscreen->b.debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
+   (sscreen->b.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
+   (sscreen->b.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
+   (!sscreen->llvm_has_working_vgpr_indexing ? 
AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
+
+   return 

[Mesa-dev] [PATCH 2/4] radeonsi: use ac_get_llvm_processor_name

[Marek Olšák]

From: Marek Olšák 

---
 src/amd/common/ac_llvm_util.c |  2 +-
 src/amd/common/ac_llvm_util.h |  2 ++
 src/gallium/drivers/radeon/r600_pipe_common.c | 37 ++-
 src/gallium/drivers/radeon/r600_pipe_common.h |  1 -
 src/gallium/drivers/radeonsi/si_pipe.c|  4 +--
 5 files changed, 7 insertions(+), 39 deletions(-)

diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index 675926e..fb2bc11 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -67,21 +67,21 @@ LLVMTargetRef ac_get_llvm_target(const char *triple)
fprintf(stderr, "Cannot find target for triple %s ", triple);
if (err_message) {
fprintf(stderr, "%s\n", err_message);
}
LLVMDisposeMessage(err_message);
return NULL;
}
return target;
 }
 
-static const char *ac_get_llvm_processor_name(enum radeon_family family)
+const char *ac_get_llvm_processor_name(enum radeon_family family)
 {
switch (family) {
case CHIP_TAHITI:
return "tahiti";
case CHIP_PITCAIRN:
return "pitcairn";
case CHIP_VERDE:
return "verde";
case CHIP_OLAND:
return "oland";
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
index cc4fe3b..d4b3915 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -51,20 +51,22 @@ enum ac_func_attr {
 * and they must match the internal LLVM definition exactly, otherwise
 * intrinsic selection fails.
 */
AC_FUNC_ATTR_LEGACY   = (1u << 31),
 };
 
 enum ac_target_machine_options {
AC_TM_SUPPORTS_SPILL = (1 << 0),
AC_TM_SISCHED = (1 << 1),
 };
+
+const char *ac_get_llvm_processor_name(enum radeon_family family);
 LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum 
ac_target_machine_options tm_options);
 
 LLVMTargetRef ac_get_llvm_target(const char *triple);
 void ac_add_attr_dereferenceable(LLVMValueRef val, uint64_t bytes);
 bool ac_is_sgpr_param(LLVMValueRef param);
 void ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
   int attr_idx, enum ac_func_attr attr);
 void ac_add_func_attributes(LLVMContextRef ctx, LLVMValueRef function,
unsigned attrib_mask);
 void ac_dump_module(LLVMModuleRef module);
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 478f626..aa72187 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -26,20 +26,21 @@
 #include "tgsi/tgsi_parse.h"
 #include "util/list.h"
 #include "util/u_draw_quad.h"
 #include "util/u_memory.h"
 #include "util/u_format_s3tc.h"
 #include "util/u_upload_mgr.h"
 #include "os/os_time.h"
 #include "vl/vl_decoder.h"
 #include "vl/vl_video_buffer.h"
 #include "radeon/radeon_video.h"
+#include "amd/common/ac_llvm_util.h"
 #include "amd/common/sid.h"
 #include 
 #include 
 #include 
 
 #include 
 
 
 struct r600_multi_fence {
struct pipe_reference reference;
@@ -989,54 +990,20 @@ static int r600_get_video_param(struct pipe_screen 
*screen,
return false;
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return true;
case PIPE_VIDEO_CAP_MAX_LEVEL:
return vl_level_supported(screen, profile);
default:
return 0;
}
 }
 
-const char *si_get_llvm_processor_name(enum radeon_family family)
-{
-   switch (family) {
-   case CHIP_TAHITI: return "tahiti";
-   case CHIP_PITCAIRN: return "pitcairn";
-   case CHIP_VERDE: return "verde";
-   case CHIP_OLAND: return "oland";
-   case CHIP_HAINAN: return "hainan";
-   case CHIP_BONAIRE: return "bonaire";
-   case CHIP_KABINI: return "kabini";
-   case CHIP_KAVERI: return "kaveri";
-   case CHIP_HAWAII: return "hawaii";
-   case CHIP_MULLINS:
-   return "mullins";
-   case CHIP_TONGA: return "tonga";
-   case CHIP_ICELAND: return "iceland";
-   case CHIP_CARRIZO: return "carrizo";
-   case CHIP_FIJI:
-   return "fiji";
-   case CHIP_STONEY:
-   return "stoney";
-   case CHIP_POLARIS10:
-   return "polaris10";
-   case CHIP_POLARIS11:
-   case CHIP_POLARIS12: /* same as polaris11 */
-   return "polaris11";
-   case CHIP_VEGA10:
-   case CHIP_RAVEN:
-   return "gfx900";
-   default:
-   return "";
-   }
-}
-
 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
  enum pipe_shader_ir ir_type)
 {
if (ir_type != PIPE_SHADER_IR_TGSI)
return 256;
 
/* Only 16 waves 

Re: [Mesa-dev] [PATCH 4/4] i965: Track the depth and render caches separately

[Jason Ekstrand]

FYI: This appears to help Car Chase by around 1%.  Not much, but I'll take
it.

On Mon, Nov 6, 2017 at 1:38 PM, Jason Ekstrand  wrote:

> Previously, we just had one hash set for tracking depth and render
> caches called brw_context::render_cache.  This is less than ideal
> because the depth and render caches are separate and we can't track
> moves between the depth and the render caches.  This limitation led
> to some unnecessary flushing around the depth cache.  There are cases
> (mostly with BLORP) where we can end up touching a depth or stencil
> buffer through the render cache.  To guard against this, blorp would
> unconditionally do a render_cache_set_check_flush on it's destination
> which meant that if you did any rendering (including a BLORP operation)
> to a given surface and then used it as a blorp destination, you would
> end up flushing it out of the render cache before rendering into it.
>
> Things get worse when you dig into the depth/stencil state code for
> regular GL draw calls.  Because we may end up rendering to a depth
> or stencil buffer via BLORP, we did a render_cache_set_check_flush on
> all depth and stencil buffers in brw_emit_depthbuffer to ensure that
> they got flushed out of the render cache prior to using them for depth
> or stencil testing.  However, because we also need to track dirtiness
> for depth and stencil so that we can implement depth and stencil
> texturing correctly, we were adding all depth and stencil buffers to the
> render cache set in brw_postdraw_set_buffers_need_resolve.  This meant
> that, if anything caused 3DSTATE_DEPTH_BUFFER to get re-emitted
> (currently _NEW_BUFFERS, BRW_NEW_BATCH, and BRW_NEW_BLORP), we would
> almost always do a full pipeline stall and render/depth cache flush.
>
> The root cause of both of these problems is that we can't tell the
> difference between the render and depth caches in our tracking.  This
> commit splits our cache tracking into two sets, one for render and one
> for depth, and properly handles transitioning between the two.  We still
> flush all the caches whenever anything needs to be flushed.  The idea is
> that if we're going to take the hit of a flush and stall, we may as well
> flush everything in the hopes that we can avoid a flush by something
> else later.
> ---
>  src/mesa/drivers/dri/i965/brw_context.h   |  7 ++
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c |  2 +-
>  src/mesa/drivers/dri/i965/intel_fbo.c | 33
> ++-
>  src/mesa/drivers/dri/i965/intel_fbo.h |  5 +---
>  4 files changed, 26 insertions(+), 21 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h
> b/src/mesa/drivers/dri/i965/brw_context.h
> index 3bee3e9..d141872 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -688,6 +688,13 @@ struct brw_context
> struct set *render_cache;
>
> /**
> +* Set of struct brw_bo * that have been used as a depth buffer within
> this
> +* batchbuffer and would need flushing before being used from another
> cache
> +* domain that isn't coherent with it (i.e. the sampler).
> +*/
> +   struct set *depth_cache;
> +
> +   /**
>  * Number of resets observed in the system at context creation.
>  *
>  * This is tracked in the context so that we can determine that another
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index 1a366c7..33c79a2 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -220,7 +220,7 @@ static void
>  intel_batchbuffer_reset_and_clear_render_cache(struct brw_context *brw)
>  {
> intel_batchbuffer_reset(brw);
> -   brw_render_cache_set_clear(brw);
> +   brw_cache_sets_clear(brw);
>  }
>
>  void
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> index 927f589..75c85ec 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -970,19 +970,16 @@ intel_renderbuffer_move_to_temp(struct brw_context
> *brw,
>  }
>
>  void
> -brw_render_cache_set_clear(struct brw_context *brw)
> +brw_cache_sets_clear(struct brw_context *brw)
>  {
> struct set_entry *entry;
>
> set_foreach(brw->render_cache, entry) {
>_mesa_set_remove(brw->render_cache, entry);
> }
> -}
>
> -void
> -brw_render_cache_set_add_bo(struct brw_context *brw, struct brw_bo *bo)
> -{
> -   _mesa_set_add(brw->render_cache, bo);
> +   set_foreach(brw->depth_cache, entry)
> +  _mesa_set_remove(brw->depth_cache, entry);
>  }
>
>  /**
> @@ -997,14 +994,11 @@ brw_render_cache_set_add_bo(struct brw_context
> *brw, struct brw_bo *bo)
>   * necessary is flushed before another use of that BO, but for reuse from
>   * different caches within a batchbuffer, it's all our responsibility.
>   */
> -void
> 

Re: [Mesa-dev] [PATCH 00/12] anv: Add support for the variablePointers feature

[Chad Versace]

On Mon 06 Nov 2017, Jason Ekstrand wrote:
> On Mon, Nov 6, 2017 at 12:18 PM, Chad Versace <[1]chadvers...@chromium.org>
> wrote:
> 
> Jason, I tested this series against the khronos-internal vk-gl-cts and
> found an assertion failure in src/compiler/spirv. Any thoughts?
> 
> I haven't debugged yet because I don't grok these parts of Mesa.
> 
> vk-gl-cts
> 
>     commit a24448cdd72ffdbd8f7f571886625b8a53100979
> 
> mesa
> 
>     refs/tags/chadv/test/anv-variable-pointers-2017-11-06-r1
>     cgit: [2]http://git.kiwitree.net/cgit/~chadv/mesa/tag/?h=chadv/test/
> anv-variable-pointers-2017-11-06-r1
>     base: master 4bcb48b "radv: add initial copy descriptor support. (v2)"
> 
> error
> 
>     Test case 'dEQP-VK.spirv_assembly.instruction.compute.variable_
> pointers.complex_types_compute.opptraccesschain_
> matrices_two_buffers_second_input'..
>     INTEL-MESA: debug: anv_GetPhysicalDeviceFeatures2KHR: ignored
> VkStructureType VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES_
> KHR(183000)
>     deqp-vk: ../../../../../src/mesa/src/compiler/spirv/vtn_variables.
> c:174: vtn_ssa_offset_pointer_dereference: Assertion `offset' failed.
> 
> 
> That looks very much like a test bug that I fixed.  The CLs have been merged
> into vulkan-gl-cts-1.0.2 but I don't know if that's been merged forward yet. 
> Try that CTS version and see if it still fails.  It's CLs #1864 and #1863 in
> gerrit if you're interested.

Weird. I'm testing with vk-gl-cts master a24448c, which contains both of
those CLs.

To be safe, I did a clean build of libdrm, mesa, and vk-gl-cts (with
external/fetch_sources.py, of course). The failure remained.

Maybe it's a toolchain problem?
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Re: [Mesa-dev] [PATCH] nir: fix a typo

[Dylan Baker]

Thanks,
I went ahead and pushed this with my r-b.

Quoting Gwan-gyeong Mun (2017-11-06 15:28:25)
> Signed-off-by: Mun Gwan-gyeong 
> ---
>  src/compiler/nir/nir.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index 87c725625d..0174c30504 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -1155,7 +1155,7 @@ typedef enum {
> nir_texop_tex,/**< Regular texture look-up */
> nir_texop_txb,/**< Texture look-up with LOD bias */
> nir_texop_txl,/**< Texture look-up with explicit LOD */
> -   nir_texop_txd,/**< Texture look-up with partial 
> derivatvies */
> +   nir_texop_txd,/**< Texture look-up with partial 
> derivatives */
> nir_texop_txf,/**< Texel fetch with explicit LOD */
> nir_texop_txf_ms,/**< Multisample texture fetch */
> nir_texop_txf_ms_mcs, /**< Multisample compression value fetch */
> -- 
> 2.15.0
> 
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[Mesa-dev] [PATCH 2/2] intel/compiler: Move the destructor from vec4_visitor to backend_shader

[Jason Ekstrand]

---
 src/intel/compiler/brw_shader.cpp   | 4 
 src/intel/compiler/brw_shader.h | 1 +
 src/intel/compiler/brw_vec4.h   | 1 -
 src/intel/compiler/brw_vec4_visitor.cpp | 4 
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/intel/compiler/brw_shader.cpp 
b/src/intel/compiler/brw_shader.cpp
index 971ff4f..b27a71c 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -673,6 +673,10 @@ backend_shader::backend_shader(const struct brw_compiler 
*compiler,
stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 }
 
+backend_shader::~backend_shader()
+{
+}
+
 bool
 backend_reg::equals(const backend_reg ) const
 {
diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h
index d632f6d..ed434ac 100644
--- a/src/intel/compiler/brw_shader.h
+++ b/src/intel/compiler/brw_shader.h
@@ -197,6 +197,7 @@ protected:
   struct brw_stage_prog_data *stage_prog_data);
 
 public:
+   virtual ~backend_shader();
 
const struct brw_compiler *compiler;
void *log_data; /* Passed to compiler->*_log functions */
diff --git a/src/intel/compiler/brw_vec4.h b/src/intel/compiler/brw_vec4.h
index d828da0..2e93ee2 100644
--- a/src/intel/compiler/brw_vec4.h
+++ b/src/intel/compiler/brw_vec4.h
@@ -72,7 +72,6 @@ public:
void *mem_ctx,
 bool no_spills,
 int shader_time_index);
-   virtual ~vec4_visitor();
 
dst_reg dst_null_f()
{
diff --git a/src/intel/compiler/brw_vec4_visitor.cpp 
b/src/intel/compiler/brw_vec4_visitor.cpp
index db27eae..a845a8d 100644
--- a/src/intel/compiler/brw_vec4_visitor.cpp
+++ b/src/intel/compiler/brw_vec4_visitor.cpp
@@ -1883,10 +1883,6 @@ vec4_visitor::vec4_visitor(const struct brw_compiler 
*compiler,
this->uniforms = 0;
 }
 
-vec4_visitor::~vec4_visitor()
-{
-}
-
 
 void
 vec4_visitor::fail(const char *format, ...)
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 1/2] i965/fs: Get rid of the early return in brw_compile_cs

[Jason Ekstrand]

---
 src/intel/compiler/brw_fs.cpp | 27 ++-
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index c0b6047..996e4c6 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -6925,27 +6925,28 @@ brw_compile_cs(const struct brw_compiler *compiler, 
void *log_data,
   }
}
 
+   const unsigned *ret = NULL;
if (unlikely(cfg == NULL)) {
   assert(fail_msg);
   if (error_str)
  *error_str = ralloc_strdup(mem_ctx, fail_msg);
+   } else {
+  fs_generator g(compiler, log_data, mem_ctx, (void*) key, 
_data->base,
+ v8.promoted_constants, false, MESA_SHADER_COMPUTE);
+  if (INTEL_DEBUG & DEBUG_CS) {
+ char *name = ralloc_asprintf(mem_ctx, "%s compute shader %s",
+  shader->info.label ? shader->info.label :
+   "unnamed",
+  shader->info.name);
+ g.enable_debug(name);
+  }
 
-  return NULL;
-   }
+  g.generate_code(cfg, prog_data->simd_size);
 
-   fs_generator g(compiler, log_data, mem_ctx, (void*) key, _data->base,
-  v8.promoted_constants, false, MESA_SHADER_COMPUTE);
-   if (INTEL_DEBUG & DEBUG_CS) {
-  char *name = ralloc_asprintf(mem_ctx, "%s compute shader %s",
-   shader->info.label ? shader->info.label :
-"unnamed",
-   shader->info.name);
-  g.enable_debug(name);
+  ret = g.get_assembly(_data->base.program_size);
}
 
-   g.generate_code(cfg, prog_data->simd_size);
-
-   return g.get_assembly(_data->base.program_size);
+   return ret;
 }
 
 /**
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH] docs: Fix GL_MESA_program_debug enums

[sroland]

From: Roland Scheidegger 

13b303ff9265b89bdd9100e32f905e9cdadfad81 added the actual enums but
didn't remove the already existing  ones. (And also duplicated
the "fragment" names instead of using the "vertex" names.)
---
 docs/specs/enums.txt | 26 --
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/docs/specs/enums.txt b/docs/specs/enums.txt
index 4b0485f..7b5709b 100644
--- a/docs/specs/enums.txt
+++ b/docs/specs/enums.txt
@@ -46,14 +46,14 @@ GL_MESA_shader_debug.spec: (obsolete)
 GL_DEBUG_ASSERT_MESA 0x875B
 
 GL_MESA_program_debug: (obsolete)
-   GL_FRAGMENT_PROGRAM_CALLBACK_MESA  0x
-   GL_VERTEX_PROGRAM_CALLBACK_MESA0x
-   GL_FRAGMENT_PROGRAM_POSITION_MESA  0x
-   GL_VERTEX_PROGRAM_POSITION_MESA0x
-   GL_FRAGMENT_PROGRAM_CALLBACK_FUNC_MESA 0x
-   GL_FRAGMENT_PROGRAM_CALLBACK_DATA_MESA 0x
-   GL_VERTEX_PROGRAM_CALLBACK_FUNC_MESA   0x
-   GL_VERTEX_PROGRAM_CALLBACK_DATA_MESA   0x
+   GL_FRAGMENT_PROGRAM_POSITION_MESA   0x8BB0
+   GL_FRAGMENT_PROGRAM_CALLBACK_MESA   0x8BB1
+   GL_FRAGMENT_PROGRAM_CALLBACK_FUNC_MESA  0x8BB2
+   GL_FRAGMENT_PROGRAM_CALLBACK_DATA_MESA  0x8BB3
+   GL_VERTEX_PROGRAM_POSITION_MESA 0x8BB4
+   GL_VERTEX_PROGRAM_CALLBACK_MESA 0x8BB5
+   GL_VERTEX_PROGRAM_CALLBACK_FUNC_MESA0x8BB6
+   GL_VERTEX_PROGRAM_CALLBACK_DATA_MESA0x8BB7
 
 GL_MESAX_texture_stack:
GL_TEXTURE_1D_STACK_MESAX0x8759
@@ -63,16 +63,6 @@ GL_MESAX_texture_stack:
GL_TEXTURE_1D_STACK_BINDING_MESAX0x875D
GL_TEXTURE_2D_STACK_BINDING_MESAX0x875E
 
-GL_MESA_program_debug
-   GL_FRAGMENT_PROGRAM_POSITION_MESA   0x8BB0
-   GL_FRAGMENT_PROGRAM_CALLBACK_MESA   0x8BB1
-   GL_FRAGMENT_PROGRAM_CALLBACK_FUNC_MESA  0x8BB2
-   GL_FRAGMENT_PROGRAM_CALLBACK_DATA_MESA  0x8BB3
-   GL_FRAGMENT_PROGRAM_POSITION_MESA   0x8BB4
-   GL_FRAGMENT_PROGRAM_CALLBACK_MESA   0x8BB5
-   GL_FRAGMENT_PROGRAM_CALLBACK_FUNC_MESA  0x8BB6
-   GL_FRAGMENT_PROGRAM_CALLBACK_DATA_MESA  0x8BB7
-
 GL_MESA_tile_raster_order
GL_TILE_RASTER_ORDER_FIXED_MESA 0x8BB8
GL_TILE_RASTER_ORDER_INCREASING_X_MESA  0x8BB9
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 07/13] autotools: set XA versions in configure.ac and configure header file

[Dylan Baker]

Quoting Emil Velikov (2017-11-02 07:00:16)
> On 1 November 2017 at 22:49, Dylan Baker  wrote:
> > Currently the versions are set in the header, and then sed is used to
> > extract them, so that autotools can use them elsewhere.
> >
> > This is odd. Autotools is perfectly capable of configuring the header
> > with the versions, and then they don't need to be extracted from the
> > the header. This is cleaner and more obvious.
> >
> > Tested with make distcheck.
> >
> The idea was to have a place (like VERSION) to grab the version and
> reuse across the board.
> Since nobody the only other user can handle .in files - it makes sense
> to remove the rather nasty construct.
> 
> 
> > +XA_VERSION_MAJOR=2
> > +AC_SUBST([XA_VERSION_MAJOR])
> Please drop the _VERSION bit and temporary variables.

XA_VERSION is used in the xatracker.pc file, do you want a separate change to
replace that with major.minor.tiny? I can certainly add that to v2.

> It make inconsistent with the rest of Mesa.
> 
> AC_SUBST([XA_MAJOR], 2)
> AC_SUBST([XA_MINOR], 2)
> AC_SUBST([XA_TINY], 0)
> 
> With the above
> Reviewed-by: Emil Velikov 
> 
> The tiny -> patch change is good, but please keep that separate change
> and update nine for consistency.
> 
> Thanks
> Emil


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[Mesa-dev] [PATCH] nir: fix a typo

[Gwan-gyeong Mun]

Signed-off-by: Mun Gwan-gyeong 
---
 src/compiler/nir/nir.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 87c725625d..0174c30504 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1155,7 +1155,7 @@ typedef enum {
nir_texop_tex,/**< Regular texture look-up */
nir_texop_txb,/**< Texture look-up with LOD bias */
nir_texop_txl,/**< Texture look-up with explicit LOD */
-   nir_texop_txd,/**< Texture look-up with partial derivatvies 
*/
+   nir_texop_txd,/**< Texture look-up with partial derivatives 
*/
nir_texop_txf,/**< Texel fetch with explicit LOD */
nir_texop_txf_ms,/**< Multisample texture fetch */
nir_texop_txf_ms_mcs, /**< Multisample compression value fetch */
-- 
2.15.0

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Re: [Mesa-dev] [PATCH] i965: disable NIR linking on HSW and below

[Mark Janes]

This needs to be backported/cc'd to stable for the 17.3 release.

Timothy Arceri  writes:

> Fixes: 379b24a40d3d "i965: make use of nir linking"
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103537
> ---
>
> Jason's fixes referenced in the bug report help a little,
> however there are still issues with the vector backend and
> I don't have time to investigate right now so just disable it.
>
>  src/mesa/drivers/dri/i965/brw_link.cpp | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
> b/src/mesa/drivers/dri/i965/brw_link.cpp
> index 9019db56aa0..5cbfd85c05f 100644
> --- a/src/mesa/drivers/dri/i965/brw_link.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_link.cpp
> @@ -272,8 +272,11 @@ brw_link_shader(struct gl_context *ctx, struct 
> gl_shader_program *shProg)
>  * ensures that inter-shader outputs written to in an earlier stage
>  * are eliminated if they are (transitively) not used in a later
>  * stage.
> +*
> +* TODO: Look into Shader of Mordor regressions on HSW and enable this for
> +* all platforms. See: https://bugs.freedesktop.org/show_bug.cgi?id=103537
>  */
> -if (first != last) {
> +if (first != last && brw->screen->devinfo.gen >= 8) {
> int next = last;
> for (int i = next - 1; i >= 0; i--) {
>if (shProg->_LinkedShaders[i] == NULL)
> -- 
> 2.13.6
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Re: [Mesa-dev] [PATCH] i965: Don't emit 3DSTATE_SAMPLER_STATE_POINTERS_VS for compute shaders.

[Jordan Justen]

Reviewed-by: Jordan Justen 

On 2017-10-31 01:58:41, Kenneth Graunke wrote:
> For the render pipeline, the upload_sampler_state_table atom emits
> 3DSTATE_BINDING_TABLE_POINTERS_XS.  It tries to avoid this for compute:
> 
>if (GEN_GEN >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) {
>   /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
>   genX(emit_sampler_state_pointers_xs)(brw, stage_state);
>} ...
> 
> However, we were failing to initialize brw->cs.base.stage, so it was
> left as 0 (MESA_SHADER_VERTEX), causing this condition to break.  We
> then emitted 3DSTATE_SAMPLER_STATE_POINTERS_VS in GPGPU mode, when
> trying to upload CS samplers.  Nothing good can come of this.
> 
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/mesa/drivers/dri/i965/brw_context.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
> b/src/mesa/drivers/dri/i965/brw_context.c
> index eed42468b11..95b00bf8fce 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -874,6 +874,7 @@ brwCreateContext(gl_api api,
> brw->tes.base.stage = MESA_SHADER_TESS_EVAL;
> brw->gs.base.stage = MESA_SHADER_GEOMETRY;
> brw->wm.base.stage = MESA_SHADER_FRAGMENT;
> +   brw->cs.base.stage = MESA_SHADER_COMPUTE;
> if (devinfo->gen >= 8) {
>brw->vtbl.emit_depth_stencil_hiz = gen8_emit_depth_stencil_hiz;
> } else if (devinfo->gen >= 7) {
> -- 
> 2.15.0
> 
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Re: [Mesa-dev] [PATCH] glsl: Allow precision mismatch on dead uniform with GLSL ES 1.00 (v3)

[Kenneth Graunke]

On Thursday, October 19, 2017 9:02:20 PM PST Tomasz Figa wrote:
> Hi Ian, Kenneth,
> 
> On Wed, Sep 27, 2017 at 2:57 AM, Tomasz Figa  wrote:
> > Commit 259fc505454ea6a67aeacf6cdebf1398d9947759 added linker error for
> > mismatching uniform precision, as required by GLES 3.0 specification and
> > conformance test-suite.
> >
> > Several Android applications, including Forge of Empires, have shaders
> > which violate this rule, on uniforms that are declared but not used
> > further in shader code. The problem affects a big number of Android
> > games, including ones built on top of one of the common 2D graphics
> > engines and other GLES implementations accept this, which poses a serious
> > application compatibility issue.
> >
> > Starting from GLSL ES 3.0, declarations with conflicting precision
> > qualifiers are explicitly prohibited. However GLSL ES 1.00 does not
> > clearly specify the behavior, except that
> >
> >   "Uniforms are defined to behave as if they are using the same storage in
> >   the vertex and fragment processors and may be implemented this way.
> >   If uniforms are used in both the vertex and fragment shaders, developers
> >   should be warned if the precisions are different. Conversion of
> >   precision should never be implicit."
> >
> > The word "used" is not clear in this context and might refer to
> >  1) declared (same as GLES 3.x)
> >  2) referred after post-processing, or
> >  3) linked after all optimizations are done.
> >
> > Looking at existing applications, 2) or 3) seems to be widely adopted.
> > To avoid compatibility issues, turn the error into a warning if GLSL ES
> > version is lower than 3.0 and the data is dead in at least one of the
> > shaders.
> >
> > v3:
> >  - Add a comment explaining the behavior.
> >  - Fix bad copy/paste in commit message (s/varyings/uniforms).
> 
> Would you be able to take a look?
> 
> Ian, I believe your previous NAK was due to the confusing erroneous
> copy/paste from the freedesktop bug I made in commit message. Looking
> at last comment from Kenneth there, we were going to go with my patch,
> but things remained quiet after that.
> 
> Thanks,
> Tomasz

Sorry, this completely fell off my radar.  I've gone ahead and pushed
your patch.  Dylan also sent out Piglit tests for this case today, which
I've reviewed.

--Ken


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Re: [Mesa-dev] [PATCH] glsl: s/unsigned/glsl_base_type/ in glsl type code

[Brian Paul]

On 11/06/2017 02:27 PM, Ian Romanick wrote:

On 11/06/2017 01:00 PM, Brian Paul wrote:

Declare glsl_type::sampled_type as glsl_base_type as we do for the
base_type field.  And make base_type a bitfield to save a few bytes.


Hmm... I have mixed feelings about this.  I made a conscious decision to
have base_type be "full size" because it's used a lot.  I suspect there
will be some increase in code size across this change.  There's probably
also some performance difference, but it may not be enough to be
measurable.  I do like actually using type names. :)

As new base types were added, sampled_type remained 2 bits because GLSL
only allows float, int and uint.  This is the reason GLSL_TYPE_UINT64
and GLSL_TYPE_INT64 are not grouped with GLSL_TYPE_UINT and GLSL_TYPE_INT.

I wonder if it might be more compact (in terms of generated code) to
make both fields 8 bits and group them together.


Probably.  I can do that in a v2.  Otherwise, I'm fine with leaving 
base_type unchanged.  Your call.


-Brian





Update glsl_type constructor to take glsl_base_type intead of unsigned

   ^^ instead


and pass GLSL_TYPE_VOID instead of zero.

No Piglit regressions with llvmpipe.
---
  src/compiler/glsl_types.cpp | 14 +++---
  src/compiler/glsl_types.h   | 14 +++---
  2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index 704b63c..1d20b02 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -52,7 +52,7 @@ glsl_type::glsl_type(GLenum gl_type,
 gl_type(gl_type),
 base_type(base_type),
 sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing(0), interface_row_major(0),
+   sampled_type(GLSL_TYPE_VOID), interface_packing(0), interface_row_major(0),
 vector_elements(vector_elements), matrix_columns(matrix_columns),
 length(0)
  {
@@ -79,7 +79,7 @@ glsl_type::glsl_type(GLenum gl_type,

  glsl_type::glsl_type(GLenum gl_type, glsl_base_type base_type,
   enum glsl_sampler_dim dim, bool shadow, bool array,
- unsigned type, const char *name) :
+ glsl_base_type type, const char *name) :
 gl_type(gl_type),
 base_type(base_type),
 sampler_dimensionality(dim), sampler_shadow(shadow),
@@ -104,7 +104,7 @@ glsl_type::glsl_type(const glsl_struct_field *fields, 
unsigned num_fields,
 gl_type(0),
 base_type(GLSL_TYPE_STRUCT),
 sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing(0), interface_row_major(0),
+   sampled_type(GLSL_TYPE_VOID), interface_packing(0), interface_row_major(0),
 vector_elements(0), matrix_columns(0),
 length(num_fields)
  {
@@ -133,7 +133,7 @@ glsl_type::glsl_type(const glsl_struct_field *fields, 
unsigned num_fields,
 gl_type(0),
 base_type(GLSL_TYPE_INTERFACE),
 sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing((unsigned) packing),
+   sampled_type(GLSL_TYPE_VOID), interface_packing((unsigned) packing),
 interface_row_major((unsigned) row_major),
 vector_elements(0), matrix_columns(0),
 length(num_fields)
@@ -161,7 +161,7 @@ glsl_type::glsl_type(const glsl_type *return_type,
 gl_type(0),
 base_type(GLSL_TYPE_FUNCTION),
 sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing(0), interface_row_major(0),
+   sampled_type(GLSL_TYPE_VOID), interface_packing(0), interface_row_major(0),
 vector_elements(0), matrix_columns(0),
 length(num_params)
  {
@@ -193,7 +193,7 @@ glsl_type::glsl_type(const char *subroutine_name) :
 gl_type(0),
 base_type(GLSL_TYPE_SUBROUTINE),
 sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing(0), interface_row_major(0),
+   sampled_type(GLSL_TYPE_VOID), interface_packing(0), interface_row_major(0),
 vector_elements(1), matrix_columns(1),
 length(0)
  {
@@ -444,7 +444,7 @@ _mesa_glsl_release_types(void)
  glsl_type::glsl_type(const glsl_type *array, unsigned length) :
 base_type(GLSL_TYPE_ARRAY),
 sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing(0), interface_row_major(0),
+   sampled_type(GLSL_TYPE_VOID), interface_packing(0), interface_row_major(0),
 vector_elements(0), matrix_columns(0),
 length(length), name(NULL)
  {
diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h
index 0b4a66c..6e2d6cc 100644
--- a/src/compiler/glsl_types.h
+++ b/src/compiler/glsl_types.h
@@ -145,16 +145,16 @@ enum {

  struct glsl_type {
 GLenum gl_type;
-   glsl_base_type base_type;
+   glsl_base_type base_type:6;

 unsigned sampler_dimensionality:4; /**< \see glsl_sampler_dim */
 unsigned sampler_shadow:1;
 unsigned sampler_array:1;

Re: [Mesa-dev] [PATCH 1/2] st/mesa: use enum types instead of int/unsigned

[Charmaine Lee]

For this series, Reviewed-by: Charmaine Lee 


From: Brian Paul 
Sent: Monday, November 6, 2017 1:00:30 PM
To: mesa-dev@lists.freedesktop.org
Cc: Charmaine Lee
Subject: [PATCH 1/2] st/mesa: use enum types instead of int/unsigned

Use the proper enum types for various variables.  Makes life in gdb
a little nicer.
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp   | 7 ---
 src/mesa/state_tracker/st_glsl_to_tgsi_private.h | 6 +++---
 src/mesa/state_tracker/st_mesa_to_tgsi.c | 6 +++---
 src/mesa/state_tracker/st_mesa_to_tgsi.h | 7 ---
 4 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 54e1961..2048b59 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -179,10 +179,10 @@ public:
int num_address_regs;
uint32_t samplers_used;
glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
-   int sampler_targets[PIPE_MAX_SAMPLERS];   /**< One of TGSI_TEXTURE_* */
+   enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
int images_used;
int image_targets[PIPE_MAX_SHADER_IMAGES];
-   unsigned image_formats[PIPE_MAX_SHADER_IMAGES];
+   enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
bool indirect_addr_consts;
int wpos_transform_const;

@@ -6489,7 +6489,8 @@ st_translate_program(
/* texture samplers */
for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
   if (program->samplers_used & (1u << i)) {
- unsigned type = st_translate_texture_type(program->sampler_types[i]);
+ enum tgsi_return_type type =
+st_translate_texture_type(program->sampler_types[i]);

  t->samplers[i] = ureg_DECL_sampler(ureg, i);

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi_private.h 
b/src/mesa/state_tracker/st_glsl_to_tgsi_private.h
index d57525d..bdc7448 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi_private.h
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi_private.h
@@ -127,13 +127,13 @@ public:
unsigned is_64bit_expanded:1;
unsigned sampler_base:5;
unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if not 
array */
-   unsigned tex_target:4; /**< One of TEXTURE_*_INDEX */
+   gl_texture_index tex_target:5;
glsl_base_type tex_type:5;
unsigned tex_shadow:1;
-   unsigned image_format:9;
+   enum pipe_format image_format:9;
unsigned tex_offset_num_offset:3;
unsigned dead_mask:4; /**< Used in dead code elimination */
-   unsigned buffer_access:3; /**< buffer access type */
+   unsigned buffer_access:3; /**< bitmask of TGSI_MEMORY_x bits */

const struct tgsi_opcode_info *info;
 };
diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c 
b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index fa9fa44..8a61776 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -166,8 +166,8 @@ src_register( struct st_translate *t,
 /**
  * Map mesa texture target to TGSI texture target.
  */
-unsigned
-st_translate_texture_target(GLuint textarget, GLboolean shadow)
+enum tgsi_texture_type
+st_translate_texture_target(gl_texture_index textarget, GLboolean shadow)
 {
if (shadow) {
   switch (textarget) {
@@ -225,7 +225,7 @@ st_translate_texture_target(GLuint textarget, GLboolean 
shadow)
 /**
  * Map GLSL base type to TGSI return type.
  */
-unsigned
+enum tgsi_return_type
 st_translate_texture_type(enum glsl_base_type type)
 {
switch (type) {
diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.h 
b/src/mesa/state_tracker/st_mesa_to_tgsi.h
index 106cf85..06e8b70 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.h
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.h
@@ -30,6 +30,7 @@
 #define ST_MESA_TO_TGSI_H

 #include "main/glheader.h"
+#include "main/mtypes.h"

 #include "pipe/p_compiler.h"
 #include "pipe/p_defines.h"
@@ -62,10 +63,10 @@ st_translate_mesa_program(
const ubyte outputSemanticName[],
const ubyte outputSemanticIndex[]);

-unsigned
-st_translate_texture_target(GLuint textarget, GLboolean shadow);
+enum tgsi_texture_type
+st_translate_texture_target(gl_texture_index textarget, GLboolean shadow);

-unsigned
+enum tgsi_return_type
 st_translate_texture_type(enum glsl_base_type type);

 #if defined __cplusplus
--
1.9.1

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[Mesa-dev] [RFC v5 16/19] vulkan/wsi: Add wsi_image_create_with_modifiers

[Louis-Francis Ratté-Boulianne]

Allow the winsys to provide a set of acceptable modifiers to the driver
when creating WSI images.

Signed-off-by: Daniel Stone 
---
 src/amd/vulkan/radv_wsi.c  |   3 ++
 src/intel/vulkan/anv_image.c   |   9 +++-
 src/intel/vulkan/anv_private.h |   3 ++
 src/intel/vulkan/anv_wsi.c | 101 -
 src/vulkan/wsi/wsi_common.h|  11 +
 5 files changed, 114 insertions(+), 13 deletions(-)

diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index c4c6ff9736..a1881eaa35 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -223,6 +223,8 @@ radv_wsi_image_create(VkDevice device_h,
 
wsi_image->image = image_h;
wsi_image->memory = memory_h;
+   wsi_image->linear_image = VK_NULL_HANDLE;
+   wsi_image->linear_memory = VK_NULL_HANDLE;
wsi_image->num_planes = 1;
wsi_image->drm_modifier = DRM_FORMAT_MOD_INVALID;
wsi_image->sizes[0] = image->size;
@@ -256,6 +258,7 @@ radv_wsi_image_free(VkDevice device,
 
 static const struct wsi_image_fns radv_wsi_image_fns = {
.create_wsi_image = radv_wsi_image_create,
+   .create_wsi_image_with_modifiers = NULL,
.free_wsi_image = radv_wsi_image_free,
 };
 
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index cd96bfd0d6..262f6805dc 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -274,12 +274,16 @@ make_surface(const struct anv_device *dev,
/* Translate the Vulkan tiling to an equivalent ISL tiling, then filter the
 * result with an optionally provided ISL tiling argument.
 */
-   isl_tiling_flags_t tiling_flags =
+   isl_tiling_flags_t mask =
   (vk_info->tiling == VK_IMAGE_TILING_LINEAR) ?
   ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
+   isl_tiling_flags_t tiling_flags = mask;
+   isl_tiling_flags_t suboptimal_tiling_flags = 0;
 
if (anv_info->isl_tiling_flags)
   tiling_flags &= anv_info->isl_tiling_flags;
+   if (anv_info->isl_suboptimal_tiling_flags)
+  suboptimal_tiling_flags = anv_info->isl_suboptimal_tiling_flags & mask;
 
assert(tiling_flags);
 
@@ -322,7 +326,8 @@ make_surface(const struct anv_device *dev,
   .min_alignment = 0,
   .row_pitch = anv_info->stride,
   .usage = usage,
-  .tiling_flags = tiling_flags);
+  .tiling_flags = tiling_flags,
+  .suboptimal_tiling_flags = suboptimal_tiling_flags);
 
/* isl_surf_init() will fail only if provided invalid input. Invalid input
 * is illegal in Vulkan.
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 8de5103453..5e5010fde9 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2630,6 +2630,9 @@ struct anv_image_create_info {
/** An opt-in bitmask which filters an ISL-mapping of the Vulkan tiling. */
isl_tiling_flags_t isl_tiling_flags;
 
+   /** Set of possible but suboptimal tiling flags. */
+   isl_tiling_flags_t isl_suboptimal_tiling_flags;
+
/** These flags will be added to any derived from VkImageCreateInfo. */
isl_surf_usage_flags_t isl_extra_usage_flags;
 
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 740bbff9d3..f41db86f12 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -169,12 +169,13 @@ VkResult anv_GetPhysicalDeviceSurfacePresentModesKHR(
 
 
 static VkResult
-anv_wsi_image_create(VkDevice device_h,
- const VkSwapchainCreateInfoKHR *pCreateInfo,
- const VkAllocationCallbacks* pAllocator,
- bool should_export,
- bool different_gpu,
- struct wsi_image_base *wsi_image)
+anv_wsi_image_alloc(VkDevice device_h,
+const VkSwapchainCreateInfoKHR *pCreateInfo,
+const VkAllocationCallbacks* pAllocator,
+bool should_export,
+isl_tiling_flags_t *isl_tiling,
+VkImageTiling vk_tiling,
+struct wsi_image_base *wsi_image)
 {
struct anv_device *device = anv_device_from_handle(device_h);
VkImage image_h;
@@ -183,7 +184,8 @@ anv_wsi_image_create(VkDevice device_h,
VkResult result;
result = anv_image_create(anv_device_to_handle(device),
   &(struct anv_image_create_info) {
- .isl_tiling_flags = ISL_TILING_X_BIT,
+ .isl_tiling_flags = isl_tiling[0],
+ .isl_suboptimal_tiling_flags = isl_tiling[1],
  .stride = 0,
  .vk_info =
   &(VkImageCreateInfo) {
@@ -198,8 +200,7 @@ anv_wsi_image_create(VkDevice device_h,
  .mipLevels = 1,
  .arrayLayers = 1,
  .samples = 1,
- /* FIXME: Need a way to use X tiling to allow scanout */
- .tiling = VK_IMAGE_TILING_OPTIMAL,
+ .tiling = vk_tiling,
  .usage = (pCreateInfo->imageUsage |
VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT),
  

[Mesa-dev] [RFC v5 19/19] vulkan/wsi: Return VK_SUBOPTIMAL_KHR for X11

[Louis-Francis Ratté-Boulianne]

When it is detected that a window could have been flipped
but has been copied because of suboptimal format/modifier.
The Vulkan client should then re-create the swapchain.

Signed-off-by: Louis-Francis Ratté-Boulianne 
---
 src/vulkan/wsi/wsi_common_x11.c | 53 -
 1 file changed, 47 insertions(+), 6 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_x11.c
index 0417166409..2c522a0aeb 100644
--- a/src/vulkan/wsi/wsi_common_x11.c
+++ b/src/vulkan/wsi/wsi_common_x11.c
@@ -130,6 +130,8 @@ wsi_x11_connection_create(const VkAllocationCallbacks 
*alloc,
 {
xcb_query_extension_cookie_t dri3_cookie, pres_cookie, amd_cookie, 
nv_cookie;
xcb_query_extension_reply_t *dri3_reply, *pres_reply, *amd_reply, *nv_reply;
+   bool has_dri3_v1_1 = false;
+   bool has_present_v1_1 = false;
 
struct wsi_x11_connection *wsi_conn =
   vk_alloc(alloc, sizeof(*wsi_conn), 8,
@@ -138,7 +140,7 @@ wsi_x11_connection_create(const VkAllocationCallbacks 
*alloc,
   return NULL;
 
dri3_cookie = xcb_query_extension(conn, 4, "DRI3");
-   pres_cookie = xcb_query_extension(conn, 7, "PRESENT");
+   pres_cookie = xcb_query_extension(conn, 7, "Present");
 
/* We try to be nice to users and emit a warning if they try to use a
 * Vulkan application on a system without DRI3 enabled.  However, this ends
@@ -173,13 +175,27 @@ wsi_x11_connection_create(const VkAllocationCallbacks 
*alloc,
 
   ver_cookie = xcb_dri3_query_version(conn, 1, 1);
   ver_reply = xcb_dri3_query_version_reply(conn, ver_cookie, NULL);
-  wsi_conn->has_dri3_v1_1 =
+  has_dri3_v1_1 =
  (ver_reply->major_version > 1 || ver_reply->minor_version >= 1);
   free(ver_reply);
}
 #endif
 
wsi_conn->has_present = pres_reply->present != 0;
+#if XCB_PRESENT_MAJOR_VERSION > 1 || XCB_PRESENT_MINOR_VERSION >= 1
+   if (wsi_conn->has_present) {
+  xcb_present_query_version_cookie_t ver_cookie;
+  xcb_present_query_version_reply_t *ver_reply;
+
+  ver_cookie = xcb_present_query_version(conn, 1, 1);
+  ver_reply = xcb_present_query_version_reply(conn, ver_cookie, NULL);
+  has_present_v1_1 =
+(ver_reply->major_version > 1 || ver_reply->minor_version >= 1);
+  free(ver_reply);
+   }
+#endif
+
+   wsi_conn->has_dri3_modifiers = has_dri3_v1_1 && has_present_v1_1;
wsi_conn->is_proprietary_x11 = false;
if (amd_reply && amd_reply->present)
   wsi_conn->is_proprietary_x11 = true;
@@ -657,6 +673,7 @@ struct x11_swapchain {
 
bool threaded;
VkResult status;
+   bool suboptimal;
struct wsi_queue present_queue;
struct wsi_queue acquire_queue;
pthread_tqueue_manager;
@@ -736,6 +753,10 @@ x11_handle_dri3_present_event(struct x11_swapchain *chain,
   xcb_present_complete_notify_event_t *complete = (void *) event;
   if (complete->kind == XCB_PRESENT_COMPLETE_KIND_PIXMAP)
  chain->last_present_msc = complete->msc;
+#if XCB_PRESENT_MAJOR_VERSION > 1 || XCB_PRESENT_MINOR_VERSION >= 1
+  if (complete->mode == XCB_PRESENT_COMPLETE_MODE_SUBOPTIMAL_COPY)
+ chain->suboptimal = true;
+#endif
   break;
}
 
@@ -865,6 +886,11 @@ x11_present_to_x11(struct x11_swapchain *chain, uint32_t 
image_index,
if (chain->base.present_mode == VK_PRESENT_MODE_IMMEDIATE_KHR)
   options |= XCB_PRESENT_OPTION_ASYNC;
 
+#if XCB_PRESENT_MAJOR_VERSION > 1 || XCB_PRESENT_MINOR_VERSION >= 1
+   if (chain->has_dri3_modifiers)
+  options |= XCB_PRESENT_OPTION_SUBOPTIMAL;
+#endif
+
xshmfence_reset(image->shm_fence);
 
++chain->send_sbc;
@@ -899,11 +925,18 @@ x11_acquire_next_image(struct wsi_swapchain *anv_chain,
uint32_t *image_index)
 {
struct x11_swapchain *chain = (struct x11_swapchain *)anv_chain;
+   VkResult result;
 
if (chain->threaded) {
-  return x11_acquire_next_image_from_queue(chain, image_index, timeout);
+  result = x11_acquire_next_image_from_queue(chain, image_index, timeout);
+   } else {
+  result = x11_acquire_next_image_poll_x11(chain, image_index, timeout);
+   }
+
+   if (result != VK_SUCCESS) {
+  return result;
} else {
-  return x11_acquire_next_image_poll_x11(chain, image_index, timeout);
+  return chain->suboptimal ? VK_SUBOPTIMAL_KHR : VK_SUCCESS;
}
 }
 
@@ -913,12 +946,19 @@ x11_queue_present(struct wsi_swapchain *anv_chain,
   const VkPresentRegionKHR *damage)
 {
struct x11_swapchain *chain = (struct x11_swapchain *)anv_chain;
+   VkResult result;
 
if (chain->threaded) {
   wsi_queue_push(>present_queue, image_index);
-  return chain->status;
+  result = chain->status;
+   } else {
+  result = x11_present_to_x11(chain, 

[Mesa-dev] [RFC v5 18/19] RFC: vulkan/wsi: Add support for DRI3 v1.1

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

Adds support for multiple planes and buffer modifiers.

v4: Rename "has_dri3_v1_1" to "has_dri3_modifiers"
---
 src/vulkan/wsi/wsi_common_x11.c | 238 +---
 1 file changed, 199 insertions(+), 39 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_x11.c
index e48d746305..0417166409 100644
--- a/src/vulkan/wsi/wsi_common_x11.c
+++ b/src/vulkan/wsi/wsi_common_x11.c
@@ -36,6 +36,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "util/hash_table.h"
 
 #include "vk_util.h"
@@ -50,6 +51,7 @@
 
 struct wsi_x11_connection {
bool has_dri3;
+   bool has_dri3_modifiers;
bool has_present;
bool is_proprietary_x11;
 };
@@ -164,6 +166,19 @@ wsi_x11_connection_create(const VkAllocationCallbacks 
*alloc,
}
 
wsi_conn->has_dri3 = dri3_reply->present != 0;
+#if XCB_DRI3_MAJOR_VERSION > 1 || XCB_DRI3_MINOR_VERSION >= 1
+   if (wsi_conn->has_dri3) {
+  xcb_dri3_query_version_cookie_t ver_cookie;
+  xcb_dri3_query_version_reply_t *ver_reply;
+
+  ver_cookie = xcb_dri3_query_version(conn, 1, 1);
+  ver_reply = xcb_dri3_query_version_reply(conn, ver_cookie, NULL);
+  wsi_conn->has_dri3_v1_1 =
+ (ver_reply->major_version > 1 || ver_reply->minor_version >= 1);
+  free(ver_reply);
+   }
+#endif
+
wsi_conn->has_present = pres_reply->present != 0;
wsi_conn->is_proprietary_x11 = false;
if (amd_reply && amd_reply->present)
@@ -626,6 +641,8 @@ struct x11_image {
 struct x11_swapchain {
struct wsi_swapchainbase;
 
+   bool has_dri3_modifiers;
+
xcb_connection_t *   conn;
xcb_window_t window;
xcb_gc_t gc;
@@ -679,7 +696,10 @@ x11_get_image_and_linear(struct wsi_swapchain *drv_chain,
 {
struct x11_swapchain *chain = (struct x11_swapchain *)drv_chain;
*image = chain->images[imageIndex].base.image;
-   *linear_image = chain->images[imageIndex].linear_base.image;
+   if (chain->images[imageIndex].base.linear_image != VK_NULL_HANDLE)
+  *linear_image = chain->images[imageIndex].base.linear_image;
+   else
+  *linear_image = chain->images[imageIndex].linear_base.image;
 }
 
 static VkResult
@@ -954,56 +974,100 @@ static VkResult
 x11_image_init(VkDevice device_h, struct x11_swapchain *chain,
const VkSwapchainCreateInfoKHR *pCreateInfo,
const VkAllocationCallbacks* pAllocator,
-   struct x11_image *image)
+   uint64_t **modifiers, int *num_modifiers,
+   int num_tranches, struct x11_image *image)
 {
xcb_void_cookie_t cookie;
VkResult result;
uint32_t bpp = 32;
-
-   result = chain->base.image_fns->create_wsi_image(device_h,
-pCreateInfo,
-pAllocator,
-
!chain->base.needs_linear_copy,
-false,
->base);
-   if (result != VK_SUCCESS)
-  return result;
-
-   if (chain->base.needs_linear_copy) {
+   int i;
+
+   image->linear_base.image = VK_NULL_HANDLE;
+   image->linear_base.memory = VK_NULL_HANDLE;
+
+   if (chain->base.image_fns->create_wsi_image_with_modifiers) {
+  result = chain->base.image_fns->create_wsi_image_with_modifiers(device_h,
+  
pCreateInfo,
+  
pAllocator,
+  
chain->base.needs_linear_copy,
+  
modifiers,
+  
num_modifiers,
+  
num_tranches,
+  
>base);
+  if (result != VK_SUCCESS)
+ return result;
+   } else {
   result = chain->base.image_fns->create_wsi_image(device_h,
pCreateInfo,
pAllocator,
-   true,
-   true,
-   >linear_base);
-
-  if (result != VK_SUCCESS) {
- chain->base.image_fns->free_wsi_image(device_h, pAllocator,
-   >base);
+   
!chain->base.needs_linear_copy,
+   false,
+   

[Mesa-dev] [RFC v5 15/19] vulkan/wsi: Rename needs_linear_copy to different_gpu

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

That's what it actually means; the fact it generally means a linear copy
is requires is incidental.

Signed-off-by: Daniel Stone 
---
 src/amd/vulkan/radv_wsi.c   | 6 +++---
 src/intel/vulkan/anv_wsi.c  | 2 +-
 src/vulkan/wsi/wsi_common.h | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 66082c4ae0..c4c6ff9736 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -144,7 +144,7 @@ radv_wsi_image_create(VkDevice device_h,
  const VkSwapchainCreateInfoKHR *pCreateInfo,
  const VkAllocationCallbacks* pAllocator,
  bool should_export,
- bool linear,
+ bool different_gpu,
  struct wsi_image_base *wsi_image)
 {
VkResult result = VK_SUCCESS;
@@ -170,7 +170,7 @@ radv_wsi_image_create(VkDevice device_h,
   .arrayLayers = 1,
   .samples = 1,
   /* FIXME: Need a way to use 
X tiling to allow scanout */
-  .tiling = linear ? 
VK_IMAGE_TILING_LINEAR : VK_IMAGE_TILING_OPTIMAL,
+  .tiling = different_gpu ? 
VK_IMAGE_TILING_LINEAR : VK_IMAGE_TILING_OPTIMAL,
   .usage = 
VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
   .flags = 0,
   },
@@ -196,7 +196,7 @@ radv_wsi_image_create(VkDevice device_h,
 .sType = 
VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO,
 .pNext = _alloc,
 .allocationSize = image->size,
-.memoryTypeIndex = linear ? 1 : 0,
+.memoryTypeIndex = different_gpu ? 
1 : 0,
 },
 NULL /* XXX: pAllocator */,
 RADV_MEM_IMPLICIT_SYNC,
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 929905052d..740bbff9d3 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -173,7 +173,7 @@ anv_wsi_image_create(VkDevice device_h,
  const VkSwapchainCreateInfoKHR *pCreateInfo,
  const VkAllocationCallbacks* pAllocator,
  bool should_export,
- bool linear,
+ bool different_gpu,
  struct wsi_image_base *wsi_image)
 {
struct anv_device *device = anv_device_from_handle(device_h);
diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
index c8a2df08f1..d808a4cfdc 100644
--- a/src/vulkan/wsi/wsi_common.h
+++ b/src/vulkan/wsi/wsi_common.h
@@ -48,7 +48,7 @@ struct wsi_image_fns {
 const VkSwapchainCreateInfoKHR *pCreateInfo,
 const VkAllocationCallbacks *pAllocator,
 bool should_export,
-bool linear,
+bool different_gpu,
 struct wsi_image_base *image_p);
void (*free_wsi_image)(VkDevice device,
   const VkAllocationCallbacks *pAllocator,
-- 
2.13.0

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[Mesa-dev] [RFC v5 17/19] vulkan/wsi/wayland: Add support for zwp_dmabuf

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

zwp_linux_dmabuf_v1 lets us use multi-planar images and buffer
modifiers.

Signed-off-by: Daniel Stone 
---
 src/vulkan/Makefile.am  |  10 +++
 src/vulkan/Makefile.sources |   4 +-
 src/vulkan/wsi/wsi_common_wayland.c | 157 +++-
 3 files changed, 151 insertions(+), 20 deletions(-)

diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am
index 8766952eaf..d7e1db3c29 100644
--- a/src/vulkan/Makefile.am
+++ b/src/vulkan/Makefile.am
@@ -67,6 +67,16 @@ wsi/wayland-drm-client-protocol.h : $(WL_DRM_XML)
$(MKDIR_GEN)
$(AM_V_GEN)$(WAYLAND_SCANNER) client-header < $< > $@
 
+WL_DMABUF_XML = 
$(WAYLAND_PROTOCOLS_DATADIR)/unstable/linux-dmabuf/linux-dmabuf-unstable-v1.xml
+
+wsi/linux-dmabuf-unstable-v1-protocol.c : $(WL_DMABUF_XML)
+   $(MKDIR_GEN)
+   $(AM_V_GEN)$(WAYLAND_SCANNER) code < $< > $@
+
+wsi/linux-dmabuf-unstable-v1-client-protocol.h : $(WL_DMABUF_XML)
+   $(MKDIR_GEN)
+   $(AM_V_GEN)$(WAYLAND_SCANNER) client-header < $< > $@
+
 if HAVE_PLATFORM_WAYLAND
 AM_CPPFLAGS += \
-I$(top_builddir)/src/vulkan/wsi \
diff --git a/src/vulkan/Makefile.sources b/src/vulkan/Makefile.sources
index 2cf7218e92..95685caab7 100644
--- a/src/vulkan/Makefile.sources
+++ b/src/vulkan/Makefile.sources
@@ -9,7 +9,9 @@ VULKAN_WSI_WAYLAND_FILES := \
 
 VULKAN_WSI_WAYLAND_GENERATED_FILES := \
wsi/wayland-drm-protocol.c \
-   wsi/wayland-drm-client-protocol.h
+   wsi/wayland-drm-client-protocol.h \
+   wsi/linux-dmabuf-unstable-v1-protocol.c \
+   wsi/linux-dmabuf-unstable-v1-client-protocol.h
 
 VULKAN_WSI_X11_FILES := \
wsi/wsi_common_x11.c \
diff --git a/src/vulkan/wsi/wsi_common_wayland.c 
b/src/vulkan/wsi/wsi_common_wayland.c
index a76e29d26e..69dbbaeb1d 100644
--- a/src/vulkan/wsi/wsi_common_wayland.c
+++ b/src/vulkan/wsi/wsi_common_wayland.c
@@ -31,9 +31,12 @@
 #include 
 #include 
 
+#include 
+
 #include "vk_util.h"
 #include "wsi_common_wayland.h"
 #include "wayland-drm-client-protocol.h"
+#include "linux-dmabuf-unstable-v1-client-protocol.h"
 
 #include 
 #include 
@@ -52,11 +55,17 @@ struct wsi_wl_display {
struct wl_display *  wl_display_wrapper;
struct wl_event_queue *  queue;
struct wl_drm *  drm;
+   struct zwp_linux_dmabuf_v1 * dmabuf;
 
struct wsi_wayland *wsi_wl;
/* Vector of VkFormats supported */
struct u_vectorformats;
 
+   struct {
+  struct u_vector   argb;
+  struct u_vector   xrgb;
+   } modifiers;
+
uint32_t capabilities;
 
/* Only used for displays created by wsi_wl_display_create */
@@ -223,6 +232,49 @@ static const struct wl_drm_listener drm_listener = {
 };
 
 static void
+dmabuf_handle_format(void *data, struct zwp_linux_dmabuf_v1 *dmabuf,
+ uint32_t format)
+{
+   /* Formats are implicitly advertised by the modifier event, so we ignore
+* them here. */
+}
+
+static void
+dmabuf_handle_modifier(void *data, struct zwp_linux_dmabuf_v1 *dmabuf,
+   uint32_t format, uint32_t modifier_hi,
+   uint32_t modifier_lo)
+{
+   struct wsi_wl_display *display = data;
+   uint64_t *mod = NULL;
+
+   if (modifier_hi == (DRM_FORMAT_MOD_INVALID >> 32) &&
+   modifier_lo == (DRM_FORMAT_MOD_INVALID & 0x))
+  return;
+
+   switch (format) {
+   case WL_DRM_FORMAT_ARGB:
+  mod = u_vector_add(>modifiers.argb);
+  break;
+   case WL_DRM_FORMAT_XRGB:
+  mod = u_vector_add(>modifiers.xrgb);
+  break;
+   default:
+  break;
+   }
+
+   if (!mod)
+  return;
+
+   *mod = (uint64_t) modifier_hi << 32;
+   *mod |= (uint64_t) (modifier_lo & 0x);
+}
+
+static const struct zwp_linux_dmabuf_v1_listener dmabuf_listener = {
+   dmabuf_handle_format,
+   dmabuf_handle_modifier,
+};
+
+static void
 registry_handle_global(void *data, struct wl_registry *registry,
uint32_t name, const char *interface, uint32_t version)
 {
@@ -236,6 +288,11 @@ registry_handle_global(void *data, struct wl_registry 
*registry,
 
   if (display->drm)
  wl_drm_add_listener(display->drm, _listener, display);
+   } else if (strcmp(interface, "zwp_linux_dmabuf_v1") == 0 && version >= 3) {
+  display->dmabuf =
+ wl_registry_bind(registry, name, _linux_dmabuf_v1_interface, 3);
+  zwp_linux_dmabuf_v1_add_listener(display->dmabuf, _listener,
+   display);
}
 }
 
@@ -276,7 +333,9 @@ wsi_wl_display_init(struct wsi_wayland *wsi_wl,
display->wl_display = wl_display;
 
if (get_format_list) {
-  if (!u_vector_init(>formats, sizeof(VkFormat), 8)) {
+  if (!u_vector_init(>formats, sizeof(VkFormat), 8) ||
+ 

[Mesa-dev] [RFC v5 12/19] intel/isl: Add ISL tiling -> modifier conversion

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

Given a tiling mode and an aux usage, return the DRM modifier.

Signed-off-by: Daniel Stone 
---
 src/intel/isl/isl.h |  6 +-
 src/intel/isl/isl_drm.c | 17 +
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index e3acb0ec28..b255f15a5d 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1551,7 +1551,7 @@ isl_tiling_is_std_y(enum isl_tiling tiling)
 uint32_t
 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
 
-enum isl_tiling 
+enum isl_tiling
 isl_tiling_from_i915_tiling(uint32_t tiling);
 
 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
@@ -1583,6 +1583,10 @@ isl_drm_modifier_get_default_aux_state(uint64_t modifier)
ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
 }
 
+uint64_t ATTRIBUTE_CONST
+isl_drm_modifier_from_tiling(enum isl_tiling tiling,
+ enum isl_aux_usage aux_usage);
+
 struct isl_extent2d ATTRIBUTE_CONST
 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
 
diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index eb3c6f5913..a40142c6ec 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -30,6 +30,10 @@
 #include "isl.h"
 #include "common/gen_device_info.h"
 
+#ifndef DRM_FORMAT_MOD_INVALID
+#define DRM_FORMAT_MOD_INVALID ((1ULL << 56) - 1)
+#endif
+
 uint32_t
 isl_tiling_to_i915_tiling(enum isl_tiling tiling)
 {
@@ -106,3 +110,16 @@ isl_drm_modifier_get_info(uint64_t modifier)
 
return NULL;
 }
+
+uint64_t
+isl_drm_modifier_from_tiling(enum isl_tiling tiling,
+ enum isl_aux_usage aux_usage)
+{
+   for (unsigned i = 0; i < ARRAY_SIZE(modifier_info); i++) {
+  if (modifier_info[i].tiling == tiling &&
+  modifier_info[i].aux_usage == aux_usage)
+ return modifier_info[i].modifier;
+   }
+
+   return DRM_FORMAT_MOD_INVALID;
+}
-- 
2.13.0

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[Mesa-dev] [RFC v5 10/19] vulkan/wsi: Rename needs_linear_copy to should_export

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

The only use for this boolean was to decide whether or not it should
export a dmabuf FD. Simplify things a bit by giving that directly.

Signed-off-by: Daniel Stone 
---
 src/amd/vulkan/radv_wsi.c   |  6 --
 src/intel/vulkan/anv_wsi.c  | 21 +
 src/vulkan/wsi/wsi_common.h |  2 +-
 src/vulkan/wsi/wsi_common_wayland.c |  2 +-
 src/vulkan/wsi/wsi_common_x11.c |  4 ++--
 5 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 2562d38e23..b24cf28d42 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -142,7 +142,7 @@ static VkResult
 radv_wsi_image_create(VkDevice device_h,
  const VkSwapchainCreateInfoKHR *pCreateInfo,
  const VkAllocationCallbacks* pAllocator,
- bool needs_linear_copy,
+ bool should_export,
  bool linear,
  struct wsi_image_base *wsi_image)
 {
@@ -209,11 +209,13 @@ radv_wsi_image_create(VkDevice device_h,
 * return the fd for the image in the no copy mode,
 * or the fd for the linear image if a copy is required.
 */
-   if (!needs_linear_copy || (needs_linear_copy && linear)) {
+   if (should_export) {
RADV_FROM_HANDLE(radv_device_memory, memory, memory_h);
if (!radv_get_memory_fd(device, memory, ))
goto fail_alloc_memory;
wsi_image->fd = fd;
+   } else {
+   wsi_image->fd = -1;
}
 
surface = >surface;
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index d520d8e3f4..916c62cad9 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -172,7 +172,7 @@ static VkResult
 anv_wsi_image_create(VkDevice device_h,
  const VkSwapchainCreateInfoKHR *pCreateInfo,
  const VkAllocationCallbacks* pAllocator,
- bool different_gpu,
+ bool should_export,
  bool linear,
  struct wsi_image_base *wsi_image)
 {
@@ -250,13 +250,18 @@ anv_wsi_image_create(VkDevice device_h,
   goto fail_alloc_memory;
}
 
-   int fd = anv_gem_handle_to_fd(device, memory->bo->gem_handle);
-   if (fd == -1) {
-  /* FINISHME: Choose a better error. */
-  result = vk_errorf(device->instance, device,
- VK_ERROR_OUT_OF_DEVICE_MEMORY,
- "handle_to_fd failed: %m");
-  goto fail_alloc_memory;
+   int fd;
+   if (should_export) {
+  fd = anv_gem_handle_to_fd(device, memory->bo->gem_handle);
+  if (fd == -1) {
+ /* FINISHME: Choose a better error. */
+ result = vk_errorf(device->instance, device,
+VK_ERROR_OUT_OF_DEVICE_MEMORY,
+"handle_to_fd failed: %m");
+ goto fail_alloc_memory;
+  }
+   } else {
+  fd = -1;
}
 
wsi_image->image = image_h;
diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
index 2a9092479d..1103703b0e 100644
--- a/src/vulkan/wsi/wsi_common.h
+++ b/src/vulkan/wsi/wsi_common.h
@@ -44,7 +44,7 @@ struct wsi_image_fns {
VkResult (*create_wsi_image)(VkDevice device_h,
 const VkSwapchainCreateInfoKHR *pCreateInfo,
 const VkAllocationCallbacks *pAllocator,
-bool needs_linear_copy,
+bool should_export,
 bool linear,
 struct wsi_image_base *image_p);
void (*free_wsi_image)(VkDevice device,
diff --git a/src/vulkan/wsi/wsi_common_wayland.c 
b/src/vulkan/wsi/wsi_common_wayland.c
index 495e7068b4..36cc4d0821 100644
--- a/src/vulkan/wsi/wsi_common_wayland.c
+++ b/src/vulkan/wsi/wsi_common_wayland.c
@@ -730,7 +730,7 @@ wsi_wl_image_init(struct wsi_wl_swapchain *chain,
result = chain->base.image_fns->create_wsi_image(vk_device,
 pCreateInfo,
 pAllocator,
-false,
+true,
 false,
 >base);
if (result != VK_SUCCESS)
diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_x11.c
index 94578b438b..78fd406aa1 100644
--- a/src/vulkan/wsi/wsi_common_x11.c
+++ b/src/vulkan/wsi/wsi_common_x11.c
@@ -963,7 +963,7 @@ x11_image_init(VkDevice device_h, struct x11_swapchain 
*chain,
result = chain->base.image_fns->create_wsi_image(device_h,
 pCreateInfo,
  

[Mesa-dev] [RFC v5 13/19] intel/isl: Add field for suboptimal tiling flags

[Louis-Francis Ratté-Boulianne]

The caller might want to discriminate between two possible
sets of tiling flags. For example, some tiling modes might
allow direct scanout, and so should be preferred even if
GPU operations are a little less performant.

Signed-off-by: Louis-Francis Ratté-Boulianne 
---
 src/intel/isl/isl.c | 33 -
 src/intel/isl/isl.h |  3 +++
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 59f512fc05..a5d9d842ba 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -304,6 +304,7 @@ isl_surf_choose_tiling(const struct isl_device *dev,
enum isl_tiling *tiling)
 {
isl_tiling_flags_t tiling_flags = info->tiling_flags;
+   isl_tiling_flags_t suboptimal_tiling_flags = info->suboptimal_tiling_flags;
 
/* HiZ surfaces always use the HiZ tiling */
if (info->usage & ISL_SURF_USAGE_HIZ_BIT) {
@@ -323,13 +324,15 @@ isl_surf_choose_tiling(const struct isl_device *dev,
 
if (ISL_DEV_GEN(dev) >= 6) {
   isl_gen6_filter_tiling(dev, info, _flags);
+  isl_gen6_filter_tiling(dev, info, _tiling_flags);
} else {
   isl_gen4_filter_tiling(dev, info, _flags);
+  isl_gen4_filter_tiling(dev, info, _tiling_flags);
}
 
-   #define CHOOSE(__tiling) \
+   #define CHOOSE(__flags, __tiling) \
   do { \
- if (tiling_flags & (1u << (__tiling))) { \
+ if (__flags & (1u << (__tiling))) { \
 *tiling = (__tiling); \
 return true; \
   } \
@@ -345,15 +348,27 @@ isl_surf_choose_tiling(const struct isl_device *dev,
* memory locality due to the swizzling and alignment restrictions
* required in tiled surfaces.
*/
-  CHOOSE(ISL_TILING_LINEAR);
+  CHOOSE((tiling_flags | suboptimal_tiling_flags),
+ ISL_TILING_LINEAR);
}
 
-   CHOOSE(ISL_TILING_Ys);
-   CHOOSE(ISL_TILING_Yf);
-   CHOOSE(ISL_TILING_Y0);
-   CHOOSE(ISL_TILING_X);
-   CHOOSE(ISL_TILING_W);
-   CHOOSE(ISL_TILING_LINEAR);
+   CHOOSE(tiling_flags, ISL_TILING_Ys);
+   CHOOSE(tiling_flags, ISL_TILING_Yf);
+   CHOOSE(tiling_flags, ISL_TILING_Y0);
+   CHOOSE(tiling_flags, ISL_TILING_X);
+   CHOOSE(tiling_flags, ISL_TILING_W);
+   CHOOSE(tiling_flags, ISL_TILING_LINEAR);
+
+   /* Let's try the suboptimal tiling modes if none of the preferred
+* ones were available. */
+   if (suboptimal_tiling_flags != 0) {
+  CHOOSE(suboptimal_tiling_flags, ISL_TILING_Ys);
+  CHOOSE(suboptimal_tiling_flags, ISL_TILING_Yf);
+  CHOOSE(suboptimal_tiling_flags, ISL_TILING_Y0);
+  CHOOSE(suboptimal_tiling_flags, ISL_TILING_X);
+  CHOOSE(suboptimal_tiling_flags, ISL_TILING_W);
+  CHOOSE(suboptimal_tiling_flags, ISL_TILING_LINEAR);
+   }
 
#undef CHOOSE
 
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index b255f15a5d..b11daf13d8 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1113,6 +1113,9 @@ struct isl_surf_init_info {
 
/** Flags that alter how ISL selects isl_surf::tiling.  */
isl_tiling_flags_t tiling_flags;
+
+   /** Flags that could also be used for isl_surf::tiling but are suboptimal. 
*/
+   isl_tiling_flags_t suboptimal_tiling_flags;
 };
 
 struct isl_surf {
-- 
2.13.0

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[Mesa-dev] [RFC v5 07/19] RFC: egl/x11: Support DRI3 v1.1

[Louis-Francis Ratté-Boulianne]

Add support for DRI3 v1.1, which allows pixmaps to be backed by
multi-planar buffers, or those with format modifiers. This is both
for allocating render buffers, as well as EGLImage imports from a
native pixmap (EGL_NATIVE_PIXMAP_KHR).

Signed-off-by: Louis-Francis Ratté-Boulianne 
Reviewed-by: Eric Engestrom 
Reviewed-by: Emil Velikov 
Reviewed-by: Daniel Stone 
---
 src/egl/drivers/dri2/egl_dri2.c  |   7 +
 src/egl/drivers/dri2/egl_dri2.h  |   3 +
 src/egl/drivers/dri2/platform_x11_dri3.c |  99 ++--
 src/glx/dri3_glx.c   |  10 +-
 src/loader/loader_dri3_helper.c  | 266 ++-
 src/loader/loader_dri3_helper.h  |  17 +-
 6 files changed, 350 insertions(+), 52 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 8a9749d207..b213bc76d4 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -875,6 +875,13 @@ dri2_setup_extensions(_EGLDisplay *disp)
if (!dri2_bind_extensions(dri2_dpy, mandatory_core_extensions, extensions, 
false))
   return EGL_FALSE;
 
+#ifdef HAVE_DRI3
+   dri2_dpy->multibuffers_available =
+  (dri2_dpy->dri3_major_version > 1 || (dri2_dpy->dri3_major_version == 1 
&&
+dri2_dpy->dri3_minor_version >= 
1)) &&
+  (dri2_dpy->image && dri2_dpy->image->base.version >= 15);
+#endif
+
dri2_bind_extensions(dri2_dpy, optional_core_extensions, extensions, true);
return EGL_TRUE;
 }
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index cd2487ab22..4a2581e52d 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -197,6 +197,9 @@ struct dri2_egl_display
xcb_screen_t *screen;
bool swap_available;
 #ifdef HAVE_DRI3
+   bool multibuffers_available;
+   int  dri3_major_version;
+   int  dri3_minor_version;
struct loader_dri3_extensions loader_dri3_ext;
 #endif
 #endif
diff --git a/src/egl/drivers/dri2/platform_x11_dri3.c 
b/src/egl/drivers/dri2/platform_x11_dri3.c
index eadd37141e..aa20fdb4b4 100644
--- a/src/egl/drivers/dri2/platform_x11_dri3.c
+++ b/src/egl/drivers/dri2/platform_x11_dri3.c
@@ -39,6 +39,21 @@
 #include "loader.h"
 #include "loader_dri3_helper.h"
 
+static uint32_t
+dri3_format_for_depth(uint32_t depth)
+{
+   switch (depth) {
+   case 16:
+  return __DRI_IMAGE_FORMAT_RGB565;
+   case 24:
+  return __DRI_IMAGE_FORMAT_XRGB;
+   case 32:
+  return __DRI_IMAGE_FORMAT_ARGB;
+   default:
+  return __DRI_IMAGE_FORMAT_NONE;
+   }
+}
+
 static struct dri3_egl_surface *
 loader_drawable_to_egl_surface(struct loader_dri3_drawable *draw) {
size_t offset = offsetof(struct dri3_egl_surface, loader_drawable);
@@ -156,7 +171,9 @@ dri3_create_surface(_EGLDriver *drv, _EGLDisplay *disp, 
EGLint type,
 
if (loader_dri3_drawable_init(dri2_dpy->conn, drawable,
  dri2_dpy->dri_screen,
- dri2_dpy->is_different_gpu, dri_config,
+ dri2_dpy->is_different_gpu,
+ dri2_dpy->multibuffers_available,
+ dri_config,
  _dpy->loader_dri3_ext,
  _dri3_vtable,
  _surf->loader_drawable)) {
@@ -262,17 +279,8 @@ dri3_create_image_khr_pixmap(_EGLDisplay *disp, 
_EGLContext *ctx,
   return NULL;
}
 
-   switch (bp_reply->depth) {
-   case 16:
-  format = __DRI_IMAGE_FORMAT_RGB565;
-  break;
-   case 24:
-  format = __DRI_IMAGE_FORMAT_XRGB;
-  break;
-   case 32:
-  format = __DRI_IMAGE_FORMAT_ARGB;
-  break;
-   default:
+   format = dri3_format_for_depth(bp_reply->depth);
+   if (format == __DRI_IMAGE_FORMAT_NONE) {
   _eglError(EGL_BAD_PARAMETER,
 "dri3_create_image_khr: unsupported pixmap depth");
   free(bp_reply);
@@ -299,13 +307,77 @@ dri3_create_image_khr_pixmap(_EGLDisplay *disp, 
_EGLContext *ctx,
return _img->base;
 }
 
+#if XCB_DRI3_MAJOR_VERSION > 1 || (XCB_DRI3_MAJOR_VERSION == 1 && 
XCB_DRI3_MINOR_VERSION >= 1)
+static _EGLImage *
+dri3_create_image_khr_pixmap_from_buffers(_EGLDisplay *disp, _EGLContext *ctx,
+  EGLClientBuffer buffer,
+  const EGLint *attr_list)
+{
+   struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
+   struct dri2_egl_image *dri2_img;
+   xcb_dri3_buffers_from_pixmap_cookie_t bp_cookie;
+   xcb_dri3_buffers_from_pixmap_reply_t  *bp_reply;
+   xcb_drawable_t drawable;
+   unsigned int format;
+
+   drawable = (xcb_drawable_t) (uintptr_t) buffer;
+   bp_cookie = 

[Mesa-dev] [RFC v5 14/19] vulkan/wsi: Add drm_modifier member to wsi_image

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

Not yet used anywhere.

Signed-off-by: Daniel Stone 
---
 src/amd/vulkan/Makefile.am  | 1 +
 src/amd/vulkan/radv_wsi.c   | 2 ++
 src/intel/vulkan/anv_wsi.c  | 9 +
 src/vulkan/wsi/wsi_common.h | 2 ++
 4 files changed, 14 insertions(+)

diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index 6b352aebf9..fb32bb83e0 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -31,6 +31,7 @@ lib_LTLIBRARIES = libvulkan_radeon.la
 
 AM_CPPFLAGS = \
-I$(top_srcdir)/include \
+   -I$(top_srcdir)/include/drm-uapi \
-I$(top_builddir)/src \
-I$(top_srcdir)/src \
-I$(top_srcdir)/src/vulkan/wsi \
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index b535dc22f4..66082c4ae0 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -28,6 +28,7 @@
 #include "wsi_common.h"
 #include "vk_util.h"
 #include "util/macros.h"
+#include 
 
 MAYBE_UNUSED static const struct wsi_callbacks wsi_cbs = {
.get_phys_device_format_properties = radv_GetPhysicalDeviceFormatProperties,
@@ -223,6 +224,7 @@ radv_wsi_image_create(VkDevice device_h,
wsi_image->image = image_h;
wsi_image->memory = memory_h;
wsi_image->num_planes = 1;
+   wsi_image->drm_modifier = DRM_FORMAT_MOD_INVALID;
wsi_image->sizes[0] = image->size;
wsi_image->offsets[0] = image->offset;
if (device->physical_device->rad_info.chip_class >= GFX9)
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index ae40f1f2f4..929905052d 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -266,6 +266,15 @@ anv_wsi_image_create(VkDevice device_h,
 
wsi_image->image = image_h;
wsi_image->memory = memory_h;
+
+   /* We don't yet allow sharing of aux planes with the winsys. Doing so
+* would require a separate external_aux_usage member in the anv_image,
+* to disambiguate between the case where we allocate an aux usage for our
+* own internal use, as opposed to when the winsys can use it. Else we may
+* incorrectly pass CCS surfaces to a non-CCS-aware winsys/kernel.
+*/
+   wsi_image->drm_modifier =
+  isl_drm_modifier_from_tiling(surface->isl.tiling, ISL_AUX_USAGE_NONE);
wsi_image->num_planes = 1;
wsi_image->fds[0] = fd;
wsi_image->sizes[0] = image->size;
diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
index b6c5a438b1..c8a2df08f1 100644
--- a/src/vulkan/wsi/wsi_common.h
+++ b/src/vulkan/wsi/wsi_common.h
@@ -33,6 +33,8 @@
 struct wsi_image_base {
VkImage image;
VkDeviceMemory memory;
+
+   uint64_t drm_modifier;
int num_planes;
uint32_t sizes[4];
uint32_t offsets[4];
-- 
2.13.0

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[Mesa-dev] [RFC v5 11/19] vulkan/wsi: Add multiple planes to wsi_image_base

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

Not currently used.

Signed-off-by: Daniel Stone 
---
 src/amd/vulkan/radv_wsi.c   | 13 +++--
 src/intel/vulkan/anv_wsi.c  |  9 +
 src/vulkan/wsi/wsi_common.h |  9 +
 src/vulkan/wsi/wsi_common_wayland.c | 11 +++
 src/vulkan/wsi/wsi_common_x11.c | 12 
 5 files changed, 32 insertions(+), 22 deletions(-)

diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index b24cf28d42..b535dc22f4 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -213,22 +213,23 @@ radv_wsi_image_create(VkDevice device_h,
RADV_FROM_HANDLE(radv_device_memory, memory, memory_h);
if (!radv_get_memory_fd(device, memory, ))
goto fail_alloc_memory;
-   wsi_image->fd = fd;
+   wsi_image->fds[0] = fd;
} else {
-   wsi_image->fd = -1;
+   wsi_image->fds[0] = -1;
}
 
surface = >surface;
 
wsi_image->image = image_h;
wsi_image->memory = memory_h;
-   wsi_image->size = image->size;
-   wsi_image->offset = image->offset;
+   wsi_image->num_planes = 1;
+   wsi_image->sizes[0] = image->size;
+   wsi_image->offsets[0] = image->offset;
if (device->physical_device->rad_info.chip_class >= GFX9)
-   wsi_image->row_pitch =
+   wsi_image->row_pitches[0] =
surface->u.gfx9.surf_pitch * surface->bpe;
else
-   wsi_image->row_pitch =
+   wsi_image->row_pitches[0] =
surface->u.legacy.level[0].nblk_x * surface->bpe;
 
return VK_SUCCESS;
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 916c62cad9..ae40f1f2f4 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -266,10 +266,11 @@ anv_wsi_image_create(VkDevice device_h,
 
wsi_image->image = image_h;
wsi_image->memory = memory_h;
-   wsi_image->fd = fd;
-   wsi_image->size = image->size;
-   wsi_image->offset = 0;
-   wsi_image->row_pitch = surface->isl.row_pitch;
+   wsi_image->num_planes = 1;
+   wsi_image->fds[0] = fd;
+   wsi_image->sizes[0] = image->size;
+   wsi_image->offsets[0] = 0;
+   wsi_image->row_pitches[0] = surface->isl.row_pitch;
return VK_SUCCESS;
 fail_alloc_memory:
anv_FreeMemory(device_h, memory_h, pAllocator);
diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
index 1103703b0e..b6c5a438b1 100644
--- a/src/vulkan/wsi/wsi_common.h
+++ b/src/vulkan/wsi/wsi_common.h
@@ -33,10 +33,11 @@
 struct wsi_image_base {
VkImage image;
VkDeviceMemory memory;
-   uint32_t size;
-   uint32_t offset;
-   uint32_t row_pitch;
-   int fd;
+   int num_planes;
+   uint32_t sizes[4];
+   uint32_t offsets[4];
+   uint32_t row_pitches[4];
+   int fds[4];
 };
 
 struct wsi_device;
diff --git a/src/vulkan/wsi/wsi_common_wayland.c 
b/src/vulkan/wsi/wsi_common_wayland.c
index 36cc4d0821..a76e29d26e 100644
--- a/src/vulkan/wsi/wsi_common_wayland.c
+++ b/src/vulkan/wsi/wsi_common_wayland.c
@@ -736,15 +736,18 @@ wsi_wl_image_init(struct wsi_wl_swapchain *chain,
if (result != VK_SUCCESS)
   return result;
 
+   /* Without passing modifiers, we can't have multi-plane RGB images. */
+   assert(image->base.num_planes == 1);
+
image->buffer = wl_drm_create_prime_buffer(chain->drm_wrapper,
-  image->base.fd, /* name */
+  image->base.fds[0], /* name */
   chain->extent.width,
   chain->extent.height,
   chain->drm_format,
-  image->base.offset,
-  image->base.row_pitch,
+  image->base.offsets[0],
+  image->base.row_pitches[0],
   0, 0, 0, 0 /* unused */);
-   close(image->base.fd);
+   close(image->base.fds[0]);
 
if (!image->buffer)
   goto fail_image;
diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_x11.c
index 78fd406aa1..e48d746305 100644
--- a/src/vulkan/wsi/wsi_common_x11.c
+++ b/src/vulkan/wsi/wsi_common_x11.c
@@ -988,18 +988,22 @@ x11_image_init(VkDevice device_h, struct x11_swapchain 
*chain,
 
struct wsi_image_base *image_ws =
   chain->base.needs_linear_copy ? >linear_base : >base;
+
+   /* Without passing modifiers, we can't have multi-plane RGB images. */
+   assert(image_ws->num_planes == 1);
+
cookie =
   xcb_dri3_pixmap_from_buffer_checked(chain->conn,
   image->pixmap,
   chain->window,
- 

[Mesa-dev] [RFC v5 08/19] egl/x11: Re-allocate buffers if format is suboptimal

[Louis-Francis Ratté-Boulianne]

If PresentCompleteNotify event says the pixmap was presented
with mode PresentCompleteModeSuboptimalCopy, it means the pixmap
could possibly have been flipped instead if allocated with a
different format/modifier.

Signed-off-by: Louis-Francis Ratté-Boulianne 
---
 src/egl/drivers/dri2/egl_dri2.c  |  2 ++
 src/egl/drivers/dri2/egl_dri2.h  |  2 ++
 src/egl/drivers/dri2/platform_x11_dri3.c |  3 +++
 src/loader/loader_dri3_helper.c  | 27 ++-
 src/loader/loader_dri3_helper.h  |  2 ++
 5 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index b213bc76d4..611bfa5aed 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -879,6 +879,8 @@ dri2_setup_extensions(_EGLDisplay *disp)
dri2_dpy->multibuffers_available =
   (dri2_dpy->dri3_major_version > 1 || (dri2_dpy->dri3_major_version == 1 
&&
 dri2_dpy->dri3_minor_version >= 
1)) &&
+  (dri2_dpy->present_major_version > 1 || (dri2_dpy->present_major_version 
== 1 &&
+   dri2_dpy->present_minor_version 
>= 1)) &&
   (dri2_dpy->image && dri2_dpy->image->base.version >= 15);
 #endif
 
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index 4a2581e52d..35b9777edb 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -200,6 +200,8 @@ struct dri2_egl_display
bool multibuffers_available;
int  dri3_major_version;
int  dri3_minor_version;
+   int  present_major_version;
+   int  present_minor_version;
struct loader_dri3_extensions loader_dri3_ext;
 #endif
 #endif
diff --git a/src/egl/drivers/dri2/platform_x11_dri3.c 
b/src/egl/drivers/dri2/platform_x11_dri3.c
index aa20fdb4b4..b61e50cb21 100644
--- a/src/egl/drivers/dri2/platform_x11_dri3.c
+++ b/src/egl/drivers/dri2/platform_x11_dri3.c
@@ -553,6 +553,9 @@ dri3_x11_connect(struct dri2_egl_display *dri2_dpy)
   free(error);
   return EGL_FALSE;
}
+
+   dri2_dpy->present_major_version = present_query->major_version;
+   dri2_dpy->present_minor_version = present_query->minor_version;
free(present_query);
 
dri2_dpy->fd = loader_dri3_open(dri2_dpy->conn, dri2_dpy->screen->root, 0);
diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index 02e00d82c5..d5a7621423 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -372,10 +372,22 @@ dri3_handle_present_event(struct loader_dri3_drawable 
*draw,
  switch (ce->mode) {
  case XCB_PRESENT_COMPLETE_MODE_FLIP:
 draw->flipping = true;
+for (int b = 0; b < sizeof(draw->buffers) / 
sizeof(draw->buffers[0]); b++) {
+   if (draw->buffers[b])
+  draw->buffers[b]->realloc_suboptimal = true;
+}
 break;
  case XCB_PRESENT_COMPLETE_MODE_COPY:
 draw->flipping = false;
 break;
+#if XCB_PRESENT_MAJOR_VERSION > 1 || (XCB_PRESENT_MAJOR_VERSION == 1 && 
XCB_PRESENT_MINOR_VERSION >= 1)
+ case XCB_PRESENT_COMPLETE_MODE_SUBOPTIMAL_COPY:
+draw->flipping = false;
+for (int b = 0; b < sizeof(draw->buffers) / 
sizeof(draw->buffers[0]); b++) {
+   if (draw->buffers[b])
+  draw->buffers[b]->suboptimal = true;
+}
+#endif
  }
  dri3_update_num_back(draw);
 
@@ -857,6 +869,11 @@ loader_dri3_swap_buffers_msc(struct loader_dri3_drawable 
*draw,
   if (!loader_dri3_have_image_blit(draw) && draw->cur_blit_source != -1)
  options |= XCB_PRESENT_OPTION_COPY;
 
+#if XCB_PRESENT_MAJOR_VERSION > 1 || (XCB_PRESENT_MAJOR_VERSION == 1 && 
XCB_PRESENT_MINOR_VERSION >= 1)
+  if (draw->multiplanes_available)
+ options  |= XCB_PRESENT_OPTION_SUBOPTIMAL;
+#endif
+
   back->busy = 1;
   back->last_swap = draw->send_sbc;
   xcb_present_pixmap(draw->conn,
@@ -1217,6 +1234,8 @@ dri3_alloc_render_buffer(struct loader_dri3_drawable 
*draw, unsigned int format,
buffer->shm_fence = shm_fence;
buffer->width = width;
buffer->height = height;
+   buffer->suboptimal = false;
+   buffer->realloc_suboptimal = true;
 
/* Mark the buffer as idle
 */
@@ -1550,7 +1569,8 @@ dri3_get_buffer(__DRIdrawable *driDrawable,
 * old one is the wrong size
 */
if (!buffer || buffer->width != draw->width ||
-   buffer->height != draw->height) {
+   buffer->height != draw->height ||
+   (buffer->suboptimal && buffer->realloc_suboptimal)) {
   struct loader_dri3_buffer *new_buffer;
 
   /* Allocate the new buffers
@@ -1609,6 +1629,11 @@ dri3_get_buffer(__DRIdrawable *driDrawable,
   0, 0, 0);
  

[Mesa-dev] [RFC v5 06/19] dri: Add createImageWithModifiers2 to DRIimageExtension

[Louis-Francis Ratté-Boulianne]

It does the same as createImagewithModifiers but allow multiple
modifiers set to be given. The modifier used to create the image
should be selected from the first tranche if possible. If not,
then the subsequent tranches should be used.

Signed-off-by: Louis-Francis Ratté-Boulianne 
---
 include/GL/internal/dri_interface.h  | 19 +++-
 src/mesa/drivers/dri/i965/intel_screen.c | 38 
 2 files changed, 47 insertions(+), 10 deletions(-)

diff --git a/include/GL/internal/dri_interface.h 
b/include/GL/internal/dri_interface.h
index 952f557f54..715c34d178 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1186,7 +1186,7 @@ struct __DRIdri2ExtensionRec {
  * extensions.
  */
 #define __DRI_IMAGE "DRI_IMAGE"
-#define __DRI_IMAGE_VERSION 18
+#define __DRI_IMAGE_VERSION 19
 
 /**
  * These formats correspond to the similarly named MESA_FORMAT_*
@@ -1656,6 +1656,23 @@ struct __DRIimageExtensionRec {
 * \since 18
 */
void (*suppressImplicitSync)(__DRIimage *image);
+
+
+   /**
+* Like createImageWithModifiers, but can take multiple tranches/sets of
+* modifiers according to the priority for which they should be selected.
+*
+* Modifier should be selected from the first tranche, from the second
+* one if not possible, etc.
+*
+* \since 19
+*/
+   __DRIimage *(*createImageWithModifiers2)(__DRIscreen *screen,
+int width, int height, int format,
+const uint64_t **modifiers,
+const unsigned int *counts,
+const unsigned tranches_count,
+void *loaderPrivate);
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 88bc41ed64..94b3670ba3 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -637,20 +637,22 @@ static __DRIimage *
 intel_create_image_common(__DRIscreen *dri_screen,
   int width, int height, int format,
   unsigned int use,
-  const uint64_t *modifiers,
-  unsigned count,
+  const uint64_t **modifiers,
+  const unsigned *counts,
+  const unsigned tranches_count,
   void *loaderPrivate)
 {
__DRIimage *image;
struct intel_screen *screen = dri_screen->driverPrivate;
uint64_t modifier = DRM_FORMAT_MOD_INVALID;
bool ok;
+   int i;
 
/* Callers of this may specify a modifier, or a dri usage, but not both. The
 * newer modifier interface deprecates the older usage flags newer modifier
 * interface deprecates the older usage flags.
 */
-   assert(!(use && count));
+   assert(!(use && tranches_count));
 
if (use & __DRI_IMAGE_USE_CURSOR) {
   if (width != 64 || height != 64)
@@ -662,10 +664,14 @@ intel_create_image_common(__DRIscreen *dri_screen,
   modifier = DRM_FORMAT_MOD_LINEAR;
 
if (modifier == DRM_FORMAT_MOD_INVALID) {
-  if (modifiers) {
+  if (tranches_count > 0 && counts && modifiers && modifiers[0]) {
  /* User requested specific modifiers */
- modifier = select_best_modifier(>devinfo, format,
- modifiers, count);
+ for (i = 0; i < tranches_count; i++) {
+modifier = select_best_modifier(>devinfo, format,
+modifiers[i], counts[i]);
+if (modifier != DRM_FORMAT_MOD_INVALID)
+   break;
+ }
  if (modifier == DRM_FORMAT_MOD_INVALID)
 return NULL;
   } else {
@@ -751,7 +757,7 @@ intel_create_image(__DRIscreen *dri_screen,
   unsigned int use,
   void *loaderPrivate)
 {
-   return intel_create_image_common(dri_screen, width, height, format, use, 
NULL, 0,
+   return intel_create_image_common(dri_screen, width, height, format, use, 
NULL, NULL, 0,
loaderPrivate);
 }
 
@@ -763,7 +769,20 @@ intel_create_image_with_modifiers(__DRIscreen *dri_screen,
   void *loaderPrivate)
 {
return intel_create_image_common(dri_screen, width, height, format, 0,
-modifiers, count, loaderPrivate);
+, , 1, loaderPrivate);
+}
+
+static __DRIimage *
+intel_create_image_with_modifiers2(__DRIscreen *dri_screen,
+   int width, int height, int format,
+   const uint64_t **modifiers,
+   const unsigned *counts,
+   const unsigned tranches_count,
+

[Mesa-dev] [RFC v5 04/19] dri: Add suppressImplicitSync to DRIimageExtension

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

Provide a hook to inform the driver that implicit synchronization should
be suppressed.
---
 include/GL/internal/dri_interface.h | 10 +-
 src/egl/drivers/dri2/egl_dri2.c | 27 +++
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/include/GL/internal/dri_interface.h 
b/include/GL/internal/dri_interface.h
index 98402eae05..952f557f54 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1186,7 +1186,7 @@ struct __DRIdri2ExtensionRec {
  * extensions.
  */
 #define __DRI_IMAGE "DRI_IMAGE"
-#define __DRI_IMAGE_VERSION 17
+#define __DRI_IMAGE_VERSION 18
 
 /**
  * These formats correspond to the similarly named MESA_FORMAT_*
@@ -1648,6 +1648,14 @@ struct __DRIimageExtensionRec {
 int renderbuffer,
 void *loaderPrivate,
 unsigned *error);
+
+   /*
+* Suppress implicit synchronization for the image. Not mandatory but
+* cannot fail if provided.
+*
+* \since 18
+*/
+   void (*suppressImplicitSync)(__DRIimage *image);
 };
 
 
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 503450542e..8a9749d207 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -765,6 +765,10 @@ dri2_setup_screen(_EGLDisplay *disp)
  disp->Extensions.EXT_image_dma_buf_import_modifiers = EGL_TRUE;
   }
 #endif
+  if (dri2_dpy->image->base.version >= 18 &&
+  dri2_dpy->image->suppressImplicitSync) {
+ disp->Extensions.EXT_image_implicit_sync_control = EGL_TRUE;
+  }
}
 }
 
@@ -1922,6 +1926,7 @@ dri2_create_image_khr_renderbuffer(_EGLDisplay *disp, 
_EGLContext *ctx,
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct dri2_egl_context *dri2_ctx = dri2_egl_context(ctx);
GLuint renderbuffer = (GLuint) (uintptr_t) buffer;
+   _EGLImageAttribs attrs;
__DRIimage *dri_image;
 
if (renderbuffer == 0) {
@@ -1934,6 +1939,9 @@ dri2_create_image_khr_renderbuffer(_EGLDisplay *disp, 
_EGLContext *ctx,
   return EGL_NO_IMAGE_KHR;
}
 
+   if (!_eglParseImageAttribList(, disp, attr_list))
+  return NULL;
+
if (dri2_dpy->image->base.version >= 17 &&
dri2_dpy->image->createImageFromRenderbuffer2) {
   unsigned error = ~0;
@@ -1956,6 +1964,9 @@ dri2_create_image_khr_renderbuffer(_EGLDisplay *disp, 
_EGLContext *ctx,
   }
}
 
+   if (dri_image && attrs.ExplicitSync)
+  dri2_dpy->image->suppressImplicitSync(dri_image);
+
return dri2_create_image_from_dri(disp, dri_image);
 }
 
@@ -2014,6 +2025,9 @@ dri2_create_image_wayland_wl_buffer(_EGLDisplay *disp, 
_EGLContext *ctx,
   return NULL;
}
 
+   if (attrs.ExplicitSync)
+  dri2_dpy->image->suppressImplicitSync(dri_image);
+
return dri2_create_image_from_dri(disp, dri_image);
 }
 #endif
@@ -2122,6 +2136,10 @@ dri2_create_image_khr_texture(_EGLDisplay *disp, 
_EGLContext *ctx,
   free(dri2_img);
   return EGL_NO_IMAGE_KHR;
}
+
+   if (attrs.ExplicitSync)
+  dri2_dpy->image->suppressImplicitSync(dri2_img->dri_image);
+
return _img->base;
 }
 
@@ -2185,6 +2203,9 @@ dri2_create_image_mesa_drm_buffer(_EGLDisplay *disp, 
_EGLContext *ctx,
pitch,
NULL);
 
+   if (dri_image && attrs.ExplicitSync)
+  dri2_dpy->image->suppressImplicitSync(dri_image);
+
return dri2_create_image_from_dri(disp, dri_image);
 }
 
@@ -2527,6 +2548,9 @@ dri2_create_image_dma_buf(_EGLDisplay *disp, _EGLContext 
*ctx,
if (!dri_image)
   return EGL_NO_IMAGE_KHR;
 
+   if (attrs.ExplicitSync)
+  dri2_dpy->image->suppressImplicitSync(dri_image);
+
res = dri2_create_image_from_dri(disp, dri_image);
 
return res;
@@ -2600,6 +2624,9 @@ dri2_create_drm_image_mesa(_EGLDriver *drv, _EGLDisplay 
*disp,
   return EGL_NO_IMAGE_KHR;
}
 
+   if (attrs.ExplicitSync)
+  dri2_dpy->image->suppressImplicitSync(dri2_img->dri_image);
+
return _img->base;
 }
 
-- 
2.13.0

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[Mesa-dev] [RFC v5 09/19] vulkan/wsi: Add wsi_image_base structure

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

This is used to hold information about the allocated image, rather than
an ever-growing function argument list.

Signed-off-by: Daniel Stone 
---
 src/amd/vulkan/radv_wsi.c   | 31 ++
 src/intel/vulkan/anv_wsi.c  | 25 +++---
 src/vulkan/wsi/wsi_common.h | 19 --
 src/vulkan/wsi/wsi_common_wayland.c | 31 +++---
 src/vulkan/wsi/wsi_common_x11.c | 52 ++---
 5 files changed, 65 insertions(+), 93 deletions(-)

diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index b65ef27351..2562d38e23 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -144,11 +144,7 @@ radv_wsi_image_create(VkDevice device_h,
  const VkAllocationCallbacks* pAllocator,
  bool needs_linear_copy,
  bool linear,
- VkImage *image_p,
- VkDeviceMemory *memory_p,
- uint32_t *size,
- uint32_t *offset,
- uint32_t *row_pitch, int *fd_p)
+ struct wsi_image_base *wsi_image)
 {
VkResult result = VK_SUCCESS;
struct radeon_surf *surface;
@@ -217,20 +213,22 @@ radv_wsi_image_create(VkDevice device_h,
RADV_FROM_HANDLE(radv_device_memory, memory, memory_h);
if (!radv_get_memory_fd(device, memory, ))
goto fail_alloc_memory;
-   *fd_p = fd;
+   wsi_image->fd = fd;
}
 
surface = >surface;
 
-   *image_p = image_h;
-   *memory_p = memory_h;
-   *size = image->size;
-   *offset = image->offset;
-
+   wsi_image->image = image_h;
+   wsi_image->memory = memory_h;
+   wsi_image->size = image->size;
+   wsi_image->offset = image->offset;
if (device->physical_device->rad_info.chip_class >= GFX9)
-   *row_pitch = surface->u.gfx9.surf_pitch * surface->bpe;
+   wsi_image->row_pitch =
+   surface->u.gfx9.surf_pitch * surface->bpe;
else
-   *row_pitch = surface->u.legacy.level[0].nblk_x * surface->bpe;
+   wsi_image->row_pitch =
+   surface->u.legacy.level[0].nblk_x * surface->bpe;
+
return VK_SUCCESS;
  fail_alloc_memory:
radv_FreeMemory(device_h, memory_h, pAllocator);
@@ -244,12 +242,11 @@ fail_create_image:
 static void
 radv_wsi_image_free(VkDevice device,
const VkAllocationCallbacks* pAllocator,
-   VkImage image_h,
-   VkDeviceMemory memory_h)
+   struct wsi_image_base *wsi_image)
 {
-   radv_DestroyImage(device, image_h, pAllocator);
+   radv_DestroyImage(device, wsi_image->image, pAllocator);
 
-   radv_FreeMemory(device, memory_h, pAllocator);
+   radv_FreeMemory(device, wsi_image->memory, pAllocator);
 }
 
 static const struct wsi_image_fns radv_wsi_image_fns = {
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 08d83cd7f7..d520d8e3f4 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -174,11 +174,7 @@ anv_wsi_image_create(VkDevice device_h,
  const VkAllocationCallbacks* pAllocator,
  bool different_gpu,
  bool linear,
- VkImage *image_p,
- VkDeviceMemory *memory_p,
- uint32_t *size,
- uint32_t *offset,
- uint32_t *row_pitch, int *fd_p)
+ struct wsi_image_base *wsi_image)
 {
struct anv_device *device = anv_device_from_handle(device_h);
VkImage image_h;
@@ -244,7 +240,6 @@ anv_wsi_image_create(VkDevice device_h,
struct anv_surface *surface = >planes[0].surface;
assert(surface->isl.tiling == ISL_TILING_X);
 
-   *row_pitch = surface->isl.row_pitch;
int ret = anv_gem_set_tiling(device, memory->bo->gem_handle,
 surface->isl.row_pitch, I915_TILING_X);
if (ret) {
@@ -264,11 +259,12 @@ anv_wsi_image_create(VkDevice device_h,
   goto fail_alloc_memory;
}
 
-   *image_p = image_h;
-   *memory_p = memory_h;
-   *fd_p = fd;
-   *size = image->size;
-   *offset = 0;
+   wsi_image->image = image_h;
+   wsi_image->memory = memory_h;
+   wsi_image->fd = fd;
+   wsi_image->size = image->size;
+   wsi_image->offset = 0;
+   wsi_image->row_pitch = surface->isl.row_pitch;
return VK_SUCCESS;
 fail_alloc_memory:
anv_FreeMemory(device_h, memory_h, pAllocator);
@@ -281,12 +277,11 @@ fail_create_image:
 static void
 anv_wsi_image_free(VkDevice device,
const VkAllocationCallbacks* pAllocator,
-   VkImage image_h,
-   VkDeviceMemory memory_h)
+   struct wsi_image_base *wsi_image)
 {
-   

[Mesa-dev] [RFC v5 01/19] dri: fromPlanar() can return NULL as a valid result

[Louis-Francis Ratté-Boulianne]

It was assumed that fromPlanar() could return NULL to mean
that the planar image is the same as the parent DRI image.
That assumption wasn't made everywhere though.

Let's fix things and make sure that all callers understand
a NULL result

Signed-off-by: Louis-Francis Ratté-Boulianne 
---
 src/egl/drivers/dri2/platform_wayland.c | 9 +++--
 src/gbm/backends/dri/gbm_dri.c  | 1 +
 src/loader/loader_dri3_helper.c | 5 -
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index b38eb1c335..fbfab5f106 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -725,13 +725,10 @@ create_wl_buffer(struct dri2_egl_display *dri2_dpy,
  int stride, offset;
  int fd = -1;
 
- if (i == 0)
-p_image = image;
- else
-p_image = dri2_dpy->image->fromPlanar(image, i, NULL);
+ p_image = dri2_dpy->image->fromPlanar(image, i, NULL);
  if (!p_image) {
-zwp_linux_buffer_params_v1_destroy(params);
-return NULL;
+assert(plane == 0);
+p_image = image;
  }
 
  query = dri2_dpy->image->queryImage(p_image,
diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
index 0a4853bf63..e057a360e9 100644
--- a/src/gbm/backends/dri/gbm_dri.c
+++ b/src/gbm/backends/dri/gbm_dri.c
@@ -825,6 +825,7 @@ gbm_dri_bo_get_offset(struct gbm_bo *_bo, int plane)
   dri->image->queryImage(image, __DRI_IMAGE_ATTRIB_OFFSET, );
   dri->image->destroyImage(image);
} else {
+  assert(plane == 0);
   dri->image->queryImage(bo->image, __DRI_IMAGE_ATTRIB_OFFSET, );
}
 
diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index 19ab581510..372a6e943a 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -1245,7 +1245,10 @@ loader_dri3_create_image(xcb_connection_t *c,
 
ret = image->fromPlanar(image_planar, 0, loaderPrivate);
 
-   image->destroyImage(image_planar);
+   if (!ret)
+  ret = image_planar;
+   else
+  image->destroyImage(image_planar);
 
return ret;
 }
-- 
2.13.0

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[Mesa-dev] [RFC v5 05/19] i965: Implement EGL_EXT_image_implicit_sync_control

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  3 +++
 src/mesa/drivers/dri/i965/intel_screen.c | 17 +++--
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index ee91324043..254d247eab 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -120,6 +120,9 @@ struct brw_bo {
int refcount;
const char *name;
 
+#ifndef EXEC_OBJECT_ASYNC
+#define EXEC_OBJECT_ASYNC  (1<<6)
+#endif
 #ifndef EXEC_OBJECT_CAPTURE
 #define EXEC_OBJECT_CAPTURE(1<<7)
 #endif
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index b87ccab0a8..88bc41ed64 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1290,8 +1290,14 @@ intel_from_planar(__DRIimage *parent, int plane, void 
*loaderPrivate)
 return image;
 }
 
-static const __DRIimageExtension intelImageExtension = {
-.base = { __DRI_IMAGE, 16 },
+static void
+intel_image_suppress_implicit_sync(__DRIimage *image)
+{
+image->bo->kflags |= EXEC_OBJECT_ASYNC;
+}
+
+static __DRIimageExtension intelImageExtension = {
+.base = { __DRI_IMAGE, 18 },
 
 .createImageFromName= intel_create_image_from_name,
 .createImageFromRenderbuffer= intel_create_image_from_renderbuffer,
@@ -1314,6 +1320,8 @@ static const __DRIimageExtension intelImageExtension = {
 .queryDmaBufFormats = intel_query_dma_buf_formats,
 .queryDmaBufModifiers   = intel_query_dma_buf_modifiers,
 .queryDmaBufFormatModifierAttribs   = intel_query_format_modifier_attribs,
+.createImageFromRenderbuffer2   = NULL,
+.suppressImplicitSync   = NULL,
 };
 
 static uint64_t
@@ -2519,6 +2527,11 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
  (ret != -1 || errno != EINVAL);
}
 
+   if (intel_get_boolean(screen, I915_PARAM_HAS_EXEC_ASYNC)) {
+  intelImageExtension.suppressImplicitSync =
+ intel_image_suppress_implicit_sync;
+   }
+
dri_screen->extensions = !screen->has_context_reset_notification
   ? screenExtensions : intelRobustScreenExtensions;
 
-- 
2.13.0

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[Mesa-dev] [RFC v5 03/19] egl: Add EGL_EXT_image_implicit_sync_control

[Louis-Francis Ratté-Boulianne]

From: Daniel Stone 

Signed-off-by: Daniel Stone 
---
 src/egl/main/eglapi.c |  1 +
 src/egl/main/egldisplay.h |  1 +
 src/egl/main/eglimage.c   | 26 ++
 src/egl/main/eglimage.h   |  3 +++
 4 files changed, 31 insertions(+)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 215332f99c..4766236ee2 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -488,6 +488,7 @@ _eglCreateExtensionsString(_EGLDisplay *dpy)
_EGL_CHECK_EXTENSION(EXT_create_context_robustness);
_EGL_CHECK_EXTENSION(EXT_image_dma_buf_import);
_EGL_CHECK_EXTENSION(EXT_image_dma_buf_import_modifiers);
+   _EGL_CHECK_EXTENSION(EXT_image_implicit_sync_control);
_EGL_CHECK_EXTENSION(EXT_swap_buffers_with_damage);
 
_EGL_CHECK_EXTENSION(IMG_context_priority);
diff --git a/src/egl/main/egldisplay.h b/src/egl/main/egldisplay.h
index 952bfe53f0..a1f680055d 100644
--- a/src/egl/main/egldisplay.h
+++ b/src/egl/main/egldisplay.h
@@ -103,6 +103,7 @@ struct _egl_extensions
EGLBoolean EXT_create_context_robustness;
EGLBoolean EXT_image_dma_buf_import;
EGLBoolean EXT_image_dma_buf_import_modifiers;
+   EGLBoolean EXT_image_implicit_sync_control;
EGLBoolean EXT_swap_buffers_with_damage;
 
unsigned int IMG_context_priority;
diff --git a/src/egl/main/eglimage.c b/src/egl/main/eglimage.c
index 46bf0c50f0..cc55accdae 100644
--- a/src/egl/main/eglimage.c
+++ b/src/egl/main/eglimage.c
@@ -265,6 +265,28 @@ 
_eglParseEXTImageDmaBufImportModifiersAttribs(_EGLImageAttribs *attrs,
return EGL_SUCCESS;
 }
 
+static EGLint
+_eglParseEXTImageImplicitSyncControlAttribs(_EGLImageAttribs *attrs,
+_EGLDisplay *dpy,
+EGLint attr, EGLint val)
+{
+   if (!dpy->Extensions.EXT_image_implicit_sync_control)
+  return EGL_BAD_PARAMETER;
+
+   switch (attr) {
+   case EGL_IMPORT_SYNC_TYPE_EXT:
+  if (val != EGL_IMPORT_IMPLICIT_SYNC_EXT &&
+  val != EGL_IMPORT_EXPLICIT_SYNC_EXT)
+ return EGL_BAD_ATTRIBUTE;
+  attrs->ExplicitSync = (val == EGL_IMPORT_EXPLICIT_SYNC_EXT);
+  break;
+   default:
+  return EGL_BAD_PARAMETER;
+   }
+
+   return EGL_SUCCESS;
+}
+
 /**
  * Parse the list of image attributes.
  *
@@ -313,6 +335,10 @@ _eglParseImageAttribList(_EGLImageAttribs *attrs, 
_EGLDisplay *dpy,
   if (err == EGL_SUCCESS)
  continue;
 
+  err = _eglParseEXTImageImplicitSyncControlAttribs(attrs, dpy, attr, val);
+  if (err == EGL_SUCCESS)
+ continue;
+
   return _eglError(err, __func__);
}
 
diff --git a/src/egl/main/eglimage.h b/src/egl/main/eglimage.h
index 8751792132..0c3c861c0c 100644
--- a/src/egl/main/eglimage.h
+++ b/src/egl/main/eglimage.h
@@ -79,6 +79,9 @@ struct _egl_image_attribs
struct _egl_image_attrib_int DMABufSampleRangeHint;
struct _egl_image_attrib_int DMABufChromaHorizontalSiting;
struct _egl_image_attrib_int DMABufChromaVerticalSiting;
+
+   /* EGL_EXT_image_implicit_sync_control */
+   EGLBoolean ExplicitSync;
 };
 
 /**
-- 
2.13.0

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[Mesa-dev] [RFC v5 02/19] i965: Only set planar_format if it's actually one

[Louis-Francis Ratté-Boulianne]

The planar_format image property was always set even for
non-planar formats. This was breaking CCS support as
intel_from_planar is now making sure we can't have both
a modifier and an planar format.

Signed-off-by: Louis-Francis Ratté-Boulianne 
Reviewed-by: Daniel Stone 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 10064c3236..b87ccab0a8 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -913,7 +913,8 @@ intel_create_image_from_names(__DRIscreen *dri_screen,
if (image == NULL)
   return NULL;
 
-image->planar_format = f;
+if (f->nplanes > 1)
+image->planar_format = f;
 for (i = 0; i < f->nplanes; i++) {
 index = f->planes[i].buffer_index;
 image->offsets[index] = offsets[index];
@@ -961,7 +962,8 @@ intel_create_image_from_fds_common(__DRIscreen *dri_screen,
image->height = height;
image->pitch = strides[0];
 
-   image->planar_format = f;
+   if (f->nplanes > 1)
+  image->planar_format = f;
 
image->bo = brw_bo_gem_create_from_prime(screen->bufmgr, fds[0]);
if (image->bo == NULL) {
-- 
2.13.0

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[Mesa-dev] [RFC v5 00/19] DRI3 v1.1, ANV dmabuf

[Louis-Francis Ratté-Boulianne]

Hi,

With full support for modifiers in DRIimage, this patch series adds
support for fully plumbing them through X11. This is the fifth
revision, more context can be found here:

https://lists.freedesktop.org/archives/mesa-dev/2017-June/158457.html
https://lists.freedesktop.org/archives/mesa-dev/2017-August/168154.html
https://lists.freedesktop.org/archives/mesa-dev/2017-September/170868.html
https://lists.freedesktop.org/archives/mesa-dev/2017-October/172899.html

Since last iteration, the following changes have been made:

 - Instead of modifying the WSI create_wsi_image() hook, add a new
   create_wsi_image_with_modifiers() function. It allows drivers not
   supporting modifiers yet (such as the radv one) to keep the same
   code path as before.

 - Use the PresentOptionSuboptimal flag to inform the server
   that the client can handle SuboptimalCopy mode.

The related Git repositories are:

https://gitlab.collabora.com/lfrb/mesa/commits/rfc/2017-11/dri3-v1.1
https://gitlab.collabora.com/lfrb/xcb-proto/commits/rfc/2017-11/dri3-v1.1

Louis-Francis

-- 
2.13.0

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Re: [Mesa-dev] [PATCH 4/4] i965: Use PTE MOCS for all external buffers

[Jason Ekstrand]

On Mon, Nov 6, 2017 at 8:45 AM, Lyude Paul  wrote:

> Didn't danvet give you a RB'd here? As well:
>

I fully expect his R-B still applies but, given that I entirely rewrote the
patch, I figured I'd give him a chance to review again.


> Tested-by: Lyude Paul 
>

Thanks!

--Jason


> On Fri, 2017-11-03 at 16:17 -0700, Jason Ekstrand wrote:
> > We were already using PTE for all render targets in case one happened to
> > get scanned out.  However, this still wasn't 100% correct because there
> > are still possibly cases where we may want to texture from an external
> > buffer even though we don't know the caching mode.  This can happen, for
> > instance, on buffers imported from another GPU via prime.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101691
> > Cc: Kenneth Graunke 
> > Cc: Chris Wilson 
> > Cc: Daniel Vetter 
> > Cc: Lyude Paul 
> > ---
> >  src/mesa/drivers/dri/i965/brw_blorp.c|  7 ---
> >  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 20
> +---
> >  2 files changed, 17 insertions(+), 10 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> > b/src/mesa/drivers/dri/i965/brw_blorp.c
> > index 5a86af8..626bf44 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > @@ -114,14 +114,14 @@ brw_blorp_init(struct brw_context *brw)
> > brw->blorp.upload_shader = brw_blorp_upload_shader;
> >  }
> >
> > -static uint32_t tex_mocs[] = {
> > +static uint32_t wb_mocs[] = {
> > [7] = GEN7_MOCS_L3,
> > [8] = BDW_MOCS_WB,
> > [9] = SKL_MOCS_WB,
> > [10] = CNL_MOCS_WB,
> >  };
> >
> > -static uint32_t rb_mocs[] = {
> > +static uint32_t pte_mocs[] = {
> > [7] = GEN7_MOCS_L3,
> > [8] = BDW_MOCS_PTE,
> > [9] = SKL_MOCS_PTE,
> > @@ -158,7 +158,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
> >.buffer = mt->bo,
> >.offset = mt->offset,
> >.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
> > -  .mocs = is_render_target ? rb_mocs[devinfo->gen] :
> tex_mocs[devinfo-
> > >gen],
> > +  .mocs = (is_render_target || mt->bo->external) ? pte_mocs[devinfo-
> > >gen] :
> > +   wb_mocs[devinfo-
> > >gen],
> > };
> >
> > surf->aux_usage = aux_usage;
> > diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > index 27c241a..f174270 100644
> > --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > @@ -55,20 +55,25 @@
> >  #include "brw_defines.h"
> >  #include "brw_wm.h"
> >
> > -uint32_t tex_mocs[] = {
> > +uint32_t wb_mocs[] = {
> > [7] = GEN7_MOCS_L3,
> > [8] = BDW_MOCS_WB,
> > [9] = SKL_MOCS_WB,
> > [10] = CNL_MOCS_WB,
> >  };
> >
> > -uint32_t rb_mocs[] = {
> > +uint32_t pte_mocs[] = {
> > [7] = GEN7_MOCS_L3,
> > [8] = BDW_MOCS_PTE,
> > [9] = SKL_MOCS_PTE,
> > [10] = CNL_MOCS_PTE,
> >  };
> >
> > +static inline uint32_t get_tex_mocs(struct brw_bo *bo, unsigned int gen)
> > +{
> > + return (bo && bo->external ? pte_mocs : wb_mocs)[gen];
> > +}
> > +
> >  static void
> >  get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
> >   GLenum target, struct isl_view *view,
> > @@ -239,7 +244,7 @@ gen6_update_renderbuffer_surface(struct brw_context
> > *brw,
> >
> > uint32_t offset;
> > brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
> > -  rb_mocs[devinfo->gen],
> > +  pte_mocs[devinfo->gen],
> >, surf_index,
> >RELOC_WRITE);
> > return offset;
> > @@ -586,7 +591,7 @@ brw_update_texture_surface(struct gl_context *ctx,
> >   aux_usage = ISL_AUX_USAGE_NONE;
> >
> >brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
> > - tex_mocs[devinfo->gen],
> > + get_tex_mocs(mt->bo, devinfo->gen),
> >   surf_offset, surf_index,
> >   0);
> > }
> > @@ -617,7 +622,7 @@ brw_emit_buffer_surface_state(struct brw_context
> *brw,
> >   .size = buffer_size,
> >   .format = surface_format,
> >   .stride = pitch,
> > - .mocs = tex_mocs[devinfo->gen]);
> > + .mocs = get_tex_mocs(bo, devinfo->gen));
> >  }
> >
> >  void
> > @@ -1107,7 +1112,7 @@ update_renderbuffer_read_surfaces(struct
> brw_context
> > *brw)
> > aux_usage = ISL_AUX_USAGE_NONE;
> >
> >  brw_emit_surface_state(brw, irb->mt, target, view,
> aux_usage,
> > -   tex_mocs[devinfo->gen],

[Mesa-dev] [PATCH 1/4] i965: Add stencil buffers to cache set regardless of stencil texturing

[Jason Ekstrand]

We may access them as a texture using blorp regardless of whether or not
stencil texturing is enabled.

Cc: mesa-sta...@lists.freedesktop.org
---
 src/mesa/drivers/dri/i965/brw_draw.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 809e722..10b6298 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -564,10 +564,8 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context 
*brw)
  brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
}
 
-   if (ctx->Extensions.ARB_stencil_texturing &&
-   stencil_irb && brw->stencil_write_enabled) {
+   if (stencil_irb && brw->stencil_write_enabled)
   brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
-   }
 
for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
   struct intel_renderbuffer *irb =
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 4/4] i965: Track the depth and render caches separately

[Jason Ekstrand]

Previously, we just had one hash set for tracking depth and render
caches called brw_context::render_cache.  This is less than ideal
because the depth and render caches are separate and we can't track
moves between the depth and the render caches.  This limitation led
to some unnecessary flushing around the depth cache.  There are cases
(mostly with BLORP) where we can end up touching a depth or stencil
buffer through the render cache.  To guard against this, blorp would
unconditionally do a render_cache_set_check_flush on it's destination
which meant that if you did any rendering (including a BLORP operation)
to a given surface and then used it as a blorp destination, you would
end up flushing it out of the render cache before rendering into it.

Things get worse when you dig into the depth/stencil state code for
regular GL draw calls.  Because we may end up rendering to a depth
or stencil buffer via BLORP, we did a render_cache_set_check_flush on
all depth and stencil buffers in brw_emit_depthbuffer to ensure that
they got flushed out of the render cache prior to using them for depth
or stencil testing.  However, because we also need to track dirtiness
for depth and stencil so that we can implement depth and stencil
texturing correctly, we were adding all depth and stencil buffers to the
render cache set in brw_postdraw_set_buffers_need_resolve.  This meant
that, if anything caused 3DSTATE_DEPTH_BUFFER to get re-emitted
(currently _NEW_BUFFERS, BRW_NEW_BATCH, and BRW_NEW_BLORP), we would
almost always do a full pipeline stall and render/depth cache flush.

The root cause of both of these problems is that we can't tell the
difference between the render and depth caches in our tracking.  This
commit splits our cache tracking into two sets, one for render and one
for depth, and properly handles transitioning between the two.  We still
flush all the caches whenever anything needs to be flushed.  The idea is
that if we're going to take the hit of a flush and stall, we may as well
flush everything in the hopes that we can avoid a flush by something
else later.
---
 src/mesa/drivers/dri/i965/brw_context.h   |  7 ++
 src/mesa/drivers/dri/i965/intel_batchbuffer.c |  2 +-
 src/mesa/drivers/dri/i965/intel_fbo.c | 33 ++-
 src/mesa/drivers/dri/i965/intel_fbo.h |  5 +---
 4 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 3bee3e9..d141872 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -688,6 +688,13 @@ struct brw_context
struct set *render_cache;
 
/**
+* Set of struct brw_bo * that have been used as a depth buffer within this
+* batchbuffer and would need flushing before being used from another cache
+* domain that isn't coherent with it (i.e. the sampler).
+*/
+   struct set *depth_cache;
+
+   /**
 * Number of resets observed in the system at context creation.
 *
 * This is tracked in the context so that we can determine that another
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 1a366c7..33c79a2 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -220,7 +220,7 @@ static void
 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context *brw)
 {
intel_batchbuffer_reset(brw);
-   brw_render_cache_set_clear(brw);
+   brw_cache_sets_clear(brw);
 }
 
 void
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 927f589..75c85ec 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -970,19 +970,16 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
 }
 
 void
-brw_render_cache_set_clear(struct brw_context *brw)
+brw_cache_sets_clear(struct brw_context *brw)
 {
struct set_entry *entry;
 
set_foreach(brw->render_cache, entry) {
   _mesa_set_remove(brw->render_cache, entry);
}
-}
 
-void
-brw_render_cache_set_add_bo(struct brw_context *brw, struct brw_bo *bo)
-{
-   _mesa_set_add(brw->render_cache, bo);
+   set_foreach(brw->depth_cache, entry)
+  _mesa_set_remove(brw->depth_cache, entry);
 }
 
 /**
@@ -997,14 +994,11 @@ brw_render_cache_set_add_bo(struct brw_context *brw, 
struct brw_bo *bo)
  * necessary is flushed before another use of that BO, but for reuse from
  * different caches within a batchbuffer, it's all our responsibility.
  */
-void
-brw_render_cache_set_check_flush(struct brw_context *brw, struct brw_bo *bo)
+static void
+flush_depth_and_render_caches(struct brw_context *brw, struct brw_bo *bo)
 {
const struct gen_device_info *devinfo = >screen->devinfo;
 
-   if (!_mesa_set_search(brw->render_cache, bo))
-  return;
-
if (devinfo->gen >= 6) {
   brw_emit_pipe_control_flush(brw,
  

[Mesa-dev] [PATCH 3/4] i965/blorp: Add more destination flushing

[Jason Ekstrand]

Right now we just always flush the destination for render and aren't
particularly careful about depth or stencil.  Soon, flush_for_render
isn't going to do the same thing as flush_for_depth and we may be doing
a good deal less depth flushing so we should be a bit more precise.
---
 src/mesa/drivers/dri/i965/genX_blorp_exec.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c 
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 296a83b..5d884cf 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -216,7 +216,12 @@ genX(blorp_exec)(struct blorp_batch *batch,
 */
if (params->src.enabled)
   brw_cache_flush_for_read(brw, params->src.addr.buffer);
-   brw_cache_flush_for_render(brw, params->dst.addr.buffer);
+   if (params->dst.enabled)
+  brw_cache_flush_for_render(brw, params->dst.addr.buffer);
+   if (params->depth.enabled)
+  brw_cache_flush_for_depth(brw, params->depth.addr.buffer);
+   if (params->stencil.enabled)
+  brw_cache_flush_for_depth(brw, params->stencil.addr.buffer);
 
brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
 
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 2/4] i965: Add more precise cache tracking helpers

[Jason Ekstrand]

In theory, this will let us track the depth and render caches
separately.  Right now, they're just wrappers around
brw_render_cache_set_*
---
 src/mesa/drivers/dri/i965/brw_draw.c  | 12 +--
 src/mesa/drivers/dri/i965/brw_misc_state.c|  4 ++--
 src/mesa/drivers/dri/i965/genX_blorp_exec.c   | 10 -
 src/mesa/drivers/dri/i965/intel_fbo.c | 29 +++
 src/mesa/drivers/dri/i965/intel_fbo.h |  6 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  2 +-
 6 files changed, 49 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 10b6298..8920b00 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -426,7 +426,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering)
 min_layer, num_layers,
 disable_aux);
 
-  brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
+  brw_cache_flush_for_read(brw, tex_obj->mt->bo);
 
   if (tex_obj->base.StencilSampling ||
   tex_obj->mt->format == MESA_FORMAT_S_UINT8) {
@@ -450,7 +450,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering)
 
intel_miptree_prepare_image(brw, tex_obj->mt);
 
-   brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
+   brw_cache_flush_for_read(brw, tex_obj->mt->bo);
 }
  }
   }
@@ -561,11 +561,11 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context 
*brw)
 depth_written);
   }
   if (depth_written)
- brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
+ brw_depth_cache_add_bo(brw, depth_irb->mt->bo);
}
 
if (stencil_irb && brw->stencil_write_enabled)
-  brw_render_cache_set_add_bo(brw, stencil_irb->mt->bo);
+  brw_depth_cache_add_bo(brw, stencil_irb->mt->bo);
 
for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
   struct intel_renderbuffer *irb =
@@ -578,7 +578,7 @@ brw_postdraw_set_buffers_need_resolve(struct brw_context 
*brw)
  _mesa_get_render_format(ctx, intel_rb_format(irb));
   enum isl_format isl_format = brw_isl_format_for_mesa_format(mesa_format);
 
-  brw_render_cache_set_add_bo(brw, irb->mt->bo);
+  brw_render_cache_add_bo(brw, irb->mt->bo);
   intel_miptree_finish_render(brw, irb->mt, irb->mt_level,
   irb->mt_layer, irb->layer_count,
   isl_format,
@@ -593,7 +593,7 @@ intel_renderbuffer_move_temp_back(struct brw_context *brw,
if (irb->align_wa_mt == NULL)
   return;
 
-   brw_render_cache_set_check_flush(brw, irb->align_wa_mt->bo);
+   brw_cache_flush_for_read(brw, irb->align_wa_mt->bo);
 
intel_miptree_copy_slice(brw, irb->align_wa_mt, 0, 0,
 irb->mt,
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 53137cc..fd96485 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -333,9 +333,9 @@ brw_emit_depthbuffer(struct brw_context *brw)
}
 
if (depth_mt)
-  brw_render_cache_set_check_flush(brw, depth_mt->bo);
+  brw_cache_flush_for_depth(brw, depth_mt->bo);
if (stencil_mt)
-  brw_render_cache_set_check_flush(brw, stencil_mt->bo);
+  brw_cache_flush_for_depth(brw, stencil_mt->bo);
 
brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
 depthbuffer_format, depth_surface_type,
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c 
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 3c7a7b4..296a83b 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -215,8 +215,8 @@ genX(blorp_exec)(struct blorp_batch *batch,
 * data.
 */
if (params->src.enabled)
-  brw_render_cache_set_check_flush(brw, params->src.addr.buffer);
-   brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
+  brw_cache_flush_for_read(brw, params->src.addr.buffer);
+   brw_cache_flush_for_render(brw, params->dst.addr.buffer);
 
brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
 
@@ -283,9 +283,9 @@ retry:
brw->ib.index_size = -1;
 
if (params->dst.enabled)
-  brw_render_cache_set_add_bo(brw, params->dst.addr.buffer);
+  brw_render_cache_add_bo(brw, params->dst.addr.buffer);
if (params->depth.enabled)
-  brw_render_cache_set_add_bo(brw, params->depth.addr.buffer);
+  brw_depth_cache_add_bo(brw, params->depth.addr.buffer);
if (params->stencil.enabled)
-  brw_render_cache_set_add_bo(brw, params->stencil.addr.buffer);
+  brw_depth_cache_add_bo(brw, params->stencil.addr.buffer);
 }
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index 

Re: [Mesa-dev] [PATCH 00/12] anv: Add support for the variablePointers feature

[Jason Ekstrand]

On Mon, Nov 6, 2017 at 12:18 PM, Chad Versace 
wrote:

> Jason, I tested this series against the khronos-internal vk-gl-cts and
> found an assertion failure in src/compiler/spirv. Any thoughts?
>
> I haven't debugged yet because I don't grok these parts of Mesa.
>
> vk-gl-cts
>
> commit a24448cdd72ffdbd8f7f571886625b8a53100979
>
> mesa
>
> refs/tags/chadv/test/anv-variable-pointers-2017-11-06-r1
> cgit: http://git.kiwitree.net/cgit/~chadv/mesa/tag/?h=chadv/test/
> anv-variable-pointers-2017-11-06-r1
> base: master 4bcb48b "radv: add initial copy descriptor support. (v2)"
>
> error
>
> Test case 'dEQP-VK.spirv_assembly.instruction.compute.variable_
> pointers.complex_types_compute.opptraccesschain_
> matrices_two_buffers_second_input'..
> INTEL-MESA: debug: anv_GetPhysicalDeviceFeatures2KHR: ignored
> VkStructureType VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES_
> KHR(183000)
> deqp-vk: ../../../../../src/mesa/src/compiler/spirv/vtn_variables.c:174:
> vtn_ssa_offset_pointer_dereference: Assertion `offset' failed.
>

That looks very much like a test bug that I fixed.  The CLs have been
merged into vulkan-gl-cts-1.0.2 but I don't know if that's been merged
forward yet.  Try that CTS version and see if it still fails.  It's CLs
#1864 and #1863 in gerrit if you're interested.

--Jason
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[Mesa-dev] [PATCH] gallium/dri2: Enable {GLX_ARB, EGL_KHR}_context_flush_control

[Adam Jackson]

Signed-off-by: Adam Jackson 
---
 src/gallium/state_trackers/dri/dri2.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/state_trackers/dri/dri2.c 
b/src/gallium/state_trackers/dri/dri2.c
index e0cd0e0bc7..d6f8f7e8d1 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -1955,6 +1955,7 @@ static const __DRIextension *dri_screen_extensions[] = {
,
,
,
+   ,
NULL
 };
 
@@ -1969,6 +1970,7 @@ static const __DRIextension 
*dri_robust_screen_extensions[] = {
,
,
,
+   ,
NULL
 };
 
-- 
2.14.3

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[Mesa-dev] [PATCH] Enable flush control for hardware gallium drivers

[Adam Jackson]

i965 and the software drivers have this, but not any other gallium
driver. Sending this out-of-line since it probably wants testing on a
broad spectrum of hardware (not all of which I have).

- ajax

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Re: [Mesa-dev] [PATCH] glsl: s/unsigned/glsl_base_type/ in glsl type code

[Ian Romanick]

On 11/06/2017 01:00 PM, Brian Paul wrote:
> Declare glsl_type::sampled_type as glsl_base_type as we do for the
> base_type field.  And make base_type a bitfield to save a few bytes.

Hmm... I have mixed feelings about this.  I made a conscious decision to
have base_type be "full size" because it's used a lot.  I suspect there
will be some increase in code size across this change.  There's probably
also some performance difference, but it may not be enough to be
measurable.  I do like actually using type names. :)

As new base types were added, sampled_type remained 2 bits because GLSL
only allows float, int and uint.  This is the reason GLSL_TYPE_UINT64
and GLSL_TYPE_INT64 are not grouped with GLSL_TYPE_UINT and GLSL_TYPE_INT.

I wonder if it might be more compact (in terms of generated code) to
make both fields 8 bits and group them together.

> Update glsl_type constructor to take glsl_base_type intead of unsigned
  ^^ instead

> and pass GLSL_TYPE_VOID instead of zero.
> 
> No Piglit regressions with llvmpipe.
> ---
>  src/compiler/glsl_types.cpp | 14 +++---
>  src/compiler/glsl_types.h   | 14 +++---
>  2 files changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
> index 704b63c..1d20b02 100644
> --- a/src/compiler/glsl_types.cpp
> +++ b/src/compiler/glsl_types.cpp
> @@ -52,7 +52,7 @@ glsl_type::glsl_type(GLenum gl_type,
> gl_type(gl_type),
> base_type(base_type),
> sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
> -   sampled_type(0), interface_packing(0), interface_row_major(0),
> +   sampled_type(GLSL_TYPE_VOID), interface_packing(0), 
> interface_row_major(0),
> vector_elements(vector_elements), matrix_columns(matrix_columns),
> length(0)
>  {
> @@ -79,7 +79,7 @@ glsl_type::glsl_type(GLenum gl_type,
>  
>  glsl_type::glsl_type(GLenum gl_type, glsl_base_type base_type,
>   enum glsl_sampler_dim dim, bool shadow, bool array,
> - unsigned type, const char *name) :
> + glsl_base_type type, const char *name) :
> gl_type(gl_type),
> base_type(base_type),
> sampler_dimensionality(dim), sampler_shadow(shadow),
> @@ -104,7 +104,7 @@ glsl_type::glsl_type(const glsl_struct_field *fields, 
> unsigned num_fields,
> gl_type(0),
> base_type(GLSL_TYPE_STRUCT),
> sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
> -   sampled_type(0), interface_packing(0), interface_row_major(0),
> +   sampled_type(GLSL_TYPE_VOID), interface_packing(0), 
> interface_row_major(0),
> vector_elements(0), matrix_columns(0),
> length(num_fields)
>  {
> @@ -133,7 +133,7 @@ glsl_type::glsl_type(const glsl_struct_field *fields, 
> unsigned num_fields,
> gl_type(0),
> base_type(GLSL_TYPE_INTERFACE),
> sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
> -   sampled_type(0), interface_packing((unsigned) packing),
> +   sampled_type(GLSL_TYPE_VOID), interface_packing((unsigned) packing),
> interface_row_major((unsigned) row_major),
> vector_elements(0), matrix_columns(0),
> length(num_fields)
> @@ -161,7 +161,7 @@ glsl_type::glsl_type(const glsl_type *return_type,
> gl_type(0),
> base_type(GLSL_TYPE_FUNCTION),
> sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
> -   sampled_type(0), interface_packing(0), interface_row_major(0),
> +   sampled_type(GLSL_TYPE_VOID), interface_packing(0), 
> interface_row_major(0),
> vector_elements(0), matrix_columns(0),
> length(num_params)
>  {
> @@ -193,7 +193,7 @@ glsl_type::glsl_type(const char *subroutine_name) :
> gl_type(0),
> base_type(GLSL_TYPE_SUBROUTINE),
> sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
> -   sampled_type(0), interface_packing(0), interface_row_major(0),
> +   sampled_type(GLSL_TYPE_VOID), interface_packing(0), 
> interface_row_major(0),
> vector_elements(1), matrix_columns(1),
> length(0)
>  {
> @@ -444,7 +444,7 @@ _mesa_glsl_release_types(void)
>  glsl_type::glsl_type(const glsl_type *array, unsigned length) :
> base_type(GLSL_TYPE_ARRAY),
> sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
> -   sampled_type(0), interface_packing(0), interface_row_major(0),
> +   sampled_type(GLSL_TYPE_VOID), interface_packing(0), 
> interface_row_major(0),
> vector_elements(0), matrix_columns(0),
> length(length), name(NULL)
>  {
> diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h
> index 0b4a66c..6e2d6cc 100644
> --- a/src/compiler/glsl_types.h
> +++ b/src/compiler/glsl_types.h
> @@ -145,16 +145,16 @@ enum {
>  
>  struct glsl_type {
> GLenum gl_type;
> -   glsl_base_type base_type;
> +   glsl_base_type base_type:6;
>  
> unsigned sampler_dimensionality:4; /**< \see glsl_sampler_dim */
> unsigned sampler_shadow:1;
> unsigned sampler_array:1;
> -   

Re: [Mesa-dev] [PATCH] [RFC] gallivm: Use new LLVM fast-math-flags API

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Mon, Nov 6, 2017 at 10:09 PM, Tobias Droste  wrote:
> LLVM 6 changed the API on the fast-math-flags:
> https://reviews.llvm.org/rL317488
>
> NOTE: This also enables the new flag 'ApproxFunc' to allow for
> approximations for library functions (sin, cos, ...). I'm not completly
> convinced, that this is something mesa should do.
>
> Signed-off-by: Tobias Droste 
> ---
>  src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp 
> b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> index d988910a7e..1319407290 100644
> --- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> +++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
> @@ -830,7 +830,11 @@ lp_create_builder(LLVMContextRef ctx, enum lp_float_mode 
> float_mode)
>llvm::unwrap(builder)->setFastMathFlags(flags);
>break;
> case LP_FLOAT_MODE_UNSAFE_FP_MATH:
> +#if HAVE_LLVM >= 0x0600
> +  flags.setFast();
> +#else
>flags.setUnsafeAlgebra();
> +#endif
>llvm::unwrap(builder)->setFastMathFlags(flags);
>break;
> }
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH] gallium: Guard assertions by NDEBUG instead of DEBUG

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Mon, Nov 6, 2017 at 6:39 PM, Michel Dänzer  wrote:
> From: Michel Dänzer 
>
> This matches the standard assert.h header.
>
> Signed-off-by: Michel Dänzer 
> ---
>  src/gallium/auxiliary/util/u_debug.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/util/u_debug.h 
> b/src/gallium/auxiliary/util/u_debug.h
> index 63940b72253..d2ea89f59c1 100644
> --- a/src/gallium/auxiliary/util/u_debug.h
> +++ b/src/gallium/auxiliary/util/u_debug.h
> @@ -185,7 +185,7 @@ void _debug_assert_fail(const char *expr,
>   * For non debug builds the assert macro will expand to a no-op, so do not
>   * call functions with side effects in the assert expression.
>   */
> -#ifdef DEBUG
> +#ifndef NDEBUG
>  #define debug_assert(expr) ((expr) ? (void)0 : _debug_assert_fail(#expr, 
> __FILE__, __LINE__, __FUNCTION__))
>  #else
>  #define debug_assert(expr) (void)(0 && (expr))
> --
> 2.15.0
>
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Re: [Mesa-dev] [PATCH v2 15/26] radeonsi: implement PIPE_FLUSH_{TOP, BOTTOM}_OF_PIPE

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Mon, Nov 6, 2017 at 11:23 AM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> v2: use uncached system memory for the fence, and use the CPU to
> clear it so we never read garbage when checking the fence
> ---
>  src/gallium/drivers/radeonsi/si_fence.c | 89 
> -
>  1 file changed, 88 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_fence.c 
> b/src/gallium/drivers/radeonsi/si_fence.c
> index 81007192994..fa80f4fd87a 100644
> --- a/src/gallium/drivers/radeonsi/si_fence.c
> +++ b/src/gallium/drivers/radeonsi/si_fence.c
> @@ -20,35 +20,44 @@
>   * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
> THE
>   * SOFTWARE.
>   *
>   */
>
>  #include 
>
>  #include "util/os_time.h"
>  #include "util/u_memory.h"
>  #include "util/u_queue.h"
> +#include "util/u_upload_mgr.h"
>
>  #include "si_pipe.h"
> +#include "radeon/r600_cs.h"
> +
> +struct si_fine_fence {
> +   struct r600_resource *buf;
> +   unsigned offset;
> +};
>
>  struct si_multi_fence {
> struct pipe_reference reference;
> struct pipe_fence_handle *gfx;
> struct pipe_fence_handle *sdma;
> struct tc_unflushed_batch_token *tc_token;
> struct util_queue_fence ready;
>
> /* If the context wasn't flushed at fence creation, this is non-NULL. 
> */
> struct {
> struct r600_common_context *ctx;
> unsigned ib_index;
> } gfx_unflushed;
> +
> +   struct si_fine_fence fine;
>  };
>
>  static void si_add_fence_dependency(struct r600_common_context *rctx,
> struct pipe_fence_handle *fence)
>  {
> struct radeon_winsys *ws = rctx->ws;
>
> if (rctx->dma.cs)
> ws->cs_add_fence_dependency(rctx->dma.cs, fence);
> ws->cs_add_fence_dependency(rctx->gfx.cs, fence);
> @@ -59,20 +68,21 @@ static void si_fence_reference(struct pipe_screen *screen,
>struct pipe_fence_handle *src)
>  {
> struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
> struct si_multi_fence **rdst = (struct si_multi_fence **)dst;
> struct si_multi_fence *rsrc = (struct si_multi_fence *)src;
>
> if (pipe_reference(&(*rdst)->reference, >reference)) {
> ws->fence_reference(&(*rdst)->gfx, NULL);
> ws->fence_reference(&(*rdst)->sdma, NULL);
> tc_unflushed_batch_token_reference(&(*rdst)->tc_token, NULL);
> +   r600_resource_reference(&(*rdst)->fine.buf, NULL);
> FREE(*rdst);
> }
>  *rdst = rsrc;
>  }
>
>  static struct si_multi_fence *si_create_multi_fence()
>  {
> struct si_multi_fence *fence = CALLOC_STRUCT(si_multi_fence);
> if (!fence)
> return NULL;
> @@ -113,20 +123,71 @@ static void si_fence_server_sync(struct pipe_context 
> *ctx,
>  * this fence dependency is signalled.
>  *
>  * Should we flush the context to allow more GPU parallelism?
>  */
> if (rfence->sdma)
> si_add_fence_dependency(rctx, rfence->sdma);
> if (rfence->gfx)
> si_add_fence_dependency(rctx, rfence->gfx);
>  }
>
> +static bool si_fine_fence_signaled(struct radeon_winsys *rws,
> +  const struct si_fine_fence *fine)
> +{
> +   char *map = rws->buffer_map(fine->buf->buf, NULL, PIPE_TRANSFER_READ |
> + 
> PIPE_TRANSFER_UNSYNCHRONIZED);
> +   if (!map)
> +   return false;
> +
> +   uint32_t *fence = (uint32_t*)(map + fine->offset);
> +   return *fence != 0;
> +}
> +
> +static void si_fine_fence_set(struct si_context *ctx,
> + struct si_fine_fence *fine,
> + unsigned flags)
> +{
> +   uint32_t *fence_ptr;
> +
> +   assert(util_bitcount(flags & (PIPE_FLUSH_TOP_OF_PIPE | 
> PIPE_FLUSH_BOTTOM_OF_PIPE)) == 1);
> +
> +   /* Use uncached system memory for the fence. */
> +   u_upload_alloc(ctx->b.b.stream_uploader, 0, 4, 4,
> +  >offset, (struct pipe_resource **)>buf, 
> (void **)_ptr);
> +   if (!fine->buf)
> +   return;
> +
> +   *fence_ptr = 0;
> +
> +   uint64_t fence_va = fine->buf->gpu_address + fine->offset;
> +
> +   radeon_add_to_buffer_list(>b, >b.gfx, fine->buf,
> + RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
> +   if (flags & PIPE_FLUSH_TOP_OF_PIPE) {
> +   struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
> +   radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
> +   radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
> +   S_370_WR_CONFIRM(1) |
> +   

[Mesa-dev] [PATCH] [RFC] gallivm: Use new LLVM fast-math-flags API

[Tobias Droste]

LLVM 6 changed the API on the fast-math-flags:
https://reviews.llvm.org/rL317488

NOTE: This also enables the new flag 'ApproxFunc' to allow for
approximations for library functions (sin, cos, ...). I'm not completly
convinced, that this is something mesa should do.

Signed-off-by: Tobias Droste 
---
 src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp 
b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
index d988910a7e..1319407290 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp
@@ -830,7 +830,11 @@ lp_create_builder(LLVMContextRef ctx, enum lp_float_mode 
float_mode)
   llvm::unwrap(builder)->setFastMathFlags(flags);
   break;
case LP_FLOAT_MODE_UNSAFE_FP_MATH:
+#if HAVE_LLVM >= 0x0600
+  flags.setFast();
+#else
   flags.setUnsafeAlgebra();
+#endif
   llvm::unwrap(builder)->setFastMathFlags(flags);
   break;
}
-- 
2.14.3

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[Mesa-dev] [PATCH] glsl: s/unsigned/glsl_base_type/ in glsl type code

[Brian Paul]

Declare glsl_type::sampled_type as glsl_base_type as we do for the
base_type field.  And make base_type a bitfield to save a few bytes.

Update glsl_type constructor to take glsl_base_type intead of unsigned
and pass GLSL_TYPE_VOID instead of zero.

No Piglit regressions with llvmpipe.
---
 src/compiler/glsl_types.cpp | 14 +++---
 src/compiler/glsl_types.h   | 14 +++---
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index 704b63c..1d20b02 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -52,7 +52,7 @@ glsl_type::glsl_type(GLenum gl_type,
gl_type(gl_type),
base_type(base_type),
sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing(0), interface_row_major(0),
+   sampled_type(GLSL_TYPE_VOID), interface_packing(0), interface_row_major(0),
vector_elements(vector_elements), matrix_columns(matrix_columns),
length(0)
 {
@@ -79,7 +79,7 @@ glsl_type::glsl_type(GLenum gl_type,
 
 glsl_type::glsl_type(GLenum gl_type, glsl_base_type base_type,
  enum glsl_sampler_dim dim, bool shadow, bool array,
- unsigned type, const char *name) :
+ glsl_base_type type, const char *name) :
gl_type(gl_type),
base_type(base_type),
sampler_dimensionality(dim), sampler_shadow(shadow),
@@ -104,7 +104,7 @@ glsl_type::glsl_type(const glsl_struct_field *fields, 
unsigned num_fields,
gl_type(0),
base_type(GLSL_TYPE_STRUCT),
sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing(0), interface_row_major(0),
+   sampled_type(GLSL_TYPE_VOID), interface_packing(0), interface_row_major(0),
vector_elements(0), matrix_columns(0),
length(num_fields)
 {
@@ -133,7 +133,7 @@ glsl_type::glsl_type(const glsl_struct_field *fields, 
unsigned num_fields,
gl_type(0),
base_type(GLSL_TYPE_INTERFACE),
sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing((unsigned) packing),
+   sampled_type(GLSL_TYPE_VOID), interface_packing((unsigned) packing),
interface_row_major((unsigned) row_major),
vector_elements(0), matrix_columns(0),
length(num_fields)
@@ -161,7 +161,7 @@ glsl_type::glsl_type(const glsl_type *return_type,
gl_type(0),
base_type(GLSL_TYPE_FUNCTION),
sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing(0), interface_row_major(0),
+   sampled_type(GLSL_TYPE_VOID), interface_packing(0), interface_row_major(0),
vector_elements(0), matrix_columns(0),
length(num_params)
 {
@@ -193,7 +193,7 @@ glsl_type::glsl_type(const char *subroutine_name) :
gl_type(0),
base_type(GLSL_TYPE_SUBROUTINE),
sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing(0), interface_row_major(0),
+   sampled_type(GLSL_TYPE_VOID), interface_packing(0), interface_row_major(0),
vector_elements(1), matrix_columns(1),
length(0)
 {
@@ -444,7 +444,7 @@ _mesa_glsl_release_types(void)
 glsl_type::glsl_type(const glsl_type *array, unsigned length) :
base_type(GLSL_TYPE_ARRAY),
sampler_dimensionality(0), sampler_shadow(0), sampler_array(0),
-   sampled_type(0), interface_packing(0), interface_row_major(0),
+   sampled_type(GLSL_TYPE_VOID), interface_packing(0), interface_row_major(0),
vector_elements(0), matrix_columns(0),
length(length), name(NULL)
 {
diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h
index 0b4a66c..6e2d6cc 100644
--- a/src/compiler/glsl_types.h
+++ b/src/compiler/glsl_types.h
@@ -145,16 +145,16 @@ enum {
 
 struct glsl_type {
GLenum gl_type;
-   glsl_base_type base_type;
+   glsl_base_type base_type:6;
 
unsigned sampler_dimensionality:4; /**< \see glsl_sampler_dim */
unsigned sampler_shadow:1;
unsigned sampler_array:1;
-   unsigned sampled_type:2;/**< Type of data returned using this
-   * sampler or image.  Only \c
-   * GLSL_TYPE_FLOAT, \c GLSL_TYPE_INT,
-   * and \c GLSL_TYPE_UINT are valid.
-   */
+   glsl_base_type sampled_type:6; /**< Type of data returned using this
+   * sampler or image.  Only \c
+   * GLSL_TYPE_FLOAT, \c GLSL_TYPE_INT,
+   * and \c GLSL_TYPE_UINT are valid.
+   */
unsigned interface_packing:2;
unsigned interface_row_major:1;
 
@@ -874,7 +874,7 @@ private:
/** Constructor for sampler or image types */
glsl_type(GLenum gl_type, glsl_base_type base_type,
 enum glsl_sampler_dim dim, bool shadow, bool array,
-unsigned type, const char *name);
+glsl_base_type type, const char *name);
 
   

[Mesa-dev] [PATCH 1/2] st/mesa: use enum types instead of int/unsigned

[Brian Paul]

Use the proper enum types for various variables.  Makes life in gdb
a little nicer.
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp   | 7 ---
 src/mesa/state_tracker/st_glsl_to_tgsi_private.h | 6 +++---
 src/mesa/state_tracker/st_mesa_to_tgsi.c | 6 +++---
 src/mesa/state_tracker/st_mesa_to_tgsi.h | 7 ---
 4 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 54e1961..2048b59 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -179,10 +179,10 @@ public:
int num_address_regs;
uint32_t samplers_used;
glsl_base_type sampler_types[PIPE_MAX_SAMPLERS];
-   int sampler_targets[PIPE_MAX_SAMPLERS];   /**< One of TGSI_TEXTURE_* */
+   enum tgsi_texture_type sampler_targets[PIPE_MAX_SAMPLERS];
int images_used;
int image_targets[PIPE_MAX_SHADER_IMAGES];
-   unsigned image_formats[PIPE_MAX_SHADER_IMAGES];
+   enum pipe_format image_formats[PIPE_MAX_SHADER_IMAGES];
bool indirect_addr_consts;
int wpos_transform_const;
 
@@ -6489,7 +6489,8 @@ st_translate_program(
/* texture samplers */
for (i = 0; i < frag_const->MaxTextureImageUnits; i++) {
   if (program->samplers_used & (1u << i)) {
- unsigned type = st_translate_texture_type(program->sampler_types[i]);
+ enum tgsi_return_type type =
+st_translate_texture_type(program->sampler_types[i]);
 
  t->samplers[i] = ureg_DECL_sampler(ureg, i);
 
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi_private.h 
b/src/mesa/state_tracker/st_glsl_to_tgsi_private.h
index d57525d..bdc7448 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi_private.h
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi_private.h
@@ -127,13 +127,13 @@ public:
unsigned is_64bit_expanded:1;
unsigned sampler_base:5;
unsigned sampler_array_size:6; /**< 1-based size of sampler array, 1 if not 
array */
-   unsigned tex_target:4; /**< One of TEXTURE_*_INDEX */
+   gl_texture_index tex_target:5;
glsl_base_type tex_type:5;
unsigned tex_shadow:1;
-   unsigned image_format:9;
+   enum pipe_format image_format:9;
unsigned tex_offset_num_offset:3;
unsigned dead_mask:4; /**< Used in dead code elimination */
-   unsigned buffer_access:3; /**< buffer access type */
+   unsigned buffer_access:3; /**< bitmask of TGSI_MEMORY_x bits */
 
const struct tgsi_opcode_info *info;
 };
diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c 
b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index fa9fa44..8a61776 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -166,8 +166,8 @@ src_register( struct st_translate *t,
 /**
  * Map mesa texture target to TGSI texture target.
  */
-unsigned
-st_translate_texture_target(GLuint textarget, GLboolean shadow)
+enum tgsi_texture_type
+st_translate_texture_target(gl_texture_index textarget, GLboolean shadow)
 {
if (shadow) {
   switch (textarget) {
@@ -225,7 +225,7 @@ st_translate_texture_target(GLuint textarget, GLboolean 
shadow)
 /**
  * Map GLSL base type to TGSI return type.
  */
-unsigned
+enum tgsi_return_type
 st_translate_texture_type(enum glsl_base_type type)
 {
switch (type) {
diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.h 
b/src/mesa/state_tracker/st_mesa_to_tgsi.h
index 106cf85..06e8b70 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.h
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.h
@@ -30,6 +30,7 @@
 #define ST_MESA_TO_TGSI_H
 
 #include "main/glheader.h"
+#include "main/mtypes.h"
 
 #include "pipe/p_compiler.h"
 #include "pipe/p_defines.h"
@@ -62,10 +63,10 @@ st_translate_mesa_program(
const ubyte outputSemanticName[],
const ubyte outputSemanticIndex[]);
 
-unsigned
-st_translate_texture_target(GLuint textarget, GLboolean shadow);
+enum tgsi_texture_type
+st_translate_texture_target(gl_texture_index textarget, GLboolean shadow);
 
-unsigned
+enum tgsi_return_type
 st_translate_texture_type(enum glsl_base_type type);
 
 #if defined __cplusplus
-- 
1.9.1

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[Mesa-dev] [PATCH 2/2] st/mesa: whitespace clean-up in st_mesa_to_tgsi.c

[Brian Paul]

Remove trailing whitespace, fix indentation, wrap lines to 78 columns, etc.
---
 src/mesa/state_tracker/st_mesa_to_tgsi.c | 336 ---
 1 file changed, 169 insertions(+), 167 deletions(-)

diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c 
b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index 8a61776..75825c3 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -1,8 +1,8 @@
 /**
- * 
+ *
  * Copyright 2007-2008 VMware, Inc.
  * All Rights Reserved.
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the
  * "Software"), to deal in the Software without restriction, including
@@ -10,11 +10,11 @@
  * distribute, sub license, and/or sell copies of the Software, and to
  * permit persons to whom the Software is furnished to do so, subject to
  * the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
@@ -22,7 +22,7 @@
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * 
+ *
  **/
 
 /*
@@ -76,17 +76,15 @@ struct st_translate {
  * Map a Mesa dst register to a TGSI ureg_dst register.
  */
 static struct ureg_dst
-dst_register( struct st_translate *t,
-  gl_register_file file,
-  GLuint index )
+dst_register(struct st_translate *t, gl_register_file file, GLuint index)
 {
-   switch( file ) {
+   switch(file) {
case PROGRAM_UNDEFINED:
   return ureg_dst_undef();
 
case PROGRAM_TEMPORARY:
   if (ureg_dst_is_undef(t->temps[index]))
- t->temps[index] = ureg_DECL_temporary( t->ureg );
+ t->temps[index] = ureg_DECL_temporary(t->ureg);
 
   return t->temps[index];
 
@@ -106,7 +104,7 @@ dst_register( struct st_translate *t,
   return t->address[index];
 
default:
-  debug_assert( 0 );
+  debug_assert(0);
   return ureg_dst_undef();
}
 }
@@ -116,11 +114,11 @@ dst_register( struct st_translate *t,
  * Map a Mesa src register to a TGSI ureg_src register.
  */
 static struct ureg_src
-src_register( struct st_translate *t,
+src_register(struct st_translate *t,
   gl_register_file file,
-  GLint index )
+  GLint index)
 {
-   switch( file ) {
+   switch(file) {
case PROGRAM_UNDEFINED:
   return ureg_src_undef();
 
@@ -128,7 +126,7 @@ src_register( struct st_translate *t,
   assert(index >= 0);
   assert(index < ARRAY_SIZE(t->temps));
   if (ureg_dst_is_undef(t->temps[index]))
- t->temps[index] = ureg_DECL_temporary( t->ureg );
+ t->temps[index] = ureg_DECL_temporary(t->ureg);
   return ureg_src(t->temps[index]);
 
case PROGRAM_UNIFORM:
@@ -137,7 +135,7 @@ src_register( struct st_translate *t,
case PROGRAM_STATE_VAR:
case PROGRAM_CONSTANT:   /* ie, immediate */
   if (index < 0)
- return ureg_DECL_constant( t->ureg, 0 );
+ return ureg_DECL_constant(t->ureg, 0);
   else
  return t->constants[index];
 
@@ -157,7 +155,7 @@ src_register( struct st_translate *t,
   return t->systemValues[index];
 
default:
-  debug_assert( 0 );
+  debug_assert(0);
   return ureg_src_undef();
}
 }
@@ -228,17 +226,17 @@ st_translate_texture_target(gl_texture_index textarget, 
GLboolean shadow)
 enum tgsi_return_type
 st_translate_texture_type(enum glsl_base_type type)
 {
-   switch (type) {
-   case GLSL_TYPE_INT:
-   return TGSI_RETURN_TYPE_SINT;
-   case GLSL_TYPE_UINT:
-   return TGSI_RETURN_TYPE_UINT;
-   case GLSL_TYPE_FLOAT:
-   return TGSI_RETURN_TYPE_FLOAT;
-   default:
-   assert(!"unexpected texture type");
-   return TGSI_RETURN_TYPE_UNKNOWN;
-   }
+   switch (type) {
+   case GLSL_TYPE_INT:
+  return TGSI_RETURN_TYPE_SINT;
+   case GLSL_TYPE_UINT:
+  return TGSI_RETURN_TYPE_UINT;
+   case GLSL_TYPE_FLOAT:
+  return TGSI_RETURN_TYPE_FLOAT;
+   default:
+  assert(!"unexpected texture type");
+  return TGSI_RETURN_TYPE_UNKNOWN;
+   }
 }
 
 
@@ -259,22 +257,19 @@ translate_texture_index(GLbitfield texBit, bool shadow)
  * Create a TGSI ureg_dst register from a Mesa dest register.
  */
 static struct ureg_dst
-translate_dst( struct st_translate *t,
-   const struct 

Re: [Mesa-dev] [PATCH v2 14/26] radeonsi: document some subtle details of fence_finish & fence_server_sync

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Mon, Nov 6, 2017 at 11:23 AM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> v2: remove the change to si_fence_server_sync, we'll handle that more
> robustly
>
> Reviewed-by: Marek Olšák  (v1)
> ---
>  src/gallium/drivers/radeonsi/si_fence.c | 22 ++
>  1 file changed, 22 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_fence.c 
> b/src/gallium/drivers/radeonsi/si_fence.c
> index 701e8df9cfc..81007192994 100644
> --- a/src/gallium/drivers/radeonsi/si_fence.c
> +++ b/src/gallium/drivers/radeonsi/si_fence.c
> @@ -168,20 +168,42 @@ static boolean si_fence_finish(struct pipe_screen 
> *screen,
> }
> }
>
> if (!rfence->gfx)
> return true;
>
> /* Flush the gfx IB if it hasn't been flushed yet. */
> if (rctx &&
> rfence->gfx_unflushed.ctx == rctx &&
> rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
> +   /* Section 4.1.2 (Signaling) of the OpenGL 4.6 (Core profile)
> +* spec says:
> +*
> +*"If the sync object being blocked upon will not be
> +* signaled in finite time (for example, by an associated
> +* fence command issued previously, but not yet flushed to
> +* the graphics pipeline), then ClientWaitSync may hang
> +* forever. To help prevent this behavior, if
> +* ClientWaitSync is called and all of the following are
> +* true:
> +*
> +* * the SYNC_FLUSH_COMMANDS_BIT bit is set in flags,
> +* * sync is unsignaled when ClientWaitSync is called,
> +* * and the calls to ClientWaitSync and FenceSync were
> +*   issued from the same context,
> +*
> +* then the GL will behave as if the equivalent of Flush
> +* were inserted immediately after the creation of sync."
> +*
> +* This means we need to flush for such fences even when we're
> +* not going to wait.
> +*/
> rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
> rfence->gfx_unflushed.ctx = NULL;
>
> if (!timeout)
> return false;
>
> /* Recompute the timeout after all that. */
> if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
> int64_t time = os_time_get_nano();
> timeout = abs_timeout > time ? abs_timeout - time : 0;
> --
> 2.11.0
>
> ___
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Re: [Mesa-dev] [PATCH v2 10/26] gallium/u_threaded: implement asynchronous flushes

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Mon, Nov 6, 2017 at 11:23 AM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> This requires out-of-band creation of fences, and will be signaled to
> the pipe_context::flush implementation by a special TC_FLUSH_ASYNC flag.
>
> v2:
> - remove an incorrect assertion
> - handle fence_server_sync for unsubmitted fences by
>   relying on the improved cs_add_fence_dependency
> - only implement asynchronous flushes on amdgpu
> ---
>  src/gallium/auxiliary/util/u_threaded_context.c|  96 ++-
>  src/gallium/auxiliary/util/u_threaded_context.h|  59 
>  .../auxiliary/util/u_threaded_context_calls.h  |   1 +
>  src/gallium/drivers/radeonsi/si_fence.c| 104 
> -
>  src/gallium/drivers/radeonsi/si_pipe.c |   3 +
>  src/gallium/drivers/radeonsi/si_pipe.h |   2 +
>  6 files changed, 238 insertions(+), 27 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_threaded_context.c 
> b/src/gallium/auxiliary/util/u_threaded_context.c
> index 24fab7f5cb6..0bb645e8522 100644
> --- a/src/gallium/auxiliary/util/u_threaded_context.c
> +++ b/src/gallium/auxiliary/util/u_threaded_context.c
> @@ -81,40 +81,47 @@ tc_debug_check(struct threaded_context *tc)
>
>  static void
>  tc_batch_execute(void *job, int thread_index)
>  {
> struct tc_batch *batch = job;
> struct pipe_context *pipe = batch->pipe;
> struct tc_call *last = >call[batch->num_total_call_slots];
>
> tc_batch_check(batch);
>
> +   assert(!batch->token);
> +
> for (struct tc_call *iter = batch->call; iter != last;
>  iter += iter->num_call_slots) {
>tc_assert(iter->sentinel == TC_SENTINEL);
>execute_func[iter->call_id](pipe, >payload);
> }
>
> tc_batch_check(batch);
> batch->num_total_call_slots = 0;
>  }
>
>  static void
>  tc_batch_flush(struct threaded_context *tc)
>  {
> struct tc_batch *next = >batch_slots[tc->next];
>
> tc_assert(next->num_total_call_slots != 0);
> tc_batch_check(next);
> tc_debug_check(tc);
> p_atomic_add(>num_offloaded_slots, next->num_total_call_slots);
>
> +   if (next->token) {
> +  next->token->tc = NULL;
> +  tc_unflushed_batch_token_reference(>token, NULL);
> +   }
> +
> util_queue_add_job(>queue, next, >fence, tc_batch_execute,
>NULL);
> tc->last = tc->next;
> tc->next = (tc->next + 1) % TC_MAX_BATCHES;
>  }
>
>  /* This is the function that adds variable-sized calls into the current
>   * batch. It also flushes the batch if there is not enough space there.
>   * All other higher-level "add" functions use it.
>   */
> @@ -172,40 +179,63 @@ _tc_sync(struct threaded_context *tc, const char *info, 
> const char *func)
> tc_debug_check(tc);
>
> /* Only wait for queued calls... */
> if (!util_queue_fence_is_signalled(>fence)) {
>util_queue_fence_wait(>fence);
>synced = true;
> }
>
> tc_debug_check(tc);
>
> +   if (next->token) {
> +  next->token->tc = NULL;
> +  tc_unflushed_batch_token_reference(>token, NULL);
> +   }
> +
> /* .. and execute unflushed calls directly. */
> if (next->num_total_call_slots) {
>p_atomic_add(>num_direct_slots, next->num_total_call_slots);
>tc_batch_execute(next, 0);
>synced = true;
> }
>
> if (synced) {
>p_atomic_inc(>num_syncs);
>
>if (tc_strcmp(func, "tc_destroy") != 0)
>   tc_printf("sync %s %s\n", func, info);
> }
>
> tc_debug_check(tc);
>  }
>
>  #define tc_sync(tc) _tc_sync(tc, "", __func__)
>  #define tc_sync_msg(tc, info) _tc_sync(tc, info, __func__)
>
> +/**
> + * Call this from fence_finish for same-context fence waits of deferred 
> fences
> + * that haven't been flushed yet.
> + *
> + * The passed pipe_context must be the one passed to 
> pipe_screen::fence_finish,
> + * i.e., the wrapped one.
> + */
> +void
> +threaded_context_flush(struct pipe_context *_pipe,
> +   struct tc_unflushed_batch_token *token)
> +{
> +   struct threaded_context *tc = threaded_context(_pipe);
> +
> +   /* This is called from the state-tracker / application thread. */
> +   if (token->tc && token->tc == tc)
> +  tc_sync(token->tc);
> +}
> +
>  static void
>  tc_set_resource_reference(struct pipe_resource **dst, struct pipe_resource 
> *src)
>  {
> *dst = NULL;
> pipe_resource_reference(dst, src);
>  }
>
>  void
>  threaded_resource_init(struct pipe_resource *res)
>  {
> @@ -1775,36 +1805,94 @@ tc_create_video_buffer(struct pipe_context *_pipe,
>  {
> unreachable("Threaded context should not be enabled for video APIs");
> return NULL;
>  }
>
>
>  /
>   * draw, launch, clear, blit, copy, flush
>   */
>
> +struct tc_flush_payload {
> +   struct pipe_fence_handle *fence;
> +   unsigned flags;
> 

Re: [Mesa-dev] [PATCH 2/2] r600g: use SIMPLE_FLOAT for blending to avoid NaNs in RTs

[Roland Scheidegger]

The patch doesn't help at all, but looks like a sensible thing to do anyway.

Reviewed-by: Roland Scheidegger 


Am 06.11.2017 um 05:22 schrieb Ilia Mirkin:
> Radeonsi also sets this flag.
> 
> Bugzilla: 
> https://urldefense.proofpoint.com/v2/url?u=https-3A__bugs.freedesktop.org_show-5Fbug.cgi-3Fid-3D103544=DwIGaQ=uilaK90D4TOVoH58JNXRgQ=_QIjpv-UJ77xEQY8fIYoQtr5qv8wKrPJc7v7_-CYAb0=yxACLhIHICZX46SSzjjTfuRdjgrY5Bxt4aJpAVfYMZw=VXVixXZEdahpJm__SRlvsGYPx9umOxP_Whefe0xyWXE=
> Signed-off-by: Ilia Mirkin 
> ---
> 
> This needs testing with the fbo-float-nan piglit that was recently added. Just
> guessing that this is the right flag to set here.
> 
>  src/gallium/drivers/r600/evergreen_state.c | 1 +
>  src/gallium/drivers/r600/r600_state.c  | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/src/gallium/drivers/r600/evergreen_state.c 
> b/src/gallium/drivers/r600/evergreen_state.c
> index 96eb35a9818..131778dea9f 100644
> --- a/src/gallium/drivers/r600/evergreen_state.c
> +++ b/src/gallium/drivers/r600/evergreen_state.c
> @@ -1211,6 +1211,7 @@ static void evergreen_set_color_surface_common(struct 
> r600_context *rctx,
>   S_028C70_COMP_SWAP(swap) |
>   S_028C70_BLEND_CLAMP(blend_clamp) |
>   S_028C70_BLEND_BYPASS(blend_bypass) |
> + S_028C70_SIMPLE_FLOAT(1) |
>   S_028C70_NUMBER_TYPE(ntype) |
>   S_028C70_ENDIAN(endian);
>  
> diff --git a/src/gallium/drivers/r600/r600_state.c 
> b/src/gallium/drivers/r600/r600_state.c
> index c21e8dabb1f..0c331537460 100644
> --- a/src/gallium/drivers/r600/r600_state.c
> +++ b/src/gallium/drivers/r600/r600_state.c
> @@ -898,6 +898,7 @@ static void r600_init_color_surface(struct r600_context 
> *rctx,
>   S_0280A0_COMP_SWAP(swap) |
>   S_0280A0_BLEND_BYPASS(blend_bypass) |
>   S_0280A0_BLEND_CLAMP(blend_clamp) |
> + S_0280A0_SIMPLE_FLOAT(1) |
>   S_0280A0_NUMBER_TYPE(ntype) |
>   S_0280A0_ENDIAN(endian);
>  
> 

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Re: [Mesa-dev] [PATCH 3/2] etnaviv: Don't over-pad compressed textures

[Christian Gmeiner]

2017-11-02 16:08 GMT+01:00 Wladimir J. van der Laan :
> HALIGN_FOUR/SIXTEEN has no meaning for compressed textures, and we can't
> render to them anyway. So use the tightest possible packing. This
> avoids bugs with non-power-of-two block sizes.
>
> Signed-off-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_resource.c | 24 +++-
>  1 file changed, 15 insertions(+), 9 deletions(-)
>
> This is important in the case of ASTC. Padding ASTC to width 4 or 16
> produces intermittent magenta blocks when using texture widths
> not a multiple of those.
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c 
> b/src/gallium/drivers/etnaviv/etnaviv_resource.c
> index d6cccd2..0a82807 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_resource.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c
> @@ -209,18 +209,24 @@ etna_resource_alloc(struct pipe_screen *pscreen, 
> unsigned layout,
>return NULL;
> }
>
> -   /* If we have the TEXTURE_HALIGN feature, we can always align to the
> -* resolve engine's width.  If not, we must not align resources used
> -* only for textures. */
> -   bool rs_align = VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN) ||
> -   !etna_resource_sampler_only(templat);
> -
> /* Determine needed padding (alignment of height/width) */
> unsigned paddingX = 0, paddingY = 0;
> unsigned halign = TEXTURE_HALIGN_FOUR;
> -   etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, 
> ,
> -, );
> -   assert(paddingX && paddingY);
> +   if (!util_format_is_compressed(templat->format)) {
> +  /* If we have the TEXTURE_HALIGN feature, we can always align to the
> +   * resolve engine's width.  If not, we must not align resources used
> +   * only for textures. */
> +  bool rs_align = VIV_FEATURE(screen, chipMinorFeatures1, 
> TEXTURE_HALIGN) ||
> +  !etna_resource_sampler_only(templat);
> +  etna_layout_multiple(layout, screen->specs.pixel_pipes, rs_align, 
> ,
> +   , );
> +  assert(paddingX && paddingY);
> +   } else {
> +  /* Compressed textures are padded to their block size, but we don't 
> have
> +   * to do anything special for that. */
> +  paddingX = 1;
> +  paddingY = 1;
> +   }
>
> if (templat->target != PIPE_BUFFER)
>etna_adjust_rs_align(screen->specs.pixel_pipes, NULL, );
> --
> 2.7.4
>
>



-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info
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Re: [Mesa-dev] [PATCH 00/12] anv: Add support for the variablePointers feature

[Chad Versace]

Jason, I tested this series against the khronos-internal vk-gl-cts and
found an assertion failure in src/compiler/spirv. Any thoughts?

I haven't debugged yet because I don't grok these parts of Mesa.

vk-gl-cts

commit a24448cdd72ffdbd8f7f571886625b8a53100979

mesa

refs/tags/chadv/test/anv-variable-pointers-2017-11-06-r1
cgit: 
http://git.kiwitree.net/cgit/~chadv/mesa/tag/?h=chadv/test/anv-variable-pointers-2017-11-06-r1
base: master 4bcb48b "radv: add initial copy descriptor support. (v2)"

error

Test case 
'dEQP-VK.spirv_assembly.instruction.compute.variable_pointers.complex_types_compute.opptraccesschain_matrices_two_buffers_second_input'..
INTEL-MESA: debug: anv_GetPhysicalDeviceFeatures2KHR: ignored 
VkStructureType 
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES_KHR(183000)
deqp-vk: ../../../../../src/mesa/src/compiler/spirv/vtn_variables.c:174: 
vtn_ssa_offset_pointer_dereference: Assertion `offset' failed.
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Re: [Mesa-dev] [PATCH 12/13] meson: build gallium va state tracker

[Dylan Baker]

Quoting Aaron Watry (2017-11-03 19:51:49)
> On an unrelated note, I also had to remove the LLVM minimum version
> check temporarily, otherwise I get llvm version parsing errors from
> 6.0.0svn at the following line:
> 
>  dep_llvm = dependency(
>   'llvm', version : '>= 3.9.0', required : with_amd_vk, modules :
> llvm_modules,
>  )
> 
> Error:
> Meson encountered an error in file meson.build, line 844, column 0:
> Invalid version to compare against: '6.0.0svn'; only numeric digits
> separated by "." are allowed: invalid literal for int() with base 10:
> '0svn'
> 
> Right after that dependency check, we try to strip the 'svn' from the
> llvm version, but at that point, we've already errored out.
> 
> 
> --Aaron
> 

We have a hack in mesa for this (but like all hacks it only sorta works), but
meson 0.43.1 will have a fix to handle the svn string in the version internally.

Dylan


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Re: [Mesa-dev] [PATCH mesa 1/2] meson: switch default build type to debugoptimized

[Emil Velikov]

On 6 November 2017 at 17:19, Eric Engestrom  wrote:
> Cc: Dylan Baker 
> Cc: Chad Versace 
> Cc: Emil Velikov 
> Cc: Ilia Mirkin 
> Cc: Andres Rodriguez 
> Cc: Michel Dänzer 
> Cc: Matt Turner 
> Cc: Christian Schmidbauer 
> Cc: Eero Tamminen 
> Cc: Ernst Sjöstrand 
> Signed-off-by: Eric Engestrom 
> ---
> Sorry for the massive Cc-list, I wanted to include everyone who took
> part in the discussion.
Yes, please. Having a reasonably optimised binary for unsuspecting
builders/users, is a great IMHO ;-)

Acked-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] Couple patches for debian-experimental mesa branch

[Matt Turner]

Wrong list, I think.
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Re: [Mesa-dev] [PATCH] automake: include git_sha1.h.in in release tarball

[Emil Velikov]

On 6 November 2017 at 15:44, Juan A. Suarez Romero  wrote:
> Fixes:
>
> make[2]: Leaving directory '/home/local/mesa/mesa-17.4.0-devel/_build/sub/src'
> make[2]: *** No rule to make target '../../../src/git_sha1.h.in', needed by 
> 'git_sha1.h'.  Stop.
> Makefile:660: recipe for target 'all-recursive' failed
>
Thanks Juan.
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH] radv: add initial copy descriptor support. (v2)

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Sat, Nov 4, 2017 at 9:15 PM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> It appears the latest dota2 vulkan uses this,
> and we get a hang in VR mode without it.
>
> v2: remove finishme I left in after finishing.
>
> Cc: "17.2 17.3" 
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_descriptor_set.c | 55 
> ++--
>  1 file changed, 53 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_descriptor_set.c 
> b/src/amd/vulkan/radv_descriptor_set.c
> index 317a2b37c43..424756c13f5 100644
> --- a/src/amd/vulkan/radv_descriptor_set.c
> +++ b/src/amd/vulkan/radv_descriptor_set.c
> @@ -757,8 +757,59 @@ void radv_update_descriptor_sets(
> }
>
> }
> -   if (descriptorCopyCount)
> -   radv_finishme("copy descriptors");
> +
> +   for (i = 0; i < descriptorCopyCount; i++) {
> +   const VkCopyDescriptorSet *copyset = [i];
> +   RADV_FROM_HANDLE(radv_descriptor_set, src_set,
> +copyset->srcSet);
> +   RADV_FROM_HANDLE(radv_descriptor_set, dst_set,
> +copyset->dstSet);
> +   const struct radv_descriptor_set_binding_layout 
> *src_binding_layout =
> +   src_set->layout->binding + copyset->srcBinding;
> +   const struct radv_descriptor_set_binding_layout 
> *dst_binding_layout =
> +   dst_set->layout->binding + copyset->dstBinding;
> +   uint32_t *src_ptr = src_set->mapped_ptr;
> +   uint32_t *dst_ptr = dst_set->mapped_ptr;
> +   struct radeon_winsys_bo **src_buffer_list = 
> src_set->descriptors;
> +   struct radeon_winsys_bo **dst_buffer_list = 
> dst_set->descriptors;
> +
> +   src_ptr += src_binding_layout->offset / 4;
> +   dst_ptr += dst_binding_layout->offset / 4;
> +
> +   src_ptr += src_binding_layout->size * 
> copyset->srcArrayElement / 4;
> +   dst_ptr += dst_binding_layout->size * 
> copyset->dstArrayElement / 4;
> +
> +   src_buffer_list += src_binding_layout->buffer_offset;
> +   src_buffer_list += copyset->srcArrayElement;
> +
> +   dst_buffer_list += dst_binding_layout->buffer_offset;
> +   dst_buffer_list += copyset->dstArrayElement;
> +
> +   for (j = 0; j < copyset->descriptorCount; ++j) {
> +   switch (src_binding_layout->type) {
> +   case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
> +   case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: {
> +   unsigned src_idx = copyset->srcArrayElement + 
> j;
> +   unsigned dst_idx = copyset->dstArrayElement + 
> j;
> +   struct radv_descriptor_range *src_range, 
> *dst_range;
> +   src_idx += 
> src_binding_layout->dynamic_offset_offset;
> +   dst_idx += 
> dst_binding_layout->dynamic_offset_offset;
> +
> +   src_range = src_set->dynamic_descriptors + 
> src_idx;
> +   dst_range = dst_set->dynamic_descriptors + 
> dst_idx;
> +   *dst_range = *src_range;
> +   break;
> +   }
> +   default:
> +   memcpy(dst_ptr, src_ptr, 
> src_binding_layout->size);
> +   }
> +   src_ptr += src_binding_layout->size / 4;
> +   dst_ptr += dst_binding_layout->size / 4;
> +   dst_buffer_list[j] = src_buffer_list[j];
> +   ++src_buffer_list;
> +   ++dst_buffer_list;
> +   }
> +   }
>  }
>
>  void radv_UpdateDescriptorSets(
> --
> 2.14.2
>
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Re: [Mesa-dev] [PATCH mesa 1/2] meson: switch default build type to debugoptimized

[Andres Rodriguez]

For both patches:


Acked-by: Andres Rodriguez 

On Mon, Nov 6, 2017 at 1:06 PM, Chad Versace  wrote:
> For both patches,
> Reviewed-by: Chad Versace 
> Tested-by: Chad Versace 
>
>
> On Mon 06 Nov 2017, Eric Engestrom wrote:
>> Cc: Dylan Baker 
>> Cc: Chad Versace 
>> Cc: Emil Velikov 
>> Cc: Ilia Mirkin 
>> Cc: Andres Rodriguez 
>> Cc: Michel Dänzer 
>> Cc: Matt Turner 
>> Cc: Christian Schmidbauer 
>> Cc: Eero Tamminen 
>> Cc: Ernst Sjöstrand 
>> Signed-off-by: Eric Engestrom 
>> ---
>> Sorry for the massive Cc-list, I wanted to include everyone who took
>> part in the discussion.
>> ---
>>  meson.build | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/meson.build b/meson.build
>> index 3ceaec483a39f398797a..6e9a799704ecf606b689 100644
>> --- a/meson.build
>> +++ b/meson.build
>> @@ -24,7 +24,7 @@ project(
>>version : '17.3.0-devel',
>>license : 'MIT',
>>meson_version : '>= 0.42',
>> -  default_options : ['c_std=c99', 'cpp_std=c++11']
>> +  default_options : ['buildtype=debugoptimized', 'c_std=c99', 
>> 'cpp_std=c++11']
>>  )
>>
>>  # Arguments for the preprocessor, put these in a separate array from the C 
>> and
>> --
>> Cheers,
>>   Eric
>>
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Re: [Mesa-dev] [PATCH] intel/fs: Use a pure vertical stride for large register strides

[Jason Ekstrand]

On Mon, Nov 6, 2017 at 4:10 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:

>
> On Thu, 2017-11-02 at 15:54 -0700, Jason Ekstrand wrote:
> > Register strides higher than 4 are uncommon but they can happen.  For
> > instance, if you have a 64-bit extract_u8 operation, we turn that
> > into
> > UB -> UQ MOV with a source stride of 8.  Our previous calculation
> > would
> > try to generate a stride of <32;8,8>:ub which is invalid because the
> > maximum horizontal stride is 4.  To solve this problem, we instead
> > use a
> > stride of <8;1,0>.  As noted in the comment, this does not work as a
> > destination but that's ok as very few things actually generate that
> > stride.
> >
>
> Great!
>
> > Cc: mesa-sta...@lists.freedesktop.org
> > ---
> >  src/intel/compiler/brw_fs_generator.cpp | 15 ---
> >  1 file changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/intel/compiler/brw_fs_generator.cpp
> > b/src/intel/compiler/brw_fs_generator.cpp
> > index 46f9a33..a557f80 100644
> > --- a/src/intel/compiler/brw_fs_generator.cpp
> > +++ b/src/intel/compiler/brw_fs_generator.cpp
> > @@ -90,9 +90,18 @@ brw_reg_from_fs_reg(const struct gen_device_info
> > *devinfo, fs_inst *inst,
> >*   different execution size when the number of
> > components
> >*   written to each destination GRF is not the same.
> >*/
> > - const unsigned width = MIN2(reg_width, phys_width);
> > - brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg-
> > >nr, 0);
> > - brw_reg = stride(brw_reg, width * reg->stride, width, reg-
> > >stride);
> > + if (reg->stride > 4) {
> > +/* For registers with an exceptionally large stride, we
> > use a
> > + * width of 1 and only use the vertical stride.  This
> > only works
> > + * for sources since destinations require hstride == 1.
> > + */
> > +brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr,
> > 0);
> > +brw_reg = stride(brw_reg, reg->stride, 1, 0);
>
> I think it is a good idea to add an assert like:
>
>assert(reg != >dst)
>
> in order to avoid applying this to dst.
>

We already have an assert that triggers, but this is more direct.  I'll add
it.


> With or without that change,
>
> Reviewed-by: Samuel Iglesias Gonsálvez 
>

Thanks!


> Sam
>
> > + } else {
> > +const unsigned width = MIN2(reg_width, phys_width);
> > +brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg),
> > reg->nr, 0);
> > +brw_reg = stride(brw_reg, width * reg->stride, width,
> > reg->stride);
> > + }
> >
> >   if (devinfo->gen == 7 && !devinfo->is_haswell) {
> >  /* From the IvyBridge PRM (EU Changes by Processor
> > Generation, page 13):
>
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Re: [Mesa-dev] [PATCH v3] meson: implement default driver arguments

[Dylan Baker]

Quoting Eric Engestrom (2017-11-03 16:44:11)
> On Friday, 2017-11-03 18:09:01 +, Dylan Baker wrote:
> > This allows drivers to be set by OS/arch in a sane manner.
> > 
> > v2: - set _drivers to a list of drivers instead of manually assigning
> >   each with_*
> > v3: - Use "auto" instead of "default", which matches the value of other
> >   automatically configured options.
> > - Set vulkan drivers as well
> > - Add error message if no automatic drivers are known for a given
> >   arch/OS combo
> > - use not(darwin or windows) instead of (linux or *bsd), which is
> >   probably more accurate (that way Solaris and other *nix systems
> >   aren't excluded)
> > - rename softpipe to swrast, as swrast is the actual option name
> > 
> > cc: Eric Engestrom 
> 
> Not sure about the duplicate error(), but that nitpick aside, this is:
> Reviewed-by: Eric Engestrom 

I think it's nice to users to be clear why they're getting an error.

Dylan


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Re: [Mesa-dev] [PATCH mesa 2/2] meson: only turn on Mesa's DEBUG for buildtype==debug

[Matt Turner]

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH v2 07/26] winsys/amdgpu: handle cs_add_fence_dependency for deferred/unsubmitted fences

[Marek Olšák]

On Mon, Nov 6, 2017 at 11:23 AM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> The idea is to fix the following interleaving of operations
> that can arise from deferred fences:
>
>  Thread 1 / Context 1  Thread 2 / Context 2
>    
>  f = deferred flush
>  <--- application-side synchronization --->
>fence_server_sync(f)
>...
>flush()
>  flush()
>
> We will now stall in fence_server_sync until the flush of context 1
> has completed.
>
> This scenario was unlikely to occur previously, because applications
> seem to be doing
>
>  Thread 1 / Context 1  Thread 2 / Context 2
>    
>  f = glFenceSync()
>  glFlush()
>  <--- application-side synchronization --->
>glWaitSync(f)
>
> ... and indeed they probably *have* to use this ordering to avoid
> deadlocks in the GLX model, where all GL operations conceptually
> go through a single connection to the X server. However, it's less
> clear whether applications have to do this with other WSI (i.e. EGL).
> Besides, even this sequence of GL commands can be translated into
> the Gallium-level sequence outlined above when Gallium threading
> and asynchronous flushes are used. So it makes sense to be more
> robust.
>
> As a side effect, we no longer busy-wait on submission_in_progress.
>
> We won't enable asynchronous flushes on radeon, but add a
> cs_add_fence_dependency stub anyway to document the potential
> issue.
> ---
>  src/gallium/drivers/radeon/radeon_winsys.h|  4 +++-
>  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 21 +
>  src/gallium/winsys/amdgpu/drm/amdgpu_cs.h |  9 ++---
>  src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 19 +++
>  4 files changed, 41 insertions(+), 12 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
> b/src/gallium/drivers/radeon/radeon_winsys.h
> index 2d3f646dc65..e8c486cb7f4 100644
> --- a/src/gallium/drivers/radeon/radeon_winsys.h
> +++ b/src/gallium/drivers/radeon/radeon_winsys.h
> @@ -536,21 +536,23 @@ struct radeon_winsys {
>   * \return Negative POSIX error code or 0 for success.
>   * Asynchronous submissions never return an error.
>   */
>  int (*cs_flush)(struct radeon_winsys_cs *cs,
>  unsigned flags,
>  struct pipe_fence_handle **fence);
>
>  /**
>   * Create a fence before the CS is flushed.
>   * The user must flush manually to complete the initializaton of the 
> fence.
> - * The fence must not be used before the flush.
> + *
> + * The fence must not be used for anything except \ref 
> cs_add_fence_dependency
> + * before the flush.
>   */
>  struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs 
> *cs);
>
>  /**
>   * Return true if a buffer is referenced by a command stream.
>   *
>   * \param csA command stream.
>   * \param buf   A winsys buffer.
>   */
>  bool (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
> b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> index 0450ccc3596..0628e547351 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> @@ -43,21 +43,22 @@ amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned 
> ip_type,
>  {
> struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
>
> fence->reference.count = 1;
> fence->ws = ctx->ws;
> fence->ctx = ctx;
> fence->fence.context = ctx->ctx;
> fence->fence.ip_type = ip_type;
> fence->fence.ip_instance = ip_instance;
> fence->fence.ring = ring;
> -   fence->submission_in_progress = true;
> +   util_queue_fence_init(>submitted);
> +   util_queue_fence_reset(>submitted);
> p_atomic_inc(>refcount);
> return (struct pipe_fence_handle *)fence;
>  }
>
>  static struct pipe_fence_handle *
>  amdgpu_fence_import_sync_file(struct radeon_winsys *rws, int fd)
>  {
> struct amdgpu_winsys *ws = amdgpu_winsys(rws);
> struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
>
> @@ -74,66 +75,69 @@ amdgpu_fence_import_sync_file(struct radeon_winsys *rws, 
> int fd)
>FREE(fence);
>return NULL;
> }
>
> r = amdgpu_cs_syncobj_import_sync_file(ws->dev, fence->syncobj, fd);
> if (r) {
>amdgpu_cs_destroy_syncobj(ws->dev, fence->syncobj);
>FREE(fence);
>return NULL;
> }
> +
> +   util_queue_fence_init(>submitted);
> +
> return (struct pipe_fence_handle*)fence;
>  }
>
>  static int amdgpu_fence_export_sync_file(struct radeon_winsys *rws,
>  struct pipe_fence_handle *pfence)
>  {
> struct 

Re: [Mesa-dev] [PATCH mesa 1/2] meson: standardize .so version to major.minor.patch

[Dylan Baker]

To clarify, with the one hunk in patch 2 moved to patch 1, both patches are:
Reviewed-by: Dylan Baker 

Quoting Dylan Baker (2017-11-02 16:51:18)
> I'm also not sure that it matters, but I think consistency with autotools is
> important,
> Reviewed-by: Dylan Baker 
> 
> Quoting Eric Engestrom (2017-11-02 16:42:11)
> > This `version` field defines the filename for the .so.
> > The plan .so as well as .so.$major are always symlinks to this.
> > 
> > Unless I'm mistaken, only the major is ever used, so this shouldn't, but
> > for consistency with autotools (and in case it does matter), let's
> > always have all 3 major.minor.patch components.
> > 
> > (The soname isn't affected, and is always .so.$major)
> > 
> > Signed-off-by: Eric Engestrom 
> > ---
> >  src/egl/meson.build| 2 +-
> >  src/gallium/targets/osmesa/meson.build | 2 +-
> >  src/gbm/meson.build| 2 +-
> >  src/glx/meson.build| 2 +-
> >  src/mapi/es1api/meson.build| 2 +-
> >  src/mapi/es2api/meson.build| 2 +-
> >  src/mesa/drivers/osmesa/meson.build| 2 +-
> >  7 files changed, 7 insertions(+), 7 deletions(-)
> > 
> > diff --git a/src/egl/meson.build b/src/egl/meson.build
> > index 67ca8cef92..36b1d9e41b 100644
> > --- a/src/egl/meson.build
> > +++ b/src/egl/meson.build
> > @@ -145,7 +145,7 @@ if not with_glvnd
> >egl_lib_version = '1.0.0'
> >  else
> >egl_lib_name = 'EGL_mesa'
> > -  egl_lib_version = '0'
> > +  egl_lib_version = '0.0.0'
> >files_egl += [g_egldispatchstubs_h, g_egldispatchstubs_c]
> >files_egl += files('main/eglglvnd.c', 'main/egldispatchstubs.c')
> >install_data(
> > diff --git a/src/gallium/targets/osmesa/meson.build 
> > b/src/gallium/targets/osmesa/meson.build
> > index b4b3911ffd..72f77724e4 100644
> > --- a/src/gallium/targets/osmesa/meson.build
> > +++ b/src/gallium/targets/osmesa/meson.build
> > @@ -62,7 +62,7 @@ libosmesa = shared_library(
> >  pkg.generate(
> >name : 'osmesa',
> >description : 'Mesa Off-screen Rendering Library',
> > -  version : '8',
> > +  version : '8.0.0',
> >libraries : libosmesa,
> >libraries_private : gl_priv_libs,
> >  )
> > diff --git a/src/gbm/meson.build b/src/gbm/meson.build
> > index 437896ef7f..f25f317202 100644
> > --- a/src/gbm/meson.build
> > +++ b/src/gbm/meson.build
> > @@ -57,7 +57,7 @@ libgbm = shared_library(
> >link_args : [ld_args_gc_sections],
> >link_with : [links_gbm, libloader, libmesa_util, libxmlconfig],
> >dependencies : [deps_gbm, dep_dl],
> > -  version : '1.0',
> > +  version : '1.0.0',
> >install : true,
> >  )
> >  
> > diff --git a/src/glx/meson.build b/src/glx/meson.build
> > index 573316c942..01ebc56773 100644
> > --- a/src/glx/meson.build
> > +++ b/src/glx/meson.build
> > @@ -112,7 +112,7 @@ if not with_glvnd
> >gl_lib_version = '1.2.0'
> >  else
> >gl_lib_name = 'GLX_mesa'
> > -  gl_lib_version = '0'
> > +  gl_lib_version = '0.0.0'
> >files_libglx += files(
> >  'g_glxglvnddispatchfuncs.c',
> >  'g_glxglvnddispatchindices.h',
> > diff --git a/src/mapi/es1api/meson.build b/src/mapi/es1api/meson.build
> > index 84a21cd6b7..8d95aee02f 100644
> > --- a/src/mapi/es1api/meson.build
> > +++ b/src/mapi/es1api/meson.build
> > @@ -36,7 +36,7 @@ libglesv1_cm = shared_library(
> >include_directories : [inc_src, inc_include, inc_mapi],
> >link_with : libglapi,
> >dependencies : [dep_thread, dep_libdrm, dep_m, dep_dl],
> > -  version : '1.1',
> > +  version : '1.1.0',
> >install : true,
> >  )
> >  
> > diff --git a/src/mapi/es2api/meson.build b/src/mapi/es2api/meson.build
> > index 3d6888a4b8..7e868d77b3 100644
> > --- a/src/mapi/es2api/meson.build
> > +++ b/src/mapi/es2api/meson.build
> > @@ -36,7 +36,7 @@ libgles2 = shared_library(
> >include_directories : [inc_src, inc_include, inc_mapi],
> >link_with : libglapi,
> >dependencies : [dep_thread, dep_libdrm, dep_m, dep_dl],
> > -  version : '2',
> > +  version : '2.0.0',
> >install : true,
> >  )
> >  
> > diff --git a/src/mesa/drivers/osmesa/meson.build 
> > b/src/mesa/drivers/osmesa/meson.build
> > index 407cda7e94..a406bb3c21 100644
> > --- a/src/mesa/drivers/osmesa/meson.build
> > +++ b/src/mesa/drivers/osmesa/meson.build
> > @@ -42,7 +42,7 @@ libosmesa = shared_library(
> >  pkg.generate(
> >name : 'osmesa',
> >description : 'Mesa Off-screen Rendering Library',
> > -  version : '8',
> > +  version : '8.0.0',
> >libraries : libosmesa,
> >libraries_private : gl_priv_libs,
> >  )
> > -- 
> > Cheers,
> >   Eric
> > 
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 
> 
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Re: [Mesa-dev] [PATCH mesa 2/2] meson: only turn on Mesa's DEBUG for buildtype==debug

[Eric Engestrom]

On Monday, 2017-11-06 17:19:35 +, Eric Engestrom wrote:
> Cc: Dylan Baker 
> Cc: Chad Versace 
> Signed-off-by: Eric Engestrom 
> ---
>  meson.build | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/meson.build b/meson.build
> index 6e9a799704ecf606b689..78d51b9b9b580fdc4058 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -350,7 +350,7 @@ if cc.get_id() == 'gcc' and 
> cc.version().version_compare('< 4.4.6')
>  endif
>  
>  # Define DEBUG for debug and debugoptimized builds

Oops, comments needs updating too. Amended locally.

> -if get_option('buildtype').startswith('debug')
> +if get_option('buildtype') == 'debug'
>pre_args += '-DDEBUG'
>  endif
>  
> -- 
> Cheers,
>   Eric
> 
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Re: [Mesa-dev] [PATCH mesa 1/2] meson: switch default build type to debugoptimized

[Dylan Baker]

Reviewed-by: Dylan Baker 

Quoting Eric Engestrom (2017-11-06 09:19:34)
> Cc: Dylan Baker 
> Cc: Chad Versace 
> Cc: Emil Velikov 
> Cc: Ilia Mirkin 
> Cc: Andres Rodriguez 
> Cc: Michel Dänzer 
> Cc: Matt Turner 
> Cc: Christian Schmidbauer 
> Cc: Eero Tamminen 
> Cc: Ernst Sjöstrand 
> Signed-off-by: Eric Engestrom 
> ---
> Sorry for the massive Cc-list, I wanted to include everyone who took
> part in the discussion.
> ---
>  meson.build | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/meson.build b/meson.build
> index 3ceaec483a39f398797a..6e9a799704ecf606b689 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -24,7 +24,7 @@ project(
>version : '17.3.0-devel',
>license : 'MIT',
>meson_version : '>= 0.42',
> -  default_options : ['c_std=c99', 'cpp_std=c++11']
> +  default_options : ['buildtype=debugoptimized', 'c_std=c99', 
> 'cpp_std=c++11']
>  )
>  
>  # Arguments for the preprocessor, put these in a separate array from the C 
> and
> -- 
> Cheers,
>   Eric
> 


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Re: [Mesa-dev] [PATCH mesa 1/2] meson: switch default build type to debugoptimized

[Chad Versace]

For both patches,
Reviewed-by: Chad Versace 
Tested-by: Chad Versace 


On Mon 06 Nov 2017, Eric Engestrom wrote:
> Cc: Dylan Baker 
> Cc: Chad Versace 
> Cc: Emil Velikov 
> Cc: Ilia Mirkin 
> Cc: Andres Rodriguez 
> Cc: Michel Dänzer 
> Cc: Matt Turner 
> Cc: Christian Schmidbauer 
> Cc: Eero Tamminen 
> Cc: Ernst Sjöstrand 
> Signed-off-by: Eric Engestrom 
> ---
> Sorry for the massive Cc-list, I wanted to include everyone who took
> part in the discussion.
> ---
>  meson.build | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/meson.build b/meson.build
> index 3ceaec483a39f398797a..6e9a799704ecf606b689 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -24,7 +24,7 @@ project(
>version : '17.3.0-devel',
>license : 'MIT',
>meson_version : '>= 0.42',
> -  default_options : ['c_std=c99', 'cpp_std=c++11']
> +  default_options : ['buildtype=debugoptimized', 'c_std=c99', 
> 'cpp_std=c++11']
>  )
>  
>  # Arguments for the preprocessor, put these in a separate array from the C 
> and
> -- 
> Cheers,
>   Eric
> 
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Re: [Mesa-dev] [PATCH] gallium: Guard assertions by NDEBUG instead of DEBUG

[Eric Engestrom]

On Monday, 2017-11-06 18:39:54 +0100, Michel Dänzer wrote:
> From: Michel Dänzer 
> 
> This matches the standard assert.h header.
> 
> Signed-off-by: Michel Dänzer 

Reviewed-by: Eric Engestrom 

Guess we should audit every DEBUG in the codebase to make sure the right
one is used.

> ---
>  src/gallium/auxiliary/util/u_debug.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/gallium/auxiliary/util/u_debug.h 
> b/src/gallium/auxiliary/util/u_debug.h
> index 63940b72253..d2ea89f59c1 100644
> --- a/src/gallium/auxiliary/util/u_debug.h
> +++ b/src/gallium/auxiliary/util/u_debug.h
> @@ -185,7 +185,7 @@ void _debug_assert_fail(const char *expr,
>   * For non debug builds the assert macro will expand to a no-op, so do not
>   * call functions with side effects in the assert expression.
>   */
> -#ifdef DEBUG
> +#ifndef NDEBUG
>  #define debug_assert(expr) ((expr) ? (void)0 : _debug_assert_fail(#expr, 
> __FILE__, __LINE__, __FUNCTION__))
>  #else
>  #define debug_assert(expr) (void)(0 && (expr))
> -- 
> 2.15.0
> 
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Re: [Mesa-dev] Meson's default build type

[Chad Versace]

On Mon 06 Nov 2017, Eric Engestrom wrote:
> On Monday, 2017-11-06 08:07:21 -0800, Chad Versace wrote:
> > On Thu 02 Nov 2017, Dylan Baker wrote:
> > > Quoting Matt Turner (2017-11-02 10:06:43)
> > > > On Thu, Nov 2, 2017 at 9:51 AM, Michel Dänzer  
> > > > wrote:
> > > > > FWIW, my vote is for debugoptimized: Assertions are enabled and 
> > > > > there's
> > > > > debugging information useful for bug reports, but performance should 
> > > > > be
> > > > > decent.
> > > > 
> > > > If debugoptimized turns on DEBUG, then I don't think performance will
> > > > be decent as that enables paths like nir_validate. Maybe we should
> > > > change debugoptimized to not do that. Not sure.
> > > > 
> > > > I think some of the messaging got confused -- autotools does specify
> > > > -g in the default CFLAGS, but that doesn't really mean it's a useful
> > > > debug build. -g -O2 is really a release build, with debugging symbols.
> > > 
> > > debugoptimized does turn on DEBUG. Last time I tried (which was a while 
> > > ago),
> > > if asserts are enabled but DEBUG is not mesa couldn't be compiled, as 
> > > asserts
> > > used members of structs that only exist when DEBUG is set. Maybe that's a
> > > situation that deserves being revisited.
> > 
> > I vote for debugoptimized, where debuoptimized contains CFLAGS='-g -O2'.
> 
> This is already the default behaviour on meson [1]
> 
> [1] http://mesonbuild.com/Running-Meson.html#configuring-the-source
> 
> > The user gets a build that's suitable for everyday use (-O2) and it the
> > user can submit meaningful bug reports (-g).
> > 
> > To -DDEBUG or not to -DDEBUG... Since I want to ensure that users with
> > a self-built Mesa have a Mesa that's suitable for everyday use, I think
> > the default build should *not* contain assertions that severely impact
> > performance. So I vote against -DDEBUG; or, at a minimum, we could keep
> > -DDEBUG and somehow disable the slooow assertions in debugoptimized.
> 
> assert()s are controlled by the standard NDEBUG, which is not tied to
> Mesa's DEBUG.
> 
> Mesa's autotools, having only two build types, locally defines NDEBUG
> when --enable-debug is not given, kind of tying the two together.
> Meson on the other hand uses the build option `b_ndebug` to control
> NDEBUG, which defaults to `false` (ie. "don't compile out asserts").
> 
> Mesa's DEBUG is currently enabled in Meson on both `debug` and
> `debugoptimized` builds. We could limit it to `debug` only, removing
> DEBUG code in `debugoptimized` but keeping assert()s.
> 
> Does that sound like a good middle-ground?

Thanks for explaining all that. Your proposal sounds good to me.
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Re: [Mesa-dev] [PATCH mesa 1/2] meson: switch default build type to debugoptimized

[Matt Turner]

Acked-by: Matt Turner 
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[Mesa-dev] [PATCH] gallium: Guard assertions by NDEBUG instead of DEBUG

[Michel Dänzer]

From: Michel Dänzer 

This matches the standard assert.h header.

Signed-off-by: Michel Dänzer 
---
 src/gallium/auxiliary/util/u_debug.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/util/u_debug.h 
b/src/gallium/auxiliary/util/u_debug.h
index 63940b72253..d2ea89f59c1 100644
--- a/src/gallium/auxiliary/util/u_debug.h
+++ b/src/gallium/auxiliary/util/u_debug.h
@@ -185,7 +185,7 @@ void _debug_assert_fail(const char *expr,
  * For non debug builds the assert macro will expand to a no-op, so do not
  * call functions with side effects in the assert expression.
  */
-#ifdef DEBUG
+#ifndef NDEBUG
 #define debug_assert(expr) ((expr) ? (void)0 : _debug_assert_fail(#expr, 
__FILE__, __LINE__, __FUNCTION__))
 #else
 #define debug_assert(expr) (void)(0 && (expr))
-- 
2.15.0

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[Mesa-dev] [PATCH mesa 2/2] meson: only turn on Mesa's DEBUG for buildtype==debug

[Eric Engestrom]

Cc: Dylan Baker 
Cc: Chad Versace 
Signed-off-by: Eric Engestrom 
---
 meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 6e9a799704ecf606b689..78d51b9b9b580fdc4058 100644
--- a/meson.build
+++ b/meson.build
@@ -350,7 +350,7 @@ if cc.get_id() == 'gcc' and cc.version().version_compare('< 
4.4.6')
 endif
 
 # Define DEBUG for debug and debugoptimized builds
-if get_option('buildtype').startswith('debug')
+if get_option('buildtype') == 'debug'
   pre_args += '-DDEBUG'
 endif
 
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 1/2] meson: switch default build type to debugoptimized

[Eric Engestrom]

Cc: Dylan Baker 
Cc: Chad Versace 
Cc: Emil Velikov 
Cc: Ilia Mirkin 
Cc: Andres Rodriguez 
Cc: Michel Dänzer 
Cc: Matt Turner 
Cc: Christian Schmidbauer 
Cc: Eero Tamminen 
Cc: Ernst Sjöstrand 
Signed-off-by: Eric Engestrom 
---
Sorry for the massive Cc-list, I wanted to include everyone who took
part in the discussion.
---
 meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 3ceaec483a39f398797a..6e9a799704ecf606b689 100644
--- a/meson.build
+++ b/meson.build
@@ -24,7 +24,7 @@ project(
   version : '17.3.0-devel',
   license : 'MIT',
   meson_version : '>= 0.42',
-  default_options : ['c_std=c99', 'cpp_std=c++11']
+  default_options : ['buildtype=debugoptimized', 'c_std=c99', 'cpp_std=c++11']
 )
 
 # Arguments for the preprocessor, put these in a separate array from the C and
-- 
Cheers,
  Eric

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[Mesa-dev] Couple patches for debian-experimental mesa branch

[Fabio Pedretti]

[PATCH 1/2] Remove libtxc-dxtn* recommends for S3TC
[PATCH 2/2] Rename --enable-gallium-llvm to --enable-llvm

Fabio
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Re: [Mesa-dev] Meson's default build type

[Eric Engestrom]

On Monday, 2017-11-06 08:07:21 -0800, Chad Versace wrote:
> On Thu 02 Nov 2017, Dylan Baker wrote:
> > Quoting Matt Turner (2017-11-02 10:06:43)
> > > On Thu, Nov 2, 2017 at 9:51 AM, Michel Dänzer  wrote:
> > > > FWIW, my vote is for debugoptimized: Assertions are enabled and there's
> > > > debugging information useful for bug reports, but performance should be
> > > > decent.
> > > 
> > > If debugoptimized turns on DEBUG, then I don't think performance will
> > > be decent as that enables paths like nir_validate. Maybe we should
> > > change debugoptimized to not do that. Not sure.
> > > 
> > > I think some of the messaging got confused -- autotools does specify
> > > -g in the default CFLAGS, but that doesn't really mean it's a useful
> > > debug build. -g -O2 is really a release build, with debugging symbols.
> > 
> > debugoptimized does turn on DEBUG. Last time I tried (which was a while 
> > ago),
> > if asserts are enabled but DEBUG is not mesa couldn't be compiled, as 
> > asserts
> > used members of structs that only exist when DEBUG is set. Maybe that's a
> > situation that deserves being revisited.
> 
> I vote for debugoptimized, where debuoptimized contains CFLAGS='-g -O2'.

This is already the default behaviour on meson [1]

[1] http://mesonbuild.com/Running-Meson.html#configuring-the-source

> The user gets a build that's suitable for everyday use (-O2) and it the
> user can submit meaningful bug reports (-g).
> 
> To -DDEBUG or not to -DDEBUG... Since I want to ensure that users with
> a self-built Mesa have a Mesa that's suitable for everyday use, I think
> the default build should *not* contain assertions that severely impact
> performance. So I vote against -DDEBUG; or, at a minimum, we could keep
> -DDEBUG and somehow disable the slooow assertions in debugoptimized.

assert()s are controlled by the standard NDEBUG, which is not tied to
Mesa's DEBUG.

Mesa's autotools, having only two build types, locally defines NDEBUG
when --enable-debug is not given, kind of tying the two together.
Meson on the other hand uses the build option `b_ndebug` to control
NDEBUG, which defaults to `false` (ie. "don't compile out asserts").

Mesa's DEBUG is currently enabled in Meson on both `debug` and
`debugoptimized` builds. We could limit it to `debug` only, removing
DEBUG code in `debugoptimized` but keeping assert()s.

Does that sound like a good middle-ground?
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Re: [Mesa-dev] [PATCH v3 01/10] egl: add dri2_surface_fixup() helper (v3)

[Gurchetan Singh]

This patch series was intended to:

a) de-duplicate code across various platforms.
b) do preparatory work for platform_tizen.

There was some confusion[1] on how we want to move forward with
platform_tizen.  Until we can figure that out, I suggest we drop patches
that move stuff out of platform_android in preparation for platform_tizen
[patches {1, 3, 4,  6}] for now.  I would change this suggestion if other
platforms (platform_wayland, platform_drm) start using the new
dri2_surface_* functions and advertising the associated extensions by the
end of the series, i.e EXT_buffer_age.

I think patch 5 can be it's own standalone patch in platform_android for
now.  You can also justify patch 8 if platform_surfaceless starts
using dri2_surface_get_front_image.

So in conclusion, I think we can go forward with patches {2, 5, 7, 8, 9},
with the appropriate changes.

[1] https://www.mail-archive.com/mesa-dev@lists.freedesktop.
org/msg173164.html

On Tue, Oct 24, 2017 at 2:44 PM, Gwan-gyeong Mun  wrote:

> From: "Mun, Gwan-gyeong" 
>
> To share common free outdated buffers and update size code.
> This compares width and height arguments with current egl surface
> dimension,
> if the compared surface dimension is differ, then it free local buffers and
> updates dimension.
>
> In preparation to adding of new platform which uses this helper.
>
> v2: Fixes from Eric's review:
>a) Split out series of refactor for helpers to a separate series.
>b) Add the new helper function and use them to replace the old code in
> the
>   same patch.
>
> v3: Fixes from Emil and Gurchetan's review
>   - Follow the naming convention which prevents too verbose name of
> functions.
> a) use a dri2_surface_$action_$object naming convention
> b) change a first argument type "struct dri2_egl_surface" to
> "_EGLSurface".
>
> Signed-off-by: Mun Gwan-gyeong 
> Reviewed-by: Emil Velikov 
> ---
>  src/egl/drivers/dri2/egl_dri2.c | 13 +
>  src/egl/drivers/dri2/egl_dri2.h |  3 +++
>  src/egl/drivers/dri2/platform_android.c |  8 ++--
>  3 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_
> dri2.c
> index 503450542e..238e299aed 100644
> --- a/src/egl/drivers/dri2/egl_dri2.c
> +++ b/src/egl/drivers/dri2/egl_dri2.c
> @@ -1079,6 +1079,19 @@ dri2_egl_surface_free_local_buffers(struct
> dri2_egl_surface *dri2_surf)
> }
>  }
>
> +void
> +dri2_surface_fixup(_EGLSurface *surf, int width, int height)
> +{
> +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> +
> +   /* free outdated buffers and update the surface size */
> +   if (surf->Width != width || surf->Height != height) {
> +  dri2_egl_surface_free_local_buffers(dri2_surf);
> +  surf->Width = width;
> +  surf->Height = height;
> +   }
> +}
> +
>  /**
>   * Called via eglTerminate(), drv->API.Terminate().
>   *
> diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_
> dri2.h
> index cd2487ab22..208a03d73a 100644
> --- a/src/egl/drivers/dri2/egl_dri2.h
> +++ b/src/egl/drivers/dri2/egl_dri2.h
> @@ -455,6 +455,9 @@ dri2_egl_surface_alloc_local_buffer(struct
> dri2_egl_surface *dri2_surf,
>  void
>  dri2_egl_surface_free_local_buffers(struct dri2_egl_surface *dri2_surf);
>
> +void
> +dri2_surface_fixup(_EGLSurface *surf, int width, int height);
> +
>  EGLBoolean
>  dri2_init_surface(_EGLSurface *surf, _EGLDisplay *dpy, EGLint type,
>  _EGLConfig *conf, const EGLint *attrib_list, EGLBoolean
> enable_out_fence);
> diff --git a/src/egl/drivers/dri2/platform_android.c
> b/src/egl/drivers/dri2/platform_android.c
> index e390365b8b..d00aa2 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -414,12 +414,8 @@ update_buffers(struct dri2_egl_surface *dri2_surf)
> }
>
> /* free outdated buffers and update the surface size */
> -   if (dri2_surf->base.Width != dri2_surf->buffer->width ||
> -   dri2_surf->base.Height != dri2_surf->buffer->height) {
> -  dri2_egl_surface_free_local_buffers(dri2_surf);
> -  dri2_surf->base.Width = dri2_surf->buffer->width;
> -  dri2_surf->base.Height = dri2_surf->buffer->height;
> -   }
> +   dri2_surface_fixup(_surf->base, dri2_surf->buffer->width,
> +  dri2_surf->buffer->height);
>
> return 0;
>  }
> --
> 2.14.2
>
>
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Re: [Mesa-dev] [PATCH 4/4] i965: Use PTE MOCS for all external buffers

[Lyude Paul]

Didn't danvet give you a RB'd here? As well:

Tested-by: Lyude Paul 

On Fri, 2017-11-03 at 16:17 -0700, Jason Ekstrand wrote:
> We were already using PTE for all render targets in case one happened to
> get scanned out.  However, this still wasn't 100% correct because there
> are still possibly cases where we may want to texture from an external
> buffer even though we don't know the caching mode.  This can happen, for
> instance, on buffers imported from another GPU via prime.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101691
> Cc: Kenneth Graunke 
> Cc: Chris Wilson 
> Cc: Daniel Vetter 
> Cc: Lyude Paul 
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c|  7 ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 20 +---
>  2 files changed, 17 insertions(+), 10 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 5a86af8..626bf44 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -114,14 +114,14 @@ brw_blorp_init(struct brw_context *brw)
> brw->blorp.upload_shader = brw_blorp_upload_shader;
>  }
>  
> -static uint32_t tex_mocs[] = {
> +static uint32_t wb_mocs[] = {
> [7] = GEN7_MOCS_L3,
> [8] = BDW_MOCS_WB,
> [9] = SKL_MOCS_WB,
> [10] = CNL_MOCS_WB,
>  };
>  
> -static uint32_t rb_mocs[] = {
> +static uint32_t pte_mocs[] = {
> [7] = GEN7_MOCS_L3,
> [8] = BDW_MOCS_PTE,
> [9] = SKL_MOCS_PTE,
> @@ -158,7 +158,8 @@ blorp_surf_for_miptree(struct brw_context *brw,
>.buffer = mt->bo,
>.offset = mt->offset,
>.reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
> -  .mocs = is_render_target ? rb_mocs[devinfo->gen] : tex_mocs[devinfo-
> >gen],
> +  .mocs = (is_render_target || mt->bo->external) ? pte_mocs[devinfo-
> >gen] :
> +   wb_mocs[devinfo-
> >gen],
> };
>  
> surf->aux_usage = aux_usage;
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 27c241a..f174270 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -55,20 +55,25 @@
>  #include "brw_defines.h"
>  #include "brw_wm.h"
>  
> -uint32_t tex_mocs[] = {
> +uint32_t wb_mocs[] = {
> [7] = GEN7_MOCS_L3,
> [8] = BDW_MOCS_WB,
> [9] = SKL_MOCS_WB,
> [10] = CNL_MOCS_WB,
>  };
>  
> -uint32_t rb_mocs[] = {
> +uint32_t pte_mocs[] = {
> [7] = GEN7_MOCS_L3,
> [8] = BDW_MOCS_PTE,
> [9] = SKL_MOCS_PTE,
> [10] = CNL_MOCS_PTE,
>  };
>  
> +static inline uint32_t get_tex_mocs(struct brw_bo *bo, unsigned int gen)
> +{
> + return (bo && bo->external ? pte_mocs : wb_mocs)[gen];
> +}
> +
>  static void
>  get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt,
>   GLenum target, struct isl_view *view,
> @@ -239,7 +244,7 @@ gen6_update_renderbuffer_surface(struct brw_context
> *brw,
>  
> uint32_t offset;
> brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
> -  rb_mocs[devinfo->gen],
> +  pte_mocs[devinfo->gen],
>, surf_index,
>RELOC_WRITE);
> return offset;
> @@ -586,7 +591,7 @@ brw_update_texture_surface(struct gl_context *ctx,
>   aux_usage = ISL_AUX_USAGE_NONE;
>  
>brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
> - tex_mocs[devinfo->gen],
> + get_tex_mocs(mt->bo, devinfo->gen),
>   surf_offset, surf_index,
>   0);
> }
> @@ -617,7 +622,7 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
>   .size = buffer_size,
>   .format = surface_format,
>   .stride = pitch,
> - .mocs = tex_mocs[devinfo->gen]);
> + .mocs = get_tex_mocs(bo, devinfo->gen));
>  }
>  
>  void
> @@ -1107,7 +1112,7 @@ update_renderbuffer_read_surfaces(struct brw_context
> *brw)
> aux_usage = ISL_AUX_USAGE_NONE;
>  
>  brw_emit_surface_state(brw, irb->mt, target, view, aux_usage,
> -   tex_mocs[devinfo->gen],
> +   get_tex_mocs(irb->mt->bo, devinfo->gen),
> surf_offset, surf_index,
> 0);
>  
> @@ -1599,7 +1604,8 @@ update_image_surface(struct brw_context *brw,
> view.base_array_laye
> r,
> view.array_len));
>  

Re: [Mesa-dev] [PATCH v2 04/26] util/u_queue: add util_queue_fence_wait_timeout

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Mon, Nov 6, 2017 at 11:23 AM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> v2:
> - style fixes
> - fix missing timeout handling in futex path
>
> Reviewed-by: Marek Olšák  (v1)
> ---
>  src/util/futex.h  |  9 --
>  src/util/simple_mtx.h |  2 +-
>  src/util/u_queue.c| 82 
> ++-
>  src/util/u_queue.h| 54 -
>  4 files changed, 121 insertions(+), 26 deletions(-)
>
> diff --git a/src/util/futex.h b/src/util/futex.h
> index fa42cf4cf59..330e18f03a2 100644
> --- a/src/util/futex.h
> +++ b/src/util/futex.h
> @@ -26,33 +26,36 @@
>
>  #if defined(HAVE_FUTEX)
>
>  #include 
>  #include 
>  #include 
>  #include 
>  #include 
>  #include 
>
> -static inline long sys_futex(void *addr1, int op, int val1, struct timespec 
> *timeout, void *addr2, int val3)
> +static inline long sys_futex(void *addr1, int op, int val1, const struct 
> timespec *timeout, void *addr2, int val3)
>  {
> return syscall(SYS_futex, addr1, op, val1, timeout, addr2, val3);
>  }
>
>  static inline int futex_wake(uint32_t *addr)
>  {
> return sys_futex(addr, FUTEX_WAKE, 1, NULL, NULL, 0);
>  }
>
>  static inline int futex_wake_all(uint32_t *addr)
>  {
> return sys_futex(addr, FUTEX_WAKE, INT_MAX, NULL, NULL, 0);
>  }
>
> -static inline int futex_wait(uint32_t *addr, int32_t value)
> +static inline int futex_wait(uint32_t *addr, int32_t value, const struct 
> timespec *timeout)
>  {
> -   return sys_futex(addr, FUTEX_WAIT, value, NULL, NULL, 0);
> +   /* FUTEX_WAIT_BITSET with FUTEX_BITSET_MATCH_ANY is equivalent to
> +* FUTEX_WAIT, except that it treats the timeout as absolute. */
> +   return sys_futex(addr, FUTEX_WAIT_BITSET, value, timeout, NULL,
> +FUTEX_BITSET_MATCH_ANY);
>  }
>
>  #endif
>
>  #endif /* UTIL_FUTEX_H */
> diff --git a/src/util/simple_mtx.h b/src/util/simple_mtx.h
> index 0c2602d03b6..4186a2d4d64 100644
> --- a/src/util/simple_mtx.h
> +++ b/src/util/simple_mtx.h
> @@ -72,21 +72,21 @@ simple_mtx_destroy(simple_mtx_t *mtx)
>  static inline void
>  simple_mtx_lock(simple_mtx_t *mtx)
>  {
> uint32_t c;
>
> c = __sync_val_compare_and_swap(>val, 0, 1);
> if (__builtin_expect(c != 0, 0)) {
>if (c != 2)
>   c = __sync_lock_test_and_set(>val, 2);
>while (c != 0) {
> - futex_wait(>val, 2);
> + futex_wait(>val, 2, NULL);
>   c = __sync_lock_test_and_set(>val, 2);
>}
> }
>  }
>
>  static inline void
>  simple_mtx_unlock(simple_mtx_t *mtx)
>  {
> uint32_t c;
>
> diff --git a/src/util/u_queue.c b/src/util/u_queue.c
> index 706ee8b04d9..43c28ac6ef8 100644
> --- a/src/util/u_queue.c
> +++ b/src/util/u_queue.c
> @@ -19,20 +19,23 @@
>   * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>   * USE OR OTHER DEALINGS IN THE SOFTWARE.
>   *
>   * The above copyright notice and this permission notice (including the
>   * next paragraph) shall be included in all copies or substantial portions
>   * of the Software.
>   */
>
>  #include "u_queue.h"
>
> +#include 
> +
> +#include "util/os_time.h"
>  #include "util/u_string.h"
>  #include "util/u_thread.h"
>
>  static void util_queue_killall_and_wait(struct util_queue *queue);
>
>  /
>   * Wait for all queues to assert idle when exit() is called.
>   *
>   * Otherwise, C++ static variable destructors can be called while threads
>   * are using the static variables.
> @@ -84,39 +87,116 @@ remove_from_atexit_list(struct util_queue *queue)
>   break;
>}
> }
> mtx_unlock(_mutex);
>  }
>
>  /
>   * util_queue_fence
>   */
>
> +#ifdef UTIL_QUEUE_FENCE_FUTEX
> +static bool
> +do_futex_fence_wait(struct util_queue_fence *fence,
> +bool timeout, int64_t abs_timeout)
> +{
> +   uint32_t v = fence->val;
> +   struct timespec ts;
> +   ts.tv_sec = abs_timeout / (1000*1000*1000);
> +   ts.tv_nsec = abs_timeout % (1000*1000*1000);
> +
> +   while (v != 0) {
> +  if (v != 2) {
> + v = p_atomic_cmpxchg(>val, 1, 2);
> + if (v == 0)
> +return true;
> +  }
> +
> +  int r = futex_wait(>val, 2, timeout ?  : NULL);
> +  if (timeout && r < 0) {
> + if (errno == -ETIMEDOUT)
> +return false;
> +  }
> +
> +  v = fence->val;
> +   }
> +
> +   return true;
> +}
> +
> +void
> +_util_queue_fence_wait(struct util_queue_fence *fence)
> +{
> +   do_futex_fence_wait(fence, false, 0);
> +}
> +
> +bool
> +_util_queue_fence_wait_timeout(struct util_queue_fence *fence,
> +   int64_t abs_timeout)
> +{
> +   return do_futex_fence_wait(fence, true, abs_timeout);
> +}
> +
> +#endif
> +
>  #ifdef 

Re: [Mesa-dev] [PATCH] automake: include git_sha1.h.in in release tarball

[Eric Engestrom]

On Monday, 2017-11-06 16:44:40 +0100, Juan A. Suarez Romero wrote:
> Fixes:
> 
> make[2]: Leaving directory '/home/local/mesa/mesa-17.4.0-devel/_build/sub/src'
> make[2]: *** No rule to make target '../../../src/git_sha1.h.in', needed by 
> 'git_sha1.h'.  Stop.
> Makefile:660: recipe for target 'all-recursive' failed
> 
> Signed-off-by: Juan A. Suarez Romero 

Oops :(

Fixes: 16be271c6ee618e79c7d "git_sha1_gen: use git_sha1.h.in on all build 
systems"
Reviewed-by: Eric Engestrom 

Thanks!

> ---
>  src/Makefile.am | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/Makefile.am b/src/Makefile.am
> index 1de4fca6a12..22973b14bc7 100644
> --- a/src/Makefile.am
> +++ b/src/Makefile.am
> @@ -26,7 +26,7 @@ git_sha1.h: $(top_srcdir)/src/git_sha1.h.in
>  
>  BUILT_SOURCES = git_sha1.h
>  CLEANFILES = $(BUILT_SOURCES)
> -EXTRA_DIST =
> +EXTRA_DIST = git_sha1.h.in
>  
>  SUBDIRS = . gtest util mapi/glapi/gen mapi
>  
> -- 
> 2.13.6
> 
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Re: [Mesa-dev] [PATCH 1/4] intel/blorp: Use mocs.tex for depth stencil

[Jason Ekstrand]

On Mon, Nov 6, 2017 at 12:56 AM, Pohjolainen, Topi <
topi.pohjolai...@gmail.com> wrote:

> On Fri, Nov 03, 2017 at 04:17:31PM -0700, Jason Ekstrand wrote:
> > ---
> >  src/intel/blorp/blorp_genX_exec.h | 6 +-
> >  1 file changed, 1 insertion(+), 5 deletions(-)
> >
> > diff --git a/src/intel/blorp/blorp_genX_exec.h
> b/src/intel/blorp/blorp_genX_exec.h
> > index 5389262..ccbfe51 100644
> > --- a/src/intel/blorp/blorp_genX_exec.h
> > +++ b/src/intel/blorp/blorp_genX_exec.h
> > @@ -1364,11 +1364,7 @@ blorp_emit_depth_stencil_config(struct
> blorp_batch *batch,
> >return;
> >
> > struct isl_depth_stencil_hiz_emit_info info = {
> > -#if GEN_GEN >= 7
> > -  .mocs = 1, /* GEN7_MOCS_L3 */
> > -#else
> > -  .mocs = 0,
> > -#endif
> > +  .mocs = batch->blorp->mocs.tex,
>
> Need to ask some questions here:
>
> It looks that the old value "1" was invalid for gen8+, how did that work?
>

I have no idea. :)


> Looking at brw_blorp_init(), we now start supplying *_MOCS_WB for gen8+.
> Does
> that work also for HIZ ops or do we need mocs::rb?
>

I looked at gen8_depth_state.c to make this choice.  There, we we use
MOCS_WB for gen8+.
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Re: [Mesa-dev] [PATCH] spirv: Use correct type for sampled images

[Jason Ekstrand]

On Mon, Nov 6, 2017 at 2:37 AM, Alex Smith 
wrote:

> We should use the result type of the OpSampledImage opcode, rather than
> the type of the underlying image/samplers.
>
> This resolves an issue when using separate images and shadow samplers
> with glslang. Example:
>
> layout (...) uniform samplerShadow s0;
> layout (...) uniform texture2D res0;
> ...
> float result = textureLod(sampler2DShadow(res0, s0), uv, 0);
>
> For this, for the combined OpSampledImage, the type of the base image
> was being used (which does not have the Depth flag set, whereas the
> result type does), therefore it was not being recognised as a shadow
> sampler. This led to the wrong LLVM intrinsics being emitted by RADV.
>

Reviewed-by: Jason Ekstrand 


> Signed-off-by: Alex Smith 
> Cc: "17.2 17.3" 
> ---
>  src/compiler/spirv/spirv_to_nir.c  | 10 --
>  src/compiler/spirv/vtn_private.h   |  1 +
>  src/compiler/spirv/vtn_variables.c |  1 +
>  3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/src/compiler/spirv/spirv_to_nir.c
> b/src/compiler/spirv/spirv_to_nir.c
> index 6825e0d6a8..93a515d731 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -1490,6 +1490,8 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp
> opcode,
>struct vtn_value *val =
>   vtn_push_value(b, w[2], vtn_value_type_sampled_image);
>val->sampled_image = ralloc(b, struct vtn_sampled_image);
> +  val->sampled_image->type =
> + vtn_value(b, w[1], vtn_value_type_type)->type;
>val->sampled_image->image =
>   vtn_value(b, w[3], vtn_value_type_pointer)->pointer;
>val->sampled_image->sampler =
> @@ -1516,16 +1518,12 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp
> opcode,
>sampled = *sampled_val->sampled_image;
> } else {
>assert(sampled_val->value_type == vtn_value_type_pointer);
> +  sampled.type = sampled_val->pointer->type;
>sampled.image = NULL;
>sampled.sampler = sampled_val->pointer;
> }
>
> -   const struct glsl_type *image_type;
> -   if (sampled.image) {
> -  image_type = sampled.image->var->var->interface_type;
> -   } else {
> -  image_type = sampled.sampler->var->var->interface_type;
> -   }
> +   const struct glsl_type *image_type = sampled.type->type;
> const enum glsl_sampler_dim sampler_dim = glsl_get_sampler_dim(image_
> type);
> const bool is_array = glsl_sampler_type_is_array(image_type);
> const bool is_shadow = glsl_sampler_type_is_shadow(image_type);
> diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_
> private.h
> index 84584620fc..6b4645acc8 100644
> --- a/src/compiler/spirv/vtn_private.h
> +++ b/src/compiler/spirv/vtn_private.h
> @@ -411,6 +411,7 @@ struct vtn_image_pointer {
>  };
>
>  struct vtn_sampled_image {
> +   struct vtn_type *type;
> struct vtn_pointer *image; /* Image or array of images */
> struct vtn_pointer *sampler; /* Sampler */
>  };
> diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_
> variables.c
> index 1cf9d597cf..9a69b4f6fc 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1805,6 +1805,7 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp
> opcode,
>   struct vtn_value *val =
>  vtn_push_value(b, w[2], vtn_value_type_sampled_image);
>   val->sampled_image = ralloc(b, struct vtn_sampled_image);
> + val->sampled_image->type = base_val->sampled_image->type;
>   val->sampled_image->image =
>  vtn_pointer_dereference(b, base_val->sampled_image->image,
> chain);
>   val->sampled_image->sampler = base_val->sampled_image->sampler;
> --
> 2.13.6
>
>
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