[Mesa-dev] [PATCH 16/16] src/intel/tools: add BatchbufferLogger to meson build system

[kevin . rogovin]

From: Kevin Rogovin 

Signed-off-by: Kevin Rogovin 
---
 meson_options.txt   |  6 
 src/intel/tools/meson.build | 71 +
 2 files changed, 77 insertions(+)

diff --git a/meson_options.txt b/meson_options.txt
index 39b137cbea..f6690c5e8e 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -261,3 +261,9 @@ option(
   choices : ['8', '16', '32'],
   description : 'Number of channel bits for OSMesa.'
 )
+option(
+  'build-intel-tools',
+  type : 'boolean',
+  value : false,
+  description : 'if true, then build intel tools.'
+)
diff --git a/src/intel/tools/meson.build b/src/intel/tools/meson.build
index 1996d5208f..e82cbedf58 100644
--- a/src/intel/tools/meson.build
+++ b/src/intel/tools/meson.build
@@ -18,6 +18,8 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
+build_intel_tools = get_option('build-intel-tools')
+
 aubinator = executable(
   'aubinator',
   files('aubinator.c', 'disasm.c', 'gen_disasm.h', 'intel_aub.h'),
@@ -37,3 +39,72 @@ aubinator_error_decode = executable(
   c_args : [c_vis_args, no_override_init_args],
   build_by_default : false,
 )
+
+i965_batchbuffer_logger = shared_library(
+  'i965_batchbuffer_logger',
+  files('i965_batchbuffer_logger.cpp', 'disasm.c', 'gen_disasm.h'),
+  dependencies : [dep_zlib, dep_thread],
+  include_directories : [inc_common, inc_intel],
+  link_with : [libintel_common, libintel_compiler, libmesa_util, libnir, 
libisl],
+  cpp_args : ['-std=c++11'],
+  build_by_default : build_intel_tools,
+  install : build_intel_tools,
+)
+
+i965_batchbuffer_dump_show = executable(
+  'i965_batchbuffer_dump_show',
+  files('i965_batchbuffer_dump_show.c'),
+  include_directories : [inc_common, inc_intel],
+  c_args : [],
+  build_by_default : build_intel_tools,
+  install : build_intel_tools,
+)
+
+i965_batchbuffer_dump_show_xml = executable(
+  'i965_batchbuffer_dump_show_xml',
+  files('i965_batchbuffer_dump_show_xml.cpp'),
+  include_directories : [inc_common, inc_intel],
+  cpp_args : [],
+  build_by_default : build_intel_tools,
+  install : build_intel_tools,
+)
+
+i965_batchbuffer_dump_show_json = executable(
+  'i965_batchbuffer_dump_show_json',
+  files('i965_batchbuffer_dump_show_json.cpp'),
+  include_directories : [inc_common, inc_intel],
+  cpp_args : [],
+  build_by_default : build_intel_tools,
+  install : build_intel_tools,
+)
+
+gen_shader_disassembler = executable(
+  'gen_shader_disassembler',
+  files('gen_shader_disassembler.c', 'disasm.c'),
+  dependencies : [dep_thread],
+  include_directories : [inc_common, inc_intel],
+  link_with : [libintel_common, libintel_compiler, libmesa_util],
+  cpp_args : [],
+  build_by_default : build_intel_tools,
+  install : build_intel_tools,
+)
+
+libdir_value = join_paths(get_option('prefix'), get_option('libdir'))
+sed_replace_string = 's,[@]libdir[@],' + libdir_value + ',g'
+i965_batchbuffer_logger_sh = custom_target(
+  'i965_batchbuffer_logger_sh',
+  input : 'i965_batchbuffer_logger_sh.in',
+  output : 'i965_batchbuffer_logger_sh',
+  command : ['sed', '-e', sed_replace_string, '@INPUT@'],
+  capture : true,
+  build_by_default : build_intel_tools,
+  install : build_intel_tools,
+  install_dir : get_option('bindir'),
+)
+
+if build_intel_tools
+  i965_batchbuffer_logger_headers = install_headers(
+'i965_batchbuffer_logger_app.h',
+'i965_batchbuffer_logger_output.h'
+  )
+endif
-- 
2.15.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 00/25] Initial gl_spirv and spirv_extensions support in Mesa and i965

[Eduardo Lima Mitev]

On 12/12/2017 03:01 AM, Ian Romanick wrote:
> Any chance you could push an updated branch to your github? :)

Yes, sure. I was meant to send the v3 series already yesterday.

I just pushed the latest version of this series
to.

And the full branch to
.

I'm will send a v3 soon, after I sort out the last review comment.

Eduardo

> On 11/30/2017 09:28 AM, Eduardo Lima Mitev wrote:
>> Hello,
>>
>> This is the second version of the series providing initial support for 
>> ARB_gl_spirv and ARB_spirv_extensions in Mesa and i965.
>>
>> First version of the series can be found at 
>> .
>>
>> In this series we hope we have addressed all issues detected during the 
>> initial review. Thank you all who participated!
>>
>> Taking the nitpicks and minor fixes apart, most important changes compared 
>> to the first version are:
>>
>> * A dedicated 'spirv' flag was removed from gl_shader struct. Now we use the 
>> nulness of 'spirv_data' member for the same purpose.
>>
>> * The per-program 'spirv' flag was moved out of this series, but will likely 
>> be re-introduced in the next delivery, because it will become necessary.
>>
>> * We enforce one SPIR-V shader per stage, and fail linking if this condition 
>> is not met.
>>
>> * 'SpirVCapabilities' struct of GL context constants is no longer a pointer 
>> but a static struct.
>>
>> As usual, a tree of this series can be found at 
>> .
>>
>> A tree of the larger WIP branch from which this series is taken: 
>> .
>>
>> Thanks in advance for the reviews!
>>
>> cheers,
>> Eduardo
>>
>> Alejandro Piñeiro (9):
>>   spirv_extensions: rename nir_spirv_supported_extensions
>>   mesa: move nir_spirv_supported_capabilities definition
>>   i965: initialize SPIR-V capabilities
>>   spirv_extensions: add GL_ARB_spirv_extensions boilerplate
>>   spirv_extensions: add list of extensions and to_string method
>>   spirv_extensions: define spirv_extensions_supported
>>   spirv_extensions: add spirv_supported_extensions on gl_constants
>>   spirv_extensions: i965: initialize SPIR-V extensions
>>   nir/spirv: add gl_spirv_validation method
>>
>> Eduardo Lima Mitev (8):
>>   mesa/glspirv: Add struct gl_shader_spirv_data
>>   mesa/glspirv: Add a _mesa_spirv_link_shaders() placeholder
>>   mesa/program: Link SPIR-V shaders using the SPIR-V code-path
>>   mesa: Add a reference to gl_shader_spirv_data to gl_linked_shader
>>   mesa/glspirv: Create gl_linked_shader objects for a SPIR-V program
>>   mesa/glspirv: Add a _mesa_spirv_to_nir() function
>>   i965: Call spirv_to_nir() instead of glsl_to_nir() for SPIR-V shaders
>>   i965: Don't call process_glsl_ir() for SPIR-V shaders
>>
>> Neil Roberts (1):
>>   mesa: Add boilerplate for the GL 4.6 alias of glSpecializeShaderARB
>>
>> Nicolai Hähnle (7):
>>   mesa: add GL_ARB_gl_spirv boilerplate
>>   mesa/glspirv: Add struct gl_spirv_module
>>   mesa: implement SPIR-V loading in glShaderBinary
>>   mesa/shaderapi: add a getter for GL_SPIR_V_BINARY_ARB
>>   mesa: refuse to compile SPIR-V shaders or link mixed shaders
>>   mesa: add gl_constants::SpirVCapabilities
>>   mesa: Implement glSpecializeShaderARB
>>
>>  src/amd/vulkan/radv_shader.c|   4 +-
>>  src/compiler/Makefile.sources   |   2 +
>>  src/compiler/spirv/nir_spirv.h  |  21 +-
>>  src/compiler/spirv/spirv_extensions.c   |  77 +++
>>  src/compiler/spirv/spirv_extensions.h   |  63 ++
>>  src/compiler/spirv/spirv_to_nir.c   | 160 +-
>>  src/compiler/spirv/vtn_private.h|   2 +-
>>  src/intel/vulkan/anv_pipeline.c |   4 +-
>>  src/mapi/glapi/gen/ARB_gl_spirv.xml |  21 ++
>>  src/mapi/glapi/gen/ARB_spirv_extensions.xml |  13 ++
>>  src/mapi/glapi/gen/GL4x.xml |  11 +
>>  src/mapi/glapi/gen/Makefile.am  |   2 +
>>  src/mapi/glapi/gen/gl_API.xml   |   8 +
>>  src/mapi/glapi/gen/gl_genexec.py|   1 +
>>  src/mapi/glapi/gen/meson.build  |   2 +
>>  src/mesa/Makefile.sources   |   4 +
>>  src/mesa/drivers/dri/i965/brw_context.c |  26 +++
>>  src/mesa/drivers/dri/i965/brw_link.cpp  |   3 +-
>>  src/mesa/drivers/dri/i965/brw_program.c |  14 +-
>>  src/mesa/main/context.c |   2 +
>>  src/mesa/main/extensions_table.h|   2 +
>>  src/mesa/main/get.c |   7 +
>>  src/mesa/main/get_hash_params.py|   3 +
>>  src/mesa/main/getstring.c   |  12 +
>>  src/mesa/main/glspirv.c | 331 
>> 
>>  src/mesa/main/glspirv.h | 108 +
>>  src/mesa/main/mtyp

[Mesa-dev] [PATCH 15/16] intel/tools: add command line GEN shader disassembler tool

[kevin . rogovin]

From: Kevin Rogovin 

Signed-off-by: Kevin Rogovin 
---
 src/intel/Makefile.tools.am   |  21 ++-
 src/intel/tools/.gitignore|   1 +
 src/intel/tools/gen_shader_disassembler.c | 213 ++
 3 files changed, 234 insertions(+), 1 deletion(-)
 create mode 100644 src/intel/tools/gen_shader_disassembler.c

diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index a86e76653b..1ccf5a35cc 100644
--- a/src/intel/Makefile.tools.am
+++ b/src/intel/Makefile.tools.am
@@ -32,7 +32,8 @@ intellib_LTLIBRARIES = \
 
 intelbin_PROGRAMS = tools/i965_batchbuffer_dump_show \
tools/i965_batchbuffer_dump_show_xml \
-   tools/i965_batchbuffer_dump_show_json
+   tools/i965_batchbuffer_dump_show_json \
+   tools/gen_shader_disassembler
 
 intelbin_SCRIPTS = tools/i965_batchbuffer_logger_sh
 CLEANFILES += $(intelbin_SCRIPTS)
@@ -111,3 +112,21 @@ tools_i965_batchbuffer_dump_show_xml_SOURCES = \
 
 tools_i965_batchbuffer_dump_show_json_SOURCES = \
tools/i965_batchbuffer_dump_show_json.cpp
+
+tools_gen_shader_disassembler_SOURCES = \
+   tools/gen_shader_disassembler.c \
+   tools/disasm.c \
+   tools/gen_disasm.h
+
+tools_gen_shader_disassembler_LDADD = \
+   common/libintel_common.la \
+   compiler/libintel_compiler.la \
+   $(top_builddir)/src/util/libmesautil.la \
+   $(PTHREAD_LIBS) \
+   $(EXPAT_LIBS) \
+   $(ZLIB_LIBS)
+
+tools_gen_shader_disassembler_CFLAGS = \
+   $(AM_CFLAGS) \
+   $(EXPAT_CFLAGS) \
+   $(ZLIB_CFLAGS)
diff --git a/src/intel/tools/.gitignore b/src/intel/tools/.gitignore
index ea4dc23c20..e9b22c89aa 100644
--- a/src/intel/tools/.gitignore
+++ b/src/intel/tools/.gitignore
@@ -4,3 +4,4 @@
 /i965_batchbuffer_dump_show
 /i965_batchbuffer_dump_show_xml
 /i965_batchbuffer_dump_show_json
+/gen_shader_disassembler
diff --git a/src/intel/tools/gen_shader_disassembler.c 
b/src/intel/tools/gen_shader_disassembler.c
new file mode 100644
index 00..070c588d54
--- /dev/null
+++ b/src/intel/tools/gen_shader_disassembler.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "compiler/brw_inst.h"
+#include "compiler/brw_eu.h"
+
+static void
+print_opcodes(const void *data, int data_sz,
+  struct gen_device_info *devinfo,
+  bool print_offsets)
+{
+   for (int offset = 0; offset < data_sz;) {
+  const brw_inst *insn = data + offset;
+  bool compacted;
+  brw_inst uncompacted;
+  enum opcode opcode;
+  const struct opcode_desc *desc;
+
+  if (print_offsets) {
+ printf("0x%08x: ", offset);
+  }
+
+  compacted = brw_inst_cmpt_control(devinfo, insn);
+  if (compacted) {
+ brw_compact_inst *compacted_insn = (brw_compact_inst *)insn;
+ brw_uncompact_instruction(devinfo, &uncompacted, compacted_insn);
+ insn = &uncompacted;
+ offset += 8;
+  } else {
+ offset += 16;
+  }
+
+  opcode = brw_inst_opcode(devinfo, insn);
+  desc = brw_opcode_desc(devinfo, opcode);
+  if (desc) {
+ printf("(0x%08x) %s", opcode, desc->name);
+  } else {
+ printf("(0x%08x) UnknownOpcode", opcode);
+  }
+
+  if (compacted) {
+ printf(" {compacted}");
+  }
+
+  printf("\n");
+   }
+}
+
+static void
+print_disassembly(const void *data, int data_sz,
+  struct gen_device_info *devinfo,
+  bool print_offsets)
+{
+   struct disasm_info *disasm_info = disasm_initialize(devinfo, NULL);
+   disasm_new_inst_group(disasm_info, 0);
+   disasm_new_inst_group(disasm_info, data_sz);
+
+   brw_validate_instructions(devinfo, data, 0, data_sz, disasm_info);
+
+   foreach_list_typed_safe(struct inst_group, group, link,
+   

[Mesa-dev] [PATCH 14/16] intel/tools/BatchbufferLogger (output-json): add json outputter

[kevin . rogovin]

From: Kevin Rogovin 

Signed-off-by: Kevin Rogovin 
---
 src/intel/Makefile.tools.am|   6 +-
 src/intel/tools/.gitignore |   1 +
 .../tools/i965_batchbuffer_dump_show_json.cpp  | 253 +
 3 files changed, 259 insertions(+), 1 deletion(-)
 create mode 100644 src/intel/tools/i965_batchbuffer_dump_show_json.cpp

diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index 1c44d92d60..a86e76653b 100644
--- a/src/intel/Makefile.tools.am
+++ b/src/intel/Makefile.tools.am
@@ -31,7 +31,8 @@ intellib_LTLIBRARIES = \
tools/libi965_batchbuffer_logger.la
 
 intelbin_PROGRAMS = tools/i965_batchbuffer_dump_show \
-   tools/i965_batchbuffer_dump_show_xml
+   tools/i965_batchbuffer_dump_show_xml \
+   tools/i965_batchbuffer_dump_show_json
 
 intelbin_SCRIPTS = tools/i965_batchbuffer_logger_sh
 CLEANFILES += $(intelbin_SCRIPTS)
@@ -107,3 +108,6 @@ tools_i965_batchbuffer_dump_show_SOURCES = \
 
 tools_i965_batchbuffer_dump_show_xml_SOURCES = \
tools/i965_batchbuffer_dump_show_xml.cpp
+
+tools_i965_batchbuffer_dump_show_json_SOURCES = \
+   tools/i965_batchbuffer_dump_show_json.cpp
diff --git a/src/intel/tools/.gitignore b/src/intel/tools/.gitignore
index 7180e4ba4b..ea4dc23c20 100644
--- a/src/intel/tools/.gitignore
+++ b/src/intel/tools/.gitignore
@@ -3,3 +3,4 @@
 /i965_batchbuffer_logger_sh
 /i965_batchbuffer_dump_show
 /i965_batchbuffer_dump_show_xml
+/i965_batchbuffer_dump_show_json
diff --git a/src/intel/tools/i965_batchbuffer_dump_show_json.cpp 
b/src/intel/tools/i965_batchbuffer_dump_show_json.cpp
new file mode 100644
index 00..81d5ca66e7
--- /dev/null
+++ b/src/intel/tools/i965_batchbuffer_dump_show_json.cpp
@@ -0,0 +1,253 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "tools/i965_batchbuffer_logger_output.h"
+
+static
+std::string
+json_name_from_file(unsigned int len, std::FILE *pfile)
+{
+   std::string return_value;
+   unsigned int i;
+   char c;
+
+   for(i = 0; i < len; ++i) {
+  if (std::fread(&c, sizeof(char), 1, pfile) != sizeof(char)) {
+ break;
+  }
+  if(c != '\n') {
+ return_value.push_back(c);
+  }
+   }
+
+   return return_value;
+}
+
+static
+std::string
+json_block_name_from_file(const struct i965_batchbuffer_logger_header *hdr,
+  std::FILE *pfile)
+{
+   std::ostringstream return_value;
+
+   return_value << json_name_from_file(hdr->name_length, pfile);
+   if (hdr->value_length > 0) {
+  return_value << ":" << json_name_from_file(hdr->value_length, pfile);
+   }
+
+   return return_value.str();
+}
+
+static
+void
+json_print_value_line(std::vector::const_iterator begin,
+  std::vector::const_iterator end)
+{
+   for(; begin != end; ++begin) {
+  switch(*begin) {
+  case '\t':
+ std::cout << "\\t";
+ break;
+  case '\"':
+ std::cout << "\\\"";
+ break;
+  case '\\':
+ /* This is silly but required; apirtace will place control
+  * character codes (sometimes) within string values (typically
+  * from shader sources). So for example if a shader source
+  * has (within a comment) something like "Famous"
+  * then the detailed function value will have then \"Famour\"
+  * within its string value. The below silly block of code
+  * just checks if there is a non-white character and if so,
+  * just assume that the \ is a control code.
+  */
+ if (begin != end) {
+++begin;
+if(isspace(*begin)) {
+   std::cout << "\\";
+} else {
+   std::cout << "\\" << *begin;
+}
+ } else {
+

[Mesa-dev] [PATCH 12/16] intel/tools/BatchbufferLogger (txt-output): example txt dumper

[kevin . rogovin]

From: Kevin Rogovin 

Signed-off-by: Kevin Rogovin 
---
 src/intel/Makefile.tools.am  |   5 +
 src/intel/tools/.gitignore   |   1 +
 src/intel/tools/i965_batchbuffer_dump_show.c | 135 +++
 3 files changed, 141 insertions(+)
 create mode 100644 src/intel/tools/i965_batchbuffer_dump_show.c

diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index f5eda31a5c..2c36649f89 100644
--- a/src/intel/Makefile.tools.am
+++ b/src/intel/Makefile.tools.am
@@ -30,6 +30,8 @@ noinst_PROGRAMS += \
 intellib_LTLIBRARIES = \
tools/libi965_batchbuffer_logger.la
 
+intelbin_PROGRAMS = tools/i965_batchbuffer_dump_show
+
 intelbin_SCRIPTS = tools/i965_batchbuffer_logger_sh
 CLEANFILES += $(intelbin_SCRIPTS)
 
@@ -98,3 +100,6 @@ tools_libi965_batchbuffer_logger_la_LDFLAGS = \
 intel_sed_prefix_vars = sed -e 's,[@]libdir[@],$(intellibdir),g'
 tools/i965_batchbuffer_logger_sh: tools/i965_batchbuffer_logger_sh.in
$(intel_sed_prefix_vars) < tools/i965_batchbuffer_logger_sh.in > 
tools/i965_batchbuffer_logger_sh
+
+tools_i965_batchbuffer_dump_show_SOURCES = \
+   tools/i965_batchbuffer_dump_show.c
diff --git a/src/intel/tools/.gitignore b/src/intel/tools/.gitignore
index fa9bf70808..7d95bcdf3a 100644
--- a/src/intel/tools/.gitignore
+++ b/src/intel/tools/.gitignore
@@ -1,3 +1,4 @@
 /aubinator
 /aubinator_error_decode
 /i965_batchbuffer_logger_sh
+/i965_batchbuffer_dump_show
diff --git a/src/intel/tools/i965_batchbuffer_dump_show.c 
b/src/intel/tools/i965_batchbuffer_dump_show.c
new file mode 100644
index 00..e69ab47edc
--- /dev/null
+++ b/src/intel/tools/i965_batchbuffer_dump_show.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "tools/i965_batchbuffer_logger_output.h"
+
+static
+void
+print_tabs(int l)
+{
+   for(int i = 0; i < l; ++i) {
+  printf("\t");
+   }
+}
+
+static
+void
+print_instrumentation_message(int block_level,
+  const struct i965_batchbuffer_logger_header *hdr,
+  FILE *pfile)
+{
+   bool line_start;
+   uint32_t i;
+   char c = 0;
+   size_t num_read;
+
+   /* assume name has no EOLs */
+   print_tabs(block_level);
+   for (i = 0; !feof(pfile) && i < hdr->name_length; ++i) {
+  num_read = fread(&c, sizeof(c), 1, pfile);
+  if (num_read != 1)
+ return;
+  printf("%c", c);
+   }
+
+   if (hdr->value_length > 0) {
+  printf(" : ");
+   }
+
+   /* print the value (if there is one). */
+   for (i = 0, line_start = false; !feof(pfile) && i < hdr->value_length; ++i) 
{
+  num_read = fread(&c, sizeof(c), 1, pfile);
+
+  if (num_read != 1)
+ break;
+
+  if (line_start) {
+ print_tabs(block_level);
+  }
+
+  printf("%c", c);
+  line_start = (c == '\n');
+   }
+
+   if (c != '\n') {
+  printf("\n");
+   }
+}
+
+
+int
+main(int argc, char **argv)
+{
+   FILE *pfile;
+   int block_level = 0;
+
+   if (argc != 2) {
+  return -1;
+   }
+
+   pfile = fopen(argv[1], "r");
+   if (pfile == NULL) {
+  return -1;
+   }
+
+   while (!feof(pfile)) {
+  struct i965_batchbuffer_logger_header hdr;
+  size_t num_read;
+
+  num_read = fread(&hdr, sizeof(hdr), 1, pfile);
+  if (num_read != 1)
+ break;
+
+  switch(hdr.type) {
+ case I965_BATCHBUFFER_LOGGER_MESSAGE_BLOCK_BEGIN: {
+print_instrumentation_message(block_level, &hdr, pfile);
+++block_level;
+ }
+ break;
+
+ case I965_BATCHBUFFER_LOGGER_MESSAGE_BLOCK_END: {
+--block_level;
+if (block_level < 0) {
+   fprintf(stderr, "Warning: negative block level encountered\n");
+}
+ }
+ break;
+
+ case I965_BATCHBUFFER_LOGGER_MESS

[Mesa-dev] [PATCH 09/16] intel/compiler: add print_offsets argument to brw_disassemble()

[kevin . rogovin]

From: Kevin Rogovin 

Signed-off-by: Kevin Rogovin 
---
 src/intel/compiler/brw_compile_clip.c | 4 +++-
 src/intel/compiler/brw_compile_sf.c   | 4 +++-
 src/intel/compiler/brw_disasm_info.c  | 4 +++-
 src/intel/compiler/brw_eu.c   | 5 +++--
 src/intel/compiler/brw_eu.h   | 3 ++-
 src/intel/tools/disasm.c  | 2 +-
 src/mesa/drivers/dri/i965/brw_ff_gs.c | 3 ++-
 src/mesa/drivers/dri/i965/brw_program_cache.c | 4 +++-
 8 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/src/intel/compiler/brw_compile_clip.c 
b/src/intel/compiler/brw_compile_clip.c
index c04d1a8277..d37a7d607e 100644
--- a/src/intel/compiler/brw_compile_clip.c
+++ b/src/intel/compiler/brw_compile_clip.c
@@ -88,7 +88,9 @@ brw_compile_clip(const struct brw_compiler *compiler,
if (unlikely(INTEL_DEBUG & DEBUG_CLIP)) {
   fprintf(stderr, "clip:\n");
   brw_disassemble(compiler->devinfo,
-  program, 0, *final_assembly_size, stderr);
+  program, 0, *final_assembly_size,
+  INTEL_DEBUG & DEBUG_PRINT_OFFSETS,
+  stderr);
   fprintf(stderr, "\n");
}
 
diff --git a/src/intel/compiler/brw_compile_sf.c 
b/src/intel/compiler/brw_compile_sf.c
index 91e8a6da6c..8294242f30 100644
--- a/src/intel/compiler/brw_compile_sf.c
+++ b/src/intel/compiler/brw_compile_sf.c
@@ -871,7 +871,9 @@ brw_compile_sf(const struct brw_compiler *compiler,
if (unlikely(INTEL_DEBUG & DEBUG_SF)) {
   fprintf(stderr, "sf:\n");
   brw_disassemble(compiler->devinfo,
-  program, 0, *final_assembly_size, stderr);
+  program, 0, *final_assembly_size,
+  INTEL_DEBUG & DEBUG_PRINT_OFFSETS,
+  stderr);
   fprintf(stderr, "\n");
}
 
diff --git a/src/intel/compiler/brw_disasm_info.c 
b/src/intel/compiler/brw_disasm_info.c
index 3db79ede70..baeb3271a9 100644
--- a/src/intel/compiler/brw_disasm_info.c
+++ b/src/intel/compiler/brw_disasm_info.c
@@ -72,7 +72,9 @@ dump_assembly(void *assembly, struct disasm_info *disasm)
 fprintf(stderr, "   %s\n", last_annotation_string);
   }
 
-  brw_disassemble(devinfo, assembly, start_offset, end_offset, stderr);
+  brw_disassemble(devinfo, assembly, start_offset, end_offset,
+  INTEL_DEBUG & DEBUG_PRINT_OFFSETS,
+  stderr);
 
   if (group->error) {
  fputs(group->error, stderr);
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index bc297a21b3..48ad82edfc 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -338,7 +338,8 @@ const unsigned *brw_get_program( struct brw_codegen *p,
 
 void
 brw_disassemble(const struct gen_device_info *devinfo,
-const void *assembly, int start, int end, FILE *out)
+const void *assembly, int start, int end,
+bool print_offsets, FILE *out)
 {
bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
 
@@ -346,7 +347,7 @@ brw_disassemble(const struct gen_device_info *devinfo,
   const brw_inst *insn = assembly + offset;
   brw_inst uncompacted;
   bool compacted = brw_inst_cmpt_control(devinfo, insn);
-  if (0)
+  if (print_offsets)
  fprintf(out, "0x%08x: ", offset);
 
   if (compacted) {
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 2d0f56f793..ec98c046ee 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -127,7 +127,8 @@ void brw_init_codegen(const struct gen_device_info *, 
struct brw_codegen *p,
 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
  const struct brw_inst *inst, bool is_compacted);
 void brw_disassemble(const struct gen_device_info *devinfo,
- const void *assembly, int start, int end, FILE *out);
+ const void *assembly, int start, int end,
+ bool print_offsets, FILE *out);
 const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
 
 brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode);
diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
index 9a136db4db..c4a23594f8 100644
--- a/src/intel/tools/disasm.c
+++ b/src/intel/tools/disasm.c
@@ -97,7 +97,7 @@ gen_disasm_disassemble(struct gen_disasm *disasm, const void 
*assembly,
   int start_offset = group->offset;
   int end_offset = next->offset;
 
-  brw_disassemble(devinfo, assembly, start_offset, end_offset, out);
+  brw_disassemble(devinfo, assembly, start_offset, end_offset, false, out);
 
   if (group->error) {
  fputs(group->error, out);
diff --git a/src/mesa/drivers/dri/i965/brw_ff_gs.c 
b/src/mesa/drivers/dri/i965/brw_ff_gs.c
index 174418a474..16db209eaa 100644
--- a/src/mesa/drivers/dri/i965/brw_ff_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_ff_gs.c
@

[Mesa-dev] [PATCH 08/16] intel/common: add new debug option print_offsets options for dumping assembly

[kevin . rogovin]

From: Kevin Rogovin 

Signed-off-by: Kevin Rogovin 
---
 src/intel/common/gen_debug.c | 1 +
 src/intel/common/gen_debug.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c
index a978f2f581..ecb6be0028 100644
--- a/src/intel/common/gen_debug.c
+++ b/src/intel/common/gen_debug.c
@@ -85,6 +85,7 @@ static const struct debug_control debug_control[] = {
{ "nohiz",   DEBUG_NO_HIZ },
{ "color",   DEBUG_COLOR },
{ "reemit",  DEBUG_REEMIT },
+   { "print_offsets", DEBUG_PRINT_OFFSETS },
{ NULL,0 }
 };
 
diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h
index da5b5a569d..e9047676d5 100644
--- a/src/intel/common/gen_debug.h
+++ b/src/intel/common/gen_debug.h
@@ -83,6 +83,7 @@ extern uint64_t INTEL_DEBUG;
 #define DEBUG_NO_HIZ  (1ull << 39)
 #define DEBUG_COLOR   (1ull << 40)
 #define DEBUG_REEMIT  (1ull << 41)
+#define DEBUG_PRINT_OFFSETS   (1ull << 42)
 
 #ifdef HAVE_ANDROID_PLATFORM
 #define LOG_TAG "INTEL-MESA"
-- 
2.15.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 13/16] intel/tools/BatchbufferLogger (output-xml): add outputter to XML

[kevin . rogovin]

From: Kevin Rogovin 

Signed-off-by: Kevin Rogovin 
---
 src/intel/Makefile.tools.am|   6 +-
 src/intel/tools/.gitignore |   1 +
 src/intel/tools/i965_batchbuffer_dump_show_xml.cpp | 217 +
 3 files changed, 223 insertions(+), 1 deletion(-)
 create mode 100644 src/intel/tools/i965_batchbuffer_dump_show_xml.cpp

diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index 2c36649f89..1c44d92d60 100644
--- a/src/intel/Makefile.tools.am
+++ b/src/intel/Makefile.tools.am
@@ -30,7 +30,8 @@ noinst_PROGRAMS += \
 intellib_LTLIBRARIES = \
tools/libi965_batchbuffer_logger.la
 
-intelbin_PROGRAMS = tools/i965_batchbuffer_dump_show
+intelbin_PROGRAMS = tools/i965_batchbuffer_dump_show \
+   tools/i965_batchbuffer_dump_show_xml
 
 intelbin_SCRIPTS = tools/i965_batchbuffer_logger_sh
 CLEANFILES += $(intelbin_SCRIPTS)
@@ -103,3 +104,6 @@ tools/i965_batchbuffer_logger_sh: 
tools/i965_batchbuffer_logger_sh.in
 
 tools_i965_batchbuffer_dump_show_SOURCES = \
tools/i965_batchbuffer_dump_show.c
+
+tools_i965_batchbuffer_dump_show_xml_SOURCES = \
+   tools/i965_batchbuffer_dump_show_xml.cpp
diff --git a/src/intel/tools/.gitignore b/src/intel/tools/.gitignore
index 7d95bcdf3a..7180e4ba4b 100644
--- a/src/intel/tools/.gitignore
+++ b/src/intel/tools/.gitignore
@@ -2,3 +2,4 @@
 /aubinator_error_decode
 /i965_batchbuffer_logger_sh
 /i965_batchbuffer_dump_show
+/i965_batchbuffer_dump_show_xml
diff --git a/src/intel/tools/i965_batchbuffer_dump_show_xml.cpp 
b/src/intel/tools/i965_batchbuffer_dump_show_xml.cpp
new file mode 100644
index 00..64916897ea
--- /dev/null
+++ b/src/intel/tools/i965_batchbuffer_dump_show_xml.cpp
@@ -0,0 +1,217 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "tools/i965_batchbuffer_logger_output.h"
+
+static
+std::string
+xml_value_from_file(unsigned int len, std::FILE *pfile)
+{
+   std::ostringstream str;
+   unsigned int i;
+   char c;
+
+   str << "";
+   return str.str();
+}
+
+static
+std::string
+xml_string_from_file(unsigned int len, std::FILE *pfile)
+{
+   std::ostringstream str;
+   unsigned int i;
+   char c;
+
+   for(i = 0; i < len; ++i) {
+  if (std::fread(&c, sizeof(char), 1, pfile) != sizeof(char)) {
+ break;
+  }
+  switch(c) {
+  case '<':
+ str << "<";
+ break;
+  case '>':
+ str << ">";
+ break;
+  case '&':
+ str << "&";
+ break;
+  case '\n':
+ str << "
";
+ break;
+  case '\"':
+ str << """;
+ break;
+  default:
+ str << c;
+  }
+   }
+
+   return str.str();
+}
+
+static
+bool
+legal_tag_char(char c)
+{
+   switch(c)
+   {
+   case '-':
+   case '_':
+   case '.':
+  return true;
+   }
+   return !std::isspace(c) && std::isalnum(c);
+}
+
+static
+std::string
+xml_tag_from_file(unsigned int len, std::FILE *pfile)
+{
+   std::string return_value;
+   unsigned int i;
+   char c;
+
+   for(i = 0; i < len; ++i) {
+  if (std::fread(&c, sizeof(char), 1, pfile) != sizeof(char)) {
+ break;
+  }
+  if (legal_tag_char(c)) {
+ if (i == 0 && (std::isdigit(c) || c == '.' || c == '-')) {
+return_value.push_back('_');
+ }
+ return_value.push_back(c);
+  } else {
+ return_value.push_back('_');
+  }
+   }
+
+   return return_value;
+}
+
+static
+void
+handle_block_begin(const struct i965_batchbuffer_logger_header *hdr,
+   std::vector &block_stack,
+   std::FILE *pfile)
+{
+   assert(hdr->type == I965_BATCHBUFFER_LOGGER_MESSAGE_BLOCK_BEGIN);
+   block_stack.push_back(xml_tag_from_file(hdr->name_length, pfile));
+   std::cout << "<" << block

[Mesa-dev] [PATCH 11/16] intel/tools/BatchbufferLogger: install i965_batchbuffer non-driver interface headers

[kevin . rogovin]

From: Kevin Rogovin 

Signed-off-by: Kevin Rogovin 
---
 src/intel/Makefile.tools.am   |  12 +++
 src/intel/tools/.gitignore|   1 +
 src/intel/tools/i965_batchbuffer_logger_sh.in | 108 ++
 3 files changed, 121 insertions(+)
 create mode 100644 src/intel/tools/i965_batchbuffer_logger_sh.in

diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index 270463589d..f5eda31a5c 100644
--- a/src/intel/Makefile.tools.am
+++ b/src/intel/Makefile.tools.am
@@ -19,7 +19,9 @@
 # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 # IN THE SOFTWARE.
 
+intelbindir = $(bindir)
 intellibdir = $(libdir)
+intelincludedir = $(includedir)
 
 noinst_PROGRAMS += \
tools/aubinator \
@@ -28,6 +30,12 @@ noinst_PROGRAMS += \
 intellib_LTLIBRARIES = \
tools/libi965_batchbuffer_logger.la
 
+intelbin_SCRIPTS = tools/i965_batchbuffer_logger_sh
+CLEANFILES += $(intelbin_SCRIPTS)
+
+intelinclude_HEADERS = tools/i965_batchbuffer_logger_app.h \
+   tools/i965_batchbuffer_logger_output.h
+
 tools_aubinator_SOURCES = \
tools/aubinator.c \
tools/disasm.c \
@@ -86,3 +94,7 @@ tools_libi965_batchbuffer_logger_la_CXXFLAGS = \
 
 tools_libi965_batchbuffer_logger_la_LDFLAGS = \
-no-undefined -avoid-version -shared -shrext .so
+
+intel_sed_prefix_vars = sed -e 's,[@]libdir[@],$(intellibdir),g'
+tools/i965_batchbuffer_logger_sh: tools/i965_batchbuffer_logger_sh.in
+   $(intel_sed_prefix_vars) < tools/i965_batchbuffer_logger_sh.in > 
tools/i965_batchbuffer_logger_sh
diff --git a/src/intel/tools/.gitignore b/src/intel/tools/.gitignore
index 27437f9eef..fa9bf70808 100644
--- a/src/intel/tools/.gitignore
+++ b/src/intel/tools/.gitignore
@@ -1,2 +1,3 @@
 /aubinator
 /aubinator_error_decode
+/i965_batchbuffer_logger_sh
diff --git a/src/intel/tools/i965_batchbuffer_logger_sh.in 
b/src/intel/tools/i965_batchbuffer_logger_sh.in
new file mode 100644
index 00..0746173417
--- /dev/null
+++ b/src/intel/tools/i965_batchbuffer_logger_sh.in
@@ -0,0 +1,108 @@
+#!/bin/bash
+# -*- mode: sh -*-
+
+function show_help() {
+cat 

[Mesa-dev] [PATCH 06/16] intel/tools/disasm: gen_disasm_disassemble to take const void* instead of void*

[kevin . rogovin]

From: Kevin Rogovin 

Reviewed-by: Matt Turner 
Signed-off-by: Kevin Rogovin 
---
 src/intel/tools/disasm.c | 6 +++---
 src/intel/tools/gen_disasm.h | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
index 5091579522..ffcd48084f 100644
--- a/src/intel/tools/disasm.c
+++ b/src/intel/tools/disasm.c
@@ -44,14 +44,14 @@ is_send(uint32_t opcode)
 }
 
 static int
-gen_disasm_find_end(struct gen_disasm *disasm, void *assembly, int start)
+gen_disasm_find_end(struct gen_disasm *disasm, const void *assembly, int start)
 {
struct gen_device_info *devinfo = &disasm->devinfo;
int offset = start;
 
/* This loop exits when send-with-EOT or when opcode is 0 */
while (true) {
-  brw_inst *insn = assembly + offset;
+  const brw_inst *insn = assembly + offset;
 
   if (brw_inst_cmpt_control(devinfo, insn)) {
  offset += 8;
@@ -70,7 +70,7 @@ gen_disasm_find_end(struct gen_disasm *disasm, void 
*assembly, int start)
 }
 
 void
-gen_disasm_disassemble(struct gen_disasm *disasm, void *assembly,
+gen_disasm_disassemble(struct gen_disasm *disasm, const void *assembly,
int start, FILE *out)
 {
struct gen_device_info *devinfo = &disasm->devinfo;
diff --git a/src/intel/tools/gen_disasm.h b/src/intel/tools/gen_disasm.h
index d2764bb90b..8d82a58617 100644
--- a/src/intel/tools/gen_disasm.h
+++ b/src/intel/tools/gen_disasm.h
@@ -32,7 +32,7 @@ struct gen_disasm;
 
 struct gen_disasm *gen_disasm_create(int pciid);
 void gen_disasm_disassemble(struct gen_disasm *disasm,
-void *assembly, int start, FILE *out);
+const void *assembly, int start, FILE *out);
 
 void gen_disasm_destroy(struct gen_disasm *disasm);
 
-- 
2.15.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 03/16] intel/tools: BatchBufferLogger define output file format of tool

[kevin . rogovin]

From: Kevin Rogovin 

Define the output format of the BatchbufferLogger. The output
is a sequence of blocks where blocks can have member blocks
or values. The top level blocks come from the application
calling into the BatchBufferLogger when an GL/GLES API call
is started and returns.

Signed-off-by: Kevin Rogovin 
---
 src/intel/tools/i965_batchbuffer_logger_output.h | 66 
 1 file changed, 66 insertions(+)
 create mode 100644 src/intel/tools/i965_batchbuffer_logger_output.h

diff --git a/src/intel/tools/i965_batchbuffer_logger_output.h 
b/src/intel/tools/i965_batchbuffer_logger_output.h
new file mode 100644
index 00..4e4c988d3c
--- /dev/null
+++ b/src/intel/tools/i965_batchbuffer_logger_output.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef I965_BATCHBUFFER_LOGGER_OUTPUT_H
+#define I965_BATCHBUFFER_LOGGER_OUTPUT_H
+
+#include 
+#include "i965_batchbuffer_logger_app.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * FILE format of the log is a seqence of (HEADER, NAME-DATA, VALUE-DATA)
+ * tuples where HEADER is the struct i965_batchbuffer_logger_header packed
+ * via fwrite, NAME-DATA is a sequence of HEADER.name_length characers and
+ * VALUE-DATA is a seqnece of HEADER.value_length characters. The start
+ * and end of blocks are used to give nested structure to the data (for
+ * example to make better JSON or XML output). Block endings will have that
+ * the name and value lengths are both ALWAYS 0. For other types, name should
+ * never be zero, but value can be (typically for blocks).
+ */
+
+struct i965_batchbuffer_logger_header {
+   enum i965_batchbuffer_logger_message_type_t type;
+
+   /**
+* length of the string for the name must be 0 for type
+* I965_BATCHBUFFER_LOGGER_MESSAGE_BLOCK_END
+*/
+   uint32_t name_length;
+
+   /**
+* length of the string for the value, must be 0 for types
+* I965_BATCHBUFFER_LOGGER_MESSAGE_BLOCK_BEGIN and
+* I965_BATCHBUFFER_LOGGER_MESSAGE_BLOCK_END
+*/
+   uint32_t value_length;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
-- 
2.15.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 07/16] intel/tools/disasm: add gen_disasm_assembly_length function

[kevin . rogovin]

From: Kevin Rogovin 

The length function is needed if one wishes to save GEN binary
shaders to file.

Signed-off-by: Kevin Rogovin 
---
 src/intel/tools/disasm.c | 7 +++
 src/intel/tools/gen_disasm.h | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
index ffcd48084f..9a136db4db 100644
--- a/src/intel/tools/disasm.c
+++ b/src/intel/tools/disasm.c
@@ -107,6 +107,13 @@ gen_disasm_disassemble(struct gen_disasm *disasm, const 
void *assembly,
ralloc_free(disasm_info);
 }
 
+int
+gen_disasm_assembly_length(struct gen_disasm *disasm,
+   const void *assembly, int start)
+{
+   return gen_disasm_find_end(disasm, assembly, start) - start;
+}
+
 struct gen_disasm *
 gen_disasm_create(int pciid)
 {
diff --git a/src/intel/tools/gen_disasm.h b/src/intel/tools/gen_disasm.h
index 8d82a58617..8b95a710e2 100644
--- a/src/intel/tools/gen_disasm.h
+++ b/src/intel/tools/gen_disasm.h
@@ -33,6 +33,8 @@ struct gen_disasm;
 struct gen_disasm *gen_disasm_create(int pciid);
 void gen_disasm_disassemble(struct gen_disasm *disasm,
 const void *assembly, int start, FILE *out);
+int gen_disasm_assembly_length(struct gen_disasm *disasm,
+   const void *assembly, int start);
 
 void gen_disasm_destroy(struct gen_disasm *disasm);
 
-- 
2.15.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 01/16] intel/tools: define BatchBufferLogger driver interface

[kevin . rogovin]

From: Kevin Rogovin 

Define the driver interface for BatchbufferLogger. The
interface assumes that for any -thread- there is only
one batchbuffer to which commands are to be added. A
driver needs to provide the information on what is the
active batchbuffer on a calling thread and also a function
that given a batchbuffer, returns where in the batchbuffer
the driver is currently "at".

Signed-off-by: Kevin Rogovin 
---
 src/intel/tools/i965_batchbuffer_logger.h | 185 ++
 1 file changed, 185 insertions(+)
 create mode 100644 src/intel/tools/i965_batchbuffer_logger.h

diff --git a/src/intel/tools/i965_batchbuffer_logger.h 
b/src/intel/tools/i965_batchbuffer_logger.h
new file mode 100644
index 00..d174af0e05
--- /dev/null
+++ b/src/intel/tools/i965_batchbuffer_logger.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef I965_BATCHBUFFER_LOGGER_DRIVER_H
+#define I965_BATCHBUFFER_LOGGER_DRIVER_H
+
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * i965_batchbuffer_logger tracks a batchbuffers
+ * by the pair (GEM-BO handle, File descriptor)
+ * pair.
+ */
+struct i965_logged_batchbuffer {
+   /**
+* GEM BO of the batch buffer, this is the BO
+* sent to kernel to execute commands on the
+* GPU
+*/
+   uint32_t gem_bo;
+
+   /**
+* The file descriptor of the GEM BO
+*/
+   int fd;
+
+   /**
+* Opaque pointer used by the driver associated
+* to the batch buffer; an i965_batchbuffer_logger
+* does NOT use this value to identify a batchbuffer.
+* It is for the driver to use to help it compute
+* where it is in a specified batchbuffer.
+*/
+   const void *driver_data;
+};
+
+/**
+ * A counter is to be used by a driver to provide counts of elements
+ * added to a batchbuffer when the counter is active. Actions acting
+ * on a counter are placed on the active batchbuffer of the calling
+ * thread, not executed immediately. The actual counting (in addition
+ * to activation, deactivation, reset, and relase) are performed when
+ * the batchbuffer is intercepted by the logger.
+ */
+struct i965_batchbuffer_counter {
+   void *opaque;
+};
+
+/**
+ * An i965_batchbuffer_logger object represents the hooking
+ * of a GPU driver.
+ */
+struct i965_batchbuffer_logger {
+   /**
+* To be called by the driver to instruct the batchbuffer logger
+* to clear the log associated to a GEM BO from an FD.
+*/
+   void (*clear_batchbuffer_log)(struct i965_batchbuffer_logger *logger,
+ int fd, uint32_t gem_bo);
+
+   /**
+* To be called by the driver if it migrates commands from one
+* batchbuffer to another batchbuffer.
+*/
+   void (*migrate_batchbuffer)(struct i965_batchbuffer_logger *logger,
+   const struct i965_logged_batchbuffer *from,
+   const struct i965_logged_batchbuffer *to);
+
+   /**
+* To be called by the driver to add log-message data to the
+* batchbuffer log. The message will be added to the log of
+* the batchbuffer dst. If counter is non-NULL the values
+* in the counter are also emitted to the log.
+*/
+   void (*add_message)(struct i965_batchbuffer_logger *logger,
+   const struct i965_logged_batchbuffer *dst,
+   const char *txt);
+
+   /**
+* call to release the i965_batchbuffer_logger
+*/
+   void (*release_driver)(struct i965_batchbuffer_logger *logger);
+
+   /**
+* Create a counter object. If filename is non-NULL, then
+* the values of the counter will be emitted to the named
+* file when the counter is deleted.
+*/
+   struct i965_batchbuffer_counter(*create_counter)(struct 
i965_batchbuffer_logger *logger,
+const char *filename)

[Mesa-dev] [PATCH 02/16] intel/tools: define BatchbufferLogger application interface

[kevin . rogovin]

From: Kevin Rogovin 

Define the application interface to BatchbufferLogger. The
BatchbufferLogger needs from the application when a GL/GLES
API call is issues and returns. It will use this information
to correctly correlate batchbuffer additions to GL/GLES API
calls.

In addition, because the BatchbufferLogger will be intercepting
drmIoctl, an application does NOT link against it. Instead, one
needs to LD_PRELOAD the .so.

Signed-off-by: Kevin Rogovin 
---
 src/intel/tools/i965_batchbuffer_logger_app.h | 186 ++
 1 file changed, 186 insertions(+)
 create mode 100644 src/intel/tools/i965_batchbuffer_logger_app.h

diff --git a/src/intel/tools/i965_batchbuffer_logger_app.h 
b/src/intel/tools/i965_batchbuffer_logger_app.h
new file mode 100644
index 00..6f131646e1
--- /dev/null
+++ b/src/intel/tools/i965_batchbuffer_logger_app.h
@@ -0,1 +1,186 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef I965_BATCHBUFFER_LOGGER_APP_H
+#define I965_BATCHBUFFER_LOGGER_APP_H
+
+#include 
+#include 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumeration value specifying the kind of data to write;
+ * Data written to a a i965_batchbuffer_logger_session
+ * can mark the start of a block, then end of a block
+ * of item within a block. Eac type has an optional
+ * name and value strings.
+ */
+enum i965_batchbuffer_logger_message_type_t {
+   I965_BATCHBUFFER_LOGGER_MESSAGE_BLOCK_BEGIN, /* start of a block */
+   I965_BATCHBUFFER_LOGGER_MESSAGE_BLOCK_END,   /* end of a block */
+   I965_BATCHBUFFER_LOGGER_MESSAGE_VALUE,   /* value in block */
+};
+
+/**
+ * An i965_batchbuffer_logger_session_params represents how
+ * to emit batchbuffer logger data. The batchbuffer logger
+ * is controlled by the following environmental variables:
+ * - I965_DECODE_BEFORE_IOCTL if non-zero, emit batchbuffer log data
+ *BEFORE calling the kernel ioctl.
+ * - I965_EMIT_TOTAL_STATS gives a filename to which to emit the total
+ * counts and lengths of GPU commands emitted
+ *  - I965_PCI_ID pci_id Give a hexadecimal value of the PCI ID value for
+ *   the GPU the BatchbufferLogger to decode for; this
+ *   value is used if and only if the driver fails to
+ *   tell the BatchbufferLogger a valid PCI ID value to
+ *   use
+ *  - I965_DECODE_LEVEL controls the level of batchbuffer decoding
+ * - no_decode do not decode batchbuffer at all
+ * - instruction_decode decode instruction name only
+ * - instruction_details_decode decode instruction contents
+ *  - I965_PRINT_RELOC_LEVEL controls at what level to print reloc data
+ * - print_reloc_nothing do not print reloc data
+ * - print_reloc_gem_gpu_updates print reloc data GEM by GEM
+ *  - I965_DECODE_SHADERS if set and is 0, shader binaries are written to
+ *file;  otherwise their disassembly is emitted
+ *in each session
+ */
+struct i965_batchbuffer_logger_session_params {
+   /**
+* Client data opaque pointer passed back to
+* function callbacks.
+*/
+   void *client_data;
+
+   /**
+* Function called by i965_batchbuffer_logger_app to write
+* data for the sessions.
+* \param client_data the pointer value in
+*i965_batchbuffer_logger_session_params::client_data
+* \param tp the message type
+* \param name of the data
+* \param name_length length of the name data
+* \param value of the data
+* \param value_length length of the value data
+*/
+   void (*write)(void *client_data,
+ enum i965_batchbuffer_logger_message_type_t tp,
+ const void *name, uint32_t name_length,
+ const void *value, uint32_t value_length);
+
+   /**

[Mesa-dev] [PATCH 00/16] Batchbuffer Logger for Intel GPU (v3)

[kevin . rogovin]

From: Kevin Rogovin 

This patch series defines and implements a BatchbufferLogger
for Intel GEN. The main purpose of the BatchbufferLogger is
to strongly correlate API calls to data added to a batchbuffer.
In addition to this function, the BatchbufferLogger also tracks
GPU state (respecting HW context as well). The logger intercepts
drmIoctl recording the information needed to decode a bachbuffer
(such as GEM BO creation/deletion, HW context create/delete,
and most importantly execbuffer2). When the execbuffer2 returns
from the kernel, the BatchbufferLogger will log information
in its log of what was added when and in addition log the
GPU state (at the point in the batchbuffer) of 3DPRIMITIVE and
GPGPU_WALKER commands.

It is an application's requirment to tell the BatchbufferLogger
just before and just after an API call. Because of the need
to intercept drmIoctl, having an application link against
BatchbufferLogger is not robust. Instead, an application is
to use dlsym to fetch the correction a function pointer that
returns the BatchbufferLogger's application interface. The
interface of the BatchbufferLogger is defined in patch 0002.
A script is also provided to use the BatchbufferLogger in
an easier way than needing to set environmental variables.

On the subject of application integration, I have a -very-
small patch series that enabled BatchbufferLogger for
apitrace. I can share these patches if anyone asks, but I
cannot submit them to apitrace until atleast the BatchbufferLogger
is in Mesa with a stable application interface.

The log emitted by the BatchbufferLogger is a sequence of blocks
with possibility of blocks being elements of blocks. There is an
environmental variable to control if the top level blocks are
API call markers created from the calls into the BatchbufferLogger
from the application OR the actual ioctl intercepted with the
next level being the API call markers. An application starts
and ends a logging session. A session provides callbacks to
write the block data; with the interface of a callback a log
does not need to just write to a file, it could also write
over a network to remote application for the purpose of remote
debugging. A specific interface is also provided to write to a
file and additional tools are included to convert the log to JSON,
XML and text. The simple file format should allow others to be able
to take the data and use it however they see fit. The JSON output
alone can be quite illuminating to use when debugging/enhancing the
i965 driver for a single frame (or even single draw call) of a troublesome
application.

It is worth noting that i965 already has a batchbuffer decoder
dumper (also making use src/intel/tools/gen_decoder). However,
BatchbufferLogger has the following features which are not in the
current dumper and are likely quite tricky to implement into it.

 1. The biggest feature is that this BatchbufferLogger contents are
annotated by the GL/GLES API calls and driver text as well.
 2. This BatchbufferLogger provides an interface to application space
to allow for applications to start/end logging sessions as
they see fit. In addition, an application can have multilpe
independent sessions active.
 3. This BatchbufferLogger repeats the state of the GPU and HW
context on 3DPRIMITIVE and GPGPU_WALKER commands. By doing
so one can see the precise state the GPU is in at that command.
Coupled with (1), one can see what precise GPU state one
has when an application issues draw commands. Moreover, coupled
with the (previously) posted patches for apitrace, one
can compare differences at specific trace points within a
trace from apitrace to help diagnose regressions.

In addition, as suggested by Chris Wilson, I have also implemented an
i965 blackbox recorder at https://github.com/krogueintel/i965-blackbox
which will perform the necessary GL/GLES API interception to
produce annotated batchbuffer recordings to assist in GPU hang
debugging. The BatchbufferLogger (again at Chris Wilson's suggestion)
has the ability to walk batchbuffers BEFORE kernel submit and to
also add an EXEC_OBJECT_CAPTURE execobject2 whose contents are
the ID of the execbuffer2 ioctl submitted. The aim is to greatly
assist in GPU hang debugging for troublesome applications.

For those interested, this BatchbufferLogger is available on
github at https://github.com/krogueintel/asem/tree/batchbuffer-logger-v3.

The patch series is organized into the following blocks:

0001-0003: Define the BatchbufferLogger interfaces
0004-0004: Minor fix to i965 driver
0005-0005: Hooking of BatchbufferLogger into i965
0006-0009: Fixes and enhancements to intel/compiler,
   intel/tools and intel/common.
0010-0011: Implementation of BatchBufferLogger
0012-0014: Tools to decode log to JSON, XML and text
0015-0015: Command line tool for disassembling shader
   binaries.
0016-0016: Meson build support

v3:
  As requested by Matt Turner, instead of adding a 

[Mesa-dev] [PATCH 05/16] i965: Enable BatchbufferLogger in i965 driver

[kevin . rogovin]

From: Kevin Rogovin 

The interface for BatchbufferLogger is that it is active
only if it is LD_PRELOAD'ed. Thus, the i965 driver is to
use dlsym to see if it is there, and if so fetch the object
at intel_screen creation.

Signed-off-by: Kevin Rogovin 
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c| 22 -
 src/mesa/drivers/dri/i965/brw_bufmgr.h|  8 -
 src/mesa/drivers/dri/i965/brw_context.c   | 37 +
 src/mesa/drivers/dri/i965/brw_context.h   | 12 +++
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 30 +++--
 src/mesa/drivers/dri/i965/intel_screen.c  | 46 +--
 src/mesa/drivers/dri/i965/intel_screen.h  |  3 ++
 7 files changed, 150 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 52b5bf97a1..c5b1bfb83d 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -65,6 +65,8 @@
 #include "string.h"
 
 #include "i915_drm.h"
+#include "intel_screen.h"
+#include "tools/i965_batchbuffer_logger.h"
 
 #ifdef HAVE_VALGRIND
 #include 
@@ -104,6 +106,7 @@ struct bo_cache_bucket {
 };
 
 struct brw_bufmgr {
+   struct intel_screen *screen;
int fd;
 
mtx_t lock;
@@ -631,9 +634,14 @@ bo_unreference_final(struct brw_bo *bo, time_t time)
 {
struct brw_bufmgr *bufmgr = bo->bufmgr;
struct bo_cache_bucket *bucket;
+   struct i965_batchbuffer_logger *bb_logger =
+  bufmgr->screen->batchbuffer_logger;
 
DBG("bo_unreference final: %d (%s)\n", bo->gem_handle, bo->name);
 
+   if(bb_logger != NULL) {
+  bb_logger->clear_batchbuffer_log(bb_logger, bufmgr->fd, bo->gem_handle);
+   }
bucket = bucket_for_size(bufmgr, bo->size);
/* Put the buffer into our internal cache for reuse if we can. */
if (bufmgr->bo_reuse && bo->reusable && bucket != NULL &&
@@ -1065,6 +1073,12 @@ brw_bufmgr_destroy(struct brw_bufmgr *bufmgr)
free(bufmgr);
 }
 
+int
+brw_bufmgr_fd(const struct brw_bufmgr *bufmgr)
+{
+   return bufmgr->fd;
+}
+
 static int
 bo_set_tiling_internal(struct brw_bo *bo, uint32_t tiling_mode,
uint32_t stride)
@@ -1369,9 +1383,14 @@ gem_param(int fd, int name)
  * \param fd File descriptor of the opened DRM device.
  */
 struct brw_bufmgr *
-brw_bufmgr_init(struct gen_device_info *devinfo, int fd)
+brw_bufmgr_init(struct intel_screen *screen)
 {
struct brw_bufmgr *bufmgr;
+   struct gen_device_info *devinfo;
+   int fd;
+
+   devinfo = &screen->devinfo;
+   fd = screen->driScrnPriv->fd;
 
bufmgr = calloc(1, sizeof(*bufmgr));
if (bufmgr == NULL)
@@ -1387,6 +1406,7 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int fd)
 * fd so that its namespace does not clash with another.
 */
bufmgr->fd = fd;
+   bufmgr->screen = screen;
 
if (mtx_init(&bufmgr->lock, mtx_plain) != 0) {
   free(bufmgr);
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 0ae541cda0..b5d724be7b 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -46,6 +46,7 @@ extern "C" {
 
 struct gen_device_info;
 struct brw_context;
+struct intel_screen;
 
 struct brw_bo {
/**
@@ -274,6 +275,11 @@ void brw_bo_wait_rendering(struct brw_bo *bo);
  */
 void brw_bufmgr_destroy(struct brw_bufmgr *bufmgr);
 
+/**
+ * Returns the file descriptor of the buffer manager
+ */
+int brw_bufmgr_fd(const struct brw_bufmgr *bufmgr);
+
 /**
  * Get the current tiling (and resulting swizzling) mode for the bo.
  *
@@ -313,7 +319,7 @@ int brw_bo_busy(struct brw_bo *bo);
 int brw_bo_madvise(struct brw_bo *bo, int madv);
 
 /* drm_bacon_bufmgr_gem.c */
-struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo, int fd);
+struct brw_bufmgr *brw_bufmgr_init(struct intel_screen *screen);
 struct brw_bo *brw_bo_gem_create_from_name(struct brw_bufmgr *bufmgr,
const char *name,
unsigned int handle);
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 126c187f62..b5e041bb7b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -75,6 +75,8 @@
 #include "util/debug.h"
 #include "isl/isl.h"
 
+#include "tools/i965_batchbuffer_logger.h"
+
 /***
  * Mesa's Driver Functions
  ***/
@@ -1075,6 +1077,7 @@ brwCreateContext(gl_api api,
 
vbo_use_buffer_objects(ctx);
vbo_always_unmap_buffers(ctx);
+   brw->have_active_batchbuffer = true;
 
brw_disk_cache_init(brw);
 
@@ -1089,6 +1092,7 @@ intelDestroyContext(__DRIcontext * driContextPriv)
struct gl_context *ctx = &brw->ctx;
const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
+   brw->have_active_batchbuffer = false;
_mesa_meta_free(&brw->ctx);
 
i

[Mesa-dev] [PATCH 04/16] i965: assign BindingTableEntryCount of INTERFACE_DESCRIPTOR_DATA

[kevin . rogovin]

From: Kevin Rogovin 

Signed-off-by: Kevin Rogovin 
---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 04a492539a..3643d79231 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -4259,6 +4259,7 @@ genX(upload_cs_state)(struct brw_context *brw)
   .SamplerStatePointer = stage_state->sampler_offset,
   .SamplerCount = DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 
4),
   .BindingTablePointer = stage_state->bind_bo_offset,
+  .BindingTableEntryCount = prog_data->binding_table.size_bytes / 4,
   .ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs,
   .NumberofThreadsinGPGPUThreadGroup = cs_prog_data->threads,
   .SharedLocalMemorySize = encode_slm_size(GEN_GEN,
-- 
2.15.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965/nir: do int64 lowering before optimization

[Iago Toral]

On Mon, 2017-12-11 at 08:01 -0800, Jason Ekstrand wrote:
> On Mon, Dec 11, 2017 at 12:55 AM, Iago Toral 
> wrote:
> > This didn't get any reviews yet. Any takers?
> > 
> > 
> > 
> > On Fri, 2017-12-01 at 13:46 +0100, Iago Toral Quiroga wrote:
> > 
> > > Otherwise loop unrolling will fail to see the actual cost of
> > 
> > > the unrolling operations when the loop body contains 64-bit
> > integer
> > 
> > > instructions, and very specially when the divmod64 lowering
> > applies,
> > 
> > > since its lowering is quite expensive.
> > 
> > >
> > 
> > > Without this change, some in-development CTS tests for int64
> > 
> > > get stuck forever trying to register allocate a shader with
> > 
> > > over 50K SSA values. The large number of SSA values is the result
> > 
> > > of NIR first unrolling multiple seemingly simple loops that
> > involve
> > 
> > > int64 instructions, only to then lower these instructions to
> > produce
> > 
> > > a massive pile of code (due to the divmod64 lowering in the
> > unrolled
> > 
> > > instructions).
> > 
> > >
> > 
> > > With this change, loop unrolling will see the loops with the
> > int64
> > 
> > > code already lowered and will realize that it is too expensive to
> > 
> > > unroll.
> > 
> 
> Hrm... I'm not quite sure what I think of this.  I put it after
> nir_optimize because I wanted opt_algebraic to be able to work it's
> magic and hopefully remove a bunch of int64 ops before we lower
> them.  In particular, we have optimizations to remove integer
> division and replace it with shifts.  However, loop unrolling does
> need to happen before lower_indirect_derefs so that
> lower_indirect_derefs will do as little work as possible.
> 
> This is a bit of a pickle...  I don't really want to add a third
> brw_nir_optimize call.  It probably wouldn't be the end of the world
> but it does add compile time.
> 
> One crazy idea which I don't think I like would be to have a quick
> pass that walks the IR and sees if there are any 64-bit SSA values. 
> If it does, we run brw_nir_optimize without loop unrolling then 64-
> bit lowering and then we go into the normal brw_nir_optimize.

With the constraints you mention above, I am not sure that we have many
more options... what if we always run opt_algebraic first followed by
int64 lowering before the first nir_optimize? That would only add an
extra opt_algebraic instead of a full nir_optimize. Would that be
better than adding that 64-bit SSA scan pre-pass?
Iago
> --Jason
>  
> > > ---
> > 
> > >  src/intel/compiler/brw_nir.c | 8 
> > 
> > >  1 file changed, 4 insertions(+), 4 deletions(-)
> > 
> > >
> > 
> > > diff --git a/src/intel/compiler/brw_nir.c
> > 
> > > b/src/intel/compiler/brw_nir.c
> > 
> > > index 8f3f77f89a..ef12cdfff8 100644
> > 
> > > --- a/src/intel/compiler/brw_nir.c
> > 
> > > +++ b/src/intel/compiler/brw_nir.c
> > 
> > > @@ -636,6 +636,10 @@ brw_preprocess_nir(const struct brw_compiler
> > 
> > > *compiler, nir_shader *nir)
> > 
> > >  
> > 
> > > OPT(nir_split_var_copies);
> > 
> > >  
> > 
> > > +   nir_lower_int64(nir, nir_lower_imul64 |
> > 
> > > +nir_lower_isign64 |
> > 
> > > +nir_lower_divmod64);
> > 
> > > +
> > 
> > > nir = brw_nir_optimize(nir, compiler, is_scalar);
> > 
> > >  
> > 
> > > if (is_scalar) {
> > 
> > > @@ -663,10 +667,6 @@ brw_preprocess_nir(const struct brw_compiler
> > 
> > > *compiler, nir_shader *nir)
> > 
> > >    brw_nir_no_indirect_mask(compiler, nir->info.stage);
> > 
> > > nir_lower_indirect_derefs(nir, indirect_mask);
> > 
> > >  
> > 
> > > -   nir_lower_int64(nir, nir_lower_imul64 |
> > 
> > > -nir_lower_isign64 |
> > 
> > > -nir_lower_divmod64);
> > 
> > > -
> > 
> > > /* Get rid of split copies */
> > 
> > > nir = brw_nir_optimize(nir, compiler, is_scalar);
> > 
> > >  
> > 
> > ___
> > 
> > mesa-dev mailing list
> > 
> > mesa-dev@lists.freedesktop.org
> > 
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > 
> > ___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 101560] SPIR-V OpSwitch with int64 not supported even though shaderInt64 is true

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101560

Jason Ekstrand  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #5 from Jason Ekstrand  ---
This should be fixed by the following commit:

commit df657ebb68a000b031d1b052748af5df4b645b59
Author: Jason Ekstrand 
Date:   Wed Dec 6 10:01:22 2017 -0800

spirv: Add support for all bit sizes in OpSwitch

Reviewed-by: Ian Romanick 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101560

-- 
You are receiving this mail because:
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2] isl: don't crash when creating a huge image

[Samuel Iglesias Gonsálvez]

On 28/11/17 11:07, Samuel Iglesias Gonsálvez wrote:
> This patch is still unreviewed.
> 

Gently reminder.

Sam

> Sam
> 
> On Tue, 2017-11-14 at 09:45 +0100, Samuel Iglesias Gonsálvez wrote:
>> The HW has some limits but, according to the spec, we can create
>> the image as it has not yet any memory backing it. This patch
>> logs a debug error and set the size to the UINT64_MAX in order to
>> avoid allocating actual memory later.
>>
>> Fixes the crashes on BDW for the following tests:
>>
>> dEQP-VK.pipeline.render_to_image.core.2d_array.huge.*
>> dEQP-VK.pipeline.render_to_image.core.cube_array.huge.*
>>
>> Signed-off-by: Samuel Iglesias Gonsálvez 
>> ---
>>  src/intel/isl/isl.c | 13 +
>>  1 file changed, 9 insertions(+), 4 deletions(-)
>>
>> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
>> index 59f512fc050..cd7f2fcd4cb 100644
>> --- a/src/intel/isl/isl.c
>> +++ b/src/intel/isl/isl.c
>> @@ -26,6 +26,7 @@
>>  #include 
>>  
>>  #include "genxml/genX_bits.h"
>> +#include "common/intel_log.h"
>>  
>>  #include "isl.h"
>>  #include "isl_gen4.h"
>> @@ -1481,8 +1482,10 @@ isl_surf_init_s(const struct isl_device *dev,
>> *
>> * This comment is applicable to all Pre-gen9 platforms.
>> */
>> -  if (size > (uint64_t) 1 << 31)
>> - return false;
>> +  if (size > (uint64_t) 1 << 31) {
>> + intel_logd("%s: Surface size is bigger than the supported
>> by the HW: %ld > (1 << 31)", __func__, size);
>> + size = UINT64_MAX;
>> +  }
>> } else {
>>/* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
>> *"In addition to restrictions on maximum height, width,
>> and depth,
>> @@ -1490,8 +1493,10 @@ isl_surf_init_s(const struct isl_device *dev,
>> * All pixels within the surface must be contained within
>> 2^38 bytes
>> * of the base address."
>> */
>> -  if (size > (uint64_t) 1 << 38)
>> - return false;
>> +  if (size > (uint64_t) 1 << 38) {
>> + intel_logd("%s: Surface size is bigger than the supported
>> by the HW: %ld > (1 << 38)", __func__, size);
>> + size = UINT64_MAX;
>> +  }
>> }
>>  
>> *surf = (struct isl_surf) {
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 



signature.asc
Description: OpenPGP digital signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] i965: Enable CCS_E sampling of sRGB textures as UNORM

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b87d356..e21e1da 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2566,9 +2566,8 @@ can_texture_with_ccs(struct brw_context *brw,
if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
   return false;
 
-   /* TODO: Replace with format_ccs_e_compat_with_miptree for better perf. */
-   if (!isl_formats_are_ccs_e_compatible(&brw->screen->devinfo,
- mt->surf.format, view_format)) {
+   if (!format_ccs_e_compat_with_miptree(&brw->screen->devinfo,
+ mt, view_format)) {
   perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
  isl_format_get_layout(view_format)->name,
  _mesa_get_format_name(mt->format));
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/2] i965/draw: Do resolves properly for textures used by TXF

[Jason Ekstrand]

---
 src/mesa/drivers/dri/i965/brw_draw.c | 41 
 1 file changed, 41 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 7e29dcf..549735d 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -40,6 +40,7 @@
 #include "swrast_setup/swrast_setup.h"
 #include "drivers/common/meta.h"
 #include "util/bitscan.h"
+#include "util/bitset.h"
 
 #include "brw_blorp.h"
 #include "brw_draw.h"
@@ -371,6 +372,20 @@ intel_disable_rb_aux_buffer(struct brw_context *brw,
return found;
 }
 
+static void
+mark_textures_used_for_txf(BITSET_WORD *used_for_txf,
+   const struct gl_program *prog)
+{
+   if (!prog)
+  return;
+
+   unsigned mask = prog->SamplersUsed & prog->info.textures_used_by_txf;
+   while (mask) {
+  int s = u_bit_scan(&mask);
+  BITSET_SET(used_for_txf, prog->SamplerUnits[s]);
+   }
+}
+
 /**
  * \brief Resolve buffers before drawing.
  *
@@ -386,6 +401,18 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering)
memset(brw->draw_aux_buffer_disabled, 0,
   sizeof(brw->draw_aux_buffer_disabled));
 
+   BITSET_DECLARE(used_for_txf, MAX_COMBINED_TEXTURE_IMAGE_UNITS);
+   memset(used_for_txf, 0, sizeof(used_for_txf));
+   if (rendering) {
+  mark_textures_used_for_txf(used_for_txf, ctx->VertexProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->TessCtrlProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->TessEvalProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->GeometryProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->FragmentProgram._Current);
+   } else {
+  mark_textures_used_for_txf(used_for_txf, ctx->ComputeProgram._Current);
+   }
+
/* Resolve depth buffer and render cache of each enabled texture. */
int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit;
for (int i = 0; i <= maxEnabledUnit; i++) {
@@ -422,6 +449,20 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering)
 min_layer, num_layers,
 disable_aux);
 
+  /* If any programs are using it with texelFetch, we may need to also do
+   * a prepare with an sRGB format to ensure texelFetch works "properly".
+   */
+  if (BITSET_TEST(used_for_txf, i)) {
+ enum isl_format txf_format =
+translate_tex_format(brw, tex_obj->_Format, GL_DECODE_EXT);
+ if (txf_format != view_format) {
+intel_miptree_prepare_texture(brw, tex_obj->mt, txf_format,
+  min_level, num_levels,
+  min_layer, num_layers,
+  disable_aux);
+ }
+  }
+
   brw_cache_flush_for_read(brw, tex_obj->mt->bo);
 
   if (tex_obj->base.StencilSampling ||
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/2] nir: fix shift for uint64_t

[Jason Ekstrand]

How about just using 1ull?

On Mon, Dec 11, 2017 at 7:47 PM, Timothy Arceri 
wrote:

> ---
>  src/compiler/nir/nir_lower_io_arrays_to_elements.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c
> b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
> index dca5719f114..cdf9a76a881 100644
> --- a/src/compiler/nir/nir_lower_io_arrays_to_elements.c
> +++ b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
> @@ -240,21 +240,21 @@ create_indirects_mask(nir_shader *shader, uint64_t
> *indirects,
> intr->intrinsic != nir_intrinsic_interp_var_at_centroid
> &&
> intr->intrinsic != nir_intrinsic_interp_var_at_sample
> &&
> intr->intrinsic != nir_intrinsic_interp_var_at_offset)
>continue;
>
> nir_variable *var = intr->variables[0]->var;
>
> if (var->data.mode != mode)
>continue;
>
> -   uint64_t loc_mask = 1 << var->data.location;
> +   uint64_t loc_mask = ((uint64_t)1) << var->data.location;
> if (var->data.patch) {
>if (deref_has_indirect(&b, var, intr->variables[0]))
>   patch_indirects[var->data.location_frac] |=
> loc_mask;
> } else {
>if (deref_has_indirect(&b, var, intr->variables[0]))
>   indirects[var->data.location_frac] |= loc_mask;
> }
>  }
>   }
>}
> @@ -282,21 +282,21 @@ lower_io_arrays_to_elements(nir_shader *shader,
> nir_variable_mode mask,
> if (intr->intrinsic != nir_intrinsic_load_var &&
> intr->intrinsic != nir_intrinsic_store_var &&
> intr->intrinsic != nir_intrinsic_interp_var_at_centroid
> &&
> intr->intrinsic != nir_intrinsic_interp_var_at_sample
> &&
> intr->intrinsic != nir_intrinsic_interp_var_at_offset)
>continue;
>
> nir_variable *var = intr->variables[0]->var;
>
> /* Skip indirects */
> -   uint64_t loc_mask = 1 << var->data.location;
> +   uint64_t loc_mask = ((uint64_t)1) << var->data.location;
> if (var->data.patch) {
>if (patch_indirects[var->data.location_frac] &
> loc_mask)
>   continue;
> } else {
>if (indirects[var->data.location_frac] & loc_mask)
>   continue;
> }
>
> nir_variable_mode mode = var->data.mode;
>
> --
> 2.14.3
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] ac: fix nir_op_f2f64

[Timothy Arceri]

Without this we get the error "FPExt only operates on FP" when
converting the following:

   vec1 32 ssa_5 = b2f ssa_4
   vec1 64 ssa_6 = f2f64 ssa_5

Which results in:

   %44 = and i32 %43, 1065353216
   %45 = fpext i32 %44 to double

With this patch we now get:

   %44 = and i32 %43, 1065353216
   %45 = bitcast i32 %44 to float
   %46 = fpext float %45 to double
---
 src/amd/common/ac_nir_to_llvm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index f5cf9d271d3..a1958b4332d 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1770,20 +1770,21 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
case nir_op_i2f64:
src[0] = ac_to_integer(&ctx->ac, src[0]);
result = LLVMBuildSIToFP(ctx->ac.builder, src[0], 
ac_to_float_type(&ctx->ac, def_type), "");
break;
case nir_op_u2f32:
case nir_op_u2f64:
src[0] = ac_to_integer(&ctx->ac, src[0]);
result = LLVMBuildUIToFP(ctx->ac.builder, src[0], 
ac_to_float_type(&ctx->ac, def_type), "");
break;
case nir_op_f2f64:
+   src[0] = ac_to_float(&ctx->ac, src[0]);
result = LLVMBuildFPExt(ctx->ac.builder, src[0], 
ac_to_float_type(&ctx->ac, def_type), "");
break;
case nir_op_f2f32:
result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], 
ac_to_float_type(&ctx->ac, def_type), "");
break;
case nir_op_u2u32:
case nir_op_u2u64:
src[0] = ac_to_integer(&ctx->ac, src[0]);
if (get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < 
get_elem_bits(&ctx->ac, def_type))
result = LLVMBuildZExt(ctx->ac.builder, src[0], 
def_type, "");
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] nir: fix shift for uint64_t

[Timothy Arceri]

---
 src/compiler/nir/nir_lower_io_arrays_to_elements.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c 
b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
index dca5719f114..cdf9a76a881 100644
--- a/src/compiler/nir/nir_lower_io_arrays_to_elements.c
+++ b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
@@ -240,21 +240,21 @@ create_indirects_mask(nir_shader *shader, uint64_t 
*indirects,
intr->intrinsic != nir_intrinsic_interp_var_at_centroid &&
intr->intrinsic != nir_intrinsic_interp_var_at_sample &&
intr->intrinsic != nir_intrinsic_interp_var_at_offset)
   continue;
 
nir_variable *var = intr->variables[0]->var;
 
if (var->data.mode != mode)
   continue;
 
-   uint64_t loc_mask = 1 << var->data.location;
+   uint64_t loc_mask = ((uint64_t)1) << var->data.location;
if (var->data.patch) {
   if (deref_has_indirect(&b, var, intr->variables[0]))
  patch_indirects[var->data.location_frac] |= loc_mask;
} else {
   if (deref_has_indirect(&b, var, intr->variables[0]))
  indirects[var->data.location_frac] |= loc_mask;
}
 }
  }
   }
@@ -282,21 +282,21 @@ lower_io_arrays_to_elements(nir_shader *shader, 
nir_variable_mode mask,
if (intr->intrinsic != nir_intrinsic_load_var &&
intr->intrinsic != nir_intrinsic_store_var &&
intr->intrinsic != nir_intrinsic_interp_var_at_centroid &&
intr->intrinsic != nir_intrinsic_interp_var_at_sample &&
intr->intrinsic != nir_intrinsic_interp_var_at_offset)
   continue;
 
nir_variable *var = intr->variables[0]->var;
 
/* Skip indirects */
-   uint64_t loc_mask = 1 << var->data.location;
+   uint64_t loc_mask = ((uint64_t)1) << var->data.location;
if (var->data.patch) {
   if (patch_indirects[var->data.location_frac] & loc_mask)
  continue;
} else {
   if (indirects[var->data.location_frac] & loc_mask)
  continue;
}
 
nir_variable_mode mode = var->data.mode;
 
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/2] st/glsl_to_nir: skip forced array splitting for tcs

[Timothy Arceri]

nir_lower_io_to_temporaries() does not support tcs so we cannot
assume there are no indirects here. Also the radeonsi backend
(the only backend to support tess) has support for tcs indirects
so there is no need to lower them anyway.
---
 src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 90b65ee85ed..70c5daaa225 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -635,21 +635,22 @@ st_link_nir(struct gl_context *ctx,
  * variant lowering.
  */
 void
 st_finalize_nir(struct st_context *st, struct gl_program *prog,
 struct gl_shader_program *shader_program, nir_shader *nir)
 {
struct pipe_screen *screen = st->pipe->screen;
 
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
-   NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
+   if (nir->info.stage != MESA_SHADER_TESS_CTRL)
+  NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
 
if (nir->info.stage == MESA_SHADER_VERTEX) {
   /* Needs special handling so drvloc matches the vbo state: */
   st_nir_assign_vs_in_locations(prog, nir);
   /* Re-lower global vars, to deal with any dead VS inputs. */
   NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 
   sort_varyings(&nir->outputs);
   st_nir_assign_var_locations(&nir->outputs,
   &nir->num_outputs,
-- 
2.14.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 00/25] Initial gl_spirv and spirv_extensions support in Mesa and i965

[Ian Romanick]

Any chance you could push an updated branch to your github? :)

On 11/30/2017 09:28 AM, Eduardo Lima Mitev wrote:
> Hello,
> 
> This is the second version of the series providing initial support for 
> ARB_gl_spirv and ARB_spirv_extensions in Mesa and i965.
> 
> First version of the series can be found at 
> .
> 
> In this series we hope we have addressed all issues detected during the 
> initial review. Thank you all who participated!
> 
> Taking the nitpicks and minor fixes apart, most important changes compared to 
> the first version are:
> 
> * A dedicated 'spirv' flag was removed from gl_shader struct. Now we use the 
> nulness of 'spirv_data' member for the same purpose.
> 
> * The per-program 'spirv' flag was moved out of this series, but will likely 
> be re-introduced in the next delivery, because it will become necessary.
> 
> * We enforce one SPIR-V shader per stage, and fail linking if this condition 
> is not met.
> 
> * 'SpirVCapabilities' struct of GL context constants is no longer a pointer 
> but a static struct.
> 
> As usual, a tree of this series can be found at 
> .
> 
> A tree of the larger WIP branch from which this series is taken: 
> .
> 
> Thanks in advance for the reviews!
> 
> cheers,
> Eduardo
> 
> Alejandro Piñeiro (9):
>   spirv_extensions: rename nir_spirv_supported_extensions
>   mesa: move nir_spirv_supported_capabilities definition
>   i965: initialize SPIR-V capabilities
>   spirv_extensions: add GL_ARB_spirv_extensions boilerplate
>   spirv_extensions: add list of extensions and to_string method
>   spirv_extensions: define spirv_extensions_supported
>   spirv_extensions: add spirv_supported_extensions on gl_constants
>   spirv_extensions: i965: initialize SPIR-V extensions
>   nir/spirv: add gl_spirv_validation method
> 
> Eduardo Lima Mitev (8):
>   mesa/glspirv: Add struct gl_shader_spirv_data
>   mesa/glspirv: Add a _mesa_spirv_link_shaders() placeholder
>   mesa/program: Link SPIR-V shaders using the SPIR-V code-path
>   mesa: Add a reference to gl_shader_spirv_data to gl_linked_shader
>   mesa/glspirv: Create gl_linked_shader objects for a SPIR-V program
>   mesa/glspirv: Add a _mesa_spirv_to_nir() function
>   i965: Call spirv_to_nir() instead of glsl_to_nir() for SPIR-V shaders
>   i965: Don't call process_glsl_ir() for SPIR-V shaders
> 
> Neil Roberts (1):
>   mesa: Add boilerplate for the GL 4.6 alias of glSpecializeShaderARB
> 
> Nicolai Hähnle (7):
>   mesa: add GL_ARB_gl_spirv boilerplate
>   mesa/glspirv: Add struct gl_spirv_module
>   mesa: implement SPIR-V loading in glShaderBinary
>   mesa/shaderapi: add a getter for GL_SPIR_V_BINARY_ARB
>   mesa: refuse to compile SPIR-V shaders or link mixed shaders
>   mesa: add gl_constants::SpirVCapabilities
>   mesa: Implement glSpecializeShaderARB
> 
>  src/amd/vulkan/radv_shader.c|   4 +-
>  src/compiler/Makefile.sources   |   2 +
>  src/compiler/spirv/nir_spirv.h  |  21 +-
>  src/compiler/spirv/spirv_extensions.c   |  77 +++
>  src/compiler/spirv/spirv_extensions.h   |  63 ++
>  src/compiler/spirv/spirv_to_nir.c   | 160 +-
>  src/compiler/spirv/vtn_private.h|   2 +-
>  src/intel/vulkan/anv_pipeline.c |   4 +-
>  src/mapi/glapi/gen/ARB_gl_spirv.xml |  21 ++
>  src/mapi/glapi/gen/ARB_spirv_extensions.xml |  13 ++
>  src/mapi/glapi/gen/GL4x.xml |  11 +
>  src/mapi/glapi/gen/Makefile.am  |   2 +
>  src/mapi/glapi/gen/gl_API.xml   |   8 +
>  src/mapi/glapi/gen/gl_genexec.py|   1 +
>  src/mapi/glapi/gen/meson.build  |   2 +
>  src/mesa/Makefile.sources   |   4 +
>  src/mesa/drivers/dri/i965/brw_context.c |  26 +++
>  src/mesa/drivers/dri/i965/brw_link.cpp  |   3 +-
>  src/mesa/drivers/dri/i965/brw_program.c |  14 +-
>  src/mesa/main/context.c |   2 +
>  src/mesa/main/extensions_table.h|   2 +
>  src/mesa/main/get.c |   7 +
>  src/mesa/main/get_hash_params.py|   3 +
>  src/mesa/main/getstring.c   |  12 +
>  src/mesa/main/glspirv.c | 331 
> 
>  src/mesa/main/glspirv.h | 108 +
>  src/mesa/main/mtypes.h  |  31 +++
>  src/mesa/main/shaderapi.c   |  60 -
>  src/mesa/main/shaderobj.c   |   3 +
>  src/mesa/main/spirv_extensions.c|  60 +
>  src/mesa/main/spirv_extensions.h|  49 
>  src/mesa/main/tests/dispatch_sanity.cpp |   3 +
>  src/mesa/meson.build|   4 +
>  src/mesa/program/ir_to_mesa.cpp |  23 +-
>  34 files changed, 1098 insertions(+), 38 d

Re: [Mesa-dev] [PATCH] cso: add point rasterization sanity check assertion

[Marek Olšák]

On Mon, Dec 11, 2017 at 10:41 PM, Roland Scheidegger  wrote:
> Am 11.12.2017 um 18:42 schrieb Brian Paul:
>> ---
>>  src/gallium/auxiliary/cso_cache/cso_context.c | 5 +
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c 
>> b/src/gallium/auxiliary/cso_cache/cso_context.c
>> index df5543c..dd9821e 100644
>> --- a/src/gallium/auxiliary/cso_cache/cso_context.c
>> +++ b/src/gallium/auxiliary/cso_cache/cso_context.c
>> @@ -592,6 +592,11 @@ enum pipe_error cso_set_rasterizer(struct cso_context 
>> *ctx,
>> (void*)templ, 
>> key_size);
>> void *handle = NULL;
>>
>> +   /* We can't have both point_quad_rasterization (sprites) and point_smooth
>> +* (round AA points) enabled at the same time.
>> +*/
>> +   assert(!(templ->point_quad_rasterization && templ->point_smooth));
>> +
>> if (cso_hash_iter_is_null(iter)) {
>>struct cso_rasterizer *cso = MALLOC(sizeof(struct cso_rasterizer));
>>if (!cso)
>>
>
> I'm ok with not allowing it, but it contradicts the gallium docs (which
> basically specify that point_quad_rasterization takes precedence over
> point_smooth). Albeit in another paragraph, the docs also state it's an
> error for mismatches in these states, so I suppose it's ok, but probably
> a doc clarification would be nice.
> Either way,
> Reviewed-by: Roland Scheidegger 

My understanding is that point_quad_rasterization enables
sprite_coord_enable and TGSI_SEMANTIC_PCOORD.

Likewise, AA points are basically point sprites where the shader
computes the alpha channel for blending AA points manually and/or
kills pixels, but the shader needs sprite coordinates for that.

In all cases, the point-quad rasterization can't be disabled. Only the
enablement of sprite coordinates can be controlled (in AMD and NV
GPUs).

Marek
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 19/25] mesa/glspirv: Add a _mesa_spirv_link_shaders() placeholder

[Timothy Arceri]

On 07/12/17 20:59, Eduardo Lima Mitev wrote:

On 12/07/2017 05:51 AM, Timothy Arceri wrote:

Please squash this with patch 22 tis is just code churn.



Ok, this makes sense, though I will have to re-order a bit the patches
to keep each single one building fine.


None of the patches in between seem to use it so it should be fine



I the squashed result would keep your R-b from patch 22, right?


Correct :)



thnaks,
Eduardo


On 01/12/17 04:28, Eduardo Lima Mitev wrote:

This will be the equivalent to link_shaders() from
src/compiler/glsl/linker.cpp, but for SPIR-V programs.
---
   src/mesa/main/glspirv.c | 10 ++
   src/mesa/main/glspirv.h |  4 
   2 files changed, 14 insertions(+)

diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c
index 18710c0d8fc..e533853f7fa 100644
--- a/src/mesa/main/glspirv.c
+++ b/src/mesa/main/glspirv.c
@@ -104,6 +104,16 @@ _mesa_spirv_shader_binary(struct gl_context *ctx,
  }
   }
   +void
+_mesa_spirv_link_shaders(struct gl_context *ctx, struct
gl_shader_program *prog)
+{
+   /* @TODO: This is a placeholder for the equivalent of
+    * compiler/glsl/linker.cpp::link_shaders() but for SPIR-V.
+    */
+   prog->data->LinkStatus = linking_success;
+   prog->data->Validated = false;
+}
+
   void GLAPIENTRY
   _mesa_SpecializeShaderARB(GLuint shader,
     const GLchar *pEntryPoint,
diff --git a/src/mesa/main/glspirv.h b/src/mesa/main/glspirv.h
index ba281f68bef..0f03b75c111 100644
--- a/src/mesa/main/glspirv.h
+++ b/src/mesa/main/glspirv.h
@@ -76,6 +76,10 @@ _mesa_spirv_shader_binary(struct gl_context *ctx,
     unsigned n, struct gl_shader **shaders,
     const void* binary, size_t length);
   +void
+_mesa_spirv_link_shaders(struct gl_context *ctx,
+ struct gl_shader_program *prog);
+
   /**
    * \name API functions
    */






___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 13/25] spirv_extensions: add list of extensions and to_string method

[Timothy Arceri]

I might be blind but in which patch does this end up being used?

Also this and the following patches seem to reinvent a system for 
exposing extension support. Is there a good reason for not simply 
expanding extensions_table.h to support tracking the spriv extensions?


On 01/12/17 04:28, Eduardo Lima Mitev wrote:

From: Alejandro Piñeiro 

Ideally this should be generated somehow. One option would be gather
all the extension dependencies listed on the core grammar, but there
would be the possibility of not including some of the extensions.

Note that spirv-tools is doing it just slightly better, as it has a
hardcoded list of extensions manually took from the registry, that
they parse to get the enum and the to_string method (see
generate_grammar_tables.py).

v2:
   * Use a macro to improve readability. (Tapani Pälli)
   * Add unreachable on the switch, no default (Eric Engestrom)
   * No typedef enum (Ian Romanick)
   * Sort extensions names (Ian Romanick)
   * Don't add extensions unlikely to be supported by Mesa at any point
 (Ian Romanick)
---
  src/compiler/Makefile.sources |  2 ++
  src/compiler/spirv/spirv_extensions.c | 46 +++
  src/compiler/spirv/spirv_extensions.h | 51 +++
  3 files changed, 99 insertions(+)
  create mode 100644 src/compiler/spirv/spirv_extensions.c
  create mode 100644 src/compiler/spirv/spirv_extensions.h

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 2ab8e163a26..f198456c751 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -293,6 +293,8 @@ SPIRV_FILES = \
spirv/GLSL.std.450.h \
spirv/nir_spirv.h \
spirv/spirv.h \
+   spirv/spirv_extensions.c \
+   spirv/spirv_extensions.h \
spirv/spirv_info.h \
spirv/spirv_to_nir.c \
spirv/vtn_alu.c \
diff --git a/src/compiler/spirv/spirv_extensions.c 
b/src/compiler/spirv/spirv_extensions.c
new file mode 100644
index 000..f50f87b52e1
--- /dev/null
+++ b/src/compiler/spirv/spirv_extensions.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "spirv.h"
+#include "spirv_extensions.h"
+
+const char *
+spirv_extensions_to_string(enum SpvExtension ext)
+{
+#define STR(x) case x: return #x;
+   switch (ext) {
+   STR(SPV_KHR_16bit_storage);
+   STR(SPV_KHR_device_group);
+   STR(SPV_KHR_multiview);
+   STR(SPV_KHR_shader_ballot);
+   STR(SPV_KHR_shader_draw_parameters);
+   STR(SPV_KHR_storage_buffer_storage_class);
+   STR(SPV_KHR_subgroup_vote);
+   STR(SPV_KHR_variable_pointers);
+   case SPV_EXTENSIONS_COUNT:
+  unreachable("Unknown SPIR-V extension");
+   }
+#undef STR
+
+   return "unknown";
+}
diff --git a/src/compiler/spirv/spirv_extensions.h 
b/src/compiler/spirv/spirv_extensions.h
new file mode 100644
index 000..0568132a517
--- /dev/null
+++ b/src/compiler/spirv/spirv_extensions.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHA

Re: [Mesa-dev] [PATCH 01/10] mapi: autotools: remove unused MAPI_FILES file list

[Ian Romanick]

Patches 1, 2, and 3 are

Reviewed-by: Ian Romanick 

I'm going to send a trivial nit on patch 4, and I'll try to look at the
others later.

On 12/07/2017 09:07 AM, Emil Velikov wrote:
> From: Emil Velikov 
> 
> The sole user was OpenVG, which was removed couple of years ago.
> 
> Signed-off-by: Emil Velikov 
> ---
>  src/mapi/Makefile.sources | 11 ---
>  1 file changed, 11 deletions(-)
> 
> diff --git a/src/mapi/Makefile.sources b/src/mapi/Makefile.sources
> index 5647158e3da..4b83caa8ed2 100644
> --- a/src/mapi/Makefile.sources
> +++ b/src/mapi/Makefile.sources
> @@ -2,9 +2,6 @@
>  #
>  # mapi may be used in several ways
>  #
> -#  - In default mode, mapi implements the interface defined by mapi.h.  To 
> use
> -#this mode, compile MAPI_FILES.
> -#
>  #  - In util mode, mapi provides utility functions for use with glapi.  To 
> use
>  #this mode, compile MAPI_UTIL_FILES with MAPI_MODE_UTIL defined.
>  #
> @@ -30,14 +27,6 @@ MAPI_BRIDGE_FILES = \
>   entry_ppc64le_tsd.h \
>   mapi_tmp.h
>  
> -MAPI_FILES = \
> - entry.c \
> - stub.c \
> - stub.h \
> - table.c \
> - table.h \
> - $(MAPI_UTIL_FILES)
> -
>  MAPI_GLAPI_FILES = \
>   entry.c \
>   mapi_glapi.c \
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 04/10] swrast: remove non-applicable GLX_SWAP_COPY_OML comment

[Ian Romanick]

On 12/07/2017 09:07 AM, Emil Velikov wrote:
> From: Emil Velikov 
> 
> Noticed while skimming for GLX_ instances i the dri codebase.

in

With that fixed, this patch is also

Reviewed-by: Ian Romanick 

> Comment is completely off and was in such a state since day 1.
> 
> Signed-off-by: Emil Velikov 
> ---
>  src/mesa/drivers/dri/swrast/swrast.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/swrast/swrast.c 
> b/src/mesa/drivers/dri/swrast/swrast.c
> index 4bee01ad308..8084be64393 100644
> --- a/src/mesa/drivers/dri/swrast/swrast.c
> +++ b/src/mesa/drivers/dri/swrast/swrast.c
> @@ -223,9 +223,6 @@ swrastFillInModes(__DRIscreen *psp,
>  unsigned back_buffer_factor;
>  mesa_format format;
>  
> -/* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
> - * support pageflipping at all.
> - */
>  static const GLenum back_buffer_modes[] = {
>   __DRI_ATTRIB_SWAP_NONE, __DRI_ATTRIB_SWAP_UNDEFINED
>  };
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 08/29] anv/cmd_buffer: Recurse in transition_color_buffer instead of falling through

[Nanley Chery]

On Mon, Dec 11, 2017 at 03:57:58PM -0800, Nanley Chery wrote:
> On Mon, Nov 27, 2017 at 07:05:58PM -0800, Jason Ekstrand wrote:
> > ---
> >  src/intel/vulkan/genX_cmd_buffer.c | 17 -
> >  1 file changed, 8 insertions(+), 9 deletions(-)
> > 
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> > b/src/intel/vulkan/genX_cmd_buffer.c
> > index 0c1ae83..be717eb 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -719,20 +719,19 @@ transition_color_buffer(struct anv_cmd_buffer 
> > *cmd_buffer,
> >if (image->samples == 1 &&
> >image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_E &&
> >final_layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
> > - /* The CCS_D buffer may not be enabled in the final layout. 
> > Continue
> > -  * executing this function to perform a resolve.
> > + /* The CCS_D buffer may not be enabled in the final layout. Call 
> > this
> > +  * function again with a initial layout of 
> > COLOR_ATTACHMENT_OPTIMAL
> > +  * to perform a resolve.
> >*/
> >anv_perf_warn(cmd_buffer->device->instance, image,
> >  "Performing an additional resolve for CCS_D layout 
> > "
> >  "transition. Consider always leaving it on or "
> >  "performing an ambiguation pass.");
> > -  } else {
> > - /* Writes in the final layout will be aware of the auxiliary 
> > buffer.
> > -  * In addition, the clear buffer entries and the auxiliary buffers
> > -  * have been populated with values that will result in correct
> > -  * rendering.
> > -  */
> > - return;
> 
> By deleting this else, we have to build the command buffer for a no-op
> resolve if the image has a CCS_E buffer. Perhaps this would fit better
> in the next patch?
> 

Actually, the next patch doesn't seem to fix this issue...

-Nanley

> -Nanley
> 
> > + transition_color_buffer(cmd_buffer, image, aspect,
> > + base_level, level_count,
> > + base_layer, layer_count,
> > + VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL,
> > + final_layout);
> >}
> > } else if (initial_layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
> >/* Resolves are only necessary if the subresource may contain blocks
> > -- 
> > 2.5.0.400.gff86faf
> > 
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 6/8] spirv: Add better parameter validation for vector

[Ian Romanick]

Reviewed-by: Ian Romanick 

On 12/11/2017 03:13 PM, Jason Ekstrand wrote:
> ---
>  src/compiler/spirv/spirv_to_nir.c | 16 +---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/src/compiler/spirv/spirv_to_nir.c 
> b/src/compiler/spirv/spirv_to_nir.c
> index 82e5c8c..c5d6131 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -934,7 +934,11 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
>struct vtn_type *base = vtn_value(b, w[2], vtn_value_type_type)->type;
>unsigned elems = w[3];
>  
> -  vtn_assert(glsl_type_is_scalar(base->type));
> +  vtn_fail_if(base->base_type != vtn_base_type_scalar,
> +  "Base type for OpTypeVector must be a scalar");
> +  vtn_fail_if(elems < 2 || elems > 4,
> +  "Invalid component count for OpTypeVector");
> +
>val->type->base_type = vtn_base_type_vector;
>val->type->type = glsl_vector_type(glsl_get_base_type(base->type), 
> elems);
>val->type->length = elems;
> @@ -947,12 +951,18 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
>struct vtn_type *base = vtn_value(b, w[2], vtn_value_type_type)->type;
>unsigned columns = w[3];
>  
> -  vtn_assert(glsl_type_is_vector(base->type));
> +  vtn_fail_if(base->base_type != vtn_base_type_vector,
> +  "Base type for OpTypeMatrix must be a vector");
> +  vtn_fail_if(columns < 2 || columns > 4,
> +  "Invalid column count for OpTypeMatrix");
> +
>val->type->base_type = vtn_base_type_matrix;
>val->type->type = glsl_matrix_type(glsl_get_base_type(base->type),
>   
> glsl_get_vector_elements(base->type),
>   columns);
> -  vtn_assert(!glsl_type_is_error(val->type->type));
> +  vtn_fail_if(glsl_type_is_error(val->type->type),
> +  "Unsupported base type for OpTypeMatrix");
> +  assert(!glsl_type_is_error(val->type->type));
>val->type->length = columns;
>val->type->array_element = base;
>val->type->row_major = false;
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 08/29] anv/cmd_buffer: Recurse in transition_color_buffer instead of falling through

[Nanley Chery]

On Mon, Nov 27, 2017 at 07:05:58PM -0800, Jason Ekstrand wrote:
> ---
>  src/intel/vulkan/genX_cmd_buffer.c | 17 -
>  1 file changed, 8 insertions(+), 9 deletions(-)
> 
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 0c1ae83..be717eb 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -719,20 +719,19 @@ transition_color_buffer(struct anv_cmd_buffer 
> *cmd_buffer,
>if (image->samples == 1 &&
>image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_E &&
>final_layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
> - /* The CCS_D buffer may not be enabled in the final layout. Continue
> -  * executing this function to perform a resolve.
> + /* The CCS_D buffer may not be enabled in the final layout. Call 
> this
> +  * function again with a initial layout of COLOR_ATTACHMENT_OPTIMAL
> +  * to perform a resolve.
>*/
>anv_perf_warn(cmd_buffer->device->instance, image,
>  "Performing an additional resolve for CCS_D layout "
>  "transition. Consider always leaving it on or "
>  "performing an ambiguation pass.");
> -  } else {
> - /* Writes in the final layout will be aware of the auxiliary buffer.
> -  * In addition, the clear buffer entries and the auxiliary buffers
> -  * have been populated with values that will result in correct
> -  * rendering.
> -  */
> - return;

By deleting this else, we have to build the command buffer for a no-op
resolve if the image has a CCS_E buffer. Perhaps this would fit better
in the next patch?

-Nanley

> + transition_color_buffer(cmd_buffer, image, aspect,
> + base_level, level_count,
> + base_layer, layer_count,
> + VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL,
> + final_layout);
>}
> } else if (initial_layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
>/* Resolves are only necessary if the subresource may contain blocks
> -- 
> 2.5.0.400.gff86faf
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/2] st/glsl_to_tgsi: Add support for SYSTEM_VALUE_BASE_VERTEX_ID

[Kenneth Graunke]

On Wednesday, November 22, 2017 6:03:25 AM PST Neil Roberts wrote:
> SYSTEM_VALUE_BASE_VERTEX has changed to be the correct value for
> gl_BaseVertex, which means it will be zero when used with a
> non-indexed call. The new BASE_VERTEX_ID value can be used as before
> as an offset to calculate a value for gl_VertexID. These values should
> be different, but this patch just makes them same for now in order to
> at least retain the previous behaviour and not break gl_BaseVertexID
> and gl_VertexID entirely on radeonsi.
> 
> Note, this hasn’t been tested apart from to verify that it compiles.
> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 0772b73..3dfed19 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -5385,6 +5385,11 @@ _mesa_sysval_to_semantic(unsigned sysval)
> case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
>return TGSI_SEMANTIC_VERTEXID_NOBASE;
> case SYSTEM_VALUE_BASE_VERTEX:
> +   case SYSTEM_VALUE_BASE_VERTEX_ID:
> +  /* FIXME: These two values are actually supposed to be different. The
> +   * one used for gl_BaseVertex is supposed to be zero when a non-indexed
> +   * draw call is used.
> +   */
>return TGSI_SEMANTIC_BASEVERTEX;
> case SYSTEM_VALUE_BASE_INSTANCE:
>return TGSI_SEMANTIC_BASEINSTANCE;
> 

I don't think altering TGSI should be necessary.  Drivers using TGSI
aren't using the NIR-based gl_VertexID lowering - they're using the old
GLSL IR based path, which for better or worse continues using the old
SYSTEM_VALUE_BASEVERTEX path.  So, nothing should break here.  (It may
have already been broken, but we're not making it worse.)

--Ken


signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 07/29] anv/image: Support color aspects in layout_to_aux_usage

[Nanley Chery]

On Mon, Nov 27, 2017 at 07:05:57PM -0800, Jason Ekstrand wrote:
> ---
>  src/intel/vulkan/anv_image.c | 48 
> ++--
>  1 file changed, 29 insertions(+), 19 deletions(-)
> 

This patch is
Reviewed-by: Nanley Chery 

> diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
> index 561da28..7e89f75 100644
> --- a/src/intel/vulkan/anv_image.c
> +++ b/src/intel/vulkan/anv_image.c
> @@ -748,12 +748,6 @@ anv_layout_to_aux_usage(const struct gen_device_info * 
> const devinfo,
> /* Stencil has no aux */
> assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);
>  
> -   /* The following switch currently only handles depth stencil aspects.
> -* TODO: Handle the color aspect.
> -*/
> -   if (image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV)
> -  return image->planes[plane].aux_usage;
> -
> switch (layout) {
>  
> /* Invalid Layouts */
> @@ -773,28 +767,38 @@ anv_layout_to_aux_usage(const struct gen_device_info * 
> const devinfo,
>  
>  
> /* Transfer Layouts
> -*
> -* This buffer could be a depth buffer used in a transfer operation. BLORP
> -* currently doesn't use HiZ for transfer operations so we must use the 
> main
> -* buffer for this layout. TODO: Enable HiZ in BLORP.
>  */
> case VK_IMAGE_LAYOUT_GENERAL:
> case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
> case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
> -  return ISL_AUX_USAGE_NONE;
> +  if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
> + /* This buffer could be a depth buffer used in a transfer operation.
> +  * BLORP currently doesn't use HiZ for transfer operations so we 
> must
> +  * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
> +  */
> + assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_HIZ);
> + return ISL_AUX_USAGE_NONE;
> +  } else {
> + assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
> + return image->planes[plane].aux_usage;
> +  }
>  
>  
> /* Sampling Layouts */
> case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
> +   case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR:
>assert((image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
>/* Fall-through */
> case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
> -   case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR:
> -  assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
> -  if (anv_can_sample_with_hiz(devinfo, image))
> - return ISL_AUX_USAGE_HIZ;
> -  else
> - return ISL_AUX_USAGE_NONE;
> +  if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
> + if (anv_can_sample_with_hiz(devinfo, image))
> +return ISL_AUX_USAGE_HIZ;
> + else
> +return ISL_AUX_USAGE_NONE;
> +  } else {
> + return image->planes[plane].aux_usage;
> +  }
> +
>  
> case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR:
>assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
> @@ -819,8 +823,14 @@ anv_layout_to_aux_usage(const struct gen_device_info * 
> const devinfo,
>  
> /* Rendering Layouts */
> case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
> -  assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
> -  unreachable("Color images are not yet supported.");
> +  assert(aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
> +  if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE) {
> + assert(image->samples == 1);
> + return ISL_AUX_USAGE_CCS_D;
> +  } else {
> + assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_D);
> + return image->planes[plane].aux_usage;
> +  }
>  
> case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
> case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR:
> -- 
> 2.5.0.400.gff86faf
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] freedreno: Update to handle rename of the base vertex ID intrinsic

[Kenneth Graunke]

On Wednesday, November 22, 2017 6:03:24 AM PST Neil Roberts wrote:
> The old intrinsic called base_vertex that is used to add to
> gl_VertexID is now called base_vertex_id so that base_vertex can be
> used for the value of gl_BaseVertex, which is different. As far as I
> can tell freedreno doesn’t support GL_ARB_shader_draw_parameters so it
> won’t need any changes to generate the new base_vertex intrinsic.
> 
> I haven’t tested this at all apart from to verify that it compiles.
> 
> Cc: Rob Clark 
> ---
>  src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c 
> b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
> index da4aeaa..e6fbf45 100644
> --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
> +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
> @@ -2071,10 +2071,10 @@ emit_intrinsic(struct ir3_context *ctx, 
> nir_intrinsic_instr *intr)
>   ctx->ir->outputs[n] = src[i];
>   }
>   break;
> - case nir_intrinsic_load_base_vertex:
> + case nir_intrinsic_load_base_vertex_id:
>   if (!ctx->basevertex) {
>   ctx->basevertex = create_driver_param(ctx, 
> IR3_DP_VTXID_BASE);
> - add_sysval_input(ctx, SYSTEM_VALUE_BASE_VERTEX,
> + add_sysval_input(ctx, SYSTEM_VALUE_BASE_VERTEX_ID,
>   ctx->basevertex);
>   }
>   dst[0] = ctx->basevertex;
> 

Hi Neil,

I think you should change a3xx/fd3_emit.c and a4xx/fd4_emit.c from
SYSTEM_VALUE_BASE_VERTEX to SYSTEM_VALUE_FIRST_VERTEX as well.

Presumably, we want to squash these changes into
"nir: Offset vertex_id by first_vertex instead of base_vertex"
to avoid intermediate breakage.

I have an a3xx I can try and get going again to test this if needed.

--Ken


signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] spirv: Allow ignoring decorations for workgroup variables

[Jordan Justen]

Reviewed-by: Jordan Justen 

On 2017-12-11 15:34:08, Jason Ekstrand wrote:
> Since we switched over to lowering SLM access directly in SPIR-V -> NIR,
> we no longer have vtn_variables for SLM.  It's all safe as with UBOs and
> SSBOs but we need to let it through in the assert.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104213
> Fixes: 8761a04d0d9332d9c0c99164faf855fc3c741f7c
> ---
>  src/compiler/spirv/vtn_variables.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/src/compiler/spirv/vtn_variables.c 
> b/src/compiler/spirv/vtn_variables.c
> index 671f18a..745269b 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1533,7 +1533,9 @@ var_decoration_cb(struct vtn_builder *b, struct 
> vtn_value *val, int member,
>*/
>   vtn_assert(vtn_var->mode == vtn_variable_mode_ubo ||
>  vtn_var->mode == vtn_variable_mode_ssbo ||
> -vtn_var->mode == vtn_variable_mode_push_constant);
> +vtn_var->mode == vtn_variable_mode_push_constant ||
> +(vtn_var->mode == vtn_variable_mode_workgroup &&
> + b->options->lower_workgroup_access_to_offsets));
>}
> }
>  }
> -- 
> 2.5.0.400.gff86faf
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] spirv: Allow ignoring decorations for workgroup variables

[Jason Ekstrand]

Since we switched over to lowering SLM access directly in SPIR-V -> NIR,
we no longer have vtn_variables for SLM.  It's all safe as with UBOs and
SSBOs but we need to let it through in the assert.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104213
Fixes: 8761a04d0d9332d9c0c99164faf855fc3c741f7c
---
 src/compiler/spirv/vtn_variables.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 671f18a..745269b 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1533,7 +1533,9 @@ var_decoration_cb(struct vtn_builder *b, struct vtn_value 
*val, int member,
   */
  vtn_assert(vtn_var->mode == vtn_variable_mode_ubo ||
 vtn_var->mode == vtn_variable_mode_ssbo ||
-vtn_var->mode == vtn_variable_mode_push_constant);
+vtn_var->mode == vtn_variable_mode_push_constant ||
+(vtn_var->mode == vtn_variable_mode_workgroup &&
+ b->options->lower_workgroup_access_to_offsets));
   }
}
 }
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 103699] Latest mesa breaks firefox on kde plasma with compositing on

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103699

--- Comment #27 from Germano Massullo  ---
Screenshots of malfunction
https://bugzilla.mozilla.org/attachment.cgi?id=8932561
https://bugzilla.mozilla.org/attachment.cgi?id=8932563(In reply to Germano
Massullo from comment #21)
> Hi there my system has
> - Mesa 17.2.4;
> - KDE Plasma 5.10
> on Fedora 26 and I think I am experiencing this problem. I opened a Firefox
> bugreport before finding out about this Mesa bugreport
> 
> https://bugzilla.mozilla.org/show_bug.cgi?id=1421353
> 
> # lspci -k | grep -iA 3 vga
> 01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI]
> Ellesmere [Radeon RX 470/480/570/580] (rev c7)
> Subsystem: XFX Pine Group Inc. Radeon RX 480
> Kernel driver in use: amdgpu
> Kernel modules: amdgpu

Just opened a similar bugreport for AMDGPU
https://bugs.freedesktop.org/show_bug.cgi?id=104216

-- 
You are receiving this mail because:
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] Gallium ARB_get_program_binary support

[Mike Lothian]

I'll check that when I'm next home

On Mon, 11 Dec 2017 at 21:19 Timothy Arceri  wrote:

> On 12/12/17 08:13, Mike Lothian wrote:
> > Tested with Dead Island, Dirt Rally and Serious Sam BFG (which I believe
> > uses this extension)
> >
> > Do you know any other games that use this?
>
> I believe Dying Light uses it also.
>
>
> >
> > On Mon, 11 Dec 2017 at 02:17 Dieter Nützel  > > wrote:
> >
> > For the V2 series:
> >
> > Tested-by: Dieter Nützel  > >
> > and
> > Acked-by: Dieter Nützel  > >
> > if this is worth from my side.
> >
> > on RX580 8GB
> >
> > with DiRT Rally, UH, UV, Blender 2.79, smoketest, F1 2017 (Vulkan),
> > glmark2 (parallel with
> > OpenCL (/opt/opencl-example>./run_tests.sh))
> >
> > Dieter
> >
> > Am 10.12.2017 23:06, schrieb Timothy Arceri:
> >  > On 10/12/17 17:56, Dieter Nützel wrote:
> >  >> First BAD commit is patch [PATCH 2/5].
> >  >> https://patchwork.freedesktop.org/patch/192329/
> >  >
> >  >
> >  > Thanks! I've sent a V2 of that patch, I've also confirmed DiRT
> Rally
> >  > no longer segfaults at start-up.
> >  >
> >  >> With it I get this in dmesg:
> >  >>
> >  >> [34581.836122] OGL_Dispatch_33[4887]: segfault at 0 ip
> >  >> 9ebeafda sp a95580d4 error 4 in
> >  >> libc-2.26.so [7f6afcaf7000+1b1000]
> >  >> [34706.224082] perf: interrupt took too long (5089 > 4913),
> lowering
> >  >> kernel.perf_event_max_sample_rate to 39250
> >  >> [34918.80] OGL_Dispatch_33[19897]: segfault at 0 ip
> >  >> d9adbd7a sp e6e1b769 error 4 in
> >  >> libc-2.26.so [7f2fc4777000+1b1000]
> >  >> [35148.576818] OGL_Dispatch_33[2934]: segfault at 0 ip
> >  >> 78a41511 sp 1f147296 error 4 in
> >  >> libc-2.26.so [7ff11fa23000+1b1000]
> >  >> [35172.410621] OGL_Dispatch_33[3371]: segfault at 0 ip
> >  >> ef37ae37 sp 99ce37ab error 4 in
> >  >> libc-2.26.so [7f0af78ff000+1b1000]
> >  >> [35383.940291] OGL_Dispatch_33[18591]: segfault at 0 ip
> >  >> 813f92d2 sp 7c9305e7 error 4 in
> >  >> libc-2.26.so [7fee87426000+1b1000]
> >  >>
> >  >> It's in the morning, now.
> >  >> Here in 'OLD' Germany, near Hamburg.
> >  >> Good night! ;-)
> >  >>
> >  >> Dieter
> >  >>
> >  >> Am 10.12.2017 05:15, schrieb Timothy Arceri:
> >  >>> Hi, as always thanks for testing :)
> >  >>>
> >  >>> Are you able to find out which patch causes the crash? I'm
> > curious if
> >  >>> its the ARB_get_program_binary support or if I break the regular
> >  >>> cache
> >  >>> when re-factoring.
> >  >>>
> >  >>> Thanks,
> >  >>> Tim
> >  >>>
> >  >>> On 09/12/17 15:58, Dieter Nützel wrote:
> >   Hello Tim,
> >  
> >   first time ever, that I got a real regression with your GREAT
> > work.
> >   ;-)
> >  
> >   DiRT Rally sig fault (SIGSEGV(11) with this series.
> >   (see attachment)
> >  
> >   Bad cache hit re-read?
> >   Removing .cache/mesa_shader_cache do not help.
> >   Searching for the rigth Feral (Steam?) cache dir. - Alex/James?
> >  
> >   Then I'll have to find which of the five did it.
> >  
> >    From the log I got this:
> >   [1209/054156:ERROR:sandbox_linux.cc(325)] InitializeSandbox()
> > called
> >   with multiple threads in process gpu-process
> >   [1209/054157:INFO:CONSOLE(0)] "The specified value '!' does not
> >   conform to the required format.  The format is '#rrggbb' where
> rr,
> >   gg, bb are two-digit hexadecimal numbers.", source:
> >  
> >
>  
> file://localhost/home1/alexander/My%20Games/Steam/steamapps/common/DiRT%20Rally/share/FeralUI/PGOW/Core/feralUI.html
> >   (0)
> >   Installing breakpad exception handler for
> >   appid(steam)/version(1509425745)
> >   [1209/054158:INFO:CONSOLE(0)] "Synchronous XMLHttpRequest on
> the
> >   main thread is deprecated because of its detrimental effects
> > to the
> >   end user's experience. For more help, check
> >   http://xhr.spec.whatwg.org/.";, source:  (0)
> >   [1209/054208:WARNING:x11_util.cc(1490)] X error received:
> serial
> >   4814, error_code 3 (BadWindow (invalid Window parameter)),
> >   request_code 4, minor_code 0 (X_DestroyWindow)
> >   SDL2 initialised [built against 2.0.5, running with 2.0.5]
> >   DirtRally: dumped to
> >   "/home/alexander/.local/share/feral-interactive/DiRT
> >   Rally/crashes/2363a778-c194-621f-0f837dfb-191070fd.dmp"
> >

[Mesa-dev] [PATCH v2 6/8] spirv: Add better parameter validation for vector

[Jason Ekstrand]

---
 src/compiler/spirv/spirv_to_nir.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 82e5c8c..c5d6131 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -934,7 +934,11 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
   struct vtn_type *base = vtn_value(b, w[2], vtn_value_type_type)->type;
   unsigned elems = w[3];
 
-  vtn_assert(glsl_type_is_scalar(base->type));
+  vtn_fail_if(base->base_type != vtn_base_type_scalar,
+  "Base type for OpTypeVector must be a scalar");
+  vtn_fail_if(elems < 2 || elems > 4,
+  "Invalid component count for OpTypeVector");
+
   val->type->base_type = vtn_base_type_vector;
   val->type->type = glsl_vector_type(glsl_get_base_type(base->type), 
elems);
   val->type->length = elems;
@@ -947,12 +951,18 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
   struct vtn_type *base = vtn_value(b, w[2], vtn_value_type_type)->type;
   unsigned columns = w[3];
 
-  vtn_assert(glsl_type_is_vector(base->type));
+  vtn_fail_if(base->base_type != vtn_base_type_vector,
+  "Base type for OpTypeMatrix must be a vector");
+  vtn_fail_if(columns < 2 || columns > 4,
+  "Invalid column count for OpTypeMatrix");
+
   val->type->base_type = vtn_base_type_matrix;
   val->type->type = glsl_matrix_type(glsl_get_base_type(base->type),
  glsl_get_vector_elements(base->type),
  columns);
-  vtn_assert(!glsl_type_is_error(val->type->type));
+  vtn_fail_if(glsl_type_is_error(val->type->type),
+  "Unsupported base type for OpTypeMatrix");
+  assert(!glsl_type_is_error(val->type->type));
   val->type->length = columns;
   val->type->array_element = base;
   val->type->row_major = false;
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 7/8] spirv: Restructure the case loop in OpSwitch handling

[Ian Romanick]

On 12/11/2017 02:50 PM, Jason Ekstrand wrote:
> On Mon, Dec 11, 2017 at 10:08 AM, Ian Romanick  > wrote:
> 
> On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> > Instead of calling vtn_add_case for the default case and then looping,
> > add an is_default variable and do everything inside the loop. 
> This will
> > make the next commit easier.
> > ---
> >  src/compiler/spirv/vtn_cfg.c | 17 ++---
> >  1 file changed, 14 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/compiler/spirv/vtn_cfg.c
> b/src/compiler/spirv/vtn_cfg.c
> > index 25140ff..9d1ca84 100644
> > --- a/src/compiler/spirv/vtn_cfg.c
> > +++ b/src/compiler/spirv/vtn_cfg.c
> > @@ -425,9 +425,20 @@ vtn_cfg_walk_blocks(struct vtn_builder *b,
> struct list_head *cf_list,
> >           const uint32_t *branch_end =
> >              block->branch + (block->branch[0] >> SpvWordCountShift);
> >
> > -         vtn_add_case(b, swtch, break_block, block->branch[2], 0,
> true);
> > -         for (const uint32_t *w = block->branch + 3; w <
> branch_end; w += 2)
> > -            vtn_add_case(b, swtch, break_block, w[1], w[0], false);
> > +         bool is_default = true;
> > +         for (const uint32_t *w = block->branch + 2; w <
> branch_end;) {
> > +            uint32_t literal = 0;
> > +            if (!is_default) {
> > +               literal = *w;
> > +               w++;
> > +            }
> > +
> > +            uint32_t block_id = *w;
> > +            w++;
> 
> In other parts of Mesa, this would be
> 
>             const uint32_t block_id = *(w++);
> 
> Is that not the preferred style here too?  Having looked ahead at the
> next patch, I can see why the other dereference of w is not like this.
> 
> 
> Yeah, that's cleaner.  I've switched to that and rebased patch 8 on it.

Reviewed-by: Ian Romanick 

> > +
> > +            vtn_add_case(b, swtch, break_block, block_id,
> literal, is_default);
> > +            is_default = false;
> > +         }
> >
> >           /* Now, we go through and walk the blocks.  While we
> walk through
> >            * the blocks, we also gather the much-needed fall-through
> >
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 7/8] spirv: Restructure the case loop in OpSwitch handling

[Jason Ekstrand]

On Mon, Dec 11, 2017 at 10:08 AM, Ian Romanick  wrote:

> On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> > Instead of calling vtn_add_case for the default case and then looping,
> > add an is_default variable and do everything inside the loop.  This will
> > make the next commit easier.
> > ---
> >  src/compiler/spirv/vtn_cfg.c | 17 ++---
> >  1 file changed, 14 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
> > index 25140ff..9d1ca84 100644
> > --- a/src/compiler/spirv/vtn_cfg.c
> > +++ b/src/compiler/spirv/vtn_cfg.c
> > @@ -425,9 +425,20 @@ vtn_cfg_walk_blocks(struct vtn_builder *b, struct
> list_head *cf_list,
> >   const uint32_t *branch_end =
> >  block->branch + (block->branch[0] >> SpvWordCountShift);
> >
> > - vtn_add_case(b, swtch, break_block, block->branch[2], 0, true);
> > - for (const uint32_t *w = block->branch + 3; w < branch_end; w
> += 2)
> > -vtn_add_case(b, swtch, break_block, w[1], w[0], false);
> > + bool is_default = true;
> > + for (const uint32_t *w = block->branch + 2; w < branch_end;) {
> > +uint32_t literal = 0;
> > +if (!is_default) {
> > +   literal = *w;
> > +   w++;
> > +}
> > +
> > +uint32_t block_id = *w;
> > +w++;
>
> In other parts of Mesa, this would be
>
> const uint32_t block_id = *(w++);
>
> Is that not the preferred style here too?  Having looked ahead at the
> next patch, I can see why the other dereference of w is not like this.
>

Yeah, that's cleaner.  I've switched to that and rebased patch 8 on it.


> > +
> > +vtn_add_case(b, swtch, break_block, block_id, literal,
> is_default);
> > +is_default = false;
> > + }
> >
> >   /* Now, we go through and walk the blocks.  While we walk
> through
> >* the blocks, we also gather the much-needed fall-through
> >
>
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 6/8] spirv: Add better parameter validation for vector and matrix types

[Jason Ekstrand]

On Mon, Dec 11, 2017 at 10:05 AM, Ian Romanick  wrote:

> On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> > ---
> >  src/compiler/spirv/spirv_to_nir.c | 14 +++---
> >  1 file changed, 11 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/compiler/spirv/spirv_to_nir.c
> b/src/compiler/spirv/spirv_to_nir.c
> > index 11c8c2a..4b93b11 100644
> > --- a/src/compiler/spirv/spirv_to_nir.c
> > +++ b/src/compiler/spirv/spirv_to_nir.c
> > @@ -934,7 +934,11 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
> >struct vtn_type *base = vtn_value(b, w[2],
> vtn_value_type_type)->type;
> >unsigned elems = w[3];
> >
> > -  vtn_assert(glsl_type_is_scalar(base->type));
> > +  vtn_fail_if(base->base_type != vtn_base_type_scalar,
> > +  "Base type for OpTypeVector must be a scalar");
> > +  vtn_fail_if(elems < 2 || elems > 4,
> > +  "Invalid component count for OpTypeVector");
> > +
> >val->type->base_type = vtn_base_type_vector;
> >val->type->type = glsl_vector_type(glsl_get_base_type(base->type),
> elems);
> >val->type->length = elems;
> > @@ -947,12 +951,16 @@ vtn_handle_type(struct vtn_builder *b, SpvOp
> opcode,
> >struct vtn_type *base = vtn_value(b, w[2],
> vtn_value_type_type)->type;
> >unsigned columns = w[3];
> >
> > -  vtn_assert(glsl_type_is_vector(base->type));
> > +  vtn_fail_if(columns < 2 || columns > 4,
> > +  "Invalid column count for OpTypeMatrix");
> > +
>
> I think we should still check glsl_type_is_vector here.  The
> glsl_type_is_error check below will catch that case, but we'll give a
> better error message with the explicit check here.
>

Sure.  I'll add something and send a v2.


> >val->type->base_type = vtn_base_type_matrix;
> >val->type->type = glsl_matrix_type(glsl_get_
> base_type(base->type),
> >   glsl_get_vector_elements(base-
> >type),
> >   columns);
> > -  vtn_assert(!glsl_type_is_error(val->type->type));
> > +  vtn_fail_if(glsl_type_is_error(val->type->type),
> > +  "Unsupported base type for OpTypeMatrix");
> > +  assert(!glsl_type_is_error(val->type->type));
> >val->type->length = columns;
> >val->type->array_element = base;
> >val->type->row_major = false;
> >
>
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/8] spirv: Add a prepass to set types on vtn_values

[Jason Ekstrand]

On Mon, Dec 11, 2017 at 11:13 AM, Ian Romanick  wrote:

> On 12/11/2017 10:50 AM, Jason Ekstrand wrote:
> > On Mon, Dec 11, 2017 at 9:50 AM, Ian Romanick  > > wrote:
> >
> > On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> > > This autogenerated pass will automatically find and set the type
> field
> > > on all vtn_values.  This way we always have the type and can use
> > it for
> > > validation and other checks.
> > > ---
> > >  src/compiler/Makefile.nir.am 
> >  |   4 +
> > >  src/compiler/nir/meson.build |  11 ++-
> > >  src/compiler/spirv/spirv_to_nir.c|   6 +-
> > >  src/compiler/spirv/vtn_gather_types_c.py | 125
> > +++
> > >  src/compiler/spirv/vtn_private.h |   4 +
> > >  5 files changed, 148 insertions(+), 2 deletions(-)
> > >  create mode 100644 src/compiler/spirv/vtn_gather_types_c.py
> > >
> > > diff --git a/src/compiler/Makefile.nir.am 
> > b/src/compiler/Makefile.nir.am 
> > > index 1533ee5..dd38c45 100644
> > > --- a/src/compiler/Makefile.nir.am 
> > > +++ b/src/compiler/Makefile.nir.am 
> > > @@ -56,6 +56,10 @@ spirv/spirv_info.c: spirv/spirv_info_c.py
> > spirv/spirv.core.grammar.json
> > >   $(MKDIR_GEN)
> > >   $(PYTHON_GEN) $(srcdir)/spirv/spirv_info_c.py
> > $(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false)
> > >
> > > +spirv/vtn_gather_types.c: spirv/vtn_gather_types_c.py
> > spirv/spirv.core.grammar.json
> > > + $(MKDIR_GEN)
> > > + $(PYTHON_GEN) $(srcdir)/spirv/vtn_gather_types_c.py
> > $(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false)
> > > +
> > >  noinst_PROGRAMS += spirv2nir
> > >
> > >  spirv2nir_SOURCES = \
> > > diff --git a/src/compiler/nir/meson.build
> > b/src/compiler/nir/meson.build
> > > index b61a077..5dd21e6 100644
> > > --- a/src/compiler/nir/meson.build
> > > +++ b/src/compiler/nir/meson.build
> > > @@ -72,6 +72,14 @@ spirv_info_c = custom_target(
> > >command : [prog_python2, '@INPUT0@', '@INPUT1@', '@OUTPUT@'],
> > >  )
> > >
> > > +vtn_gather_types_c = custom_target(
> > > +  'vtn_gather_types.c',
> > > +  input : files('../spirv/vtn_gather_types_c.py',
> > > +'../spirv/spirv.core.grammar.json'),
> > > +  output : 'vtn_gather_types.c',
> > > +  command : [prog_python2, '@INPUT0@', '@INPUT1@', '@OUTPUT@'],
> > > +)
> > > +
> > >  files_libnir = files(
> > >'nir.c',
> > >'nir.h',
> > > @@ -189,7 +197,8 @@ files_libnir = files(
> > >  libnir = static_library(
> > >'nir',
> > >[files_libnir, spirv_info_c, nir_opt_algebraic_c, nir_opcodes_c,
> > > -   nir_opcodes_h, nir_constant_expressions_c,
> nir_builder_opcodes_h],
> > > +   nir_opcodes_h, nir_constant_expressions_c,
> nir_builder_opcodes_h,
> > > +   vtn_gather_types_c],
> > >include_directories : [inc_common, inc_compiler,
> > include_directories('../spirv')],
> > >c_args : [c_vis_args, c_msvc_compat_args,
> no_override_init_args],
> > >link_with : libcompiler,
> > > diff --git a/src/compiler/spirv/spirv_to_nir.c
> > b/src/compiler/spirv/spirv_to_nir.c
> > > index a50b14d..a2426bc 100644
> > > --- a/src/compiler/spirv/spirv_to_nir.c
> > > +++ b/src/compiler/spirv/spirv_to_nir.c
> > > @@ -1261,7 +1261,6 @@ vtn_handle_constant(struct vtn_builder *b,
> > SpvOp opcode,
> > >  const uint32_t *w, unsigned count)
> > >  {
> > > struct vtn_value *val = vtn_push_value(b, w[2],
> > vtn_value_type_constant);
> > > -   val->type = vtn_value(b, w[1], vtn_value_type_type)->type;
> > > val->constant = rzalloc(b, nir_constant);
> > > switch (opcode) {
> > > case SpvOpConstantTrue:
> > > @@ -3268,6 +3267,8 @@ static bool
> > >  vtn_handle_variable_or_type_instruction(struct vtn_builder *b,
> > SpvOp opcode,
> > >  const uint32_t *w,
> > unsigned count)
> > >  {
> > > +   vtn_set_instruction_result_type(b, opcode, w, count);
> > > +
> > > switch (opcode) {
> > > case SpvOpSource:
> > > case SpvOpSourceContinued:
> > > @@ -3658,6 +3659,9 @@ spirv_to_nir(const uint32_t *words, size_t
> > word_count,
> > > words = vtn_foreach_instruction(b, words, word_end,
> > >
> >  vtn_handle_variable_or_type_instruction);
> > >
> > > +   /* Set types on all vtn_values */
> > > +   vtn_foreach_instruction(b, words, word_end,
> > vtn_set_instruction_result_type);
> > > +
> > > vtn_build_cfg(b, words, word_end);
> > >
> > > assert(b->entry_poin

Re: [Mesa-dev] [PATCH mesa] meson: add dep_thread to every lib that includes threads.h

[Dylan Baker]

Quoting Emil Velikov (2017-12-11 12:06:35)
> On 7 December 2017 at 17:25, Dylan Baker  wrote:
> > Quoting Emil Velikov (2017-12-07 08:40:27)
> >> On 7 December 2017 at 14:51, Eric Engestrom  
> >> wrote:
> >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104141
> >> > Signed-off-by: Eric Engestrom 
> >> > ---
> >> >  src/broadcom/meson.build| 2 +-
> >> >  src/gallium/auxiliary/meson.build   | 2 +-
> >> >  src/gallium/state_trackers/nine/meson.build | 1 +
> >> >  src/gallium/targets/xa/meson.build  | 2 +-
> >> >  src/gallium/targets/xvmc/meson.build| 2 +-
> >> >  src/gbm/meson.build | 2 +-
> >> >  src/intel/common/meson.build| 2 +-
> >> >  src/loader/meson.build  | 2 +-
> >> >  src/util/meson.build| 2 +-
> >> >  9 files changed, 9 insertions(+), 8 deletions(-)
> >> >
> >> I doubt we can continue and pretend to be libpthread.so free.
> >> To make it even funnier, depending on moon cycle or other fun factors,
> >> we could get the pthread dependency implicitly satisfied as one of the
> >> other shared libraries already pulls the library.
> >>
> >> So how about we simply append -pthread to CC/CXX with at global scope
> >> and drop the all the individual dependencies?
> >> It will safe us a few characters to type, plus will ensure that newly
> >> added binaries don't fall victim of the same issue.
> >
> > Absolutely not. The meson build has dep_thread for a reason, because meson
> > guarantees that calling `dependency('threads')` will always return the right
> > value for your platform, even if that platform is windows and doesn't have
> > pthreads at all (but does the right thing for cygwin).
> >
> I would recommend looking through clang/gcc. AFAICS any* platform/arch
> combo supported by Mesa handles -pthread and that toggle does the
> "right thing".
> Obviously that can seem a bit hacky, so a better way to avoid all the
> copy/paste is for meson to grow an option that allows folding the
> required cflags/libs with the compiler directive.

That's all fine, but the meson build is planning on supporting haiku and plain
windows (with msvc), neither of which have pthreads (haiku does, but it's not a
standalone library and you don't pass -pthreads to the compiler or linker and
it's an error to do so). macOS clang also warns when passing -pthreads to the
linker (but only the one shipped with xcode), not if you build clang yourself.

If you feel strongly about it, open a bug upstream and discuss it with upstream.
If they agree and add a mechanism to do so I'd be fine using it. 

> > The reason that we're running into this problem is as you guessed that some
> > dependencies pull in pthreads implicitly, for example LLVM, which is why 
> > we're
> > seeing this so often in gallium.
> >
> Precisely. Due to the combinatoric explosions things are bound to
> break again, hence my earlier suggestion.
> I doubt you or anyone on the team will be excited to see things break.

That's possible, obviously. I also think these sort of issues will work
themselves out fairly quickly, while I'm very concerned adding -pthread into the
list of arguments we pass unconditionally is going to break whole platforms in
subtle and hard to fix ways, and really goes against the philosophy of meson,
which is to solve these sort of problems in meson itself, rather than each build
system solving them again and again, usually incorrectly.

If we want to trot out the big hammer, I'd be happier just to add dep_thread to
every shared library and binary than trying to add the right combination of
-pthreads and -lpthreads for each platform ourselves to the C and C++ flags.

There's about 350 uses of pthread symbols in mesa itself, of that there are 56
unique files containing pthread symbols (some of which are generators), and of
that there are only 23 unique folders containing pthread symbols. I think that
getting this right is very doable.

I'll start auditing the meson build to see if there's any place that we're
missing passing pthreads directly.

Dylan

> 
> -Emil
> 
> * I've checked Cygwin, Solaris-like, BSD-like, Linuxen, Hurd and
> Android, on both 32 and 64bit x86, ARM and PPC.
> I believe msys/mingw should be fine as well, but I'm short on details.


signature.asc
Description: signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] i965/bufmgr: Add a helper to mark a BO as external

[Jason Ekstrand]

On Mon, Dec 11, 2017 at 12:08 PM, Emil Velikov 
wrote:

> On 21 November 2017 at 00:13, Andres Gomez  wrote:
> > Jason, this nominated series landed without mentioning any specific
> > stable queue.
> >
> > From what I'm seeing, both depend on 2c4097aff1b which didn't make it
> > for 17.2 so I'm dropping them for that queue.
> >
> This is a preparatory patch for the follow-up commit.
> With the latter addressing issue caused by
> 4b1e70cc57d7ff5f465544644b2180dee1490cee - only available in
> 17.4.0-dev.
>
> I believe the 17.2 and 17.3 series should be safe ;-)
>

This bug goes all the way back.  It interacts with the patch mentioned but
is not the same thing.  This patch (and the subsequent one) should probably
go back as far as brw_bufmgr does.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 5/7] nir: Offset vertex_id by first_vertex instead of base_vertex

[Marek Olšák]

On Mon, Dec 11, 2017 at 8:43 PM, Ian Romanick  wrote:
> On 12/04/2017 12:12 PM, Antia Puentes wrote:
>> From: Neil Roberts 
>>
>> base_vertex will be zero for non-indexed calls, but we need it to
>> include the ‘first’ parameter. This is true for both GL and Vulkan.
>>
>> I think this patch will also affect freedreno and radeonsi. I believe
>
> If you think a patch might break someone's driver, you should CC them on
> the patch... they're more likely to verify it that way.  Adding Marek
> and Rob. :)

On radeonsi with NIR, nir_intrinsic_load_base_vertex returns firstvertex.

nir_intrinsic_load_first_vertex is unhandled.

Marek
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] cso: add point rasterization sanity check assertion

[Roland Scheidegger]

Am 11.12.2017 um 18:42 schrieb Brian Paul:
> ---
>  src/gallium/auxiliary/cso_cache/cso_context.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c 
> b/src/gallium/auxiliary/cso_cache/cso_context.c
> index df5543c..dd9821e 100644
> --- a/src/gallium/auxiliary/cso_cache/cso_context.c
> +++ b/src/gallium/auxiliary/cso_cache/cso_context.c
> @@ -592,6 +592,11 @@ enum pipe_error cso_set_rasterizer(struct cso_context 
> *ctx,
> (void*)templ, 
> key_size);
> void *handle = NULL;
>  
> +   /* We can't have both point_quad_rasterization (sprites) and point_smooth
> +* (round AA points) enabled at the same time.
> +*/
> +   assert(!(templ->point_quad_rasterization && templ->point_smooth));
> +
> if (cso_hash_iter_is_null(iter)) {
>struct cso_rasterizer *cso = MALLOC(sizeof(struct cso_rasterizer));
>if (!cso)
> 

I'm ok with not allowing it, but it contradicts the gallium docs (which
basically specify that point_quad_rasterization takes precedence over
point_smooth). Albeit in another paragraph, the docs also state it's an
error for mismatches in these states, so I suppose it's ok, but probably
a doc clarification would be nice.
Either way,
Reviewed-by: Roland Scheidegger 
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] Gallium ARB_get_program_binary support

[Timothy Arceri]

On 12/12/17 08:13, Mike Lothian wrote:
Tested with Dead Island, Dirt Rally and Serious Sam BFG (which I believe 
uses this extension)


Do you know any other games that use this?


I believe Dying Light uses it also.




On Mon, 11 Dec 2017 at 02:17 Dieter Nützel > wrote:


For the V2 series:

Tested-by: Dieter Nützel mailto:die...@nuetzel-hh.de>>
and
Acked-by: Dieter Nützel mailto:die...@nuetzel-hh.de>>
if this is worth from my side.

on RX580 8GB

with DiRT Rally, UH, UV, Blender 2.79, smoketest, F1 2017 (Vulkan),
glmark2 (parallel with
OpenCL (/opt/opencl-example>./run_tests.sh))

Dieter

Am 10.12.2017 23:06, schrieb Timothy Arceri:
 > On 10/12/17 17:56, Dieter Nützel wrote:
 >> First BAD commit is patch [PATCH 2/5].
 >> https://patchwork.freedesktop.org/patch/192329/
 >
 >
 > Thanks! I've sent a V2 of that patch, I've also confirmed DiRT Rally
 > no longer segfaults at start-up.
 >
 >> With it I get this in dmesg:
 >>
 >> [34581.836122] OGL_Dispatch_33[4887]: segfault at 0 ip
 >> 9ebeafda sp a95580d4 error 4 in
 >> libc-2.26.so [7f6afcaf7000+1b1000]
 >> [34706.224082] perf: interrupt took too long (5089 > 4913), lowering
 >> kernel.perf_event_max_sample_rate to 39250
 >> [34918.80] OGL_Dispatch_33[19897]: segfault at 0 ip
 >> d9adbd7a sp e6e1b769 error 4 in
 >> libc-2.26.so [7f2fc4777000+1b1000]
 >> [35148.576818] OGL_Dispatch_33[2934]: segfault at 0 ip
 >> 78a41511 sp 1f147296 error 4 in
 >> libc-2.26.so [7ff11fa23000+1b1000]
 >> [35172.410621] OGL_Dispatch_33[3371]: segfault at 0 ip
 >> ef37ae37 sp 99ce37ab error 4 in
 >> libc-2.26.so [7f0af78ff000+1b1000]
 >> [35383.940291] OGL_Dispatch_33[18591]: segfault at 0 ip
 >> 813f92d2 sp 7c9305e7 error 4 in
 >> libc-2.26.so [7fee87426000+1b1000]
 >>
 >> It's in the morning, now.
 >> Here in 'OLD' Germany, near Hamburg.
 >> Good night! ;-)
 >>
 >> Dieter
 >>
 >> Am 10.12.2017 05:15, schrieb Timothy Arceri:
 >>> Hi, as always thanks for testing :)
 >>>
 >>> Are you able to find out which patch causes the crash? I'm
curious if
 >>> its the ARB_get_program_binary support or if I break the regular
 >>> cache
 >>> when re-factoring.
 >>>
 >>> Thanks,
 >>> Tim
 >>>
 >>> On 09/12/17 15:58, Dieter Nützel wrote:
  Hello Tim,
 
  first time ever, that I got a real regression with your GREAT
work.
  ;-)
 
  DiRT Rally sig fault (SIGSEGV(11) with this series.
  (see attachment)
 
  Bad cache hit re-read?
  Removing .cache/mesa_shader_cache do not help.
  Searching for the rigth Feral (Steam?) cache dir. - Alex/James?
 
  Then I'll have to find which of the five did it.
 
   From the log I got this:
  [1209/054156:ERROR:sandbox_linux.cc(325)] InitializeSandbox()
called
  with multiple threads in process gpu-process
  [1209/054157:INFO:CONSOLE(0)] "The specified value '!' does not
  conform to the required format.  The format is '#rrggbb' where rr,
  gg, bb are two-digit hexadecimal numbers.", source:
 

file://localhost/home1/alexander/My%20Games/Steam/steamapps/common/DiRT%20Rally/share/FeralUI/PGOW/Core/feralUI.html
  (0)
  Installing breakpad exception handler for
  appid(steam)/version(1509425745)
  [1209/054158:INFO:CONSOLE(0)] "Synchronous XMLHttpRequest on the
  main thread is deprecated because of its detrimental effects
to the
  end user's experience. For more help, check
  http://xhr.spec.whatwg.org/.";, source:  (0)
  [1209/054208:WARNING:x11_util.cc(1490)] X error received: serial
  4814, error_code 3 (BadWindow (invalid Window parameter)),
  request_code 4, minor_code 0 (X_DestroyWindow)
  SDL2 initialised [built against 2.0.5, running with 2.0.5]
  DirtRally: dumped to
  "/home/alexander/.local/share/feral-interactive/DiRT
  Rally/crashes/2363a778-c194-621f-0f837dfb-191070fd.dmp"
 
  Cheers,
  Dieter
 
  Am 08.12.2017 10:57, schrieb Timothy Arceri:
 > Core support in now in master so this is just a resend of the
 > gallium
 > patches.
 >
 > Resolves crash in Dead Island:
 >
 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85564
 >
 > Branch available here:
 >
 > https://github.com/tarceri/Mesa.git gallium-program-binary
 >
 > ___
 

Re: [Mesa-dev] [PATCH 21/18] ac: skip type for tcs input on RADV

[Timothy Arceri]

On 12/12/17 05:44, Dieter Nützel wrote:

Tim,

I'm somewhat baffled...
V1 do not have 20,21
V2 do not have 19,21
V3 do not have 19,20

Which one is right?


These are follow-on patches for the tess nir support for radeonsi (v1). 
The other two patches are standalone but this patch should probably be 
squashed with patch 3 before pushing if people agree its the right thing 
to do. I tried adding struct support to nir2llvmtype() but unfortunately 
the Vulkan vars had NULL in their names so I couldn't lookup the struct 
members index, not sure if this is a Vulkan bug but this and the 
previous patch work around it for now.




Thanks,
Dieter

Am 11.12.2017 10:56, schrieb Timothy Arceri:

The type can be a struct on RADV and causes an assert() to be
thrown, for radeonsi all structs should have been lowered away.
---
 src/amd/common/ac_nir_to_llvm.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c 
b/src/amd/common/ac_nir_to_llvm.c

index 38a840bf813..1466c7f875f 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2972,23 +2972,25 @@ static LLVMValueRef visit_load_var(struct
ac_nir_context *ctx,
 unsigned const_index = 0;
 unsigned location = instr->variables[0]->var->data.location;
 unsigned driver_location = 
instr->variables[0]->var->data.driver_location;

 const bool is_patch =  instr->variables[0]->var->data.patch;
 const bool is_compact = 
instr->variables[0]->var->data.compact;


 get_deref_offset(ctx, instr->variables[0],
  false, NULL, is_patch ? NULL : &vertex_index,
  &const_index, &indir_index);

+    LLVMTypeRef type = ctx->nctx ? NULL :
+    nir2llvmtype(ctx, instr->variables[0]->var->type);
+
 result = ctx->abi->load_tess_inputs(ctx->abi, 
vertex_index, indir_index,

-    const_index, location, driver_location,
-    nir2llvmtype(ctx, 
instr->variables[0]->var->type),
+    const_index, location, 
driver_location, type,
 
instr->variables[0]->var->data.location_frac,

 instr->num_components,
 is_patch, is_compact);
 return ctx->nctx ?
 LLVMBuildBitCast(ctx->nctx->builder, result, 
get_def_type(ctx,

&instr->dest.ssa), "") :
 result;
 }

 if (ctx->stage == MESA_SHADER_GEOMETRY) {
 LLVMValueRef indir_index;

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] Gallium ARB_get_program_binary support

[Mike Lothian]

Tested with Dead Island, Dirt Rally and Serious Sam BFG (which I believe
uses this extension)

Do you know any other games that use this?

On Mon, 11 Dec 2017 at 02:17 Dieter Nützel  wrote:

> For the V2 series:
>
> Tested-by: Dieter Nützel 
> and
> Acked-by: Dieter Nützel 
> if this is worth from my side.
>
> on RX580 8GB
>
> with DiRT Rally, UH, UV, Blender 2.79, smoketest, F1 2017 (Vulkan),
> glmark2 (parallel with
> OpenCL (/opt/opencl-example>./run_tests.sh))
>
> Dieter
>
> Am 10.12.2017 23:06, schrieb Timothy Arceri:
> > On 10/12/17 17:56, Dieter Nützel wrote:
> >> First BAD commit is patch [PATCH 2/5].
> >> https://patchwork.freedesktop.org/patch/192329/
> >
> >
> > Thanks! I've sent a V2 of that patch, I've also confirmed DiRT Rally
> > no longer segfaults at start-up.
> >
> >> With it I get this in dmesg:
> >>
> >> [34581.836122] OGL_Dispatch_33[4887]: segfault at 0 ip
> >> 9ebeafda sp a95580d4 error 4 in
> >> libc-2.26.so[7f6afcaf7000+1b1000]
> >> [34706.224082] perf: interrupt took too long (5089 > 4913), lowering
> >> kernel.perf_event_max_sample_rate to 39250
> >> [34918.80] OGL_Dispatch_33[19897]: segfault at 0 ip
> >> d9adbd7a sp e6e1b769 error 4 in
> >> libc-2.26.so[7f2fc4777000+1b1000]
> >> [35148.576818] OGL_Dispatch_33[2934]: segfault at 0 ip
> >> 78a41511 sp 1f147296 error 4 in
> >> libc-2.26.so[7ff11fa23000+1b1000]
> >> [35172.410621] OGL_Dispatch_33[3371]: segfault at 0 ip
> >> ef37ae37 sp 99ce37ab error 4 in
> >> libc-2.26.so[7f0af78ff000+1b1000]
> >> [35383.940291] OGL_Dispatch_33[18591]: segfault at 0 ip
> >> 813f92d2 sp 7c9305e7 error 4 in
> >> libc-2.26.so[7fee87426000+1b1000]
> >>
> >> It's in the morning, now.
> >> Here in 'OLD' Germany, near Hamburg.
> >> Good night! ;-)
> >>
> >> Dieter
> >>
> >> Am 10.12.2017 05:15, schrieb Timothy Arceri:
> >>> Hi, as always thanks for testing :)
> >>>
> >>> Are you able to find out which patch causes the crash? I'm curious if
> >>> its the ARB_get_program_binary support or if I break the regular
> >>> cache
> >>> when re-factoring.
> >>>
> >>> Thanks,
> >>> Tim
> >>>
> >>> On 09/12/17 15:58, Dieter Nützel wrote:
>  Hello Tim,
> 
>  first time ever, that I got a real regression with your GREAT work.
>  ;-)
> 
>  DiRT Rally sig fault (SIGSEGV(11) with this series.
>  (see attachment)
> 
>  Bad cache hit re-read?
>  Removing .cache/mesa_shader_cache do not help.
>  Searching for the rigth Feral (Steam?) cache dir. - Alex/James?
> 
>  Then I'll have to find which of the five did it.
> 
>   From the log I got this:
>  [1209/054156:ERROR:sandbox_linux.cc(325)] InitializeSandbox() called
>  with multiple threads in process gpu-process
>  [1209/054157:INFO:CONSOLE(0)] "The specified value '!' does not
>  conform to the required format.  The format is '#rrggbb' where rr,
>  gg, bb are two-digit hexadecimal numbers.", source:
> 
> file://localhost/home1/alexander/My%20Games/Steam/steamapps/common/DiRT%20Rally/share/FeralUI/PGOW/Core/feralUI.html
>  (0)
>  Installing breakpad exception handler for
>  appid(steam)/version(1509425745)
>  [1209/054158:INFO:CONSOLE(0)] "Synchronous XMLHttpRequest on the
>  main thread is deprecated because of its detrimental effects to the
>  end user's experience. For more help, check
>  http://xhr.spec.whatwg.org/.";, source:  (0)
>  [1209/054208:WARNING:x11_util.cc(1490)] X error received: serial
>  4814, error_code 3 (BadWindow (invalid Window parameter)),
>  request_code 4, minor_code 0 (X_DestroyWindow)
>  SDL2 initialised [built against 2.0.5, running with 2.0.5]
>  DirtRally: dumped to
>  "/home/alexander/.local/share/feral-interactive/DiRT
>  Rally/crashes/2363a778-c194-621f-0f837dfb-191070fd.dmp"
> 
>  Cheers,
>  Dieter
> 
>  Am 08.12.2017 10:57, schrieb Timothy Arceri:
> > Core support in now in master so this is just a resend of the
> > gallium
> > patches.
> >
> > Resolves crash in Dead Island:
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85564
> >
> > Branch available here:
> >
> > https://github.com/tarceri/Mesa.git gallium-program-binary
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] egl: remove unneeded _eglGetNativePlatform check

[Emil Velikov]

On 6 December 2017 at 20:36, Ian Romanick  wrote:
> Do we have any tests at all that exercise this path?  I don't know this
> code well enough to feel comfortable reviewing this (says everyone). :(
>
At first I was thinking that the error "can never happen", although it
seems like it can...
Although that's a bug in Mesa - it shouldn't flag up ;-)

Thanks for the prod Ian! A simple piglit test, have uncovered a bug in
the shmfence/DRI3 code.
DRI2 works like a charm - I'll send the patches in a second.

Emil
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] gallium/u_blitter: enable MSAA when blitting to MSAA surfaces

[Brian Paul]

If we're doing a Z -> Z MSAA blit (for example) we need to enable
msaa rasterization when drawing the quads so that we can properly
write the per-sample values.

This fixes a number of Piglit ext_framebuffer_multisample blit tests
such as ext_framebuffer_multisample/no-color 2 depth combined with
the VMware driver.

v2: This depends on the previous patch to save/set/restore the
min_samples state.
---
 src/gallium/auxiliary/util/u_blitter.c | 54 +-
 1 file changed, 33 insertions(+), 21 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_blitter.c 
b/src/gallium/auxiliary/util/u_blitter.c
index 371daf1..acb9fcf 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -123,7 +123,8 @@ struct blitter_context_priv
void *sampler_state_rect_linear;
 
/* Rasterizer state. */
-   void *rs_state, *rs_state_scissor, *rs_discard_state;
+   void *rs_state[2][2];  /**< [scissor][msaa] */
+   void *rs_discard_state;
 
/* Destination surface dimensions. */
unsigned dst_width;
@@ -275,13 +276,19 @@ struct blitter_context *util_blitter_create(struct 
pipe_context *pipe)
rs_state.bottom_edge_rule = 1;
rs_state.flatshade = 1;
rs_state.depth_clip = 1;
-   ctx->rs_state = pipe->create_rasterizer_state(pipe, &rs_state);
 
-   rs_state.scissor = 1;
-   ctx->rs_state_scissor = pipe->create_rasterizer_state(pipe, &rs_state);
+   unsigned scissor, msaa;
+   for (scissor = 0; scissor < 2; scissor++) {
+  for (msaa = 0; msaa < 2; msaa++) {
+ rs_state.scissor = scissor;
+ rs_state.multisample = msaa;
+ ctx->rs_state[scissor][msaa] =
+pipe->create_rasterizer_state(pipe, &rs_state);
+  }
+   }
 
if (ctx->has_stream_out) {
-  rs_state.scissor = 0;
+  rs_state.scissor = rs_state.multisample = 0;
   rs_state.rasterizer_discard = 1;
   ctx->rs_discard_state = pipe->create_rasterizer_state(pipe, &rs_state);
}
@@ -454,8 +461,13 @@ void util_blitter_destroy(struct blitter_context *blitter)
pipe->delete_depth_stencil_alpha_state(pipe, ctx->dsa_write_depth_stencil);
pipe->delete_depth_stencil_alpha_state(pipe, 
ctx->dsa_keep_depth_write_stencil);
 
-   pipe->delete_rasterizer_state(pipe, ctx->rs_state);
-   pipe->delete_rasterizer_state(pipe, ctx->rs_state_scissor);
+   unsigned scissor, msaa;
+   for (scissor = 0; scissor < 2; scissor++) {
+  for (msaa = 0; msaa < 2; msaa++) {
+ pipe->delete_rasterizer_state(pipe, ctx->rs_state[scissor][msaa]);
+  }
+   }
+
if (ctx->rs_discard_state)
   pipe->delete_rasterizer_state(pipe, ctx->rs_discard_state);
if (ctx->vs)
@@ -1222,12 +1234,12 @@ void util_blitter_cache_all_shaders(struct 
blitter_context *blitter)
 }
 
 static void blitter_set_common_draw_rect_state(struct blitter_context_priv 
*ctx,
-   bool scissor)
+   bool scissor, bool msaa)
 {
struct pipe_context *pipe = ctx->base.pipe;
 
-   pipe->bind_rasterizer_state(pipe, scissor ? ctx->rs_state_scissor
- : ctx->rs_state);
+   pipe->bind_rasterizer_state(pipe, ctx->rs_state[scissor][msaa]);
+
if (ctx->has_geometry_shader)
   pipe->bind_gs_state(pipe, NULL);
if (ctx->has_tessellation) {
@@ -1401,7 +1413,7 @@ static void util_blitter_clear_custom(struct 
blitter_context *blitter,
if (num_layers > 1 && ctx->has_layered) {
   blitter_get_vs_func get_vs = get_vs_layered;
 
-  blitter_set_common_draw_rect_state(ctx, false);
+  blitter_set_common_draw_rect_state(ctx, false, false);
   blitter->draw_rectangle(blitter, ctx->velem_state, get_vs,
   0, 0, width, height,
   (float) depth, num_layers, type, &attrib);
@@ -1413,7 +1425,7 @@ static void util_blitter_clear_custom(struct 
blitter_context *blitter,
   else
  get_vs = get_vs_passthrough_pos;
 
-  blitter_set_common_draw_rect_state(ctx, false);
+  blitter_set_common_draw_rect_state(ctx, false, false);
   blitter->draw_rectangle(blitter, ctx->velem_state, get_vs,
   0, 0, width, height,
   (float) depth, 1, type, &attrib);
@@ -1966,7 +1978,7 @@ void util_blitter_blit_generic(struct blitter_context 
*blitter,
   pipe->set_scissor_states(pipe, 0, 1, scissor);
}
 
-   blitter_set_common_draw_rect_state(ctx, scissor != NULL);
+   blitter_set_common_draw_rect_state(ctx, scissor != NULL, dst_samples > 1);
 
do_blits(ctx, dst, dstbox, src, src_width0, src_height0,
 srcbox, blit_depth || blit_stencil, use_txf);
@@ -2072,7 +2084,7 @@ void util_blitter_generate_mipmap(struct blitter_context 
*blitter,
pipe->bind_sampler_states(pipe, PIPE_SHADER_FRAGMENT,
  0, 1, &sampler_state);
 
-   blitter_set_common_draw_rect_state(ctx, false);
+   blitter_set_common

[Mesa-dev] [PATCH 1/2] gallium/u_blitter: add code to save/set/restore min_samples for msaa

[Brian Paul]

Will be used by the next patch.
---
 src/gallium/auxiliary/util/u_blitter.c |  8 
 src/gallium/auxiliary/util/u_blitter.h | 11 +++
 2 files changed, 19 insertions(+)

diff --git a/src/gallium/auxiliary/util/u_blitter.c 
b/src/gallium/auxiliary/util/u_blitter.c
index 476ef08..371daf1 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -646,6 +646,12 @@ void util_blitter_restore_fragment_states(struct 
blitter_context *blitter)
   ctx->base.is_sample_mask_saved = false;
}
 
+   /* Min samples. */
+   if (ctx->base.is_min_samples_saved) {
+  pipe->set_min_samples(pipe, ctx->base.saved_min_samples);
+  ctx->base.is_min_samples_saved = false;
+   }
+
/* Miscellaneous states. */
/* XXX check whether these are saved and whether they need to be restored
 * (depending on the operation) */
@@ -1675,6 +1681,8 @@ static void do_blits(struct blitter_context_priv *ctx,
 
blitter_set_dst_dimensions(ctx, fb_state.width, fb_state.height);
 
+   pipe->set_min_samples(pipe, 1);
+
if ((src_target == PIPE_TEXTURE_1D ||
 src_target == PIPE_TEXTURE_2D ||
 src_target == PIPE_TEXTURE_RECT) &&
diff --git a/src/gallium/auxiliary/util/u_blitter.h 
b/src/gallium/auxiliary/util/u_blitter.h
index dba7739..251cd9b 100644
--- a/src/gallium/auxiliary/util/u_blitter.h
+++ b/src/gallium/auxiliary/util/u_blitter.h
@@ -117,6 +117,9 @@ struct blitter_context
bool is_sample_mask_saved;
unsigned saved_sample_mask;
 
+   bool is_min_samples_saved;
+   unsigned saved_min_samples;
+
unsigned saved_num_sampler_states;
void *saved_sampler_states[PIPE_MAX_SAMPLERS];
 
@@ -546,6 +549,14 @@ util_blitter_save_sample_mask(struct blitter_context 
*blitter,
 }
 
 static inline void
+util_blitter_save_min_samples(struct blitter_context *blitter,
+  unsigned min_samples)
+{
+   blitter->is_min_samples_saved = true;
+   blitter->saved_min_samples = min_samples;
+}
+
+static inline void
 util_blitter_save_render_condition(struct blitter_context *blitter,
struct pipe_query *query,
bool condition,
-- 
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] i965/bufmgr: Add a helper to mark a BO as external

[Emil Velikov]

On 21 November 2017 at 00:13, Andres Gomez  wrote:
> Jason, this nominated series landed without mentioning any specific
> stable queue.
>
> From what I'm seeing, both depend on 2c4097aff1b which didn't make it
> for 17.2 so I'm dropping them for that queue.
>
This is a preparatory patch for the follow-up commit.
With the latter addressing issue caused by
4b1e70cc57d7ff5f465544644b2180dee1490cee - only available in
17.4.0-dev.

I believe the 17.2 and 17.3 series should be safe ;-)

-Emil
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] st/va: change frame_idx from array to hash table

[Emil Velikov]

On 28 November 2017 at 13:32, Andres Gomez  wrote:
> Julien, this looks like a good candidate to nominate for inclusion in
> the 17.2 stable queue.
>
> What do you think?
>
Based on the discussion in the bugreport, we really want that in 17.2.
I've picked it up for 17.2.7, although let me know if you believe we
should drop it.

Thanks
Emil
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v4 1/2] glsl: allow any l-value of an input variable as interpolant in interpolateAt*

[Emil Velikov]

On 28 November 2017 at 14:31, Nicolai Hähnle  wrote:
> On 28.11.2017 14:58, Andres Gomez wrote:
>>
>> Nicolai, this looks like a good candidate to nominate for inclusion in
>> all the stable queues.
>>
>> What do you think?
>
>
> It's a rare enough use case, but the change is small and there seem to have
> been no regressions, so sure, go ahead for both of them.
>
Thanks for the confirmation Nicolai - picked both for 17.2.7.

Emil
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [Mesa-stable] [PATCH 01/12] i965/fs: Unpack count argument to 64-bit shift ops on Atom

[Emil Velikov]

On 29 November 2017 at 03:25, Matt Turner  wrote:
> On Tue, Nov 28, 2017 at 5:54 AM, Andres Gomez  wrote:
>> Matt, this looks like a good candidate to nominate for inclusion in
>> the 17.2 stable queue.
>>
>> What do you think?
>
> Yes, I think so. I didn't realize that ARB_shader_ballot was in 17.2,
> but this is a bug fix for it so it should be included.

Picked for 17.2.7. Thanks guys.

-Emil
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 4/4] meson: build clover

[Dylan Baker]

Quoting Eric Engestrom (2017-12-11 08:17:50)
> On Friday, 2017-12-08 16:27:22 -0800, Dylan Baker wrote:
> > This has only been compile tested.
> > 
> > cc: Curro Jerez 
> > Signed-off-by: Dylan Baker 
> > ---
> >  include/meson.build   |  19 
> >  meson.build   |  27 +-
> >  meson_options.txt |  12 +++
> >  src/gallium/meson.build   |  12 ++-
> >  src/gallium/state_trackers/clover/meson.build | 122 
> > ++
> >  src/gallium/targets/opencl/meson.build|  73 +++
> >  src/gallium/targets/pipe-loader/meson.build   |  76 
> >  7 files changed, 336 insertions(+), 5 deletions(-)
> >  create mode 100644 src/gallium/state_trackers/clover/meson.build
> >  create mode 100644 src/gallium/targets/opencl/meson.build
> >  create mode 100644 src/gallium/targets/pipe-loader/meson.build
> > 
> > diff --git a/include/meson.build b/include/meson.build
> > index e4dae91cede..a2e7ce6580e 100644
> > --- a/include/meson.build
> > +++ b/include/meson.build
> > @@ -78,3 +78,22 @@ if with_gallium_st_nine
> >  subdir : 'd3dadapter',
> >)
> >  endif
> > +
> > +# Only install the headers if we are building a stand alone implementation 
> > and
> > +# not an ICD enabled implementation
> > +if with_gallium_opencl and not with_opencl_icd
> > +  install_headers(
> > +'CL/cl.h',
> > +'CL/cl.hpp',
> > +'CL/cl_d3d10.h',
> > +'CL/cl_d3d11.h',
> > +'CL/cl_dx9_media_sharing.h',
> > +'CL/cl_egl.h',
> > +'CL/cl_ext.h',
> > +'CL/cl_gl.h',
> > +'CL/cl_gl_ext.h',
> > +'CL/cl_platform.h',
> > +'CL/opencl.h',
> > +subdir: 'CL'
> > +  )
> > +endif
> > diff --git a/meson.build b/meson.build
> > index 842d441199e..7892d2d0ec4 100644
> > --- a/meson.build
> > +++ b/meson.build
> > @@ -583,6 +583,20 @@ if with_gallium_st_nine
> >endif
> >  endif
> >  
> > +if get_option('gallium-opencl')
> > +  if not with_gallium
> > +error('OpenCL Clover implementation requires at least one gallium 
> > driver.')
> > +  endif
> > +
> > +  # TODO: alitvec?
> > +  dep_clc = dependency('libclc')
> > +  with_gallium_opencl = true
> > +else
> > +  dep_clc = []
> > +  with_gallium_opencl = false
> > +endif
> > +with_opencl_icd = get_option('gallium-opencl-icd')
> 
> I would kinda prefer `combo(icd, standalone, false), default: icd`
> 
> Don't have time to look in depth at this patch and 1/4 right now,
> but they both are:
> Acked-by: Eric Engestrom 
> 

I don't have a strong opinion either way, so I'll change it to a single option.
The default I think should match autotools and be disabled.

I'd also like to at least have someone from SWR and clover look at it before I
push so I don't think this is going to land immediately.


signature.asc
Description: signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH mesa] meson: add dep_thread to every lib that includes threads.h

[Emil Velikov]

On 7 December 2017 at 17:25, Dylan Baker  wrote:
> Quoting Emil Velikov (2017-12-07 08:40:27)
>> On 7 December 2017 at 14:51, Eric Engestrom  
>> wrote:
>> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104141
>> > Signed-off-by: Eric Engestrom 
>> > ---
>> >  src/broadcom/meson.build| 2 +-
>> >  src/gallium/auxiliary/meson.build   | 2 +-
>> >  src/gallium/state_trackers/nine/meson.build | 1 +
>> >  src/gallium/targets/xa/meson.build  | 2 +-
>> >  src/gallium/targets/xvmc/meson.build| 2 +-
>> >  src/gbm/meson.build | 2 +-
>> >  src/intel/common/meson.build| 2 +-
>> >  src/loader/meson.build  | 2 +-
>> >  src/util/meson.build| 2 +-
>> >  9 files changed, 9 insertions(+), 8 deletions(-)
>> >
>> I doubt we can continue and pretend to be libpthread.so free.
>> To make it even funnier, depending on moon cycle or other fun factors,
>> we could get the pthread dependency implicitly satisfied as one of the
>> other shared libraries already pulls the library.
>>
>> So how about we simply append -pthread to CC/CXX with at global scope
>> and drop the all the individual dependencies?
>> It will safe us a few characters to type, plus will ensure that newly
>> added binaries don't fall victim of the same issue.
>
> Absolutely not. The meson build has dep_thread for a reason, because meson
> guarantees that calling `dependency('threads')` will always return the right
> value for your platform, even if that platform is windows and doesn't have
> pthreads at all (but does the right thing for cygwin).
>
I would recommend looking through clang/gcc. AFAICS any* platform/arch
combo supported by Mesa handles -pthread and that toggle does the
"right thing".
Obviously that can seem a bit hacky, so a better way to avoid all the
copy/paste is for meson to grow an option that allows folding the
required cflags/libs with the compiler directive.

> The reason that we're running into this problem is as you guessed that some
> dependencies pull in pthreads implicitly, for example LLVM, which is why we're
> seeing this so often in gallium.
>
Precisely. Due to the combinatoric explosions things are bound to
break again, hence my earlier suggestion.
I doubt you or anyone on the team will be excited to see things break.

-Emil

* I've checked Cygwin, Solaris-like, BSD-like, Linuxen, Hurd and
Android, on both 32 and 64bit x86, ARM and PPC.
I believe msys/mingw should be fine as well, but I'm short on details.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] gallium/u_blitter: enable MSAA when blitting to MSAA surfaces

[Brian Paul]

On 12/11/2017 11:06 AM, Marek Olšák wrote:

On Thu, Dec 7, 2017 at 5:09 PM, Brian Paul  wrote:

If we're doing a Z -> Z MSAA blit (for example) we need to enable
msaa rasterization when drawing the quads so that we can properly
write the per-sample values.

This fixes a number of Piglit ext_framebuffer_multisample blit tests
such as ext_framebuffer_multisample/no-color 2 depth combined with
the VMware driver.

---

Marek, I'm not sure how this could have worked without MSAA enabled.
Perhaps you can comment.


Enabling MSAA rasterization should have no effect, because the blitter
draws an axis-aligned quad, so each pixel will generate only one
sample.

radeon drivers still obey the sample mask even if MSAA is disabled. I
guess svga doesn't.


If we'd set the sample mask in the fs (with a TGSI_SEMANTIC_SAMPLEMASK 
output register) we'd get automatic MSAA, but we don't do that with the 
pipe_context::set_sample_mask() state.





I guess enabling MSAA is OK, but now we also have to save and restore
the "min_samples" value if it's not 1, because we don't want to use
sample shading because u_blitter doesn't need it.


OK, I can add a predecessor patch to take care of that.  I'll send a v2...

-Brian

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [ANNOUNCE] Mesa 17.2.7 release candidate

[Emil Velikov]

Hello list,

The candidate for the Mesa 17.2.7 is now available. Currently we have:
 - 45 queued
 - 2 nominated (outstanding)
 - and 1 rejected patches

The current queue consists of a variety of fixes, with a sizeable hunk in the
shared GLSL codebase.

Whereas for individual drivers - i965 has a crash fix for when playing various
Valve games, r600 and nouveau have tweaks in their compiler backends. Fast
clears on radeonsi and RADV are better now, while the VAAPI encoding is playing
nicely with GStreamer.

The WGL state tracker and SWR driver have also seen minor improvements.

To top of up - Mesa should build fine with the latest glibc 2.17.


Take a look at section "Mesa stable queue" for more information.


Testing reports/general approval

Any testing reports (or general approval of the state of the branch) will be
greatly appreciated.

The plan is to have 17.2.7 this Wednesday(13th Dec 2017), around or shortly
after 20:00 GMT.

If you have any questions or suggestions - be that about the current patch
queue or otherwise, please go ahead.


Trivial merge conflicts
---
List of commits where manual intervention was required.
Keep the authors in the CC list.

commit a8a5a97f4627182f6345f50bcbea4ab51ba80480
Author: Ilia Mirkin 

glsl: fix derived cs variables

(cherry picked from commit 4d24a7cb97641cacecd371d1968f6964785822e4)


commit a995d6bb78a2bf2881018316cdbf8bb45fa4a18b
Author: Marek Olšák 

radeonsi/gfx9: fix importing shared textures with DCC

(cherry picked from commit ed4780383cae61e051b3d3d120649222da49feae)


commit 4d0ec672cbff094175bb055bf34acdfeb8a92992
Author: Marek Olšák 

radeonsi: flush the context after resource_copy_region for buffer exports

(cherry picked from commit 5e805cc74bc52f97de8f6308fc06bc96623e7e09)


commit 6c9c07b0f9728192184108f1c0cd155139990914
Author: Alex Smith 

radv: Add LLVM version to the device name string

(cherry picked from commit 8fda98c4f1dba2488b9e3ef3e820585f48a8a2f9)


commit 83c85b28a4905e84c56f37b9d561fa372d11b0ea
Author: Eric Engestrom 

compiler: use NDEBUG to guard asserts

(cherry picked from commit 7b85b9b8773b119360a31b66b321ae560a77cb6d)


commit ecf8e4a64ca48eda14314b84ccd061713492d122
Author: Vadym Shovkoplias 

intel/blorp: Fix possible NULL pointer dereferencing

(cherry picked from commit cdb3eb7174f84f3200408c4b43c819fb093da9c6)


commit ac78f7c76a7d21de280592d539aafdea6eecd5bb
Author: Vinson Lee 

anv: Check if memfd_create is already defined.

(cherry picked from commit 8c1e4b1afc8d396ccf99c725c59b29a9aa305557)


Cheers,
Emil


Mesa stable queue
-

Nominated (2)
=

Bas Nieuwenhuizen (1):
  b926da2 spirv: Fix loading an entire block at once.

Leo Liu (1):
  6d74cb2 radeon/vce: move destroy command before feedback command


Queued (45)
===

Alex Smith (1):
  radv: Add LLVM version to the device name string

Andres Gomez (2):
  docs: add sha256 checksums for 17.2.6
  docs: remove bug 103626 from fix list as per 17.2.6

Ben Crocker (2):
  docs/llvmpipe.html: Minor edits
  docs/llvmpipe: document ppc64le as alternative architecture to x86.

Dave Airlie (1):
  r600/sb: handle jump after target to end of program. (v2)

Denis Pauk (1):
  gallium/{r600, radeonsi}: Fix segfault with color format (v2)

Eduardo Lima Mitev (3):
  glsl_parser_extra: Add utility to copy symbols between symbol tables
  glsl: Use the utility function to copy symbols between symbol tables
  glsl/linker: Check that re-declared, inter-shader built-in blocks match

Emil Velikov (2):
  gl_table.py: add extern C guard for the generated glapitable.h
  cherry-ignore: radeonsi: allow DMABUF exports for local buffers

Eric Anholt (1):
  broadcom/vc4: Fix handling of GFXH-515 workaround with a start
vertex count.

Eric Engestrom (1):
  compiler: use NDEBUG to guard asserts

Fabian Bieler (2):
  glsl: Match order of gl_LightSourceParameters elements.
  glsl: Fix gl_NormalScale.

Frank Richter (1):
  gallium/wgl: fix default pixel format issue

George Kyriazis (1):
  swr: Handle resource across context changes

Gert Wollny (2):
  r600: Emit EOP for more CF instruction types
  r600/sb: do not convert if-blocks that contain indirect array access

Ilia Mirkin (1):
  glsl: fix derived cs variables

James Legg (1):
  nir/opcodes: Fix constant-folding of bitfield_insert

Jason Ekstrand (1):
  i965: Disable regular fast-clears (CCS_D) on gen9+

Juan A. Suarez Romero (1):
  glsl: add varying resources for arrays of complex types

Julien Isorce (1):
  st/va: change frame_idx from array to hash table

Kai Wasserbäch (1):
  docs: Point to apt.llvm.org for development snapshot packages

Kenneth Graunke (3):
  meta: Initialize depth/clear values on declaration.
  meta: Fix ClearTexture with GL_DEPTH_COMPONENT.
  i965: Fix Smooth Point

Re: [Mesa-dev] [PATCH 3/4] meson: set opencl flags for r600

[Dylan Baker]

Quoting Eric Engestrom (2017-12-11 07:55:30)
> On Friday, 2017-12-08 16:27:21 -0800, Dylan Baker wrote:
> > Signed-off-by: Dylan Baker 
> 
> Should come after the current 4/4, but
> Reviewed-by: Eric Engestrom 
> 
> > ---
> >  src/gallium/drivers/r600/meson.build | 7 +--
> >  1 file changed, 5 insertions(+), 2 deletions(-)
> > 
> > diff --git a/src/gallium/drivers/r600/meson.build 
> > b/src/gallium/drivers/r600/meson.build
> > index 2132dbb33ad..5899518a2e8 100644
> > --- a/src/gallium/drivers/r600/meson.build
> > +++ b/src/gallium/drivers/r600/meson.build
> > @@ -113,12 +113,15 @@ egd_tables_h = custom_target(
> >capture : true,
> >  )
> >  
> > -# TODO: compute defines
> > +r600_c_args = []
> > +if with_gallium_opencl
> > +  r600_c_args += '-DHAVE_OPENCL'
> > +endif
> >  
> >  libr600 = static_library(
> >'r600',
> >[files_r600, egd_tables_h],
> > -  c_args : [c_vis_args],
> > +  c_args : [c_vis_args, r600_c_args],
> >cpp_args : [cpp_vis_args],
> >include_directories : [
> >  inc_src, inc_include, inc_gallium, inc_gallium_aux, inc_amd_common,
> > -- 
> > 2.15.1
> > 

r600 needs this to work with clover at all. Since it's so minimal, how would you
feel about just squashing this into 4/4?


signature.asc
Description: signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 5/7] nir: Offset vertex_id by first_vertex instead of base_vertex

[Ian Romanick]

On 12/04/2017 12:12 PM, Antia Puentes wrote:
> From: Neil Roberts 
> 
> base_vertex will be zero for non-indexed calls, but we need it to
> include the ‘first’ parameter. This is true for both GL and Vulkan.
> 
> I think this patch will also affect freedreno and radeonsi. I believe

If you think a patch might break someone's driver, you should CC them on
the patch... they're more likely to verify it that way.  Adding Marek
and Rob. :)

> if they are relying on this lowering then they are currently already
> broken because they will have the wrong values for gl_BaseVertex.
> However this patch will also make them break for gl_VertexID and they
> will need to be fixed to use firt_vertex instead.
> ---
>  src/compiler/nir/nir_lower_system_values.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/compiler/nir/nir_lower_system_values.c 
> b/src/compiler/nir/nir_lower_system_values.c
> index 3594f4ae5ce..6f4fb8233ab 100644
> --- a/src/compiler/nir/nir_lower_system_values.c
> +++ b/src/compiler/nir/nir_lower_system_values.c
> @@ -105,7 +105,7 @@ convert_block(nir_block *block, nir_builder *b)
>   if (b->shader->options->vertex_id_zero_based) {
>  sysval = nir_iadd(b,
>nir_load_vertex_id_zero_base(b),
> -  nir_load_base_vertex(b));
> +  nir_load_first_vertex(b));
>   } else {
>  sysval = nir_load_vertex_id(b);
>   }
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 4/7] i965: Let nir lower gl_VertexID instead of the linker

[Ian Romanick]

I sent this patch a few weeks ago.  Since my commit message has
additional information, can we use mine instead?

https://patchwork.freedesktop.org/patch/189441/

On 12/04/2017 12:12 PM, Antia Puentes wrote:
> From: Neil Roberts 
> 
> ---
>  src/mesa/drivers/dri/i965/brw_context.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
> b/src/mesa/drivers/dri/i965/brw_context.c
> index b62852d90c8..249f62847b9 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -585,7 +585,8 @@ brw_initialize_context_constants(struct brw_context *brw)
>ctx->Const.QuadsFollowProvokingVertexConvention = false;
>  
> ctx->Const.NativeIntegers = true;
> -   ctx->Const.VertexID_is_zero_based = true;
> +   /* This is lowered by NIR instead */
> +   ctx->Const.VertexID_is_zero_based = false;
>  
> /* Regarding the CMP instruction, the Ivybridge PRM says:
>  *
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 3/7] intel: emit first_vertex and reorder the VE' components

[Ian Romanick]

On 12/04/2017 12:12 PM, Antia Puentes wrote:
> The new order is:
> * VE 1: 
> * VE 2: 
> 
> Previously it was:
> * VE 1: 
> * VE 2: 
> 
> The gl_BaseVertex is in a new location now, and firstvertex occupies
> the old gl_BaseVertex place. This way we can keep pointing to the
> indirect buffer for indirect draw calls.
> 
> Reviewed-by: Neil Roberts 
> ---
>  src/intel/compiler/brw_nir.c  | 11 +---
>  src/intel/compiler/brw_vec4.cpp   | 13 +
>  src/mesa/drivers/dri/i965/brw_context.h   | 36 ++---
>  src/mesa/drivers/dri/i965/brw_draw.c  | 26 +++---
>  src/mesa/drivers/dri/i965/brw_draw_upload.c   | 13 -
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 39 
> +++
>  6 files changed, 88 insertions(+), 50 deletions(-)
> 
> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
> index 8f3f77f89ae..f702f5b8534 100644
> --- a/src/intel/compiler/brw_nir.c
> +++ b/src/intel/compiler/brw_nir.c
> @@ -240,7 +240,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>  */
> const bool has_sgvs =
>nir->info.system_values_read &
> -  (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
> +  (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
> BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
> BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
> BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID));
> @@ -262,6 +262,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>  nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
>  
>  switch (intrin->intrinsic) {
> +case nir_intrinsic_load_first_vertex:
>  case nir_intrinsic_load_base_vertex:
>  case nir_intrinsic_load_base_instance:
>  case nir_intrinsic_load_vertex_id_zero_base:
> @@ -279,7 +280,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>  
> nir_intrinsic_set_base(load, num_inputs);
> switch (intrin->intrinsic) {
> -   case nir_intrinsic_load_base_vertex:
> +   case nir_intrinsic_load_first_vertex:
>nir_intrinsic_set_component(load, 0);
>break;
> case nir_intrinsic_load_base_instance:
> @@ -292,11 +293,15 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
>nir_intrinsic_set_component(load, 3);
>break;
> case nir_intrinsic_load_draw_id:
> +   case nir_intrinsic_load_base_vertex:
>/* gl_DrawID is stored right after gl_VertexID and friends
> * if any of them exist.
> */
>nir_intrinsic_set_base(load, num_inputs + has_sgvs);
> -  nir_intrinsic_set_component(load, 0);
> +  if (intrin->intrinsic ==  nir_intrinsic_load_draw_id)
 ^
Delete this extra space.

> + nir_intrinsic_set_component(load, 0);
> +  else
> + nir_intrinsic_set_component(load, 1);
>break;
> default:
>unreachable("Invalid system value intrinsic");
> diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
> index 14f930e0264..70a197a9fa0 100644
> --- a/src/intel/compiler/brw_vec4.cpp
> +++ b/src/intel/compiler/brw_vec4.cpp
> @@ -2789,13 +2789,19 @@ brw_compile_vs(const struct brw_compiler *compiler, 
> void *log_data,
>  * incoming vertex attribute.  So, add an extra slot.
>  */
> if (shader->info.system_values_read &
> -   (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
> +   (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
>  BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
>  BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
>  BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))) {
>nr_attribute_slots++;
> }
>  
> +   if (shader->info.system_values_read &
> +   (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
> +BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID))) {
> +  nr_attribute_slots++;
> +   }
> +
> if (shader->info.system_values_read &
> BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX))
>prog_data->uses_basevertex = true;
> @@ -2816,12 +2822,9 @@ brw_compile_vs(const struct brw_compiler *compiler, 
> void *log_data,
> BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))
>prog_data->uses_instanceid = true;
>  
> -   /* gl_DrawID has its very own vec4 */
> if (shader->info.system_values_read &
> -   BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID)) {
> +   BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID))
>prog_data->uses_drawid = true;
> -  nr_attribute_slots++;
> -   }
>  
> /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
>  * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode.  Empirically, in
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
>

Re: [Mesa-dev] [PATCH] gallivm: fix texture wrapping for texture gather for mirror modes

[Roland Scheidegger]

Am 11.12.2017 um 18:39 schrieb Jose Fonseca:
> Looks good AFAICT.  Thanks for the detailed comments. I can't really
> follow the math to the minutiae, but I trust your testing.
> 
> I wonder how much we gain by maitaining these gather and non-gather
> paths.  That is, I wonder if the hit of just using the more accurate
> gather paths is insignificant.
Well, they do look more complicated (don't forget the gather paths omit
the weight calculation so that's additional instructions). Texture
sampling is slow, and it's done separately for each direction (well of
course the wrap mode could be different for other coords), so I'm
reluctant to make it even slower (albeit granted it's slow for different
reasons really, but still).
And I thought they would not actually be more accurate with bilinear
filtering, but thinking about this I actually realize this is not
actually 100% true - well as far as swapping of texels is concerned it
does not matter, however picking the wrong texel could theoretically
alter the result - this is because with weight 0, if the wrongly picked
texel was a NaN or Inf the result will be a NaN, regardless what the
other texels were. (Or likewise, if it was a finite number but the texel
which should have gotten picked instead was a NaN or Inf the result
would be finite, if the other texels are finite. That said, I believe
implementations are permitted to not consider texels with weight 0 at
all for filtering purposes, with minmax reduction mode according to
ARB_texture_filter_minmax or the corresponding d3d functionality they
are actually even required to be ignored, so this case may not be a
problem.)

Roland


> 
> Some cosmetic remarks inline.
> 
> On 10/12/17 04:49, srol...@vmware.com wrote:
>> From: Roland Scheidegger 
>>
>> Care must be taken that all coords end up correct, the tests are very
>> sensitive that everything is correctly rounded. This doesn't matter
>> for bilinear filter (since picking a wrong texel with weight zero is
>> ok), and we could also switch the per-sample coords mistakenly.
>> While here, also optimize the coord_mirror helper a bit (we can do the
>> mirroring directly by exploiting float rounding, no need for fixing up
>> odd/even manually).
>> I did not touch the mirror_clamp and mirror_clamp_to_border modes.
>> In contrast to mirror_clamp_to_edge and mirror_repeat these are legacy
>> modes. They are specified against old gl rules, which actually does
>> the mirroring not per sample (so you get swapped order if the coord
>> is in the mirrored section). I think the idea though is that they should
>> follow the respecified mirror_clamp_to_edge rules so the order would be
>> correct.
>> ---
>>   src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 242
>> +++---
>>   1 file changed, 169 insertions(+), 73 deletions(-)
>>
>> diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
>> b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
>> index b67a089..3605c77 100644
>> --- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
>> +++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
>> @@ -218,34 +218,42 @@ lp_build_sample_texel_soa(struct
>> lp_build_sample_context *bld,
>>       /**
>> - * Helper to compute the mirror function for the PIPE_WRAP_MIRROR modes.
>> + * Helper to compute the mirror function for the
>> PIPE_WRAP_MIRROR_REPEAT mode.
>> + * (Note that with pot sizes could do this much more easily post-scale
>> + * with some bit arithmetic.)
>>    */
>>   static LLVMValueRef
>>   lp_build_coord_mirror(struct lp_build_sample_context *bld,
>> -  LLVMValueRef coord)
>> +  LLVMValueRef coord, boolean posOnly)
>>   {
>>  struct lp_build_context *coord_bld = &bld->coord_bld;
>> -   struct lp_build_context *int_coord_bld = &bld->int_coord_bld;
>> -   LLVMValueRef fract, flr, isOdd;
>> -
>> -   lp_build_ifloor_fract(coord_bld, coord, &flr, &fract);
>> -   /* kill off NaNs */
>> -   /* XXX: not safe without arch rounding, fract can be anything. */
>> -   fract = lp_build_max_ext(coord_bld, fract, coord_bld->zero,
>> -    GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN);
>> -
>> -   /* isOdd = flr & 1 */
>> -   isOdd = LLVMBuildAnd(bld->gallivm->builder, flr,
>> int_coord_bld->one, "");
>> +   LLVMValueRef fract;
>> +   LLVMValueRef half = lp_build_const_vec(bld->gallivm,
>> coord_bld->type, 0.5);
>>   -   /* make coord positive or negative depending on isOdd */
>> -   /* XXX slight overkill masking out sign bit is unnecessary */
>> -   coord = lp_build_set_sign(coord_bld, fract, isOdd);
>> +   /*
>> +    * We can just use 2*(x - round(0.5*x)) to do all the mirroring,
>> +    * it all works out. (The result is in range [-1, 1.0], negative if
>> +    * the coord is in the "odd" section, otherwise positive.)
>> +    */
>>   -   /* convert isOdd to float */
>> -   isOdd = lp_build_int_to_float(coord_bld, isOdd);
>> +   coord = lp_build_mul(coord_bld, coord, half);
>> +   fract = lp_build_rou

Re: [Mesa-dev] [PATCH v2 1/7] compiler: Add SYSTEM_VALUE_FIRST_VERTEX and instrinsics

[Ian Romanick]

On 12/04/2017 12:12 PM, Antia Puentes wrote:
> This VS system value will contain the value passed as 
> for indexed draw calls or the value passed as  for non-indexed
> draw calls. It will be used to calculate the gl_VertexID as
> SYSTEM_VALUE_VERTEX_ID_ZERO_BASE plus SYSTEM_VALUE_FIRST_VERTEX.
> Note that the current calculation which uses SYSTEM_VALUE_BASE_VERTEX
> is not right, as gl_BaseVertex should be zero for non-indexed calls.
> 
> v2: use SYSTEM_VALUE_FIRST_VERTEX as name for the value, instead of
> SYSTEM_VALUE_BASE_VERTEX_ID (Kenneth).
> 
> Reviewed-by: Neil Roberts 
> Reviewed-by: Kenneth Graunke 
> ---
>  src/compiler/nir/nir.c |  4 
>  src/compiler/nir/nir_gather_info.c |  1 +
>  src/compiler/nir/nir_intrinsics.h  |  1 +
>  src/compiler/shader_enums.c|  1 +
>  src/compiler/shader_enums.h| 15 +++
>  5 files changed, 22 insertions(+)
> 
> diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
> index 7380bf436a8..29730f5fa86 100644
> --- a/src/compiler/nir/nir.c
> +++ b/src/compiler/nir/nir.c
> @@ -1913,6 +1913,8 @@ nir_intrinsic_from_system_value(gl_system_value val)
>return nir_intrinsic_load_base_instance;
> case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
>return nir_intrinsic_load_vertex_id_zero_base;
> +   case SYSTEM_VALUE_FIRST_VERTEX:
> +  return nir_intrinsic_load_first_vertex;
> case SYSTEM_VALUE_BASE_VERTEX:
>return nir_intrinsic_load_base_vertex;
> case SYSTEM_VALUE_INVOCATION_ID:
> @@ -1982,6 +1984,8 @@ nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
>return SYSTEM_VALUE_BASE_INSTANCE;
> case nir_intrinsic_load_vertex_id_zero_base:
>return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
> +   case nir_intrinsic_load_first_vertex:
> +  return SYSTEM_VALUE_FIRST_VERTEX;
> case nir_intrinsic_load_base_vertex:
>return SYSTEM_VALUE_BASE_VERTEX;
> case nir_intrinsic_load_invocation_id:
> diff --git a/src/compiler/nir/nir_gather_info.c 
> b/src/compiler/nir/nir_gather_info.c
> index 946939657ec..555ae77b1d3 100644
> --- a/src/compiler/nir/nir_gather_info.c
> +++ b/src/compiler/nir/nir_gather_info.c
> @@ -247,6 +247,7 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, 
> nir_shader *shader)
> case nir_intrinsic_load_vertex_id:
> case nir_intrinsic_load_vertex_id_zero_base:
> case nir_intrinsic_load_base_vertex:
> +   case nir_intrinsic_load_first_vertex:
> case nir_intrinsic_load_base_instance:
> case nir_intrinsic_load_instance_id:
> case nir_intrinsic_load_sample_id:
> diff --git a/src/compiler/nir/nir_intrinsics.h 
> b/src/compiler/nir/nir_intrinsics.h
> index 20bef339ac4..a7770bf6a85 100644
> --- a/src/compiler/nir/nir_intrinsics.h
> +++ b/src/compiler/nir/nir_intrinsics.h
> @@ -326,6 +326,7 @@ SYSTEM_VALUE(frag_coord, 4, 0, xx, xx, xx)
>  SYSTEM_VALUE(front_face, 1, 0, xx, xx, xx)
>  SYSTEM_VALUE(vertex_id, 1, 0, xx, xx, xx)
>  SYSTEM_VALUE(vertex_id_zero_base, 1, 0, xx, xx, xx)
> +SYSTEM_VALUE(first_vertex, 1, 0, xx, xx, xx)
>  SYSTEM_VALUE(base_vertex, 1, 0, xx, xx, xx)
>  SYSTEM_VALUE(instance_id, 1, 0, xx, xx, xx)
>  SYSTEM_VALUE(base_instance, 1, 0, xx, xx, xx)
> diff --git a/src/compiler/shader_enums.c b/src/compiler/shader_enums.c
> index 2179c475abd..5e123f29f37 100644
> --- a/src/compiler/shader_enums.c
> +++ b/src/compiler/shader_enums.c
> @@ -214,6 +214,7 @@ gl_system_value_name(gl_system_value sysval)
>   ENUM(SYSTEM_VALUE_INSTANCE_ID),
>   ENUM(SYSTEM_VALUE_INSTANCE_INDEX),
>   ENUM(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE),
> + ENUM(SYSTEM_VALUE_FIRST_VERTEX),
>   ENUM(SYSTEM_VALUE_BASE_VERTEX),
>   ENUM(SYSTEM_VALUE_BASE_INSTANCE),
>   ENUM(SYSTEM_VALUE_DRAW_ID),
> diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h
> index ffe551ab20f..76bb2cc4203 100644
> --- a/src/compiler/shader_enums.h
> +++ b/src/compiler/shader_enums.h
> @@ -472,6 +472,21 @@ typedef enum
>  */
> SYSTEM_VALUE_BASE_VERTEX,
>  
> +

Delete this blank line.

> +   /**
> +* Depending on the type of the draw call (indexed or non-indexed),
> +* is the value of \c basevertex passed to \c glDrawElementsBaseVertex and
> +* similar, or is the value of \c first passed to \c glDrawArrays and
> +* similar.
> +*
> +* \note
> +* It can be used to calculate the \c SYSTEM_VALUE_VERTEX_ID as
> +* \c SYSTEM_VALUE_VERTEX_ID_ZERO_BASE plus \c SYSTEM_VALUE_FIRST_VERTEX.
> +*
> +* \sa SYSTEM_VALUE_VERTEX_ID_ZERO_BASE, SYSTEM_VALUE_VERTEX_ID
> +*/
> +   SYSTEM_VALUE_FIRST_VERTEX,
> +
> /**
>  * Value of \c baseinstance passed to instanced draw entry points
>  *
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/4] meson: Build SWR driver

[Dylan Baker]

Quoting Eric Engestrom (2017-12-11 07:49:07)
> > +if with_gallium_swr
> > +  if meson.version().version_compare('< 0.44.0')
> > +error('SWR requires meson 0.44.0 or greater.')
> > +  endif
> 
> Mixed feelings about this, but I guess I'd rather land this now and
> remove these three lines later.

I'm not really a big fan either, but I'm even less of a fan of requiring 0.44
(which was released yesterday) when nothing except SWR and clover actually
depend on it, and neither of those are the most common components of mesa.

Given a couple more releases I'd like to bump the requirements.
Unfortunately I'm not sure what the final version we're going to require is, I'd
still like to overhaul meson's pkg-config generator to be smarter, but that
wont land until 0.45 at the earliest.

Dylan


signature.asc
Description: signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/8] spirv: Add a prepass to set types on vtn_values

[Ian Romanick]

On 12/11/2017 10:50 AM, Jason Ekstrand wrote:
> On Mon, Dec 11, 2017 at 9:50 AM, Ian Romanick  > wrote:
> 
> On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> > This autogenerated pass will automatically find and set the type field
> > on all vtn_values.  This way we always have the type and can use
> it for
> > validation and other checks.
> > ---
> >  src/compiler/Makefile.nir.am            
>  |   4 +
> >  src/compiler/nir/meson.build             |  11 ++-
> >  src/compiler/spirv/spirv_to_nir.c        |   6 +-
> >  src/compiler/spirv/vtn_gather_types_c.py | 125
> +++
> >  src/compiler/spirv/vtn_private.h         |   4 +
> >  5 files changed, 148 insertions(+), 2 deletions(-)
> >  create mode 100644 src/compiler/spirv/vtn_gather_types_c.py
> >
> > diff --git a/src/compiler/Makefile.nir.am 
> b/src/compiler/Makefile.nir.am 
> > index 1533ee5..dd38c45 100644
> > --- a/src/compiler/Makefile.nir.am 
> > +++ b/src/compiler/Makefile.nir.am 
> > @@ -56,6 +56,10 @@ spirv/spirv_info.c: spirv/spirv_info_c.py
> spirv/spirv.core.grammar.json
> >       $(MKDIR_GEN)
> >       $(PYTHON_GEN) $(srcdir)/spirv/spirv_info_c.py
> $(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false)
> >
> > +spirv/vtn_gather_types.c: spirv/vtn_gather_types_c.py
> spirv/spirv.core.grammar.json
> > +     $(MKDIR_GEN)
> > +     $(PYTHON_GEN) $(srcdir)/spirv/vtn_gather_types_c.py
> $(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false)
> > +
> >  noinst_PROGRAMS += spirv2nir
> >
> >  spirv2nir_SOURCES = \
> > diff --git a/src/compiler/nir/meson.build
> b/src/compiler/nir/meson.build
> > index b61a077..5dd21e6 100644
> > --- a/src/compiler/nir/meson.build
> > +++ b/src/compiler/nir/meson.build
> > @@ -72,6 +72,14 @@ spirv_info_c = custom_target(
> >    command : [prog_python2, '@INPUT0@', '@INPUT1@', '@OUTPUT@'],
> >  )
> >
> > +vtn_gather_types_c = custom_target(
> > +  'vtn_gather_types.c',
> > +  input : files('../spirv/vtn_gather_types_c.py',
> > +                '../spirv/spirv.core.grammar.json'),
> > +  output : 'vtn_gather_types.c',
> > +  command : [prog_python2, '@INPUT0@', '@INPUT1@', '@OUTPUT@'],
> > +)
> > +
> >  files_libnir = files(
> >    'nir.c',
> >    'nir.h',
> > @@ -189,7 +197,8 @@ files_libnir = files(
> >  libnir = static_library(
> >    'nir',
> >    [files_libnir, spirv_info_c, nir_opt_algebraic_c, nir_opcodes_c,
> > -   nir_opcodes_h, nir_constant_expressions_c, nir_builder_opcodes_h],
> > +   nir_opcodes_h, nir_constant_expressions_c, nir_builder_opcodes_h,
> > +   vtn_gather_types_c],
> >    include_directories : [inc_common, inc_compiler,
> include_directories('../spirv')],
> >    c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
> >    link_with : libcompiler,
> > diff --git a/src/compiler/spirv/spirv_to_nir.c
> b/src/compiler/spirv/spirv_to_nir.c
> > index a50b14d..a2426bc 100644
> > --- a/src/compiler/spirv/spirv_to_nir.c
> > +++ b/src/compiler/spirv/spirv_to_nir.c
> > @@ -1261,7 +1261,6 @@ vtn_handle_constant(struct vtn_builder *b,
> SpvOp opcode,
> >                      const uint32_t *w, unsigned count)
> >  {
> >     struct vtn_value *val = vtn_push_value(b, w[2],
> vtn_value_type_constant);
> > -   val->type = vtn_value(b, w[1], vtn_value_type_type)->type;
> >     val->constant = rzalloc(b, nir_constant);
> >     switch (opcode) {
> >     case SpvOpConstantTrue:
> > @@ -3268,6 +3267,8 @@ static bool
> >  vtn_handle_variable_or_type_instruction(struct vtn_builder *b,
> SpvOp opcode,
> >                                          const uint32_t *w,
> unsigned count)
> >  {
> > +   vtn_set_instruction_result_type(b, opcode, w, count);
> > +
> >     switch (opcode) {
> >     case SpvOpSource:
> >     case SpvOpSourceContinued:
> > @@ -3658,6 +3659,9 @@ spirv_to_nir(const uint32_t *words, size_t
> word_count,
> >     words = vtn_foreach_instruction(b, words, word_end,
> >                                   
>  vtn_handle_variable_or_type_instruction);
> >
> > +   /* Set types on all vtn_values */
> > +   vtn_foreach_instruction(b, words, word_end,
> vtn_set_instruction_result_type);
> > +
> >     vtn_build_cfg(b, words, word_end);
> >
> >     assert(b->entry_point->value_type == vtn_value_type_function);
> > diff --git a/src/compiler/spirv/vtn_gather_types_c.py
> b/src/compiler/spirv/vtn_gather_types_c.py
> > new file mode 100644
> > index 000..8cd8d9f
> > --- /dev/null
>

Re: [Mesa-dev] [PATCH v2 3/7] intel: emit first_vertex and reorder the VE' components

[Kenneth Graunke]

On Tuesday, December 5, 2017 3:23:03 PM PST Kenneth Graunke wrote:
> Reviewed-by: Kenneth Graunke 

It turns out that patches 1-3 by themselves cause piles of Piglit and
CTS failures.  Please make sure the series doesn't cause regressions at
each step along the way.

For reference, here are some of the failures I noticed when testing:

piglit.spec.arb_draw_indirect.gl_vertexid used with gldrawarraysindirect
piglit.spec.arb_draw_indirect.gl_vertexid used with gldrawelementsindirect
piglit.spec.arb_gpu_shader_fp64.shader_storage.layout-std140-fp64-shader
piglit.spec.arb_shader_draw_parameters.baseinstance [Gen6-7.5 only?]
piglit.spec.arb_shader_draw_parameters.drawid-indirect-baseinstance
piglit.spec.arb_shader_draw_parameters.drawid-indirect-basevertex
piglit.spec.arb_shader_draw_parameters.drawid-indirect-vertexid
piglit.spec.arb_shader_draw_parameters.drawid-vertexid
piglit.spec.arb_shader_storage_buffer_object.layout-std140-write-shader
piglit.spec.arb_shader_storage_buffer_object.layout-std430-write-shader
piglit.spec.glsl-1_50.transform-feedback-vertex-id
piglit.spec.!opengl 3_0.gl_vertexid used with glmultidrawarrays
piglit.spec.!opengl 3_2.gl_vertexid used with glmultidrawelementsbasevertex
piglit.spec.!opengl es 3_0.gl_vertexid used with gldrawarrays
dEQP-GLES31.functional.draw_base_vertex.draw_elements_base_vertex.builtin_variable.vertex_id
dEQP-GLES31.functional.draw_base_vertex.draw_elements_instanced_base_vertex.builtin_variable.vertex_id
dEQP-GLES31.functional.draw_base_vertex.draw_range_elements_base_vertex.builtin_variable.vertex_id
dEQP-GLES31.functional.primitive_bounding_box.clear.full_clear_with_triangles
dEQP-GLES31.functional.primitive_bounding_box.clear.scissored_clear_with_triangles
dEQP-GLES3.functional.shaders.builtin_variable.vertex_id
KHR-GL46.clip_distance.functional
KHR-GL46.draw_elements_base_vertex_tests.AEP_shader_stages
KHR-GL46.draw_elements_base_vertex_tests.basevertex_behavior1
KHR-GL46.draw_elements_base_vertex_tests.overflow
KHR-GL46.draw_elements_base_vertex_tests.underflow
KHR-GL46.enhanced_layouts.vertex_attrib_locations
KHR-GL46.geometry_shader.rendering.rendering.lines_input_line_strip_output_line_loop_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_input_line_strip_output_lines_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_input_line_strip_output_line_strip_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_input_points_output_line_loop_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_input_points_output_lines_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_input_points_output_line_strip_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_input_triangle_strip_output_line_loop_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_input_triangle_strip_output_lines_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_input_triangle_strip_output_line_strip_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_with_adjacency_input_line_strip_output_lines_adjacency_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_with_adjacency_input_line_strip_output_line_strip_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_with_adjacency_input_points_output_lines_adjacency_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_with_adjacency_input_points_output_line_strip_drawcall
KHR-GL46.geometry_shader.rendering.rendering.lines_with_adjacency_input_triangle_strip_output_lines_adjacency_drawcall
KHR-GL46.geometry_shader.rendering.rendering.points_input_line_strip_output
KHR-GL46.geometry_shader.rendering.rendering.points_input_points_output
KHR-GL46.geometry_shader.rendering.rendering.points_input_triangles_output
KHR-GL46.geometry_shader.rendering.rendering.triangles_input_line_strip_output_triangle_fan_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_input_line_strip_output_triangles_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_input_line_strip_output_triangle_strip_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_input_points_output_triangle_fan_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_input_points_output_triangles_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_input_points_output_triangle_strip_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_input_triangle_strip_output_triangle_fan_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_input_triangle_strip_output_triangles_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_input_triangle_strip_output_triangle_strip_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_with_adjacency_input_line_strip_output_triangles_adjacency_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_with_adjacency_input_line_strip_output_triangle_strip_adjacency_drawcall
KHR-GL46.geometry_shader.rendering.rendering.triangles_with_adjacency_input_points_output_triangles_adjacency_drawcall
KHR-G

Re: [Mesa-dev] [PATCH 1/3] nir: Fix interaction of GL_CLAMP lowering with texture offsets.

[Ian Romanick]

For some reason the patches didn't show up in my inbox, but I found it
on patchwork.  Series is

Reviewed-by: Ian Romanick 

On 12/06/2017 07:10 PM, Eric Anholt wrote:
> Eric Anholt  writes:
> 
>> We want the clamping of the coordinate to apply after the offset, so we
>> need to do math to lower the offset out of the instruction.  Fixes texwrap
>> offset cases for GL_CLAMP with GL_NEAREST on vc5.
> 
> Still looking for a review on this series.
> 
> 
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 




signature.asc
Description: OpenPGP digital signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 9/9] mesa: always compare optype with symbolic name in ATI_fs

[Marek Olšák]

For the series:

Reviewed-by: Marek Olšák 

Marek

On Sat, Dec 2, 2017 at 11:35 PM, Miklós Máté  wrote:
> Signed-off-by: Miklós Máté 
> ---
>  src/mesa/main/atifragshader.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/main/atifragshader.c b/src/mesa/main/atifragshader.c
> index 8538e3a53e..6b636f1dc7 100644
> --- a/src/mesa/main/atifragshader.c
> +++ b/src/mesa/main/atifragshader.c
> @@ -76,7 +76,7 @@ _mesa_delete_ati_fragment_shader(struct gl_context *ctx, 
> struct ati_fragment_sha
>  static void match_pair_inst(struct ati_fragment_shader *curProg, GLuint 
> optype)
>  {
> if (optype == curProg->last_optype) {
> -  curProg->last_optype = 1;
> +  curProg->last_optype = ATI_FRAGMENT_SHADER_ALPHA_OP;
> }
>  }
>
> @@ -125,7 +125,7 @@ static void debug_op(GLint optype, GLuint arg_count, 
> GLenum op, GLuint dst,
>
>fprintf(stderr, "%s(%s, %s", op_name, _mesa_enum_to_string(op),
>   _mesa_enum_to_string(dst));
> -  if (!optype)
> +  if (optype == ATI_FRAGMENT_SHADER_COLOR_OP)
>  fprintf(stderr, ", %d", dstMask);
>
>fprintf(stderr, ", %s", create_dst_mod_str(dstMod));
> @@ -631,7 +631,7 @@ _mesa_FragmentOpXATI(GLint optype, GLuint arg_count, 
> GLenum op, GLuint dst,
>_mesa_error(ctx, GL_INVALID_ENUM, "C/AFragmentOpATI(op)");
>return;
> }
> -   if (optype == 1) {
> +   if (optype == ATI_FRAGMENT_SHADER_ALPHA_OP) {
>if (((op == GL_DOT2_ADD_ATI) && (curI->Opcode[0] != GL_DOT2_ADD_ATI)) 
> ||
>  ((op == GL_DOT3_ATI) && (curI->Opcode[0] != GL_DOT3_ATI)) ||
>  ((op == GL_DOT4_ATI) && (curI->Opcode[0] != GL_DOT4_ATI)) ||
> --
> 2.15.0.rc0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/8] spirv: Add a prepass to set types on vtn_values

[Jason Ekstrand]

On Mon, Dec 11, 2017 at 9:50 AM, Ian Romanick  wrote:

> On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> > This autogenerated pass will automatically find and set the type field
> > on all vtn_values.  This way we always have the type and can use it for
> > validation and other checks.
> > ---
> >  src/compiler/Makefile.nir.am |   4 +
> >  src/compiler/nir/meson.build |  11 ++-
> >  src/compiler/spirv/spirv_to_nir.c|   6 +-
> >  src/compiler/spirv/vtn_gather_types_c.py | 125
> +++
> >  src/compiler/spirv/vtn_private.h |   4 +
> >  5 files changed, 148 insertions(+), 2 deletions(-)
> >  create mode 100644 src/compiler/spirv/vtn_gather_types_c.py
> >
> > diff --git a/src/compiler/Makefile.nir.am b/src/compiler/Makefile.nir.am
> > index 1533ee5..dd38c45 100644
> > --- a/src/compiler/Makefile.nir.am
> > +++ b/src/compiler/Makefile.nir.am
> > @@ -56,6 +56,10 @@ spirv/spirv_info.c: spirv/spirv_info_c.py
> spirv/spirv.core.grammar.json
> >   $(MKDIR_GEN)
> >   $(PYTHON_GEN) $(srcdir)/spirv/spirv_info_c.py
> $(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false)
> >
> > +spirv/vtn_gather_types.c: spirv/vtn_gather_types_c.py
> spirv/spirv.core.grammar.json
> > + $(MKDIR_GEN)
> > + $(PYTHON_GEN) $(srcdir)/spirv/vtn_gather_types_c.py
> $(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false)
> > +
> >  noinst_PROGRAMS += spirv2nir
> >
> >  spirv2nir_SOURCES = \
> > diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> > index b61a077..5dd21e6 100644
> > --- a/src/compiler/nir/meson.build
> > +++ b/src/compiler/nir/meson.build
> > @@ -72,6 +72,14 @@ spirv_info_c = custom_target(
> >command : [prog_python2, '@INPUT0@', '@INPUT1@', '@OUTPUT@'],
> >  )
> >
> > +vtn_gather_types_c = custom_target(
> > +  'vtn_gather_types.c',
> > +  input : files('../spirv/vtn_gather_types_c.py',
> > +'../spirv/spirv.core.grammar.json'),
> > +  output : 'vtn_gather_types.c',
> > +  command : [prog_python2, '@INPUT0@', '@INPUT1@', '@OUTPUT@'],
> > +)
> > +
> >  files_libnir = files(
> >'nir.c',
> >'nir.h',
> > @@ -189,7 +197,8 @@ files_libnir = files(
> >  libnir = static_library(
> >'nir',
> >[files_libnir, spirv_info_c, nir_opt_algebraic_c, nir_opcodes_c,
> > -   nir_opcodes_h, nir_constant_expressions_c, nir_builder_opcodes_h],
> > +   nir_opcodes_h, nir_constant_expressions_c, nir_builder_opcodes_h,
> > +   vtn_gather_types_c],
> >include_directories : [inc_common, inc_compiler,
> include_directories('../spirv')],
> >c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
> >link_with : libcompiler,
> > diff --git a/src/compiler/spirv/spirv_to_nir.c
> b/src/compiler/spirv/spirv_to_nir.c
> > index a50b14d..a2426bc 100644
> > --- a/src/compiler/spirv/spirv_to_nir.c
> > +++ b/src/compiler/spirv/spirv_to_nir.c
> > @@ -1261,7 +1261,6 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp
> opcode,
> >  const uint32_t *w, unsigned count)
> >  {
> > struct vtn_value *val = vtn_push_value(b, w[2],
> vtn_value_type_constant);
> > -   val->type = vtn_value(b, w[1], vtn_value_type_type)->type;
> > val->constant = rzalloc(b, nir_constant);
> > switch (opcode) {
> > case SpvOpConstantTrue:
> > @@ -3268,6 +3267,8 @@ static bool
> >  vtn_handle_variable_or_type_instruction(struct vtn_builder *b, SpvOp
> opcode,
> >  const uint32_t *w, unsigned
> count)
> >  {
> > +   vtn_set_instruction_result_type(b, opcode, w, count);
> > +
> > switch (opcode) {
> > case SpvOpSource:
> > case SpvOpSourceContinued:
> > @@ -3658,6 +3659,9 @@ spirv_to_nir(const uint32_t *words, size_t
> word_count,
> > words = vtn_foreach_instruction(b, words, word_end,
> > vtn_handle_variable_or_type_
> instruction);
> >
> > +   /* Set types on all vtn_values */
> > +   vtn_foreach_instruction(b, words, word_end,
> vtn_set_instruction_result_type);
> > +
> > vtn_build_cfg(b, words, word_end);
> >
> > assert(b->entry_point->value_type == vtn_value_type_function);
> > diff --git a/src/compiler/spirv/vtn_gather_types_c.py
> b/src/compiler/spirv/vtn_gather_types_c.py
> > new file mode 100644
> > index 000..8cd8d9f
> > --- /dev/null
> > +++ b/src/compiler/spirv/vtn_gather_types_c.py
> > @@ -0,0 +1,125 @@
> > +COPYRIGHT = """\
> > +/*
> > + * Copyright (C) 2017 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> obtaining a
> > + * copy of this software and associated documentation files (the
> "Software"),
> > + * to deal in the Software without restriction, including without
> limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > +

Re: [Mesa-dev] [PATCH 21/18] ac: skip type for tcs input on RADV

[Dieter Nützel]

Tim,

I'm somewhat baffled...
V1 do not have 20,21
V2 do not have 19,21
V3 do not have 19,20

Which one is right?

Thanks,
Dieter

Am 11.12.2017 10:56, schrieb Timothy Arceri:

The type can be a struct on RADV and causes an assert() to be
thrown, for radeonsi all structs should have been lowered away.
---
 src/amd/common/ac_nir_to_llvm.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c 
b/src/amd/common/ac_nir_to_llvm.c

index 38a840bf813..1466c7f875f 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2972,23 +2972,25 @@ static LLVMValueRef visit_load_var(struct
ac_nir_context *ctx,
unsigned const_index = 0;
unsigned location = 
instr->variables[0]->var->data.location;
 			unsigned driver_location = 
instr->variables[0]->var->data.driver_location;

const bool is_patch =  
instr->variables[0]->var->data.patch;
const bool is_compact = 
instr->variables[0]->var->data.compact;

get_deref_offset(ctx, instr->variables[0],
 false, NULL, is_patch ? NULL : 
&vertex_index,
 &const_index, &indir_index);

+   LLVMTypeRef type = ctx->nctx ? NULL :
+   nir2llvmtype(ctx, 
instr->variables[0]->var->type);
+
 			result = ctx->abi->load_tess_inputs(ctx->abi, vertex_index, 
indir_index,

-   const_index, 
location, driver_location,
-   nir2llvmtype(ctx, 
instr->variables[0]->var->type),
+   const_index, 
location, driver_location, type,

instr->variables[0]->var->data.location_frac,

instr->num_components,
is_patch, 
is_compact);
return ctx->nctx ?
LLVMBuildBitCast(ctx->nctx->builder, result, 
get_def_type(ctx,
&instr->dest.ssa), "") :
result;
}

if (ctx->stage == MESA_SHADER_GEOMETRY) {
LLVMValueRef indir_index;

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/2] gallium/util: don't pass a pipe_resource to util_resource_is_array_texture()

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Thu, Dec 7, 2017 at 11:25 PM, Brian Paul  wrote:
> No need to pass a pipe_resource when we can just pass the target.
> This makes the function potentially more usable.  Rename it too.
> ---
>  src/gallium/auxiliary/util/u_resource.h   | 6 +++---
>  src/gallium/drivers/radeon/r600_texture.c | 2 +-
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_resource.h 
> b/src/gallium/auxiliary/util/u_resource.h
> index 6736476..3c6194b 100644
> --- a/src/gallium/auxiliary/util/u_resource.h
> +++ b/src/gallium/auxiliary/util/u_resource.h
> @@ -32,14 +32,14 @@ unsigned
>  util_resource_size(const struct pipe_resource *res);
>
>  /**
> - * Return true if the resource is an array texture.
> + * Return true if the texture target is an array type.
>   *
>   * Note that this function returns true for single-layered array textures.
>   */
>  static inline boolean
> -util_resource_is_array_texture(const struct pipe_resource *res)
> +util_texture_is_array(enum pipe_texture_target target)
>  {
> -   switch (res->target) {
> +   switch (target) {
> case PIPE_TEXTURE_1D_ARRAY:
> case PIPE_TEXTURE_2D_ARRAY:
> case PIPE_TEXTURE_CUBE_ARRAY:
> diff --git a/src/gallium/drivers/radeon/r600_texture.c 
> b/src/gallium/drivers/radeon/r600_texture.c
> index cb69398..66d4f02 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -582,7 +582,7 @@ static void si_query_opaque_metadata(struct si_screen 
> *sscreen,
> PIPE_SWIZZLE_W
> };
> uint32_t desc[8], i;
> -   bool is_array = util_resource_is_array_texture(res);
> +   bool is_array = util_texture_is_array(res->target);
>
> /* DRM 2.x.x doesn't support this. */
> if (sscreen->info.drm_major != 3)
> --
> 1.9.1
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH mesa] i915: add missing 0 defines

[Ian Romanick]

Reviewed-by: Ian Romanick 

On 12/04/2017 06:52 AM, Eric Engestrom wrote:
> Thanks to Emil's -Wundef, t_dd_dmatmp.h now complains that intel_render.c
> is missing a couple `#define`s.
> 
> Assigning them to 0 keeps the existing behaviour; I'll let someone else
> turn them on if this is the behaviour that was intended.
> 
> Signed-off-by: Eric Engestrom 
> ---
>  src/mesa/drivers/dri/i915/intel_render.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i915/intel_render.c 
> b/src/mesa/drivers/dri/i915/intel_render.c
> index c1603565cc2a6157c0bd..a3952826246a7e52aea6 100644
> --- a/src/mesa/drivers/dri/i915/intel_render.c
> +++ b/src/mesa/drivers/dri/i915/intel_render.c
> @@ -62,6 +62,8 @@
>  #define HAVE_TRI_FANS1
>  #define HAVE_POLYGONS1
>  
> +#define HAVE_QUADS   0
> +#define HAVE_QUAD_STRIPS 0
>  #define HAVE_ELTS0
>  
>  static const uint32_t hw_prim[GL_POLYGON + 1] = {
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] testing for certain compiler options does not work

[Ian Romanick]

On 12/07/2017 02:15 AM, Marc Dietrich wrote:
> Hi Ian,
> 
> Am Mittwoch, 6. Dezember 2017, 21:21:53 CET schrieb Ian Romanick:
>> On 11/29/2017 08:16 AM, Marc Dietrich wrote:
>>> Hi,
>>>
>>> just found that my gcc 'gcc (SUSE Linux) 7.2.1 20171020 [gcc-7-branch
>>> revision 253932]' does not warn when using the negative form of
>>> unsupported warning options. So all the configure tests for such options
>>> erroneously succeed, e.g:
>>>
>>> gcc -Wno-bob test.c # works fine
>>>
>>> gcc -Walice test.c # warns for unsupported compiler option
>>>
>>> Maybe gcc bug or intended behaviour, maybe only unique to my version?
>>
>> At least 6.4.1 does not have this problem, but our checks must be broken
>> in a different way.  I see piles of
> 
> I just found that this is not a gcc bug but a feature (since 4.4), so this 
> should also happen with your compiler:
> 
> https://gcc.gnu.org/wiki/FAQ#wnowarning
> 
>>
>> cc1: warning: unrecognized command line option ‘-Wno-initializer-
> overrides’
> 
> this should not happen, because this is the clang option which fails with 
> gcc. 
> Is this with meson or autotools? Are you sure you applied the patch? I tested 
> it with both, gcc and clang and it works file here.

This was without your patch.  I didn't test your patch. :)  To answer
the other question, I've recently been seeing this with meson, but I
believe I also saw it with autotools.

>> This probably explains why I see piles of
>>
>> cc1: warning: unrecognized command line option ‘-Wno-initializer-
> overrides’
>>
>> in my builds.




signature.asc
Description: OpenPGP digital signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] gallium/aux: include nr_samples in util_resource_size() computation

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Thu, Dec 7, 2017 at 11:25 PM, Brian Paul  wrote:
> This function is only used in two places:
> 1. VMware driver, but only for HUD reporting
> 2. st/nine state tracker, used for texture memory accounting
> ---
>  src/gallium/auxiliary/util/u_resource.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/util/u_resource.c 
> b/src/gallium/auxiliary/util/u_resource.c
> index 66caaae..ed6c150 100644
> --- a/src/gallium/auxiliary/util/u_resource.c
> +++ b/src/gallium/auxiliary/util/u_resource.c
> @@ -42,6 +42,7 @@ util_resource_size(const struct pipe_resource *res)
> unsigned depth = res->depth0;
> unsigned size = 0;
> unsigned level;
> +   unsigned samples = MAX2(1, res->nr_samples);
>
> for (level = 0; level <= res->last_level; level++) {
>unsigned slices;
> @@ -54,7 +55,7 @@ util_resource_size(const struct pipe_resource *res)
>   slices = res->array_size;
>
>size += (util_format_get_nblocksy(res->format, height) *
> -   util_format_get_stride(res->format, width) * slices);
> +   util_format_get_stride(res->format, width) * slices * 
> samples);
>
>width  = u_minify(width, 1);
>height = u_minify(height, 1);
> --
> 1.9.1
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 8/8] spirv: Add support for all bit sizes in OpSwitch

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101560
> Cc: Juan A. Suarez Romero 
> ---
>  src/compiler/spirv/vtn_cfg.c | 33 +
>  1 file changed, 25 insertions(+), 8 deletions(-)
> 
> diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
> index 9d1ca84..3befc1f 100644
> --- a/src/compiler/spirv/vtn_cfg.c
> +++ b/src/compiler/spirv/vtn_cfg.c
> @@ -170,7 +170,7 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
> SpvOp opcode,
>  static void
>  vtn_add_case(struct vtn_builder *b, struct vtn_switch *swtch,
>   struct vtn_block *break_block,
> - uint32_t block_id, uint32_t val, bool is_default)
> + uint32_t block_id, uint64_t val, bool is_default)
>  {
> struct vtn_block *case_block =
>vtn_value(b, block_id, vtn_value_type_block)->block;
> @@ -197,7 +197,7 @@ vtn_add_case(struct vtn_builder *b, struct vtn_switch 
> *swtch,
> if (is_default) {
>case_block->switch_case->is_default = true;
> } else {
> -  util_dynarray_append(&case_block->switch_case->values, uint32_t, val);
> +  util_dynarray_append(&case_block->switch_case->values, uint64_t, val);
> }
>  }
>  
> @@ -425,12 +425,29 @@ vtn_cfg_walk_blocks(struct vtn_builder *b, struct 
> list_head *cf_list,
>   const uint32_t *branch_end =
>  block->branch + (block->branch[0] >> SpvWordCountShift);
>  
> + struct vtn_value *cond_val = vtn_untyped_value(b, block->branch[1]);
> + vtn_fail_if(!cond_val->type ||
> + cond_val->type->base_type != vtn_base_type_scalar,
> + "Selector of OpSelect must have a type of OpTypeInt");
> +
> + nir_alu_type cond_type =
> +nir_get_nir_type_for_glsl_type(cond_val->type->type);
> + vtn_fail_if(nir_alu_type_get_base_type(cond_type) != nir_type_int &&
> + nir_alu_type_get_base_type(cond_type) != nir_type_uint,
> + "Selector of OpSelect must have a type of OpTypeInt");
> +
>   bool is_default = true;
>   for (const uint32_t *w = block->branch + 2; w < branch_end;) {
> -uint32_t literal = 0;
> +uint64_t literal = 0;
>  if (!is_default) {
> -   literal = *w;
> -   w++;
> +   if (nir_alu_type_get_type_size(cond_type) <= 32) {
> +  literal = *w;
> +  w++;
> +   } else {
> +  assert(nir_alu_type_get_type_size(cond_type) == 64);
> +  literal = vtn_u64_literal(w);
> +  w += 2;
> +   }
>  }
>  
>  uint32_t block_id = *w;
> @@ -730,9 +747,9 @@ vtn_emit_cf_list(struct vtn_builder *b, struct list_head 
> *cf_list,
>  }
>  
>  nir_ssa_def *cond = NULL;
> -util_dynarray_foreach(&cse->values, uint32_t, val) {
> -   nir_ssa_def *is_val =
> -  nir_ieq(&b->nb, sel, nir_imm_int(&b->nb, *val));
> +util_dynarray_foreach(&cse->values, uint64_t, val) {
> +   nir_ssa_def *imm = nir_imm_intN_t(&b->nb, *val, 
> sel->bit_size);
> +   nir_ssa_def *is_val = nir_ieq(&b->nb, sel, imm);
>  
> cond = cond ? nir_ior(&b->nb, cond, is_val) : is_val;
>  }
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 7/8] spirv: Restructure the case loop in OpSwitch handling

[Ian Romanick]

On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> Instead of calling vtn_add_case for the default case and then looping,
> add an is_default variable and do everything inside the loop.  This will
> make the next commit easier.
> ---
>  src/compiler/spirv/vtn_cfg.c | 17 ++---
>  1 file changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
> index 25140ff..9d1ca84 100644
> --- a/src/compiler/spirv/vtn_cfg.c
> +++ b/src/compiler/spirv/vtn_cfg.c
> @@ -425,9 +425,20 @@ vtn_cfg_walk_blocks(struct vtn_builder *b, struct 
> list_head *cf_list,
>   const uint32_t *branch_end =
>  block->branch + (block->branch[0] >> SpvWordCountShift);
>  
> - vtn_add_case(b, swtch, break_block, block->branch[2], 0, true);
> - for (const uint32_t *w = block->branch + 3; w < branch_end; w += 2)
> -vtn_add_case(b, swtch, break_block, w[1], w[0], false);
> + bool is_default = true;
> + for (const uint32_t *w = block->branch + 2; w < branch_end;) {
> +uint32_t literal = 0;
> +if (!is_default) {
> +   literal = *w;
> +   w++;
> +}
> +
> +uint32_t block_id = *w;
> +w++;

In other parts of Mesa, this would be

const uint32_t block_id = *(w++);

Is that not the preferred style here too?  Having looked ahead at the
next patch, I can see why the other dereference of w is not like this.

> +
> +vtn_add_case(b, swtch, break_block, block_id, literal, 
> is_default);
> +is_default = false;
> + }
>  
>   /* Now, we go through and walk the blocks.  While we walk through
>* the blocks, we also gather the much-needed fall-through
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/2] gallium/u_blitter: replace tabs with spaces

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Thu, Dec 7, 2017 at 5:09 PM, Brian Paul  wrote:
> ---
>  src/gallium/auxiliary/util/u_blitter.c | 36 
> +-
>  1 file changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_blitter.c 
> b/src/gallium/auxiliary/util/u_blitter.c
> index 2a2fd17..5e8800e 100644
> --- a/src/gallium/auxiliary/util/u_blitter.c
> +++ b/src/gallium/auxiliary/util/u_blitter.c
> @@ -1579,7 +1579,7 @@ bool util_blitter_is_copy_supported(struct 
> blitter_context *blitter,
>  }
>
>  bool util_blitter_is_blit_supported(struct blitter_context *blitter,
> -   const struct pipe_blit_info *info)
> +const struct pipe_blit_info *info)
>  {
> return is_blit_generic_supported(blitter,
>  info->dst.resource, info->dst.format,
> @@ -1988,7 +1988,7 @@ void util_blitter_blit_generic(struct blitter_context 
> *blitter,
>
>  void
>  util_blitter_blit(struct blitter_context *blitter,
> - const struct pipe_blit_info *info)
> +  const struct pipe_blit_info *info)
>  {
> struct pipe_resource *dst = info->dst.resource;
> struct pipe_resource *src = info->src.resource;
> @@ -2020,7 +2020,7 @@ util_blitter_blit(struct blitter_context *blitter,
>  }
>
>  void util_blitter_generate_mipmap(struct blitter_context *blitter,
> - struct pipe_resource *tex,
> +  struct pipe_resource *tex,
>enum pipe_format format,
>unsigned base_level, unsigned last_level,
>unsigned first_layer, unsigned last_layer)
> @@ -2268,10 +2268,10 @@ void util_blitter_clear_depth_stencil(struct 
> blitter_context *blitter,
>
>  /* draw a rectangle across a region using a custom dsa stage - for r600g */
>  void util_blitter_custom_depth_stencil(struct blitter_context *blitter,
> -  struct pipe_surface *zsurf,
> -  struct pipe_surface *cbsurf,
> -  unsigned sample_mask,
> -  void *dsa_stage, float depth)
> +   struct pipe_surface *zsurf,
> +   struct pipe_surface *cbsurf,
> +   unsigned sample_mask,
> +   void *dsa_stage, float depth)
>  {
> struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter;
> struct pipe_context *pipe = ctx->base.pipe;
> @@ -2302,11 +2302,11 @@ void util_blitter_custom_depth_stencil(struct 
> blitter_context *blitter,
> fb_state.height = zsurf->height;
> fb_state.nr_cbufs = 1;
> if (cbsurf) {
> -  fb_state.cbufs[0] = cbsurf;
> -  fb_state.nr_cbufs = 1;
> +  fb_state.cbufs[0] = cbsurf;
> +  fb_state.nr_cbufs = 1;
> } else {
> -  fb_state.cbufs[0] = NULL;
> -  fb_state.nr_cbufs = 0;
> +  fb_state.cbufs[0] = NULL;
> +  fb_state.nr_cbufs = 0;
> }
> fb_state.zsbuf = zsurf;
> pipe->set_framebuffer_state(pipe, &fb_state);
> @@ -2464,13 +2464,13 @@ out:
>
>  /* probably radeon specific */
>  void util_blitter_custom_resolve_color(struct blitter_context *blitter,
> -  struct pipe_resource *dst,
> -  unsigned dst_level,
> -  unsigned dst_layer,
> -  struct pipe_resource *src,
> -  unsigned src_layer,
> -  unsigned sample_mask,
> -  void *custom_blend,
> +   struct pipe_resource *dst,
> +   unsigned dst_level,
> +   unsigned dst_layer,
> +   struct pipe_resource *src,
> +   unsigned src_layer,
> +   unsigned sample_mask,
> +   void *custom_blend,
> enum pipe_format format)
>  {
> struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter;
> --
> 1.9.1
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] gallium/u_blitter: enable MSAA when blitting to MSAA surfaces

[Marek Olšák]

On Thu, Dec 7, 2017 at 5:09 PM, Brian Paul  wrote:
> If we're doing a Z -> Z MSAA blit (for example) we need to enable
> msaa rasterization when drawing the quads so that we can properly
> write the per-sample values.
>
> This fixes a number of Piglit ext_framebuffer_multisample blit tests
> such as ext_framebuffer_multisample/no-color 2 depth combined with
> the VMware driver.
>
> ---
>
> Marek, I'm not sure how this could have worked without MSAA enabled.
> Perhaps you can comment.

Enabling MSAA rasterization should have no effect, because the blitter
draws an axis-aligned quad, so each pixel will generate only one
sample.

radeon drivers still obey the sample mask even if MSAA is disabled. I
guess svga doesn't.

I guess enabling MSAA is OK, but now we also have to save and restore
the "min_samples" value if it's not 1, because we don't want to use
sample shading because u_blitter doesn't need it.

Marek
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 6/8] spirv: Add better parameter validation for vector and matrix types

[Ian Romanick]

On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> ---
>  src/compiler/spirv/spirv_to_nir.c | 14 +++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/src/compiler/spirv/spirv_to_nir.c 
> b/src/compiler/spirv/spirv_to_nir.c
> index 11c8c2a..4b93b11 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -934,7 +934,11 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
>struct vtn_type *base = vtn_value(b, w[2], vtn_value_type_type)->type;
>unsigned elems = w[3];
>  
> -  vtn_assert(glsl_type_is_scalar(base->type));
> +  vtn_fail_if(base->base_type != vtn_base_type_scalar,
> +  "Base type for OpTypeVector must be a scalar");
> +  vtn_fail_if(elems < 2 || elems > 4,
> +  "Invalid component count for OpTypeVector");
> +
>val->type->base_type = vtn_base_type_vector;
>val->type->type = glsl_vector_type(glsl_get_base_type(base->type), 
> elems);
>val->type->length = elems;
> @@ -947,12 +951,16 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
>struct vtn_type *base = vtn_value(b, w[2], vtn_value_type_type)->type;
>unsigned columns = w[3];
>  
> -  vtn_assert(glsl_type_is_vector(base->type));
> +  vtn_fail_if(columns < 2 || columns > 4,
> +  "Invalid column count for OpTypeMatrix");
> +

I think we should still check glsl_type_is_vector here.  The
glsl_type_is_error check below will catch that case, but we'll give a
better error message with the explicit check here.

>val->type->base_type = vtn_base_type_matrix;
>val->type->type = glsl_matrix_type(glsl_get_base_type(base->type),
>   
> glsl_get_vector_elements(base->type),
>   columns);
> -  vtn_assert(!glsl_type_is_error(val->type->type));
> +  vtn_fail_if(glsl_type_is_error(val->type->type),
> +  "Unsupported base type for OpTypeMatrix");
> +  assert(!glsl_type_is_error(val->type->type));
>val->type->length = columns;
>val->type->array_element = base;
>val->type->row_major = false;
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 4/8] spirv: Set lengths on scalar and vector types

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> ---
>  src/compiler/spirv/spirv_to_nir.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/src/compiler/spirv/spirv_to_nir.c 
> b/src/compiler/spirv/spirv_to_nir.c
> index a2426bc..253a012 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -887,6 +887,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
> case SpvOpTypeBool:
>val->type->base_type = vtn_base_type_scalar;
>val->type->type = glsl_bool_type();
> +  val->type->length = 1;
>break;
> case SpvOpTypeInt: {
>int bit_size = w[2];
> @@ -905,6 +906,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
>default:
>   vtn_fail("Invalid int bit size");
>}
> +  val->type->length = 1;
>break;
> }
>  
> @@ -924,6 +926,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
>default:
>   vtn_fail("Invalid float bit size");
>}
> +  val->type->length = 1;
>break;
> }
>  
> @@ -934,6 +937,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
>vtn_assert(glsl_type_is_scalar(base->type));
>val->type->base_type = vtn_base_type_vector;
>val->type->type = glsl_vector_type(glsl_get_base_type(base->type), 
> elems);
> +  val->type->length = elems;
>val->type->stride = glsl_get_bit_size(base->type) / 8;
>val->type->array_element = base;
>break;
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 5/8] spirv: Add type validation for OpSelect

[Ian Romanick]

On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> ---
>  src/compiler/spirv/spirv_to_nir.c | 32 
>  1 file changed, 32 insertions(+)
> 
> diff --git a/src/compiler/spirv/spirv_to_nir.c 
> b/src/compiler/spirv/spirv_to_nir.c
> index 253a012..11c8c2a 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -3460,6 +3460,38 @@ vtn_handle_body_instruction(struct vtn_builder *b, 
> SpvOp opcode,
>/* Handle OpSelect up-front here because it needs to be able to handle
> * pointers and not just regular vectors and scalars.
> */
> +  struct vtn_value *res_val = vtn_untyped_value(b, w[2]);
> +  struct vtn_value *sel_val = vtn_untyped_value(b, w[3]);
> +  struct vtn_value *obj1_val = vtn_untyped_value(b, w[4]);
> +  struct vtn_value *obj2_val = vtn_untyped_value(b, w[5]);
> +
> +  const struct glsl_type *sel_type;
> +  switch (res_val->type->base_type) {
> +  case vtn_base_type_scalar:
> + sel_type = glsl_bool_type();
> + break;
> +  case vtn_base_type_vector:
> + sel_type = glsl_vector_type(GLSL_TYPE_BOOL, res_val->type->length);
> + break;
> +  case vtn_base_type_pointer:
> + /* We need to have actual storage for pointer types */
> + vtn_fail_if(res_val->type->type == NULL,
> + "Invalid pointer result type for OpSelect");
> + sel_type = glsl_bool_type();
> + break;
> +  default:
> + vtn_fail("Result type of OpSelect must be a scalar, vector, or 
> pointer");
> +  }
> +
> +  vtn_fail_if(sel_val->type->type != sel_type,
> +  "Condition type of ObSelect must be a scalar or vector of "

OpSelect

With that fixed, this patch is

Reviewed-by: Ian Romanick 

> +  "Boolean type. It must have the same number of components "
> +  "as Result Type");
> +
> +  vtn_fail_if(obj1_val->type != res_val->type ||
> +  obj2_val->type != res_val->type,
> +  "Object types must match the result type in OpSelect");
> +
>struct vtn_type *res_type = vtn_value(b, w[1], 
> vtn_value_type_type)->type;
>struct vtn_ssa_value *ssa = vtn_create_ssa_value(b, res_type->type);
>ssa->def = nir_bcsel(&b->nb, vtn_ssa_value(b, w[3])->def,
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/8] spirv: Add a vtn_type field to all vtn_values

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> At the moment, this just lets us drop the const_type for constants and
> unify things a bit.  Eventually, we will use this to store the types of
> all SPIR-V SSA values.
> ---
>  src/compiler/spirv/spirv_to_nir.c | 63 
> +--
>  src/compiler/spirv/vtn_private.h  |  7 ++---
>  2 files changed, 29 insertions(+), 41 deletions(-)
> 
> diff --git a/src/compiler/spirv/spirv_to_nir.c 
> b/src/compiler/spirv/spirv_to_nir.c
> index d321d1a..a50b14d 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -257,7 +257,7 @@ vtn_ssa_value(struct vtn_builder *b, uint32_t value_id)
>return vtn_undef_ssa_value(b, val->type->type);
>  
> case vtn_value_type_constant:
> -  return vtn_const_ssa_value(b, val->constant, val->const_type);
> +  return vtn_const_ssa_value(b, val->constant, val->type->type);
>  
> case vtn_value_type_ssa:
>return val->ssa;
> @@ -1249,7 +1249,7 @@ handle_workgroup_size_decoration_cb(struct vtn_builder 
> *b,
> dec->literals[0] != SpvBuiltInWorkgroupSize)
>return;
>  
> -   vtn_assert(val->const_type == glsl_vector_type(GLSL_TYPE_UINT, 3));
> +   vtn_assert(val->type->type == glsl_vector_type(GLSL_TYPE_UINT, 3));
>  
> b->shader->info.cs.local_size[0] = val->constant->values[0].u32[0];
> b->shader->info.cs.local_size[1] = val->constant->values[0].u32[1];
> @@ -1261,21 +1261,21 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp 
> opcode,
>  const uint32_t *w, unsigned count)
>  {
> struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_constant);
> -   val->const_type = vtn_value(b, w[1], vtn_value_type_type)->type->type;
> +   val->type = vtn_value(b, w[1], vtn_value_type_type)->type;
> val->constant = rzalloc(b, nir_constant);
> switch (opcode) {
> case SpvOpConstantTrue:
> -  vtn_assert(val->const_type == glsl_bool_type());
> +  vtn_assert(val->type->type == glsl_bool_type());
>val->constant->values[0].u32[0] = NIR_TRUE;
>break;
> case SpvOpConstantFalse:
> -  vtn_assert(val->const_type == glsl_bool_type());
> +  vtn_assert(val->type->type == glsl_bool_type());
>val->constant->values[0].u32[0] = NIR_FALSE;
>break;
>  
> case SpvOpSpecConstantTrue:
> case SpvOpSpecConstantFalse: {
> -  vtn_assert(val->const_type == glsl_bool_type());
> +  vtn_assert(val->type->type == glsl_bool_type());
>uint32_t int_val =
>   get_specialization(b, val, (opcode == SpvOpSpecConstantTrue));
>val->constant->values[0].u32[0] = int_val ? NIR_TRUE : NIR_FALSE;
> @@ -1283,8 +1283,8 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
> }
>  
> case SpvOpConstant: {
> -  vtn_assert(glsl_type_is_scalar(val->const_type));
> -  int bit_size = glsl_get_bit_size(val->const_type);
> +  vtn_assert(glsl_type_is_scalar(val->type->type));
> +  int bit_size = glsl_get_bit_size(val->type->type);
>switch (bit_size) {
>case 64:
>   val->constant->values->u64[0] = vtn_u64_literal(&w[3]);
> @@ -1301,9 +1301,9 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
>break;
> }
> case SpvOpSpecConstant: {
> -  vtn_assert(glsl_type_is_scalar(val->const_type));
> +  vtn_assert(glsl_type_is_scalar(val->type->type));
>val->constant->values[0].u32[0] = get_specialization(b, val, w[3]);
> -  int bit_size = glsl_get_bit_size(val->const_type);
> +  int bit_size = glsl_get_bit_size(val->type->type);
>switch (bit_size) {
>case 64:
>   val->constant->values[0].u64[0] =
> @@ -1327,7 +1327,7 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
>for (unsigned i = 0; i < elem_count; i++)
>   elems[i] = vtn_value(b, w[i + 3], 
> vtn_value_type_constant)->constant;
>  
> -  switch (glsl_get_base_type(val->const_type)) {
> +  switch (glsl_get_base_type(val->type->type)) {
>case GLSL_TYPE_UINT:
>case GLSL_TYPE_INT:
>case GLSL_TYPE_UINT16:
> @@ -1338,14 +1338,14 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp 
> opcode,
>case GLSL_TYPE_FLOAT16:
>case GLSL_TYPE_BOOL:
>case GLSL_TYPE_DOUBLE: {
> - int bit_size = glsl_get_bit_size(val->const_type);
> - if (glsl_type_is_matrix(val->const_type)) {
> -vtn_assert(glsl_get_matrix_columns(val->const_type) == 
> elem_count);
> + int bit_size = glsl_get_bit_size(val->type->type);
> + if (glsl_type_is_matrix(val->type->type)) {
> +vtn_assert(glsl_get_matrix_columns(val->type->type) == 
> elem_count);
>  for (unsigned i = 0; i < elem_count; i++)
> val->constant->values[i] = elems[i]->values[0];
>   } else {
> -vtn_assert(glsl_type_is_vector(val->const_type));
> -

Re: [Mesa-dev] [PATCH] gallivm: fix texture wrapping for texture gather for mirror modes

[Jose Fonseca]

Looks good AFAICT.  Thanks for the detailed comments. I can't really 
follow the math to the minutiae, but I trust your testing.


I wonder how much we gain by maitaining these gather and non-gather 
paths.  That is, I wonder if the hit of just using the more accurate 
gather paths is insignificant.


Some cosmetic remarks inline.

On 10/12/17 04:49, srol...@vmware.com wrote:

From: Roland Scheidegger 

Care must be taken that all coords end up correct, the tests are very
sensitive that everything is correctly rounded. This doesn't matter
for bilinear filter (since picking a wrong texel with weight zero is
ok), and we could also switch the per-sample coords mistakenly.
While here, also optimize the coord_mirror helper a bit (we can do the
mirroring directly by exploiting float rounding, no need for fixing up
odd/even manually).
I did not touch the mirror_clamp and mirror_clamp_to_border modes.
In contrast to mirror_clamp_to_edge and mirror_repeat these are legacy
modes. They are specified against old gl rules, which actually does
the mirroring not per sample (so you get swapped order if the coord
is in the mirrored section). I think the idea though is that they should
follow the respecified mirror_clamp_to_edge rules so the order would be
correct.
---
  src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 242 +++---
  1 file changed, 169 insertions(+), 73 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c 
b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
index b67a089..3605c77 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
@@ -218,34 +218,42 @@ lp_build_sample_texel_soa(struct lp_build_sample_context 
*bld,
  
  
  /**

- * Helper to compute the mirror function for the PIPE_WRAP_MIRROR modes.
+ * Helper to compute the mirror function for the PIPE_WRAP_MIRROR_REPEAT mode.
+ * (Note that with pot sizes could do this much more easily post-scale
+ * with some bit arithmetic.)
   */
  static LLVMValueRef
  lp_build_coord_mirror(struct lp_build_sample_context *bld,
-  LLVMValueRef coord)
+  LLVMValueRef coord, boolean posOnly)
  {
 struct lp_build_context *coord_bld = &bld->coord_bld;
-   struct lp_build_context *int_coord_bld = &bld->int_coord_bld;
-   LLVMValueRef fract, flr, isOdd;
-
-   lp_build_ifloor_fract(coord_bld, coord, &flr, &fract);
-   /* kill off NaNs */
-   /* XXX: not safe without arch rounding, fract can be anything. */
-   fract = lp_build_max_ext(coord_bld, fract, coord_bld->zero,
-GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN);
-
-   /* isOdd = flr & 1 */
-   isOdd = LLVMBuildAnd(bld->gallivm->builder, flr, int_coord_bld->one, "");
+   LLVMValueRef fract;
+   LLVMValueRef half = lp_build_const_vec(bld->gallivm, coord_bld->type, 0.5);
  
-   /* make coord positive or negative depending on isOdd */

-   /* XXX slight overkill masking out sign bit is unnecessary */
-   coord = lp_build_set_sign(coord_bld, fract, isOdd);
+   /*
+* We can just use 2*(x - round(0.5*x)) to do all the mirroring,
+* it all works out. (The result is in range [-1, 1.0], negative if
+* the coord is in the "odd" section, otherwise positive.)
+*/
  
-   /* convert isOdd to float */

-   isOdd = lp_build_int_to_float(coord_bld, isOdd);
+   coord = lp_build_mul(coord_bld, coord, half);
+   fract = lp_build_round(coord_bld, coord);
+   fract = lp_build_sub(coord_bld, coord, fract);
+   coord = lp_build_add(coord_bld, fract, fract);
  
-   /* add isOdd to coord */

-   coord = lp_build_add(coord_bld, coord, isOdd);
+   if (posOnly) {
+  /*
+   * Theoretically it's not quite 100% accurate because the spec says
+   * that ultimately a scaled coord of -x.0 should map to int coord
+   * -x + 1 with mirroring, not -x (this does not matter for bilinear
+   * filtering).
+   */
+  coord = lp_build_abs(coord_bld, coord);
+  /* kill off NaNs */
+  /* XXX: not safe without arch rounding, fract can be anything. */
+  coord = lp_build_max_ext(coord_bld, coord, coord_bld->zero,
+   GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN);
+   }
  
 return coord;

  }
@@ -363,6 +371,11 @@ lp_build_sample_wrap_linear(struct lp_build_sample_context 
*bld,
}
  
/* clamp to [0, length] */

+  /*


Let's merge these comments (ie, one comment with two paragraphs.)  It 
looks more appealing.



+   * Unlike some other wrap modes, this should be correct for gather
+   * too. GL_CLAMP explicitly does this clamp on the coord prior to
+   * actual wrapping (which is per sample).
+   */
coord = lp_build_clamp(coord_bld, coord, coord_bld->zero, length_f);
  
coord = lp_build_sub(coord_bld, coord, half);

@@ -426,8 +439,13 @@ lp_build_sample_wrap_linear(struct lp_build_sample_context 
*bld,
   offset = lp_build_int_to_float(coord_bld, offset);

Re: [Mesa-dev] [PATCH 3/8] spirv: Add basic type validation for OpLoad, OpStore, and OpCopyMemory

[Ian Romanick]

On 12/07/2017 02:26 PM, Jason Ekstrand wrote:
> On Thu, Dec 7, 2017 at 11:54 AM, Michael Schellenberger Costa
>  > wrote:
> 
> Hi Jason,
> 
> 
> Am 07.12.2017 um 17:12 schrieb Jason Ekstrand:
> 
> ---
>   src/compiler/spirv/vtn_variables.c | 18 ++
>   1 file changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/src/compiler/spirv/vtn_variables.c
> b/src/compiler/spirv/vtn_variables.c
> index cf44ed3..8ce19ff 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1969,6 +1969,9 @@ vtn_handle_variables(struct vtn_builder
> *b, SpvOp opcode,
>         struct vtn_value *dest = vtn_value(b, w[1],
> vtn_value_type_pointer);
>         struct vtn_value *src = vtn_value(b, w[2],
> vtn_value_type_pointer);
>   +      vtn_fail_if(dest->type->deref != src->type->deref,
> +                  "Result and pointer types of OpLoad do not
> match");
> 
> This should be OpCopyMemory?
> 
> 
> Oops.  Fixed locally.
>  
> 
> On a more general side: As you want to cover every OpCode, why not
> overload vtn_fail_if() so that it takes the OpCode and then prepends
> it to the error message, e.g.:
> 
> vtn_fail_if(dest->type->deref != src->type->deref, opcode,"Result
> and pointer types of do not match");
> 
> Would extend to
> 
> "OpCodeMemory: Result and pointer types of do not match"
> 
> That way there is no chance to really mess op the opcodes.
> 
> 
> I'm not sure what I think about that.  There may be cases where we want
> to use vtn_fail_if where we don't have ready access to the opcode.  One
> option would be to use spirv_opcode_to_string instead of putting it in
> the string but it may be hard to make that happen in such a way that we
> only call that function if the vtn_fail condition is true.

You could make a vtn_fail_opcode_if that takes the opcode as a
parameter.  I'm not sure if that would strictly be an improvement. *shrug*

>  
> 
> All the best
> Michael
> 
> 
> +
>         vtn_variable_copy(b, dest->pointer, src->pointer);
>         break;
>      }
> @@ -1976,8 +1979,11 @@ vtn_handle_variables(struct vtn_builder
> *b, SpvOp opcode,
>      case SpvOpLoad: {
>         struct vtn_type *res_type =
>            vtn_value(b, w[1], vtn_value_type_type)->type;
> -      struct vtn_pointer *src =
> -         vtn_value(b, w[3], vtn_value_type_pointer)->pointer;
> +      struct vtn_value *src_val = vtn_value(b, w[3],
> vtn_value_type_pointer);
> +      struct vtn_pointer *src = src_val->pointer;
> +
> +      vtn_fail_if(res_type != src_val->type->deref,
> +                  "Result and pointer types of OpLoad do not
> match");
>           if (src->mode == vtn_variable_mode_image ||
>             src->mode == vtn_variable_mode_sampler) {
> @@ -1990,8 +1996,12 @@ vtn_handle_variables(struct vtn_builder
> *b, SpvOp opcode,
>      }
>        case SpvOpStore: {
> -      struct vtn_pointer *dest =
> -         vtn_value(b, w[1], vtn_value_type_pointer)->pointer;
> +      struct vtn_value *dest_val = vtn_value(b, w[1],
> vtn_value_type_pointer);
> +      struct vtn_pointer *dest = dest_val->pointer;
> +      struct vtn_value *src_val = vtn_untyped_value(b, w[2]);
> +
> +      vtn_fail_if(dest_val->type->deref != src_val->type,
> +                  "Value and pointer types of OpStore do not
> match");
>           if (glsl_type_is_sampler(dest->type->type)) {
>            vtn_warn("OpStore of a sampler detected.  Doing
> on-the-fly copy "
> 
> 
> 
> 
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] winsys/amdgpu: disable local BOs again due to worse performance

[Nicolai Hähnle]

On 11.12.2017 16:31, Marek Olšák wrote:

From: Marek Olšák 

Cc: 17.3 


Reviewed-by: Nicolai Hähnle 



---
  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 0d82402..4b12735 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -411,23 +411,24 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
amdgpu_winsys *ws,
  * DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
  * placements even with a low amount of stolen VRAM.
  */
 if (!ws->info.has_dedicated_vram && ws->info.drm_minor < 6)
request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
  
 if (flags & RADEON_FLAG_NO_CPU_ACCESS)

request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 if (flags & RADEON_FLAG_GTT_WC)
request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-   if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
+   /* TODO: Enable this once the kernel handles it efficiently. */
+   /*if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
 ws->info.drm_minor >= 20)
-  request.flags |= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID;
+  request.flags |= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID;*/
  
 r = amdgpu_bo_alloc(ws->dev, &request, &buf_handle);

 if (r) {
fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
fprintf(stderr, "amdgpu:size  : %"PRIu64" bytes\n", size);
fprintf(stderr, "amdgpu:alignment : %u bytes\n", alignment);
fprintf(stderr, "amdgpu:domains   : %u\n", initial_domain);
goto error_bo_alloc;
 }
  




--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/8] spirv: Add a prepass to set types on vtn_values

[Ian Romanick]

On 12/07/2017 08:12 AM, Jason Ekstrand wrote:
> This autogenerated pass will automatically find and set the type field
> on all vtn_values.  This way we always have the type and can use it for
> validation and other checks.
> ---
>  src/compiler/Makefile.nir.am |   4 +
>  src/compiler/nir/meson.build |  11 ++-
>  src/compiler/spirv/spirv_to_nir.c|   6 +-
>  src/compiler/spirv/vtn_gather_types_c.py | 125 
> +++
>  src/compiler/spirv/vtn_private.h |   4 +
>  5 files changed, 148 insertions(+), 2 deletions(-)
>  create mode 100644 src/compiler/spirv/vtn_gather_types_c.py
> 
> diff --git a/src/compiler/Makefile.nir.am b/src/compiler/Makefile.nir.am
> index 1533ee5..dd38c45 100644
> --- a/src/compiler/Makefile.nir.am
> +++ b/src/compiler/Makefile.nir.am
> @@ -56,6 +56,10 @@ spirv/spirv_info.c: spirv/spirv_info_c.py 
> spirv/spirv.core.grammar.json
>   $(MKDIR_GEN)
>   $(PYTHON_GEN) $(srcdir)/spirv/spirv_info_c.py 
> $(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false)
>  
> +spirv/vtn_gather_types.c: spirv/vtn_gather_types_c.py 
> spirv/spirv.core.grammar.json
> + $(MKDIR_GEN)
> + $(PYTHON_GEN) $(srcdir)/spirv/vtn_gather_types_c.py 
> $(srcdir)/spirv/spirv.core.grammar.json $@ || ($(RM) $@; false)
> +
>  noinst_PROGRAMS += spirv2nir
>  
>  spirv2nir_SOURCES = \
> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> index b61a077..5dd21e6 100644
> --- a/src/compiler/nir/meson.build
> +++ b/src/compiler/nir/meson.build
> @@ -72,6 +72,14 @@ spirv_info_c = custom_target(
>command : [prog_python2, '@INPUT0@', '@INPUT1@', '@OUTPUT@'],
>  )
>  
> +vtn_gather_types_c = custom_target(
> +  'vtn_gather_types.c',
> +  input : files('../spirv/vtn_gather_types_c.py',
> +'../spirv/spirv.core.grammar.json'),
> +  output : 'vtn_gather_types.c',
> +  command : [prog_python2, '@INPUT0@', '@INPUT1@', '@OUTPUT@'],
> +)
> +
>  files_libnir = files(
>'nir.c',
>'nir.h',
> @@ -189,7 +197,8 @@ files_libnir = files(
>  libnir = static_library(
>'nir',
>[files_libnir, spirv_info_c, nir_opt_algebraic_c, nir_opcodes_c,
> -   nir_opcodes_h, nir_constant_expressions_c, nir_builder_opcodes_h],
> +   nir_opcodes_h, nir_constant_expressions_c, nir_builder_opcodes_h,
> +   vtn_gather_types_c],
>include_directories : [inc_common, inc_compiler, 
> include_directories('../spirv')],
>c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
>link_with : libcompiler,
> diff --git a/src/compiler/spirv/spirv_to_nir.c 
> b/src/compiler/spirv/spirv_to_nir.c
> index a50b14d..a2426bc 100644
> --- a/src/compiler/spirv/spirv_to_nir.c
> +++ b/src/compiler/spirv/spirv_to_nir.c
> @@ -1261,7 +1261,6 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
>  const uint32_t *w, unsigned count)
>  {
> struct vtn_value *val = vtn_push_value(b, w[2], vtn_value_type_constant);
> -   val->type = vtn_value(b, w[1], vtn_value_type_type)->type;
> val->constant = rzalloc(b, nir_constant);
> switch (opcode) {
> case SpvOpConstantTrue:
> @@ -3268,6 +3267,8 @@ static bool
>  vtn_handle_variable_or_type_instruction(struct vtn_builder *b, SpvOp opcode,
>  const uint32_t *w, unsigned count)
>  {
> +   vtn_set_instruction_result_type(b, opcode, w, count);
> +
> switch (opcode) {
> case SpvOpSource:
> case SpvOpSourceContinued:
> @@ -3658,6 +3659,9 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
> words = vtn_foreach_instruction(b, words, word_end,
> vtn_handle_variable_or_type_instruction);
>  
> +   /* Set types on all vtn_values */
> +   vtn_foreach_instruction(b, words, word_end, 
> vtn_set_instruction_result_type);
> +
> vtn_build_cfg(b, words, word_end);
>  
> assert(b->entry_point->value_type == vtn_value_type_function);
> diff --git a/src/compiler/spirv/vtn_gather_types_c.py 
> b/src/compiler/spirv/vtn_gather_types_c.py
> new file mode 100644
> index 000..8cd8d9f
> --- /dev/null
> +++ b/src/compiler/spirv/vtn_gather_types_c.py
> @@ -0,0 +1,125 @@
> +COPYRIGHT = """\
> +/*
> + * Copyright (C) 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IM

Re: [Mesa-dev] [PATCH] cso: add point rasterization sanity check assertion

[Nicolai Hähnle]

On 11.12.2017 18:42, Brian Paul wrote:

---
  src/gallium/auxiliary/cso_cache/cso_context.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c 
b/src/gallium/auxiliary/cso_cache/cso_context.c
index df5543c..dd9821e 100644
--- a/src/gallium/auxiliary/cso_cache/cso_context.c
+++ b/src/gallium/auxiliary/cso_cache/cso_context.c
@@ -592,6 +592,11 @@ enum pipe_error cso_set_rasterizer(struct cso_context *ctx,
 (void*)templ, 
key_size);
 void *handle = NULL;
  
+   /* We can't have both point_quad_rasterization (sprites) and point_smooth

+* (round AA points) enabled at the same time.
+*/
+   assert(!(templ->point_quad_rasterization && templ->point_smooth));
+
 if (cso_hash_iter_is_null(iter)) {
struct cso_rasterizer *cso = MALLOC(sizeof(struct cso_rasterizer));
if (!cso)



Sure, why not.

Reviewed-by: Nicolai Hähnle 


--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [Mesa-stable] [PATCH] xlib: call _mesa_warning() instead of fprintf()

[Ian Romanick]

Reviewed-by: Ian Romanick 

On 12/11/2017 09:42 AM, Brian Paul wrote:
> We use _mesa_warning() everywhere else in this code.  Change requested
> by Rick Irons of Mathworks.
> 
> CC: 
> ---
>  src/mesa/drivers/x11/fakeglx.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/x11/fakeglx.c b/src/mesa/drivers/x11/fakeglx.c
> index 22d878e..42c4826 100644
> --- a/src/mesa/drivers/x11/fakeglx.c
> +++ b/src/mesa/drivers/x11/fakeglx.c
> @@ -2804,7 +2804,8 @@ Fake_glXCreateContextAttribs(Display *dpy, GLXFBConfig 
> config,
>   profileFlags = attrib_list[i + 1];
>   break;
>default:
> - fprintf(stderr, "Bad attribute in glXCreateContextAttribs()\n");
> + _mesa_warning(NULL, "Unexpected attribute 0x%x in "
> +   "glXCreateContextAttribs()\n", attrib_list[i]);
>   return 0;
>}
> }
> 

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 104214] Dota crashes when switching from game to desktop

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104214

--- Comment #4 from Sven  ---
Yes, I can reproduce the issue with steam overlay disabled.

I will have to try gdb some other day when I have some more time.

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] cso: add point rasterization sanity check assertion

[Brian Paul]

---
 src/gallium/auxiliary/cso_cache/cso_context.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c 
b/src/gallium/auxiliary/cso_cache/cso_context.c
index df5543c..dd9821e 100644
--- a/src/gallium/auxiliary/cso_cache/cso_context.c
+++ b/src/gallium/auxiliary/cso_cache/cso_context.c
@@ -592,6 +592,11 @@ enum pipe_error cso_set_rasterizer(struct cso_context *ctx,
(void*)templ, key_size);
void *handle = NULL;
 
+   /* We can't have both point_quad_rasterization (sprites) and point_smooth
+* (round AA points) enabled at the same time.
+*/
+   assert(!(templ->point_quad_rasterization && templ->point_smooth));
+
if (cso_hash_iter_is_null(iter)) {
   struct cso_rasterizer *cso = MALLOC(sizeof(struct cso_rasterizer));
   if (!cso)
-- 
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] xlib: call _mesa_warning() instead of fprintf()

[Brian Paul]

We use _mesa_warning() everywhere else in this code.  Change requested
by Rick Irons of Mathworks.

CC: 
---
 src/mesa/drivers/x11/fakeglx.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/x11/fakeglx.c b/src/mesa/drivers/x11/fakeglx.c
index 22d878e..42c4826 100644
--- a/src/mesa/drivers/x11/fakeglx.c
+++ b/src/mesa/drivers/x11/fakeglx.c
@@ -2804,7 +2804,8 @@ Fake_glXCreateContextAttribs(Display *dpy, GLXFBConfig 
config,
  profileFlags = attrib_list[i + 1];
  break;
   default:
- fprintf(stderr, "Bad attribute in glXCreateContextAttribs()\n");
+ _mesa_warning(NULL, "Unexpected attribute 0x%x in "
+   "glXCreateContextAttribs()\n", attrib_list[i]);
  return 0;
   }
}
-- 
1.9.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 11/20] mesa: reduce the size of gl_vertex_array_object

[Marek Olšák]

On Wed, Nov 22, 2017 at 11:10 PM, Ian Romanick  wrote:
> On 11/21/2017 10:01 AM, Marek Olšák wrote:
>> From: Marek Olšák 
>>
>> RelativeOffset should actually be uint, not intptr,
>> according to ARB_vertex_attrib_binding.
>>
>> gl_vertex_array_object: 3632 -> 3112 bytes
>> ---
>>  src/mesa/main/mtypes.h | 17 -
>>  1 file changed, 8 insertions(+), 9 deletions(-)
>>
>> diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
>> index 6ddef05..773fa57 100644
>> --- a/src/mesa/main/mtypes.h
>> +++ b/src/mesa/main/mtypes.h
>> @@ -1492,32 +1492,33 @@ struct gl_vertex_array
>>   *
>>   * Note that the Stride field corresponds to VERTEX_ATTRIB_ARRAY_STRIDE
>>   * and is only present for backwards compatibility reasons.
>>   * Rendering always uses VERTEX_BINDING_STRIDE.
>>   * The gl*Pointer() functions will set VERTEX_ATTRIB_ARRAY_STRIDE
>>   * and VERTEX_BINDING_STRIDE to the same value, while
>>   * glBindVertexBuffer() will only set VERTEX_BINDING_STRIDE.
>>   */
>>  struct gl_array_attributes
>>  {
>> -   GLint Size;  /**< Components per element (1,2,3,4) */
>> +   GLuint RelativeOffset; /**< Offset of the first element relative to the 
>> binding offset */
> ^
> More spaces before the comment.
>
>> GLenum16 Type;   /**< Datatype: GL_FLOAT, GL_INT, etc */
>> GLenum16 Format; /**< Default: GL_RGBA, but may be GL_BGRA */
>> -   GLsizei Stride;  /**< Stride as specified with gl*Pointer() */
>> -   const GLubyte *Ptr;  /**< Points to client array data. Not used when 
>> a VBO is bound */
>> -   GLintptr RelativeOffset; /**< Offset of the first element relative to 
>> the binding offset */
>> +   GLshort Stride;  /**< Stride as specified with gl*Pointer() */
>> +   GLubyte Size;/**< Components per element (1,2,3,4) */
>> GLboolean Enabled;   /**< Whether the array is enabled */
>> GLboolean Normalized;/**< Fixed-point values are normalized when 
>> converted to floats */
>> GLboolean Integer;   /**< Fixed-point values are not converted to 
>> floats */
>> GLboolean Doubles;   /**< double precision values are not converted 
>> to floats */
>> GLuint _ElementSize; /**< Size of each element in bytes */
>> GLuint BufferBindingIndex;/**< Vertex buffer binding */
>
> Do these two fields need to be 32-bits?

No. I'll change them to GLubyte.

Marek
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev