[Mesa-dev] [PATCH] i965/fs: Reset the register file to VGRF in lower_integer_multiplication

2017-12-15 Thread Jason Ekstrand 
18fde36ced4279f2577097a1a7d31b55f2f5f141 changed the way temporary
registers were allocated in lower_integer_multiplication so that we
allocate regs_written(inst) space and keep the stride of the original
destination register.  This was to ensure that any MUL which originally
followed the CHV/BXT integer multiply regioning restrictions would
continue to follow those restrictions even after lowering.  This works
fine except that I forgot to reset the register file to VGRF so, even
though they were assigned a number from alloc.allocate(), they had the
wrong register file.  This caused some GLES 3.0 CTS tests to start
failing on Sandy Bridge due to attempted reads from the MRF:

ES3-CTS.functional.shaders.precision.int.highp_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.int.mediump_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.int.lowp_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.uint.highp_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.uint.mediump_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.uint.lowp_mul_fragment.snbm64

This commit remedies this problem by, instead of copying inst->dst and
overwriting nr, just make a new register and set the region to match
inst->dst.

Cc: Matt Turner 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103626
Fixes: 18fde36ced4279f2577097a1a7d31b55f2f5f141
Cc: "17.3" 
---
 src/intel/compiler/brw_fs.cpp | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 3717c50..db5468c 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3631,13 +3631,18 @@ fs_visitor::lower_integer_multiplication()
 regions_overlap(inst->dst, inst->size_written,
 inst->src[1], inst->size_read(1))) {
needs_mov = true;
-   low.nr = alloc.allocate(regs_written(inst));
-   low.offset = low.offset % REG_SIZE;
+   /* Get a new VGRF but keep the same stride as inst->dst */
+   low = fs_reg(VGRF, alloc.allocate(regs_written(inst)),
+inst->dst.type);
+   low.stride = inst->dst.stride;
+   low.offset = inst->dst.offset % REG_SIZE;
 }
 
-fs_reg high = inst->dst;
-high.nr = alloc.allocate(regs_written(inst));
-high.offset = high.offset % REG_SIZE;
+/* Get a new VGRF but keep the same stride as inst->dst */
+fs_reg high(VGRF, alloc.allocate(regs_written(inst)),
+inst->dst.type);
+high.stride = inst->dst.stride;
+high.offset = inst->dst.offset % REG_SIZE;
 
 if (devinfo->gen >= 7) {
if (inst->src[1].file == IMM) {
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 17/17] anv/cmd_buffer: Move gen7 index buffer state to graphics state

2017-12-15 Thread Jason Ekstrand 
---
 src/intel/vulkan/anv_private.h | 12 ++--
 src/intel/vulkan/gen7_cmd_buffer.c | 14 +++---
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 70c83d9..57b0051 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1709,6 +1709,12 @@ struct anv_cmd_graphics_state {
uint32_t vb_dirty;
 
struct anv_dynamic_state dynamic;
+
+   struct {
+  struct anv_buffer *index_buffer;
+  uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
+  uint32_t index_offset;
+   } gen7;
 };
 
 /** State tracking for compute pipeline
@@ -1782,12 +1788,6 @@ struct anv_cmd_state {
 * is one of the states in render_pass_states.
 */
struct anv_state null_surface_state;
-
-   struct {
-  struct anv_buffer *   index_buffer;
-  uint32_t  index_type; /**< 
3DSTATE_INDEX_BUFFER.IndexFormat */
-  uint32_t  index_offset;
-   } gen7;
 };
 
 struct anv_cmd_pool {
diff --git a/src/intel/vulkan/gen7_cmd_buffer.c 
b/src/intel/vulkan/gen7_cmd_buffer.c
index db96c4f..cbeb838 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -116,9 +116,9 @@ void genX(CmdBindIndexBuffer)(
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
if (GEN_IS_HASWELL)
   cmd_buffer->state.restart_index = restart_index_for_type[indexType];
-   cmd_buffer->state.gen7.index_buffer = buffer;
-   cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
-   cmd_buffer->state.gen7.index_offset = offset;
+   cmd_buffer->state.gfx.gen7.index_buffer = buffer;
+   cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type[indexType];
+   cmd_buffer->state.gfx.gen7.index_offset = offset;
 }
 
 static uint32_t
@@ -227,11 +227,11 @@ genX(cmd_buffer_flush_dynamic_state)(struct 
anv_cmd_buffer *cmd_buffer)
   }
}
 
-   if (cmd_buffer->state.gen7.index_buffer &&
+   if (cmd_buffer->state.gfx.gen7.index_buffer &&
cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
   ANV_CMD_DIRTY_INDEX_BUFFER)) {
-  struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
-  uint32_t offset = cmd_buffer->state.gen7.index_offset;
+  struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer;
+  uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset;
 
 #if GEN_IS_HASWELL
   anv_batch_emit(_buffer->batch, GEN75_3DSTATE_VF, vf) {
@@ -244,7 +244,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer 
*cmd_buffer)
 #if !GEN_IS_HASWELL
  ib.CutIndexEnable = pipeline->primitive_restart;
 #endif
- ib.IndexFormat= cmd_buffer->state.gen7.index_type;
+ ib.IndexFormat= cmd_buffer->state.gfx.gen7.index_type;
  ib.MemoryObjectControlState   = GENX(MOCS);
 
  ib.BufferStartingAddress =
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 16/17] anv/cmd_buffer: Move num_workgroups to compute state

2017-12-15 Thread Jason Ekstrand 
While we're here, make it an anv_address.
---
 src/intel/vulkan/anv_private.h |  4 ++--
 src/intel/vulkan/genX_cmd_buffer.c | 17 ++---
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 5ceec6b..70c83d9 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1722,6 +1722,8 @@ struct anv_cmd_compute_state {
struct anv_cmd_pipeline_state base;
 
bool pipeline_dirty;
+
+   struct anv_address num_workgroups;
 };
 
 /** State required while building cmd buffer */
@@ -1734,8 +1736,6 @@ struct anv_cmd_state {
struct anv_cmd_compute_state compute;
 
enum anv_pipe_bits   pending_pipe_bits;
-   uint32_t num_workgroups_offset;
-   struct anv_bo*num_workgroups_bo;
VkShaderStageFlags   descriptors_dirty;
VkShaderStageFlags   push_constants_dirty;
 
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index a94c565..dea0248 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1505,8 +1505,8 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
 
if (stage == MESA_SHADER_COMPUTE &&
get_cs_prog_data(pipeline)->uses_num_work_groups) {
-  struct anv_bo *bo = cmd_buffer->state.num_workgroups_bo;
-  uint32_t bo_offset = cmd_buffer->state.num_workgroups_offset;
+  struct anv_bo *bo = cmd_buffer->state.compute.num_workgroups.bo;
+  uint32_t bo_offset = cmd_buffer->state.compute.num_workgroups.offset;
 
   struct anv_state surface_state;
   surface_state =
@@ -2594,9 +2594,10 @@ void genX(CmdDispatch)(
   sizes[1] = y;
   sizes[2] = z;
   anv_state_flush(cmd_buffer->device, state);
-  cmd_buffer->state.num_workgroups_offset = state.offset;
-  cmd_buffer->state.num_workgroups_bo =
- _buffer->device->dynamic_state_pool.block_pool.bo;
+  cmd_buffer->state.compute.num_workgroups = (struct anv_address) {
+ .bo = _buffer->device->dynamic_state_pool.block_pool.bo,
+ .offset = state.offset,
+  };
}
 
genX(cmd_buffer_flush_compute_state)(cmd_buffer);
@@ -2643,8 +2644,10 @@ void genX(CmdDispatchIndirect)(
 #endif
 
if (prog_data->uses_num_work_groups) {
-  cmd_buffer->state.num_workgroups_offset = bo_offset;
-  cmd_buffer->state.num_workgroups_bo = bo;
+  cmd_buffer->state.compute.num_workgroups = (struct anv_address) {
+ .bo = bo,
+ .offset = bo_offset,
+  };
}
 
genX(cmd_buffer_flush_compute_state)(cmd_buffer);
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 14/17] anv/cmd_buffer: Use a temporary variable for dynamic state

2017-12-15 Thread Jason Ekstrand 
We were already doing this for some packets to keep the lines shorter.
We may as well just do it for all of them.
---
 src/intel/vulkan/gen7_cmd_buffer.c | 19 +--
 src/intel/vulkan/gen8_cmd_buffer.c | 32 +++-
 2 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/src/intel/vulkan/gen7_cmd_buffer.c 
b/src/intel/vulkan/gen7_cmd_buffer.c
index f16056a..6571b07 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -155,6 +155,7 @@ void
 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 {
struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
+   struct anv_dynamic_state *d = _buffer->state.dynamic;
 
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
   ANV_CMD_DIRTY_RENDER_TARGETS |
@@ -164,10 +165,10 @@ genX(cmd_buffer_flush_dynamic_state)(struct 
anv_cmd_buffer *cmd_buffer)
   struct GENX(3DSTATE_SF) sf = {
  GENX(3DSTATE_SF_header),
  .DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
- .LineWidth = cmd_buffer->state.dynamic.line_width,
- .GlobalDepthOffsetConstant = 
cmd_buffer->state.dynamic.depth_bias.bias,
- .GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
- .GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
+ .LineWidth = d->line_width,
+ .GlobalDepthOffsetConstant = d->depth_bias.bias,
+ .GlobalDepthOffsetScale = d->depth_bias.slope,
+ .GlobalDepthOffsetClamp = d->depth_bias.clamp
   };
   GENX(3DSTATE_SF_pack)(NULL, sf_dw, );
 
@@ -176,16 +177,15 @@ genX(cmd_buffer_flush_dynamic_state)(struct 
anv_cmd_buffer *cmd_buffer)
 
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
   
ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
-  struct anv_dynamic_state *d = _buffer->state.dynamic;
   struct anv_state cc_state =
  anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
 GENX(COLOR_CALC_STATE_length) * 4,
 64);
   struct GENX(COLOR_CALC_STATE) cc = {
- .BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
- .BlendConstantColorGreen = 
cmd_buffer->state.dynamic.blend_constants[1],
- .BlendConstantColorBlue = 
cmd_buffer->state.dynamic.blend_constants[2],
- .BlendConstantColorAlpha = 
cmd_buffer->state.dynamic.blend_constants[3],
+ .BlendConstantColorRed = d->blend_constants[0],
+ .BlendConstantColorGreen = d->blend_constants[1],
+ .BlendConstantColorBlue = d->blend_constants[2],
+ .BlendConstantColorAlpha = d->blend_constants[3],
  .StencilReferenceValue = d->stencil_reference.front & 0xff,
  .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
   };
@@ -202,7 +202,6 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer 
*cmd_buffer)
   
ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
   
ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
   uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
-  struct anv_dynamic_state *d = _buffer->state.dynamic;
 
   struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
  .StencilTestMask = d->stencil_compare_mask.front & 0xff,
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c 
b/src/intel/vulkan/gen8_cmd_buffer.c
index b0a44ef..d939d03 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -382,6 +382,7 @@ void
 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
 {
struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
+   struct anv_dynamic_state *d = _buffer->state.dynamic;
 
if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
   ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)) {
@@ -391,12 +392,12 @@ genX(cmd_buffer_flush_dynamic_state)(struct 
anv_cmd_buffer *cmd_buffer)
   };
 #if GEN_GEN == 8
   if (cmd_buffer->device->info.is_cherryview) {
- sf.CHVLineWidth = cmd_buffer->state.dynamic.line_width;
+ sf.CHVLineWidth = d->line_width;
   } else {
- sf.LineWidth = cmd_buffer->state.dynamic.line_width;
+ sf.LineWidth = d->line_width;
   }
 #else
-  sf.LineWidth = cmd_buffer->state.dynamic.line_width,
+  sf.LineWidth = d->line_width,
 #endif
   GENX(3DSTATE_SF_pack)(NULL, sf_dw, );
   anv_batch_emit_merge(_buffer->batch, sf_dw, pipeline->gen8.sf);
@@ -407,9 +408,9 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer 
*cmd_buffer)
   uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
   struct GENX(3DSTATE_RASTER) raster = {
  GENX(3DSTATE_RASTER_header),
- .GlobalDepthOffsetConstant =

[Mesa-dev] [PATCH 15/17] anv/cmd_buffer: Move dynamic state to graphics state

2017-12-15 Thread Jason Ekstrand 
---
 src/intel/vulkan/anv_cmd_buffer.c  | 42 +++---
 src/intel/vulkan/anv_private.h |  3 ++-
 src/intel/vulkan/gen7_cmd_buffer.c |  6 +++---
 src/intel/vulkan/gen8_cmd_buffer.c | 12 ++-
 4 files changed, 33 insertions(+), 30 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index dd6fb9d..bf80061 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -120,7 +120,7 @@ anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
memset(state, 0, sizeof(*state));
 
state->restart_index = UINT32_MAX;
-   state->dynamic = default_dynamic_state;
+   state->gfx.dynamic = default_dynamic_state;
 }
 
 static void
@@ -359,7 +359,7 @@ void anv_CmdBindPipeline(
 
   /* Apply the dynamic state from the pipeline */
   cmd_buffer->state.gfx.dirty |= pipeline->dynamic_state_mask;
-  anv_dynamic_state_copy(_buffer->state.dynamic,
+  anv_dynamic_state_copy(_buffer->state.gfx.dynamic,
  >dynamic_state,
  pipeline->dynamic_state_mask);
   break;
@@ -379,10 +379,10 @@ void anv_CmdSetViewport(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 
const uint32_t total_count = firstViewport + viewportCount;
-   if (cmd_buffer->state.dynamic.viewport.count < total_count)
-  cmd_buffer->state.dynamic.viewport.count = total_count;
+   if (cmd_buffer->state.gfx.dynamic.viewport.count < total_count)
+  cmd_buffer->state.gfx.dynamic.viewport.count = total_count;
 
-   memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
+   memcpy(cmd_buffer->state.gfx.dynamic.viewport.viewports + firstViewport,
   pViewports, viewportCount * sizeof(*pViewports));
 
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
@@ -397,10 +397,10 @@ void anv_CmdSetScissor(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 
const uint32_t total_count = firstScissor + scissorCount;
-   if (cmd_buffer->state.dynamic.scissor.count < total_count)
-  cmd_buffer->state.dynamic.scissor.count = total_count;
+   if (cmd_buffer->state.gfx.dynamic.scissor.count < total_count)
+  cmd_buffer->state.gfx.dynamic.scissor.count = total_count;
 
-   memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
+   memcpy(cmd_buffer->state.gfx.dynamic.scissor.scissors + firstScissor,
   pScissors, scissorCount * sizeof(*pScissors));
 
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
@@ -412,7 +412,7 @@ void anv_CmdSetLineWidth(
 {
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 
-   cmd_buffer->state.dynamic.line_width = lineWidth;
+   cmd_buffer->state.gfx.dynamic.line_width = lineWidth;
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
 }
 
@@ -424,9 +424,9 @@ void anv_CmdSetDepthBias(
 {
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 
-   cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
-   cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
-   cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
+   cmd_buffer->state.gfx.dynamic.depth_bias.bias = depthBiasConstantFactor;
+   cmd_buffer->state.gfx.dynamic.depth_bias.clamp = depthBiasClamp;
+   cmd_buffer->state.gfx.dynamic.depth_bias.slope = depthBiasSlopeFactor;
 
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
 }
@@ -437,7 +437,7 @@ void anv_CmdSetBlendConstants(
 {
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 
-   memcpy(cmd_buffer->state.dynamic.blend_constants,
+   memcpy(cmd_buffer->state.gfx.dynamic.blend_constants,
   blendConstants, sizeof(float) * 4);
 
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
@@ -450,8 +450,8 @@ void anv_CmdSetDepthBounds(
 {
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 
-   cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
-   cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
+   cmd_buffer->state.gfx.dynamic.depth_bounds.min = minDepthBounds;
+   cmd_buffer->state.gfx.dynamic.depth_bounds.max = maxDepthBounds;
 
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
 }
@@ -464,9 +464,9 @@ void anv_CmdSetStencilCompareMask(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 
if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
-  cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
+  cmd_buffer->state.gfx.dynamic.stencil_compare_mask.front = compareMask;
if (faceMask & VK_STENCIL_FACE_BACK_BIT)
-  cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
+  cmd_buffer->state.gfx.dynamic.stencil_compare_mask.back = compareMask;
 
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
 }
@@ -479,9 +479,9 @@ void anv_CmdSetStencilWriteMask(
ANV_FROM_HANDLE(anv_cmd_buffer,

[Mesa-dev] [PATCH 01/17] anv/pipeline: Don't assert on more than 32 samplers

2017-12-15 Thread Jason Ekstrand 
This prevents an assert when running one unreleased Vulkan game.
---
 src/intel/vulkan/genX_pipeline.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 0ae9ead..b6a537b 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1081,7 +1081,13 @@ emit_3dstate_streamout(struct anv_pipeline *pipeline,
 static uint32_t
 get_sampler_count(const struct anv_shader_bin *bin)
 {
-   return DIV_ROUND_UP(bin->bind_map.sampler_count, 4);
+   uint32_t count_by_4 = DIV_ROUND_UP(bin->bind_map.sampler_count, 4);
+
+   /* We can potentially have way more than 32 samplers and that's ok.
+* However, the 3DSTATE_XS packets only have 3 bits to specify how
+* many to pre-fetch and all values above 4 are marked reserved.
+*/
+   return MIN2(count_by_4, 4);
 }
 
 static uint32_t
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 02/17] anv/cmd_state: Drop the scratch_size field

2017-12-15 Thread Jason Ekstrand 
This is a legacy left-over from the mechanism we used to use to handle
scratch.  The new (and better) mechanism doesn't use this.
---
 src/intel/vulkan/anv_private.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index b7bde4b..2d35aaa 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1689,7 +1689,6 @@ struct anv_cmd_state {
struct anv_bo*num_workgroups_bo;
VkShaderStageFlags   descriptors_dirty;
VkShaderStageFlags   push_constants_dirty;
-   uint32_t scratch_size;
struct anv_pipeline *pipeline;
struct anv_pipeline *compute_pipeline;
struct anv_framebuffer * framebuffer;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 00/17] anv: Rework state tracking to better separate

2017-12-15 Thread Jason Ekstrand 
This series is intended to address a bug filed in September:

https://bugs.freedesktop.org/show_bug.cgi?id=102897

Unfortunately, the fix is either a lot of patches or very messy.  This
series (as is common for me) takes the lots of patches approach.  The
general idea is to break out a large chunk of anv_cmd_state into sub-
structs for graphics and compute.  This way, it's very clear when you're
accessing any bit of state that you're pulling from one or the other.  By
giving these a base struct, we can also make clear that a certain set of
states are are per-pipeline-bind-point.  In order to reduce churn in the
patches which actually move state from one struct to another, there are
several patches which just make us make better use of helper functions and
temporary variables.

Jason Ekstrand (17):
  anv/pipeline: Don't assert on more than 32 samplers
  anv/cmd_state: Drop the scratch_size field
  anv/cmd_buffer: Get rid of the meta query workaround
  anv/cmd_buffer: Rework anv_cmd_state_reset
  anv/cmd_buffer: Use some pre-existing pipeline temporaries
  anv/cmd_buffer: Add substructs to anv_cmd_state for graphics and
compute
  anv: Remove semicolons from vk_error[f] definitions
  anv/cmd_buffer: Refactor ensure_push_descriptor_set
  anv/cmd_buffer: Add a helper for binding descriptor sets
  anv/cmd_buffer: Use anv_descriptor_for_binding for samplers
  anv: Separate compute and graphics descriptor sets
  anv/cmd_buffer: Move dirty bits into anv_cmd_*_state
  anv/cmd_buffer: Move vb_dirty bits into anv_cmd_graphics_state
  anv/cmd_buffer: Use a temporary variable for dynamic state
  anv/cmd_buffer: Move dynamic state to graphics state
  anv/cmd_buffer: Move num_workgroups to compute state
  anv/cmd_buffer: Move gen7 index buffer state to graphics state

 src/intel/vulkan/anv_cmd_buffer.c | 274 +++---
 src/intel/vulkan/anv_descriptor_set.c |   2 +
 src/intel/vulkan/anv_private.h|  85 ---
 src/intel/vulkan/gen7_cmd_buffer.c|  67 -
 src/intel/vulkan/gen8_cmd_buffer.c|  91 ++-
 src/intel/vulkan/genX_blorp_exec.c|   4 +-
 src/intel/vulkan/genX_cmd_buffer.c| 121 ---
 src/intel/vulkan/genX_gpu_memcpy.c|   2 +-
 src/intel/vulkan/genX_pipeline.c  |   8 +-
 src/intel/vulkan/genX_query.c |  14 --
 10 files changed, 369 insertions(+), 299 deletions(-)

-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 12/17] anv/cmd_buffer: Move dirty bits into anv_cmd_*_state

2017-12-15 Thread Jason Ekstrand 
---
 src/intel/vulkan/anv_cmd_buffer.c  | 24 +++
 src/intel/vulkan/anv_private.h |  6 --
 src/intel/vulkan/gen7_cmd_buffer.c | 28 +-
 src/intel/vulkan/gen8_cmd_buffer.c | 40 +++---
 src/intel/vulkan/genX_blorp_exec.c |  2 +-
 src/intel/vulkan/genX_cmd_buffer.c | 20 +--
 src/intel/vulkan/genX_gpu_memcpy.c |  2 +-
 7 files changed, 62 insertions(+), 60 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 9720e7e..ad5baee 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -345,7 +345,7 @@ void anv_CmdBindPipeline(
switch (pipelineBindPoint) {
case VK_PIPELINE_BIND_POINT_COMPUTE:
   cmd_buffer->state.compute.base.pipeline = pipeline;
-  cmd_buffer->state.compute_dirty |= ANV_CMD_DIRTY_PIPELINE;
+  cmd_buffer->state.compute.pipeline_dirty = true;
   cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
   cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
   break;
@@ -353,12 +353,12 @@ void anv_CmdBindPipeline(
case VK_PIPELINE_BIND_POINT_GRAPHICS:
   cmd_buffer->state.gfx.base.pipeline = pipeline;
   cmd_buffer->state.vb_dirty |= pipeline->vb_used;
-  cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
+  cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
   cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
   cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
 
   /* Apply the dynamic state from the pipeline */
-  cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
+  cmd_buffer->state.gfx.dirty |= pipeline->dynamic_state_mask;
   anv_dynamic_state_copy(_buffer->state.dynamic,
  >dynamic_state,
  pipeline->dynamic_state_mask);
@@ -385,7 +385,7 @@ void anv_CmdSetViewport(
memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
   pViewports, viewportCount * sizeof(*pViewports));
 
-   cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
+   cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
 }
 
 void anv_CmdSetScissor(
@@ -403,7 +403,7 @@ void anv_CmdSetScissor(
memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
   pScissors, scissorCount * sizeof(*pScissors));
 
-   cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
+   cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
 }
 
 void anv_CmdSetLineWidth(
@@ -413,7 +413,7 @@ void anv_CmdSetLineWidth(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
 
cmd_buffer->state.dynamic.line_width = lineWidth;
-   cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
+   cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
 }
 
 void anv_CmdSetDepthBias(
@@ -428,7 +428,7 @@ void anv_CmdSetDepthBias(
cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
 
-   cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
+   cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
 }
 
 void anv_CmdSetBlendConstants(
@@ -440,7 +440,7 @@ void anv_CmdSetBlendConstants(
memcpy(cmd_buffer->state.dynamic.blend_constants,
   blendConstants, sizeof(float) * 4);
 
-   cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
+   cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
 }
 
 void anv_CmdSetDepthBounds(
@@ -453,7 +453,7 @@ void anv_CmdSetDepthBounds(
cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
 
-   cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
+   cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
 }
 
 void anv_CmdSetStencilCompareMask(
@@ -468,7 +468,7 @@ void anv_CmdSetStencilCompareMask(
if (faceMask & VK_STENCIL_FACE_BACK_BIT)
   cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
 
-   cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
+   cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
 }
 
 void anv_CmdSetStencilWriteMask(
@@ -483,7 +483,7 @@ void anv_CmdSetStencilWriteMask(
if (faceMask & VK_STENCIL_FACE_BACK_BIT)
   cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
 
-   cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
+   cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
 }
 
 void anv_CmdSetStencilReference(
@@ -498,7 +498,7 @@ void anv_CmdSetStencilReference(
if (faceMask & VK_STENCIL_FACE_BACK_BIT)
   cmd_buffer->state.dynamic.stencil_reference.back = reference;
 
-   cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
+   cmd_buffer->state.gfx.dirty

[Mesa-dev] [PATCH 06/17] anv/cmd_buffer: Add substructs to anv_cmd_state for graphics and compute

2017-12-15 Thread Jason Ekstrand 
Initially, these just contain the pipeline in a base struct.
---
 src/intel/vulkan/anv_cmd_buffer.c  | 12 +-
 src/intel/vulkan/anv_private.h | 41 --
 src/intel/vulkan/gen7_cmd_buffer.c |  2 +-
 src/intel/vulkan/gen8_cmd_buffer.c |  6 ++---
 src/intel/vulkan/genX_cmd_buffer.c | 45 --
 5 files changed, 74 insertions(+), 32 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 5436d54..dd50563 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -336,14 +336,14 @@ void anv_CmdBindPipeline(
 
switch (pipelineBindPoint) {
case VK_PIPELINE_BIND_POINT_COMPUTE:
-  cmd_buffer->state.compute_pipeline = pipeline;
+  cmd_buffer->state.compute.base.pipeline = pipeline;
   cmd_buffer->state.compute_dirty |= ANV_CMD_DIRTY_PIPELINE;
   cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
   cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
   break;
 
case VK_PIPELINE_BIND_POINT_GRAPHICS:
-  cmd_buffer->state.pipeline = pipeline;
+  cmd_buffer->state.gfx.base.pipeline = pipeline;
   cmd_buffer->state.vb_dirty |= pipeline->vb_used;
   cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
   cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
@@ -636,14 +636,16 @@ struct anv_state
 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
   gl_shader_stage stage)
 {
+   struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
+
/* If we don't have this stage, bail. */
-   if (!anv_pipeline_has_stage(cmd_buffer->state.pipeline, stage))
+   if (!anv_pipeline_has_stage(pipeline, stage))
   return (struct anv_state) { .offset = 0 };
 
struct anv_push_constants *data =
   cmd_buffer->state.push_constants[stage];
const struct brw_stage_prog_data *prog_data =
-  cmd_buffer->state.pipeline->shaders[stage]->prog_data;
+  pipeline->shaders[stage]->prog_data;
 
/* If we don't actually have any push constants, bail. */
if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
@@ -669,7 +671,7 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer 
*cmd_buffer)
 {
struct anv_push_constants *data =
   cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
-   struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
+   struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
const struct brw_stage_prog_data *prog_data = _prog_data->base;
 
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index d6436d5..9860778 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1676,11 +1676,49 @@ struct anv_attachment_state {
bool clear_color_is_zero;
 };
 
+/** State tracking for particular pipeline bind point
+ *
+ * This struct is the base struct for anv_cmd_graphics_state and
+ * anv_cmd_compute_state.  These are used to track state which is bound to a
+ * particular type of pipeline.  Generic state that applies per-stage such as
+ * binding table offsets and push constants is tracked generically with a
+ * per-stage array in anv_cmd_state.
+ */
+struct anv_cmd_pipeline_state {
+   struct anv_pipeline *pipeline;
+};
+
+/** State tracking for graphics pipeline
+ *
+ * This has anv_cmd_pipeline_state as a base struct to track things which get
+ * bound to a graphics pipeline.  Along with general pipeline bind point state
+ * which is in the anv_cmd_pipeline_state base struct, it also contains other
+ * state which is graphics-specific.
+ */
+struct anv_cmd_graphics_state {
+   struct anv_cmd_pipeline_state base;
+};
+
+/** State tracking for compute pipeline
+ *
+ * This has anv_cmd_pipeline_state as a base struct to track things which get
+ * bound to a compute pipeline.  Along with general pipeline bind point state
+ * which is in the anv_cmd_pipeline_state base struct, it also contains other
+ * state which is compute-specific.
+ */
+struct anv_cmd_compute_state {
+   struct anv_cmd_pipeline_state base;
+};
+
 /** State required while building cmd buffer */
 struct anv_cmd_state {
/* PIPELINE_SELECT.PipelineSelection */
uint32_t current_pipeline;
const struct gen_l3_config * current_l3_config;
+
+   struct anv_cmd_graphics_stategfx;
+   struct anv_cmd_compute_state compute;
+
uint32_t vb_dirty;
anv_cmd_dirty_mask_t dirty;
anv_cmd_dirty_mask_t compute_dirty;
@@ -1689,8 +1727,7 @@ struct anv_cmd_state {
struct anv_bo*num_workgroups_bo;

[Mesa-dev] [PATCH 05/17] anv/cmd_buffer: Use some pre-existing pipeline temporaries

2017-12-15 Thread Jason Ekstrand 
There are several places where we'd already saved the pipeline off to a
temporary variable but, due to an artifact of history, weren't actually
using that temporary everywhere.  No functional change.
---
 src/intel/vulkan/gen8_cmd_buffer.c | 3 +--
 src/intel/vulkan/genX_cmd_buffer.c | 9 -
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/intel/vulkan/gen8_cmd_buffer.c 
b/src/intel/vulkan/gen8_cmd_buffer.c
index 751212b..687de41 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -399,8 +399,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer 
*cmd_buffer)
   sf.LineWidth = cmd_buffer->state.dynamic.line_width,
 #endif
   GENX(3DSTATE_SF_pack)(NULL, sf_dw, );
-  anv_batch_emit_merge(_buffer->batch, sf_dw,
-   cmd_buffer->state.pipeline->gen8.sf);
+  anv_batch_emit_merge(_buffer->batch, sf_dw, pipeline->gen8.sf);
}
 
if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 0bd3874..9a5e750 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1501,7 +1501,7 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
   return VK_ERROR_OUT_OF_DEVICE_MEMORY;
 
if (stage == MESA_SHADER_COMPUTE &&
-   
get_cs_prog_data(cmd_buffer->state.compute_pipeline)->uses_num_work_groups) {
+   get_cs_prog_data(pipeline)->uses_num_work_groups) {
   struct anv_bo *bo = cmd_buffer->state.num_workgroups_bo;
   uint32_t bo_offset = cmd_buffer->state.num_workgroups_offset;
 
@@ -1847,7 +1847,7 @@ static void
 cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer,
 VkShaderStageFlags dirty_stages)
 {
-   UNUSED const struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
+   const struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
 
static const uint32_t push_constant_opcodes[] = {
   [MESA_SHADER_VERTEX]  = 21,
@@ -1867,7 +1867,7 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer 
*cmd_buffer,
   anv_batch_emit(_buffer->batch, GENX(3DSTATE_CONSTANT_VS), c) {
  c._3DCommandSubOpcode = push_constant_opcodes[stage];
 
- if (anv_pipeline_has_stage(cmd_buffer->state.pipeline, stage)) {
+ if (anv_pipeline_has_stage(pipeline, stage)) {
 #if GEN_GEN >= 8 || GEN_IS_HASWELL
 const struct brw_stage_prog_data *prog_data =
pipeline->shaders[stage]->prog_data;
@@ -2038,8 +2038,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer 
*cmd_buffer)
   /* The exact descriptor layout is pulled from the pipeline, so we need
* to re-emit binding tables on every pipeline change.
*/
-  cmd_buffer->state.descriptors_dirty |=
- cmd_buffer->state.pipeline->active_stages;
+  cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
 
   /* If the pipeline changed, we may need to re-allocate push constant
* space in the URB.
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 13/17] anv/cmd_buffer: Move vb_dirty bits into anv_cmd_graphics_state

2017-12-15 Thread Jason Ekstrand 
Vertex buffers are entirely a graphics pipeline thing.
---
 src/intel/vulkan/anv_cmd_buffer.c  | 4 ++--
 src/intel/vulkan/anv_private.h | 2 +-
 src/intel/vulkan/genX_blorp_exec.c | 2 +-
 src/intel/vulkan/genX_cmd_buffer.c | 6 +++---
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index ad5baee..dd6fb9d 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -352,7 +352,7 @@ void anv_CmdBindPipeline(
 
case VK_PIPELINE_BIND_POINT_GRAPHICS:
   cmd_buffer->state.gfx.base.pipeline = pipeline;
-  cmd_buffer->state.vb_dirty |= pipeline->vb_used;
+  cmd_buffer->state.gfx.vb_dirty |= pipeline->vb_used;
   cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
   cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
   cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
@@ -590,7 +590,7 @@ void anv_CmdBindVertexBuffers(
for (uint32_t i = 0; i < bindingCount; i++) {
   vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
   vb[firstBinding + i].offset = pOffsets[i];
-  cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
+  cmd_buffer->state.gfx.vb_dirty |= 1 << (firstBinding + i);
}
 }
 
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 413f8d5..2e4e2ff 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1706,6 +1706,7 @@ struct anv_cmd_graphics_state {
struct anv_cmd_pipeline_state base;
 
anv_cmd_dirty_mask_t dirty;
+   uint32_t vb_dirty;
 };
 
 /** State tracking for compute pipeline
@@ -1730,7 +1731,6 @@ struct anv_cmd_state {
struct anv_cmd_graphics_stategfx;
struct anv_cmd_compute_state compute;
 
-   uint32_t vb_dirty;
enum anv_pipe_bits   pending_pipe_bits;
uint32_t num_workgroups_offset;
struct anv_bo*num_workgroups_bo;
diff --git a/src/intel/vulkan/genX_blorp_exec.c 
b/src/intel/vulkan/genX_blorp_exec.c
index 871ade8..04f7675 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -218,7 +218,7 @@ genX(blorp_exec)(struct blorp_batch *batch,
 
blorp_exec(batch, params);
 
-   cmd_buffer->state.vb_dirty = ~0;
+   cmd_buffer->state.gfx.vb_dirty = ~0;
cmd_buffer->state.gfx.dirty = ~0;
cmd_buffer->state.push_constants_dirty = ~0;
 }
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 491ec7b..a94c565 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1982,7 +1982,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer 
*cmd_buffer)
struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
uint32_t *p;
 
-   uint32_t vb_emit = cmd_buffer->state.vb_dirty & pipeline->vb_used;
+   uint32_t vb_emit = cmd_buffer->state.gfx.vb_dirty & pipeline->vb_used;
 
assert((pipeline->active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
 
@@ -2033,7 +2033,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer 
*cmd_buffer)
   }
}
 
-   cmd_buffer->state.vb_dirty &= ~vb_emit;
+   cmd_buffer->state.gfx.vb_dirty &= ~vb_emit;
 
if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) {
   anv_batch_emit_batch(_buffer->batch, >batch);
@@ -3100,7 +3100,7 @@ genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer 
*cmd_buffer,
 * of each subpass.
 */
if (GEN_GEN == 7)
-  cmd_buffer->state.vb_dirty |= ~0;
+  cmd_buffer->state.gfx.vb_dirty |= ~0;
 
/* Perform transitions to the subpass layout before any writes have
 * occurred.
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 10/17] anv/cmd_buffer: Use anv_descriptor_for_binding for samplers

2017-12-15 Thread Jason Ekstrand 
---
 src/intel/vulkan/genX_cmd_buffer.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 9d6f753..994c996 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1723,10 +1723,8 @@ emit_samplers(struct anv_cmd_buffer *cmd_buffer,
 
for (uint32_t s = 0; s < map->sampler_count; s++) {
   struct anv_pipeline_binding *binding = >sampler_to_descriptor[s];
-  struct anv_descriptor_set *set =
- cmd_buffer->state.descriptors[binding->set];
-  uint32_t offset = 
set->layout->binding[binding->binding].descriptor_index;
-  struct anv_descriptor *desc = >descriptors[offset + binding->index];
+  const struct anv_descriptor *desc =
+ anv_descriptor_for_binding(cmd_buffer, binding);
 
   if (desc->type != VK_DESCRIPTOR_TYPE_SAMPLER &&
   desc->type != VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 09/17] anv/cmd_buffer: Add a helper for binding descriptor sets

2017-12-15 Thread Jason Ekstrand 
This lets us unify some code between push descriptors and regular
descriptors.  It doesn't do much for us yet but it will.
---
 src/intel/vulkan/anv_cmd_buffer.c | 70 +++
 1 file changed, 42 insertions(+), 28 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index e5366fd..636f515 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -493,6 +493,40 @@ void anv_CmdSetStencilReference(
cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
 }
 
+static void
+anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
+   struct anv_pipeline_layout *layout,
+   uint32_t set_index,
+   struct anv_descriptor_set *set,
+   uint32_t *dynamic_offset_count,
+   const uint32_t **dynamic_offsets)
+{
+   struct anv_descriptor_set_layout *set_layout =
+  layout->set[set_index].layout;
+
+   cmd_buffer->state.descriptors[set_index] = set;
+
+   if (dynamic_offsets) {
+  if (set_layout->dynamic_offset_count > 0) {
+ uint32_t dynamic_offset_start =
+layout->set[set_index].dynamic_offset_start;
+
+ /* Assert that everything is in range */
+ assert(set_layout->dynamic_offset_count <= *dynamic_offset_count);
+ assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
+ARRAY_SIZE(cmd_buffer->state.dynamic_offsets));
+
+ typed_memcpy(_buffer->state.dynamic_offsets[dynamic_offset_start],
+  *dynamic_offsets, set_layout->dynamic_offset_count);
+
+ *dynamic_offsets += set_layout->dynamic_offset_count;
+ *dynamic_offset_count -= set_layout->dynamic_offset_count;
+  }
+   }
+
+   cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
+}
+
 void anv_CmdBindDescriptorSets(
 VkCommandBuffer commandBuffer,
 VkPipelineBindPoint pipelineBindPoint,
@@ -505,35 +539,15 @@ void anv_CmdBindDescriptorSets(
 {
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
-   struct anv_descriptor_set_layout *set_layout;
 
assert(firstSet + descriptorSetCount < MAX_SETS);
 
-   uint32_t dynamic_slot = 0;
for (uint32_t i = 0; i < descriptorSetCount; i++) {
   ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
-  set_layout = layout->set[firstSet + i].layout;
-
-  cmd_buffer->state.descriptors[firstSet + i] = set;
-
-  if (set_layout->dynamic_offset_count > 0) {
- uint32_t dynamic_offset_start =
-layout->set[firstSet + i].dynamic_offset_start;
-
- /* Assert that everything is in range */
- assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
-ARRAY_SIZE(cmd_buffer->state.dynamic_offsets));
- assert(dynamic_slot + set_layout->dynamic_offset_count <=
-dynamicOffsetCount);
-
- typed_memcpy(_buffer->state.dynamic_offsets[dynamic_offset_start],
-  [dynamic_slot],
-  set_layout->dynamic_offset_count);
-
- dynamic_slot += set_layout->dynamic_offset_count;
-  }
-
-  cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
+  anv_cmd_buffer_bind_descriptor_set(cmd_buffer, layout,
+ firstSet + i, set,
+ ,
+ );
}
 }
 
@@ -944,8 +958,8 @@ void anv_CmdPushDescriptorSetKHR(
   }
}
 
-   cmd_buffer->state.descriptors[_set] = set;
-   cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
+   anv_cmd_buffer_bind_descriptor_set(cmd_buffer, layout, _set,
+  set, NULL, NULL);
 }
 
 void anv_CmdPushDescriptorSetWithTemplateKHR(
@@ -983,6 +997,6 @@ void anv_CmdPushDescriptorSetWithTemplateKHR(
  template,
  pData);
 
-   cmd_buffer->state.descriptors[_set] = set;
-   cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
+   anv_cmd_buffer_bind_descriptor_set(cmd_buffer, layout, _set,
+  set, NULL, NULL);
 }
-- 
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[Mesa-dev] [PATCH 03/17] anv/cmd_buffer: Get rid of the meta query workaround

2017-12-15 Thread Jason Ekstrand 
Meta has been gone for a long time.
---
 src/intel/vulkan/anv_cmd_buffer.c |  1 -
 src/intel/vulkan/anv_private.h|  1 -
 src/intel/vulkan/genX_query.c | 14 --
 3 files changed, 16 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 69acafa..c0270e1 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -146,7 +146,6 @@ anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
state->push_constant_stages = 0;
state->restart_index = UINT32_MAX;
state->dynamic = default_dynamic_state;
-   state->need_query_wa = true;
state->pma_fix_enabled = false;
state->hiz_enabled = false;
 
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 2d35aaa..d6436d5 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1704,7 +1704,6 @@ struct anv_cmd_state {
struct anv_state 
binding_tables[MESA_SHADER_STAGES];
struct anv_state samplers[MESA_SHADER_STAGES];
struct anv_dynamic_state dynamic;
-   bool need_query_wa;
 
struct anv_push_descriptor_set * push_descriptors[MAX_SETS];
 
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 7683d0d..726e565 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -385,20 +385,6 @@ void genX(CmdBeginQuery)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
 
-   /* Workaround: When meta uses the pipeline with the VS disabled, it seems
-* that the pipelining of the depth write breaks. What we see is that
-* samples from the render pass clear leaks into the first query
-* immediately after the clear. Doing a pipecontrol with a post-sync
-* operation and DepthStallEnable seems to work around the issue.
-*/
-   if (cmd_buffer->state.need_query_wa) {
-  cmd_buffer->state.need_query_wa = false;
-  anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
- pc.DepthCacheFlushEnable   = true;
- pc.DepthStallEnable= true;
-  }
-   }
-
switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION:
   emit_ps_depth_count(cmd_buffer, >bo, query * pool->stride + 8);
-- 
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[Mesa-dev] [PATCH 04/17] anv/cmd_buffer: Rework anv_cmd_state_reset

2017-12-15 Thread Jason Ekstrand 
This splits anv_cmd_state_reset into separate init and finish functions.
This lets us share init code with cmd_buffer_create.  This potentially
fixes subtle bugs where we may have missed some bit of state that needs
to get initialized on command buffer creation.
---
 src/intel/vulkan/anv_cmd_buffer.c | 60 ++-
 1 file changed, 22 insertions(+), 38 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index c0270e1..5436d54 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -113,46 +113,35 @@ anv_dynamic_state_copy(struct anv_dynamic_state *dest,
 }
 
 static void
-anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
+anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
 {
struct anv_cmd_state *state = _buffer->state;
 
-   cmd_buffer->batch.status = VK_SUCCESS;
+   memset(state, 0, sizeof(*state));
 
-   memset(>descriptors, 0, sizeof(state->descriptors));
-   for (uint32_t i = 0; i < ARRAY_SIZE(state->push_descriptors); i++) {
-  vk_free(_buffer->pool->alloc, state->push_descriptors[i]);
-  state->push_descriptors[i] = NULL;
-   }
-   for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
-  vk_free(_buffer->pool->alloc, state->push_constants[i]);
-  state->push_constants[i] = NULL;
-   }
-   memset(state->binding_tables, 0, sizeof(state->binding_tables));
-   memset(state->samplers, 0, sizeof(state->samplers));
-
-   /* 0 isn't a valid config.  This ensures that we always configure L3$. */
-   cmd_buffer->state.current_l3_config = 0;
-
-   state->dirty = 0;
-   state->vb_dirty = 0;
-   state->pending_pipe_bits = 0;
-   state->descriptors_dirty = 0;
-   state->push_constants_dirty = 0;
-   state->pipeline = NULL;
-   state->framebuffer = NULL;
-   state->pass = NULL;
-   state->subpass = NULL;
-   state->push_constant_stages = 0;
state->restart_index = UINT32_MAX;
state->dynamic = default_dynamic_state;
-   state->pma_fix_enabled = false;
-   state->hiz_enabled = false;
+}
+
+static void
+anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
+{
+   struct anv_cmd_state *state = _buffer->state;
+
+   for (uint32_t i = 0; i < ARRAY_SIZE(state->push_descriptors); i++)
+  vk_free(_buffer->pool->alloc, state->push_descriptors[i]);
+
+   for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
+  vk_free(_buffer->pool->alloc, state->push_constants[i]);
 
vk_free(_buffer->pool->alloc, state->attachments);
-   state->attachments = NULL;
+}
 
-   state->gen7.index_buffer = NULL;
+static void
+anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
+{
+   anv_cmd_state_finish(cmd_buffer);
+   anv_cmd_state_init(cmd_buffer);
 }
 
 VkResult
@@ -197,14 +186,10 @@ static VkResult anv_create_cmd_buffer(
 
cmd_buffer->batch.status = VK_SUCCESS;
 
-   for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
-  cmd_buffer->state.push_constants[i] = NULL;
-   }
cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
cmd_buffer->device = device;
cmd_buffer->pool = pool;
cmd_buffer->level = level;
-   cmd_buffer->state.attachments = NULL;
 
result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
if (result != VK_SUCCESS)
@@ -215,8 +200,7 @@ static VkResult anv_create_cmd_buffer(
anv_state_stream_init(_buffer->dynamic_state_stream,
  >dynamic_state_pool, 16384);
 
-   memset(cmd_buffer->state.push_descriptors, 0,
-  sizeof(cmd_buffer->state.push_descriptors));
+   anv_cmd_state_init(cmd_buffer);
 
if (pool) {
   list_addtail(_buffer->pool_link, >cmd_buffers);
@@ -275,7 +259,7 @@ anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
anv_state_stream_finish(_buffer->surface_state_stream);
anv_state_stream_finish(_buffer->dynamic_state_stream);
 
-   anv_cmd_state_reset(cmd_buffer);
+   anv_cmd_state_finish(cmd_buffer);
 
vk_free(_buffer->pool->alloc, cmd_buffer);
 }
-- 
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[Mesa-dev] [PATCH 08/17] anv/cmd_buffer: Refactor ensure_push_descriptor_set

2017-12-15 Thread Jason Ekstrand 
It's now a function which returns the push descriptor set.  Since we set
the error on the command buffer, returning the error is a little
redundant.  Returning the descriptor set (or NULL on error) is more
convenient.
---
 src/intel/vulkan/anv_cmd_buffer.c | 24 +---
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index dd50563..e5366fd 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -835,9 +835,9 @@ anv_cmd_buffer_get_depth_stencil_view(const struct 
anv_cmd_buffer *cmd_buffer)
return iview;
 }
 
-static VkResult
-anv_cmd_buffer_ensure_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
-  uint32_t set)
+static struct anv_push_descriptor_set *
+anv_cmd_buffer_get_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
+   uint32_t set)
 {
struct anv_push_descriptor_set **push_set =
   _buffer->state.push_descriptors[set];
@@ -848,11 +848,11 @@ anv_cmd_buffer_ensure_push_descriptor_set(struct 
anv_cmd_buffer *cmd_buffer,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
   if (*push_set == NULL) {
  anv_batch_set_error(_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ return NULL;
   }
}
 
-   return VK_SUCCESS;
+   return *push_set;
 }
 
 void anv_CmdPushDescriptorSetKHR(
@@ -873,10 +873,11 @@ void anv_CmdPushDescriptorSetKHR(
const struct anv_descriptor_set_layout *set_layout =
   layout->set[_set].layout;
 
-   if (anv_cmd_buffer_ensure_push_descriptor_set(cmd_buffer, _set) != 
VK_SUCCESS)
-  return;
struct anv_push_descriptor_set *push_set =
-  cmd_buffer->state.push_descriptors[_set];
+  anv_cmd_buffer_get_push_descriptor_set(cmd_buffer, _set);
+   if (!push_set)
+  return;
+
struct anv_descriptor_set *set = _set->set;
 
set->layout = set_layout;
@@ -964,10 +965,11 @@ void anv_CmdPushDescriptorSetWithTemplateKHR(
const struct anv_descriptor_set_layout *set_layout =
   layout->set[_set].layout;
 
-   if (anv_cmd_buffer_ensure_push_descriptor_set(cmd_buffer, _set) != 
VK_SUCCESS)
-  return;
struct anv_push_descriptor_set *push_set =
-  cmd_buffer->state.push_descriptors[_set];
+  anv_cmd_buffer_get_push_descriptor_set(cmd_buffer, _set);
+   if (!push_set)
+  return;
+
struct anv_descriptor_set *set = _set->set;
 
set->layout = set_layout;
-- 
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[Mesa-dev] [PATCH 11/17] anv: Separate compute and graphics descriptor sets

2017-12-15 Thread Jason Ekstrand 
The Vulkan spec says:

"pipelineBindPoint is a VkPipelineBindPoint indicating whether the
descriptors will be used by graphics pipelines or compute pipelines.
There is a separate set of bind points for each of graphics and
compute, so binding one does not disturb the other."

Up until now, we've been ignoring the pipeline bind point and had just
one bind point for everything.  This commit separates things out into
separate bind points.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102897
---
 src/intel/vulkan/anv_cmd_buffer.c | 65 ++-
 src/intel/vulkan/anv_descriptor_set.c |  2 ++
 src/intel/vulkan/anv_private.h| 11 +++---
 src/intel/vulkan/genX_cmd_buffer.c| 24 +++--
 4 files changed, 70 insertions(+), 32 deletions(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 636f515..9720e7e 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -124,12 +124,20 @@ anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
 }
 
 static void
+anv_cmd_pipeline_state_finish(struct anv_cmd_buffer *cmd_buffer,
+  struct anv_cmd_pipeline_state *pipe_state)
+{
+   for (uint32_t i = 0; i < ARRAY_SIZE(pipe_state->push_descriptors); i++)
+  vk_free(_buffer->pool->alloc, pipe_state->push_descriptors[i]);
+}
+
+static void
 anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
 {
struct anv_cmd_state *state = _buffer->state;
 
-   for (uint32_t i = 0; i < ARRAY_SIZE(state->push_descriptors); i++)
-  vk_free(_buffer->pool->alloc, state->push_descriptors[i]);
+   anv_cmd_pipeline_state_finish(cmd_buffer, >gfx.base);
+   anv_cmd_pipeline_state_finish(cmd_buffer, >compute.base);
 
for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
   vk_free(_buffer->pool->alloc, state->push_constants[i]);
@@ -495,6 +503,7 @@ void anv_CmdSetStencilReference(
 
 static void
 anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
+   VkPipelineBindPoint bind_point,
struct anv_pipeline_layout *layout,
uint32_t set_index,
struct anv_descriptor_set *set,
@@ -504,7 +513,14 @@ anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer 
*cmd_buffer,
struct anv_descriptor_set_layout *set_layout =
   layout->set[set_index].layout;
 
-   cmd_buffer->state.descriptors[set_index] = set;
+   struct anv_cmd_pipeline_state *pipe_state;
+   if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
+  pipe_state = _buffer->state.compute.base;
+   } else {
+  assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
+  pipe_state = _buffer->state.gfx.base;
+   }
+   pipe_state->descriptors[set_index] = set;
 
if (dynamic_offsets) {
   if (set_layout->dynamic_offset_count > 0) {
@@ -514,9 +530,9 @@ anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer 
*cmd_buffer,
  /* Assert that everything is in range */
  assert(set_layout->dynamic_offset_count <= *dynamic_offset_count);
  assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
-ARRAY_SIZE(cmd_buffer->state.dynamic_offsets));
+ARRAY_SIZE(pipe_state->dynamic_offsets));
 
- typed_memcpy(_buffer->state.dynamic_offsets[dynamic_offset_start],
+ typed_memcpy(_state->dynamic_offsets[dynamic_offset_start],
   *dynamic_offsets, set_layout->dynamic_offset_count);
 
  *dynamic_offsets += set_layout->dynamic_offset_count;
@@ -524,7 +540,13 @@ anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer 
*cmd_buffer,
   }
}
 
-   cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
+   if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
+  cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
+   } else {
+  assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
+  cmd_buffer->state.descriptors_dirty |=
+ set_layout->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
+   }
 }
 
 void anv_CmdBindDescriptorSets(
@@ -544,8 +566,8 @@ void anv_CmdBindDescriptorSets(
 
for (uint32_t i = 0; i < descriptorSetCount; i++) {
   ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
-  anv_cmd_buffer_bind_descriptor_set(cmd_buffer, layout,
- firstSet + i, set,
+  anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
+ layout, firstSet + i, set,
  ,
  );
}
@@ -851,10 +873,19 @@ anv_cmd_buffer_get_depth_stencil_view(const struct 
anv_cmd_buffer *cmd_buffer)
 
 static struct anv_push_descriptor_set *
 anv_cmd_buffer_get_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
+

[Mesa-dev] [PATCH 07/17] anv: Remove semicolons from vk_error[f] definitions

2017-12-15 Thread Jason Ekstrand 
With the semicolons, they can't be used in a function argument without
throwing syntax errors.
---
 src/intel/vulkan/anv_private.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 9860778..e8d0d27 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -312,10 +312,10 @@ VkResult __vk_errorf(struct anv_instance *instance, const 
void *object,
 #ifdef DEBUG
 #define vk_error(error) __vk_errorf(NULL, NULL,\
 VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT,\
-error, __FILE__, __LINE__, NULL);
+error, __FILE__, __LINE__, NULL)
 #define vk_errorf(instance, obj, error, format, ...)\
 __vk_errorf(instance, obj, REPORT_OBJECT_TYPE(obj), error,\
-__FILE__, __LINE__, format, ## __VA_ARGS__);
+__FILE__, __LINE__, format, ## __VA_ARGS__)
 #else
 #define vk_error(error) error
 #define vk_errorf(instance, obj, error, format, ...) error
-- 
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[Mesa-dev] [PATCH] Revert "anv/pipeline: Don't assert on more than 32 samplers"

2017-12-15 Thread Jason Ekstrand 
This reverts commit 5fe67607d261b2f85c8f89914fe9bfef4eaf7561.
---
 src/intel/vulkan/genX_pipeline.c | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index b6a537b..0ae9ead 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1081,13 +1081,7 @@ emit_3dstate_streamout(struct anv_pipeline *pipeline,
 static uint32_t
 get_sampler_count(const struct anv_shader_bin *bin)
 {
-   uint32_t count_by_4 = DIV_ROUND_UP(bin->bind_map.sampler_count, 4);
-
-   /* We can potentially have way more than 32 samplers and that's ok.
-* However, the 3DSTATE_XS packets only have 3 bits to specify how
-* many to pre-fetch and all values above 4 are marked reserved.
-*/
-   return MIN2(count_by_4, 4);
+   return DIV_ROUND_UP(bin->bind_map.sampler_count, 4);
 }
 
 static uint32_t
-- 
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Re: [Mesa-dev] [PATCH 22/22] mesa: Add GL_UNSIGNED_INT_2_10_10_10_REV OES read type for BGRX1010102.

2017-12-15 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek

On Fri, Dec 15, 2017 at 11:05 PM, Mario Kleiner
 wrote:
> As Marek noted, the GL_RGBA + GL_UNSIGNED_INT_2_10_10_10_REV type
> combo is also good for readback of BGRX1010102 framebuffers, not
> only for BGRA1010102 framebuffers for use with glReadPixels()
> under GLES, so add it for the GL_IMPLEMENTATION_COLOR_READ_TYPE_OES
> query.
>
> Successfully tested on gallium r600 driver with a (quickly hacked
> for RGBA 10 10 10 0) dEQP testcase
> dEQP-EGL.functional.wide_color.window_1010102_colorspace_default.
>
> Suggested-by: Marek Olšák 
> Signed-off-by: Mario Kleiner 
> ---
>  src/mesa/main/framebuffer.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
> index a0de669..e103f31 100644
> --- a/src/mesa/main/framebuffer.c
> +++ b/src/mesa/main/framebuffer.c
> @@ -889,7 +889,8 @@ _mesa_get_color_read_type(struct gl_context *ctx,
>if (format == MESA_FORMAT_B5G6R5_UNORM)
>   return GL_UNSIGNED_SHORT_5_6_5;
>
> -  if (format == MESA_FORMAT_B10G10R10A2_UNORM)
> +  if (format == MESA_FORMAT_B10G10R10A2_UNORM ||
> +  format == MESA_FORMAT_B10G10R10X2_UNORM)
>   return GL_UNSIGNED_INT_2_10_10_10_REV;
>
>switch (data_type) {
> --
> 2.7.4
>
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[Mesa-dev] [PATCH 3/8] anv: Make the clear state buffer 64 bytes aligned.

2017-12-15 Thread Rafael Antognolli 
On Gen10+, if we use the clear state address field in the surface state
instead of the clear color directly, there's a restriction that the
address must point to the lower part of a 64 byte cache-line.

Signed-off-by: Rafael Antognolli 
---
 src/intel/vulkan/anv_private.h | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index b7bde4b8ce6..43cbf065724 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2490,7 +2490,17 @@ anv_fast_clear_state_entry_size(const struct anv_device 
*device)
 * GPU memcpy operations.
 */
assert(device->isl_dev.ss.clear_value_size % 4 == 0);
-   return device->isl_dev.ss.clear_value_size + 4;
+
+   const unsigned entry_size = device->isl_dev.ss.clear_value_size + 4;
+   /* On Gen10+, we use the clear color address of the surface to point to this
+* buffer directly. However, according to the bspec:
+*
+*The memory layout of the clear color pointed to by this address is a
+*value stored in the lower-order bytes of a 64-byte cache-line.
+*
+* So add some padding here for Gen10+.
+*/
+   return device->info.gen >= 10 ? ALIGN(entry_size, 64) : entry_size;
 }
 
 static inline struct anv_address
-- 
2.14.3

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[Mesa-dev] [PATCH 4/8] intel/blorp: Add suport for fast clear address.

2017-12-15 Thread Rafael Antognolli 
On gen10+, if surface->clear_color_addr is present, use it directly
intead of copying it to the surface state.

Signed-off-by: Rafael Antognolli 
---
 src/intel/blorp/blorp_genX_exec.h | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 1968460be05..a01d21c2cdd 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1276,11 +1276,15 @@ blorp_emit_surface_state(struct blorp_batch *batch,
  write_disable_mask |= ISL_CHANNEL_ALPHA_BIT;
}
 
+   const bool use_clear_address =
+  GEN_GEN >= 10 && (surface->clear_color_addr.buffer != NULL);
+
isl_surf_fill_state(batch->blorp->isl_dev, state,
.surf = , .view = >view,
.aux_surf = >aux_surf, .aux_usage = aux_usage,
.mocs = surface->addr.mocs,
.clear_color = surface->clear_color,
+   .use_clear_address = use_clear_address,
.write_disables = write_disable_mask);
 
blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset,
@@ -1300,9 +1304,11 @@ blorp_emit_surface_state(struct blorp_batch *batch,
blorp_flush_range(batch, state, GENX(RENDER_SURFACE_STATE_length) * 4);
 
if (surface->clear_color_addr.buffer) {
-#if GEN_GEN > 10
-  unreachable("Implement indirect clear support on gen11+");
-#elif GEN_GEN >= 7 && GEN_GEN <= 10
+#if GEN_GEN >= 10
+  assert((surface->clear_color_addr.offset & 0x3f) == 0);
+  blorp_surface_reloc(batch, state_offset + isl_dev->ss.clear_value_offset,
+  surface->clear_color_addr, 0);
+#elif GEN_GEN >= 7 && GEN_GEN < 10
   struct blorp_address dst_addr = blorp_get_surface_base_address(batch);
   dst_addr.offset += state_offset + isl_dev->ss.clear_value_offset;
   blorp_emit_memcpy(batch, dst_addr, surface->clear_color_addr,
-- 
2.14.3

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[Mesa-dev] [PATCH 8/8] i965/surface_state: Silence warning.

2017-12-15 Thread Rafael Antognolli 
This warning showed up after aux_bo started being used inside

if (use_clear_address) {...

But use_clear_address depends on aux_surf being not null, in which case
aux_bo would also be set. Make the compiler happy anyway.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 9f583ca995f..78968aa83d0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -148,7 +148,7 @@ brw_emit_surface_state(struct brw_context *brw,
 
union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
 
-   struct brw_bo *aux_bo;
+   struct brw_bo *aux_bo = NULL;
struct isl_surf *aux_surf = NULL;
uint64_t aux_offset = 0;
switch (aux_usage) {
-- 
2.14.3

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[Mesa-dev] [PATCH 7/8] i965/surface_state: Emit the clear color address instead of value.

2017-12-15 Thread Rafael Antognolli 
On Gen10, when emitting the surface state, use the value stored in the
clear color entry buffer by using a clear color address in the surface
state.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index adf60a840b0..9f583ca995f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -182,6 +182,10 @@ brw_emit_surface_state(struct brw_context *brw,
  brw->isl_dev.ss.align,
  surf_offset);
 
+   bool use_clear_address = devinfo->gen >= 10 && aux_surf;
+   uint32_t clear_offset =
+  use_clear_address ? aux_offset + aux_surf->size : 0;
+
isl_surf_fill_state(>isl_dev, state, .surf = >surf, .view = ,
.address = brw_state_reloc(>batch,
   *surf_offset + 
brw->isl_dev.ss.addr_offset,
@@ -190,6 +194,8 @@ brw_emit_surface_state(struct brw_context *brw,
.aux_address = aux_offset,
.mocs = brw_get_bo_mocs(devinfo, mt->bo),
.clear_color = clear_color,
+   .use_clear_address = use_clear_address,
+   .clear_address = clear_offset,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
if (aux_surf) {
   /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
@@ -208,6 +214,16 @@ brw_emit_surface_state(struct brw_context *brw,
   aux_bo, *aux_addr,
   reloc_flags);
}
+
+   if (use_clear_address) {
+  /* Make sure the offset is aligned with a cacheline. */
+  assert((clear_offset & 0x3f) == 0);
+  uint32_t *clear_address = state + brw->isl_dev.ss.clear_value_offset;
+  *clear_address = brw_state_reloc(>batch,
+   *surf_offset +
+   brw->isl_dev.ss.clear_value_offset,
+   aux_bo, *clear_address, reloc_flags);
+   }
 }
 
 static uint32_t
-- 
2.14.3

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[Mesa-dev] [PATCH 2/8] intel/isl: Add support to emit clear value address.

2017-12-15 Thread Rafael Antognolli 
gen10 can emit the clear color by setting it on a buffer somewhere, and
then adding only the address to the surface state.

This commit add support for that on isl_surf_fill_state, and if that is
requested, skip setting the clear value itself.

Signed-off-by: Rafael Antognolli 
---
 src/intel/isl/isl.h   |  9 +
 src/intel/isl/isl_surface_state.c | 15 +++
 2 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index e3acb0ec280..c6e1fee27c1 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -1277,6 +1277,15 @@ struct isl_surf_fill_state_info {
 */
union isl_color_value clear_color;
 
+   /**
+* Send only the clear value address
+*
+* If set, we only pass the clear address to the GPU and it will fetch it
+* from wherever it is.
+*/
+   bool use_clear_address;
+   uint64_t clear_address;
+
/**
 * Surface write disables for gen4-5
 */
diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index bfb27fa4a44..14741459687 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -635,11 +635,18 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
 #endif
 
if (info->aux_usage != ISL_AUX_USAGE_NONE) {
+#if GEN_GEN >= 10
+  s.ClearValueAddressEnable = info->use_clear_address;
+  s.ClearValueAddressHigh = info->clear_address >> 32;
+  s.ClearValueAddressLow = info->clear_address;
+#endif
 #if GEN_GEN >= 9
-  s.RedClearColor = info->clear_color.u32[0];
-  s.GreenClearColor = info->clear_color.u32[1];
-  s.BlueClearColor = info->clear_color.u32[2];
-  s.AlphaClearColor = info->clear_color.u32[3];
+  if (!info->use_clear_address) {
+ s.RedClearColor = info->clear_color.u32[0];
+ s.GreenClearColor = info->clear_color.u32[1];
+ s.BlueClearColor = info->clear_color.u32[2];
+ s.AlphaClearColor = info->clear_color.u32[3];
+  }
 #elif GEN_GEN >= 7
   /* Prior to Sky Lake, we only have one bit for the clear color which
* gives us 0 or 1 in whatever the surface's format happens to be.
-- 
2.14.3

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[Mesa-dev] [PATCH 6/8] i965/blorp: Update the fast clear color entry buffer.

2017-12-15 Thread Rafael Antognolli 
On Gen10, whenever the fast clear color changes, update it on the clear
color entry buffer. This allow us to use it directly when emitting the
surface state.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 680121b6ab1..9ca5626ba91 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1135,6 +1135,27 @@ set_write_disables(const struct intel_renderbuffer *irb,
return disables;
 }
 
+static void
+update_fast_clear_color(struct brw_context *brw,
+struct blorp_surf *surf,
+const union isl_color_value clear_color)
+{
+   assert(surf);
+   /* Clear values are stored at the same bo as the aux surface, right
+* after the surface.
+*/
+   uint32_t clear_offset = surf->aux_addr.offset + surf->aux_surf->size;
+   for (int i = 0; i < brw->isl_dev.ss.clear_value_size; i++) {
+  brw_store_data_imm32(brw, surf->aux_addr.buffer,
+   clear_offset + i * 4, clear_color.u32[i]);
+   }
+
+   surf->clear_color_addr = (struct blorp_address) {
+  .buffer = surf->aux_addr.buffer,
+  .offset = clear_offset,
+   };
+}
+
 static void
 do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
   struct gl_renderbuffer *rb, unsigned buf,
@@ -1230,6 +1251,11 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   blorp_surf_for_miptree(brw, , irb->mt, irb->mt->aux_usage, true,
  , irb->mt_layer, num_layers, isl_tmp);
 
+  /* update clear color */
+  const struct gen_device_info *devinfo = >screen->devinfo;
+  if (devinfo->gen >= 10 && !same_clear_color)
+ update_fast_clear_color(brw, , clear_color);
+
   /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
*
*"Any transition from any value in {Clear, Render, Resolve} to a
-- 
2.14.3

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[Mesa-dev] [PATCH 5/8] i965/miptree: Add space to store the clear value in the aux surface.

2017-12-15 Thread Rafael Antognolli 
Similarly to vulkan where we store the clear value in the aux surface,
we can do the same in GL.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ead0c359c0f..6400a2a616a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1663,6 +1663,21 @@ intel_miptree_init_mcs(struct brw_context *brw,
brw_bo_unmap(mt->mcs_buf->bo);
 }
 
+static unsigned
+fast_clear_state_entry_size(const struct brw_context *brw)
+{
+   assert(brw);
+
+   /* Entry contents:
+*   ++
+*   | clear value dword(s)   |
+*   ++
+*/
+   assert(brw->isl_dev.ss.clear_value_size % 4 == 0);
+
+   return brw->isl_dev.ss.clear_value_size;
+}
+
 static struct intel_miptree_aux_buffer *
 intel_alloc_aux_buffer(struct brw_context *brw,
const char *name,
@@ -1675,6 +1690,16 @@ intel_alloc_aux_buffer(struct brw_context *brw,
   return false;
 
buf->size = aux_surf->size;
+
+   const struct gen_device_info *devinfo = >screen->devinfo;
+   if (devinfo->gen >= 10) {
+  /* On CNL, instead of setting the clear color in the SURFACE_STATE, we
+   * will set a pointer to a dword somewhere that contains the color. So,
+   * allocate the space for the clear color value here on the aux buffer.
+   */
+  buf->size += fast_clear_state_entry_size(brw);
+   }
+
buf->pitch = aux_surf->row_pitch;
buf->qpitch = isl_surf_get_array_pitch_sa_rows(aux_surf);
 
-- 
2.14.3

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[Mesa-dev] [PATCH 1/8] intel/genxml: Use a single field for clear color address on gen10.

2017-12-15 Thread Rafael Antognolli 
genxml does not support having two address fields with different names
but same position in the state struct. Both "Clear Color Address"
and "Clear Depth Address Low" mean the same thing, only for different
surface types.

To workaround this genxml limitation, rename "Clear Color Address"
to "Clear Value Address Low" and use it for both color and depth. Do the
same for the high bits.

TODO: add support for multiple addresses at the same position in the
xml.

Signed-off-by: Rafael Antognolli 
---
 src/intel/genxml/gen10.xml | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index a6b8f48fda5..aeaa77871c8 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -801,11 +801,13 @@
 
 
 
-
-
+
+
 
-
-
+
+
 
 
   
-- 
2.14.3

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[Mesa-dev] [PATCH 17/22] st/dri2: Add format translations for BGR[A/X]1010102 formats.

2017-12-15 Thread Mario Kleiner 
Signed-off-by: Mario Kleiner 
Reviewed-by: Marek Olšák 
---
 src/gallium/state_trackers/dri/dri2.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/src/gallium/state_trackers/dri/dri2.c 
b/src/gallium/state_trackers/dri/dri2.c
index d5ae9cb..f7fd08d 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -55,6 +55,8 @@
 #endif
 
 static const int fourcc_formats[] = {
+   __DRI_IMAGE_FOURCC_ARGB2101010,
+   __DRI_IMAGE_FOURCC_XRGB2101010,
__DRI_IMAGE_FOURCC_ARGB,
__DRI_IMAGE_FOURCC_ABGR,
__DRI_IMAGE_FOURCC_SARGB,
@@ -105,6 +107,14 @@ static int convert_fourcc(int format, int 
*dri_components_p)
   format = __DRI_IMAGE_FORMAT_XBGR;
   dri_components = __DRI_IMAGE_COMPONENTS_RGB;
   break;
+   case __DRI_IMAGE_FOURCC_ARGB2101010:
+  format = __DRI_IMAGE_FORMAT_ARGB2101010;
+  dri_components = __DRI_IMAGE_COMPONENTS_RGBA;
+  break;
+   case __DRI_IMAGE_FOURCC_XRGB2101010:
+  format = __DRI_IMAGE_FORMAT_XRGB2101010;
+  dri_components = __DRI_IMAGE_COMPONENTS_RGB;
+  break;
case __DRI_IMAGE_FOURCC_R8:
   format = __DRI_IMAGE_FORMAT_R8;
   dri_components = __DRI_IMAGE_COMPONENTS_R;
@@ -166,6 +176,12 @@ static int convert_to_fourcc(int format)
case __DRI_IMAGE_FORMAT_XBGR:
   format = __DRI_IMAGE_FOURCC_XBGR;
   break;
+   case __DRI_IMAGE_FORMAT_ARGB2101010:
+  format = __DRI_IMAGE_FOURCC_ARGB2101010;
+  break;
+   case __DRI_IMAGE_FORMAT_XRGB2101010:
+  format = __DRI_IMAGE_FOURCC_XRGB2101010;
+  break;
case __DRI_IMAGE_FORMAT_R8:
   format = __DRI_IMAGE_FOURCC_R8;
   break;
@@ -198,6 +214,12 @@ static enum pipe_format dri2_format_to_pipe_format (int 
format)
case __DRI_IMAGE_FORMAT_ABGR:
   pf = PIPE_FORMAT_RGBA_UNORM;
   break;
+   case __DRI_IMAGE_FORMAT_XRGB2101010:
+  pf = PIPE_FORMAT_B10G10R10X2_UNORM;
+  break;
+   case __DRI_IMAGE_FORMAT_ARGB2101010:
+  pf = PIPE_FORMAT_B10G10R10A2_UNORM;
+  break;
case __DRI_IMAGE_FORMAT_R8:
   pf = PIPE_FORMAT_R8_UNORM;
   break;
@@ -253,6 +275,12 @@ static enum pipe_format fourcc_to_pipe_format(int fourcc)
case __DRI_IMAGE_FOURCC_XBGR:
   pf = PIPE_FORMAT_RGBX_UNORM;
   break;
+   case __DRI_IMAGE_FOURCC_ARGB2101010:
+  pf = PIPE_FORMAT_B10G10R10A2_UNORM;
+  break;
+   case __DRI_IMAGE_FOURCC_XRGB2101010:
+  pf = PIPE_FORMAT_B10G10R10X2_UNORM;
+  break;
 
case __DRI_IMAGE_FOURCC_NV12:
   pf = PIPE_FORMAT_NV12;
-- 
2.7.4

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[Mesa-dev] [PATCH 21/22] st/dri: Add option to control exposure of 10 bpc color configs.

2017-12-15 Thread Mario Kleiner 
Some clients may not like rgb10 fbconfigs and visuals.
Support driconf option 'allow_rgb10_configs' on gallium
to allow per application enable/disable.

The option defaults to enabled.

Signed-off-by: Mario Kleiner 
Reviewed-by: Marek Olšák 
---
 src/gallium/auxiliary/pipe-loader/driinfo_gallium.h | 1 +
 src/gallium/state_trackers/dri/dri_screen.c | 8 
 2 files changed, 9 insertions(+)

diff --git a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h 
b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
index 003a3d7..505aae4 100644
--- a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
+++ b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
@@ -32,4 +32,5 @@ DRI_CONF_SECTION_END
 DRI_CONF_SECTION_MISCELLANEOUS
DRI_CONF_ALWAYS_HAVE_DEPTH_BUFFER("false")
DRI_CONF_GLSL_ZERO_INIT("false")
+   DRI_CONF_ALLOW_RGB10_CONFIGS("true")
 DRI_CONF_SECTION_END
diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
b/src/gallium/state_trackers/dri/dri_screen.c
index 46ca8fa..adce2ff 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -158,6 +158,7 @@ dri_fill_in_modes(struct dri_screen *screen)
struct pipe_screen *p_screen = screen->base.screen;
boolean pf_z16, pf_x8z24, pf_z24x8, pf_s8z24, pf_z24s8, pf_z32;
boolean mixed_color_depth;
+   boolean allow_rgb10;
 
static const GLenum back_buffer_modes[] = {
   __DRI_ATTRIB_SWAP_NONE, __DRI_ATTRIB_SWAP_UNDEFINED,
@@ -174,6 +175,8 @@ dri_fill_in_modes(struct dri_screen *screen)
   depth_buffer_factor = 1;
}
 
+   allow_rgb10 = driQueryOptionb(>dev->option_cache, 
"allow_rgb10_configs");
+
msaa_samples_max = (screen->st_api->feature_mask & 
ST_API_FEATURE_MS_VISUALS_MASK)
   ? MSAA_VISUAL_MAX_SAMPLES : 1;
 
@@ -233,6 +236,11 @@ dri_fill_in_modes(struct dri_screen *screen)
   unsigned num_msaa_modes = 0; /* includes a single-sample mode */
   uint8_t msaa_modes[MSAA_VISUAL_MAX_SAMPLES];
 
+  if (!allow_rgb10 &&
+  (mesa_formats[format] == MESA_FORMAT_B10G10R10A2_UNORM ||
+   mesa_formats[format] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
   if (!p_screen->is_format_supported(p_screen, pipe_formats[format],
  PIPE_TEXTURE_2D, 0,
  PIPE_BIND_RENDER_TARGET))
-- 
2.7.4

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[Mesa-dev] [PATCH 22/22] mesa: Add GL_UNSIGNED_INT_2_10_10_10_REV OES read type for BGRX1010102.

2017-12-15 Thread Mario Kleiner 
As Marek noted, the GL_RGBA + GL_UNSIGNED_INT_2_10_10_10_REV type
combo is also good for readback of BGRX1010102 framebuffers, not
only for BGRA1010102 framebuffers for use with glReadPixels()
under GLES, so add it for the GL_IMPLEMENTATION_COLOR_READ_TYPE_OES
query.

Successfully tested on gallium r600 driver with a (quickly hacked
for RGBA 10 10 10 0) dEQP testcase
dEQP-EGL.functional.wide_color.window_1010102_colorspace_default.

Suggested-by: Marek Olšák 
Signed-off-by: Mario Kleiner 
---
 src/mesa/main/framebuffer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index a0de669..e103f31 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa/main/framebuffer.c
@@ -889,7 +889,8 @@ _mesa_get_color_read_type(struct gl_context *ctx,
   if (format == MESA_FORMAT_B5G6R5_UNORM)
  return GL_UNSIGNED_SHORT_5_6_5;
 
-  if (format == MESA_FORMAT_B10G10R10A2_UNORM)
+  if (format == MESA_FORMAT_B10G10R10A2_UNORM ||
+  format == MESA_FORMAT_B10G10R10X2_UNORM)
  return GL_UNSIGNED_INT_2_10_10_10_REV;
 
   switch (data_type) {
-- 
2.7.4

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[Mesa-dev] [PATCH 20/22] st/dri: Add support for BGR[A/X]1010102 formats.

2017-12-15 Thread Mario Kleiner 
Exposes RGBA 10 10 10 2 and 10 10 10 0 visuals and
fbconfigs for rendering.

Signed-off-by: Mario Kleiner 
Reviewed-by: Marek Olšák 
---
 src/gallium/state_trackers/dri/dri_screen.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
b/src/gallium/state_trackers/dri/dri_screen.c
index 1ca5116..46ca8fa 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -108,6 +108,8 @@ static const __DRIconfig **
 dri_fill_in_modes(struct dri_screen *screen)
 {
static const mesa_format mesa_formats[] = {
+  MESA_FORMAT_B10G10R10A2_UNORM,
+  MESA_FORMAT_B10G10R10X2_UNORM,
   MESA_FORMAT_B8G8R8A8_UNORM,
   MESA_FORMAT_B8G8R8X8_UNORM,
   MESA_FORMAT_B8G8R8A8_SRGB,
@@ -136,6 +138,8 @@ dri_fill_in_modes(struct dri_screen *screen)
   MESA_FORMAT_R8G8B8X8_UNORM,
};
static const enum pipe_format pipe_formats[] = {
+  PIPE_FORMAT_B10G10R10A2_UNORM,
+  PIPE_FORMAT_B10G10R10X2_UNORM,
   PIPE_FORMAT_BGRA_UNORM,
   PIPE_FORMAT_BGRX_UNORM,
   PIPE_FORMAT_BGRA_SRGB,
@@ -221,7 +225,7 @@ dri_fill_in_modes(struct dri_screen *screen)
if (dri_loader_get_cap(screen, DRI_LOADER_CAP_RGBA_ORDERING))
   num_formats = ARRAY_SIZE(mesa_formats);
else
-  num_formats = ARRAY_SIZE(mesa_formats) - 2;
+  num_formats = ARRAY_SIZE(mesa_formats) - 2; /* all - RGBA_ORDERING 
formats */
 
/* Add configs. */
for (format = 0; format < num_formats; format++) {
@@ -289,6 +293,15 @@ dri_fill_st_visual(struct st_visual *stvis, struct 
dri_screen *screen,
 
/* Deduce the color format. */
switch (mode->redMask) {
+   case 0x3FF0:
+  if (mode->alphaMask) {
+ assert(mode->alphaMask == 0xC000);
+ stvis->color_format = PIPE_FORMAT_B10G10R10A2_UNORM;
+  } else {
+ stvis->color_format = PIPE_FORMAT_B10G10R10X2_UNORM;
+  }
+  break;
+
case 0x00FF:
   if (mode->alphaMask) {
  assert(mode->alphaMask == 0xFF00);
-- 
2.7.4

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[Mesa-dev] [PATCH 16/22] st/mesa: Handle BGR[A/X]1010102 formats.

2017-12-15 Thread Mario Kleiner 
Signed-off-by: Mario Kleiner 
Reviewed-by: Marek Olšák 
---
 src/mesa/state_tracker/st_cb_fbo.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/state_tracker/st_cb_fbo.c 
b/src/mesa/state_tracker/st_cb_fbo.c
index e2303b4..a982f87 100644
--- a/src/mesa/state_tracker/st_cb_fbo.c
+++ b/src/mesa/state_tracker/st_cb_fbo.c
@@ -286,6 +286,12 @@ st_new_renderbuffer_fb(enum pipe_format format, int 
samples, boolean sw)
strb->software = sw;
 
switch (format) {
+   case PIPE_FORMAT_B10G10R10A2_UNORM:
+  strb->Base.InternalFormat = GL_RGB10_A2;
+  break;
+   case PIPE_FORMAT_B10G10R10X2_UNORM:
+  strb->Base.InternalFormat = GL_RGB10;
+  break;
case PIPE_FORMAT_R8G8B8A8_UNORM:
case PIPE_FORMAT_B8G8R8A8_UNORM:
case PIPE_FORMAT_A8R8G8B8_UNORM:
-- 
2.7.4

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[Mesa-dev] [PATCH 19/22] st/dri: Support texture_from_pixmap for BGR[A/X]1010102 formats.

2017-12-15 Thread Mario Kleiner 
Signed-off-by: Mario Kleiner 
Reviewed-by: Marek Olšák 
---
 src/gallium/state_trackers/dri/dri_drawable.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/state_trackers/dri/dri_drawable.c 
b/src/gallium/state_trackers/dri/dri_drawable.c
index 92ce9d2..a5999be 100644
--- a/src/gallium/state_trackers/dri/dri_drawable.c
+++ b/src/gallium/state_trackers/dri/dri_drawable.c
@@ -260,6 +260,9 @@ dri_set_tex_buffer2(__DRIcontext *pDRICtx, GLint target,
   if (format == __DRI_TEXTURE_FORMAT_RGB)  {
  /* only need to cover the formats recognized by dri_fill_st_visual */
  switch (internal_format) {
+ case PIPE_FORMAT_B10G10R10A2_UNORM:
+internal_format = PIPE_FORMAT_B10G10R10X2_UNORM;
+break;
  case PIPE_FORMAT_BGRA_UNORM:
 internal_format = PIPE_FORMAT_BGRX_UNORM;
 break;
-- 
2.7.4

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[Mesa-dev] [PATCH 13/22] egl/wayland: Add Wayland drm support for RGB10 winsys buffers.

2017-12-15 Thread Mario Kleiner 
Successfully tested under Weston 3.0.
Photometer confirms 10 rgb bits from rendering to display.

Signed-off-by: Mario Kleiner 
Reviewed-by: Marek Olšák 
---
 src/egl/drivers/dri2/platform_wayland.c   | 37 ---
 src/egl/wayland/wayland-drm/wayland-drm.c |  6 +
 2 files changed, 40 insertions(+), 3 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 02b32f9..3633c83 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -61,6 +61,8 @@ enum wl_drm_format_flags {
HAS_ARGB = 1,
HAS_XRGB = 2,
HAS_RGB565 = 4,
+   HAS_ARGB2101010 = 8,
+   HAS_XRGB2101010 = 16,
 };
 
 static int
@@ -148,10 +150,14 @@ dri2_wl_create_window_surface(_EGLDriver *drv, 
_EGLDisplay *disp,
if (dri2_dpy->wl_dmabuf || dri2_dpy->wl_drm) {
   if (conf->RedSize == 5)
  dri2_surf->format = WL_DRM_FORMAT_RGB565;
-  else if (conf->AlphaSize == 0)
+  else if (conf->RedSize == 8 && conf->AlphaSize == 0)
  dri2_surf->format = WL_DRM_FORMAT_XRGB;
-  else
+  else if (conf->RedSize == 8)
  dri2_surf->format = WL_DRM_FORMAT_ARGB;
+  else if (conf->RedSize == 10 && conf->AlphaSize == 0)
+ dri2_surf->format = WL_DRM_FORMAT_XRGB2101010;
+  else if (conf->RedSize == 10)
+ dri2_surf->format = WL_DRM_FORMAT_ARGB2101010;
} else {
   assert(dri2_dpy->wl_shm);
   if (conf->RedSize == 5)
@@ -340,11 +346,18 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
uint64_t *modifiers;
int num_modifiers;
 
-   /* currently supports three WL DRM formats,
+   /* currently supports five WL DRM formats,
+* WL_DRM_FORMAT_ARGB2101010, WL_DRM_FORMAT_XRGB2101010,
 * WL_DRM_FORMAT_ARGB, WL_DRM_FORMAT_XRGB,
 * and WL_DRM_FORMAT_RGB565
 */
switch (dri2_surf->format) {
+   case WL_DRM_FORMAT_ARGB2101010:
+  dri_image_format = __DRI_IMAGE_FORMAT_ARGB2101010;
+  break;
+   case WL_DRM_FORMAT_XRGB2101010:
+  dri_image_format = __DRI_IMAGE_FORMAT_XRGB2101010;
+  break;
case WL_DRM_FORMAT_ARGB:
   dri_image_format = __DRI_IMAGE_FORMAT_ARGB;
   modifiers = u_vector_tail(_dpy->wl_modifiers.argb);
@@ -581,6 +594,8 @@ dri2_wl_get_buffers(__DRIdrawable * driDrawable,
unsigned int bpp;
 
switch (dri2_surf->format) {
+   case WL_DRM_FORMAT_ARGB2101010:
+   case WL_DRM_FORMAT_XRGB2101010:
case WL_DRM_FORMAT_ARGB:
case WL_DRM_FORMAT_XRGB:
   bpp = 32;
@@ -972,6 +987,14 @@ dri2_wl_create_wayland_buffer_from_image(_EGLDriver *drv,
 
dri2_dpy->image->queryImage(image, __DRI_IMAGE_ATTRIB_FORMAT, );
switch (format) {
+   case __DRI_IMAGE_FORMAT_ARGB2101010:
+  if (!(dri2_dpy->formats & HAS_ARGB2101010))
+ goto bad_format;
+  break;
+   case __DRI_IMAGE_FORMAT_XRGB2101010:
+  if (!(dri2_dpy->formats & HAS_XRGB2101010))
+ goto bad_format;
+  break;
case __DRI_IMAGE_FORMAT_ARGB:
   if (!(dri2_dpy->formats & HAS_ARGB))
  goto bad_format;
@@ -1059,6 +1082,12 @@ drm_handle_format(void *data, struct wl_drm *drm, 
uint32_t format)
struct dri2_egl_display *dri2_dpy = data;
 
switch (format) {
+   case WL_DRM_FORMAT_ARGB2101010:
+  dri2_dpy->formats |= HAS_ARGB2101010;
+  break;
+   case WL_DRM_FORMAT_XRGB2101010:
+  dri2_dpy->formats |= HAS_XRGB2101010;
+  break;
case WL_DRM_FORMAT_ARGB:
   dri2_dpy->formats |= HAS_ARGB;
   break;
@@ -1227,6 +1256,8 @@ dri2_wl_add_configs_for_visuals(_EGLDriver *drv, 
_EGLDisplay *disp)
   int has_format;
   unsigned int rgba_masks[4];
} visuals[] = {
+  { "XRGB2101010", HAS_XRGB2101010, { 0x3ff0, 0xffc00, 0x3ff, 0 } },
+  { "ARGB2101010", HAS_ARGB2101010, { 0x3ff0, 0xffc00, 0x3ff, 
0xc000 } },
   { "XRGB", HAS_XRGB, { 0xff, 0xff00, 0x00ff, 0xff00 } },
   { "ARGB", HAS_ARGB, { 0xff, 0xff00, 0x00ff, 0 } },
   { "RGB565",   HAS_RGB565,   { 0x00f800, 0x07e0, 0x001f, 0 } },
diff --git a/src/egl/wayland/wayland-drm/wayland-drm.c 
b/src/egl/wayland/wayland-drm/wayland-drm.c
index 81f6f528..3c6696d 100644
--- a/src/egl/wayland/wayland-drm/wayland-drm.c
+++ b/src/egl/wayland/wayland-drm/wayland-drm.c
@@ -111,6 +111,8 @@ drm_create_buffer(struct wl_client *client, struct 
wl_resource *resource,
  uint32_t stride, uint32_t format)
 {
 switch (format) {
+case WL_DRM_FORMAT_ARGB2101010:
+case WL_DRM_FORMAT_XRGB2101010:
 case WL_DRM_FORMAT_ARGB:
 case WL_DRM_FORMAT_XRGB:
 case WL_DRM_FORMAT_YUYV:
@@ -209,6 +211,10 @@ bind_drm(struct wl_client *client, void *data, uint32_t 
version, uint32_t id)
 
wl_resource_post_event(resource, WL_DRM_DEVICE, drm->device_name);
wl_resource_post_event(resource, WL_DRM_FORMAT,
+

[Mesa-dev] [PATCH 18/22] st/dri2: Add buffer handling for BGR[A/X]1010102 formats.

2017-12-15 Thread Mario Kleiner 
Signed-off-by: Mario Kleiner 
Reviewed-by: Marek Olšák 
---
 src/gallium/state_trackers/dri/dri2.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/gallium/state_trackers/dri/dri2.c 
b/src/gallium/state_trackers/dri/dri2.c
index f7fd08d..e3b9377 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -398,10 +398,14 @@ dri2_drawable_get_buffers(struct dri_drawable *drawable,
* may occur as the stvis->color_format.
*/
   switch(format) {
+  case PIPE_FORMAT_B10G10R10A2_UNORM:
   case PIPE_FORMAT_BGRA_UNORM:
   case PIPE_FORMAT_RGBA_UNORM:
 depth = 32;
 break;
+  case PIPE_FORMAT_B10G10R10X2_UNORM:
+ depth = 30;
+ break;
   case PIPE_FORMAT_BGRX_UNORM:
   case PIPE_FORMAT_RGBX_UNORM:
 depth = 24;
@@ -485,6 +489,12 @@ dri_image_drawable_get_buffers(struct dri_drawable 
*drawable,
   case PIPE_FORMAT_RGBA_UNORM:
  image_format = __DRI_IMAGE_FORMAT_ABGR;
  break;
+  case PIPE_FORMAT_B10G10R10X2_UNORM:
+ image_format = __DRI_IMAGE_FORMAT_XRGB2101010;
+ break;
+  case PIPE_FORMAT_B10G10R10A2_UNORM:
+ image_format = __DRI_IMAGE_FORMAT_ARGB2101010;
+ break;
   default:
  image_format = __DRI_IMAGE_FORMAT_NONE;
  break;
@@ -531,6 +541,9 @@ dri2_allocate_buffer(__DRIscreen *sPriv,
   case 32:
  pf = PIPE_FORMAT_BGRA_UNORM;
  break;
+  case 30:
+ pf = PIPE_FORMAT_B10G10R10X2_UNORM;
+ break;
   case 24:
  pf = PIPE_FORMAT_BGRX_UNORM;
  break;
-- 
2.7.4

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[Mesa-dev] [PATCH 15/22] egl/wayland: Add Wayland shm swrast support for RGB10 winsys buffers.

2017-12-15 Thread Mario Kleiner 
Signed-off-by: Mario Kleiner 
Reviewed-by: Marek Olšák 
---
 src/egl/drivers/dri2/platform_wayland.c | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 7451027..4a0b8c2 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -162,10 +162,14 @@ dri2_wl_create_window_surface(_EGLDriver *drv, 
_EGLDisplay *disp,
   assert(dri2_dpy->wl_shm);
   if (conf->RedSize == 5)
  dri2_surf->format = WL_SHM_FORMAT_RGB565;
-  else if (conf->AlphaSize == 0)
+  else if (conf->RedSize == 8 && conf->AlphaSize == 0)
  dri2_surf->format = WL_SHM_FORMAT_XRGB;
-  else
+  else if (conf->RedSize == 8)
  dri2_surf->format = WL_SHM_FORMAT_ARGB;
+  else if (conf->RedSize == 10 && conf->AlphaSize == 0)
+ dri2_surf->format = WL_SHM_FORMAT_XRGB2101010;
+  else if (conf->RedSize == 10)
+ dri2_surf->format = WL_SHM_FORMAT_ARGB2101010;
}
 
dri2_surf->wl_queue = wl_display_create_queue(dri2_dpy->wl_dpy);
@@ -1469,7 +1473,7 @@ dri2_wl_swrast_get_stride_for_format(int format, int w)
 {
if (format == WL_SHM_FORMAT_RGB565)
   return 2 * w;
-   else /* ARGB || XRGB */
+   else /* ARGB || XRGB || ARGB2101010 || XRGB2101010 */
   return 4 * w;
 }
 
@@ -1894,6 +1898,12 @@ shm_handle_format(void *data, struct wl_shm *shm, 
uint32_t format)
struct dri2_egl_display *dri2_dpy = data;
 
switch (format) {
+   case WL_SHM_FORMAT_ARGB2101010:
+  dri2_dpy->formats |= HAS_ARGB2101010;
+  break;
+   case WL_SHM_FORMAT_XRGB2101010:
+  dri2_dpy->formats |= HAS_XRGB2101010;
+  break;
case WL_SHM_FORMAT_ARGB:
   dri2_dpy->formats |= HAS_ARGB;
   break;
-- 
2.7.4

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[Mesa-dev] [PATCH 14/22] egl/wayland: Add Wayland dmabuf support for RGB10 winsys buffers. (v2)

2017-12-15 Thread Mario Kleiner 
Successfully tested under Weston 3.0.
Photometer confirms 10 rgb bits from rendering to display.

v2: Rebased onto master for dri2_teardown_wayland().

Signed-off-by: Mario Kleiner 
Reviewed-by: Marek Olšák 
---
 src/egl/drivers/dri2/egl_dri2.h |  2 ++
 src/egl/drivers/dri2/platform_wayland.c | 18 +-
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index ef375b6..cc76c73 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -212,6 +212,8 @@ struct dri2_egl_display
struct wl_event_queue*wl_queue;
struct zwp_linux_dmabuf_v1 *wl_dmabuf;
struct {
+  struct u_vectorxrgb2101010;
+  struct u_vectorargb2101010;
   struct u_vectorxrgb;
   struct u_vectorargb;
   struct u_vectorrgb565;
diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 3633c83..7451027 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -354,9 +354,13 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
switch (dri2_surf->format) {
case WL_DRM_FORMAT_ARGB2101010:
   dri_image_format = __DRI_IMAGE_FORMAT_ARGB2101010;
+  modifiers = u_vector_tail(_dpy->wl_modifiers.argb2101010);
+  num_modifiers = u_vector_length(_dpy->wl_modifiers.argb2101010);
   break;
case WL_DRM_FORMAT_XRGB2101010:
   dri_image_format = __DRI_IMAGE_FORMAT_XRGB2101010;
+  modifiers = u_vector_tail(_dpy->wl_modifiers.xrgb2101010);
+  num_modifiers = u_vector_length(_dpy->wl_modifiers.xrgb2101010);
   break;
case WL_DRM_FORMAT_ARGB:
   dri_image_format = __DRI_IMAGE_FORMAT_ARGB;
@@ -1143,6 +1147,14 @@ dmabuf_handle_modifier(void *data, struct 
zwp_linux_dmabuf_v1 *dmabuf,
   return;
 
switch (format) {
+   case WL_DRM_FORMAT_ARGB2101010:
+  mod = u_vector_add(_dpy->wl_modifiers.argb2101010);
+  dri2_dpy->formats |= HAS_ARGB2101010;
+  break;
+   case WL_DRM_FORMAT_XRGB2101010:
+  mod = u_vector_add(_dpy->wl_modifiers.xrgb2101010);
+  dri2_dpy->formats |= HAS_XRGB2101010;
+  break;
case WL_DRM_FORMAT_ARGB:
   mod = u_vector_add(_dpy->wl_modifiers.argb);
   dri2_dpy->formats |= HAS_ARGB;
@@ -1314,7 +1326,9 @@ dri2_initialize_wayland_drm(_EGLDriver *drv, _EGLDisplay 
*disp)
   dri2_dpy->wl_dpy = disp->PlatformDisplay;
}
 
-   if (!u_vector_init(_dpy->wl_modifiers.xrgb, sizeof(uint64_t), 32) 
||
+   if (!u_vector_init(_dpy->wl_modifiers.xrgb2101010, sizeof(uint64_t), 
32) ||
+   !u_vector_init(_dpy->wl_modifiers.argb2101010, sizeof(uint64_t), 
32) ||
+   !u_vector_init(_dpy->wl_modifiers.xrgb, sizeof(uint64_t), 32) 
||
!u_vector_init(_dpy->wl_modifiers.argb, sizeof(uint64_t), 32) 
||
!u_vector_init(_dpy->wl_modifiers.rgb565, sizeof(uint64_t), 32)) {
   goto cleanup;
@@ -2055,6 +2069,8 @@ dri2_teardown_wayland(struct dri2_egl_display *dri2_dpy)
   wl_event_queue_destroy(dri2_dpy->wl_queue);
if (dri2_dpy->wl_dpy_wrapper)
   wl_proxy_wrapper_destroy(dri2_dpy->wl_dpy_wrapper);
+   u_vector_finish(_dpy->wl_modifiers.argb2101010);
+   u_vector_finish(_dpy->wl_modifiers.xrgb2101010);
u_vector_finish(_dpy->wl_modifiers.argb);
u_vector_finish(_dpy->wl_modifiers.xrgb);
u_vector_finish(_dpy->wl_modifiers.rgb565);
-- 
2.7.4

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[Mesa-dev] [PATCH 10/22] egl/x11: Match depth 30 RGB visuals to 32-bit RGBA EGLConfigs.

2017-12-15 Thread Mario Kleiner 
Similar to the matching of 24 bit RGB visuals to 32-bit
RGBA EGLConfigs, so X11 compositors won't alpha-blend any
config with a destination alpha buffer during compositing.

Additionally this fixes failure to select ARGB2101010
configs via eglChooseConfig() with EGL_ALPHA_BITS 2 on
a depth 30 X-Screen. The X-Server doesn't provide any
visuals of depth 32 for ARGB2101010 configs, it only
provides depth 30 visuals. Therefore if we'd only match
ARGB2101010 configs to depth 32 RGBA visuals, we would
not ever get a visual for such a config.

This was apparent in piglit tests for egl configs, which
are fixed by this commit.

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
Reviewed-by: Marek Olšák 
---
 src/egl/drivers/dri2/platform_x11.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index 8ede590b..d22b83f 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -782,13 +782,14 @@ dri2_x11_add_configs_for_visuals(struct dri2_egl_display 
*dri2_dpy,
   config_count++;
 
 /* Allow a 24-bit RGB visual to match a 32-bit RGBA EGLConfig.
+ * Ditto for 30-bit RGB visuals to match a 32-bit RGBA EGLConfig.
  * Otherwise it will only match a 32-bit RGBA visual.  On a
  * composited window manager on X11, this will make all of the
  * EGLConfigs with destination alpha get blended by the
  * compositor.  This is probably not what the application
  * wants... especially on drivers that only have 32-bit RGBA
  * EGLConfigs! */
-if (d.data->depth == 24) {
+if (d.data->depth == 24 || d.data->depth == 30) {
rgba_masks[3] =
   ~(rgba_masks[0] | rgba_masks[1] | rgba_masks[2]);
dri2_conf = dri2_add_config(disp, config, config_count + 1,
-- 
2.7.4

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[Mesa-dev] [PATCH 09/22] mesa: Add GL_RGBA + GL_UNSIGNED_INT_2_10_10_10_REV for OES read type.

2017-12-15 Thread Mario Kleiner 
This format + type combo is good for BGRA1010102 framebuffers
for use with glReadPixels() under GLES, so add it for the
GL_IMPLEMENTATION_COLOR_READ_TYPE_OES query.

Allows successful testing of 10 bpc / depth 30 rendering with dEQP test
case dEQP-EGL.functional.wide_color.window_1010102_colorspace_default.

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
Reviewed-by: Marek Olšák 
---
 src/mesa/main/framebuffer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/framebuffer.c b/src/mesa/main/framebuffer.c
index b17d7cb..a0de669 100644
--- a/src/mesa/main/framebuffer.c
+++ b/src/mesa/main/framebuffer.c
@@ -889,6 +889,9 @@ _mesa_get_color_read_type(struct gl_context *ctx,
   if (format == MESA_FORMAT_B5G6R5_UNORM)
  return GL_UNSIGNED_SHORT_5_6_5;
 
+  if (format == MESA_FORMAT_B10G10R10A2_UNORM)
+ return GL_UNSIGNED_INT_2_10_10_10_REV;
+
   switch (data_type) {
   case GL_SIGNED_NORMALIZED:
  return GL_BYTE;
-- 
2.7.4

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[Mesa-dev] [PATCH 08/22] i965/screen: Honor 'allow_rgb10_configs' option. (v2)

2017-12-15 Thread Mario Kleiner 
Allows to prevent exposing RGB10 configs and visuals to
clients.

v2: Rename expose_rgb10_configs to allow_rgb10_configs,
as suggested by Emil.

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 668440a..2ce73f4 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2114,11 +2114,20 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
else
   num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */
 
+   /* Shall we expose 10 bpc formats? */
+   bool allow_rgb10_configs = driQueryOptionb(_screen->optionCache,
+  "allow_rgb10_configs");
+
/* Generate singlesample configs without accumulation buffer. */
for (unsigned i = 0; i < num_formats; i++) {
   __DRIconfig **new_configs;
   int num_depth_stencil_bits = 2;
 
+  if (!allow_rgb10_configs &&
+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+   formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
   /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil
* buffer that has a different number of bits per pixel than the color
* buffer, gen >= 6 supports this.
@@ -2155,6 +2164,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
for (unsigned i = 0; i < num_formats; i++) {
   __DRIconfig **new_configs;
 
+  if (!allow_rgb10_configs &&
+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+  formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
   if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) {
  depth_bits[0] = 16;
  stencil_bits[0] = 0;
@@ -2188,6 +2202,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
   if (devinfo->gen < 6)
  break;
 
+  if (!allow_rgb10_configs &&
+  (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM ||
+  formats[i] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
   __DRIconfig **new_configs;
   const int num_depth_stencil_bits = 2;
   int num_msaa_modes = 0;
-- 
2.7.4

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[Mesa-dev] [PATCH 12/22] egl/x11: Handle depth 30 drawables for EGL_KHR_image_pixmap.

2017-12-15 Thread Mario Kleiner 
Enables eglCreateImageKHR() with target set to
EGL_NATIVE_PIXMAP_KHR to handle color depth 30
X11 drawables.

Note that in theory the drawable depth 32 case in the
current implementation is ambiguous: A depth 32 drawable
could be of format ARGB or ARGB2101010, therefore an
assignment of __DRI_IMAGE_FORMAT_ARGB for a pixmap of
ARGB2101010 format would be wrong. In practice however, the
X-Server (as of v1.19) does not provide any depth 32 visuals
for ARGB2101010 EGL/GLX configs. Those are associated with
depth 30 visuals without an alpha channel instead. Therefore
the switch-case depth 32 branch is only executed for ARGB
pixmaps and we get away with this.

Tested with KDE Plasma 5 under X11, DRI2 and DRI3/Present,
selecting EGL + OpenGL compositing and different fbconfigs
with/without 2 bit alpha channel. glxinfo confirms use of
depth 30 visuals for ARGB2101010 only.

Suggested-by: Eric Engestrom 
Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
Reviewed-by: Marek Olšák 
---
 src/egl/drivers/dri2/platform_x11.c  | 3 +++
 src/egl/drivers/dri2/platform_x11_dri3.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index 4750872..8b701d5 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -1049,6 +1049,9 @@ dri2_create_image_khr_pixmap(_EGLDisplay *disp, 
_EGLContext *ctx,
case 24:
   format = __DRI_IMAGE_FORMAT_XRGB;
   break;
+   case 30:
+  format = __DRI_IMAGE_FORMAT_XRGB2101010;
+  break;
case 32:
   format = __DRI_IMAGE_FORMAT_ARGB;
   break;
diff --git a/src/egl/drivers/dri2/platform_x11_dri3.c 
b/src/egl/drivers/dri2/platform_x11_dri3.c
index eadd371..6e40eaa 100644
--- a/src/egl/drivers/dri2/platform_x11_dri3.c
+++ b/src/egl/drivers/dri2/platform_x11_dri3.c
@@ -269,6 +269,9 @@ dri3_create_image_khr_pixmap(_EGLDisplay *disp, _EGLContext 
*ctx,
case 24:
   format = __DRI_IMAGE_FORMAT_XRGB;
   break;
+   case 30:
+  format = __DRI_IMAGE_FORMAT_XRGB2101010;
+  break;
case 32:
   format = __DRI_IMAGE_FORMAT_ARGB;
   break;
-- 
2.7.4

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[Mesa-dev] [PATCH 11/22] egl/x11: Handle depth 30 drawables under software rasterizer.

2017-12-15 Thread Mario Kleiner 
For fixing eglCreateWindowSurface() under swrast, as tested
with LIBGL_ALWAYS_SOFTWARE=1.

Suggested-by: Eric Engestrom 
Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
Reviewed-by: Marek Olšák 
---
 src/egl/drivers/dri2/platform_x11.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index d22b83f..4750872 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -75,6 +75,7 @@ swrastCreateDrawable(struct dri2_egl_display * dri2_dpy,
xcb_create_gc(dri2_dpy->conn, dri2_surf->swapgc, dri2_surf->drawable, mask, 
valgc);
switch (dri2_surf->depth) {
   case 32:
+  case 30:
   case 24:
  dri2_surf->bytes_per_pixel = 4;
  break;
-- 
2.7.4

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[Mesa-dev] [PATCH 05/22] i965/screen: Add XRGB2101010 and ARGB2101010 support for DRI3.

2017-12-15 Thread Mario Kleiner 
Allow DRI3/Present buffer sharing for 10 bpc buffers.
Otherwise composited desktops under DRI3 will only display
black client areas for redirected windows.

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 50346de..4748987 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -182,6 +182,12 @@ static const struct __DRI2flushExtensionRec 
intelFlushExtension = {
 };
 
 static const struct intel_image_format intel_image_formats[] = {
+   { __DRI_IMAGE_FOURCC_ARGB2101010, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB2101010, 4 } } },
+
+   { __DRI_IMAGE_FOURCC_XRGB2101010, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB2101010, 4 } } },
+
{ __DRI_IMAGE_FOURCC_ARGB, __DRI_IMAGE_COMPONENTS_RGBA, 1,
  { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB, 4 } } },
 
-- 
2.7.4

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[Mesa-dev] [PATCH 07/22] dri/common: Add option to allow exposure of 10 bpc color configs. (v2)

2017-12-15 Thread Mario Kleiner 
Some clients may not like RGB10X2 and RGB10A2 fbconfigs and
visuals. Add a new driconf option 'allow_rgb10_configs' to
allow per application enable/disable.

The option defaults to enabled.

v2: Rename expose_rgb10_configs to allow_rgb10_configs,
as suggested by Emil. Add comment to option parsing,
to make sure it stays before the ->InitScreen().

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
Reviewed-by: Marek Olšák 
---
 src/mesa/drivers/dri/common/dri_util.c | 12 
 src/util/xmlpool/t_options.h   |  5 +
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/common/dri_util.c 
b/src/mesa/drivers/dri/common/dri_util.c
index d504751..d4fba0b 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -55,6 +55,10 @@ const char __dri2ConfigOptions[] =
   DRI_CONF_SECTION_PERFORMANCE
  DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_1)
   DRI_CONF_SECTION_END
+
+  DRI_CONF_SECTION_MISCELLANEOUS
+ DRI_CONF_ALLOW_RGB10_CONFIGS("true")
+  DRI_CONF_SECTION_END
DRI_CONF_END;
 
 /*/
@@ -144,6 +148,10 @@ driCreateNewScreen2(int scrn, int fd,
 psp->fd = fd;
 psp->myNum = scrn;
 
+/* Option parsing before ->InitScreen(), as some options apply there. */
+driParseOptionInfo(>optionInfo, __dri2ConfigOptions);
+driParseConfigFiles(>optionCache, >optionInfo, psp->myNum, 
"dri2");
+
 *driver_configs = psp->driver->InitScreen(psp);
 if (*driver_configs == NULL) {
free(psp);
@@ -179,10 +187,6 @@ driCreateNewScreen2(int scrn, int fd,
 if (psp->max_gl_es2_version >= 30)
psp->api_mask |= (1 << __DRI_API_GLES3);
 
-driParseOptionInfo(>optionInfo, __dri2ConfigOptions);
-driParseConfigFiles(>optionCache, >optionInfo, psp->myNum, 
"dri2");
-
-
 return psp;
 }
 
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index bd55308..5f377c9 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -379,6 +379,11 @@ DRI_CONF_OPT_BEGIN_B(glsl_zero_init, def) \
 DRI_CONF_DESC(en,gettext("Force uninitialized variables to default to 
zero")) \
 DRI_CONF_OPT_END
 
+#define DRI_CONF_ALLOW_RGB10_CONFIGS(def) \
+DRI_CONF_OPT_BEGIN_B(allow_rgb10_configs, def) \
+DRI_CONF_DESC(en,gettext("Allow exposure of visuals and fbconfigs with rgb10a2 
formats")) \
+DRI_CONF_OPT_END
+
 /**
  * \brief Initialization configuration options
  */
-- 
2.7.4

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[Mesa-dev] [PATCH 02/22] i965: Support accelerated blit for depth 30 formats. (v2)

2017-12-15 Thread Mario Kleiner 
Extend intel_miptree_blit() to handle at least
ARGB2101010 -> XRGB2101010, ARGB2101010 -> ARGB2101010,
and XRGB2101010 -> XRGB2101010 via the BLT engine,
but not XRGB2101010 -> ARGB2101010 yet.

This works as tested under Compiz, KDE-5, Gnome-Shell.

v2: Restrict BLT fast path to exclude XRGB2101010 -> ARGB2101010,
as intel_miptree_set_alpha_to_one() isn't ready to set 2 bit
alpha channels to 1.0 yet. However, couldn't find a test case
where this specific blit would be needed, so maybe not much
of a point to improve here.

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
---
 src/mesa/drivers/dri/i965/intel_blit.c | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 5f25bfa..46945b2 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -170,6 +170,19 @@ intel_miptree_blit_compatible_formats(mesa_format src, 
mesa_format dst)
   return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
   dst == MESA_FORMAT_R8G8B8X8_UNORM);
 
+   /* We can also discard alpha when going from A2->X2 for 2 bit alpha,
+* however we can't fill the alpha channel with two 1 bits when going
+* from X2->A2, because intel_miptree_set_alpha_to_one() is not yet
+* ready for this / can only handle 8 bit alpha.
+*/
+   if (src == MESA_FORMAT_B10G10R10A2_UNORM)
+  return (dst == MESA_FORMAT_B10G10R10A2_UNORM ||
+  dst == MESA_FORMAT_B10G10R10X2_UNORM);
+
+   if (src == MESA_FORMAT_R10G10B10A2_UNORM)
+  return (dst == MESA_FORMAT_R10G10B10A2_UNORM ||
+  dst == MESA_FORMAT_R10G10B10X2_UNORM);
+
return false;
 }
 
@@ -322,7 +335,8 @@ intel_miptree_blit(struct brw_context *brw,
/* The blitter doesn't support doing any format conversions.  We do also
 * support blitting ARGB to XRGB (trivial, the values dropped into
 * the X channel don't matter), and XRGB to ARGB by setting the A
-* channel to 1.0 at the end.
+* channel to 1.0 at the end. Also trivially ARGB2101010 to XRGB2101010,
+* but not XRGB2101010 to ARGB2101010 yet.
 */
if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
   perf_debug("%s: Can't use hardware blitter from %s to %s, "
@@ -789,6 +803,10 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
__func__, mt->bo, pitch, x, y, width, height);
 
+   /* Note: Currently only handles 8 bit alpha channel. Extension to < 8 Bit
+* alpha channel would be likely possible via ROP code 0xfa instead of 0xf0
+* and writing a suitable bit-mask instead of 0x.
+*/
BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
CMD = XY_COLOR_BLT_CMD;
CMD |= XY_BLT_WRITE_ALPHA;
-- 
2.7.4

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[Mesa-dev] [PATCH 01/22] i965: Support xrgb/argb2101010 formats for glx_texture_from_pixmap.

2017-12-15 Thread Mario Kleiner 
Makes compositing under X11/GLX work.

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
---
 src/mesa/drivers/dri/i965/intel_tex_image.c | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 37c8e24..2ee3658 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -464,11 +464,19 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
if (rb->mt->cpp == 4) {
   if (texture_format == __DRI_TEXTURE_FORMAT_RGB) {
  internal_format = GL_RGB;
- texFormat = MESA_FORMAT_B8G8R8X8_UNORM;
+ if (rb->mt->format == MESA_FORMAT_B10G10R10X2_UNORM ||
+ rb->mt->format == MESA_FORMAT_B10G10R10A2_UNORM)
+texFormat = MESA_FORMAT_B10G10R10X2_UNORM;
+ else
+texFormat = MESA_FORMAT_B8G8R8X8_UNORM;
   }
   else {
  internal_format = GL_RGBA;
- texFormat = MESA_FORMAT_B8G8R8A8_UNORM;
+ if (rb->mt->format == MESA_FORMAT_B10G10R10X2_UNORM ||
+ rb->mt->format == MESA_FORMAT_B10G10R10A2_UNORM)
+texFormat = MESA_FORMAT_B10G10R10A2_UNORM;
+ else
+texFormat = MESA_FORMAT_B8G8R8A8_UNORM;
   }
} else if (rb->mt->cpp == 2) {
   internal_format = GL_RGB;
-- 
2.7.4

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[Mesa-dev] [PATCH 03/22] dri: Add 10 bpc formats as available formats. (v2)

2017-12-15 Thread Mario Kleiner 
Used to support ARGB2101010 and XRGB2101010
winsys framebuffers / drawables, but added
other 10 bpc fourcc's as well for consistency
with definitions in wayland_drm.h, gbm.h, and
drm_fourcc.h.

v2: Align new defines with tabs instead of spaces, for
consistency with remainder of that block of definitions,
as suggested by Tapani.

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
Reviewed-by: Marek Olšák 
---
 include/GL/internal/dri_interface.h | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/include/GL/internal/dri_interface.h 
b/include/GL/internal/dri_interface.h
index b479473..0fdabc7 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1261,7 +1261,15 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FOURCC_XRGB0x34325258
 #define __DRI_IMAGE_FOURCC_ABGR0x34324241
 #define __DRI_IMAGE_FOURCC_XBGR0x34324258
-#define __DRI_IMAGE_FOURCC_SARGB0x83324258
+#define __DRI_IMAGE_FOURCC_SARGB   0x83324258
+#define __DRI_IMAGE_FOURCC_ARGB2101010 0x30335241
+#define __DRI_IMAGE_FOURCC_XRGB2101010 0x30335258
+#define __DRI_IMAGE_FOURCC_ABGR2101010 0x30334241
+#define __DRI_IMAGE_FOURCC_XBGR2101010 0x30334258
+#define __DRI_IMAGE_FOURCC_RGBA1010102 0x30334152
+#define __DRI_IMAGE_FOURCC_RGBX1010102 0x30335852
+#define __DRI_IMAGE_FOURCC_BGRA1010102 0x30334142
+#define __DRI_IMAGE_FOURCC_BGRX1010102 0x30335842
 #define __DRI_IMAGE_FOURCC_YUV410  0x39565559
 #define __DRI_IMAGE_FOURCC_YUV411  0x31315559
 #define __DRI_IMAGE_FOURCC_YUV420  0x32315559
-- 
2.7.4

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[Mesa-dev] [PATCH 04/22] loader/dri3: Add XRGB2101010 and ARGB2101010 support.

2017-12-15 Thread Mario Kleiner 
To allow DRI3/Present buffer sharing for 10 bpc buffers.

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
Reviewed-by: Marek Olšák 
---
 src/loader/loader_dri3_helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index 7e6b8b2..cc890bc 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -1018,6 +1018,8 @@ image_format_to_fourcc(int format)
case __DRI_IMAGE_FORMAT_ARGB: return __DRI_IMAGE_FOURCC_ARGB;
case __DRI_IMAGE_FORMAT_ABGR: return __DRI_IMAGE_FOURCC_ABGR;
case __DRI_IMAGE_FORMAT_XBGR: return __DRI_IMAGE_FOURCC_XBGR;
+   case __DRI_IMAGE_FORMAT_XRGB2101010: return __DRI_IMAGE_FOURCC_XRGB2101010;
+   case __DRI_IMAGE_FORMAT_ARGB2101010: return __DRI_IMAGE_FOURCC_ARGB2101010;
}
return 0;
 }
-- 
2.7.4

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[Mesa-dev] Mesa 30 bit color depth patches, rev 4.

2017-12-15 Thread Mario Kleiner 
This is mostly the same as the last series rev 3, with the following
changes:

1. Rebased onto current master, some trivial merge conflict resolved.

2. R-b's of Tapani and Marek tacked onto all patches. Only the new
   patch 22/22 is new and unreviewed.

3. Following Tapani's suggestion i moved old patch 1 to patch 6, so
   the enable for i965 30 bit formats is done after the basic dri and
   i965 bits are in place. This is more consistent with flipping the
   on-switch on gallium.

4. Added patch 22/22, so OES read type queries for glReadPixels also
   handle B10G10R10X2, not only B10G10R10A2, following Marek's advice.
   I've tested this by quickly hacking up the
   dEQP-EGL.functional.wide_color.window_1010102_colorspace_default
   test to ask for zero alpha bits, verifying via apitrace it gets
   a X2R10G10B10 format and that the precision test fails in the
   expected way, ie. with a constant alpha == 3 ( ~ 1.0f) returned
   from a fb that doesn't have an alpha channel when reading via
   glReadPixels(GL_RGBA, GL_UNSIGNED_INT_10_10_10_2_REV).

5. Finally i've dropped the nouveau patch which added a hacky
   B10G10R10X2 pixel format for visuals, which isn't actually
   supported by the driver or NVidia hardware.

   This means that depth 30 display on NVidia hardware won't work
   atm., but that needs more work on nouveau-ddx and nouveau-kms
   anyway to get it working properly.

   Prime renderoffload from a Intel or AMD display gpu to a NVidia
   gpu works, as tested on Wayland+Weston and X11, so there's some
   use to the current nouveau gallium support for depth 30.

So this one should be probably good to push after checking patch
22/22.

Thanks,
-mario

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[Mesa-dev] [PATCH 06/22] i965/screen: Add basic support for rendering 10 bpc/depth 30 framebuffers. (v3)

2017-12-15 Thread Mario Kleiner 
Expose formats which are supported at least back to Gen 5 Ironlake,
possibly further. Allow creation of 10 bpc winsys buffers for drawables.

glxinfo now lists new RGBA 10 10 10 2/0 formats.

v2: Move the BGRA/BGRX1010102 formats before the RGBA/RGBX
32 bit formats, as the code comments require. Thanks Emil!
Update num_formats from 3 to 5, to keep the special Android
handling intact.

v3: Use num_formats = ARRAY_SIZE(formats) - 2 as suggested by Tapani,
to only exclude the last 2 Android formats, add Tapani's r-b.

Signed-off-by: Mario Kleiner 
Reviewed-by: Tapani Pälli 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 4748987..668440a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1653,7 +1653,13 @@ intelCreateBuffer(__DRIscreen *dri_screen,
   fb->Visual.samples = num_samples;
}
 
-   if (mesaVis->redBits == 5) {
+   if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) {
+  rgbFormat = mesaVis->redMask == 0x3ff0 ? 
MESA_FORMAT_B10G10R10A2_UNORM
+ : 
MESA_FORMAT_R10G10B10A2_UNORM;
+   } else if (mesaVis->redBits == 10) {
+  rgbFormat = mesaVis->redMask == 0x3ff0 ? 
MESA_FORMAT_B10G10R10X2_UNORM
+ : 
MESA_FORMAT_R10G10B10X2_UNORM;
+   } else if (mesaVis->redBits == 5) {
   rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM
: MESA_FORMAT_B5G6R5_UNORM;
} else if (mesaVis->sRGBCapable) {
@@ -2063,6 +2069,10 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
 
   MESA_FORMAT_B8G8R8A8_SRGB,
 
+  /* For 10 bpc, 30 bit depth framebuffers. */
+  MESA_FORMAT_B10G10R10A2_UNORM,
+  MESA_FORMAT_B10G10R10X2_UNORM,
+
   /* The 32-bit RGBA format must not precede the 32-bit BGRA format.
* Likewise for RGBX and BGRX.  Otherwise, the GLX client and the GLX
* server may disagree on which format the GLXFBConfig represents,
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

2017-12-15 Thread Chris Wilson 
Quoting Jason Ekstrand (2017-12-15 17:38:10)
> On Fri, Dec 15, 2017 at 8:27 AM, Chris Wilson  
> wrote:
> 
> Quoting Jason Ekstrand (2017-12-15 16:21:42)
> > On Fri, Dec 15, 2017 at 5:42 AM, Chris Wilson 
> wrote:
> >
> >     Every client (everyone instance that opens /dev/dri/card0 or the
> render
> >     nodes), receives a unique per-process GTT (where supported by the
> >     hardware, unfortunately that means only Broadwell and later). Every
> >     context created by each client, in turns receives its own unique
> ppGTT.
> >     This is overkill in terms of allocations and tracking, both in the
> >     kernel and in the hardware, as we could be sharing the per-client 
> GTT
> >     amongst all of its contexts. The downside is that context 
> segregation
> is
> >     reduced, a stray write from one context may affect another, and so 
> we
> >     must honour any client requests that require robust segregation 
> (e.g.
> >     ARB_robustness).
> >
> >     Signed-off-by: Chris Wilson 
> >     ---
> >      src/mesa/drivers/dri/i965/brw_bufmgr.c  | 23 
> +--
> >      src/mesa/drivers/dri/i965/brw_bufmgr.h  |  2 +-
> >      src/mesa/drivers/dri/i965/brw_context.c |  2 +-
> >      3 files changed, 19 insertions(+), 8 deletions(-)
> >
> >     diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/
> drivers/dri/
> >     i965/brw_bufmgr.c
> >     index 52b5bf97a1..d8a9635f5d 100644
> >     --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> >     +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> >     @@ -1297,13 +1297,24 @@ init_cache_buckets(struct brw_bufmgr 
> *bufmgr)
> >      }
> >
> >      uint32_t
> >     -brw_create_hw_context(struct brw_bufmgr *bufmgr)
> >     +brw_create_hw_context(struct brw_bufmgr *bufmgr, unsigned int 
> flags)
> >      {
> >     -   struct drm_i915_gem_context_create create = { };
> >     -   int ret = drmIoctl(bufmgr->fd, 
> DRM_IOCTL_I915_GEM_CONTEXT_CREATE,
> &
> >     create);
> >     -   if (ret != 0) {
> >     -      DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", 
> strerror
> >     (errno));
> >     -      return 0;
> >     +   struct local_i915_gem_context_create_v2 {
> >     +      uint32_t ctx_id; /* out */
> >     +      uint32_t flags;
> >     +#define I915_GEM_CONTEXT_SHARE_GTT 0x1
> >     +      uint32_t share_ctx;
> >
> >
> > So, we've left share_ctx as 0.  What does that mean?  Does that mean 
> that
> we
> > share with some context that was implicitly created by opening /dev/dri/
> card0? 
> > Does it mean we share with the default context and therefore other
> processes? 
> 
> The default context, 0, is per fd.
> 
> So a second open() of /dev/dri/card0 will get a different default context?

Yes. But dup() retains the same, as does passing the fd over a unix
socket. At least, you have to actively circumvent the segregation.
-Chris
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Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

2017-12-15 Thread Dylan Baker 
Quoting Gert Wollny (2017-12-15 11:30:07)
> Am Freitag, den 15.12.2017, 18:49 +0100 schrieb Gert Wollny:
> > Am Freitag, den 15.12.2017, 17:17 +0100 schrieb Juan A. Suarez
> > Romero:
> > > Travis CI has moved to LLVM 5.0, and meson is detecting
> > > automatically
> > > the available version.
> > 
> > Considering that LLVM 5.0 is obviously not properly made available in
> > the travis-ci environment, I've reported the problem with travis-
> > upstream: 
> > 
> > https://github.com/travis-ci/travis-ci/issues/8925
> 
> Actually, I was wrong: meson 0.44 explicitly searches for the dynamic
> library that is not available in the installation which comes straight
> from the LLVM.org provided tarball, so it's not travis fault. 
> 
> It seems meson is using an old library dectection method where it
> should use the new one (reported [1])
> 
> Best, 
> Gert 
> 
> [1] https://github.com/mesonbuild/meson/issues/2786

Gah, TravisCI doing something different than everyone else, sigh.

I've submitted a pull request to fix this.


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Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

2017-12-15 Thread Nicolai Hähnle 

On 15.12.2017 12:37, Rob Clark wrote:

On Fri, Dec 15, 2017 at 4:41 AM, Nicolai Hähnle  wrote:

On 15.12.2017 00:56, Rob Clark wrote:


On Wed, Dec 6, 2017 at 3:31 PM, Ian Romanick  wrote:


On 12/05/2017 08:25 AM, Ilia Mirkin wrote:


On Tue, Dec 5, 2017 at 8:18 AM, Emil Velikov 
wrote:


Hi Rob,

On 5 December 2017 at 12:54, Rob Clark  wrote:


This is a bit sad/annoying.  But with current GPU firmware (at least
on
a5xx) we can support both draw-indirect and base-instance.  But we
can't
support draw-indirect with a non-zero base-instance specified.  So add
a
driconf option to hide the extension from games that are known to use
both.

Signed-off-by: Rob Clark 
---
Tbh, I'm also not really sure what to do when/if we got updated
firmware
which handled draw-indirect with base-instance, since we'd need to
make
this option conditional on fw version.  For STK that probably isn't a
big deal since it doesn't use draw-indirect in a particularly useful
way
(the indirect buffer is generated on CPU).


Couldn't freedreno just return 0 for PIPE_CAP_DRAW_INDIRECT (aka
disable the extension) as it detects buggy FW?
This is what radeons have been doing as they encounter iffy firmware or
LLVM.

AFAICT freedreno doesn't do GL 4.0 or GLES 3.1 so one should be safe.



Rob is this -><- close to ES 3.1, so that's not a great option.



And I don't suppose there's a way to get updated firmware?  i965 has
similar sorts of cases where higher versions are disabled due to missing
kernel features.



so after r/e the instruction set for the CP microcontrollers and
writing a disassembler and assembler[1], and figuring out how the fw
handles CP_DRAW_INDIRECT and CP_DRAW_INDX_INDIRECT packets, I've come
to the conclusion that the issue isn't actually with draw-indirect vs
base-instance (at least not w/ the fw from my pixel2 which md5sum
claims is the same as what is in linux-firmware.. it is possible that
I was using an earlier version of the fw before when I came to this
conclusion).  On the plus side, the PFP/ME microcontrollers that parse
the cmdstream are pretty neat and I learned some useful stuff along
the way.

But thinking a bit about how stk is using GL_MAP_PERSISTENT_BIT to map
and update the draw-indirect buffers, it seems to me there are plenty
of ways this can go wrong w/ tilers (and even more when you throw
re-ordering into the mix).  Possibly I should disable reordering when
the indirect buffer is mapped w/ PERSISTENT bit, although for games
like stk this is probably counter-productive vs just hiding the
draw-indirect extension.. for games that actually use the GPU to write
the draw-indirect buffer it shouldn't be a problem.  So I think a
driconf patch like this probably still ends up being useful in the
end.



Can you detail a bit what you think could go wrong? I believe that the
intention of the GL spec is that reordering in tilers should be possible at
least for buffers that are mapped PERSISTENT but not COHERENT.

You may only have to block reordering if the buffer is mapped both
PERSISTENT *and* COHERENT -- and even then, reordering is probably possible.

Granted, the spec is unclear as usual when it comes to these memory
synchronization issues -- the description of the MAP_COHERENT_BIT in section
6.2 does not mention WAR hazards (in particular, Write by client after Read
by server) -- but perhaps that can be fixed.

To go into a bit more detail, what I suspect you're worried about is
applications doing stuff like:

1. Write to indirect buffer (persistently & coherently mapped)
2. Draw*Indirect
3. Write to the same location in the indirect buffer
4. Draw*Indirect

... but this is bound to fail with "normal" GPUs (like ours) as well.
Perhaps you have a different scenario in mind?


yeah, this was basically the scenario I had in mind.. although I'm
perhaps more aggressive in deferring rendering, to the point of
re-ordering draws if unnecessary fbo switches are made.  Normally I
track which buffers are read and written in a given batch (draw pass)
in order to preserve correctness (and in some cases shadowing or doing
a staging transfer to update buffers/textures to avoid splitting a
batch).  Perhaps it is only an issue w/ persistent+coherent, but w/
cpu updating buffer without driver knowing when is kind of
sub-optimal.

I'm thinking I do need to keep track when there are outstanding
coherent+persistent transfers mapped and switch off some of the
cleverness.


I'm not convinced that this is actually necessary. You probably only 
need to break for things like glFlushMappedBufferRange() and glFenceSync().


The reasoning is basically this: unless one of those synchronizing 
commands is used, every desktop GPU will effectively re-order a sequence of:


1. Write #1 to persistent-mapped buffer
2. Draw #1
3. Write #2 to persistent-mapped buffer
4. Draw #2

to:

1. Write #1 to persistent-mapped buffer
2.

Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

2017-12-15 Thread Gert Wollny 
Am Freitag, den 15.12.2017, 18:49 +0100 schrieb Gert Wollny:
> Am Freitag, den 15.12.2017, 17:17 +0100 schrieb Juan A. Suarez
> Romero:
> > Travis CI has moved to LLVM 5.0, and meson is detecting
> > automatically
> > the available version.
> 
> Considering that LLVM 5.0 is obviously not properly made available in
> the travis-ci environment, I've reported the problem with travis-
> upstream: 
> 
> https://github.com/travis-ci/travis-ci/issues/8925

Actually, I was wrong: meson 0.44 explicitly searches for the dynamic
library that is not available in the installation which comes straight
from the LLVM.org provided tarball, so it's not travis fault. 

It seems meson is using an old library dectection method where it
should use the new one (reported [1])

Best, 
Gert 

[1] https://github.com/mesonbuild/meson/issues/2786

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Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

2017-12-15 Thread Dylan Baker 
Quoting Emil Velikov (2017-12-15 09:35:03)
> 
> Not to mention that distributions (Debian for example) allow multiple
> versions to coexist, naming the binary - llvm-config-$version.
> 

Just to add information, meson will try (with 0.44.0):
llvm-config, reversed(llvm-config-${3.5-5.0}), reversed(llvm-config${35-50}),
llvm-config-6.0, llvm-config-devel in that order

with 0.43.0 and 0.42.x:
llvm-config, reversed(llvm-config-${3.5-4.0}), reversed(llvm-config${35-40}),
llvm-config-5.0, llvm-config-devel in that order

Which should cover Debian derivatives and FreeBSD, at least thats what the
Debian and FreeBSD guys who added those patches said :)

Dylan


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Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

2017-12-15 Thread Dylan Baker 
Quoting Emil Velikov (2017-12-15 09:35:03)
> On 15 December 2017 at 16:49, Eric Engestrom  
> wrote:
> > On Friday, 2017-12-15 17:17:55 +0100, Juan A. Suarez Romero wrote:
> >> Travis CI has moved to LLVM 5.0, and meson is detecting automatically
> >> the available version.
> >>
> >> So just let's change to LLVM 5.0 for this case.
> >
> > I thought we were using 3.9 on purpose, to test our minimum required
> > llvm version?
> >
> > I think the proper fix would be to add a `-D llvm-version=3.9` option
> > and use that in the dependency() check.
> >
> Allow me to suggest and alternative solution:
> 
> Feed in the llvm-config name (aka LLVM_CONFIG) like we do for scons
> and autotools.
> It will provide some nice consistency, plus it will allow for easier
> selection as path and version.
> 
> Not to mention that distributions (Debian for example) allow multiple
> versions to coexist, naming the binary - llvm-config-$version.
> 
> -Emil

I don't object to that solution, but it would require a change to upstream
meson, which currently doesn't have support for passing an explicit binary to
the dependency call. It would/will take some time for that to move through
review and would not be available until 0.45.0 at the earliest. Since 0.44.0
was released less than a week ago I would not expect 0.45 until mid January at
the earliest.

I think the easiest immediate solution would be to set the path environment
variable to not include /usr/local, or to use a symlink to mask the version in
/usr/local with the version that we want to use.


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[Mesa-dev] [PATCH v3 4/4] meson: set opencl flags for r600

2017-12-15 Thread Dylan Baker 
Signed-off-by: Dylan Baker 
---
 src/gallium/drivers/r600/meson.build | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/meson.build 
b/src/gallium/drivers/r600/meson.build
index 2132dbb33ad..5899518a2e8 100644
--- a/src/gallium/drivers/r600/meson.build
+++ b/src/gallium/drivers/r600/meson.build
@@ -113,12 +113,15 @@ egd_tables_h = custom_target(
   capture : true,
 )
 
-# TODO: compute defines
+r600_c_args = []
+if with_gallium_opencl
+  r600_c_args += '-DHAVE_OPENCL'
+endif
 
 libr600 = static_library(
   'r600',
   [files_r600, egd_tables_h],
-  c_args : [c_vis_args],
+  c_args : [c_vis_args, r600_c_args],
   cpp_args : [cpp_vis_args],
   include_directories : [
 inc_src, inc_include, inc_gallium, inc_gallium_aux, inc_amd_common,
-- 
2.15.1

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[Mesa-dev] [PATCH v3 1/4] meson: Build SWR driver

2017-12-15 Thread Dylan Baker 
This enables the SWR driver, but doesn't actually hook it up to any of
the targets yet. I felt like this patch was big and complicated enough
without adding that.

v2: - Fix typo 'delemeited' -> 'delimited' (Eric E)
- Fix type 'errror' -> 'error' (Eric E)
- Use variables to hold files instead of looking above the current
  meson build (Eric E)
- Use foreach loops to reduce the number of unique generators
- Add comment about why some generators have names and some are just
  added to a list
v3: - Remove trailing whitespace

Signed-off-by: Dylan Baker 
---
 meson.build|  12 +-
 meson_options.txt  |   6 +
 src/gallium/drivers/swr/meson.build| 289 +
 .../drivers/swr/rasterizer/codegen/meson.build | 158 +++
 src/gallium/meson.build|   8 +
 5 files changed, 467 insertions(+), 6 deletions(-)
 create mode 100644 src/gallium/drivers/swr/meson.build
 create mode 100644 src/gallium/drivers/swr/rasterizer/codegen/meson.build

diff --git a/meson.build b/meson.build
index 6e5ae4d24e9..842d441199e 100644
--- a/meson.build
+++ b/meson.build
@@ -47,6 +47,7 @@ with_valgrind = get_option('valgrind')
 with_libunwind = get_option('libunwind')
 with_asm = get_option('asm')
 with_osmesa = get_option('osmesa')
+with_swr_arches = get_option('swr-arches').split(',')
 if get_option('texture-float')
   pre_args += '-DTEXTURE_FLOAT_ENABLED'
   message('WARNING: Floating-point texture enabled. Please consult 
docs/patents.txt and your lawyer before building mesa.')
@@ -155,6 +156,7 @@ if _drivers != ''
   with_gallium_i915 = _split.contains('i915')
   with_gallium_svga = _split.contains('svga')
   with_gallium_virgl = _split.contains('virgl')
+  with_gallium_swr = _split.contains('swr')
   with_gallium = true
 endif
 
@@ -181,7 +183,7 @@ if _vulkan_drivers != ''
   with_any_vk = with_amd_vk or with_intel_vk
 endif
 
-if with_dri_swrast and with_gallium_softpipe
+if with_dri_swrast and (with_gallium_softpipe or with_gallium_swr)
   error('Only one swrast provider can be built')
 endif
 if with_dri_i915 and with_gallium_i915
@@ -975,7 +977,7 @@ _llvm = get_option('llvm')
 if _llvm == 'auto'
   dep_llvm = dependency(
 'llvm', version : '>= 3.9.0', modules : llvm_modules,
-required : with_amd_vk or with_gallium_radeonsi,
+required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr,
   )
   with_llvm = dep_llvm.found()
 elif _llvm == 'true'
@@ -997,8 +999,8 @@ if with_llvm
 '-DHAVE_LLVM=0x0@0@@1@@2@'.format(_llvm_version[0], _llvm_version[1], 
_llvm_patch),
 '-DMESA_LLVM_VERSION_PATCH=@0@'.format(_llvm_patch),
   ]
-elif with_amd_vk or with_gallium_radeonsi
-  error('The following drivers requires LLVM: Radv, RadeonSI. One of these is 
enabled, but LLVM is disabled.')
+elif with_amd_vk or with_gallium_radeonsi or with_gallium_swr
+  error('The following drivers requires LLVM: Radv, RadeonSI, SWR. One of 
these is enabled, but LLVM is disabled.')
 endif
 
 dep_glvnd = []
@@ -1158,8 +1160,6 @@ endif
 
 # TODO: various libdirs
 
-# TODO: swr
-
 # TODO: gallium driver dirs
 
 # FIXME: this is a workaround for #2326
diff --git a/meson_options.txt b/meson_options.txt
index 39b137cbeaf..4f4db5b7d26 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -261,3 +261,9 @@ option(
   choices : ['8', '16', '32'],
   description : 'Number of channel bits for OSMesa.'
 )
+option(
+  'swr-arches',
+  type : 'string',
+  value : 'avx,avx2',
+  description : 'Comma delemited swr architectures. choices : avx,avx2,knl,skx'
+)
diff --git a/src/gallium/drivers/swr/meson.build 
b/src/gallium/drivers/swr/meson.build
new file mode 100644
index 000..c8c69b096a6
--- /dev/null
+++ b/src/gallium/drivers/swr/meson.build
@@ -0,0 +1,289 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+

[Mesa-dev] [PATCH v3 2/4] meson: Turn on swr for relevant targets

2017-12-15 Thread Dylan Baker 
Currently that's dri, libgl-xlib, and osmesa.

v2: - put drivers on a separate line from normal dependencies (Eric E)

cc: George Kyriazis 
cc: Tim Rowley 
cc: Bruce Cherniak 
Signed-off-by: Dylan Baker 
Reviewed-by: Eric Engestrom 
---

George, Tim, and Bruce,

I don't know if you guys have any time or desire to test this or the previous
patch, it currently only works on Linux, but windows support will be coming
afterwards.

 src/gallium/meson.build| 1 -
 src/gallium/targets/dri/meson.build| 4 ++--
 src/gallium/targets/libgl-xlib/meson.build | 4 ++--
 src/gallium/targets/osmesa/meson.build | 5 ++---
 4 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 3e2fd095710..fc21dcf03e1 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -145,7 +145,6 @@ endif
 if with_gallium_st_nine
   subdir('state_trackers/nine')
 endif
-# TODO: SWR
 # TODO: clover
 if with_dri
   subdir('state_trackers/dri')
diff --git a/src/gallium/targets/dri/meson.build 
b/src/gallium/targets/dri/meson.build
index 5ca7b015d91..edf8d67fe39 100644
--- a/src/gallium/targets/dri/meson.build
+++ b/src/gallium/targets/dri/meson.build
@@ -69,7 +69,7 @@ libgallium_dri = shared_library(
 dep_selinux, dep_expat, dep_libdrm, dep_llvm, dep_lmsensors, dep_thread,
 driver_swrast, driver_r300, driver_r600, driver_radeonsi, driver_nouveau,
 driver_pl111, driver_vc4, driver_vc5, driver_freedreno, driver_etnaviv,
-driver_imx, driver_i915, driver_svga, driver_virgl,
+driver_imx, driver_i915, driver_svga, driver_virgl, driver_swr,
   ],
 )
 
@@ -77,7 +77,7 @@ foreach d : [[with_gallium_pl111, 'pl111_dri.so'],
  [with_gallium_radeonsi, 'radeonsi_dri.so'],
  [with_gallium_nouveau, 'nouveau_dri.so'],
  [with_gallium_freedreno, ['msm_dri.so', 'kgsl_dri.so']],
- [with_gallium_softpipe, 'swrast_dri.so'],
+ [with_gallium_softpipe or with_gallium_swr, 'swrast_dri.so'],
  [with_gallium_softpipe and with_gallium_drisw_kms, 
'kms_swrast_dri.so'],
  [with_gallium_vc4, 'vc4_dri.so'],
  [with_gallium_vc5, 'vc5_dri.so'],
diff --git a/src/gallium/targets/libgl-xlib/meson.build 
b/src/gallium/targets/libgl-xlib/meson.build
index c413a25bd66..6c8d2b4bc0e 100644
--- a/src/gallium/targets/libgl-xlib/meson.build
+++ b/src/gallium/targets/libgl-xlib/meson.build
@@ -38,7 +38,6 @@ endif
 if with_shared_glapi
   gallium_xlib_link_with += libglapi
 endif
-# TODO: SWR
 
 libgl = shared_library(
   'GL',
@@ -55,7 +54,8 @@ libgl = shared_library(
 libgallium, libmesa_util, libmesa_gallium, gallium_xlib_link_with,
   ],
   dependencies : [
-dep_thread, dep_clock, dep_unwind, dep_lmsensors, driver_swrast,
+dep_thread, dep_clock, dep_unwind, dep_lmsensors,
+driver_swrast, driver_swr,
   ],
   install : true,
   version : '1.5.0',
diff --git a/src/gallium/targets/osmesa/meson.build 
b/src/gallium/targets/osmesa/meson.build
index cbf0e3d096a..e51c54f8bc4 100644
--- a/src/gallium/targets/osmesa/meson.build
+++ b/src/gallium/targets/osmesa/meson.build
@@ -32,8 +32,6 @@ if with_ld_version_script
   osmesa_link_deps += files('osmesa.sym')
 endif
 
-# TODO: swr
-
 libosmesa = shared_library(
   osmesa_lib_name,
   'target.c',
@@ -51,7 +49,8 @@ libosmesa = shared_library(
 osmesa_link_with,
   ],
   dependencies : [
-dep_selinux, dep_thread, dep_clock, dep_unwind, driver_swrast,
+dep_selinux, dep_thread, dep_clock, dep_unwind,
+driver_swrast, driver_swr,
   ],
   version : '8.0.0',
   install : true,
-- 
2.15.1

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[Mesa-dev] [PATCH v3 3/4] meson: build clover

2017-12-15 Thread Dylan Baker 
This has only been compile tested.

v2: - Have a single option for opencl (Eric E)
- fix typo "tgis" -> "tgsi" (Curro)
- Don't add "lib" to pipe loader libraries, which matches the
  autotools behavior
v3: - Remove trailing whitespace
- Make PIPE_SEARCH_DIR an absolute path

cc: Curro Jerez 
cc: Jan Vesely 
cc: Aaron Watry 
Signed-off-by: Dylan Baker 
---
 include/meson.build   |  19 
 meson.build   |  29 +-
 meson_options.txt |   7 ++
 src/gallium/auxiliary/pipe-loader/meson.build |   3 +-
 src/gallium/meson.build   |  12 ++-
 src/gallium/state_trackers/clover/meson.build | 122 ++
 src/gallium/targets/opencl/meson.build|  73 +++
 src/gallium/targets/pipe-loader/meson.build   |  77 
 8 files changed, 336 insertions(+), 6 deletions(-)
 create mode 100644 src/gallium/state_trackers/clover/meson.build
 create mode 100644 src/gallium/targets/opencl/meson.build
 create mode 100644 src/gallium/targets/pipe-loader/meson.build

diff --git a/include/meson.build b/include/meson.build
index e4dae91cede..a2e7ce6580e 100644
--- a/include/meson.build
+++ b/include/meson.build
@@ -78,3 +78,22 @@ if with_gallium_st_nine
 subdir : 'd3dadapter',
   )
 endif
+
+# Only install the headers if we are building a stand alone implementation and
+# not an ICD enabled implementation
+if with_gallium_opencl and not with_opencl_icd
+  install_headers(
+'CL/cl.h',
+'CL/cl.hpp',
+'CL/cl_d3d10.h',
+'CL/cl_d3d11.h',
+'CL/cl_dx9_media_sharing.h',
+'CL/cl_egl.h',
+'CL/cl_ext.h',
+'CL/cl_gl.h',
+'CL/cl_gl_ext.h',
+'CL/cl_platform.h',
+'CL/opencl.h',
+subdir: 'CL'
+  )
+endif
diff --git a/meson.build b/meson.build
index 842d441199e..74b2d5c49dc 100644
--- a/meson.build
+++ b/meson.build
@@ -583,6 +583,22 @@ if with_gallium_st_nine
   endif
 endif
 
+_opencl = get_option('gallium-opencl')
+if _opencl !=' disabled'
+  if not with_gallium
+error('OpenCL Clover implementation requires at least one gallium driver.')
+  endif
+
+  # TODO: alitvec?
+  dep_clc = dependency('libclc')
+  with_gallium_opencl = true
+  with_opencl_icd = _opencl == 'icd'
+else
+  dep_clc = []
+  with_gallium_opencl = false
+  with_gallium_icd = false
+endif
+
 gl_pkgconfig_c_flags = []
 if with_platform_x11
   if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
@@ -930,7 +946,7 @@ dep_thread = dependency('threads')
 if dep_thread.found() and host_machine.system() != 'windows'
   pre_args += '-DHAVE_PTHREAD'
 endif
-if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 # TODO: clover
+if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 or 
with_gallium_opencl
   dep_elf = dependency('libelf', required : false)
   if not dep_elf.found()
 dep_elf = cc.find_library('elf')
@@ -972,12 +988,19 @@ if with_amd_vk or with_gallium_radeonsi or 
with_gallium_r600
 llvm_modules += 'asmparser'
   endif
 endif
+if with_gallium_opencl
+  llvm_modules += [
+'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 'irreader',
+'lto', 'option', 'objcarcopts', 'profiledata',
+  ]
+  # TODO: optional modules
+endif
 
 _llvm = get_option('llvm')
 if _llvm == 'auto'
   dep_llvm = dependency(
 'llvm', version : '>= 3.9.0', modules : llvm_modules,
-required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr,
+required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr or 
with_gallium_opencl,
   )
   with_llvm = dep_llvm.found()
 elif _llvm == 'true'
@@ -1154,8 +1177,6 @@ else
   dep_lmsensors = []
 endif
 
-# TODO: clover
-
 # TODO: gallium tests
 
 # TODO: various libdirs
diff --git a/meson_options.txt b/meson_options.txt
index 4f4db5b7d26..894378985fd 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -120,6 +120,13 @@ option(
   value : false,
   description : 'build gallium "nine" Direct3D 9.x state tracker.',
 )
+option(
+  'gallium-opencl',
+  type : 'combo',
+  choices : ['icd', 'standalone', 'disabled'],
+  value : 'disabled',
+  description : 'build gallium "clover" OpenCL state tracker.',
+)
 option(
   'd3d-drivers-path',
   type : 'string',
diff --git a/src/gallium/auxiliary/pipe-loader/meson.build 
b/src/gallium/auxiliary/pipe-loader/meson.build
index 9b12432aea0..869a2935149 100644
--- a/src/gallium/auxiliary/pipe-loader/meson.build
+++ b/src/gallium/auxiliary/pipe-loader/meson.build
@@ -60,7 +60,8 @@ libpipe_loader_dynamic = static_library(
   ],
   c_args : [
 c_vis_args, libpipe_loader_defines, '-DHAVE_PIPE_LOADER_DRI',
-'-DPIPE_SEARCH_DIR="@0@"'.format(join_paths(get_option('libdir'), 
'gallium-pipe')
+'-DPIPE_SEARCH_DIR="@0@"'.format(
+  join_paths(get_option('prefix'), get_option('libdir'), 'gallium-pipe')
 )
   ],
   link_with :

Re: [Mesa-dev] [PATCH v2 3/4] meson: build clover

2017-12-15 Thread Dylan Baker 
Quoting Jan Vesely (2017-12-14 11:58:03)
> 
> I use a symlink from install target to build dir to make it work on
> autotools build.
> My point was that meson defines PIPE_SEARCH_DIR to be relative path
> '-DPIPE_SEARCH_DIR="lib64/gallium-pipe"'
> even if I configure meson using --prefix=$HOME/.local/
> 
> Jan

Ahhh, okay, I understand the problem now, and the fix is rather easy too. I'll
update and send a V3 shortly.

Dylan


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Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround

2017-12-15 Thread Nanley Chery 
On Thu, Dec 14, 2017 at 07:39:46PM +0200, kevin.rogo...@intel.com wrote:
> From: Kevin Rogovin 
> 
> This patch series implements a needed workaround for Gen9 for ASTC5x5
> sampler reads. The crux of the work around is to make sure that the
> sampler does not read an ASTC5x5 texture and a surface with an auxilary
> buffer without having a texture cache invalidate and command streamer
> stall between such accesses.
> 

This workaround sounds like it deals with the same types of surfaces
dealt with in the RENDER_SURFACE_STATE field, Sampler L2 Out of Order
Mode Disable (or SamplerL2BypassModeDisable in our driver).

Here's the programming note from the SKL PRM on this field:
* This bit must be set for the following surface types:
  BC2_UNORM BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
* This bit must be set for surfaces which contain a HiZ auxilliary surface
  if other surfaces using AUX_CCS_E or AUX_CCS_D auxiliary surface state
  (lossless color compression) are being sampled at the same time.

Have we tried setting this bit for ASTC_5x5 textures?

-Nanley

> With this patch series applied to the (current) master branch of mesa,
> carchase works on my SKL GT4.
> 
> v2:
>   Rename workaround functions from brw_ to gen9_
>   (suggested/requested by Topi Pohjolainen).
> 
>   Place texture resolve to avoid using auxilary surface
>   when ASTC5x5 is detected in brw_predraw_resolve_inputs()
>   instead of another detected function; doing so allows
>   one to avoid walking the textures again.
>   (suggested/requested by Topi Pohjolainen).
> 
>   Emit command streamer stall in addition to texture
>   invalidate.
>   (original short-coming caught by Jason Ekstrand)
> 
>   Place workaround function in (new) dedicated file.
> 
>   Minor path re-ordering to accomodate changes.
> 
> Kevin Rogovin (5):
>   i965: define astx5x5 workaround infrastructure
>   i965: set ASTC5x5 workaround texture type tracking on texture validate
>   i965: use ASTC5x5 workaround in brw_draw
>   i965: use ASTC5x5 workaround in brw_compute
>   i965: ASTC5x5 workaround logic for blorp
> 
>  src/mesa/drivers/dri/i965/Makefile.sources   |  1 +
>  src/mesa/drivers/dri/i965/brw_compute.c  |  6 
>  src/mesa/drivers/dri/i965/brw_context.c  |  6 
>  src/mesa/drivers/dri/i965/brw_context.h  | 24 
>  src/mesa/drivers/dri/i965/brw_draw.c | 16 +--
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  5 
>  src/mesa/drivers/dri/i965/gen9_astc5x5_wa.c  | 36 
> 
>  src/mesa/drivers/dri/i965/genX_blorp_exec.c  |  5 
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c|  1 +
>  src/mesa/drivers/dri/i965/intel_tex_image.c  | 16 ---
>  src/mesa/drivers/dri/i965/intel_tex_validate.c   | 13 +
>  src/mesa/drivers/dri/i965/meson.build|  1 +
>  12 files changed, 124 insertions(+), 6 deletions(-)
>  create mode 100644 src/mesa/drivers/dri/i965/gen9_astc5x5_wa.c
> 
> -- 
> 2.7.4
> 
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Re: [Mesa-dev] [PATCH 22/22] st/dri: Add option to control exposure of 10 bpc color configs.

2017-12-15 Thread Mario Kleiner 

Hi,

about to push out a revision 4 of the series, which has all the r-b's of 
Tapani and Marek tacked on, rebased onto current master, and remaining 
suggestions by Tapani and Marek implemented and tested. That one should 
be totally ready to push if you are happy with it.


Just one last test to do...
-mario

On 12/13/2017 05:27 PM, Marek Olšák wrote:

Mario, can we push these patches?

Marek

On Wed, Nov 29, 2017 at 5:21 AM, Mario Kleiner
 wrote:

Some clients may not like rgb10 fbconfigs and visuals.
Support driconf option 'allow_rgb10_configs' on gallium
to allow per application enable/disable.h

The option defaults to enabled.

Signed-off-by: Mario Kleiner 
---
  src/gallium/auxiliary/pipe-loader/driinfo_gallium.h | 1 +
  src/gallium/state_trackers/dri/dri_screen.c | 8 
  2 files changed, 9 insertions(+)

diff --git a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h 
b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
index d2d2c9d..db0d633 100644
--- a/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
+++ b/src/gallium/auxiliary/pipe-loader/driinfo_gallium.h
@@ -31,4 +31,5 @@ DRI_CONF_SECTION_END
  DRI_CONF_SECTION_MISCELLANEOUS
 DRI_CONF_ALWAYS_HAVE_DEPTH_BUFFER("false")
 DRI_CONF_GLSL_ZERO_INIT("false")
+   DRI_CONF_ALLOW_RGB10_CONFIGS("true")
  DRI_CONF_SECTION_END
diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
b/src/gallium/state_trackers/dri/dri_screen.c
index 04afe71..d307b4f 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -156,6 +156,7 @@ dri_fill_in_modes(struct dri_screen *screen)
 struct pipe_screen *p_screen = screen->base.screen;
 boolean pf_z16, pf_x8z24, pf_z24x8, pf_s8z24, pf_z24s8, pf_z32;
 boolean mixed_color_depth;
+   boolean allow_rgb10;

 static const GLenum back_buffer_modes[] = {
__DRI_ATTRIB_SWAP_NONE, __DRI_ATTRIB_SWAP_UNDEFINED,
@@ -172,6 +173,8 @@ dri_fill_in_modes(struct dri_screen *screen)
depth_buffer_factor = 1;
 }

+   allow_rgb10 = driQueryOptionb(>dev->option_cache, 
"allow_rgb10_configs");
+
 msaa_samples_max = (screen->st_api->feature_mask & 
ST_API_FEATURE_MS_VISUALS_MASK)
? MSAA_VISUAL_MAX_SAMPLES : 1;

@@ -231,6 +234,11 @@ dri_fill_in_modes(struct dri_screen *screen)
unsigned num_msaa_modes = 0; /* includes a single-sample mode */
uint8_t msaa_modes[MSAA_VISUAL_MAX_SAMPLES];

+  if (!allow_rgb10 &&
+  (mesa_formats[format] == MESA_FORMAT_B10G10R10A2_UNORM ||
+   mesa_formats[format] == MESA_FORMAT_B10G10R10X2_UNORM))
+ continue;
+
if (!p_screen->is_format_supported(p_screen, pipe_formats[format],
   PIPE_TEXTURE_2D, 0,
   PIPE_BIND_RENDER_TARGET))
--
2.7.4

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Re: [Mesa-dev] [PATCH] radv: remove useless radv_cmask_info::base_address_reg

2017-12-15 Thread Bas Nieuwenhuizen 
Reviewed-by: Bas Nieuwenhuizen 

On Fri, Dec 15, 2017 at 6:54 PM, Samuel Pitoiset
 wrote:
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_private.h | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 2e1362c446..1017266efd 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1256,7 +1256,6 @@ struct radv_cmask_info {
> uint64_t size;
> unsigned alignment;
> unsigned slice_tile_max;
> -   unsigned base_address_reg;
>  };
>
>  struct radv_image {
> --
> 2.15.1
>
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[Mesa-dev] [PATCH] radv: remove useless radv_cmask_info::base_address_reg

2017-12-15 Thread Samuel Pitoiset 
Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_private.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 2e1362c446..1017266efd 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1256,7 +1256,6 @@ struct radv_cmask_info {
uint64_t size;
unsigned alignment;
unsigned slice_tile_max;
-   unsigned base_address_reg;
 };
 
 struct radv_image {
-- 
2.15.1

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Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

2017-12-15 Thread Gert Wollny 
Am Freitag, den 15.12.2017, 17:17 +0100 schrieb Juan A. Suarez Romero:
> Travis CI has moved to LLVM 5.0, and meson is detecting automatically
> the available version.

Considering that LLVM 5.0 is obviously not properly made available in
the travis-ci environment, I've reported the problem with travis-
upstream: 

https://github.com/travis-ci/travis-ci/issues/8925

Apart from that I think Eric is right, one should be able to specify
the version instead of just taking the latest availabe version. The
autotools based builds all force a version, which helps work around the
other problem:  

The travis version of LLVM is in /usr/local, so it is definitely not a
packaged version, since this would go into /usr, and because the PATH
defines /usr/local/bin before /usr/bin, and the local (incomplete)
version takes precedence, so adding llvm-5.0-dev like this is probably
useless.

Gallium ST Clover with LLVM-5.0 passes because it uses the package
version by specifically picking llvm-config-5.0 which, as Emil pointed
out, is a Debian+derivatives feat.

Best, 
Gert

> 
> So just let's change to LLVM 5.0 for this case.
> ---
>  .travis.yml | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/.travis.yml b/.travis.yml
> index 211df3ec1ef..20432361176 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -37,12 +37,12 @@ matrix:
>    addons:
>  apt:
>    sources:
> -- llvm-toolchain-trusty-3.9
> +- llvm-toolchain-trusty-5.0
>    packages:
>  # LLVM packaging is broken and misses these dependencies
>  - libedit-dev
>  # From sources above
> -- llvm-3.9-dev
> +- llvm-5.0-dev
>  # Common
>  - xz-utils
>  - libexpat1-dev
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Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

2017-12-15 Thread Jason Ekstrand 
On Fri, Dec 15, 2017 at 8:27 AM, Chris Wilson 
wrote:

> Quoting Jason Ekstrand (2017-12-15 16:21:42)
> > On Fri, Dec 15, 2017 at 5:42 AM, Chris Wilson 
> wrote:
> >
> > Every client (everyone instance that opens /dev/dri/card0 or the
> render
> > nodes), receives a unique per-process GTT (where supported by the
> > hardware, unfortunately that means only Broadwell and later). Every
> > context created by each client, in turns receives its own unique
> ppGTT.
> > This is overkill in terms of allocations and tracking, both in the
> > kernel and in the hardware, as we could be sharing the per-client GTT
> > amongst all of its contexts. The downside is that context
> segregation is
> > reduced, a stray write from one context may affect another, and so we
> > must honour any client requests that require robust segregation (e.g.
> > ARB_robustness).
> >
> > Signed-off-by: Chris Wilson 
> > ---
> >  src/mesa/drivers/dri/i965/brw_bufmgr.c  | 23
> +--
> >  src/mesa/drivers/dri/i965/brw_bufmgr.h  |  2 +-
> >  src/mesa/drivers/dri/i965/brw_context.c |  2 +-
> >  3 files changed, 19 insertions(+), 8 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> b/src/mesa/drivers/dri/
> > i965/brw_bufmgr.c
> > index 52b5bf97a1..d8a9635f5d 100644
> > --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > @@ -1297,13 +1297,24 @@ init_cache_buckets(struct brw_bufmgr *bufmgr)
> >  }
> >
> >  uint32_t
> > -brw_create_hw_context(struct brw_bufmgr *bufmgr)
> > +brw_create_hw_context(struct brw_bufmgr *bufmgr, unsigned int flags)
> >  {
> > -   struct drm_i915_gem_context_create create = { };
> > -   int ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE,
> &
> > create);
> > -   if (ret != 0) {
> > -  DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
> strerror
> > (errno));
> > -  return 0;
> > +   struct local_i915_gem_context_create_v2 {
> > +  uint32_t ctx_id; /* out */
> > +  uint32_t flags;
> > +#define I915_GEM_CONTEXT_SHARE_GTT 0x1
> > +  uint32_t share_ctx;
> >
> >
> > So, we've left share_ctx as 0.  What does that mean?  Does that mean
> that we
> > share with some context that was implicitly created by opening
> /dev/dri/card0?
> > Does it mean we share with the default context and therefore other
> processes?
>
> The default context, 0, is per fd.
>

So a second open() of /dev/dri/card0 will get a different default context?
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Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

2017-12-15 Thread Emil Velikov 
On 15 December 2017 at 16:49, Eric Engestrom  wrote:
> On Friday, 2017-12-15 17:17:55 +0100, Juan A. Suarez Romero wrote:
>> Travis CI has moved to LLVM 5.0, and meson is detecting automatically
>> the available version.
>>
>> So just let's change to LLVM 5.0 for this case.
>
> I thought we were using 3.9 on purpose, to test our minimum required
> llvm version?
>
> I think the proper fix would be to add a `-D llvm-version=3.9` option
> and use that in the dependency() check.
>
Allow me to suggest and alternative solution:

Feed in the llvm-config name (aka LLVM_CONFIG) like we do for scons
and autotools.
It will provide some nice consistency, plus it will allow for easier
selection as path and version.

Not to mention that distributions (Debian for example) allow multiple
versions to coexist, naming the binary - llvm-config-$version.

-Emil
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Re: [Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

2017-12-15 Thread Eric Engestrom 
On Friday, 2017-12-15 17:17:55 +0100, Juan A. Suarez Romero wrote:
> Travis CI has moved to LLVM 5.0, and meson is detecting automatically
> the available version.
> 
> So just let's change to LLVM 5.0 for this case.

I thought we were using 3.9 on purpose, to test our minimum required
llvm version?

I think the proper fix would be to add a `-D llvm-version=3.9` option
and use that in the dependency() check.

Untested patch follows; Dylan, what do you think?

8<
diff --git a/meson.build b/meson.build
index 6e5ae4d24e9e55b1b2d3..e990eb9717b36f1b4b8a 100644
--- a/meson.build
+++ b/meson.build
@@ -972,14 +972,18 @@ if with_amd_vk or with_gallium_radeonsi or 
with_gallium_r600
 endif
 
 _llvm = get_option('llvm')
+_llvm_version = get_option('llvm-version')
+if _llvm_version == 'auto'
+  _llvm_version = '>= 3.9.0'
+endif
 if _llvm == 'auto'
   dep_llvm = dependency(
-'llvm', version : '>= 3.9.0', modules : llvm_modules,
+'llvm', version : _llvm_version, modules : llvm_modules,
 required : with_amd_vk or with_gallium_radeonsi,
   )
   with_llvm = dep_llvm.found()
 elif _llvm == 'true'
-  dep_llvm = dependency('llvm', version : '>= 3.9.0', modules : llvm_modules)
+  dep_llvm = dependency('llvm', version : _llvm_version, modules : 
llvm_modules)
   with_llvm = true
 else
   dep_llvm = []
diff --git a/meson_options.txt b/meson_options.txt
index 39b137cbeafb82a4f845..e72988755c2d1c8401f9 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -208,6 +208,12 @@ option(
   choices : ['auto', 'true', 'false'],
   description : 'Build with LLVM support.'
 )
+option(
+  'llvm-version',
+  type : 'string',
+  value : 'auto',
+  description : 'LLVM version to use, or `auto`'
+)
 option(
   'valgrind',
   type : 'combo',
diff --git a/.travis.yml b/.travis.yml
index 211df3ec1efe47aa4092..e054a6c5210e755a2c68 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -33,7 +33,7 @@ matrix:
 - env:
 - LABEL="meson Vulkan"
 - BUILD=meson
-- MESON_OPTIONS="-Ddri-drivers= -Dgallium-drivers="
+- MESON_OPTIONS="-Ddri-drivers= -Dgallium-drivers= -Dllvm-version=3.9"
   addons:
 apt:
   sources:
>8

> ---
>  .travis.yml | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/.travis.yml b/.travis.yml
> index 211df3ec1ef..20432361176 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -37,12 +37,12 @@ matrix:
>addons:
>  apt:
>sources:
> -- llvm-toolchain-trusty-3.9
> +- llvm-toolchain-trusty-5.0
>packages:
>  # LLVM packaging is broken and misses these dependencies
>  - libedit-dev
>  # From sources above
> -- llvm-3.9-dev
> +- llvm-5.0-dev
>  # Common
>  - xz-utils
>  - libexpat1-dev
> -- 
> 2.14.3
> 
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Re: [Mesa-dev] [PATCH 00/20] swr: update rasterizer

2017-12-15 Thread Cherniak, Bruce 
Reviewed-by: Bruce Cherniak  

> On Dec 14, 2017, at 3:34 PM, Tim Rowley  wrote:
> 
> Highlights include simd16 work, thread pool initialization rework,
> and code cleanup.
> 
> Tim Rowley (20):
>  swr/rast: Remove unneeded copy of gather mask
>  swr/rast: Binner fixes for viewport index offset handling
>  swr/rast: Corrections to multi-scissor handling
>  swr/rast: WIP - Widen fetch shader to SIMD16
>  swr/rast: Convert gather masks to Nx1bit
>  swr/rast: Rewrite Shuffle8bpcGatherd using shuffle
>  swr/rast: Move GatherScissors to header
>  swr/rast: Pull most of the VPAI manipulation out of the binner/clipper
>  swr/rast: Pass prim to ClipSimd
>  swr/rast: SIMD16 Fetch - Fully widen 32-bit float vertex components
>  swr/rast: SIMD16 Fetch - Fully widen 16-bit float vertex components
>  swr/rast: Replace INSERT2 vextract/vinsert with JOIN2 vshuffle
>  swr/rast: SIMD16 Fetch - Fully widen 32-bit integer vertex components
>  swr/rast: Remove no-op VBROADCAST of vID
>  swr/rast: Pull of RTAI gather & offset out of clip/bin code
>  swr/rast: Rework thread binding parameters for machine partitioning
>  swr/rast: Replace VPSRL with LSHR
>  swr/rast: Fix cache of API thread event manager
>  swr/rast: EXTRACT2 changed from vextract/vinsert to vshuffle
>  swr/rast: Move more RTAI handling out of binner
> 
> .../swr/rasterizer/codegen/gen_llvm_ir_macros.py   |4 +-
> .../drivers/swr/rasterizer/codegen/knob_defs.py|   29 +-
> src/gallium/drivers/swr/rasterizer/core/api.cpp|   42 +-
> src/gallium/drivers/swr/rasterizer/core/api.h  |   33 +
> src/gallium/drivers/swr/rasterizer/core/binner.cpp |  345 ++-
> src/gallium/drivers/swr/rasterizer/core/binner.h   |  127 +++
> src/gallium/drivers/swr/rasterizer/core/clip.cpp   |   31 +-
> src/gallium/drivers/swr/rasterizer/core/clip.h |   67 +-
> src/gallium/drivers/swr/rasterizer/core/context.h  |5 +-
> .../drivers/swr/rasterizer/core/frontend.cpp   |  179 +++-
> src/gallium/drivers/swr/rasterizer/core/frontend.h |8 +-
> src/gallium/drivers/swr/rasterizer/core/pa.h   |5 +-
> .../drivers/swr/rasterizer/core/threads.cpp|  299 --
> src/gallium/drivers/swr/rasterizer/core/threads.h  |4 +
> .../drivers/swr/rasterizer/core/tilemgr.cpp|4 +-
> .../drivers/swr/rasterizer/jitter/builder_misc.cpp |  157 ++-
> .../drivers/swr/rasterizer/jitter/builder_misc.h   |   13 +-
> .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 1038 
> 18 files changed, 1657 insertions(+), 733 deletions(-)
> 
> -- 
> 2.14.1
> 
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Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

2017-12-15 Thread Chris Wilson 
Quoting Jason Ekstrand (2017-12-15 16:21:42)
> On Fri, Dec 15, 2017 at 5:42 AM, Chris Wilson  
> wrote:
> 
> Every client (everyone instance that opens /dev/dri/card0 or the render
> nodes), receives a unique per-process GTT (where supported by the
> hardware, unfortunately that means only Broadwell and later). Every
> context created by each client, in turns receives its own unique ppGTT.
> This is overkill in terms of allocations and tracking, both in the
> kernel and in the hardware, as we could be sharing the per-client GTT
> amongst all of its contexts. The downside is that context segregation is
> reduced, a stray write from one context may affect another, and so we
> must honour any client requests that require robust segregation (e.g.
> ARB_robustness).
> 
> Signed-off-by: Chris Wilson 
> ---
>  src/mesa/drivers/dri/i965/brw_bufmgr.c  | 23 +--
>  src/mesa/drivers/dri/i965/brw_bufmgr.h  |  2 +-
>  src/mesa/drivers/dri/i965/brw_context.c |  2 +-
>  3 files changed, 19 insertions(+), 8 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
> b/src/mesa/drivers/dri/
> i965/brw_bufmgr.c
> index 52b5bf97a1..d8a9635f5d 100644
> --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> @@ -1297,13 +1297,24 @@ init_cache_buckets(struct brw_bufmgr *bufmgr)
>  }
> 
>  uint32_t
> -brw_create_hw_context(struct brw_bufmgr *bufmgr)
> +brw_create_hw_context(struct brw_bufmgr *bufmgr, unsigned int flags)
>  {
> -   struct drm_i915_gem_context_create create = { };
> -   int ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &
> create);
> -   if (ret != 0) {
> -      DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror
> (errno));
> -      return 0;
> +   struct local_i915_gem_context_create_v2 {
> +      uint32_t ctx_id; /* out */
> +      uint32_t flags;
> +#define I915_GEM_CONTEXT_SHARE_GTT 0x1
> +      uint32_t share_ctx;
> 
> 
> So, we've left share_ctx as 0.  What does that mean?  Does that mean that we
> share with some context that was implicitly created by opening 
> /dev/dri/card0? 
> Does it mean we share with the default context and therefore other processes? 

The default context, 0, is per fd.
-Chris
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[Mesa-dev] [PATCH] swr: Account for VBO index_bias in offsets

2017-12-15 Thread George Kyriazis 
Account for info.index_bias when calculating buffers offsets.

Fixes the follow piglit tests:
arb_draw_elements_base_vertex-drawelements-user_varrays
arb_draw_elements_base_vertex-negative-index-user_varrays
---
 src/gallium/drivers/swr/swr_state.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_state.cpp 
b/src/gallium/drivers/swr/swr_state.cpp
index 4530d37..d320c90 100644
--- a/src/gallium/drivers/swr/swr_state.cpp
+++ b/src/gallium/drivers/swr/swr_state.cpp
@@ -1012,8 +1012,8 @@ swr_user_vbuf_range(const struct pipe_draw_info *info,
   *size = elems * vb->stride;
} else if (vb->stride) {
   elems = info->max_index - info->min_index + 1;
-  *totelems = info->max_index + 1;
-  *base = info->min_index * vb->stride;
+  *totelems = (info->max_index + info->index_bias) + 1;
+  *base = (info->min_index + info->index_bias) * vb->stride;
   *size = elems * vb->stride;
} else {
   *totelems = 1;
@@ -1304,7 +1304,7 @@ swr_update_derived(struct pipe_context *pipe,
 uint32_t base;
 swr_user_vbuf_range(, ctx->velems, vb, i, , , 
);
 partial_inbounds = 0;
-min_vertex_index = info.min_index;
+min_vertex_index = info.min_index + info.index_bias;
 
 size = AlignUp(size, 4);
 /* If size of client memory copy is too large, don't copy. The
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

2017-12-15 Thread Jason Ekstrand 
On Fri, Dec 15, 2017 at 5:42 AM, Chris Wilson 
wrote:

> Every client (everyone instance that opens /dev/dri/card0 or the render
> nodes), receives a unique per-process GTT (where supported by the
> hardware, unfortunately that means only Broadwell and later). Every
> context created by each client, in turns receives its own unique ppGTT.
> This is overkill in terms of allocations and tracking, both in the
> kernel and in the hardware, as we could be sharing the per-client GTT
> amongst all of its contexts. The downside is that context segregation is
> reduced, a stray write from one context may affect another, and so we
> must honour any client requests that require robust segregation (e.g.
> ARB_robustness).
>
> Signed-off-by: Chris Wilson 
> ---
>  src/mesa/drivers/dri/i965/brw_bufmgr.c  | 23 +--
>  src/mesa/drivers/dri/i965/brw_bufmgr.h  |  2 +-
>  src/mesa/drivers/dri/i965/brw_context.c |  2 +-
>  3 files changed, 19 insertions(+), 8 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> index 52b5bf97a1..d8a9635f5d 100644
> --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> @@ -1297,13 +1297,24 @@ init_cache_buckets(struct brw_bufmgr *bufmgr)
>  }
>
>  uint32_t
> -brw_create_hw_context(struct brw_bufmgr *bufmgr)
> +brw_create_hw_context(struct brw_bufmgr *bufmgr, unsigned int flags)
>  {
> -   struct drm_i915_gem_context_create create = { };
> -   int ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE,
> );
> -   if (ret != 0) {
> -  DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
> strerror(errno));
> -  return 0;
> +   struct local_i915_gem_context_create_v2 {
> +  uint32_t ctx_id; /* out */
> +  uint32_t flags;
> +#define I915_GEM_CONTEXT_SHARE_GTT 0x1
> +  uint32_t share_ctx;
>

So, we've left share_ctx as 0.  What does that mean?  Does that mean that
we share with some context that was implicitly created by opening
/dev/dri/card0?  Does it mean we share with the default context and
therefore other processes?  If some other component (say, vaapi) opens
/dev/dri/card0 but from the same process, are we now sharing with it?

I mean, as far as the kernel UABI bits go, it seems perfectly reasonable.
There are just a lot of crazy implications here and I'd like to understand
the subtle details better.

--Jason


> +  uint32_t pad;
> +   } create =  { };
> +#define LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE  DRM_IOWR
> (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct
> local_i915_gem_context_create_v2)
> +
> +   if (!(flags & __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS))
> +  create.flags |= I915_GEM_CONTEXT_SHARE_GTT;
> +
> +   if (drmIoctl(bufmgr->fd, LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE,
> )) {
> +  create.flags = 0;
> +  if (drmIoctl(bufmgr->fd, LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE,
> ))
> + return 0;
> }
>
> return create.ctx_id;
> diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h
> b/src/mesa/drivers/dri/i965/brw_bufmgr.h
> index 0ae541cda0..f5191aff76 100644
> --- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
> +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
> @@ -321,7 +321,7 @@ void brw_bufmgr_enable_reuse(struct brw_bufmgr
> *bufmgr);
>
>  int brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns);
>
> -uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr);
> +uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr, unsigned int
> flags);
>
>  #define BRW_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
>  #define BRW_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> index 9e0f875b27..e374236b6b 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -986,7 +986,7 @@ brwCreateContext(gl_api api,
>  * This is required for transform feedback buffer offsets, query
> objects,
>  * and also allows us to reduce how much state we have to emit.
>  */
> -   brw->hw_ctx = brw_create_hw_context(brw->bufmgr);
> +   brw->hw_ctx = brw_create_hw_context(brw->bufmgr, ctx_config->flags);
> if (!brw->hw_ctx && devinfo->gen >= 6) {
>fprintf(stderr, "Failed to create hardware context.\n");
>intelDestroyContext(driContextPriv);
> --
> 2.15.1
>
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[Mesa-dev] [PATCH] travis: use LLVM 5.0 for Meson Vulkan

2017-12-15 Thread Juan A. Suarez Romero 
Travis CI has moved to LLVM 5.0, and meson is detecting automatically
the available version.

So just let's change to LLVM 5.0 for this case.
---
 .travis.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 211df3ec1ef..20432361176 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -37,12 +37,12 @@ matrix:
   addons:
 apt:
   sources:
-- llvm-toolchain-trusty-3.9
+- llvm-toolchain-trusty-5.0
   packages:
 # LLVM packaging is broken and misses these dependencies
 - libedit-dev
 # From sources above
-- llvm-3.9-dev
+- llvm-5.0-dev
 # Common
 - xz-utils
 - libexpat1-dev
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

2017-12-15 Thread Chris Wilson 
Quoting Jason Ekstrand (2017-12-15 15:40:51)
> What does this actually gain us?  Multiple contexts aren't common.

UE4 is one that I know of that uses multiple contexts to separate
rendering from presentation, afaik. The API is precursor to try and
define a lighterweight context object for future execution queues. The
RFC is to see if there is interest in having that as standalone.
-Chris
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Re: [Mesa-dev] [PATCH] anv: fix bug when VK_REMAINING_ARRAY_LAYERS is used in vkCmdClearAttachments()

2017-12-15 Thread Jason Ekstrand 
Ugh... The problem here is that we may not know the framebuffer in 
CmdCearAttachments if it's in a secondary command buffer.  I'm not actually 
sure what to do in that case.  I guess we could store the number of later 
somewhere and teach blorp how to do an indirect draw.  Really, I think it 
makes more sense to just disallow VK_REMAINING_LAYERS in that function.


--Jason


On December 15, 2017 03:36:07 Samuel Iglesias Gonsálvez 
 wrote:



Blorp was not supporting the use of the constant VK_REMAINING_ARRAY_LAYERS
(whose value is ~0) in the VkClearRect structure. If we receive it, we need
to calculate the layer count as the image layers count minus the base array
layer.

Signed-off-by: Samuel Iglesias Gonsálvez 
---
 src/intel/vulkan/anv_blorp.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index e244468e03..4ab4458246 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -989,10 +989,15 @@ clear_color_attachment(struct anv_cmd_buffer *cmd_buffer,
for (uint32_t r = 0; r < rectCount; ++r) {
   const VkOffset2D offset = pRects[r].rect.offset;
   const VkExtent2D extent = pRects[r].rect.extent;
+  unsigned layer_count =
+ anv_get_layerCount(
+cmd_buffer->state.framebuffer->attachments[att_idx]->image,
+[r]);
+
   blorp_clear_attachments(batch, binding_table,
   ISL_FORMAT_UNSUPPORTED, pass_att->samples,
   pRects[r].baseArrayLayer,
-  pRects[r].layerCount,
+  layer_count,
   offset.x, offset.y,
   offset.x + extent.width, offset.y + 
extent.height,
   true, clear_color, false, 0.0f, 0, 0);
@@ -1059,11 +1064,16 @@ clear_depth_stencil_attachment(struct 
anv_cmd_buffer *cmd_buffer,

for (uint32_t r = 0; r < rectCount; ++r) {
   const VkOffset2D offset = pRects[r].rect.offset;
   const VkExtent2D extent = pRects[r].rect.extent;
+  unsigned layer_count =
+ anv_get_layerCount(
+cmd_buffer->state.framebuffer->attachments[att_idx]->image,
+[r]);
+
   VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
   blorp_clear_attachments(batch, binding_table,
   depth_format, pass_att->samples,
   pRects[r].baseArrayLayer,
-  pRects[r].layerCount,
+  layer_count,
   offset.x, offset.y,
   offset.x + extent.width, offset.y + 
extent.height,
   false, color_value,
--
2.14.1

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Re: [Mesa-dev] [PATCH] loader/dri3: Try to make sure we only process our own NotifyMSC events

2017-12-15 Thread Michel Dänzer 

Ping (sorry I forgot to mark this as v2 in the subject)


On 2017-11-23 10:26 AM, Michel Dänzer wrote:
> From: Michel Dänzer 
> 
> We were using a sequence counter value to wait for a specific NotifyMSC
> event. However, we can receive events from other clients as well, which
> may already be using higher sequence numbers than us. In that case, we
> could stop processing after an event from another client, which could
> have been received significantly earlier. This would have multiple
> undesirable effects:
> 
> * The computed MSC and UST values would be lower than they should be
> * We could leave a growing number of NotifyMSC events from ourselves and
>   other clients in XCB's special event queue
> 
> I ran into this with Firefox and Thunderbird, whose VSync threads both
> seem to use the same window. The result was sluggish screen updates and
> growing memory consumption in one of them.
> 
> Fix this by checking the XCB sequence number and MSC value of NotifyMSC
> events, instead of using our own sequence number.
> 
> v2:
> * Use the Present event ID for the sequence parameter of the
>   PresentNotifyMSC request, as another safeguard against processing
>   events from other clients
> * Rebase on drawable mutex changes
> 
> Cc: mesa-sta...@lists.freedesktop.org
> Reviewed-by: Nicolai Hähnle  # v1
> Signed-off-by: Michel Dänzer 
> ---
>  src/loader/loader_dri3_helper.c | 36 ++--
>  src/loader/loader_dri3_helper.h |  4 
>  2 files changed, 18 insertions(+), 22 deletions(-)
> 
> diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
> index 7e6b8b2e056..d4cd9737ab2 100644
> --- a/src/loader/loader_dri3_helper.c
> +++ b/src/loader/loader_dri3_helper.c
> @@ -384,8 +384,7 @@ dri3_handle_present_event(struct loader_dri3_drawable 
> *draw,
>  
>   draw->ust = ce->ust;
>   draw->msc = ce->msc;
> -  } else {
> - draw->recv_msc_serial = ce->serial;
> +  } else if (ce->serial == draw->eid) {
>   draw->notify_ust = ce->ust;
>   draw->notify_msc = ce->msc;
>}
> @@ -453,28 +452,29 @@ loader_dri3_wait_for_msc(struct loader_dri3_drawable 
> *draw,
>   int64_t divisor, int64_t remainder,
>   int64_t *ust, int64_t *msc, int64_t *sbc)
>  {
> -   uint32_t msc_serial;
> -
> -   msc_serial = ++draw->send_msc_serial;
> -   xcb_present_notify_msc(draw->conn,
> -  draw->drawable,
> -  msc_serial,
> -  target_msc,
> -  divisor,
> -  remainder);
> +   xcb_void_cookie_t cookie = xcb_present_notify_msc(draw->conn,
> + draw->drawable,
> + draw->eid,
> + target_msc,
> + divisor,
> + remainder);
> +   xcb_generic_event_t *ev;
> +   unsigned full_sequence;
>  
> mtx_lock(>mtx);
> xcb_flush(draw->conn);
>  
> /* Wait for the event */
> -   if (draw->special_event) {
> -  while ((int32_t) (msc_serial - draw->recv_msc_serial) > 0) {
> - if (!dri3_wait_for_event_locked(draw)) {
> -mtx_unlock(>mtx);
> -return false;
> - }
> +   do {
> +  ev = xcb_wait_for_special_event(draw->conn, draw->special_event);
> +  if (!ev) {
> + mtx_unlock(>mtx);
> + return false;
>}
> -   }
> +
> +  full_sequence = ev->full_sequence;
> +  dri3_handle_present_event(draw, (void *) ev);
> +   } while (full_sequence != cookie.sequence || draw->notify_msc < 
> target_msc);
>  
> *ust = draw->notify_ust;
> *msc = draw->notify_msc;
> diff --git a/src/loader/loader_dri3_helper.h b/src/loader/loader_dri3_helper.h
> index 0dd37e91717..4ce98b8c59f 100644
> --- a/src/loader/loader_dri3_helper.h
> +++ b/src/loader/loader_dri3_helper.h
> @@ -137,10 +137,6 @@ struct loader_dri3_drawable {
> /* Last received UST/MSC values from present notify msc event */
> uint64_t notify_ust, notify_msc;
>  
> -   /* Serial numbers for tracking wait_for_msc events */
> -   uint32_t send_msc_serial;
> -   uint32_t recv_msc_serial;
> -
> struct loader_dri3_buffer *buffers[LOADER_DRI3_NUM_BUFFERS];
> int cur_back;
> int num_back;
> 


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

2017-12-15 Thread Jason Ekstrand 

What does this actually gain us?  Multiple contexts aren't common.


On December 15, 2017 05:43:09 Chris Wilson  wrote:


Every client (everyone instance that opens /dev/dri/card0 or the render
nodes), receives a unique per-process GTT (where supported by the
hardware, unfortunately that means only Broadwell and later). Every
context created by each client, in turns receives its own unique ppGTT.
This is overkill in terms of allocations and tracking, both in the
kernel and in the hardware, as we could be sharing the per-client GTT
amongst all of its contexts. The downside is that context segregation is
reduced, a stray write from one context may affect another, and so we
must honour any client requests that require robust segregation (e.g.
ARB_robustness).

Signed-off-by: Chris Wilson 
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c  | 23 +--
 src/mesa/drivers/dri/i965/brw_bufmgr.h  |  2 +-
 src/mesa/drivers/dri/i965/brw_context.c |  2 +-
 3 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c

index 52b5bf97a1..d8a9635f5d 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -1297,13 +1297,24 @@ init_cache_buckets(struct brw_bufmgr *bufmgr)
 }

 uint32_t
-brw_create_hw_context(struct brw_bufmgr *bufmgr)
+brw_create_hw_context(struct brw_bufmgr *bufmgr, unsigned int flags)
 {
-   struct drm_i915_gem_context_create create = { };
-   int ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, );
-   if (ret != 0) {
-  DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno));
-  return 0;
+   struct local_i915_gem_context_create_v2 {
+  uint32_t ctx_id; /* out */
+  uint32_t flags;
+#define I915_GEM_CONTEXT_SHARE_GTT 0x1
+  uint32_t share_ctx;
+  uint32_t pad;
+   } create =  { };
+#define LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE  DRM_IOWR 
(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct 
local_i915_gem_context_create_v2)

+
+   if (!(flags & __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS))
+  create.flags |= I915_GEM_CONTEXT_SHARE_GTT;
+
+   if (drmIoctl(bufmgr->fd, LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE, )) {
+  create.flags = 0;
+  if (drmIoctl(bufmgr->fd, LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE, ))
+ return 0;
}

return create.ctx_id;
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h

index 0ae541cda0..f5191aff76 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -321,7 +321,7 @@ void brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr);

 int brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns);

-uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr);
+uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr, unsigned int flags);

 #define BRW_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
 #define BRW_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c

index 9e0f875b27..e374236b6b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -986,7 +986,7 @@ brwCreateContext(gl_api api,
 * This is required for transform feedback buffer offsets, query objects,
 * and also allows us to reduce how much state we have to emit.
 */
-   brw->hw_ctx = brw_create_hw_context(brw->bufmgr);
+   brw->hw_ctx = brw_create_hw_context(brw->bufmgr, ctx_config->flags);
if (!brw->hw_ctx && devinfo->gen >= 6) {
   fprintf(stderr, "Failed to create hardware context.\n");
   intelDestroyContext(driContextPriv);
--
2.15.1

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Re: [Mesa-dev] [PATCH] Revert "radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components"

2017-12-15 Thread Alex Smith 
Tested-by: Alex Smith 

On 15 December 2017 at 15:01, Samuel Pitoiset 
wrote:

> This reverts commit 2294d35b243dee15af15895e876a63b7d22e48cc.
>
> We can't do this without adjusting the input SGPRs/VGPRs logic.
> For now, just revert it. I will send a proper solution later.
>
> It fixes a rendering issue in F1 2017 that CTS didn't catch up.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_shader.c | 7 ++-
>  1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index ab8ba42511..f96b0c07f1 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -395,11 +395,8 @@ radv_fill_shader_variant(struct radv_device *device,
> case MESA_SHADER_COMPUTE: {
> struct ac_shader_info *info = >info.info;
> variant->rsrc2 |=
> -   S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
> -   S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
> -   S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
> -   S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2]
> ? 2 :
> -   info->cs.uses_thread_id[1]
> ? 1 : 0) |
> +   S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
> +   S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2)
> |
> 
> S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx)
> |
> S_00B84C_LDS_SIZE(variant->config.lds_size);
> break;
> --
> 2.15.1
>
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[Mesa-dev] [PATCH] Revert "radv: do not load unused gl_LocalInvocationID/gl_WorkGroupID components"

2017-12-15 Thread Samuel Pitoiset 
This reverts commit 2294d35b243dee15af15895e876a63b7d22e48cc.

We can't do this without adjusting the input SGPRs/VGPRs logic.
For now, just revert it. I will send a proper solution later.

It fixes a rendering issue in F1 2017 that CTS didn't catch up.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_shader.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index ab8ba42511..f96b0c07f1 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -395,11 +395,8 @@ radv_fill_shader_variant(struct radv_device *device,
case MESA_SHADER_COMPUTE: {
struct ac_shader_info *info = >info.info;
variant->rsrc2 |=
-   S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
-   S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
-   S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
-   S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
-   info->cs.uses_thread_id[1] ? 1 
: 0) |
+   S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) |
+   S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) |
S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) 
|
S_00B84C_LDS_SIZE(variant->config.lds_size);
break;
-- 
2.15.1

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[Mesa-dev] [PATCH 1/2] amd/common: add ac_get_cb_shader_mask() helper

2017-12-15 Thread Samuel Pitoiset 
Signed-off-by: Samuel Pitoiset 
---
 src/amd/common/ac_shader_util.c | 35 +
 src/amd/common/ac_shader_util.h |  3 +++
 src/amd/vulkan/radv_pipeline.c  | 34 +---
 src/gallium/drivers/radeonsi/si_state_shaders.c | 34 +---
 4 files changed, 40 insertions(+), 66 deletions(-)

diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
index 9d33a46559..ab8d3ed49b 100644
--- a/src/amd/common/ac_shader_util.c
+++ b/src/amd/common/ac_shader_util.c
@@ -21,6 +21,8 @@
  * IN THE SOFTWARE.
  */
 
+#include 
+
 #include "ac_shader_util.h"
 #include "sid.h"
 
@@ -43,3 +45,36 @@ ac_get_spi_shader_z_format(bool writes_z, bool 
writes_stencil,
return V_028710_SPI_SHADER_ZERO;
}
 }
+
+unsigned
+ac_get_cb_shader_mask(unsigned spi_shader_col_format)
+{
+   unsigned i, cb_shader_mask = 0;
+
+   for (i = 0; i < 8; i++) {
+   switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
+   case V_028714_SPI_SHADER_ZERO:
+   break;
+   case V_028714_SPI_SHADER_32_R:
+   cb_shader_mask |= 0x1 << (i * 4);
+   break;
+   case V_028714_SPI_SHADER_32_GR:
+   cb_shader_mask |= 0x3 << (i * 4);
+   break;
+   case V_028714_SPI_SHADER_32_AR:
+   cb_shader_mask |= 0x9 << (i * 4);
+   break;
+   case V_028714_SPI_SHADER_FP16_ABGR:
+   case V_028714_SPI_SHADER_UNORM16_ABGR:
+   case V_028714_SPI_SHADER_SNORM16_ABGR:
+   case V_028714_SPI_SHADER_UINT16_ABGR:
+   case V_028714_SPI_SHADER_SINT16_ABGR:
+   case V_028714_SPI_SHADER_32_ABGR:
+   cb_shader_mask |= 0xf << (i * 4);
+   break;
+   default:
+   assert(0);
+   }
+   }
+   return cb_shader_mask;
+}
diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h
index 1f971e76f1..d3804b8fb1 100644
--- a/src/amd/common/ac_shader_util.h
+++ b/src/amd/common/ac_shader_util.h
@@ -30,4 +30,7 @@ unsigned
 ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
   bool writes_samplemask);
 
+unsigned
+ac_get_cb_shader_mask(unsigned spi_shader_col_format);
+
 #endif
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1ada69d92f..1086f70d05 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -416,38 +416,6 @@ static unsigned si_choose_spi_color_format(VkFormat 
vk_format,
return normal;
 }
 
-static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
-{
-   unsigned i, cb_shader_mask = 0;
-
-   for (i = 0; i < 8; i++) {
-   switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
-   case V_028714_SPI_SHADER_ZERO:
-   break;
-   case V_028714_SPI_SHADER_32_R:
-   cb_shader_mask |= 0x1 << (i * 4);
-   break;
-   case V_028714_SPI_SHADER_32_GR:
-   cb_shader_mask |= 0x3 << (i * 4);
-   break;
-   case V_028714_SPI_SHADER_32_AR:
-   cb_shader_mask |= 0x9 << (i * 4);
-   break;
-   case V_028714_SPI_SHADER_FP16_ABGR:
-   case V_028714_SPI_SHADER_UNORM16_ABGR:
-   case V_028714_SPI_SHADER_SNORM16_ABGR:
-   case V_028714_SPI_SHADER_UINT16_ABGR:
-   case V_028714_SPI_SHADER_SINT16_ABGR:
-   case V_028714_SPI_SHADER_32_ABGR:
-   cb_shader_mask |= 0xf << (i * 4);
-   break;
-   default:
-   assert(0);
-   }
-   }
-   return cb_shader_mask;
-}
-
 static void
 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo 
*pCreateInfo,
@@ -477,7 +445,7 @@ radv_pipeline_compute_spi_color_formats(struct 
radv_pipeline *pipeline,
col_format |= cf << (4 * i);
}
 
-   blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
+   blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
 
if (blend_mrt0_is_dual_src)
col_format |= (col_format & 0xf) << 4;
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 25854a1fde..d33008cdda 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -981,38 +981,6 @@ static unsigned si_get_spi_shader_col_format(struct 
si_shader *shader)
return value;
 }
 
-static unsigned

[Mesa-dev] [PATCH 2/2] amd/common: add ac_vgt_gs_mode() helper

2017-12-15 Thread Samuel Pitoiset 
Signed-off-by: Samuel Pitoiset 
---
 src/amd/common/ac_shader_util.c | 27 +
 src/amd/common/ac_shader_util.h |  6 +
 src/amd/vulkan/radv_pipeline.c  | 32 +
 src/gallium/drivers/radeonsi/si_state_shaders.c | 32 +++--
 4 files changed, 42 insertions(+), 55 deletions(-)

diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
index ab8d3ed49b..12f86dc677 100644
--- a/src/amd/common/ac_shader_util.c
+++ b/src/amd/common/ac_shader_util.c
@@ -78,3 +78,30 @@ ac_get_cb_shader_mask(unsigned spi_shader_col_format)
}
return cb_shader_mask;
 }
+
+/**
+ * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
+ * geometry shader.
+ */
+uint32_t
+ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class)
+{
+   unsigned cut_mode;
+
+   if (gs_max_vert_out <= 128) {
+   cut_mode = V_028A40_GS_CUT_128;
+   } else if (gs_max_vert_out <= 256) {
+   cut_mode = V_028A40_GS_CUT_256;
+   } else if (gs_max_vert_out <= 512) {
+   cut_mode = V_028A40_GS_CUT_512;
+   } else {
+   assert(gs_max_vert_out <= 1024);
+   cut_mode = V_028A40_GS_CUT_1024;
+   }
+
+   return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
+  S_028A40_CUT_MODE(cut_mode)|
+  S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
+  S_028A40_GS_WRITE_OPTIMIZE(1) |
+  S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
+}
diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h
index d3804b8fb1..1bdf909e09 100644
--- a/src/amd/common/ac_shader_util.h
+++ b/src/amd/common/ac_shader_util.h
@@ -25,6 +25,9 @@
 #define AC_SHADER_UTIL_H
 
 #include 
+#include 
+
+#include "amd_family.h"
 
 unsigned
 ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
@@ -33,4 +36,7 @@ ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
 unsigned
 ac_get_cb_shader_mask(unsigned spi_shader_col_format);
 
+uint32_t
+ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class);
+
 #endif
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1086f70d05..9daa2c9a1e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1465,30 +1465,6 @@ static const struct radv_prim_vertex_count 
prim_size_table[] = {
[V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
 };
 
-static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs,
-   enum chip_class chip_class)
-{
-   unsigned gs_max_vert_out = gs->info.gs.vertices_out;
-   unsigned cut_mode;
-
-   if (gs_max_vert_out <= 128) {
-   cut_mode = V_028A40_GS_CUT_128;
-   } else if (gs_max_vert_out <= 256) {
-   cut_mode = V_028A40_GS_CUT_256;
-   } else if (gs_max_vert_out <= 512) {
-   cut_mode = V_028A40_GS_CUT_512;
-   } else {
-   assert(gs_max_vert_out <= 1024);
-   cut_mode = V_028A40_GS_CUT_1024;
-   }
-
-   return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
-  S_028A40_CUT_MODE(cut_mode)|
-  S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
-  S_028A40_GS_WRITE_OPTIMIZE(1) |
-  S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
-}
-
 static struct ac_vs_output_info *get_vs_output_info(struct radv_pipeline 
*pipeline)
 {
if (radv_pipeline_has_gs(pipeline))
@@ -1507,8 +1483,12 @@ static void calculate_vgt_gs_mode(struct radv_pipeline 
*pipeline)
pipeline->graphics.vgt_gs_mode = 0;
 
if (radv_pipeline_has_gs(pipeline)) {
-   pipeline->graphics.vgt_gs_mode = 
si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY],
-   
pipeline->device->physical_device->rad_info.chip_class);
+   struct radv_shader_variant *gs =
+   pipeline->shaders[MESA_SHADER_GEOMETRY];
+
+   pipeline->graphics.vgt_gs_mode =
+   ac_vgt_gs_mode(gs->info.gs.vertices_out,
+  
pipeline->device->physical_device->rad_info.chip_class);
} else if (outinfo->export_prim_id) {
pipeline->graphics.vgt_gs_mode = 
S_028A40_MODE(V_028A40_GS_SCENARIO_A);
pipeline->graphics.vgt_primitiveid_en = true;
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index d33008cdda..9143f61fcd 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -573,34 +573,6 @@ static void si_shader_es(struct si_screen *sscreen, struct 
si_shader *shader)
polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
 }
 
-/**
- * Calculate the appropriate setting of VGT_GS_MODE when

[Mesa-dev] [PATCH 1/2] i965: Always try to create a logical context

2017-12-15 Thread Chris Wilson 
Always enable use of HW logical contexts to preserve GPU state between
batches when the kernel supports such constructs, continuing to enforce
the required support for gen6+.

At runtime, this effectively removes the BRW_NEW_CONTEXT flag (and the
upload of invariant state) from the start of every batch for any kernel
supporting contexts. So long as the older atoms are correctly listening
to the right flag (NEW_CONTEXT rather than NEW_BATCH) this should
eliminate a few redundant state uploads for the older platforms.

No piglits were harmed on ctg and ilk, both with and without logical
contexts.

Cc: Jason Ekstrand 
Cc: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_context.c | 29 ++---
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 126c187f62..9e0f875b27 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -979,22 +979,21 @@ brwCreateContext(gl_api api,
 
intel_batchbuffer_init(brw);
 
-   if (devinfo->gen >= 6) {
-  /* Create a new hardware context.  Using a hardware context means that
-   * our GPU state will be saved/restored on context switch, allowing us
-   * to assume that the GPU is in the same state we left it in.
-   *
-   * This is required for transform feedback buffer offsets, query objects,
-   * and also allows us to reduce how much state we have to emit.
-   */
-  brw->hw_ctx = brw_create_hw_context(brw->bufmgr);
-
-  if (!brw->hw_ctx) {
- fprintf(stderr, "Failed to create hardware context.\n");
- intelDestroyContext(driContextPriv);
- return false;
-  }
+   /* Create a new hardware context.  Using a hardware context means that
+* our GPU state will be saved/restored on context switch, allowing us
+* to assume that the GPU is in the same state we left it in.
+*
+* This is required for transform feedback buffer offsets, query objects,
+* and also allows us to reduce how much state we have to emit.
+*/
+   brw->hw_ctx = brw_create_hw_context(brw->bufmgr);
+   if (!brw->hw_ctx && devinfo->gen >= 6) {
+  fprintf(stderr, "Failed to create hardware context.\n");
+  intelDestroyContext(driContextPriv);
+  return false;
+   }
 
+   if (brw->hw_ctx) {
   int hw_priority = BRW_CONTEXT_MEDIUM_PRIORITY;
   if (ctx_config->attribute_mask & __DRIVER_CONTEXT_ATTRIB_PRIORITY) {
  switch (ctx_config->priority) {
-- 
2.15.1

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[Mesa-dev] [PATCH 2/2] RFC i965: Share the GTT between non-robust contexts

2017-12-15 Thread Chris Wilson 
Every client (everyone instance that opens /dev/dri/card0 or the render
nodes), receives a unique per-process GTT (where supported by the
hardware, unfortunately that means only Broadwell and later). Every
context created by each client, in turns receives its own unique ppGTT.
This is overkill in terms of allocations and tracking, both in the
kernel and in the hardware, as we could be sharing the per-client GTT
amongst all of its contexts. The downside is that context segregation is
reduced, a stray write from one context may affect another, and so we
must honour any client requests that require robust segregation (e.g.
ARB_robustness).

Signed-off-by: Chris Wilson 
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c  | 23 +--
 src/mesa/drivers/dri/i965/brw_bufmgr.h  |  2 +-
 src/mesa/drivers/dri/i965/brw_context.c |  2 +-
 3 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 52b5bf97a1..d8a9635f5d 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -1297,13 +1297,24 @@ init_cache_buckets(struct brw_bufmgr *bufmgr)
 }
 
 uint32_t
-brw_create_hw_context(struct brw_bufmgr *bufmgr)
+brw_create_hw_context(struct brw_bufmgr *bufmgr, unsigned int flags)
 {
-   struct drm_i915_gem_context_create create = { };
-   int ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, );
-   if (ret != 0) {
-  DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno));
-  return 0;
+   struct local_i915_gem_context_create_v2 {
+  uint32_t ctx_id; /* out */
+  uint32_t flags;
+#define I915_GEM_CONTEXT_SHARE_GTT 0x1
+  uint32_t share_ctx;
+  uint32_t pad;
+   } create =  { };
+#define LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE  DRM_IOWR (DRM_COMMAND_BASE + 
DRM_I915_GEM_CONTEXT_CREATE, struct local_i915_gem_context_create_v2)
+
+   if (!(flags & __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS))
+  create.flags |= I915_GEM_CONTEXT_SHARE_GTT;
+
+   if (drmIoctl(bufmgr->fd, LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE, )) {
+  create.flags = 0;
+  if (drmIoctl(bufmgr->fd, LOCAL_IOCTL_I915_GEM_CONTEXT_CREATE, ))
+ return 0;
}
 
return create.ctx_id;
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 0ae541cda0..f5191aff76 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -321,7 +321,7 @@ void brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr);
 
 int brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns);
 
-uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr);
+uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr, unsigned int flags);
 
 #define BRW_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
 #define BRW_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 9e0f875b27..e374236b6b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -986,7 +986,7 @@ brwCreateContext(gl_api api,
 * This is required for transform feedback buffer offsets, query objects,
 * and also allows us to reduce how much state we have to emit.
 */
-   brw->hw_ctx = brw_create_hw_context(brw->bufmgr);
+   brw->hw_ctx = brw_create_hw_context(brw->bufmgr, ctx_config->flags);
if (!brw->hw_ctx && devinfo->gen >= 6) {
   fprintf(stderr, "Failed to create hardware context.\n");
   intelDestroyContext(driContextPriv);
-- 
2.15.1

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[Mesa-dev] travis-ci: meson build expects LLVM 5.0, but travis profile provides 3.9

2017-12-15 Thread Gert Wollny 
Currently, the first build fails with 

  meson encountered an error in file meson.build, line 976, column 2:
  Could not generate link_args for config-tool.
  llvm-config: error: libLLVM-5.0.so is missing

https://travis-ci.org/gerddie/mesa/jobs/316902885

Best, 
Gert

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Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

2017-12-15 Thread Rob Clark 
On Fri, Dec 15, 2017 at 4:41 AM, Nicolai Hähnle  wrote:
> On 15.12.2017 00:56, Rob Clark wrote:
>>
>> On Wed, Dec 6, 2017 at 3:31 PM, Ian Romanick  wrote:
>>>
>>> On 12/05/2017 08:25 AM, Ilia Mirkin wrote:

 On Tue, Dec 5, 2017 at 8:18 AM, Emil Velikov 
 wrote:
>
> Hi Rob,
>
> On 5 December 2017 at 12:54, Rob Clark  wrote:
>>
>> This is a bit sad/annoying.  But with current GPU firmware (at least
>> on
>> a5xx) we can support both draw-indirect and base-instance.  But we
>> can't
>> support draw-indirect with a non-zero base-instance specified.  So add
>> a
>> driconf option to hide the extension from games that are known to use
>> both.
>>
>> Signed-off-by: Rob Clark 
>> ---
>> Tbh, I'm also not really sure what to do when/if we got updated
>> firmware
>> which handled draw-indirect with base-instance, since we'd need to
>> make
>> this option conditional on fw version.  For STK that probably isn't a
>> big deal since it doesn't use draw-indirect in a particularly useful
>> way
>> (the indirect buffer is generated on CPU).
>>
> Couldn't freedreno just return 0 for PIPE_CAP_DRAW_INDIRECT (aka
> disable the extension) as it detects buggy FW?
> This is what radeons have been doing as they encounter iffy firmware or
> LLVM.
>
> AFAICT freedreno doesn't do GL 4.0 or GLES 3.1 so one should be safe.


 Rob is this -><- close to ES 3.1, so that's not a great option.
>>>
>>>
>>> And I don't suppose there's a way to get updated firmware?  i965 has
>>> similar sorts of cases where higher versions are disabled due to missing
>>> kernel features.
>>>
>>
>> so after r/e the instruction set for the CP microcontrollers and
>> writing a disassembler and assembler[1], and figuring out how the fw
>> handles CP_DRAW_INDIRECT and CP_DRAW_INDX_INDIRECT packets, I've come
>> to the conclusion that the issue isn't actually with draw-indirect vs
>> base-instance (at least not w/ the fw from my pixel2 which md5sum
>> claims is the same as what is in linux-firmware.. it is possible that
>> I was using an earlier version of the fw before when I came to this
>> conclusion).  On the plus side, the PFP/ME microcontrollers that parse
>> the cmdstream are pretty neat and I learned some useful stuff along
>> the way.
>>
>> But thinking a bit about how stk is using GL_MAP_PERSISTENT_BIT to map
>> and update the draw-indirect buffers, it seems to me there are plenty
>> of ways this can go wrong w/ tilers (and even more when you throw
>> re-ordering into the mix).  Possibly I should disable reordering when
>> the indirect buffer is mapped w/ PERSISTENT bit, although for games
>> like stk this is probably counter-productive vs just hiding the
>> draw-indirect extension.. for games that actually use the GPU to write
>> the draw-indirect buffer it shouldn't be a problem.  So I think a
>> driconf patch like this probably still ends up being useful in the
>> end.
>
>
> Can you detail a bit what you think could go wrong? I believe that the
> intention of the GL spec is that reordering in tilers should be possible at
> least for buffers that are mapped PERSISTENT but not COHERENT.
>
> You may only have to block reordering if the buffer is mapped both
> PERSISTENT *and* COHERENT -- and even then, reordering is probably possible.
>
> Granted, the spec is unclear as usual when it comes to these memory
> synchronization issues -- the description of the MAP_COHERENT_BIT in section
> 6.2 does not mention WAR hazards (in particular, Write by client after Read
> by server) -- but perhaps that can be fixed.
>
> To go into a bit more detail, what I suspect you're worried about is
> applications doing stuff like:
>
> 1. Write to indirect buffer (persistently & coherently mapped)
> 2. Draw*Indirect
> 3. Write to the same location in the indirect buffer
> 4. Draw*Indirect
>
> ... but this is bound to fail with "normal" GPUs (like ours) as well.
> Perhaps you have a different scenario in mind?

yeah, this was basically the scenario I had in mind.. although I'm
perhaps more aggressive in deferring rendering, to the point of
re-ordering draws if unnecessary fbo switches are made.  Normally I
track which buffers are read and written in a given batch (draw pass)
in order to preserve correctness (and in some cases shadowing or doing
a staging transfer to update buffers/textures to avoid splitting a
batch).  Perhaps it is only an issue w/ persistent+coherent, but w/
cpu updating buffer without driver knowing when is kind of
sub-optimal.

I'm thinking I do need to keep track when there are outstanding
coherent+persistent transfers mapped and switch off some of the
cleverness.

All the same, the way stk uses draw-indirect is not useful and it
would be better to shut it off, at least for me.  Although perhaps

[Mesa-dev] [PATCH] anv: fix bug when VK_REMAINING_ARRAY_LAYERS is used in vkCmdClearAttachments()

2017-12-15 Thread Samuel Iglesias Gonsálvez 
Blorp was not supporting the use of the constant VK_REMAINING_ARRAY_LAYERS
(whose value is ~0) in the VkClearRect structure. If we receive it, we need
to calculate the layer count as the image layers count minus the base array
layer.

Signed-off-by: Samuel Iglesias Gonsálvez 
---
 src/intel/vulkan/anv_blorp.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index e244468e03..4ab4458246 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -989,10 +989,15 @@ clear_color_attachment(struct anv_cmd_buffer *cmd_buffer,
for (uint32_t r = 0; r < rectCount; ++r) {
   const VkOffset2D offset = pRects[r].rect.offset;
   const VkExtent2D extent = pRects[r].rect.extent;
+  unsigned layer_count =
+ anv_get_layerCount(
+cmd_buffer->state.framebuffer->attachments[att_idx]->image,
+[r]);
+
   blorp_clear_attachments(batch, binding_table,
   ISL_FORMAT_UNSUPPORTED, pass_att->samples,
   pRects[r].baseArrayLayer,
-  pRects[r].layerCount,
+  layer_count,
   offset.x, offset.y,
   offset.x + extent.width, offset.y + 
extent.height,
   true, clear_color, false, 0.0f, 0, 0);
@@ -1059,11 +1064,16 @@ clear_depth_stencil_attachment(struct anv_cmd_buffer 
*cmd_buffer,
for (uint32_t r = 0; r < rectCount; ++r) {
   const VkOffset2D offset = pRects[r].rect.offset;
   const VkExtent2D extent = pRects[r].rect.extent;
+  unsigned layer_count =
+ anv_get_layerCount(
+cmd_buffer->state.framebuffer->attachments[att_idx]->image,
+[r]);
+
   VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
   blorp_clear_attachments(batch, binding_table,
   depth_format, pass_att->samples,
   pRects[r].baseArrayLayer,
-  pRects[r].layerCount,
+  layer_count,
   offset.x, offset.y,
   offset.x + extent.width, offset.y + 
extent.height,
   false, color_value,
-- 
2.14.1

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Re: [Mesa-dev] [PATCH] util: scons: wire up the sha1 test

2017-12-15 Thread Andres Gomez 
Ugh! How did we miss this?

This is:

Reviewed-by: Andres Gomez 

On Thu, 2017-12-14 at 19:10 +, Emil Velikov wrote:
> From: Emil Velikov 
> 
> Cc: 
> Fixes: 513d7ffa23d ("util: Add a SHA1 unit test program")
> Signed-off-by: Emil Velikov 
> ---
> We want this and the original commit for stable, to catch any 
> breakage that may happen.
> 
>  src/util/SConscript | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/src/util/SConscript b/src/util/SConscript
> index 0c3c98a5f4c..66a0d1c04ff 100644
> --- a/src/util/SConscript
> +++ b/src/util/SConscript
> @@ -63,3 +63,10 @@ roundeven_test = env.Program(
>  source = ['roundeven_test.c'],
>  )
>  env.UnitTest("roundeven_test", roundeven_test)
> +
> +env.Prepend(LIBS = [mesautil])
> +mesa_sha1_test = env.Program(
> +target = 'mesa-sha1_test',
> +source = ['mesa-sha1_test.c'],
> +)
> +env.UnitTest("mesa-sha1_test", mesa_sha1_test)
-- 
Br,

Andres
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Re: [Mesa-dev] [RFC libdrm 0/5] Move alloc_handle_t from gralloc impls.

2017-12-15 Thread Robert Foss 
+Kalyan Kondapally

On Wed, 2017-12-13 at 15:02 -0800, Gurchetan Singh wrote:
> Hi Robert,
> 
> Thanks for looking into this!  We need to decide if we want:
> 
> (1) A common struct that implementations can subclass, i.e:
> 
> struct blah_gralloc_handle {
> alloc_handle_t alloc_handle;
> int x, y, z;
> 
> } 
> 
> (2) An accessor library that vendors can implement, i.e:
> 
> struct drmAndroidHandleInfo {  
>uint32_t (*get_fourcc)(buffer_handle_t handle); 
>uint32_t (*get_stride)(buffer_handle_t handle, uint32_t plane);
>uint32_t (*get_offsets)(buffer_handle_t handle, uint32_t plane);
>uint64_t (*get_modifier)(buffer_handle_t handle);
> };
> 
> From my perspective as someone who has to maintain the minigbm
> gralloc implementation, (2) is preferable since:
> 
> a) We really don't have a need for fields like data_owner, void
> *data, etc.  Also, minigbm puts per plane fds, strides, offsets into
> the handle.  Separating the information for the first plane (for
> the alloc_handle_t) and then rest of the planes would be annoying.
> 
> b) we can avoid the struct within a struct that happens when we
> subclass, since alignment/padding issues often pop up during
> serialization/de-serialization.  Using __attribute__((aligned(xx)))
> is less portable than maintaining a POD struct.
> 
> c) IMO creating the handle should be left to the gralloc
> implementation.  Having accessor functions clearly defines what we
> need from libdrm -- to make up for shortcomings of the gralloc API
> for DRM/KMS use cases. 
> 

To me that is pretty persuasive, however I maintain 0 of these
implementations, so I'd like to get some input from Rob Herring
(gbm_gralloc) and Kalyan Kondapally (intel-minigbm) too.

The previous related discussion can be found here:
https://patchwork.freedesktop.org/patch/190406/


Rob.

> 
> On Wed, Dec 13, 2017 at 9:30 AM, Robert Foss  om> wrote:
> > This series moves {gbm,drm,cros}_gralloc_handle_t struct to libdrm,
> > since at least 4 implementations exist, and share a lot of
> > contents.
> > The idea is to keep the common stuff defined in one place, and
> > libdrm
> > is the common codebase to all of these platforms.
> > 
> > Additionally, having this struct defined in libdrm will make it
> > easier for mesa and grallocs to communicate.
> > 
> > Curretly missing is:
> >  - Planar formats
> >  - Get/Set functions
> > 
> > 
> > Planar formats
> > --
> > Support for planar formats is needed, but has not been added
> > yet, mostly since this was not already implemented in
> > {gbm,drm}_gralloc
> > and the fact the having at least initial backwards compatability
> > would
> > be nice. Anonymous unions can of course be used later on to provide
> > backwards compatability if so desired.
> > 
> > 
> > Get/Set functions
> > -
> > During the previous discussion[1] one suggestion was to add
> > accessor
> > functions. In this RFC I've only provided a alloc_handle_create()
> > function.
> > 
> > The Get/Set functions have not been added yet, I was hoping for
> > some
> > conclusive arguments for them being adeded.
> > 
> > Lastly it was suggested by Rob Herring that having a fourcc<-
> > >android
> > pixel format conversion function would be useful.
> > 
> > 
> > [1] https://lists.freedesktop.org/archives/mesa-dev/2017-November/1
> > 78199.html
> > 
> > Robert Foss (5):
> >   android: Move gralloc handle struct to libdrm
> >   android: Add version variable to alloc_handle_t
> >   android: Mark alloc_handle_t magic variable as const
> >   android: Remove member name from alloc_handle_t
> >   android: Change alloc_handle_t format from Android format to
> > fourcc
> > 
> >  Android.mk   |  8 +++-
> >  Makefile.sources |  3 ++
> >  android/alloc_handle.h   | 87
> > 
> >  android/gralloc_drm_handle.h |  1 +
> >  4 files changed, 97 insertions(+), 2 deletions(-)
> >  create mode 100644 android/alloc_handle.h
> >  create mode 12 android/gralloc_drm_handle.h
> > 
> > --
> > 2.14.1
> > 
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 
> 

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Re: [Mesa-dev] [PATCH 3/3] radeonsi: don't call force_dcc_off for buffers

2017-12-15 Thread Michel Dänzer 
On 2017-12-12 10:47 PM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> This was undefined yet harmless behavior in LLVM.
> Not anymore - it causes a hang now.
> 
> Cc: 17.3 

Not sure about backporting this to the 17.3 branch, since that doesn't
support LLVM 6. OTOH might be nice to add some bugzilla references.

Anyway,

Tested-by: Michel Dänzer 


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [Mesa-dev] [PATCH] drirc: add option to disable ARB_draw_indirect

2017-12-15 Thread Nicolai Hähnle 

On 15.12.2017 00:56, Rob Clark wrote:

On Wed, Dec 6, 2017 at 3:31 PM, Ian Romanick  wrote:

On 12/05/2017 08:25 AM, Ilia Mirkin wrote:

On Tue, Dec 5, 2017 at 8:18 AM, Emil Velikov  wrote:

Hi Rob,

On 5 December 2017 at 12:54, Rob Clark  wrote:

This is a bit sad/annoying.  But with current GPU firmware (at least on
a5xx) we can support both draw-indirect and base-instance.  But we can't
support draw-indirect with a non-zero base-instance specified.  So add a
driconf option to hide the extension from games that are known to use
both.

Signed-off-by: Rob Clark 
---
Tbh, I'm also not really sure what to do when/if we got updated firmware
which handled draw-indirect with base-instance, since we'd need to make
this option conditional on fw version.  For STK that probably isn't a
big deal since it doesn't use draw-indirect in a particularly useful way
(the indirect buffer is generated on CPU).


Couldn't freedreno just return 0 for PIPE_CAP_DRAW_INDIRECT (aka
disable the extension) as it detects buggy FW?
This is what radeons have been doing as they encounter iffy firmware or LLVM.

AFAICT freedreno doesn't do GL 4.0 or GLES 3.1 so one should be safe.


Rob is this -><- close to ES 3.1, so that's not a great option.


And I don't suppose there's a way to get updated firmware?  i965 has
similar sorts of cases where higher versions are disabled due to missing
kernel features.



so after r/e the instruction set for the CP microcontrollers and
writing a disassembler and assembler[1], and figuring out how the fw
handles CP_DRAW_INDIRECT and CP_DRAW_INDX_INDIRECT packets, I've come
to the conclusion that the issue isn't actually with draw-indirect vs
base-instance (at least not w/ the fw from my pixel2 which md5sum
claims is the same as what is in linux-firmware.. it is possible that
I was using an earlier version of the fw before when I came to this
conclusion).  On the plus side, the PFP/ME microcontrollers that parse
the cmdstream are pretty neat and I learned some useful stuff along
the way.

But thinking a bit about how stk is using GL_MAP_PERSISTENT_BIT to map
and update the draw-indirect buffers, it seems to me there are plenty
of ways this can go wrong w/ tilers (and even more when you throw
re-ordering into the mix).  Possibly I should disable reordering when
the indirect buffer is mapped w/ PERSISTENT bit, although for games
like stk this is probably counter-productive vs just hiding the
draw-indirect extension.. for games that actually use the GPU to write
the draw-indirect buffer it shouldn't be a problem.  So I think a
driconf patch like this probably still ends up being useful in the
end.


Can you detail a bit what you think could go wrong? I believe that the 
intention of the GL spec is that reordering in tilers should be possible 
at least for buffers that are mapped PERSISTENT but not COHERENT.


You may only have to block reordering if the buffer is mapped both 
PERSISTENT *and* COHERENT -- and even then, reordering is probably possible.


Granted, the spec is unclear as usual when it comes to these memory 
synchronization issues -- the description of the MAP_COHERENT_BIT in 
section 6.2 does not mention WAR hazards (in particular, Write by client 
after Read by server) -- but perhaps that can be fixed.


To go into a bit more detail, what I suspect you're worried about is 
applications doing stuff like:


1. Write to indirect buffer (persistently & coherently mapped)
2. Draw*Indirect
3. Write to the same location in the indirect buffer
4. Draw*Indirect

... but this is bound to fail with "normal" GPUs (like ours) as well. 
Perhaps you have a different scenario in mind?


Cheers,
Nicolai
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