Re: [Mesa-dev] [PATCH] egl/android: Fix build break with dri2_initialize_android _EGLDisplay parameter

[Tapani Pälli]

Reviewed-by: Tapani Pälli 

On 01/03/2018 06:28 PM, Rob Herring wrote:

Commit 2f421651aca9 ("egl: let each platform decided how to handle
LIBGL_ALWAYS_SOFTWARE") broke the build due to copy-n-paste of misnamed
function parameter.:

src/egl/drivers/dri2/platform_android.c:1183:8: error: use of undeclared 
identifier 'disp'

Rather than just fixing 'disp', rename the function parameter 'dpy' to
'disp' to align with the other EGL platforms' implementations.

Fixes: 2f421651aca9 ("egl: let each platform decided how to handle 
LIBGL_ALWAYS_SOFTWARE")
Cc: Eric Engestrom 
Signed-off-by: Rob Herring 
---
  src/egl/drivers/dri2/platform_android.c | 30 +++---
  1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 34e3ef66bfeb..4f25cb746915 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -1173,7 +1173,7 @@ static const __DRIextension 
*droid_image_loader_extensions[] = {
  };
  
  EGLBoolean

-dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
+dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *disp)
  {
 struct dri2_egl_display *dri2_dpy;
 const char *err;
@@ -1197,7 +1197,7 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
goto cleanup;
 }
  
-   dpy->DriverData = (void *) dri2_dpy;

+   disp->DriverData = (void *) dri2_dpy;
  
 dri2_dpy->fd = droid_open_device(dri2_dpy);

 if (dri2_dpy->fd < 0) {
@@ -1217,43 +1217,43 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay 
*dpy)
  * the __DRI_DRI2_LOADER extension */
 if (!dri2_dpy->is_render_node) {
dri2_dpy->loader_extensions = droid_dri2_loader_extensions;
-  if (!dri2_load_driver(dpy)) {
+  if (!dri2_load_driver(disp)) {
   err = "DRI2: failed to load driver";
   goto cleanup;
}
 } else {
dri2_dpy->loader_extensions = droid_image_loader_extensions;
-  if (!dri2_load_driver_dri3(dpy)) {
+  if (!dri2_load_driver_dri3(disp)) {
   err = "DRI3: failed to load driver";
   goto cleanup;
}
 }
  
-   if (!dri2_create_screen(dpy)) {

+   if (!dri2_create_screen(disp)) {
err = "DRI2: failed to create screen";
goto cleanup;
 }
  
-   if (!dri2_setup_extensions(dpy)) {

+   if (!dri2_setup_extensions(disp)) {
err = "DRI2: failed to setup extensions";
goto cleanup;
 }
  
-   dri2_setup_screen(dpy);

+   dri2_setup_screen(disp);
  
-   if (!droid_add_configs_for_visuals(drv, dpy)) {

+   if (!droid_add_configs_for_visuals(drv, disp)) {
err = "DRI2: failed to add configs";
goto cleanup;
 }
  
-   dpy->Extensions.ANDROID_framebuffer_target = EGL_TRUE;

-   dpy->Extensions.ANDROID_image_native_buffer = EGL_TRUE;
-   dpy->Extensions.ANDROID_recordable = EGL_TRUE;
-   dpy->Extensions.EXT_buffer_age = EGL_TRUE;
+   disp->Extensions.ANDROID_framebuffer_target = EGL_TRUE;
+   disp->Extensions.ANDROID_image_native_buffer = EGL_TRUE;
+   disp->Extensions.ANDROID_recordable = EGL_TRUE;
+   disp->Extensions.EXT_buffer_age = EGL_TRUE;
  #if ANDROID_API_LEVEL >= 23
-   dpy->Extensions.KHR_partial_update = EGL_TRUE;
+   disp->Extensions.KHR_partial_update = EGL_TRUE;
  #endif
-   dpy->Extensions.KHR_image = EGL_TRUE;
+   disp->Extensions.KHR_image = EGL_TRUE;
  
 /* Fill vtbl last to prevent accidentally calling virtual function during

  * initialization.
@@ -1263,6 +1263,6 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
 return EGL_TRUE;
  
  cleanup:

-   dri2_display_destroy(dpy);
+   dri2_display_destroy(disp);
 return _eglError(EGL_NOT_INITIALIZED, err);
  }


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Re: [Mesa-dev] Radeonsi NIR tess support V3

[Dieter Nützel]

Hello Tim,

this third version didn't make it into Patchwork.
Do you have a pointer?

Thanks and a
Happy New Year
to you!

Dieter

Am 03.01.2018 06:04, schrieb Timothy Arceri:

V3:
- rebased on recent changes/fixes

V2:
- addressed feedback from Nicolai

The following patches lack a reviewed-by:

1-3, 5, 20
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Re: [Mesa-dev] [PATCH 1/1] nir: Use a freelist in nir_opt_dce to avoid spamming ralloc

[Dieter Nützel]

Hello to all of you and a

Happy New Year! ;-)

Any thoughts about this, Marek, Nicolai?
I'm running this for four weeks without any hickup, now.

Thanks,
Dieter

Am 06.12.2017 09:56, schrieb Dieter Nützel:

Tested-by: Dieter Nützel 

Dieter

Am 02.12.2017 15:49, schrieb Thomas Helland:

Also, allocate worklist_elem in groups of 20, to reduce the burden of
allocation. Do not use rzalloc, as there is no need. This lets us drop
the number of calls to ralloc from aproximately 10% of all calls to
ralloc(130 000 calls), down to a mere 2000 calls to ralloc_array_size.
This cuts the runtime of shader-db by 1%, while at the same time
reducing the number of stalled cycles, executed cycles, and executed
instructions by about 1 % as reported by perf. I did a five-run
benchmark pre and post and got a statistical variance less than 0.1% 
pre
and post. This was with i965's ir validation polluting the benchmark, 
so

the numbers are even better in release builds.

Performance change as found with perf-diff:
4.74% -0.23%  libc-2.26.so[.] _int_malloc
1.88% -0.21%  libc-2.26.so[.] malloc
2.27% +0.16%  libmesa_dri_drivers.so  [.] match_value.part.7
2.95% -0.12%  libc-2.26.so[.] _int_free
  +0.11%  libmesa_dri_drivers.so  [.] worklist_push
1.22% -0.08%  libc-2.26.so[.] malloc_consolidate
0.16% -0.06%  libmesa_dri_drivers.so  [.] mark_live_cb
1.21% +0.06%  libmesa_dri_drivers.so  [.] match_expression.part.6
0.75% -0.05%  libc-2.26.so[.] cfree@GLIBC_2.2.5
0.50% -0.05%  libmesa_dri_drivers.so  [.] ralloc_size
0.57% +0.04%  libmesa_dri_drivers.so  [.] nir_replace_instr
1.29% -0.04%  libmesa_dri_drivers.so  [.] unsafe_free
---
 src/compiler/nir/nir_opt_dce.c | 47 
--

 1 file changed, 32 insertions(+), 15 deletions(-)

diff --git a/src/compiler/nir/nir_opt_dce.c 
b/src/compiler/nir/nir_opt_dce.c

index 5cefba3a72..f9285fe4ac 100644
--- a/src/compiler/nir/nir_opt_dce.c
+++ b/src/compiler/nir/nir_opt_dce.c
@@ -29,32 +29,46 @@

 /* SSA-based mark-and-sweep dead code elimination */

+typedef struct {
+   struct exec_list *worklist;
+   struct exec_list *free_nodes;
+} worklist;
+
 typedef struct {
struct exec_node node;
nir_instr *instr;
 } worklist_elem;

 static void
-worklist_push(struct exec_list *worklist, nir_instr *instr)
+worklist_push(worklist *worklist, nir_instr *instr)
 {
-   worklist_elem *elem = ralloc(worklist, worklist_elem);
+   if (exec_list_is_empty(worklist->free_nodes)) {
+  worklist_elem *elements = ralloc_array(worklist, worklist_elem, 
20);

+  for (int i = 0; i < 20; i++)
+ exec_list_push_tail(worklist->free_nodes, 
[i].node);

+   }
+
+   struct exec_node *node = exec_list_pop_head(worklist->free_nodes);
+   worklist_elem *elem = exec_node_data(worklist_elem, node, node);
elem->instr = instr;
instr->pass_flags = 1;
-   exec_list_push_tail(worklist, >node);
+   exec_list_push_tail(worklist->worklist, >node);
 }

 static nir_instr *
-worklist_pop(struct exec_list *worklist)
+worklist_pop(worklist *worklist)
 {
-   struct exec_node *node = exec_list_pop_head(worklist);
+
+   struct exec_node *node = exec_list_pop_head(worklist->worklist);
worklist_elem *elem = exec_node_data(worklist_elem, node, node);
+   exec_list_push_head(worklist->free_nodes, node);
return elem->instr;
 }

 static bool
 mark_live_cb(nir_src *src, void *_state)
 {
-   struct exec_list *worklist = (struct exec_list *) _state;
+   worklist *worklist = _state;

if (src->is_ssa && !src->ssa->parent_instr->pass_flags) {
   worklist_push(worklist, src->ssa->parent_instr);
@@ -64,7 +78,7 @@ mark_live_cb(nir_src *src, void *_state)
 }

 static void
-init_instr(nir_instr *instr, struct exec_list *worklist)
+init_instr(nir_instr *instr, worklist *worklist)
 {
nir_alu_instr *alu_instr;
nir_intrinsic_instr *intrin_instr;
@@ -113,7 +127,7 @@ init_instr(nir_instr *instr, struct exec_list 
*worklist)

 }

 static bool
-init_block(nir_block *block, struct exec_list *worklist)
+init_block(nir_block *block, worklist *worklist)
 {
nir_foreach_instr(instr, block)
   init_instr(instr, worklist);
@@ -131,19 +145,22 @@ init_block(nir_block *block, struct exec_list 
*worklist)

 static bool
 nir_opt_dce_impl(nir_function_impl *impl)
 {
-   struct exec_list *worklist = rzalloc(NULL, struct exec_list);
-   exec_list_make_empty(worklist);
+   worklist *wl = ralloc(NULL, worklist);
+   wl->free_nodes = ralloc(wl, struct exec_list);
+   wl->worklist = ralloc(wl, struct exec_list);
+   exec_list_make_empty(wl->free_nodes);
+   exec_list_make_empty(wl->worklist);

nir_foreach_block(block, impl) {
-  init_block(block, worklist);
+  init_block(block, wl);
}

-   while (!exec_list_is_empty(worklist)) {
-  nir_instr *instr = worklist_pop(worklist);
-  nir_foreach_src(instr, mark_live_cb, worklist);
+   while 

Re: [Mesa-dev] [PATCH] radv: Add support for ETC2 textures.

[Roland Scheidegger]

I thought the reason they are included nowadays in hardware is because
they are required by gl 4.3 and of course GLES (I think they were added
in GL via ES compatibility).
Of course, for proper gles (3.2) you also need astc, but still it looks
to me like these formats are here to stay.

Roland


Am 04.01.2018 um 04:43 schrieb Mao, David:
> Hi Bas,
> AMD does not support ETC2 officially on the GFX9. 
> It would be risky for Radv to export that feature for gfx9 family. 
> Anyway, t’s just a heads up, and it is up to you to make the final call. 
> FYI: AMDVLK and proprietary AMD vulkan driver don’t’ support that. 
> 
> Thanks.
> Best Regards,
> David
> 
>> On Jan 4, 2018, at 8:38 AM, Bas Nieuwenhuizen  
>> wrote:
>>
>> Was surprised that is even supported by Vega.
>> ---
>> src/amd/vulkan/radv_device.c|  4 +++-
>> src/amd/vulkan/radv_formats.c   | 36 
>> src/amd/vulkan/vk_format_layout.csv | 20 ++--
>> 3 files changed, 49 insertions(+), 11 deletions(-)
>>
>> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
>> index cbf8f5cf49..bbed9f0ec2 100644
>> --- a/src/amd/vulkan/radv_device.c
>> +++ b/src/amd/vulkan/radv_device.c
>> @@ -530,6 +530,7 @@ void radv_GetPhysicalDeviceFeatures(
>>  VkPhysicalDevicephysicalDevice,
>>  VkPhysicalDeviceFeatures*   pFeatures)
>> {
>> +RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
>>  memset(pFeatures, 0, sizeof(*pFeatures));
>>
>>  *pFeatures = (VkPhysicalDeviceFeatures) {
>> @@ -553,7 +554,8 @@ void radv_GetPhysicalDeviceFeatures(
>>  .alphaToOne   = true,
>>  .multiViewport= true,
>>  .samplerAnisotropy= true,
>> -.textureCompressionETC2   = false,
>> +.textureCompressionETC2   = 
>> pdevice->rad_info.chip_class >= GFX9 ||
>> +
>> pdevice->rad_info.family == CHIP_STONEY,
>>  .textureCompressionASTC_LDR   = false,
>>  .textureCompressionBC = true,
>>  .occlusionQueryPrecise= true,
>> diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
>> index c008c1bae6..4b0b4c8320 100644
>> --- a/src/amd/vulkan/radv_formats.c
>> +++ b/src/amd/vulkan/radv_formats.c
>> @@ -224,6 +224,28 @@ uint32_t radv_translate_tex_dataformat(VkFormat format,
>>  }
>>  }
>>
>> +if (desc->layout == VK_FORMAT_LAYOUT_ETC) {
>> +switch (format) {
>> +case VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK:
>> +case VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK:
>> +return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
>> +case VK_FORMAT_ETC2_R8G8B8A1_UNORM_BLOCK:
>> +case VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK:
>> +return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
>> +case VK_FORMAT_ETC2_R8G8B8A8_UNORM_BLOCK:
>> +case VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK:
>> +return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
>> +case VK_FORMAT_EAC_R11_UNORM_BLOCK:
>> +case VK_FORMAT_EAC_R11_SNORM_BLOCK:
>> +return V_008F14_IMG_DATA_FORMAT_ETC2_R;
>> +case VK_FORMAT_EAC_R11G11_UNORM_BLOCK:
>> +case VK_FORMAT_EAC_R11G11_SNORM_BLOCK:
>> +return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
>> +default:
>> +break;
>> +}
>> +}
>> +
>>  if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
>>  return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
>>  } else if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32) {
>> @@ -351,10 +373,15 @@ uint32_t radv_translate_tex_numformat(VkFormat format,
>>  case VK_FORMAT_BC2_SRGB_BLOCK:
>>  case VK_FORMAT_BC3_SRGB_BLOCK:
>>  case VK_FORMAT_BC7_SRGB_BLOCK:
>> +case VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK:
>> +case VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK:
>> +case VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK:
>>  return V_008F14_IMG_NUM_FORMAT_SRGB;
>>  case VK_FORMAT_BC4_SNORM_BLOCK:
>>  case VK_FORMAT_BC5_SNORM_BLOCK:
>>  case VK_FORMAT_BC6H_SFLOAT_BLOCK:
>> +case VK_FORMAT_EAC_R11_SNORM_BLOCK:
>> +case VK_FORMAT_EAC_R11G11_SNORM_BLOCK:
>>  return V_008F14_IMG_NUM_FORMAT_SNORM;
>>  default:
>>  return V_008F14_IMG_NUM_FORMAT_UNORM;
>> @@ 

Re: [Mesa-dev] [PATCH 6/6] r600: don't emit tes samplers/views when tes isn't active

[Roland Scheidegger]

Thanks for testing. I fixed the whitespace, and resent patch 4 due to a bug.

Roland

Am 03.01.2018 um 08:29 schrieb Konstantin Kharlamov:
> Sorry, I don't have an expertise to give a r-b, but here's my t-b :) I
> found no statistically significant changes at "the big keybench" of
> `vblank_mode=0 ./xonotic-linux64-glx`.
> 
> But note, there's a trailing whitespace at patch 5 (first "+" after "@@
> -1267,6 +1268,20 @@"), and patch 6 (first "+" after "@@ -1723,6 +1723,21
> @@").
> 
> Tested-by: Konstantin Kharlamov 
> 
> On 03.01.2018 05:25, srol...@vmware.com wrote:
>> From: Roland Scheidegger 
>>
>> Similar to const buffers. The driver must not emit any tes-related
>> state if tes
>> is disabled, since the hw slots are all shared by VS, therefore it would
>> overwrite them (the mesa state tracker might not do this, but it would be
>> perfectly legal to do so).
>> Nevertheless I think the dirty state tracking logic in the driver is
>> fundamentally flawed when tes is disabled/enabled, since it looks to
>> me like
>> the VS (and TES) state would not get reemitted to the correct slots
>> (if it's
>> not dirty anyway). Unless I'm missing something...
>> Theoretically, the overwrite problem could be solved by using
>> non-overlapping
>> resource slots for TES and VS (since we're not even close to using
>> half the
>> resource slots), but it wouldn't work for constant buffers nor
>> samplers, and
>> for VS would still need to propagate changes to both LS and VS, so
>> probably
>> not a useful idea.
>> Unfortunately there's zero coverage of this with piglit, since all
>> tessellation
>> shader tests are just shader_runner tests, which are unsuitable for
>> testing
>> any kind of state dependency tracking issues (so I can't even quickly
>> hack
>> something up to proove it and fix it...).
>> TCS otoh is just fine - like GS it has its own hw slots.
>> ---
>>   src/gallium/drivers/r600/evergreen_state.c   |  4 
>>   src/gallium/drivers/r600/r600_state_common.c | 15 +++
>>   2 files changed, 19 insertions(+)
>>
>> diff --git a/src/gallium/drivers/r600/evergreen_state.c
>> b/src/gallium/drivers/r600/evergreen_state.c
>> index 4cc48dfa11..fb1de9cbf4 100644
>> --- a/src/gallium/drivers/r600/evergreen_state.c
>> +++ b/src/gallium/drivers/r600/evergreen_state.c
>> @@ -2334,6 +2334,8 @@ static void
>> evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r
>>     static void evergreen_emit_tes_sampler_views(struct r600_context
>> *rctx, struct r600_atom *atom)
>>   {
>> +    if (!rctx->tes_shader)
>> +    return;
>>   evergreen_emit_sampler_views(rctx,
>> >samplers[PIPE_SHADER_TESS_EVAL].views,
>>    EG_FETCH_CONSTANTS_OFFSET_VS +
>> R600_MAX_CONST_BUFFERS, 0);
>>   }
>> @@ -2404,6 +2406,8 @@ static void
>> evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct
>>     static void evergreen_emit_tes_sampler_states(struct r600_context
>> *rctx, struct r600_atom *atom)
>>   {
>> +    if (!rctx->tes_shader)
>> +    return;
>>   evergreen_emit_sampler_states(rctx,
>> >samplers[PIPE_SHADER_TESS_EVAL], 18,
>>     R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
>>   }
>> diff --git a/src/gallium/drivers/r600/r600_state_common.c
>> b/src/gallium/drivers/r600/r600_state_common.c
>> index 4364350487..a434156c16 100644
>> --- a/src/gallium/drivers/r600/r600_state_common.c
>> +++ b/src/gallium/drivers/r600/r600_state_common.c
>> @@ -1723,6 +1723,21 @@ static bool r600_update_derived_state(struct
>> r600_context *rctx)
>>   UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
>>   }
>>   }
>> +   
>> +    /*
>> + * XXX: I believe there's some fatal flaw in the dirty state
>> logic when
>> + * enabling/disabling tes.
>> + * VS/ES share all buffer/resource/sampler slots. If TES is enabled,
>> + * it will therefore overwrite the VS slots. If it now gets
>> disabled,
>> + * the VS needs to rebind all buffer/resource/sampler slots - not
>> only
>> + * has TES overwritten the corresponding slots, but when the VS was
>> + * operating as LS the things with correpsonding dirty bits got
>> bound
>> + * to LS slots and won't reflect what is dirty as VS stage even
>> if the
>> + * TES didn't overwrite it. The story for re-enabled TES is similar.
>> + * In any case, we're not allowed to submit any TES state when
>> + * TES is disabled (the state tracker may not do this but this looks
>> + * like an optimization to me, not something which can be relied
>> on).
>> + */
>>     /* Update clip misc state. */
>>   if (clip_so_current) {
>>

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[Mesa-dev] [PATCH] anv/query: implement multiview interactions

[Iago Toral Quiroga]

From the Vulkan spec with KHX extensions:

  "If queries are used while executing a render pass instance that has
   multiview enabled, the query uses N consecutive query indices
   in the query pool (starting at query) where N is the number of bits
   set in the view mask in the subpass the query is used in.

   How the numerical results of the query are distributed among the
   queries is implementation-dependent. For example, some implementations
   may write each view's results to a distinct query, while other
   implementations may write the total result to the first query and write
   zero to the other queries. However, the sum of the results in all the
   queries must accurately reflect the total result of the query summed
   over all views. Applications can sum the results from all the queries to
   compute the total result."

In our case we only really emit a single query (in the first query index)
that stores the aggregated result for all views, but we still need to manage
availability for all the other query indices involved, even if we don't
actually use them.

This is relevant when clients call vkGetQueryPoolResults and pass all N
queries to retrieve the results. In that scenario, without this patch,
we will never see queries other than the first being available since we
never emit them.

Fixes test failures in some work-in-progress CTS multiview+query tests.
---
 src/intel/vulkan/genX_query.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 7683d0d1e3..4e6ccd73ab 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -462,6 +462,24 @@ void genX(CmdEndQuery)(
default:
   unreachable("");
}
+
+   /* When multiview is active the spec requires that N consecutive query
+* indices are used, where N is the number of active views in the subpass.
+* The spec allows that we only write the results to one of the queries
+* but we still need to manage result availability for all the query 
indices.
+* Since we only emit a single query for all active views in the
+* first index, mark the other query indices as being already available
+* with result 0.
+*/
+   if (!cmd_buffer->state.subpass || !cmd_buffer->state.subpass->view_mask)
+  return;
+
+   uint32_t num_queries = _mesa_bitcount(cmd_buffer->state.subpass->view_mask);
+   for (uint32_t i = 1; i < num_queries; i++) {
+  uint64_t *slot = pool->bo.map + (query + i) * pool->stride;
+  slot[0] = 1;
+  memset([1], 0, sizeof(uint64_t) * pool->stride);
+   }
 }
 
 #define TIMESTAMP 0x2358
-- 
2.11.0

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Re: [Mesa-dev] [PATCH] radv: Add support for ETC2 textures.

[Mao, David]

Hi Bas,
AMD does not support ETC2 officially on the GFX9. 
It would be risky for Radv to export that feature for gfx9 family. 
Anyway, t’s just a heads up, and it is up to you to make the final call. 
FYI: AMDVLK and proprietary AMD vulkan driver don’t’ support that. 

Thanks.
Best Regards,
David

> On Jan 4, 2018, at 8:38 AM, Bas Nieuwenhuizen  
> wrote:
> 
> Was surprised that is even supported by Vega.
> ---
> src/amd/vulkan/radv_device.c|  4 +++-
> src/amd/vulkan/radv_formats.c   | 36 
> src/amd/vulkan/vk_format_layout.csv | 20 ++--
> 3 files changed, 49 insertions(+), 11 deletions(-)
> 
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index cbf8f5cf49..bbed9f0ec2 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -530,6 +530,7 @@ void radv_GetPhysicalDeviceFeatures(
>   VkPhysicalDevicephysicalDevice,
>   VkPhysicalDeviceFeatures*   pFeatures)
> {
> + RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
>   memset(pFeatures, 0, sizeof(*pFeatures));
> 
>   *pFeatures = (VkPhysicalDeviceFeatures) {
> @@ -553,7 +554,8 @@ void radv_GetPhysicalDeviceFeatures(
>   .alphaToOne   = true,
>   .multiViewport= true,
>   .samplerAnisotropy= true,
> - .textureCompressionETC2   = false,
> + .textureCompressionETC2   = 
> pdevice->rad_info.chip_class >= GFX9 ||
> + 
> pdevice->rad_info.family == CHIP_STONEY,
>   .textureCompressionASTC_LDR   = false,
>   .textureCompressionBC = true,
>   .occlusionQueryPrecise= true,
> diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
> index c008c1bae6..4b0b4c8320 100644
> --- a/src/amd/vulkan/radv_formats.c
> +++ b/src/amd/vulkan/radv_formats.c
> @@ -224,6 +224,28 @@ uint32_t radv_translate_tex_dataformat(VkFormat format,
>   }
>   }
> 
> + if (desc->layout == VK_FORMAT_LAYOUT_ETC) {
> + switch (format) {
> + case VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK:
> + case VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK:
> + return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
> + case VK_FORMAT_ETC2_R8G8B8A1_UNORM_BLOCK:
> + case VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK:
> + return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
> + case VK_FORMAT_ETC2_R8G8B8A8_UNORM_BLOCK:
> + case VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK:
> + return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
> + case VK_FORMAT_EAC_R11_UNORM_BLOCK:
> + case VK_FORMAT_EAC_R11_SNORM_BLOCK:
> + return V_008F14_IMG_DATA_FORMAT_ETC2_R;
> + case VK_FORMAT_EAC_R11G11_UNORM_BLOCK:
> + case VK_FORMAT_EAC_R11G11_SNORM_BLOCK:
> + return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
> + default:
> + break;
> + }
> + }
> +
>   if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
>   return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
>   } else if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32) {
> @@ -351,10 +373,15 @@ uint32_t radv_translate_tex_numformat(VkFormat format,
>   case VK_FORMAT_BC2_SRGB_BLOCK:
>   case VK_FORMAT_BC3_SRGB_BLOCK:
>   case VK_FORMAT_BC7_SRGB_BLOCK:
> + case VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK:
> + case VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK:
> + case VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK:
>   return V_008F14_IMG_NUM_FORMAT_SRGB;
>   case VK_FORMAT_BC4_SNORM_BLOCK:
>   case VK_FORMAT_BC5_SNORM_BLOCK:
>   case VK_FORMAT_BC6H_SFLOAT_BLOCK:
> + case VK_FORMAT_EAC_R11_SNORM_BLOCK:
> + case VK_FORMAT_EAC_R11G11_SNORM_BLOCK:
>   return V_008F14_IMG_NUM_FORMAT_SNORM;
>   default:
>   return V_008F14_IMG_NUM_FORMAT_UNORM;
> @@ -557,6 +584,15 @@ radv_physical_device_get_format_properties(struct 
> radv_physical_device *physical
>   return;
>   }
> 
> + if (desc->layout == VK_FORMAT_LAYOUT_ETC &&
> + physical_device->rad_info.chip_class < GFX9 &&
> + physical_device->rad_info.family != CHIP_STONEY) {
> + out_properties->linearTilingFeatures = linear;
> +  

[Mesa-dev] [PATCH] r600: RFC: use GET_BUFFER_RESINFO vtx fetch on eg instead of setting up consts

[sroland]

From: Roland Scheidegger 

Contrary to what the comment said, this appears to work just fine on my rv770
(tested with piglit textureSize 140 fs/vs samplerBuffer).
I have no clue though if it's actually preferrable to use it (unfortunately
we cannot get rid of the tex constants completely, as we still require them
for cube map txq).
Albeit filling in the format (1 channels or 4?) and the stuff related to mega-
or mini-fetch (what the hell is this...) is just a guess based on other usage
of vtx fetch instructions...

v2: it really needs to be done through texture cache (I botched the
testing because sb optimizations turned it automatically into tc, but
can't rely on it and isn't happening on tes).

Tested-by: Konstantin Kharlamov 
---
 src/gallium/drivers/r600/evergreen_state.c   |  7 ++--
 src/gallium/drivers/r600/r600_asm.c  |  3 +-
 src/gallium/drivers/r600/r600_shader.c   | 59 ++--
 src/gallium/drivers/r600/r600_state_common.c | 39 +++---
 4 files changed, 50 insertions(+), 58 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index f5b8e7115d..f645791a2c 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -653,11 +653,12 @@ static void evergreen_fill_buffer_resource_words(struct 
r600_context *rctx,
S_030008_ENDIAN_SWAP(endian);
tex_resource_words[3] = swizzle_res | 
S_03000C_UNCACHED(params->uncached);
/*
-* in theory dword 4 is for number of elements, for use with resinfo,
-* but it seems to utterly fail to work, the amd gpu shader analyser
+* dword 4 is for number of elements, for use with resinfo,
+* albeit the amd gpu shader analyser
 * uses a const buffer to store the element sizes for buffer txq
 */
-   tex_resource_words[4] = 0;
+   tex_resource_words[4] = params->size / stride;
+
tex_resource_words[5] = tex_resource_words[6] = 0;
tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
 }
diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c
index d6bd561f01..92c2bdf27c 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -1510,7 +1510,8 @@ int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
 /* common to all 3 families */
 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct 
r600_bytecode_vtx *vtx, unsigned id)
 {
-   bc->bytecode[id] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
+   bc->bytecode[id] = S_SQ_VTX_WORD0_VTX_INST(vtx->op) |
+   S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 8a36bcf1b4..d349c9d7f1 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -6949,31 +6949,48 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx 
*ctx, boolean src_requires_l
 static int r600_do_buffer_txq(struct r600_shader_ctx *ctx, int reg_idx, int 
offset)
 {
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
-   struct r600_bytecode_alu alu;
int r;
int id = tgsi_tex_get_src_gpr(ctx, reg_idx) + offset;
+   int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 
0; // CF_INDEX_1 : CF_INDEX_NONE
 
-   memset(, 0, sizeof(struct r600_bytecode_alu));
-   alu.op = ALU_OP1_MOV;
-   alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
-   if (ctx->bc->chip_class >= EVERGREEN) {
-   /* with eg each dword is either buf size or number of cubes */
-   alu.src[0].sel += id / 4;
-   alu.src[0].chan = id % 4;
-   } else {
+   if (ctx->bc->chip_class < EVERGREEN) {
+   struct r600_bytecode_alu alu;
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP1_MOV;
+   alu.src[0].sel = R600_SHADER_BUFFER_INFO_SEL;
/* r600 we have them at channel 2 of the second dword */
alu.src[0].sel += (id * 2) + 1;
alu.src[0].chan = 1;
+   alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
+   tgsi_dst(ctx, >Dst[0], 0, );
+   alu.last = 1;
+   r = r600_bytecode_add_alu(ctx->bc, );
+   if (r)
+   return r;
+   return 0;
+   } else {
+   struct r600_bytecode_vtx vtx;
+   memset(, 0, sizeof(vtx));
+   vtx.op = FETCH_OP_GDS_MIN_UINT; /* aka GET_BUFFER_RESINFO */
+   vtx.buffer_id = id + 

[Mesa-dev] [PATCH v2] i965: allocate a SGVS element when VertexID or InstanceID are read

[Iago Toral Quiroga]

Although on gen8+ platforms we can in theory use 3DSTATE_VF_SGVS
to put these beyond the last vertex element it seems that we still
need to allocate the SVGS element, otherwise we have observed cases
where we end up reading garbage. Specifically, the CTS test mentioned
below was flaky with a fail rate of ~1% on some gen9+ platforms caused
by reading garbage for the gl_InstanceID value. The flakyness goes
away as soon as we start allocating the SVGS element.

v2:
  - Do this for gen8+, not just gen9+, and pull the boolean
outside the #if block (Jason)

Fixes flaky test:
KHR-GL45.vertex_attrib_64bit.limits_test

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104335
---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 17 ++---
 1 file changed, 2 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 50ac5bc59f..d0a980f973 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -486,26 +486,13 @@ genX(emit_vertices)(struct brw_context *brw)
} else {
   brw_batch_emit(brw, GENX(3DSTATE_VF_SGVS), vfs);
}
+#endif
 
-   /* Normally we don't need an element for the SGVS attribute because the
-* 3DSTATE_VF_SGVS instruction lets you store the generated attribute in an
-* element that is past the list in 3DSTATE_VERTEX_ELEMENTS. However if
-* we're using draw parameters then we need an element for the those
-* values.  Additionally if there is an edge flag element then the SGVS
-* can't be inserted past that so we need a dummy element to ensure that
-* the edge flag is the last one.
-*/
-   const bool needs_sgvs_element = (vs_prog_data->uses_basevertex ||
-vs_prog_data->uses_baseinstance ||
-((vs_prog_data->uses_instanceid ||
-  vs_prog_data->uses_vertexid)
- && uses_edge_flag));
-#else
const bool needs_sgvs_element = (vs_prog_data->uses_basevertex ||
 vs_prog_data->uses_baseinstance ||
 vs_prog_data->uses_instanceid ||
 vs_prog_data->uses_vertexid);
-#endif
+
unsigned nr_elements =
   brw->vb.nr_enabled + needs_sgvs_element + vs_prog_data->uses_drawid;
 
-- 
2.11.0

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[Mesa-dev] [PATCH] radv: reset semaphores & fences on sync_file export.

[Bas Nieuwenhuizen]

Per spec:

"Additionally, exporting a fence payload to a handle with copy transference has 
the same side effects
on the source fence’s payload as executing a fence reset operation. If the 
fence was using a
temporarily imported payload, the fence’s prior permanent payload will be 
restored."

And similar for semaphores:

"Additionally, exporting a semaphore payload to a handle with copy transference 
has the same side
effects on the source semaphore’s payload as executing a semaphore wait 
operation. If the
semaphore was using a temporarily imported payload, the semaphore’s prior 
permanent payload
will be restored."

Fixes: 42bc25a79c "radv: Advertise sync fd import and export."
---
 src/amd/vulkan/radv_device.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index cbf8f5cf49..716a880fa8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3801,6 +3801,14 @@ VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
break;
case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
ret = device->ws->export_syncobj_to_sync_file(device->ws, 
syncobj_handle, pFd);
+   if (!ret) {
+   if (sem->temp_syncobj) {
+   close (sem->temp_syncobj);
+   sem->temp_syncobj = 0;
+   } else {
+   device->ws->reset_syncobj(device->ws, 
syncobj_handle);
+   }
+   }
break;
default:
unreachable("Unhandled semaphore handle type");
@@ -3882,6 +3890,14 @@ VkResult radv_GetFenceFdKHR(VkDevice _device,
break;
case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
ret = device->ws->export_syncobj_to_sync_file(device->ws, 
syncobj_handle, pFd);
+   if (!ret) {
+   if (fence->temp_syncobj) {
+   close (fence->temp_syncobj);
+   fence->temp_syncobj = 0;
+   } else {
+   device->ws->reset_syncobj(device->ws, 
syncobj_handle);
+   }
+   }
break;
default:
unreachable("Unhandled fence handle type");
-- 
2.15.1

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Re: [Mesa-dev] [PATCH] radeonsi: don't expose 8xMSAA on slowest APUs

[Roland Scheidegger]

Deos AMD degrade these chips to d3d10.1 on windows?
Just asking because d3d11 requires 8x msaa ;-).

(But I won't say what I think about this patch...)

Roland

Am 04.01.2018 um 01:54 schrieb Marek Olšák:
> From: Marek Olšák 
> 
> i.e. Kabini, Mullins, Stoney.
> 
> This was requested internally.
> ---
>  src/gallium/drivers/radeonsi/si_state.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/src/gallium/drivers/radeonsi/si_state.c 
> b/src/gallium/drivers/radeonsi/si_state.c
> index f88bf29..d52fccd 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -2136,41 +2136,46 @@ static bool si_is_zs_format_supported(enum 
> pipe_format format)
>  {
>   return si_translate_dbformat(format) != V_028040_Z_INVALID;
>  }
>  
>  static boolean si_is_format_supported(struct pipe_screen *screen,
> enum pipe_format format,
> enum pipe_texture_target target,
> unsigned sample_count,
> unsigned usage)
>  {
> + struct si_screen *sscreen = (struct si_screen*)screen;
>   unsigned retval = 0;
>  
>   if (target >= PIPE_MAX_TEXTURE_TYPES) {
>   R600_ERR("r600: unsupported texture type %d\n", target);
>   return false;
>   }
>  
>   if (!util_format_is_supported(format, usage))
>   return false;
>  
>   if (sample_count > 1) {
>   if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
>   return false;
>  
>   if (usage & PIPE_BIND_SHADER_IMAGE)
>   return false;
>  
>   switch (sample_count) {
>   case 2:
>   case 4:
> + break;
>   case 8:
> + /* Don't expose 8x MSAA on slowest chips. */
> + if (sscreen->info.num_render_backends == 1)
> + return false;
>   break;
>   case 16:
>   if (format == PIPE_FORMAT_NONE)
>   return true;
>   else
>   return false;
>   default:
>   return false;
>   }
>   }
> 

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[Mesa-dev] [PATCH v3 6/6] spirv: Do implicit conversions of uint to bool in OpStore

[Jason Ekstrand]

Technically, the GLSLang bug related to this can also affect SSBO writes
where the bool -> uint conversion is missing.  However, the only known
shipping application with an old enough version of GLSLang to cause
issues with this is the new DOOM game so we keep the workaround as small
as possible.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104424
---
 src/compiler/spirv/vtn_variables.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 41125f6..eb306d0 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -2041,6 +2041,25 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
   vtn_fail_if(dest->type->type == NULL,
   "Invalid destination type for OpStore");
 
+  if (glsl_get_base_type(dest->type->type) == GLSL_TYPE_BOOL &&
+  glsl_get_base_type(src_val->type->type) == GLSL_TYPE_UINT) {
+ /* Early versions of GLSLang would use uint types for UBOs/SSBOs but
+  * would then store them to a local variable as bool.  Work around
+  * the issue by doing an implicit conversion.
+  *
+  * https://github.com/KhronosGroup/glslang/issues/170
+  * https://bugs.freedesktop.org/show_bug.cgi?id=104424
+  */
+ vtn_warn("OpStore of value of type OpTypeInt to a pointer to type "
+  "OpTypeBool.  Doing an implicit conversion to work around "
+  "the problem.");
+ struct vtn_ssa_value *bool_ssa =
+vtn_create_ssa_value(b, dest->type->type);
+ bool_ssa->def = nir_i2b(>nb, vtn_ssa_value(b, w[2])->def);
+ vtn_variable_store(b, bool_ssa, dest);
+ break;
+  }
+
   vtn_assert_types_equal(b, opcode, dest_val->type->deref, src_val->type);
 
   if (glsl_type_is_sampler(dest->type->type)) {
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v3 3/6] spirv: Add a vtn_types_compatible helper

[Jason Ekstrand]

Tested-by: Eero Tamminen 
---
 src/compiler/spirv/spirv_to_nir.c | 52 +++
 src/compiler/spirv/vtn_private.h  |  3 +++
 2 files changed, 55 insertions(+)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 89e9286..08a7205 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -537,6 +537,58 @@ struct member_decoration_ctx {
struct vtn_type *type;
 };
 
+/** Returns true if two types are "compatible", i.e. you can do an OpLoad,
+ * OpStore, or OpCopyMemory between them without breaking anything.
+ * Technically, the SPIR-V rules require the exact same type ID but this lets
+ * us internally be a bit looser.
+ */
+bool
+vtn_types_compatible(struct vtn_builder *b,
+ struct vtn_type *t1, struct vtn_type *t2)
+{
+   if (t1->id == t2->id)
+  return true;
+
+   if (t1->base_type != t2->base_type)
+  return false;
+
+   switch (t1->base_type) {
+   case vtn_base_type_void:
+   case vtn_base_type_scalar:
+   case vtn_base_type_vector:
+   case vtn_base_type_matrix:
+   case vtn_base_type_image:
+   case vtn_base_type_sampler:
+   case vtn_base_type_sampled_image:
+  return t1->type == t2->type;
+
+   case vtn_base_type_array:
+  return t1->length == t2->length &&
+ vtn_types_compatible(b, t1->array_element, t2->array_element);
+
+   case vtn_base_type_pointer:
+  return vtn_types_compatible(b, t1->deref, t2->deref);
+
+   case vtn_base_type_struct:
+  if (t1->length != t2->length)
+ return false;
+
+  for (unsigned i = 0; i < t1->length; i++) {
+ if (!vtn_types_compatible(b, t1->members[i], t2->members[i]))
+return false;
+  }
+  return true;
+
+   case vtn_base_type_function:
+  /* This case shouldn't get hit since you can't copy around function
+   * types.  Just require them to be identical.
+   */
+  return false;
+   }
+
+   vtn_fail("Invalid base type");
+}
+
 /* does a shallow copy of a vtn_type */
 
 static struct vtn_type *
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index f27ef8e..3e49df4 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -365,6 +365,9 @@ struct vtn_type {
};
 };
 
+bool vtn_types_compatible(struct vtn_builder *b,
+  struct vtn_type *t1, struct vtn_type *t2);
+
 struct vtn_variable;
 
 enum vtn_access_mode {
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v3 5/6] spirv: Loosen the validation for load/store type matching

[Jason Ekstrand]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104338
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104424
Tested-by: Eero Tamminen 
---
 src/compiler/spirv/vtn_variables.c | 39 --
 1 file changed, 33 insertions(+), 6 deletions(-)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 399860b..41125f6 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1902,6 +1902,36 @@ vtn_create_variable(struct vtn_builder *b, struct 
vtn_value *val,
}
 }
 
+static void
+vtn_assert_types_equal(struct vtn_builder *b, SpvOp opcode,
+   struct vtn_type *dst_type,
+   struct vtn_type *src_type)
+{
+   if (dst_type->id == src_type->id)
+  return;
+
+   if (vtn_types_compatible(b, dst_type, src_type)) {
+  /* Early versions of GLSLang would re-emit types unnecessarily and you
+   * would end up with OpLoad, OpStore, or OpCopyMemory opcodes which have
+   * mismatched source and destination types.
+   *
+   * https://github.com/KhronosGroup/glslang/issues/304
+   * https://github.com/KhronosGroup/glslang/issues/307
+   * https://bugs.freedesktop.org/show_bug.cgi?id=104338
+   * https://bugs.freedesktop.org/show_bug.cgi?id=104424
+   */
+  vtn_warn("Source and destination types of %s do not have the same "
+   "ID (but are compatible): %u vs %u",
+spirv_op_to_string(opcode), dst_type->id, src_type->id);
+  return;
+   }
+
+   vtn_fail("Source and destination types of %s do not match: %s vs. %s",
+spirv_op_to_string(opcode),
+glsl_get_type_name(dst_type->type),
+glsl_get_type_name(src_type->type));
+}
+
 void
 vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
  const uint32_t *w, unsigned count)
@@ -1978,8 +2008,7 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
   struct vtn_value *dest = vtn_value(b, w[1], vtn_value_type_pointer);
   struct vtn_value *src = vtn_value(b, w[2], vtn_value_type_pointer);
 
-  vtn_fail_if(dest->type->deref != src->type->deref,
-  "Dereferenced pointer types to OpCopyMemory do not match");
+  vtn_assert_types_equal(b, opcode, dest->type->deref, src->type->deref);
 
   vtn_variable_copy(b, dest->pointer, src->pointer);
   break;
@@ -1991,8 +2020,7 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
   struct vtn_value *src_val = vtn_value(b, w[3], vtn_value_type_pointer);
   struct vtn_pointer *src = src_val->pointer;
 
-  vtn_fail_if(res_type != src_val->type->deref,
-  "Result and pointer types of OpLoad do not match");
+  vtn_assert_types_equal(b, opcode, res_type, src_val->type->deref);
 
   if (src->mode == vtn_variable_mode_image ||
   src->mode == vtn_variable_mode_sampler) {
@@ -2013,8 +2041,7 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
   vtn_fail_if(dest->type->type == NULL,
   "Invalid destination type for OpStore");
 
-  vtn_fail_if(dest_val->type->deref != src_val->type,
-  "Value and pointer types of OpStore do not match");
+  vtn_assert_types_equal(b, opcode, dest_val->type->deref, src_val->type);
 
   if (glsl_type_is_sampler(dest->type->type)) {
  vtn_warn("OpStore of a sampler detected.  Doing on-the-fly copy "
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v3 4/6] spirv: Require a storage type for OpStore destinations

[Jason Ekstrand]

This rules out things such as trying to store a pointer to a local
variable.
---
 src/compiler/spirv/vtn_variables.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 2b3b340..399860b 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -2009,6 +2009,10 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
   struct vtn_pointer *dest = dest_val->pointer;
   struct vtn_value *src_val = vtn_untyped_value(b, w[2]);
 
+  /* OpStore requires us to actually have a storage type */
+  vtn_fail_if(dest->type->type == NULL,
+  "Invalid destination type for OpStore");
+
   vtn_fail_if(dest_val->type->deref != src_val->type,
   "Value and pointer types of OpStore do not match");
 
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v3 2/6] spirv: Store the id of the type in vtn_type

[Jason Ekstrand]

Previously, we were storing a pointer to the vtn_value because we use it
to look up decorations when we create input/output variables.  This
works, but it also may be useful to have the id itself so we may as well
store that instead.
---
 src/compiler/spirv/spirv_to_nir.c  | 2 +-
 src/compiler/spirv/vtn_private.h   | 4 ++--
 src/compiler/spirv/vtn_variables.c | 7 +--
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 66ea267..89e9286 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -928,7 +928,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
struct vtn_value *val = vtn_push_value(b, w[1], vtn_value_type_type);
 
val->type = rzalloc(b, struct vtn_type);
-   val->type->val = val;
+   val->type->id = w[1];
 
switch (opcode) {
case SpvOpTypeVoid:
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 374643a..f27ef8e 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -274,8 +274,8 @@ struct vtn_type {
 
const struct glsl_type *type;
 
-   /* The value that declares this type.  Used for finding decorations */
-   struct vtn_value *val;
+   /* The SPIR-V id of the given type. */
+   uint32_t id;
 
/* Specifies the length of complex types.
 *
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index d69b056..2b3b340 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1793,7 +1793,8 @@ vtn_create_variable(struct vtn_builder *b, struct 
vtn_value *val,
   vtn_foreach_decoration(b, val, var_is_patch_cb, >patch);
   if (glsl_type_is_array(var->type->type) &&
   glsl_type_is_struct(without_array->type)) {
- vtn_foreach_decoration(b, without_array->val,
+ vtn_foreach_decoration(b, vtn_value(b, without_array->id,
+ vtn_value_type_type),
 var_is_patch_cb, >patch);
   }
 
@@ -1849,7 +1850,9 @@ vtn_create_variable(struct vtn_builder *b, struct 
vtn_value *val,
   /* For inputs and outputs, we need to grab locations and builtin
* information from the interface type.
*/
-  vtn_foreach_decoration(b, interface_type->val, var_decoration_cb, var);
+  vtn_foreach_decoration(b, vtn_value(b, interface_type->id,
+  vtn_value_type_type),
+ var_decoration_cb, var);
   break;
}
 
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v3 1/6] spirv: Add a mechanism for dumping failing shaders

[Jason Ekstrand]

---
 src/compiler/spirv/spirv_to_nir.c | 28 
 src/compiler/spirv/vtn_private.h  |  1 +
 2 files changed, 29 insertions(+)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index dcff56f..66ea267 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -31,6 +31,8 @@
 #include "nir/nir_constant_expressions.h"
 #include "spirv_info.h"
 
+#include 
+
 void
 vtn_log(struct vtn_builder *b, enum nir_spirv_debug_level level,
 size_t spirv_offset, const char *message)
@@ -94,6 +96,27 @@ vtn_log_err(struct vtn_builder *b,
ralloc_free(msg);
 }
 
+static void
+vtn_dump_shader(struct vtn_builder *b, const char *path, const char *prefix)
+{
+   static int idx = 0;
+
+   char filename[1024];
+   int len = snprintf(filename, sizeof(filename), "%s/%s-%d.spirv",
+  path, prefix, idx++);
+   if (len < 0 || len >= sizeof(filename))
+  return;
+
+   FILE *f = fopen(filename, "w");
+   if (f == NULL)
+  return;
+
+   fwrite(b->spirv, sizeof(*b->spirv), b->spirv_word_count, f);
+   fclose(f);
+
+   vtn_info("SPIR-V shader dumped to %s", filename);
+}
+
 void
 _vtn_warn(struct vtn_builder *b, const char *file, unsigned line,
   const char *fmt, ...)
@@ -117,6 +140,10 @@ _vtn_fail(struct vtn_builder *b, const char *file, 
unsigned line,
file, line, fmt, args);
va_end(args);
 
+   const char *dump_path = getenv("MESA_SPIRV_FAIL_DUMP_PATH");
+   if (dump_path)
+  vtn_dump_shader(b, dump_path, "fail");
+
longjmp(b->fail_jump, 1);
 }
 
@@ -3690,6 +3717,7 @@ spirv_to_nir(const uint32_t *words, size_t word_count,
/* Initialize the stn_builder object */
struct vtn_builder *b = rzalloc(NULL, struct vtn_builder);
b->spirv = words;
+   b->spirv_word_count = word_count;
b->file = NULL;
b->line = -1;
b->col = -1;
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index f7d8f49..374643a 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -531,6 +531,7 @@ struct vtn_builder {
jmp_buf fail_jump;
 
const uint32_t *spirv;
+   size_t spirv_word_count;
 
nir_shader *shader;
const struct spirv_to_nir_options *options;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH] radv: Use correct flush bits for flushing L2 during CB/DB flushes.

[Bas Nieuwenhuizen]

Copied from radeonsi.

Putting in the correct metadata flush commands for eventually not
flushing L2 on CB/DB switch.

Does not remove the need for V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
at the moment.
---
 src/amd/vulkan/si_cmd_buffer.c | 29 -
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 7d75d69a9a..e16765b5ae 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1006,24 +1006,27 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
 #else
cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
 #endif
-   /* TC| TC_WB = invalidate L2 data
-* TC_MD | TC_WB = invalidate L2 metadata
-* TC| TC_WB | TC_MD = invalidate L2 data & metadata
+   /* These are the only allowed combinations. If you need to
+* do multiple operations at once, do them separately.
+* All operations that invalidate L2 also seem to invalidate
+* metadata. Volatile (VOL) and WC flushes are not listed here.
 *
-* The metadata cache must always be invalidated for coherency
-* between CB/DB and shaders. (metadata = HTILE, CMASK, DCC)
-*
-* TC must be invalidated on GFX9 only if the CB/DB surface is
-* not pipe-aligned. If the surface is RB-aligned, it might not
-* strictly be pipe-aligned since RB alignment takes 
precendence.
+* TC| TC_WB = writeback & invalidate L2 & L1
+* TC| TC_WB | TC_NC = writeback & invalidate L2 for MTYPE 
== NC
+* TC_WB | TC_NC = writeback L2 for MTYPE == NC
+* TC| TC_NC = invalidate L2 for MTYPE == NC
+* TC| TC_MD = writeback & invalidate L2 metadata 
(DCC, etc.)
+* TCL1  = invalidate L1
 */
-   tc_flags = EVENT_TC_WB_ACTION_ENA |
-  EVENT_TC_MD_ACTION_ENA;
+   tc_flags = EVENT_TC_ACTION_ENA |
+  EVENT_TC_MD_ACTION_ENA;
 
/* Ideally flush TC together with CB/DB. */
if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
-   tc_flags |= EVENT_TC_ACTION_ENA |
-   EVENT_TCL1_ACTION_ENA;
+   /* Writeback and invalidate everything in L2 & L1. */
+   tc_flags = EVENT_TC_ACTION_ENA |
+  EVENT_TC_WB_ACTION_ENA;
+
 
/* Clear the flags. */
flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
-- 
2.15.1

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Re: [Mesa-dev] [PATCH v3 3/4] meson: build clover

[Francisco Jerez]

Dylan Baker  writes:

> This has only been compile tested.
>
> v2: - Have a single option for opencl (Eric E)
> - fix typo "tgis" -> "tgsi" (Curro)
> - Don't add "lib" to pipe loader libraries, which matches the
>   autotools behavior
> v3: - Remove trailing whitespace
> - Make PIPE_SEARCH_DIR an absolute path
>
> cc: Curro Jerez 
> cc: Jan Vesely 
> cc: Aaron Watry 
> Signed-off-by: Dylan Baker 

Acked-by: Francisco Jerez 

> ---
>  include/meson.build   |  19 
>  meson.build   |  29 +-
>  meson_options.txt |   7 ++
>  src/gallium/auxiliary/pipe-loader/meson.build |   3 +-
>  src/gallium/meson.build   |  12 ++-
>  src/gallium/state_trackers/clover/meson.build | 122 
> ++
>  src/gallium/targets/opencl/meson.build|  73 +++
>  src/gallium/targets/pipe-loader/meson.build   |  77 
>  8 files changed, 336 insertions(+), 6 deletions(-)
>  create mode 100644 src/gallium/state_trackers/clover/meson.build
>  create mode 100644 src/gallium/targets/opencl/meson.build
>  create mode 100644 src/gallium/targets/pipe-loader/meson.build
>
> diff --git a/include/meson.build b/include/meson.build
> index e4dae91cede..a2e7ce6580e 100644
> --- a/include/meson.build
> +++ b/include/meson.build
> @@ -78,3 +78,22 @@ if with_gallium_st_nine
>  subdir : 'd3dadapter',
>)
>  endif
> +
> +# Only install the headers if we are building a stand alone implementation 
> and
> +# not an ICD enabled implementation
> +if with_gallium_opencl and not with_opencl_icd
> +  install_headers(
> +'CL/cl.h',
> +'CL/cl.hpp',
> +'CL/cl_d3d10.h',
> +'CL/cl_d3d11.h',
> +'CL/cl_dx9_media_sharing.h',
> +'CL/cl_egl.h',
> +'CL/cl_ext.h',
> +'CL/cl_gl.h',
> +'CL/cl_gl_ext.h',
> +'CL/cl_platform.h',
> +'CL/opencl.h',
> +subdir: 'CL'
> +  )
> +endif
> diff --git a/meson.build b/meson.build
> index 842d441199e..74b2d5c49dc 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -583,6 +583,22 @@ if with_gallium_st_nine
>endif
>  endif
>  
> +_opencl = get_option('gallium-opencl')
> +if _opencl !=' disabled'
> +  if not with_gallium
> +error('OpenCL Clover implementation requires at least one gallium 
> driver.')
> +  endif
> +
> +  # TODO: alitvec?
> +  dep_clc = dependency('libclc')
> +  with_gallium_opencl = true
> +  with_opencl_icd = _opencl == 'icd'
> +else
> +  dep_clc = []
> +  with_gallium_opencl = false
> +  with_gallium_icd = false
> +endif
> +
>  gl_pkgconfig_c_flags = []
>  if with_platform_x11
>if with_any_vk or (with_glx == 'dri' and with_dri_platform == 'drm')
> @@ -930,7 +946,7 @@ dep_thread = dependency('threads')
>  if dep_thread.found() and host_machine.system() != 'windows'
>pre_args += '-DHAVE_PTHREAD'
>  endif
> -if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 # TODO: clover
> +if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 or 
> with_gallium_opencl
>dep_elf = dependency('libelf', required : false)
>if not dep_elf.found()
>  dep_elf = cc.find_library('elf')
> @@ -972,12 +988,19 @@ if with_amd_vk or with_gallium_radeonsi or 
> with_gallium_r600
>  llvm_modules += 'asmparser'
>endif
>  endif
> +if with_gallium_opencl
> +  llvm_modules += [
> +'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 
> 'irreader',
> +'lto', 'option', 'objcarcopts', 'profiledata',
> +  ]
> +  # TODO: optional modules
> +endif
>  
>  _llvm = get_option('llvm')
>  if _llvm == 'auto'
>dep_llvm = dependency(
>  'llvm', version : '>= 3.9.0', modules : llvm_modules,
> -required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr,
> +required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr or 
> with_gallium_opencl,
>)
>with_llvm = dep_llvm.found()
>  elif _llvm == 'true'
> @@ -1154,8 +1177,6 @@ else
>dep_lmsensors = []
>  endif
>  
> -# TODO: clover
> -
>  # TODO: gallium tests
>  
>  # TODO: various libdirs
> diff --git a/meson_options.txt b/meson_options.txt
> index 4f4db5b7d26..894378985fd 100644
> --- a/meson_options.txt
> +++ b/meson_options.txt
> @@ -120,6 +120,13 @@ option(
>value : false,
>description : 'build gallium "nine" Direct3D 9.x state tracker.',
>  )
> +option(
> +  'gallium-opencl',
> +  type : 'combo',
> +  choices : ['icd', 'standalone', 'disabled'],
> +  value : 'disabled',
> +  description : 'build gallium "clover" OpenCL state tracker.',
> +)
>  option(
>'d3d-drivers-path',
>type : 'string',
> diff --git a/src/gallium/auxiliary/pipe-loader/meson.build 
> b/src/gallium/auxiliary/pipe-loader/meson.build
> index 9b12432aea0..869a2935149 100644
> --- a/src/gallium/auxiliary/pipe-loader/meson.build
> +++ 

Re: [Mesa-dev] [PATCH] radeonsi: fix alpha-to-coverage if color writes are disabled

[Marek Olšák]

Thanks! I slightly modified the patch and pushed it.

Marek

On Sun, Dec 31, 2017 at 10:19 AM, Józef Kucia  wrote:
> If alpha-to-coverage is enabled, we have to compute alpha
> even if color writes are disabled.
>
> Signed-off-by: Józef Kucia 
> ---
>
> Found while running The Witness under Wine.
>
> ---
>  src/gallium/drivers/radeonsi/si_state_shaders.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
> b/src/gallium/drivers/radeonsi/si_state_shaders.c
> index 9143f61fcdf2..eaf72e8ee684 100644
> --- a/src/gallium/drivers/radeonsi/si_state_shaders.c
> +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
> @@ -1173,6 +1173,8 @@ static void si_shader_selector_key_hw_vs(struct 
> si_context *sctx,
>   ps->info.writes_stencil ||
>   ps->info.writes_samplemask ||
>   si_get_alpha_test_func(sctx) != 
> PIPE_FUNC_ALWAYS;
> +   const struct si_state_blend *blend = sctx->queued.named.blend;
> +   bool alpha_to_coverage = blend && blend->alpha_to_coverage;
>
> unsigned ps_colormask = 
> sctx->framebuffer.colorbuf_enabled_4bit &
> 
> sctx->queued.named.blend->cb_target_mask;
> @@ -1182,7 +1184,8 @@ static void si_shader_selector_key_hw_vs(struct 
> si_context *sctx,
> ps_disabled = 
> sctx->queued.named.rasterizer->rasterizer_discard ||
>   (!ps_colormask &&
>!ps_modifies_zs &&
> -  !ps->info.writes_memory);
> +  !ps->info.writes_memory &&
> +  !alpha_to_coverage);
> }
>
> /* Find out which VS outputs aren't used by the PS. */
> --
> 2.15.1
>
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[Mesa-dev] [PATCH 1/2] ac: add ac_build_fmin/fmax helpers

[Marek Olšák]

From: Marek Olšák 

---
 src/amd/common/ac_llvm_build.c | 32 ++--
 src/amd/common/ac_llvm_build.h |  5 -
 2 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 96ad715..7100e52 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1198,44 +1198,48 @@ ac_build_umsb(struct ac_llvm_context *ctx,
msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
   msb, "");
 
/* check for zero */
return LLVMBuildSelect(ctx->builder,
   LLVMBuildICmp(ctx->builder, LLVMIntEQ, arg,
 LLVMConstInt(ctx->i32, 0, 0), ""),
   LLVMConstInt(ctx->i32, -1, true), msb, "");
 }
 
+LLVMValueRef ac_build_fmin(struct ac_llvm_context *ctx, LLVMValueRef a,
+  LLVMValueRef b)
+{
+   LLVMValueRef args[2] = {a, b};
+   return ac_build_intrinsic(ctx, "llvm.minnum.f32", ctx->f32, args, 2,
+ AC_FUNC_ATTR_READNONE);
+}
+
+LLVMValueRef ac_build_fmax(struct ac_llvm_context *ctx, LLVMValueRef a,
+  LLVMValueRef b)
+{
+   LLVMValueRef args[2] = {a, b};
+   return ac_build_intrinsic(ctx, "llvm.maxnum.f32", ctx->f32, args, 2,
+ AC_FUNC_ATTR_READNONE);
+}
+
 LLVMValueRef ac_build_umin(struct ac_llvm_context *ctx, LLVMValueRef a,
   LLVMValueRef b)
 {
LLVMValueRef cmp = LLVMBuildICmp(ctx->builder, LLVMIntULE, a, b, "");
return LLVMBuildSelect(ctx->builder, cmp, a, b, "");
 }
 
 LLVMValueRef ac_build_clamp(struct ac_llvm_context *ctx, LLVMValueRef value)
 {
if (HAVE_LLVM >= 0x0500) {
-   LLVMValueRef max[2] = {
-   value,
-   LLVMConstReal(ctx->f32, 0),
-   };
-   LLVMValueRef min[2] = {
-   LLVMConstReal(ctx->f32, 1),
-   };
-
-   min[1] = ac_build_intrinsic(ctx, "llvm.maxnum.f32",
-   ctx->f32, max, 2,
-   AC_FUNC_ATTR_READNONE);
-   return ac_build_intrinsic(ctx, "llvm.minnum.f32",
- ctx->f32, min, 2,
- AC_FUNC_ATTR_READNONE);
+   return ac_build_fmin(ctx, ac_build_fmax(ctx, value, ctx->f32_0),
+ctx->f32_1);
}
 
LLVMValueRef args[3] = {
value,
LLVMConstReal(ctx->f32, 0),
LLVMConstReal(ctx->f32, 1),
};
 
return ac_build_intrinsic(ctx, "llvm.AMDGPU.clamp.", ctx->f32, args, 3,
  AC_FUNC_ATTR_READNONE |
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 3e0285b..0deb5b5 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -234,21 +234,24 @@ void ac_build_sendmsg(struct ac_llvm_context *ctx,
  uint32_t msg,
  LLVMValueRef wave_id);
 
 LLVMValueRef ac_build_imsb(struct ac_llvm_context *ctx,
   LLVMValueRef arg,
   LLVMTypeRef dst_type);
 
 LLVMValueRef ac_build_umsb(struct ac_llvm_context *ctx,
  LLVMValueRef arg,
  LLVMTypeRef dst_type);
-
+LLVMValueRef ac_build_fmin(struct ac_llvm_context *ctx, LLVMValueRef a,
+  LLVMValueRef b);
+LLVMValueRef ac_build_fmax(struct ac_llvm_context *ctx, LLVMValueRef a,
+  LLVMValueRef b);
 LLVMValueRef ac_build_umin(struct ac_llvm_context *ctx, LLVMValueRef a, 
LLVMValueRef b);
 LLVMValueRef ac_build_clamp(struct ac_llvm_context *ctx, LLVMValueRef value);
 
 struct ac_export_args {
LLVMValueRef out[4];
 unsigned target;
 unsigned enabled_channels;
 bool compr;
 bool done;
 bool valid_mask;
-- 
2.7.4

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[Mesa-dev] [PATCH 2/2] radeonsi: use pknorm_i16/u16 and pk_i16/u16 LLVM intrinsics

[Marek Olšák]

From: Marek Olšák 

---
 src/amd/common/ac_llvm_build.c   | 164 +++
 src/amd/common/ac_llvm_build.h   |  13 +++
 src/gallium/drivers/radeonsi/si_shader.c | 152 
 3 files changed, 216 insertions(+), 113 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 7100e52..c48a186 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -61,20 +61,21 @@ ac_llvm_context_init(struct ac_llvm_context *ctx, 
LLVMContextRef context,
ctx->voidt = LLVMVoidTypeInContext(ctx->context);
ctx->i1 = LLVMInt1TypeInContext(ctx->context);
ctx->i8 = LLVMInt8TypeInContext(ctx->context);
ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
ctx->intptr = HAVE_32BIT_POINTERS ? ctx->i32 : ctx->i64;
ctx->f16 = LLVMHalfTypeInContext(ctx->context);
ctx->f32 = LLVMFloatTypeInContext(ctx->context);
ctx->f64 = LLVMDoubleTypeInContext(ctx->context);
+   ctx->v2i16 = LLVMVectorType(ctx->i16, 2);
ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
 
ctx->i32_0 = LLVMConstInt(ctx->i32, 0, false);
ctx->i32_1 = LLVMConstInt(ctx->i32, 1, false);
ctx->f32_0 = LLVMConstReal(ctx->f32, 0.0);
@@ -1214,20 +1215,34 @@ LLVMValueRef ac_build_fmin(struct ac_llvm_context *ctx, 
LLVMValueRef a,
 }
 
 LLVMValueRef ac_build_fmax(struct ac_llvm_context *ctx, LLVMValueRef a,
   LLVMValueRef b)
 {
LLVMValueRef args[2] = {a, b};
return ac_build_intrinsic(ctx, "llvm.maxnum.f32", ctx->f32, args, 2,
  AC_FUNC_ATTR_READNONE);
 }
 
+LLVMValueRef ac_build_imin(struct ac_llvm_context *ctx, LLVMValueRef a,
+  LLVMValueRef b)
+{
+   LLVMValueRef cmp = LLVMBuildICmp(ctx->builder, LLVMIntSLE, a, b, "");
+   return LLVMBuildSelect(ctx->builder, cmp, a, b, "");
+}
+
+LLVMValueRef ac_build_imax(struct ac_llvm_context *ctx, LLVMValueRef a,
+  LLVMValueRef b)
+{
+   LLVMValueRef cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, a, b, "");
+   return LLVMBuildSelect(ctx->builder, cmp, a, b, "");
+}
+
 LLVMValueRef ac_build_umin(struct ac_llvm_context *ctx, LLVMValueRef a,
   LLVMValueRef b)
 {
LLVMValueRef cmp = LLVMBuildICmp(ctx->builder, LLVMIntULE, a, b, "");
return LLVMBuildSelect(ctx->builder, cmp, a, b, "");
 }
 
 LLVMValueRef ac_build_clamp(struct ac_llvm_context *ctx, LLVMValueRef value)
 {
if (HAVE_LLVM >= 0x0500) {
@@ -1439,20 +1454,169 @@ LLVMValueRef ac_build_cvt_pkrtz_f16(struct 
ac_llvm_context *ctx,
   v2f16, args, 2,
   AC_FUNC_ATTR_READNONE);
return LLVMBuildBitCast(ctx->builder, res, ctx->i32, "");
}
 
return ac_build_intrinsic(ctx, "llvm.SI.packf16", ctx->i32, args, 2,
  AC_FUNC_ATTR_READNONE |
  AC_FUNC_ATTR_LEGACY);
 }
 
+/* Upper 16 bits must be zero. */
+static LLVMValueRef ac_llvm_pack_two_int16(struct ac_llvm_context *ctx,
+  LLVMValueRef val[2])
+{
+   return LLVMBuildOr(ctx->builder, val[0],
+  LLVMBuildShl(ctx->builder, val[1],
+   LLVMConstInt(ctx->i32, 16, 0),
+   ""), "");
+}
+
+/* Upper 16 bits are ignored and will be dropped. */
+static LLVMValueRef ac_llvm_pack_two_int32_as_int16(struct ac_llvm_context 
*ctx,
+   LLVMValueRef val[2])
+{
+   LLVMValueRef v[2] = {
+   LLVMBuildAnd(ctx->builder, val[0],
+LLVMConstInt(ctx->i32, 0x, 0), ""),
+   val[1],
+   };
+   return ac_llvm_pack_two_int16(ctx, v);
+}
+
+LLVMValueRef ac_build_cvt_pknorm_i16(struct ac_llvm_context *ctx,
+LLVMValueRef args[2])
+{
+   if (HAVE_LLVM >= 0x0600) {
+   LLVMValueRef res =
+   ac_build_intrinsic(ctx, "llvm.amdgcn.cvt.pknorm.i16",
+  ctx->v2i16, args, 2,
+  AC_FUNC_ATTR_READNONE);
+   return LLVMBuildBitCast(ctx->builder, res, ctx->i32, "");
+   }
+
+   LLVMValueRef val[2];
+
+   for (int chan = 0; chan < 2; chan++) {
+   /* Clamp between [-1, 1]. */
+   val[chan] = 

[Mesa-dev] [PATCH] radeonsi: don't expose 8xMSAA on slowest APUs

[Marek Olšák]

From: Marek Olšák 

i.e. Kabini, Mullins, Stoney.

This was requested internally.
---
 src/gallium/drivers/radeonsi/si_state.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index f88bf29..d52fccd 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2136,41 +2136,46 @@ static bool si_is_zs_format_supported(enum pipe_format 
format)
 {
return si_translate_dbformat(format) != V_028040_Z_INVALID;
 }
 
 static boolean si_is_format_supported(struct pipe_screen *screen,
  enum pipe_format format,
  enum pipe_texture_target target,
  unsigned sample_count,
  unsigned usage)
 {
+   struct si_screen *sscreen = (struct si_screen*)screen;
unsigned retval = 0;
 
if (target >= PIPE_MAX_TEXTURE_TYPES) {
R600_ERR("r600: unsupported texture type %d\n", target);
return false;
}
 
if (!util_format_is_supported(format, usage))
return false;
 
if (sample_count > 1) {
if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
return false;
 
if (usage & PIPE_BIND_SHADER_IMAGE)
return false;
 
switch (sample_count) {
case 2:
case 4:
+   break;
case 8:
+   /* Don't expose 8x MSAA on slowest chips. */
+   if (sscreen->info.num_render_backends == 1)
+   return false;
break;
case 16:
if (format == PIPE_FORMAT_NONE)
return true;
else
return false;
default:
return false;
}
}
-- 
2.7.4

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[Mesa-dev] [PATCH] radv: Invildate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.

[Bas Nieuwenhuizen]

These are just shaders reads, so we need to invalidate L1.

Fixes: 6dbb0eaccc "radv: handle subpass cache flushes"
---
 src/amd/vulkan/radv_cmd_buffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 6dc80acef0..0faf8030b4 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2014,11 +2014,11 @@ radv_dst_access_flush(struct radv_cmd_buffer 
*cmd_buffer,
switch ((VkAccessFlagBits)(1 << b)) {
case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
case VK_ACCESS_INDEX_READ_BIT:
-   case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
break;
case VK_ACCESS_UNIFORM_READ_BIT:
flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | 
RADV_CMD_FLAG_INV_SMEM_L1;
break;
+   case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
case VK_ACCESS_SHADER_READ_BIT:
case VK_ACCESS_TRANSFER_READ_BIT:
case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
-- 
2.15.1

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[Mesa-dev] [PATCH] radv: Add support for ETC2 textures.

[Bas Nieuwenhuizen]

Was surprised that is even supported by Vega.
---
 src/amd/vulkan/radv_device.c|  4 +++-
 src/amd/vulkan/radv_formats.c   | 36 
 src/amd/vulkan/vk_format_layout.csv | 20 ++--
 3 files changed, 49 insertions(+), 11 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index cbf8f5cf49..bbed9f0ec2 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -530,6 +530,7 @@ void radv_GetPhysicalDeviceFeatures(
VkPhysicalDevicephysicalDevice,
VkPhysicalDeviceFeatures*   pFeatures)
 {
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
memset(pFeatures, 0, sizeof(*pFeatures));
 
*pFeatures = (VkPhysicalDeviceFeatures) {
@@ -553,7 +554,8 @@ void radv_GetPhysicalDeviceFeatures(
.alphaToOne   = true,
.multiViewport= true,
.samplerAnisotropy= true,
-   .textureCompressionETC2   = false,
+   .textureCompressionETC2   = 
pdevice->rad_info.chip_class >= GFX9 ||
+   
pdevice->rad_info.family == CHIP_STONEY,
.textureCompressionASTC_LDR   = false,
.textureCompressionBC = true,
.occlusionQueryPrecise= true,
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index c008c1bae6..4b0b4c8320 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -224,6 +224,28 @@ uint32_t radv_translate_tex_dataformat(VkFormat format,
}
}
 
+   if (desc->layout == VK_FORMAT_LAYOUT_ETC) {
+   switch (format) {
+   case VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK:
+   case VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK:
+   return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
+   case VK_FORMAT_ETC2_R8G8B8A1_UNORM_BLOCK:
+   case VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK:
+   return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
+   case VK_FORMAT_ETC2_R8G8B8A8_UNORM_BLOCK:
+   case VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK:
+   return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
+   case VK_FORMAT_EAC_R11_UNORM_BLOCK:
+   case VK_FORMAT_EAC_R11_SNORM_BLOCK:
+   return V_008F14_IMG_DATA_FORMAT_ETC2_R;
+   case VK_FORMAT_EAC_R11G11_UNORM_BLOCK:
+   case VK_FORMAT_EAC_R11G11_SNORM_BLOCK:
+   return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
+   default:
+   break;
+   }
+   }
+
if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32) {
return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
} else if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32) {
@@ -351,10 +373,15 @@ uint32_t radv_translate_tex_numformat(VkFormat format,
case VK_FORMAT_BC2_SRGB_BLOCK:
case VK_FORMAT_BC3_SRGB_BLOCK:
case VK_FORMAT_BC7_SRGB_BLOCK:
+   case VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK:
+   case VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK:
+   case VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK:
return V_008F14_IMG_NUM_FORMAT_SRGB;
case VK_FORMAT_BC4_SNORM_BLOCK:
case VK_FORMAT_BC5_SNORM_BLOCK:
case VK_FORMAT_BC6H_SFLOAT_BLOCK:
+   case VK_FORMAT_EAC_R11_SNORM_BLOCK:
+   case VK_FORMAT_EAC_R11G11_SNORM_BLOCK:
return V_008F14_IMG_NUM_FORMAT_SNORM;
default:
return V_008F14_IMG_NUM_FORMAT_UNORM;
@@ -557,6 +584,15 @@ radv_physical_device_get_format_properties(struct 
radv_physical_device *physical
return;
}
 
+   if (desc->layout == VK_FORMAT_LAYOUT_ETC &&
+   physical_device->rad_info.chip_class < GFX9 &&
+   physical_device->rad_info.family != CHIP_STONEY) {
+   out_properties->linearTilingFeatures = linear;
+   out_properties->optimalTilingFeatures = tiled;
+   out_properties->bufferFeatures = buffer;
+   return;
+   }
+
if (radv_is_storage_image_format_supported(physical_device, format)) {
tiled |= VK_FORMAT_FEATURE_STORAGE_IMAGE_BIT;
linear |= VK_FORMAT_FEATURE_STORAGE_IMAGE_BIT;
diff --git a/src/amd/vulkan/vk_format_layout.csv 

Re: [Mesa-dev] [PATCH 1/3] Add meson build system

[Dylan Baker]

Quoting Igor Gnatenko (2018-01-03 15:22:36)
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA256
> 
> On Wed, 2018-01-03 at 13:31 -0800, Dylan Baker wrote:
> > This patch adds a complete meson build system, including tests and
> > install. It has the necessary hooks to allow it be used as a subproject
> > for other meson based builds such as mesa.
> 
> It is failing to build with (autofoo-based builds fine):
> 
> [25/109] cc  -Iamdgpu/drm_amdgpu@sha -Iamdgpu -I../amdgpu -I. -I../
> - -I../include/drm -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64
> - -std=gnu99 -DHAVE_CONFIG_H -O2 -g -Wall -Werror=format-security -Wp,-
> D_FORTIFY_SOURCE=2 -fexceptions -fstack-protector-strong --param=ssp-buffer-
> size=4 -grecord-gcc-switches -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1
> - -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fPIC 
> -Wall
> - -Wextra -Wsign-compare -Werror-implicit-function-declaration -Wpointer-arith
> - -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes 
> -Wmissing-declarations 
> - -Wnested-externs -Wpacked -Wswitch-enum -Wmissing-format-attribute -Wstrict-
> aliasing=2 -Winit-self -Winline -Wshadow -Wdeclaration-after-statement -Wold-
> style-definition -Wno-unused-parameter -Wno-attributes -Wno-long-long -Wno-
> missing-field-initializers '-DAMDGPU_ASIC_ID_TABLE="share/amdgpu.ids"' -MMD 
> -MQ
> 'amdgpu/drm_amdgpu@sha/amdgpu_asic_id.c.o' -MF 
> 'amdgpu/drm_amdgpu@sha/amdgpu_as
> ic_id.c.o.d' -o 'amdgpu/drm_amdgpu@sha/amdgpu_asic_id.c.o' -c
> ../amdgpu/amdgpu_asic_id.c
> FAILED: amdgpu/drm_amdgpu@sha/amdgpu_asic_id.c.o 
> cc  -Iamdgpu/drm_amdgpu@sha -Iamdgpu -I../amdgpu -I. -I../ -I../include/drm
> - -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -std=gnu99
> - -DHAVE_CONFIG_H -O2 -g -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2
> - -fexceptions -fstack-protector-strong --param=ssp-buffer-size=4 
> -grecord-gcc-
> switches -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1
> - -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fPIC 
> -Wall
> - -Wextra -Wsign-compare -Werror-implicit-function-declaration -Wpointer-arith
> - -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes 
> -Wmissing-declarations 
> - -Wnested-externs -Wpacked -Wswitch-enum -Wmissing-format-attribute -Wstrict-
> aliasing=2 -Winit-self -Winline -Wshadow -Wdeclaration-after-statement -Wold-
> style-definition -Wno-unused-parameter -Wno-attributes -Wno-long-long -Wno-
> missing-field-initializers '-DAMDGPU_ASIC_ID_TABLE="share/amdgpu.ids"' -MMD 
> -MQ
> 'amdgpu/drm_amdgpu@sha/amdgpu_asic_id.c.o' -MF 
> 'amdgpu/drm_amdgpu@sha/amdgpu_as
> ic_id.c.o.d' -o 'amdgpu/drm_amdgpu@sha/amdgpu_asic_id.c.o' -c
> ../amdgpu/amdgpu_asic_id.c
> ../amdgpu/amdgpu_asic_id.c: In function ‘amdgpu_parse_asic_ids’:
> ../amdgpu/amdgpu_asic_id.c:122:26: error: ‘AMDGPU_ASIC_ID_TABLE_NUM_ENTRIES’
> undeclared (first use in this function); did you mean
> ‘AMDGPU_VCE_CLOCK_TABLE_ENTRIES’?
>   size_t table_max_size = AMDGPU_ASIC_ID_TABLE_NUM_ENTRIES;
>   ^~~~
>   AMDGPU_VCE_CLOCK_TABLE_ENTRIES
> ../amdgpu/amdgpu_asic_id.c:122:26: note: each undeclared identifier is 
> reported
> only once for each function it appears in

You need to rebase on master, that was removed in 
f05a2b4cb1aedb906524718db8ba2e62383f3064.

> 
> [...]
> 
> > diff --git a/freedreno/meson.build b/freedreno/meson.build
> > new file mode 100644
> > index 000..47d6e44
> > --- /dev/null
> > +++ b/freedreno/meson.build
> > @@ -0,0 +1,82 @@
> > [...]
> > +if with_freedreno_kgsl != 'false'
> 
> Booleans should not compare with strings, so do just `if with_freedreno_kgsl`.
> 
> Submitted meson RFE to warn: https://github.com/mesonbuild/meson/issues/2870.
> 
> > +  files_freedreno += files(
> > +'kgsl/kgsl_bo.c',
> > +'kgsl/kgsl_device.c',
> > +'kgsl/kgsl_drm.h',
> > +'kgsl/kgsl_pipe.c',
> > +'kgsl/kgsl_priv.h',
> > +'kgsl/kgsl_ringbuffer.c',
> > +'kgsl/msm_kgsl.h',
> > +  )
> > +endif
> 
> [...]
> 
> > diff --git a/meson_options.txt b/meson_options.txt
> > new file mode 100644
> > index 000..7c2fa4f
> > --- /dev/null
> > +++ b/meson_options.txt
> > @@ -0,0 +1,38 @@
> > [...]
> > +option('libkms',  type : 'combo', value : 'auto',  choices : ['true',
> > 'false', 'auto'])
> > +option('intel',   type : 'combo', value : 'auto',  choices : ['true',
> > 'false', 'auto'])
> > +option('radeon',  type : 'combo', value : 'auto',  choices : ['true',
> > 'false', 'auto'])
> > +option('amdgpu',  type : 'combo', value : 'auto',  choices : ['true',
> > 'false', 'auto'])
> > +option('nouveau', type : 'combo', value : 'auto',  choices : ['true',
> > 'false', 'auto'])
> > +option('vmwgfx',  type : 'combo', value : 'true',  choices : ['true',
> > 'false', 'auto'])
> > +option('omap',type : 'combo', value : 'false', choices : ['true',
> > 'false', 'auto'])
> > +option('exynos',  type : 

Re: [Mesa-dev] [PATCH] ac: rename has_sync_file to has_fence_to_handle.

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Thu, Jan 4, 2018 at 12:24 AM, Bas Nieuwenhuizen
 wrote:
> sync_files are in linux since 4.7, while the amdgpu fence_to_handle
> ioctl is only in 4.15.
>
> In particular we don't need it for sync_file in radv, because
> everything happens via syncobjs, which got support earlier than
> fence_to_handle.
> ---
>  src/amd/common/ac_gpu_info.c| 4 ++--
>  src/amd/common/ac_gpu_info.h| 2 +-
>  src/gallium/drivers/radeonsi/si_fence.c | 4 ++--
>  src/gallium/drivers/radeonsi/si_get.c   | 2 +-
>  4 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index 2599fb6164..6d9dcb5c56 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -278,7 +278,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
> info->has_userptr = true;
> info->has_syncobj = has_syncobj(fd);
> info->has_syncobj_wait_for_submit = info->has_syncobj && 
> info->drm_minor >= 20;
> -   info->has_sync_file = info->has_syncobj && info->drm_minor >= 21;
> +   info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 
> 21;
> info->has_ctx_priority = info->drm_minor >= 22;
> info->num_render_backends = amdinfo->rb_pipes;
> info->clock_crystal_freq = amdinfo->gpu_counter_freq;
> @@ -392,7 +392,7 @@ void ac_print_gpu_info(struct radeon_info *info)
>info->drm_minor, info->drm_patchlevel);
> printf("has_userptr = %i\n", info->has_userptr);
> printf("has_syncobj = %u\n", info->has_syncobj);
> -   printf("has_sync_file = %u\n", info->has_sync_file);
> +   printf("has_fence_to_handle = %u\n", info->has_fence_to_handle);
>
> printf("r600_max_quad_pipes = %i\n", info->r600_max_quad_pipes);
> printf("max_shader_clock = %i\n", info->max_shader_clock);
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index 235cc245bd..cca3e98d36 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -82,7 +82,7 @@ struct radeon_info {
> boolhas_userptr;
> boolhas_syncobj;
> boolhas_syncobj_wait_for_submit;
> -   boolhas_sync_file;
> +   boolhas_fence_to_handle;
> boolhas_ctx_priority;
>
> /* Shader cores. */
> diff --git a/src/gallium/drivers/radeonsi/si_fence.c 
> b/src/gallium/drivers/radeonsi/si_fence.c
> index 3c4d75462a..5f320803aa 100644
> --- a/src/gallium/drivers/radeonsi/si_fence.c
> +++ b/src/gallium/drivers/radeonsi/si_fence.c
> @@ -306,7 +306,7 @@ static void si_create_fence_fd(struct pipe_context *ctx,
>
> *pfence = NULL;
>
> -   if (!sscreen->info.has_sync_file)
> +   if (!sscreen->info.has_fence_to_handle)
> return;
>
> rfence = si_create_multi_fence();
> @@ -330,7 +330,7 @@ static int si_fence_get_fd(struct pipe_screen *screen,
> struct si_multi_fence *rfence = (struct si_multi_fence *)fence;
> int gfx_fd = -1, sdma_fd = -1;
>
> -   if (!sscreen->info.has_sync_file)
> +   if (!sscreen->info.has_fence_to_handle)
> return -1;
>
> util_queue_fence_wait(>ready);
> diff --git a/src/gallium/drivers/radeonsi/si_get.c 
> b/src/gallium/drivers/radeonsi/si_get.c
> index fd42adbcae..9b5a03edaf 100644
> --- a/src/gallium/drivers/radeonsi/si_get.c
> +++ b/src/gallium/drivers/radeonsi/si_get.c
> @@ -278,7 +278,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum 
> pipe_cap param)
> return 0;
>
> case PIPE_CAP_NATIVE_FENCE_FD:
> -   return sscreen->info.has_sync_file;
> +   return sscreen->info.has_fence_to_handle;
>
> case PIPE_CAP_QUERY_BUFFER_OBJECT:
> return si_have_tgsi_compute(sscreen);
> --
> 2.15.1
>
> ___
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[Mesa-dev] [PATCH] ac: rename has_sync_file to has_fence_to_handle.

[Bas Nieuwenhuizen]

sync_files are in linux since 4.7, while the amdgpu fence_to_handle
ioctl is only in 4.15.

In particular we don't need it for sync_file in radv, because
everything happens via syncobjs, which got support earlier than
fence_to_handle.
---
 src/amd/common/ac_gpu_info.c| 4 ++--
 src/amd/common/ac_gpu_info.h| 2 +-
 src/gallium/drivers/radeonsi/si_fence.c | 4 ++--
 src/gallium/drivers/radeonsi/si_get.c   | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 2599fb6164..6d9dcb5c56 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -278,7 +278,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
info->has_syncobj_wait_for_submit = info->has_syncobj && 
info->drm_minor >= 20;
-   info->has_sync_file = info->has_syncobj && info->drm_minor >= 21;
+   info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
info->has_ctx_priority = info->drm_minor >= 22;
info->num_render_backends = amdinfo->rb_pipes;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
@@ -392,7 +392,7 @@ void ac_print_gpu_info(struct radeon_info *info)
   info->drm_minor, info->drm_patchlevel);
printf("has_userptr = %i\n", info->has_userptr);
printf("has_syncobj = %u\n", info->has_syncobj);
-   printf("has_sync_file = %u\n", info->has_sync_file);
+   printf("has_fence_to_handle = %u\n", info->has_fence_to_handle);
 
printf("r600_max_quad_pipes = %i\n", info->r600_max_quad_pipes);
printf("max_shader_clock = %i\n", info->max_shader_clock);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 235cc245bd..cca3e98d36 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -82,7 +82,7 @@ struct radeon_info {
boolhas_userptr;
boolhas_syncobj;
boolhas_syncobj_wait_for_submit;
-   boolhas_sync_file;
+   boolhas_fence_to_handle;
boolhas_ctx_priority;
 
/* Shader cores. */
diff --git a/src/gallium/drivers/radeonsi/si_fence.c 
b/src/gallium/drivers/radeonsi/si_fence.c
index 3c4d75462a..5f320803aa 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -306,7 +306,7 @@ static void si_create_fence_fd(struct pipe_context *ctx,
 
*pfence = NULL;
 
-   if (!sscreen->info.has_sync_file)
+   if (!sscreen->info.has_fence_to_handle)
return;
 
rfence = si_create_multi_fence();
@@ -330,7 +330,7 @@ static int si_fence_get_fd(struct pipe_screen *screen,
struct si_multi_fence *rfence = (struct si_multi_fence *)fence;
int gfx_fd = -1, sdma_fd = -1;
 
-   if (!sscreen->info.has_sync_file)
+   if (!sscreen->info.has_fence_to_handle)
return -1;
 
util_queue_fence_wait(>ready);
diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index fd42adbcae..9b5a03edaf 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -278,7 +278,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
return 0;
 
case PIPE_CAP_NATIVE_FENCE_FD:
-   return sscreen->info.has_sync_file;
+   return sscreen->info.has_fence_to_handle;
 
case PIPE_CAP_QUERY_BUFFER_OBJECT:
return si_have_tgsi_compute(sscreen);
-- 
2.15.1

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Re: [Mesa-dev] [PATCH 1/3] Add meson build system

[Igor Gnatenko]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256

On Wed, 2018-01-03 at 13:31 -0800, Dylan Baker wrote:
> This patch adds a complete meson build system, including tests and
> install. It has the necessary hooks to allow it be used as a subproject
> for other meson based builds such as mesa.

It is failing to build with (autofoo-based builds fine):

[25/109] cc  -Iamdgpu/drm_amdgpu@sha -Iamdgpu -I../amdgpu -I. -I../
- -I../include/drm -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64
- -std=gnu99 -DHAVE_CONFIG_H -O2 -g -Wall -Werror=format-security -Wp,-
D_FORTIFY_SOURCE=2 -fexceptions -fstack-protector-strong --param=ssp-buffer-
size=4 -grecord-gcc-switches -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1
- -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fPIC -Wall
- -Wextra -Wsign-compare -Werror-implicit-function-declaration -Wpointer-arith
- -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes 
-Wmissing-declarations 
- -Wnested-externs -Wpacked -Wswitch-enum -Wmissing-format-attribute -Wstrict-
aliasing=2 -Winit-self -Winline -Wshadow -Wdeclaration-after-statement -Wold-
style-definition -Wno-unused-parameter -Wno-attributes -Wno-long-long -Wno-
missing-field-initializers '-DAMDGPU_ASIC_ID_TABLE="share/amdgpu.ids"' -MMD -MQ
'amdgpu/drm_amdgpu@sha/amdgpu_asic_id.c.o' -MF 'amdgpu/drm_amdgpu@sha/amdgpu_as
ic_id.c.o.d' -o 'amdgpu/drm_amdgpu@sha/amdgpu_asic_id.c.o' -c
../amdgpu/amdgpu_asic_id.c
FAILED: amdgpu/drm_amdgpu@sha/amdgpu_asic_id.c.o 
cc  -Iamdgpu/drm_amdgpu@sha -Iamdgpu -I../amdgpu -I. -I../ -I../include/drm
- -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -std=gnu99
- -DHAVE_CONFIG_H -O2 -g -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2
- -fexceptions -fstack-protector-strong --param=ssp-buffer-size=4 -grecord-gcc-
switches -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1
- -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fPIC -Wall
- -Wextra -Wsign-compare -Werror-implicit-function-declaration -Wpointer-arith
- -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes 
-Wmissing-declarations 
- -Wnested-externs -Wpacked -Wswitch-enum -Wmissing-format-attribute -Wstrict-
aliasing=2 -Winit-self -Winline -Wshadow -Wdeclaration-after-statement -Wold-
style-definition -Wno-unused-parameter -Wno-attributes -Wno-long-long -Wno-
missing-field-initializers '-DAMDGPU_ASIC_ID_TABLE="share/amdgpu.ids"' -MMD -MQ
'amdgpu/drm_amdgpu@sha/amdgpu_asic_id.c.o' -MF 'amdgpu/drm_amdgpu@sha/amdgpu_as
ic_id.c.o.d' -o 'amdgpu/drm_amdgpu@sha/amdgpu_asic_id.c.o' -c
../amdgpu/amdgpu_asic_id.c
../amdgpu/amdgpu_asic_id.c: In function ‘amdgpu_parse_asic_ids’:
../amdgpu/amdgpu_asic_id.c:122:26: error: ‘AMDGPU_ASIC_ID_TABLE_NUM_ENTRIES’
undeclared (first use in this function); did you mean
‘AMDGPU_VCE_CLOCK_TABLE_ENTRIES’?
  size_t table_max_size = AMDGPU_ASIC_ID_TABLE_NUM_ENTRIES;
  ^~~~
  AMDGPU_VCE_CLOCK_TABLE_ENTRIES
../amdgpu/amdgpu_asic_id.c:122:26: note: each undeclared identifier is reported
only once for each function it appears in

[...]

> diff --git a/freedreno/meson.build b/freedreno/meson.build
> new file mode 100644
> index 000..47d6e44
> --- /dev/null
> +++ b/freedreno/meson.build
> @@ -0,0 +1,82 @@
> [...]
> +if with_freedreno_kgsl != 'false'

Booleans should not compare with strings, so do just `if with_freedreno_kgsl`.

Submitted meson RFE to warn: https://github.com/mesonbuild/meson/issues/2870.

> +  files_freedreno += files(
> +'kgsl/kgsl_bo.c',
> +'kgsl/kgsl_device.c',
> +'kgsl/kgsl_drm.h',
> +'kgsl/kgsl_pipe.c',
> +'kgsl/kgsl_priv.h',
> +'kgsl/kgsl_ringbuffer.c',
> +'kgsl/msm_kgsl.h',
> +  )
> +endif

[...]

> diff --git a/meson_options.txt b/meson_options.txt
> new file mode 100644
> index 000..7c2fa4f
> --- /dev/null
> +++ b/meson_options.txt
> @@ -0,0 +1,38 @@
> [...]
> +option('libkms',  type : 'combo', value : 'auto',  choices : ['true',
> 'false', 'auto'])
> +option('intel',   type : 'combo', value : 'auto',  choices : ['true',
> 'false', 'auto'])
> +option('radeon',  type : 'combo', value : 'auto',  choices : ['true',
> 'false', 'auto'])
> +option('amdgpu',  type : 'combo', value : 'auto',  choices : ['true',
> 'false', 'auto'])
> +option('nouveau', type : 'combo', value : 'auto',  choices : ['true',
> 'false', 'auto'])
> +option('vmwgfx',  type : 'combo', value : 'true',  choices : ['true',
> 'false', 'auto'])
> +option('omap',type : 'combo', value : 'false', choices : ['true',
> 'false', 'auto'])
> +option('exynos',  type : 'combo', value : 'false', choices : ['true',
> 'false', 'auto'])
> +option('freedreno',   type : 'combo', value : 'auto',  choices : ['true',
> 'false', 'auto'])
> +option('tegra',   type : 'combo', value : 'false', choices : ['true',
> 'false', 'auto'])
> +option('vc4', type : 'combo', value : 'auto',  choices : ['true',
> 'false', 'auto'])
> +option('etnaviv', 

[Mesa-dev] [Bug 104214] Dota crashes when switching from game to desktop

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104214

--- Comment #19 from Sven  ---
It sound like bug 104392 .

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[Mesa-dev] [Bug 104214] Dota crashes when switching from game to desktop

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104214

--- Comment #18 from Evangelos Foutras  ---
Could this be related to bug 104342 (and the most likely duplicate bugs I've
added to its "See Also" bugs)? The backtrace here looks a bit different but the
brw_clear() call is common (and a few other calls further up).

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[Mesa-dev] [Bug 104214] Dota crashes when switching from game to desktop

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104214

--- Comment #17 from Sven  ---
The bug I originally reported (dota crashed when switching between game and
desktop) is not yet fixed. I managed to rebuild mesa with the patch applied. I
will try to enable debug symbols next and then I'll try to provide the gdb
trace like Cyril did.

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Re: [Mesa-dev] [PATCH 1/3] Add meson build system

[Dylan Baker]

Quoting Dylan Baker (2018-01-03 13:31:28)

> diff --git a/freedreno/meson.build b/freedreno/meson.build
> new file mode 100644
> index 000..47d6e44
> --- /dev/null
> +++ b/freedreno/meson.build
> @@ -0,0 +1,82 @@
> +# Copyright © 2017 Intel Corporation
> +
> +# Permission is hereby granted, free of charge, to any person obtaining a 
> copy
> +# of this software and associated documentation files (the "Software"), to 
> deal
> +# in the Software without restriction, including without limitation the 
> rights
> +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> +# copies of the Software, and to permit persons to whom the Software is
> +# furnished to do so, subject to the following conditions:
> +
> +# The above copyright notice and this permission notice shall be included in
> +# all copies or substantial portions of the Software.
> +
> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
> +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> FROM,
> +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
> THE
> +# SOFTWARE.
> +
> +files_freedreno = files(
> +  'freedreno_device.c',
> +  'freedreno_pipe.c',
> +  'freedreno_priv.h',
> +  'freedreno_ringbuffer.c',
> +  'freedreno_bo.c',
> +  'freedreno_bo_cache.c',
> +  'msm/msm_bo.c',
> +  'msm/msm_device.c',
> +  'msm/msm_drm.h',
> +  'msm/msm_pipe.c',
> +  'msm/msm_priv.h',
> +  'msm/msm_ringbuffer.c',
> +)
> +
> +if with_freedreno_kgsl != 'false'

This should be "if with_freedreno_kgsl" I've fixed that locally.

> +  files_freedreno += files(
> +'kgsl/kgsl_bo.c',
> +'kgsl/kgsl_device.c',
> +'kgsl/kgsl_drm.h',
> +'kgsl/kgsl_pipe.c',
> +'kgsl/kgsl_priv.h',
> +'kgsl/kgsl_ringbuffer.c',
> +'kgsl/msm_kgsl.h',
> +  )
> +endif




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Re: [Mesa-dev] [PATCH] ac: rename has_syncobj_wait -> has_syncobj_wait_for_submit

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

We should probably do something similar for has_sync_file since
sync_files are significantly older.

On Wed, Jan 3, 2018 at 10:51 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> ---
>  src/amd/common/ac_gpu_info.c  | 2 +-
>  src/amd/common/ac_gpu_info.h  | 2 +-
>  src/amd/vulkan/radv_device.c  | 6 +++---
>  src/amd/vulkan/radv_extensions.py | 4 ++--
>  4 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index c042bb2..2599fb6 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -270,21 +270,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
> info->max_se = amdinfo->num_shader_engines;
> info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
> info->has_hw_decode =
> (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
> info->uvd_fw_version =
> uvd.available_rings ? uvd_version : 0;
> info->vce_fw_version =
> vce.available_rings ? vce_version : 0;
> info->has_userptr = true;
> info->has_syncobj = has_syncobj(fd);
> -   info->has_syncobj_wait = info->has_syncobj && info->drm_minor >= 20;
> +   info->has_syncobj_wait_for_submit = info->has_syncobj && 
> info->drm_minor >= 20;
> info->has_sync_file = info->has_syncobj && info->drm_minor >= 21;
> info->has_ctx_priority = info->drm_minor >= 22;
> info->num_render_backends = amdinfo->rb_pipes;
> info->clock_crystal_freq = amdinfo->gpu_counter_freq;
> if (!info->clock_crystal_freq) {
> fprintf(stderr, "amdgpu: clock crystal frequency is 0, 
> timestamps will be wrong\n");
> info->clock_crystal_freq = 1;
> }
> info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
> if (info->chip_class == GFX9) {
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index 04e17f9..235cc24 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -74,21 +74,21 @@ struct radeon_info {
> uint32_tvce_harvest_config;
> uint32_tclock_crystal_freq;
> uint32_ttcc_cache_line_size;
>
> /* Kernel info. */
> uint32_tdrm_major; /* version */
> uint32_tdrm_minor;
> uint32_tdrm_patchlevel;
> boolhas_userptr;
> boolhas_syncobj;
> -   boolhas_syncobj_wait;
> +   boolhas_syncobj_wait_for_submit;
> boolhas_sync_file;
> boolhas_ctx_priority;
>
> /* Shader cores. */
> uint32_tr600_max_quad_pipes; /* wave size / 16 */
> uint32_tmax_shader_clock;
> uint32_tnum_good_compute_units;
> uint32_tmax_se; /* shader engines */
> uint32_tmax_sh_per_se; /* shader arrays per 
> shader engine */
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index ed46692..cbf8f5c 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -3811,22 +3811,22 @@ VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
> return VK_SUCCESS;
>  }
>
>  void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
> VkPhysicalDevicephysicalDevice,
> const VkPhysicalDeviceExternalSemaphoreInfoKHR* 
> pExternalSemaphoreInfo,
> VkExternalSemaphorePropertiesKHR*   
> pExternalSemaphoreProperties)
>  {
> RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
>
> -   /* Require has_syncobj_wait for the syncobj signal ioctl introduced 
> at virtually the same time */
> -   if (pdevice->rad_info.has_syncobj_wait &&
> +   /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl 
> introduced at virtually the same time */
> +   if (pdevice->rad_info.has_syncobj_wait_for_submit &&
> (pExternalSemaphoreInfo->handleType == 
> VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
>  pExternalSemaphoreInfo->handleType == 
> VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
> pExternalSemaphoreProperties->exportFromImportedHandleTypes = 
> VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | 
> VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
> pExternalSemaphoreProperties->compatibleHandleTypes = 
> VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | 
> VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
> 

[Mesa-dev] [PATCH] mesa: remove dd_function_table::GetCompressedTexSubImage and clean it up

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/drivers/common/driverfuncs.c  |  1 -
 src/mesa/main/dd.h | 10 --
 src/mesa/main/texgetimage.c| 23 +++
 src/mesa/main/texgetimage.h|  8 
 src/mesa/state_tracker/st_cb_texture.c |  1 -
 5 files changed, 11 insertions(+), 32 deletions(-)

diff --git a/src/mesa/drivers/common/driverfuncs.c 
b/src/mesa/drivers/common/driverfuncs.c
index ddb4bb6..94dc0e6 100644
--- a/src/mesa/drivers/common/driverfuncs.c
+++ b/src/mesa/drivers/common/driverfuncs.c
@@ -94,21 +94,20 @@ _mesa_init_driver_functions(struct dd_function_table 
*driver)
driver->QueryInternalFormat = _mesa_query_internal_format_default;
driver->TexImage = _mesa_store_teximage;
driver->TexSubImage = _mesa_store_texsubimage;
driver->GetTexSubImage = _mesa_meta_GetTexSubImage;
driver->ClearTexSubImage = _mesa_meta_ClearTexSubImage;
driver->CopyTexSubImage = _mesa_meta_CopyTexSubImage;
driver->GenerateMipmap = _mesa_meta_GenerateMipmap;
driver->TestProxyTexImage = _mesa_test_proxy_teximage;
driver->CompressedTexImage = _mesa_store_compressed_teximage;
driver->CompressedTexSubImage = _mesa_store_compressed_texsubimage;
-   driver->GetCompressedTexSubImage = _mesa_GetCompressedTexSubImage_sw;
driver->BindTexture = NULL;
driver->NewTextureObject = _mesa_new_texture_object;
driver->DeleteTexture = _mesa_delete_texture_object;
driver->NewTextureImage = _swrast_new_texture_image;
driver->DeleteTextureImage = _swrast_delete_texture_image;
driver->AllocTextureImageBuffer = _swrast_alloc_texture_image_buffer;
driver->FreeTextureImageBuffer = _swrast_free_texture_image_buffer;
driver->MapTextureImage = _swrast_map_teximage;
driver->UnmapTextureImage = _swrast_unmap_teximage;
driver->DrawTex = _mesa_meta_DrawTex;
diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
index 4e4d2a6..3455ddb 100644
--- a/src/mesa/main/dd.h
+++ b/src/mesa/main/dd.h
@@ -330,30 +330,20 @@ struct dd_function_table {
 
/**
 * Called by glCompressedTexSubImage[123]D().
 */
void (*CompressedTexSubImage)(struct gl_context *ctx, GLuint dims,
  struct gl_texture_image *texImage,
  GLint xoffset, GLint yoffset, GLint zoffset,
  GLsizei width, GLsizei height, GLsizei depth,
  GLenum format,
  GLsizei imageSize, const GLvoid *data);
-
-   /**
-* Called by glGetCompressedTexImage.
-*/
-   void (*GetCompressedTexSubImage)(struct gl_context *ctx,
-struct gl_texture_image *texImage,
-GLint xoffset, GLint yoffset,
-GLint zoffset, GLsizei width,
-GLsizei height, GLsizei depth,
-GLvoid *data);
/*@}*/
 
/**
 * \name Texture object / image functions
 */
/*@{*/
 
/**
 * Called by glBindTexture() and glBindTextures().
 */
diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c
index 26cf3e5..c61842e 100644
--- a/src/mesa/main/texgetimage.c
+++ b/src/mesa/main/texgetimage.c
@@ -754,30 +754,29 @@ _mesa_GetTexSubImage_sw(struct gl_context *ctx,
}
 
if (_mesa_is_bufferobj(ctx->Pack.BufferObj)) {
   ctx->Driver.UnmapBuffer(ctx, ctx->Pack.BufferObj, MAP_INTERNAL);
}
 }
 
 
 
 /**
- * This is the software fallback for Driver.GetCompressedTexSubImage().
- * All error checking will have been done before this routine is called.
+ * This function assumes that all error checking has been done.
  */
-void
-_mesa_GetCompressedTexSubImage_sw(struct gl_context *ctx,
-  struct gl_texture_image *texImage,
-  GLint xoffset, GLint yoffset,
-  GLint zoffset, GLsizei width,
-  GLint height, GLint depth,
-  GLvoid *img)
+static void
+get_compressed_texsubimage_sw(struct gl_context *ctx,
+  struct gl_texture_image *texImage,
+  GLint xoffset, GLint yoffset,
+  GLint zoffset, GLsizei width,
+  GLint height, GLint depth,
+  GLvoid *img)
 {
const GLuint dimensions =
   _mesa_get_texture_dimensions(texImage->TexObject->Target);
struct compressed_pixelstore store;
GLint slice;
GLubyte *dest;
 
_mesa_compute_compressed_pixelstore(dimensions, texImage->TexFormat,
width, height, depth,
>Pack, );
@@ -1654,23 +1653,23 @@ get_compressed_texture_image(struct gl_context *ctx,
   firstFace = 

[Mesa-dev] [PATCH] ac: rename has_syncobj_wait -> has_syncobj_wait_for_submit

[Marek Olšák]

From: Marek Olšák 

---
 src/amd/common/ac_gpu_info.c  | 2 +-
 src/amd/common/ac_gpu_info.h  | 2 +-
 src/amd/vulkan/radv_device.c  | 6 +++---
 src/amd/vulkan/radv_extensions.py | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index c042bb2..2599fb6 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -270,21 +270,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->max_se = amdinfo->num_shader_engines;
info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
info->has_hw_decode =
(uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
info->uvd_fw_version =
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
vce.available_rings ? vce_version : 0;
info->has_userptr = true;
info->has_syncobj = has_syncobj(fd);
-   info->has_syncobj_wait = info->has_syncobj && info->drm_minor >= 20;
+   info->has_syncobj_wait_for_submit = info->has_syncobj && 
info->drm_minor >= 20;
info->has_sync_file = info->has_syncobj && info->drm_minor >= 21;
info->has_ctx_priority = info->drm_minor >= 22;
info->num_render_backends = amdinfo->rb_pipes;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
if (!info->clock_crystal_freq) {
fprintf(stderr, "amdgpu: clock crystal frequency is 0, 
timestamps will be wrong\n");
info->clock_crystal_freq = 1;
}
info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
if (info->chip_class == GFX9) {
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 04e17f9..235cc24 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -74,21 +74,21 @@ struct radeon_info {
uint32_tvce_harvest_config;
uint32_tclock_crystal_freq;
uint32_ttcc_cache_line_size;
 
/* Kernel info. */
uint32_tdrm_major; /* version */
uint32_tdrm_minor;
uint32_tdrm_patchlevel;
boolhas_userptr;
boolhas_syncobj;
-   boolhas_syncobj_wait;
+   boolhas_syncobj_wait_for_submit;
boolhas_sync_file;
boolhas_ctx_priority;
 
/* Shader cores. */
uint32_tr600_max_quad_pipes; /* wave size / 16 */
uint32_tmax_shader_clock;
uint32_tnum_good_compute_units;
uint32_tmax_se; /* shader engines */
uint32_tmax_sh_per_se; /* shader arrays per shader 
engine */
 
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index ed46692..cbf8f5c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3811,22 +3811,22 @@ VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
return VK_SUCCESS;
 }
 
 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
VkPhysicalDevicephysicalDevice,
const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
VkExternalSemaphorePropertiesKHR*   
pExternalSemaphoreProperties)
 {
RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
 
-   /* Require has_syncobj_wait for the syncobj signal ioctl introduced at 
virtually the same time */
-   if (pdevice->rad_info.has_syncobj_wait &&
+   /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl 
introduced at virtually the same time */
+   if (pdevice->rad_info.has_syncobj_wait_for_submit &&
(pExternalSemaphoreInfo->handleType == 
VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR || 
 pExternalSemaphoreInfo->handleType == 
VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
pExternalSemaphoreProperties->exportFromImportedHandleTypes = 
VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | 
VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
pExternalSemaphoreProperties->compatibleHandleTypes = 
VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | 
VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
pExternalSemaphoreProperties->externalSemaphoreFeatures = 
VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
} else if (pExternalSemaphoreInfo->handleType == 
VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
pExternalSemaphoreProperties->exportFromImportedHandleTypes = 

[Mesa-dev] [PATCH 1/3] Add meson build system

[Dylan Baker]

This patch adds a complete meson build system, including tests and
install. It has the necessary hooks to allow it be used as a subproject
for other meson based builds such as mesa.

Signed-off-by: Dylan Baker 
---
 .editorconfig   |   4 +-
 amdgpu/.editorconfig|   5 +-
 amdgpu/meson.build  |  70 +++-
 data/meson.build|  27 +++-
 etnaviv/meson.build |  64 ++-
 exynos/meson.build  |  53 +-
 freedreno/meson.build   |  82 -
 intel/meson.build   | 111 +++-
 libkms/meson.build  |  75 +++-
 man/meson.build |  66 ++-
 meson.build | 378 +-
 meson_options.txt   |  38 -
 nouveau/meson.build |  65 ++-
 omap/meson.build|  53 +-
 radeon/meson.build  |  65 ++-
 tegra/meson.build   |  52 +-
 tests/amdgpu/meson.build|  40 -
 tests/etnaviv/meson.build   |  54 +-
 tests/exynos/meson.build|  54 +-
 tests/kms/meson.build   |  54 +-
 tests/kmstest/meson.build   |  28 +++-
 tests/meson.build   |  85 -
 tests/modeprint/meson.build |  29 +++-
 tests/nouveau/meson.build   |  30 +++-
 tests/proptest/meson.build  |  30 +++-
 tests/radeon/meson.build|  27 +++-
 tests/tegra/meson.build |  27 +++-
 tests/util/meson.build  |  37 -
 tests/vbltest/meson.build   |  28 +++-
 vc4/meson.build |  28 +++-
 30 files changed, 1759 insertions(+)
 create mode 100644 amdgpu/meson.build
 create mode 100644 data/meson.build
 create mode 100644 etnaviv/meson.build
 create mode 100644 exynos/meson.build
 create mode 100644 freedreno/meson.build
 create mode 100644 intel/meson.build
 create mode 100644 libkms/meson.build
 create mode 100644 man/meson.build
 create mode 100644 meson.build
 create mode 100644 meson_options.txt
 create mode 100644 nouveau/meson.build
 create mode 100644 omap/meson.build
 create mode 100644 radeon/meson.build
 create mode 100644 tegra/meson.build
 create mode 100644 tests/amdgpu/meson.build
 create mode 100644 tests/etnaviv/meson.build
 create mode 100644 tests/exynos/meson.build
 create mode 100644 tests/kms/meson.build
 create mode 100644 tests/kmstest/meson.build
 create mode 100644 tests/meson.build
 create mode 100644 tests/modeprint/meson.build
 create mode 100644 tests/nouveau/meson.build
 create mode 100644 tests/proptest/meson.build
 create mode 100644 tests/radeon/meson.build
 create mode 100644 tests/tegra/meson.build
 create mode 100644 tests/util/meson.build
 create mode 100644 tests/vbltest/meson.build
 create mode 100644 vc4/meson.build

diff --git a/.editorconfig b/.editorconfig
index 893b7be..bbad3e6 100644
--- a/.editorconfig
+++ b/.editorconfig
@@ -17,3 +17,7 @@ indent_style = tab
 [*.m4]
 indent_style = space
 indent_size = 2
+
+[meson.build,meson_options.txt]
+indent_style = space
+indent_size = 2
diff --git a/amdgpu/.editorconfig b/amdgpu/.editorconfig
index 2528d67..0c758d6 100644
--- a/amdgpu/.editorconfig
+++ b/amdgpu/.editorconfig
@@ -7,3 +7,8 @@ indent_style = tab
 indent_size = 8
 tab_width = 8
 insert_final_newline = true
+
+[meson.build]
+indent_style = space
+indent_size = 2
+insert_final_newline = false
diff --git a/amdgpu/meson.build b/amdgpu/meson.build
new file mode 100644
index 000..13bf88b
--- /dev/null
+++ b/amdgpu/meson.build
@@ -0,0 +1,70 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+files_amdgpu = files(
+  'amdgpu_asic_id.c',
+  'amdgpu_bo.c',
+  'amdgpu_cs.c',
+  'amdgpu_device.c',
+  'amdgpu_gpu_info.c',
+  'amdgpu_internal.h',
+  'amdgpu_vamgr.c',
+  'amdgpu_vm.c',
+  'util_hash.c',
+  'util_hash.h',
+  'util_hash_table.c',
+  'util_hash_table.h',
+)
+
+libdrm_amdgpu = shared_library(
+  'drm_amdgpu',
+  [files_amdgpu, config_file],
+  c_args : [
+warn_c_args,
+

[Mesa-dev] [PATCH 3/3] README: Add note about meson

[Dylan Baker]

Signed-off-by: Dylan Baker 
---
 README | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/README b/README
index 26cab9d..58e55bc 100644
--- a/README
+++ b/README
@@ -15,9 +15,24 @@ with an older kernel.
 Compiling
 -
 
-libdrm  is  a  standard  autotools  package and  follows  the  normal
-configure, build  and install steps.   The first step is  to configure
-the package, which is done by running the configure shell script:
+libdrm has two build systems, a legacy autotools build system, and a newer
+meson build system. The meson build system is much faster, and offers a 
+slightly different interface, but otherwise provides much the same 
+feature set.
+
+To use it:
+
+meson builddir
+
+By default this will install into /usr/local, you can change your prefix
+with --prefix=/usr (or -Dprefix=/usr to meson configure).
+
+Then use ninja to build and install:
+
+ninja -C builddir install
+
+
+Alternatively you can invoke autotools configure:
 
./configure
 
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH 2/3] autotools: Include meson.build files in tarball

[Dylan Baker]

I have tested that a tarball generated by autotools can be built with meson.

Signed-off-by: Dylan Baker 
---
 Makefile.am | 30 +-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/Makefile.am b/Makefile.am
index 7b86214..66f70ca 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -135,7 +135,35 @@ if HAVE_VMWGFX
 klibdrminclude_HEADERS += $(LIBDRM_INCLUDE_VMWGFX_H_FILES)
 endif
 
-EXTRA_DIST = include/drm/README
+EXTRA_DIST = \
+   include/drm/README \
+   amdgpu/meson.build \
+   etnaviv/meson.build \
+   exynos/meson.build \
+   freedreno/meson.build \
+   intel/meson.build \
+   libkms/meson.build \
+   man/meson.build \
+   nouveau/meson.build \
+   omap/meson.build \
+   radeon/meson.build \
+   tests/amdgpu/meson.build \
+   tests/etnaviv/meson.build \
+   tests/exynos/meson.build \
+   tests/kms/meson.build \
+   tests/kmstest/meson.build \
+   tests/modeprint/meson.build \
+   tests/nouveau/meson.build \
+   tests/proptest/meson.build \
+   tests/radeon/meson.build \
+   tests/tegra/meson.build \
+   tests/util/meson.build \
+   tests/vbltest/meson.build \
+   tests/meson.build \
+   vc4/meson.build \
+   data/meson.build \
+   meson.build \
+   meson_options.txt
 
 copy-headers :
cp -r $(kernel_source)/include/uapi/drm/*.h $(top_srcdir)/include/drm/
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH 0/3] Meson build system

[Dylan Baker]

This is a third iteration of the meson build system for libdrm. This
version is significantly cleaned up from the last version and uses a
style more like the build system in mesa.

It builds all of the drivers and tests, and the tests can be run via
`ninja test`.

It has support for being used as a wrapped dependency wit ext_foo
variables. This means it can be used to build a mesa that requires a
newer libdrm than the system provides (which can be especially useful if
you can't install packages on that system) and for testing.

This has been build tested only.

Dylan Baker (3):
  Add meson build system
  autotools: Include meson.build files in tarball
  README: Add note about meson

 .editorconfig   |   4 +-
 Makefile.am |  30 ++-
 README  |  21 +-
 amdgpu/.editorconfig|   5 +-
 amdgpu/meson.build  |  70 +++-
 data/meson.build|  27 +++-
 etnaviv/meson.build |  64 ++-
 exynos/meson.build  |  53 +-
 freedreno/meson.build   |  82 -
 intel/meson.build   | 111 +++-
 libkms/meson.build  |  75 +++-
 man/meson.build |  66 ++-
 meson.build | 378 +-
 meson_options.txt   |  38 -
 nouveau/meson.build |  65 ++-
 omap/meson.build|  53 +-
 radeon/meson.build  |  65 ++-
 tegra/meson.build   |  52 +-
 tests/amdgpu/meson.build|  40 -
 tests/etnaviv/meson.build   |  54 +-
 tests/exynos/meson.build|  54 +-
 tests/kms/meson.build   |  54 +-
 tests/kmstest/meson.build   |  28 +++-
 tests/meson.build   |  85 -
 tests/modeprint/meson.build |  29 +++-
 tests/nouveau/meson.build   |  30 +++-
 tests/proptest/meson.build  |  30 +++-
 tests/radeon/meson.build|  27 +++-
 tests/tegra/meson.build |  27 +++-
 tests/util/meson.build  |  37 -
 tests/vbltest/meson.build   |  28 +++-
 vc4/meson.build |  28 +++-
 32 files changed, 1806 insertions(+), 4 deletions(-)
 create mode 100644 amdgpu/meson.build
 create mode 100644 data/meson.build
 create mode 100644 etnaviv/meson.build
 create mode 100644 exynos/meson.build
 create mode 100644 freedreno/meson.build
 create mode 100644 intel/meson.build
 create mode 100644 libkms/meson.build
 create mode 100644 man/meson.build
 create mode 100644 meson.build
 create mode 100644 meson_options.txt
 create mode 100644 nouveau/meson.build
 create mode 100644 omap/meson.build
 create mode 100644 radeon/meson.build
 create mode 100644 tegra/meson.build
 create mode 100644 tests/amdgpu/meson.build
 create mode 100644 tests/etnaviv/meson.build
 create mode 100644 tests/exynos/meson.build
 create mode 100644 tests/kms/meson.build
 create mode 100644 tests/kmstest/meson.build
 create mode 100644 tests/meson.build
 create mode 100644 tests/modeprint/meson.build
 create mode 100644 tests/nouveau/meson.build
 create mode 100644 tests/proptest/meson.build
 create mode 100644 tests/radeon/meson.build
 create mode 100644 tests/tegra/meson.build
 create mode 100644 tests/util/meson.build
 create mode 100644 tests/vbltest/meson.build
 create mode 100644 vc4/meson.build

base-commit: 831036a6f62005da9fb4a75fe043bd96ce672d27
-- 
git-series 0.9.1
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Re: [Mesa-dev] [PATCH] i965/miptree: Fail gracefully when make_surface returns NULL

[Jason Ekstrand]

This patch looks good in isolation and you can have my rb.  However, this 
all a bit concerning and it makes me wonder if we're papering over the real 
bug.



On January 3, 2018 12:41:56 "Ian Romanick"  wrote:


From: Ian Romanick 

Every other caller of make_surface does something sensible when NULL is
returned.

Signed-off-by: Ian Romanick 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104214
Tested-by: Cyril 
Cc: "17.3" 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

index ead0c35..0079a08 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -719,6 +719,9 @@ miptree_create(struct brw_context *brw,
  ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
  BO_ALLOC_BUSY, 0, NULL);

+  if (mt == NULL)
+ return NULL;
+
   if (needs_separate_stencil(brw, mt, format) &&
   !make_separate_stencil_surface(brw, mt)) {
  intel_miptree_release();
--
2.9.5

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Re: [Mesa-dev] 10-bit Mesa/Gallium support

[Ilia Mirkin]

On Tue, Jan 2, 2018 at 11:51 PM, Mario Kleiner
 wrote:
> On 12/31/2017 05:53 PM, Ilia Mirkin wrote:
>> I went through and added support for xbgr2101010 throughout (and
>> hacked the kernel to assume that 30bpp == that).
>>
>
> Cool!
>
>> Your (I hope latest) patches + my mesa patches are available at
>> https://github.com/imirkin/mesa/commits/30bpp . It all seems to not be
>
>
> Yes, those are the latest patches. It would be great if somebody could push
> them to master now if there aren't any objections, given that they are all
> tested, and reviewed by Marek and Tapani, and as far as i'm concerned
> finished at least for intel and amd. Having a new baseline to work off
> without rebasing and manually resolving frequent merge conflicts would be
> nice.

Please try to get Marek to merge it. I wouldn't feel comfortable doing
it until it was all worked out on NVIDIA, and I think you're much
closer on other hardware.

>
>> totally broken, at least glxgears colors are right with X -depth 30.
>> And rendercheck seems not extremely unhappy either (with
>> xf86-video-nouveau at least). DRI3 seems broken for some reason that I
>> haven't determined yet (client stops sending stuff at the protocol
>> level after the Open call, but I'm weak on what the protocol _should_
>> be), but DRI2 is totally fine. (And DRI3 is apparently
>> broken-by-design anyways on all EXA drivers I guess, so I'm not going
>> to loose too much sleep over it.)
>>
>
> I'll give them a try when i get back to my machines and colorimeter sometime
> within the next couple of days.
>
>> Like you said, Kepler+ supports ARGB, but Tesla and Fermi are stuck
>> with ABGR. If possible (which in this case it seems to be), I'd rather
>> maximise the amount of hardware this can all work with.
>>
>
> Having it working on older gpu's would be nice - most of mine are still
> tesla. I assume the downside is Prime renderoffload with intel + nvidia
> won't automagically work anymore? Unless we can do a format conversion xbgr
> -> xrgb during the blitImage op that converts from tiled renderoffload gpu
> format to the linear scanout format of the display gpu? Or make the exported
> format dependent on what the display gpu prefers.

I hadn't considered PRIME offload. I was so happy when the spinning
gears had the correct colors... In theory, the NVIDIA gpu will happily
render to either ABGR or ARGB. It can only scan out one of those, but
assuming that my fiddling with flags doesn't mess up the infra's
ability to allocate a properly-formatted buffer to pass in for
rendering, it should all be fine.

>
>> If you do decide to play with it, on top of the hack to make 30bpp ==
>> xbgr, if you want to use GF119+, you also need to apply
>> https://lists.freedesktop.org/archives/nouveau/2017-December/029408.html
>
>
> Do i understand that patch correctly, that the current code for gf119+
> enabled a 1024 slot lut, but only initialized the first 256 slots? And then

More like every 4th slot, which worked just fine for 8bpc buffers.

> a 8 bpc fb would only index the properly initialized slots, but the 10 bpc
> fb also indexed into the 768 uninitialized slots? And your patch switches
> back to pure 256 slot lut? That would explain the kind of corruption i've
> seen on maxwell and pascal which made things untestable on those cards.

Correct. Ideally we'd want to use a 1024-position LUT, but legacy API
/ software sadness prevents it for now. There must be a clean way out
of all this, but it'll be more involved -- I took the quick way
initially, esp since it's no worse than what we're doing today.

>
>> -- I'm going to send out an email about the whole LUT situation, but
>> the backwards-compatibility makes it all rather annoying. I suspect
>> that without either disabling the LUT (which would be easy to hack
>> nv50_display.c to do), or using a 1024-entry LUT, you won't get actual
>> 10bpp per channel, still just 8bpp. But can't really tell from just
>> looking at the SMPTE pattern on my fading LCD monitor :) The
>> 1024-entry LUT is only available on GF119+, so I'm curious whether
>> earlier chips can output 10bpp at all, or if it all gets chopped down
>> to 8bpp "on the wire" even if LUT is disabled. Perhaps you can
>> experiment with a colorimeter and known-good display if you get some
>> time.
>
>
> I enabled the spatial dithering to 8 bpc via xrandr props, outputting to two
> different 8 bpc panels via DVI and HDMI iirc and measuring that i got 10 bpc
> on GeForce 9600 and 330M, so that worked fine enough to at least convince
> the colorimeter and my eyes. Years ago i also measured native VGA out to a
> CRT via DVI-I with the builtin 10 bit dacs of a GeForce 8800 with the
> proprietary driver.
>
> I could misremember, with my poor memory and all the testing i did lately on
> different gpu's, but i think what happened on nvidia with the nouveau
> programmed lut's (also under linux 4.4 with the old lut setup code) was that
> the lut's at least on 

[Mesa-dev] [PATCH] radv: Use correct HTILE expanded words.

[Bas Nieuwenhuizen]

Seems like users are actually hitting 0x actually making
things broken for them, and the mad max regression is fixed, so
lets put this in once more.

v2: Use 0xf for depth-only htile. (Dave)

Fixes: af2844116fd "radv: Revert HTILE reset word to 0x."
---
 src/amd/vulkan/radv_cmd_buffer.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7c86aa9d8c1..c6d7ca9b171 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3789,7 +3789,8 @@ void radv_CmdEndRenderPass(
 
 /*
  * For HTILE we have the following interesting clear words:
- *   0x030f: Uncompressed.
+ *   0x030f: Uncompressed for depth+stencil HTILE.
+ *   0x000f: Uncompressed for depth only HTILE.
  *   0xfff0: Clear depth to 1.0
  *   0x: Clear depth to 0.0
  */
@@ -3837,7 +3838,8 @@ static void radv_handle_depth_image_transition(struct 
radv_cmd_buffer *cmd_buffe
radv_initialize_htile(cmd_buffer, image, range, 0);
} else if (!radv_layout_is_htile_compressed(image, src_layout, 
src_queue_mask) &&
   radv_layout_is_htile_compressed(image, dst_layout, 
dst_queue_mask)) {
-   radv_initialize_htile(cmd_buffer, image, range, 0x);
+   uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 
0x30f : 0xf;
+   radv_initialize_htile(cmd_buffer, image, range, clear_value);
} else if (radv_layout_is_htile_compressed(image, src_layout, 
src_queue_mask) &&
   !radv_layout_is_htile_compressed(image, dst_layout, 
dst_queue_mask)) {
VkImageSubresourceRange local_range = *range;
-- 
2.15.1

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[Mesa-dev] [Bug 104214] Dota crashes when switching from game to desktop

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104214

Ian Romanick  changed:

   What|Removed |Added

 Status|NEEDINFO|ASSIGNED

--- Comment #16 from Ian Romanick  ---
(In reply to Cyril from comment #15)
> (In reply to Ian Romanick from comment #14)
> > (In reply to Cyril from comment #13)
> > > The game start with the patch on top of mesa-17.3.1.
> > > 
> > > Also tried the Steam overlay (Shift+tab) and switching desktop while in
> > > game, had no crash so it seems good.
> > 
> > And does everything look correct too?
> 
> I don't see any artifacts or glitches, it does look good to me. In the other
> hand, i only tested for 3/4 min as i don't have enough time for an entire
> game right now.

Excellent.  I've sent a patch to the list with your Tested-by added.

https://patchwork.freedesktop.org/patch/195626/

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Re: [Mesa-dev] [PATCH 02/22] gallium: rename pipe fences to semaphores

[Cherniak, Bruce]

On Dec 21, 2017, at 6:41 PM, Andres Rodriguez 
> wrote:

Rename fences -> semaphores in preparation for upgrading fence
functionality.

This series renames the following symbols:
 - pipe_fence_handle -> pipe_semaphore_handle
 - fence_server_sync -> semaphore_server_sync
 - create_fence_fd -> create_semaphore_fd
 - fence_reference -> semaphore_reference
 - fence_finish -> semaphore_finish
 - fence_get_fd -> semaphore_get_fd
 - PIPE_FLUSH_FENCE_FD -> PIPE_FLUSH_SEMAPHORE_FD
 - PIPE_CAP_NATIVE_FENCE_FD -> PIPE_CAP_NATIVE_SEMAPHORE_FD

This patch does not introduce any functionality changes.

Hi Andres.  This rename leaves the drivers in a weird mixed nomenclature between
fence and semaphore.  Is there a plan to clean this up?

Example, pulled from lp_screen.c:

* Fence reference counting.
*/
static void
-llvmpipe_fence_reference(struct pipe_screen *screen,
- struct pipe_fence_handle **ptr,
- struct pipe_fence_handle *fence)
+llvmpipe_semaphore_reference(struct pipe_screen *screen,
+ struct pipe_semaphore_handle **ptr,
+ struct pipe_semaphore_handle *fence)
{
  struct lp_fence **old = (struct lp_fence **) ptr;
  struct lp_fence *f = (struct lp_fence *) fence;

-   lp_fence_reference(old, f);
+   lp_semaphore_reference(old, f);
}

We're casting semaphore handles to lp_fence pointers and passing
fences into lp_semaphore_reference.  A confusing mix of terminology.

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[Mesa-dev] [PATCH] radv: Use correct HTILE expanded words.

[Bas Nieuwenhuizen]

Seems like users are actually hitting 0x actually making
things broken for them, and the mad max regression is fixed, so
lets put this in once more.

Fixes: af2844116fd "radv: Revert HTILE reset word to 0x."
---
 src/amd/vulkan/radv_cmd_buffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7c86aa9d8c1..ae2727ee647 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3837,7 +3837,7 @@ static void radv_handle_depth_image_transition(struct 
radv_cmd_buffer *cmd_buffe
radv_initialize_htile(cmd_buffer, image, range, 0);
} else if (!radv_layout_is_htile_compressed(image, src_layout, 
src_queue_mask) &&
   radv_layout_is_htile_compressed(image, dst_layout, 
dst_queue_mask)) {
-   radv_initialize_htile(cmd_buffer, image, range, 0x);
+   radv_initialize_htile(cmd_buffer, image, range, 0x30f);
} else if (radv_layout_is_htile_compressed(image, src_layout, 
src_queue_mask) &&
   !radv_layout_is_htile_compressed(image, dst_layout, 
dst_queue_mask)) {
VkImageSubresourceRange local_range = *range;
-- 
2.15.1

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Re: [Mesa-dev] [PATCH] mesa/bindless: fix missing image _Layer initialization

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 12/30/2017 06:30 AM, Ilia Mirkin wrote:

Some later code relies on _Layer to set first/last_layer. Make sure it's
always initialized.

Detected by valgrind's conditional jump/move with uninit value logic.

Signed-off-by: Ilia Mirkin 
---
  src/mesa/main/texturebindless.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/src/mesa/main/texturebindless.c b/src/mesa/main/texturebindless.c
index f062ea904a1..9aaa0367c2d 100644
--- a/src/mesa/main/texturebindless.c
+++ b/src/mesa/main/texturebindless.c
@@ -327,6 +327,7 @@ get_image_handle(struct gl_context *ctx, struct 
gl_texture_object *texObj,
 } else {
imgObj.Layered = GL_FALSE;
imgObj.Layer = 0;
+  imgObj._Layer = 0;
 }
  
 /* Request a new image handle from the driver. */



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Re: [Mesa-dev] Allocator Nouveau driver, Mesa EXT_external_objects, and DRM metadata import interfaces

[James Jones]

On 12/28/2017 10:24 AM, Miguel Angel Vico wrote:

(Adding dri-devel back, and trying to respond to some comments from
the different forks)

James Jones wrote:


Your worst case analysis above isn't far off from our HW, give or take
some bits and axes here and there.  We've started an internal discussion
about how to lay out all the bits we need.  It's hard to even enumerate
them all without having a complete understanding of what capability sets
are going to include, a fully-optimized implementation of the mechanism
on our HW, and lot's of test scenarios though.


(thanks James for most of the info below)

To elaborate a bit, if we want to share an allocation across GPUs for 3D
rendering, it seems we would need 12 bits to express our
swizzling/tiling memory layouts for fermi+. In addition to that,
maxwell uses 3 more bits for this, and we need an extra bit to identify
pre-fermi representations.

We also need one bit to differentiate between Tegra and desktop, and
another one to indicate whether the layout is otherwise linear.

Then things like whether compression is used (one more bit), and we can
probably get by with 3 bits for the type of compression if we are
creative. However, it'd be way easier to just track arch + page kind,
which would be like 32 bits on its own.


Not clear if this is an NV-only term, so for those not familiar, page 
kind is very loosely the equivalent of a format modifier our HW uses 
internally in its memory management subsystem.  The value mappings vary 
a bit for each HW generation.



Whether Z-culling and/or zero-bandwidth-clears are used may be another 3
bits.

If device-local properties are included, we might need a couple more
bits for caching.

We may also need to express locality information, which may take at
least another 2 or 3 bits.

If we want to share array textures too, you also need to pass the array
pitch. Is it supposed to be encoded in a modifier too? That's 64 bits on
its own.

So yes, as James mentioned, with some effort, we could technically fit
our current allocation parameters in a modifier, but I'm still not
convinced this is as future proof as it could be as our hardware grows
in capabilities.


Daniel Stone wrote:


So I reflexively
get a bit itchy when I see the kernel being used to transit magic
blobs of data which are supplied by userspace, and only interpreted by
different userspace. Having tiling formats hidden away means that
we've had real-world bugs in AMD hardware, where we end up displaying
garbage because we cannot generically reason about the buffer
attributes.


I'm a bit confused. Can't modifiers be specified by vendors and only
interpreted by drivers? My understanding was that modifiers could
actually be treated as opaque 64-bit data, in which case they would
qualify as "magic blobs of data". Otherwise, it seems this wouldn't be
scalable. What am I missing?


Daniel Vetter wrote:


I think in the interim figuring out how to expose kms capabilities
better (and necessarily standardizing at least some of them which
matter at the compositor level, like size limits of framebuffers)
feels like the place to push the ecosystem forward. In some way
Miguel's proposal looks a bit backwards, since it adds the pitch
capabilities to addfb, but at addfb time you've allocated everything
already, so way too late to fix things up. With modifiers we've added
a very simple per-plane property to list which modifiers can be
combined with which pixel formats. Tiny start, but obviously very far
from all that we'll need.


Not sure whether I might be misunderstanding your statement, but one of
the allocator main features is negotiation of nearly optimal allocation
parameters given a set of uses on different devices/engines by the
capability merge operation. A client should have queried what every
device/engine is capable of for the given uses, find the optimal set of
capabilities, and use it for allocating a buffer. At the moment these
parameters are given to KMS, they are expected to be good. If they
aren't, the client didn't do things right.


Rob Clark wrote:


It does seem like, if possible, starting out with modifiers for now at
the kernel interface would make life easier, vs trying to reinvent
both kernel and userspace APIs at the same time.  Userspace APIs are
easier to change or throw away.  Presumably by the time we get to the
point of changing kernel uabi, we are already using, and pretty happy
with, serialized liballoc data over the wire in userspace so it is
only a matter of changing the kernel interface.


I guess we can indeed start with modifiers for now, if that's what it
takes to get the allocator mechanisms rolling. However, it seems to me
that we won't be able to encode the same type of information included
in capability sets with modifiers in all cases. For instance, if we end
up encoding usage transition information in capability sets, how that
would translate to modifiers?

I assume display doesn't really care about a lot of the data 

[Mesa-dev] [PATCH] i965/miptree: Fail gracefully when make_surface returns NULL

[Ian Romanick]

From: Ian Romanick 

Every other caller of make_surface does something sensible when NULL is
returned.

Signed-off-by: Ian Romanick 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104214
Tested-by: Cyril 
Cc: "17.3" 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ead0c35..0079a08 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -719,6 +719,9 @@ miptree_create(struct brw_context *brw,
  ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
  BO_ALLOC_BUSY, 0, NULL);
 
+  if (mt == NULL)
+ return NULL;
+
   if (needs_separate_stencil(brw, mt, format) &&
   !make_separate_stencil_surface(brw, mt)) {
  intel_miptree_release();
-- 
2.9.5

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Re: [Mesa-dev] [PATCH] meson: nir_control_flow_test needs to depend on nir_builder_opcodes_h

[Dylan Baker]

I have such a patch series :)

It just needs a little more testing and this resolves an intermittent build
failure in the CI.

Quoting Jason Ekstrand (2018-01-03 09:37:36)
> Is there any way we can just make a "nir_deps" helper list and put
> nir_builder_opcodes_h in it?  Requiring everything which depends on nir gather
> up a bunch of random generator dependencies seems a bit fragile.
> 
> On Wed, Jan 3, 2018 at 9:28 AM, Dylan Baker  wrote:
> 
> Fixes a race condition in the build which causes sporadic failures when
> -Dbuild-tests=true and a significant number of cores is present.
> 
> Fixes: d1992255bb29 ("meson: Add build Intel "anv" vulkan driver")
> CC: Mark Janes 
> Signed-off-by: Dylan Baker 
> ---
>  src/compiler/nir/meson.build | 20 +++-
>  1 file changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> index 5dd21e6652f..7d2309078b1 100644
> --- a/src/compiler/nir/meson.build
> +++ b/src/compiler/nir/meson.build
> @@ -208,14 +208,16 @@ libnir = static_library(
>  nir_algebraic_py = files('nir_algebraic.py')
> 
>  if with_tests
> -  nir_control_flow_test = executable(
> -    'nir_control_flow_test',
> -    [files('tests/control_flow_tests.cpp'), nir_opcodes_h],
> -    c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
> -    include_directories : [inc_common],
> -    dependencies : [dep_thread, idep_gtest],
> -    link_with : [libmesa_util, libnir],
> +  test(
> +    'nir_control_flow',
> +    executable(
> +      'nir_control_flow_test',
> +      [files('tests/control_flow_tests.cpp'), nir_opcodes_h,
> +       nir_builder_opcodes_h],
> +      c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
> +      include_directories : [inc_common],
> +      dependencies : [dep_thread, idep_gtest],
> +      link_with : [libmesa_util, libnir],
> +    )
>    )
> -
> -  test('nir_control_flow', nir_control_flow_test)
>  endif
> --
> 2.15.1
> 
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> 


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Re: [Mesa-dev] [PATCH] meson: nir_control_flow_test needs to depend on nir_builder_opcodes_h

[Jason Ekstrand]

Is there any way we can just make a "nir_deps" helper list and put
nir_builder_opcodes_h in it?  Requiring everything which depends on nir
gather up a bunch of random generator dependencies seems a bit fragile.

On Wed, Jan 3, 2018 at 9:28 AM, Dylan Baker  wrote:

> Fixes a race condition in the build which causes sporadic failures when
> -Dbuild-tests=true and a significant number of cores is present.
>
> Fixes: d1992255bb29 ("meson: Add build Intel "anv" vulkan driver")
> CC: Mark Janes 
> Signed-off-by: Dylan Baker 
> ---
>  src/compiler/nir/meson.build | 20 +++-
>  1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> index 5dd21e6652f..7d2309078b1 100644
> --- a/src/compiler/nir/meson.build
> +++ b/src/compiler/nir/meson.build
> @@ -208,14 +208,16 @@ libnir = static_library(
>  nir_algebraic_py = files('nir_algebraic.py')
>
>  if with_tests
> -  nir_control_flow_test = executable(
> -'nir_control_flow_test',
> -[files('tests/control_flow_tests.cpp'), nir_opcodes_h],
> -c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
> -include_directories : [inc_common],
> -dependencies : [dep_thread, idep_gtest],
> -link_with : [libmesa_util, libnir],
> +  test(
> +'nir_control_flow',
> +executable(
> +  'nir_control_flow_test',
> +  [files('tests/control_flow_tests.cpp'), nir_opcodes_h,
> +   nir_builder_opcodes_h],
> +  c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
> +  include_directories : [inc_common],
> +  dependencies : [dep_thread, idep_gtest],
> +  link_with : [libmesa_util, libnir],
> +)
>)
> -
> -  test('nir_control_flow', nir_control_flow_test)
>  endif
> --
> 2.15.1
>
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[Mesa-dev] [PATCH] meson: nir_control_flow_test needs to depend on nir_builder_opcodes_h

[Dylan Baker]

Fixes a race condition in the build which causes sporadic failures when
-Dbuild-tests=true and a significant number of cores is present.

Fixes: d1992255bb29 ("meson: Add build Intel "anv" vulkan driver")
CC: Mark Janes 
Signed-off-by: Dylan Baker 
---
 src/compiler/nir/meson.build | 20 +++-
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 5dd21e6652f..7d2309078b1 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -208,14 +208,16 @@ libnir = static_library(
 nir_algebraic_py = files('nir_algebraic.py')
 
 if with_tests
-  nir_control_flow_test = executable(
-'nir_control_flow_test',
-[files('tests/control_flow_tests.cpp'), nir_opcodes_h],
-c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
-include_directories : [inc_common],
-dependencies : [dep_thread, idep_gtest],
-link_with : [libmesa_util, libnir],
+  test(
+'nir_control_flow',
+executable(
+  'nir_control_flow_test',
+  [files('tests/control_flow_tests.cpp'), nir_opcodes_h,
+   nir_builder_opcodes_h],
+  c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
+  include_directories : [inc_common],
+  dependencies : [dep_thread, idep_gtest],
+  link_with : [libmesa_util, libnir],
+)
   )
-
-  test('nir_control_flow', nir_control_flow_test)
 endif
-- 
2.15.1

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Re: [Mesa-dev] [PATCH] swr/rast: fix build break for llvm-6

[Cherniak, Bruce]

Reviewed-by: Bruce Cherniak 

> On Jan 2, 2018, at 10:57 AM, Tim Rowley  wrote:
> 
> LLVM api change.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104381
> ---
> src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp | 4 
> 1 file changed, 4 insertions(+)
> 
> diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp 
> b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
> index 3f0772c942..59672bb545 100644
> --- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
> +++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
> @@ -498,7 +498,11 @@ std::unique_ptr 
> JitCache::getObject(const llvm::Module* M)
> break;
> }
> 
> +#if LLVM_VERSION_MAJOR < 6
> pBuf = 
> llvm::MemoryBuffer::getNewUninitMemBuffer(size_t(header.GetBufferSize()));
> +#else
> +pBuf = 
> llvm::WritableMemoryBuffer::getNewUninitMemBuffer(size_t(header.GetBufferSize()));
> +#endif
> if (!fread(const_cast(pBuf->getBufferStart()), 
> header.GetBufferSize(), 1, fpIn))
> {
> pBuf = nullptr;
> -- 
> 2.14.1
> 
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Re: [Mesa-dev] [PATCH 1/3] spirv: Add a mechanism for dumping failing shaders

[Jason Ekstrand]

On Tue, Jan 2, 2018 at 4:55 PM, Ian Romanick  wrote:

> On 01/02/2018 04:24 PM, Grazvydas Ignotas wrote:
> > On Tue, Jan 2, 2018 at 6:30 PM, Jason Ekstrand 
> wrote:
> >> ---
> >>  src/compiler/spirv/spirv_to_nir.c | 29 +
> >>  src/compiler/spirv/vtn_private.h  |  1 +
> >>  2 files changed, 30 insertions(+)
> >>
> >> diff --git a/src/compiler/spirv/spirv_to_nir.c
> b/src/compiler/spirv/spirv_to_nir.c
> >> index dcff56f..751fb03 100644
> >> --- a/src/compiler/spirv/spirv_to_nir.c
> >> +++ b/src/compiler/spirv/spirv_to_nir.c
> >> @@ -31,6 +31,9 @@
> >>  #include "nir/nir_constant_expressions.h"
> >>  #include "spirv_info.h"
> >>
> >> +#include 
> >> +#include 
> >> +
> >>  void
> >>  vtn_log(struct vtn_builder *b, enum nir_spirv_debug_level level,
> >>  size_t spirv_offset, const char *message)
> >> @@ -94,6 +97,27 @@ vtn_log_err(struct vtn_builder *b,
> >> ralloc_free(msg);
> >>  }
> >>
> >> +static void
> >> +vtn_dump_shader(struct vtn_builder *b, const char *path, const char
> *prefix)
> >> +{
> >> +   static int idx = 0;
> >> +
> >> +   char filename[1024];
> >> +   int len = snprintf(filename, sizeof(filename), "%s/%s-%d.spirv",
> >> +  path, prefix, idx++);
> >> +   if (len < 0 || len >= sizeof(filename))
> >> +  return;
> >> +
> >> +   int fd = open(filename, O_CREAT | O_CLOEXEC | O_WRONLY, 0777);
> >> +   if (fd < 0)
> >> +  return;
> >> +
> >> +   write(fd, b->spirv, b->spirv_word_count * 4);
> >
> > Feel free to ignore, but what about * sizeof(b->spirv[0]) ?
> >
> > also, this emits a not-so-useful warning for me:
> > warning: ignoring return value of ‘write’, declared with attribute
> > warn_unused_result [-Wunused-result]
> > (and no, sticking (void) before write() doesn't help)
>
> Oh, that's annoying... but technically correct.  The problem is that
> write() might only write part of your data.  If the returned size is
> less than the size you asked, you have to try again.  This is why people
> use fopen/fwrite/fclose. :)  Either that or:
>

fopen/fwrite/fclose it is!


>
>ssize_t remain = b->spirv_word_count * 4;
>unsigned offset = 0;
>
>do {
>   ssize_t written =
>  write(fd, (uint8_t *) b->spriv + offset, remain);
>
>   if (written < 0) {
>  /* Error.  Bail out. */
>  break;
>}
>
>   remain -= written;
>   offset += written;
>} while (remain > 0);
>
> I'll let Jason pick. :D
>
> > Gražvydas
> > ___
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[Mesa-dev] [PATCH] egl/android: Fix build break with dri2_initialize_android _EGLDisplay parameter

[Rob Herring]

Commit 2f421651aca9 ("egl: let each platform decided how to handle
LIBGL_ALWAYS_SOFTWARE") broke the build due to copy-n-paste of misnamed
function parameter.:

src/egl/drivers/dri2/platform_android.c:1183:8: error: use of undeclared 
identifier 'disp'

Rather than just fixing 'disp', rename the function parameter 'dpy' to
'disp' to align with the other EGL platforms' implementations.

Fixes: 2f421651aca9 ("egl: let each platform decided how to handle 
LIBGL_ALWAYS_SOFTWARE")
Cc: Eric Engestrom 
Signed-off-by: Rob Herring 
---
 src/egl/drivers/dri2/platform_android.c | 30 +++---
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 34e3ef66bfeb..4f25cb746915 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -1173,7 +1173,7 @@ static const __DRIextension 
*droid_image_loader_extensions[] = {
 };
 
 EGLBoolean
-dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
+dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *disp)
 {
struct dri2_egl_display *dri2_dpy;
const char *err;
@@ -1197,7 +1197,7 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
   goto cleanup;
}
 
-   dpy->DriverData = (void *) dri2_dpy;
+   disp->DriverData = (void *) dri2_dpy;
 
dri2_dpy->fd = droid_open_device(dri2_dpy);
if (dri2_dpy->fd < 0) {
@@ -1217,43 +1217,43 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay 
*dpy)
 * the __DRI_DRI2_LOADER extension */
if (!dri2_dpy->is_render_node) {
   dri2_dpy->loader_extensions = droid_dri2_loader_extensions;
-  if (!dri2_load_driver(dpy)) {
+  if (!dri2_load_driver(disp)) {
  err = "DRI2: failed to load driver";
  goto cleanup;
   }
} else {
   dri2_dpy->loader_extensions = droid_image_loader_extensions;
-  if (!dri2_load_driver_dri3(dpy)) {
+  if (!dri2_load_driver_dri3(disp)) {
  err = "DRI3: failed to load driver";
  goto cleanup;
   }
}
 
-   if (!dri2_create_screen(dpy)) {
+   if (!dri2_create_screen(disp)) {
   err = "DRI2: failed to create screen";
   goto cleanup;
}
 
-   if (!dri2_setup_extensions(dpy)) {
+   if (!dri2_setup_extensions(disp)) {
   err = "DRI2: failed to setup extensions";
   goto cleanup;
}
 
-   dri2_setup_screen(dpy);
+   dri2_setup_screen(disp);
 
-   if (!droid_add_configs_for_visuals(drv, dpy)) {
+   if (!droid_add_configs_for_visuals(drv, disp)) {
   err = "DRI2: failed to add configs";
   goto cleanup;
}
 
-   dpy->Extensions.ANDROID_framebuffer_target = EGL_TRUE;
-   dpy->Extensions.ANDROID_image_native_buffer = EGL_TRUE;
-   dpy->Extensions.ANDROID_recordable = EGL_TRUE;
-   dpy->Extensions.EXT_buffer_age = EGL_TRUE;
+   disp->Extensions.ANDROID_framebuffer_target = EGL_TRUE;
+   disp->Extensions.ANDROID_image_native_buffer = EGL_TRUE;
+   disp->Extensions.ANDROID_recordable = EGL_TRUE;
+   disp->Extensions.EXT_buffer_age = EGL_TRUE;
 #if ANDROID_API_LEVEL >= 23
-   dpy->Extensions.KHR_partial_update = EGL_TRUE;
+   disp->Extensions.KHR_partial_update = EGL_TRUE;
 #endif
-   dpy->Extensions.KHR_image = EGL_TRUE;
+   disp->Extensions.KHR_image = EGL_TRUE;
 
/* Fill vtbl last to prevent accidentally calling virtual function during
 * initialization.
@@ -1263,6 +1263,6 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *dpy)
return EGL_TRUE;
 
 cleanup:
-   dri2_display_destroy(dpy);
+   dri2_display_destroy(disp);
return _eglError(EGL_NOT_INITIALIZED, err);
 }
-- 
2.14.1

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[Mesa-dev] [Bug 104214] Dota crashes when switching from game to desktop

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104214

--- Comment #15 from Cyril  ---
(In reply to Ian Romanick from comment #14)
> (In reply to Cyril from comment #13)
> > The game start with the patch on top of mesa-17.3.1.
> > 
> > Also tried the Steam overlay (Shift+tab) and switching desktop while in
> > game, had no crash so it seems good.
> 
> And does everything look correct too?

I don't see any artifacts or glitches, it does look good to me. In the other
hand, i only tested for 3/4 min as i don't have enough time for an entire game
right now.

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[Mesa-dev] [Bug 104214] Dota crashes when switching from game to desktop

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104214

Ian Romanick  changed:

   What|Removed |Added

 Status|NEW |NEEDINFO
   Assignee|mesa-dev@lists.freedesktop. |i...@freedesktop.org
   |org |

--- Comment #14 from Ian Romanick  ---
(In reply to Cyril from comment #13)
> The game start with the patch on top of mesa-17.3.1.
> 
> Also tried the Steam overlay (Shift+tab) and switching desktop while in
> game, had no crash so it seems good.

And does everything look correct too?

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Re: [Mesa-dev] Allocator Nouveau driver, Mesa EXT_external_objects, and DRM metadata import interfaces

[Rob Clark]

On Thu, Dec 28, 2017 at 1:24 PM, Miguel Angel Vico  wrote:
> (Adding dri-devel back, and trying to respond to some comments from
> the different forks)
>
> James Jones wrote:
>
>> Your worst case analysis above isn't far off from our HW, give or take
>> some bits and axes here and there.  We've started an internal discussion
>> about how to lay out all the bits we need.  It's hard to even enumerate
>> them all without having a complete understanding of what capability sets
>> are going to include, a fully-optimized implementation of the mechanism
>> on our HW, and lot's of test scenarios though.
>
> (thanks James for most of the info below)
>
> To elaborate a bit, if we want to share an allocation across GPUs for 3D
> rendering, it seems we would need 12 bits to express our
> swizzling/tiling memory layouts for fermi+. In addition to that,
> maxwell uses 3 more bits for this, and we need an extra bit to identify
> pre-fermi representations.
>
> We also need one bit to differentiate between Tegra and desktop, and
> another one to indicate whether the layout is otherwise linear.
>
> Then things like whether compression is used (one more bit), and we can
> probably get by with 3 bits for the type of compression if we are
> creative. However, it'd be way easier to just track arch + page kind,
> which would be like 32 bits on its own.
>
> Whether Z-culling and/or zero-bandwidth-clears are used may be another 3
> bits.
>
> If device-local properties are included, we might need a couple more
> bits for caching.
>
> We may also need to express locality information, which may take at
> least another 2 or 3 bits.
>
> If we want to share array textures too, you also need to pass the array
> pitch. Is it supposed to be encoded in a modifier too? That's 64 bits on
> its own.
>
> So yes, as James mentioned, with some effort, we could technically fit
> our current allocation parameters in a modifier, but I'm still not
> convinced this is as future proof as it could be as our hardware grows
> in capabilities.
>
>
> Daniel Stone wrote:
>
>> So I reflexively
>> get a bit itchy when I see the kernel being used to transit magic
>> blobs of data which are supplied by userspace, and only interpreted by
>> different userspace. Having tiling formats hidden away means that
>> we've had real-world bugs in AMD hardware, where we end up displaying
>> garbage because we cannot generically reason about the buffer
>> attributes.
>
> I'm a bit confused. Can't modifiers be specified by vendors and only
> interpreted by drivers? My understanding was that modifiers could
> actually be treated as opaque 64-bit data, in which case they would
> qualify as "magic blobs of data". Otherwise, it seems this wouldn't be
> scalable. What am I missing?
>
>
> Daniel Vetter wrote:
>
>> I think in the interim figuring out how to expose kms capabilities
>> better (and necessarily standardizing at least some of them which
>> matter at the compositor level, like size limits of framebuffers)
>> feels like the place to push the ecosystem forward. In some way
>> Miguel's proposal looks a bit backwards, since it adds the pitch
>> capabilities to addfb, but at addfb time you've allocated everything
>> already, so way too late to fix things up. With modifiers we've added
>> a very simple per-plane property to list which modifiers can be
>> combined with which pixel formats. Tiny start, but obviously very far
>> from all that we'll need.
>
> Not sure whether I might be misunderstanding your statement, but one of
> the allocator main features is negotiation of nearly optimal allocation
> parameters given a set of uses on different devices/engines by the
> capability merge operation. A client should have queried what every
> device/engine is capable of for the given uses, find the optimal set of
> capabilities, and use it for allocating a buffer. At the moment these
> parameters are given to KMS, they are expected to be good. If they
> aren't, the client didn't do things right.
>
>
> Rob Clark wrote:
>
>> It does seem like, if possible, starting out with modifiers for now at
>> the kernel interface would make life easier, vs trying to reinvent
>> both kernel and userspace APIs at the same time.  Userspace APIs are
>> easier to change or throw away.  Presumably by the time we get to the
>> point of changing kernel uabi, we are already using, and pretty happy
>> with, serialized liballoc data over the wire in userspace so it is
>> only a matter of changing the kernel interface.
>
> I guess we can indeed start with modifiers for now, if that's what it
> takes to get the allocator mechanisms rolling. However, it seems to me
> that we won't be able to encode the same type of information included
> in capability sets with modifiers in all cases. For instance, if we end
> up encoding usage transition information in capability sets, how that
> would translate to modifiers?
>
> I assume display doesn't really care about a lot of the data capability
> 

Re: [Mesa-dev] [PATCH][RFC] i965: allocate a SGVS element when VertexID or InstanceID are read in gen9+

[Jason Ekstrand]

On January 3, 2018 03:21:51 Iago Toral Quiroga  wrote:


Although in theory this should not be necessary it seems that doing this
fixes a spurious low rate failure of ~1% in a CTS test that seems to happen
in some gen9+ platforms only.

Fixes flakyness in:
KHR-GL45.vertex_attrib_64bit.limits_test

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104335
---

I am not sure why this fixes the spurious fails, but it clearly does, at 
least for

me. I have not seen any workarounds related to this in the PRMs so maybe
this is just papering over some other problem in the end. It would be great if
someone else could test this and verify that it fixes the spurious fails 
for them
as well and I'd also appreciate any thoughts on what could be causing this 
problem

and why this seems to fix it. There is more detail in the bug report.

 src/mesa/drivers/dri/i965/genX_state_upload.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c

index 50ac5bc59f..523e9688a6 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -494,12 +494,25 @@ genX(emit_vertices)(struct brw_context *brw)
 * values.  Additionally if there is an edge flag element then the SGVS
 * can't be inserted past that so we need a dummy element to ensure that
 * the edge flag is the last one.
+*
+* In gen9+, the CTS test KHR-GL45.vertex_attrib_64bit.limits_test fails
+* with a fail rate of ~1% for the cases where it reads gl_InstanceID 
but no

+* SGVS element is programmed. Programming the SGVS element in this case
+* seems to make the problem go away.
 */
+#if GEN_GEN >= 9
+   const bool needs_sgvs_element = (vs_prog_data->uses_basevertex ||
+vs_prog_data->uses_baseinstance ||
+vs_prog_data->uses_instanceid ||
+vs_prog_data->uses_vertexid);
+#else
const bool needs_sgvs_element = (vs_prog_data->uses_basevertex ||
 vs_prog_data->uses_baseinstance ||
 ((vs_prog_data->uses_instanceid ||
   vs_prog_data->uses_vertexid)
  && uses_edge_flag));


Something smells fishy here.  Why are the last to && with uses_edge_flag in 
the first place?  (That's a rhetorical question; I went and read the code.) 
It seems to me as if we want the element even if we're just going to put 
instance or vertex id in it.  In particular, I'm not sure that emitting 
3DSTATE_VERTEX_ELEMENTS actually clears out the elements not specified so 
we may have some random vertex element from a previous draw that we're 
overwriting. When you combine that with the following two restrictions, 
things could get very weird:


 It is INVALID to use this command to overwrite any portion of a 64-bit 
vertex element component.
 It is INVALID to use this command to overwrite a EdgeFlag vertex element 
component or any vertex

element beyond it.

I think this patch is probably more-or-less doing the right thing though I 
would argue we should probably do it on all gen8+ and we could pull 
needs_sgvs_element out of the #if entirely.  Good work hunting this down.


--Jason


+#endif
+
 #else
const bool needs_sgvs_element = (vs_prog_data->uses_basevertex ||
 vs_prog_data->uses_baseinstance ||
--
2.11.0

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Re: [Mesa-dev] bad object in mesa git repo

[Jason Ekstrand]

On January 3, 2018 02:15:08 Kevin Gallagher  wrote:


Hi,

Upon cloning the main mesa repository, git with fsckObjects enabled
(receive, transfer, fetch) reports an error:

error: object c2908f1b53c841bfa450b066c6fa1ee78c2fdb85:
missingSpaceBeforeDate: invalid author/committer line - missing
space before date
ba

This is true of anongit.freedesktop.org as well as github.com/mesa3d/mesa.

Someone mentioned this object in a previous thread:
https://lists.freedesktop.org/archives/mesa-dev/2016-February/106268.html
but it seems not to have been addressed. This should be straightforward
for a maintainer to fix with some investigation, git-fsck magic and
force push rights.


It's that last one that's the problem.  It's not that no one has force-push 
rights, it does happen in very rare cases.  However, if solving this 
problem requires blowing away years worth of git SHAs, that's not going to 
happen.  We use commit SHAs to tie things such as bug closures to the git 
history and breaking all those links would be bad.  Worse yet is that doing 
so would make hash of people's development branches and, lest you think 
that's no big deal, some of us have hundreds of them lying around.


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[Mesa-dev] [Bug 104478] Add EGL information to docs/features.txt

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104478

Dennis Schridde  changed:

   What|Removed |Added

   See Also||https://github.com/MightyCr
   ||eak/mesamatrix/issues/121

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[Mesa-dev] [Bug 104478] Add EGL information to docs/features.txt

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104478

Bug ID: 104478
   Summary: Add EGL information to docs/features.txt
   Product: Mesa
   Version: unspecified
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: EGL
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: dennis.schri...@uni-heidelberg.de
QA Contact: mesa-dev@lists.freedesktop.org

It would be nice if docs/features.txt would also contain information about what
EGL versions and extensions are supported.

This would e.g. allow for mesamatrix.net to display this information in a nice
way, and allow for users / developers to easily see what EGL parts will work
with Mesa.

See-Also: https://github.com/MightyCreak/mesamatrix/issues/121

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Re: [Mesa-dev] [PATCH v3 17/20] st/glsl_to_nir/radeonsi: enable tessellation shaders

[Karol Herbst]

in case v3 doesn't get into mesa, could you extract the
src/mesa/state_tracker/st_glsl_to_nir.cpp change into a seperate patch
and just push that one? I kind of needs this as well and have a patch
doing exactly this in my repository as well.

A patch with only this would be Reviewed-by: Karol Herbst 

On Wed, Jan 3, 2018 at 6:04 AM, Timothy Arceri  wrote:
> Reviewed-by: Nicolai Hähnle 
> ---
>  src/gallium/drivers/radeonsi/si_shader_nir.c | 2 ++
>  src/mesa/state_tracker/st_glsl_to_nir.cpp| 4 +++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
> b/src/gallium/drivers/radeonsi/si_shader_nir.c
> index f96bf7c2d2..5ac020d9fc 100644
> --- a/src/gallium/drivers/radeonsi/si_shader_nir.c
> +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
> @@ -157,6 +157,8 @@ void si_nir_scan_shader(const struct nir_shader *nir,
>
> assert(nir->info.stage == MESA_SHADER_VERTEX ||
>nir->info.stage == MESA_SHADER_GEOMETRY ||
> +  nir->info.stage == MESA_SHADER_TESS_CTRL ||
> +  nir->info.stage == MESA_SHADER_TESS_EVAL ||
>nir->info.stage == MESA_SHADER_FRAGMENT);
>
> info->processor = pipe_shader_type_from_mesa(nir->info.stage);
> diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
> b/src/mesa/state_tracker/st_glsl_to_nir.cpp
> index 276450a64a..5683df 100644
> --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
> @@ -675,7 +675,9 @@ st_finalize_nir(struct st_context *st, struct gl_program 
> *prog,
>>num_outputs,
>nir->info.stage);
>st_nir_fixup_varying_slots(st, >outputs);
> -   } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
> +   } else if (nir->info.stage == MESA_SHADER_GEOMETRY ||
> +  nir->info.stage == MESA_SHADER_TESS_CTRL ||
> +  nir->info.stage == MESA_SHADER_TESS_EVAL) {
>sort_varyings(>inputs);
>st_nir_assign_var_locations(>inputs,
>>num_inputs,
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH] swr/rast: fix build break for llvm-6

[Laurent Carlier]

Le mardi 2 janvier 2018, 17:57:03 CET Tim Rowley a écrit :
> LLVM api change.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104381

Tested-by: Laurent Carlier 

> ---
>  src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
> b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp index
> 3f0772c942..59672bb545 100644
> --- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
> +++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
> @@ -498,7 +498,11 @@ std::unique_ptr
> JitCache::getObject(const llvm::Module* M) break;
>  }
> 
> +#if LLVM_VERSION_MAJOR < 6
>  pBuf =
> llvm::MemoryBuffer::getNewUninitMemBuffer(size_t(header.GetBufferSize()));
> +#else
> +pBuf =
> llvm::WritableMemoryBuffer::getNewUninitMemBuffer(size_t(header.GetBufferSi
> ze())); +#endif
>  if (!fread(const_cast(pBuf->getBufferStart()),
> header.GetBufferSize(), 1, fpIn)) {
>  pBuf = nullptr;


-- 
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http://www.archlinux.org

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[Mesa-dev] [Bug 104214] Dota crashes when switching from game to desktop

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=104214

--- Comment #13 from Cyril  ---
The game start with the patch on top of mesa-17.3.1.

Also tried the Steam overlay (Shift+tab) and switching desktop while in game,
had no crash so it seems good.

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[Mesa-dev] [PATCH][RFC] i965: allocate a SGVS element when VertexID or InstanceID are read in gen9+

[Iago Toral Quiroga]

Although in theory this should not be necessary it seems that doing this
fixes a spurious low rate failure of ~1% in a CTS test that seems to happen
in some gen9+ platforms only.

Fixes flakyness in:
KHR-GL45.vertex_attrib_64bit.limits_test

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104335
---

I am not sure why this fixes the spurious fails, but it clearly does, at least 
for
me. I have not seen any workarounds related to this in the PRMs so maybe
this is just papering over some other problem in the end. It would be great if
someone else could test this and verify that it fixes the spurious fails for 
them
as well and I'd also appreciate any thoughts on what could be causing this 
problem
and why this seems to fix it. There is more detail in the bug report.

 src/mesa/drivers/dri/i965/genX_state_upload.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 50ac5bc59f..523e9688a6 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -494,12 +494,25 @@ genX(emit_vertices)(struct brw_context *brw)
 * values.  Additionally if there is an edge flag element then the SGVS
 * can't be inserted past that so we need a dummy element to ensure that
 * the edge flag is the last one.
+*
+* In gen9+, the CTS test KHR-GL45.vertex_attrib_64bit.limits_test fails
+* with a fail rate of ~1% for the cases where it reads gl_InstanceID but no
+* SGVS element is programmed. Programming the SGVS element in this case
+* seems to make the problem go away.
 */
+#if GEN_GEN >= 9
+   const bool needs_sgvs_element = (vs_prog_data->uses_basevertex ||
+vs_prog_data->uses_baseinstance ||
+vs_prog_data->uses_instanceid ||
+vs_prog_data->uses_vertexid);
+#else
const bool needs_sgvs_element = (vs_prog_data->uses_basevertex ||
 vs_prog_data->uses_baseinstance ||
 ((vs_prog_data->uses_instanceid ||
   vs_prog_data->uses_vertexid)
  && uses_edge_flag));
+#endif
+
 #else
const bool needs_sgvs_element = (vs_prog_data->uses_basevertex ||
 vs_prog_data->uses_baseinstance ||
-- 
2.11.0

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[Mesa-dev] [PATCH 02/14] vc4, vc5: add ETIME fallback define

[Greg V]

FreeBSD only has ETIMEDOUT, not ETIME
---
 src/gallium/drivers/vc4/vc4_bufmgr.c | 4 
 src/gallium/drivers/vc5/vc5_bufmgr.c | 4 
 2 files changed, 8 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_bufmgr.c 
b/src/gallium/drivers/vc4/vc4_bufmgr.c
index 274c4c3120..cbc1e1ae1b 100644
--- a/src/gallium/drivers/vc4/vc4_bufmgr.c
+++ b/src/gallium/drivers/vc4/vc4_bufmgr.c
@@ -35,6 +35,10 @@
 #include "vc4_context.h"
 #include "vc4_screen.h"
 
+#ifndef ETIME
+#define ETIME ETIMEDOUT
+#endif
+
 #ifdef HAVE_VALGRIND
 #include 
 #include 
diff --git a/src/gallium/drivers/vc5/vc5_bufmgr.c 
b/src/gallium/drivers/vc5/vc5_bufmgr.c
index c6c06dcfda..b676373689 100644
--- a/src/gallium/drivers/vc5/vc5_bufmgr.c
+++ b/src/gallium/drivers/vc5/vc5_bufmgr.c
@@ -35,6 +35,10 @@
 #include "vc5_context.h"
 #include "vc5_screen.h"
 
+#ifndef ETIME
+#define ETIME ETIMEDOUT
+#endif
+
 #ifdef HAVE_VALGRIND
 #include 
 #include 
-- 
2.15.1

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[Mesa-dev] [PATCH 12/14] swr: build on FreeBSD/DragonFlyBSD

[Greg V]

(Needs CPU topology detection to actually work)
---
 src/gallium/drivers/swr/rasterizer/common/os.h  | 3 ++-
 src/gallium/drivers/swr/rasterizer/core/threads.cpp | 4 ++--
 src/gallium/drivers/swr/swr_fence.cpp   | 2 ++
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h 
b/src/gallium/drivers/swr/rasterizer/common/os.h
index 358cb33b6e..307308b737 100644
--- a/src/gallium/drivers/swr/rasterizer/common/os.h
+++ b/src/gallium/drivers/swr/rasterizer/common/os.h
@@ -89,7 +89,8 @@ static inline void AlignedFree(void* p)
 #define _mm_popcount_sizeT _mm_popcnt_u32
 #endif
 
-#elif defined(__APPLE__) || defined(FORCE_LINUX) || defined(__linux__) || 
defined(__gnu_linux__)
+#elif defined(FORCE_LINUX) || defined(__linux__) || defined(__gnu_linux__) || \
+   defined(__APPLE__) || defined(__FreeBSD__) || defined(__DragonFly__)
 
 #define SWR_API
 #define SWR_VISIBLE __attribute__((visibility("default")))
diff --git a/src/gallium/drivers/swr/rasterizer/core/threads.cpp 
b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
index d684ffe727..1c7ffcd0cd 100644
--- a/src/gallium/drivers/swr/rasterizer/core/threads.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
@@ -30,7 +30,7 @@
 #include 
 #include 
 
-#if defined(__linux__) || defined(__gnu_linux__) || defined(__APPLE__)
+#if defined(__linux__) || defined(__gnu_linux__) || defined(__APPLE__) || 
defined(__FreeBSD__) || defined(__DragonFly__)
 #include 
 #include 
 #include 
@@ -217,7 +217,7 @@ void CalculateProcessorTopology(CPUNumaNodes& out_nodes, 
uint32_t& out_numThread
 }
 }
 
-#elif defined(__APPLE__)
+#elif defined(__APPLE__) || defined(__FreeBSD__) || defined(__DragonFly__)
 
 #else
 
diff --git a/src/gallium/drivers/swr/swr_fence.cpp 
b/src/gallium/drivers/swr/swr_fence.cpp
index 3005eb9aaa..39024baef9 100644
--- a/src/gallium/drivers/swr/swr_fence.cpp
+++ b/src/gallium/drivers/swr/swr_fence.cpp
@@ -31,6 +31,8 @@
 
 #if defined(PIPE_CC_MSVC) // portable thread yield
#define sched_yield SwitchToThread
+#elif defined(__FreeBSD__) || defined(__DragonFly__)
+   #include 
 #endif
 
 /*
-- 
2.15.1

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[Mesa-dev] [PATCH 06/14] anv: remove unused Linux-specific include

[Greg V]

---
 src/intel/vulkan/anv_queue.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index b1662c1720..5da652df68 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -27,7 +27,6 @@
 
 #include 
 #include 
-#include 
 
 #include "anv_private.h"
 #include "vk_util.h"
-- 
2.15.1

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[Mesa-dev] [PATCH 14/14] meson: glsl: add missing nir header dependency

[Greg V]

---
 src/compiler/glsl/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/glsl/meson.build b/src/compiler/glsl/meson.build
index 6aaa9bab05..9e7589c325 100644
--- a/src/compiler/glsl/meson.build
+++ b/src/compiler/glsl/meson.build
@@ -200,7 +200,7 @@ files_libglsl_standalone = files(
 libglsl = static_library(
   'glsl',
   [files_libglsl, glsl_parser, glsl_lexer_cpp, ir_expression_operation_h,
-   ir_expression_operation_strings_h, ir_expression_operation_constant_h],
+   ir_expression_operation_strings_h, ir_expression_operation_constant_h, 
nir_opcodes_h],
   c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
   cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
   link_with : [libnir, libglcpp],
-- 
2.15.1

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[Mesa-dev] [PATCH 10/14] meson: handle LLVM 'x.x.xgit-revision' versions

[Greg V]

When LLVM is built inside of a git repo (even way below, e.g. /usr/ports/.git
exists, and LLVM is built in /usr/ports/devel/llvm50/work), its version
becomes something like 5.0.0git-f8ab206b2176.

Don't blow up on these versions.
---
 meson.build | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/meson.build b/meson.build
index 23faad0a71..0e8e695965 100644
--- a/meson.build
+++ b/meson.build
@@ -994,9 +994,12 @@ if with_llvm
   _llvm_version = dep_llvm.version().split('.')
   # Development versions of LLVM have an 'svn' suffix, we don't want that for
   # our version checks.
+  # Also LLVM can end up with a 'git-$revision' suffix if built inside a git 
repo.
   _llvm_patch = _llvm_version[2]
   if _llvm_patch.endswith('svn')
 _llvm_patch = _llvm_patch.split('s')[0]
+  elif _llvm_patch.contains('git')
+_llvm_patch = _llvm_patch.split('g')[0]
   endif
   pre_args += [
 '-DHAVE_LLVM=0x0@0@@1@@2@'.format(_llvm_version[0], _llvm_version[1], 
_llvm_patch),
-- 
2.15.1

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[Mesa-dev] [PATCH 00/14] BSD portability (Meson, ANV, RADV, VC4/5, SWR)

[Greg V]

Hello everyone and happy new year! :)

This set of patches makes the Meson build work on FreeBSD, including 
RADV, ANV, wayland-egl, VAAPI, VDPAU.

I also managed to get SWR working, but I haven't included the CPU 
topology detection code in here. CPU topology is exposed as XML on 
FreeBSD, so my implementation uses TinyXML2, which is a new dependency.
And I couldn't even figure out how to link to it with all the libtool
stuff. Had to test it with LD_PRELOAD :D
This will be much easier to do with Meson.

Greg V (14):
  util: fix ElfW macro
  vc4, vc5: add ETIME fallback define
  radv: add ETIME fallback define
  anv: add ETIME fallback define
  anv: use POSIX sysconf to get memory info on non-glibc systems
  anv: remove unused Linux-specific include
  anv: FreeBSD support in the allocator
  meson: fix BSD build
  meson: do not redeclare pkg-config dependencies (yet)
  meson: handle LLVM 'x.x.xgit-revision' versions
  meson: fix missing dependencies
  swr: build on FreeBSD/DragonFlyBSD
  swr: fix clang 5 null cast warning
  meson: glsl: add missing nir header dependency

 meson.build| 74 --
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c  |  3 +
 src/compiler/glsl/meson.build  |  2 +-
 src/gallium/drivers/radeonsi/meson.build   |  2 +-
 src/gallium/drivers/swr/rasterizer/common/os.h |  3 +-
 .../drivers/swr/rasterizer/core/threads.cpp|  4 +-
 .../swr/rasterizer/memory/TilingFunctions.h|  6 +-
 src/gallium/drivers/swr/swr_fence.cpp  |  2 +
 src/gallium/drivers/vc4/vc4_bufmgr.c   |  4 ++
 src/gallium/drivers/vc5/vc5_bufmgr.c   |  4 ++
 src/intel/vulkan/anv_allocator.c   | 56 
 src/intel/vulkan/anv_device.c  | 11 
 src/intel/vulkan/anv_gem.c |  4 ++
 src/intel/vulkan/anv_queue.c   |  5 +-
 src/mesa/meson.build   |  1 +
 src/util/build_id.c|  6 +-
 16 files changed, 144 insertions(+), 43 deletions(-)

-- 
2.15.1

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[Mesa-dev] [PATCH 05/14] anv: use POSIX sysconf to get memory info on non-glibc systems

[Greg V]

---
 src/intel/vulkan/anv_device.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 6f77d33f93..2d3062d103 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -25,7 +25,9 @@
 #include 
 #include 
 #include 
+#ifdef __GLIBC__
 #include 
+#endif
 #include 
 #include 
 #include 
@@ -79,10 +81,15 @@ anv_compute_heap_size(int fd, uint64_t *heap_size)
}
 
/* Query the total ram from the system */
+#ifdef __GLIBC__
struct sysinfo info;
sysinfo();
 
uint64_t total_ram = (uint64_t)info.totalram * (uint64_t)info.mem_unit;
+#else
+   uint64_t total_ram = sysconf(_SC_PHYS_PAGES) * sysconf(_SC_PAGE_SIZE);
+#endif
+
 
/* We don't want to burn too much ram with the GPU.  If the user has 4GiB
 * or less, we use at most half.  If they have more than 4GiB, we use 3/4.
-- 
2.15.1

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[Mesa-dev] bad object in mesa git repo

[Kevin Gallagher]

Hi,

Upon cloning the main mesa repository, git with fsckObjects enabled
(receive, transfer, fetch) reports an error:

error: object c2908f1b53c841bfa450b066c6fa1ee78c2fdb85:
missingSpaceBeforeDate: invalid author/committer line - missing
space before date
ba

This is true of anongit.freedesktop.org as well as github.com/mesa3d/mesa.

Someone mentioned this object in a previous thread:
https://lists.freedesktop.org/archives/mesa-dev/2016-February/106268.html
but it seems not to have been addressed. This should be straightforward
for a maintainer to fix with some investigation, git-fsck magic and
force push rights.

best,
Kevin
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[Mesa-dev] [PATCH 07/14] anv: FreeBSD support in the allocator

[Greg V]

Use umtx for futex, and SHM_ANON for memfd.

Also use temp files as memfd fallback for other OSes.

Obtained from: FreeBSD ports
---
 src/intel/vulkan/anv_allocator.c | 56 
 1 file changed, 56 insertions(+)

diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 33bd3c68c5..c31d3d17d2 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -25,7 +25,13 @@
 #include 
 #include 
 #include 
+#ifdef __linux__
 #include 
+#elif __FreeBSD__
+#include 
+#include 
+#include 
+#endif
 #include 
 
 #include "anv_private.h"
@@ -50,6 +56,34 @@
 #define VG_NOACCESS_WRITE(__ptr, __val) (*(__ptr) = (__val))
 #endif
 
+#ifdef __FreeBSD__
+static inline int
+sys_futex(void *addr, int op, int32_t val)
+{
+   return _umtx_op(addr, op, (uint32_t)val, NULL, NULL) == -1 ? errno : 0;
+}
+
+static inline int
+futex_wake(uint32_t *addr, int count)
+{
+   return sys_futex(addr, UMTX_OP_WAKE, count);
+}
+
+static inline int
+futex_wait(uint32_t *addr, int32_t value, int32_t _)
+{
+   return sys_futex(addr, UMTX_OP_WAIT_UINT, value);
+}
+#endif
+
+#ifndef MAP_POPULATE
+#define MAP_POPULATE 0
+#endif
+
+#ifndef MFD_CLOEXEC
+#define MFD_CLOEXEC O_CLOEXEC
+#endif
+
 /* Design goals:
  *
  *  - Lock free (except when resizing underlying bos)
@@ -113,7 +147,29 @@ struct anv_mmap_cleanup {
 static inline int
 memfd_create(const char *name, unsigned int flags)
 {
+#if defined(__linux__)
return syscall(SYS_memfd_create, name, flags);
+#elif defined(__FreeBSD__)
+   return shm_open(SHM_ANON, flags | O_RDWR | O_CREAT, 0600);
+#else /* DragonFly, NetBSD, OpenBSD, Solaris */
+   char template[] = "/tmp/shmfd-XX";
+#ifdef HAVE_MKOSTEMP
+   int fd = mkostemp(template, flags);
+#else
+   int fd = mkstemp(template);
+   if (flags & O_CLOEXEC) {
+ int flags = fcntl(fd, F_GETFD);
+ if (flags != -1) {
+   flags |= FD_CLOEXEC;
+   (void) fcntl(fd, F_SETFD, );
+ }
+   }
+#endif /* HAVE_MKOSTEMP */
+   if (fd >= 0)
+ unlink(template);
+
+   return fd;
+#endif /* __linux__ */
 }
 #endif
 
-- 
2.15.1

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[Mesa-dev] [PATCH 09/14] meson: do not redeclare pkg-config dependencies (yet)

[Greg V]

get_pkgconfig_variable('cflags') always returns an empty list. This only
worked on Linux because the libraries were in the standard include path.
---
 meson.build | 28 
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/meson.build b/meson.build
index af62baf437..23faad0a71 100644
--- a/meson.build
+++ b/meson.build
@@ -395,9 +395,10 @@ else
   with_gallium_vdpau = false
 endif
 if with_gallium_vdpau
-  dep_vdpau = declare_dependency(
-compile_args : dep_vdpau.get_pkgconfig_variable('cflags').split()
-  )
+  # XXX: https://github.com/mesonbuild/meson/issues/2725
+  # dep_vdpau = declare_dependency(
+  #   compile_args : dep_vdpau.get_pkgconfig_variable('cflags').split()
+  # )
 endif
 
 if with_gallium_vdpau
@@ -436,9 +437,10 @@ else
   with_gallium_xvmc = false
 endif
 if with_gallium_xvmc
-  dep_xvmc = declare_dependency(
-compile_args : dep_xvmc.get_pkgconfig_variable('cflags').split()
-  )
+  # XXX: https://github.com/mesonbuild/meson/issues/2725
+  # dep_xvmc = declare_dependency(
+  #   compile_args : dep_xvmc.get_pkgconfig_variable('cflags').split()
+  # )
 endif
 
 xvmc_drivers_path = get_option('xvmc-libs-path')
@@ -499,9 +501,10 @@ if with_gallium_omx
   endif
 endif
 if with_gallium_omx
-  dep_omx = declare_dependency(
-compile_args : dep_omx.get_pkgconfig_variable('cflags').split()
-  )
+  # XXX: https://github.com/mesonbuild/meson/issues/2725
+  # dep_omx = declare_dependency(
+  #   compile_args : dep_omx.get_pkgconfig_variable('cflags').split()
+  # )
 endif
 
 dep_va = []
@@ -532,9 +535,10 @@ else
   with_gallium_va = false
 endif
 if with_gallium_va
-  dep_va = declare_dependency(
-compile_args : dep_va.get_pkgconfig_variable('cflags').split()
-  )
+  # XXX: https://github.com/mesonbuild/meson/issues/2725
+  # dep_va = declare_dependency(
+  #   compile_args : dep_va.get_pkgconfig_variable('cflags').split()
+  # )
 endif
 
 va_drivers_path = get_option('va-libs-path')
-- 
2.15.1

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[Mesa-dev] [PATCH 03/14] radv: add ETIME fallback define

[Greg V]

FreeBSD only has ETIMEDOUT, not ETIME
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 4578a9b548..84ceee2f5d 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -33,6 +33,9 @@
 #include "radv_amdgpu_bo.h"
 #include "sid.h"
 
+#ifndef ETIME
+#define ETIME ETIMEDOUT
+#endif
 
 enum {
VIRTUAL_BUFFER_HASH_TABLE_SIZE = 1024
-- 
2.15.1

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[Mesa-dev] [PATCH 01/14] util: fix ElfW macro

[Greg V]

Elf64_Nhdr exists, Elf_Nhdr does not.

Obtained from: FreeBSD ports
---
 src/util/build_id.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/util/build_id.c b/src/util/build_id.c
index 536c74360e..cb35e90b09 100644
--- a/src/util/build_id.c
+++ b/src/util/build_id.c
@@ -34,7 +34,11 @@
 #endif
 
 #ifndef ElfW
-#define ElfW(type) Elf_##type
+#ifdef __LP64__
+#define ElfW(type) Elf64_##type
+#else
+#define ElfW(type) Elf32_##type
+#endif
 #endif
 
 #define ALIGN(val, align)  (((val) + (align) - 1) & ~((align) - 1))
-- 
2.15.1

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[Mesa-dev] [PATCH 13/14] swr: fix clang 5 null cast warning

[Greg V]

---
 src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h 
b/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
index 6c801c7ff6..abb0c53ec4 100644
--- a/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
+++ b/src/gallium/drivers/swr/rasterizer/memory/TilingFunctions.h
@@ -624,7 +624,7 @@ uint32_t TileSwizzle2D(uint32_t xOffsetBytes, uint32_t 
yOffsetRows, const SWR_SU
 case SWR_TILE_MODE_WMAJOR: return 
ComputeTileSwizzle2D >(xOffsetBytes, 
yOffsetRows, pState);
 default: SWR_INVALID("Unsupported tiling mode");
 }
-return (uint32_t) NULL;
+return 0;
 }
 
 //
@@ -644,7 +644,7 @@ uint32_t TileSwizzle3D(uint32_t xOffsetBytes, uint32_t 
yOffsetRows, uint32_t zOf
 case SWR_TILE_MODE_YMAJOR: return 
ComputeTileSwizzle3D >(xOffsetBytes, 
yOffsetRows, zOffsetSlices, pState);
 default: SWR_INVALID("Unsupported tiling mode");
 }
-return (uint32_t) NULL;
+return 0;
 }
 
 template
@@ -677,7 +677,7 @@ uint32_t ComputeSurfaceOffset(uint32_t x, uint32_t y, 
uint32_t z, uint32_t array
 default: SWR_INVALID("Unsupported format");
 }
 
-return (uint32_t) NULL;
+return 0;
 }
 
 typedef void*(*PFN_COMPUTESURFADDR)(uint32_t, uint32_t, uint32_t, uint32_t, 
uint32_t, uint32_t, const SWR_SURFACE_STATE*);
-- 
2.15.1

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[Mesa-dev] [PATCH 08/14] meson: fix BSD build

[Greg V]

---
 meson.build | 43 ++-
 1 file changed, 22 insertions(+), 21 deletions(-)

diff --git a/meson.build b/meson.build
index d9f7ea9b2c..af62baf437 100644
--- a/meson.build
+++ b/meson.build
@@ -199,12 +199,13 @@ if with_dri_i915 or with_gallium_i915
   dep_libdrm_intel = dependency('libdrm_intel', version : '>= 2.4.75')
 endif
 
+is_like_linux = host_machine.system() == 'linux' or 
host_machine.system().contains('bsd') # FIXME: illumos?
+
 if host_machine.system() == 'darwin'
   with_dri_platform = 'apple'
 elif ['windows', 'cygwin'].contains(host_machine.system())
   with_dri_platform = 'windows'
-elif host_machine.system() == 'linux'
-  # FIXME: This should include BSD and possibly other systems
+elif is_like_linux
   with_dri_platform = 'drm'
 else
   # FIXME: haiku doesn't use dri, and xlib doesn't use dri, probably should
@@ -222,7 +223,7 @@ with_platform_surfaceless = false
 egl_native_platform = ''
 _platforms = get_option('platforms')
 if _platforms == 'auto'
-  if ['linux'].contains(host_machine.system())
+  if is_like_linux
 _platforms = 'x11,wayland,drm,surfaceless'
   else
 error('Unknown OS, no platforms enabled. Patches gladly accepted to fix 
this.')
@@ -265,9 +266,9 @@ endif
 
 with_gbm = get_option('gbm')
 if with_gbm == 'auto' and with_dri  # TODO: or gallium
-  with_gbm = host_machine.system() == 'linux'
+  with_gbm = is_like_linux
 elif with_gbm == 'true'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 error('GBM only supports unix-like platforms')
   endif
   with_gbm = true
@@ -344,7 +345,7 @@ endif
 with_dri2 = (with_dri or with_any_vk) and with_dri_platform == 'drm'
 with_dri3 = get_option('dri3')
 if with_dri3 == 'auto'
-  if host_machine.system() == 'linux' and with_dri2
+  if is_like_linux and with_dri2
 with_dri3 = true
   else
 with_dri3 = false
@@ -367,7 +368,7 @@ endif
 dep_vdpau = []
 _vdpau = get_option('gallium-vdpau')
 if _vdpau == 'auto'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 with_gallium_vdpau = false
   elif not with_platform_x11
 with_gallium_vdpau = false
@@ -379,7 +380,7 @@ if _vdpau == 'auto'
 with_gallium_vdpau = dep_vdpau.found()
   endif
 elif _vdpau == 'true'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 error('VDPAU state tracker can only be build on unix-like OSes.')
   elif not with_platform_x11
 error('VDPAU state tracker requires X11 support.')
@@ -410,7 +411,7 @@ endif
 dep_xvmc = []
 _xvmc = get_option('gallium-xvmc')
 if _xvmc == 'auto'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 with_gallium_xvmc = false
   elif not with_platform_x11
 with_gallium_xvmc = false
@@ -421,7 +422,7 @@ if _xvmc == 'auto'
 with_gallium_xvmc = dep_xvmc.found()
   endif
 elif _xvmc == 'true'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 error('XVMC state tracker can only be build on unix-like OSes.')
   elif not with_platform_x11
 error('XVMC state tracker requires X11 support.')
@@ -448,7 +449,7 @@ endif
 dep_omx = []
 _omx = get_option('gallium-omx')
 if _omx == 'auto'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 with_gallium_omx = false
   elif not with_platform_x11
 with_gallium_omx = false
@@ -459,7 +460,7 @@ if _omx == 'auto'
 with_gallium_omx = dep_omx.found()
   endif
 elif _omx == 'true'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 error('OMX state tracker can only be built on unix-like OSes.')
   elif not (with_platform_x11 or with_platform_drm)
 error('OMX state tracker requires X11 or drm platform support.')
@@ -506,7 +507,7 @@ endif
 dep_va = []
 _va = get_option('gallium-va')
 if _va == 'auto'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 with_gallium_va = false
   elif not with_platform_x11
 with_gallium_va = false
@@ -517,7 +518,7 @@ if _va == 'auto'
 with_gallium_va = dep_va.found()
   endif
 elif _va == 'true'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 error('VA state tracker can only be built on unix-like OSes.')
   elif not (with_platform_x11 or with_platform_drm)
 error('VA state tracker requires X11 or drm or wayland platform support.')
@@ -543,7 +544,7 @@ endif
 
 _xa = get_option('gallium-xa')
 if _xa == 'auto'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 with_gallium_xa = false
   elif not (with_gallium_nouveau or with_gallium_freedreno or with_gallium_i915
 or with_gallium_svga)
@@ -552,7 +553,7 @@ if _xa == 'auto'
 with_gallium_xa = true
   endif
 elif _xa == 'true'
-  if not ['linux', 'bsd'].contains(host_machine.system())
+  if not is_like_linux
 error('XA state tracker can only be built on unix-like 

[Mesa-dev] [PATCH 04/14] anv: add ETIME fallback define

[Greg V]

FreeBSD only has ETIMEDOUT, not ETIME
---
 src/intel/vulkan/anv_device.c | 4 
 src/intel/vulkan/anv_gem.c| 4 
 src/intel/vulkan/anv_queue.c  | 4 
 3 files changed, 12 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 680f5a752d..6f77d33f93 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -40,6 +40,10 @@
 
 #include "genxml/gen7_pack.h"
 
+#ifndef ETIME
+#define ETIME ETIMEDOUT
+#endif
+
 static void
 compiler_debug_log(void *data, const char *fmt, ...)
 { }
diff --git a/src/intel/vulkan/anv_gem.c b/src/intel/vulkan/anv_gem.c
index 34c0989108..4a885617ab 100644
--- a/src/intel/vulkan/anv_gem.c
+++ b/src/intel/vulkan/anv_gem.c
@@ -31,6 +31,10 @@
 
 #include "anv_private.h"
 
+#ifndef ETIME
+#define ETIME ETIMEDOUT
+#endif
+
 static int
 anv_ioctl(int fd, unsigned long request, void *arg)
 {
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index c6b2e01c62..b1662c1720 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -34,6 +34,10 @@
 
 #include "genxml/gen7_pack.h"
 
+#ifndef ETIME
+#define ETIME ETIMEDOUT
+#endif
+
 VkResult
 anv_device_execbuf(struct anv_device *device,
struct drm_i915_gem_execbuffer2 *execbuf,
-- 
2.15.1

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[Mesa-dev] [PATCH 11/14] meson: fix missing dependencies

[Greg V]

---
 src/gallium/drivers/radeonsi/meson.build | 2 +-
 src/mesa/meson.build | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/meson.build 
b/src/gallium/drivers/radeonsi/meson.build
index 58132bf072..8a7045de0d 100644
--- a/src/gallium/drivers/radeonsi/meson.build
+++ b/src/gallium/drivers/radeonsi/meson.build
@@ -77,7 +77,7 @@ libradeonsi = static_library(
   ],
   c_args : [c_vis_args],
   cpp_args : [cpp_vis_args],
-  dependencies : dep_llvm,
+  dependencies : [dep_llvm, dep_libdrm],
 )
 
 driver_radeonsi = declare_dependency(
diff --git a/src/mesa/meson.build b/src/mesa/meson.build
index ab6bc27312..74b8d97231 100644
--- a/src/mesa/meson.build
+++ b/src/mesa/meson.build
@@ -721,6 +721,7 @@ libmesa_gallium = static_library(
   cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
   include_directories : [inc_common, include_directories('main')],
   link_with : [libglsl, libmesa_sse41],
+  dependencies : [dep_vdpau],
   build_by_default : false,
 )
 
-- 
2.15.1

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