[Mesa-dev] [Bug 106881] glUniform4fv does not work

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106881

Tapani Pälli  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEEDINFO|RESOLVED

--- Comment #6 from Tapani Pälli  ---
by commit e266b320590ebbeadf7c98b0b493d89886534ccb

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[Mesa-dev] [Bug 106881] glUniform4fv does not work

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106881

--- Comment #5 from Tapani Pälli  ---
(In reply to xinghua from comment #4)
> (In reply to Tapani Pälli from comment #3)
> > IMO this looks like a shader cache issue that got fixed by following commit.
> > Please pull the latest Mesa and test again.
> > 
> > --- 8< ---
> > commit e266b320590ebbeadf7c98b0b493d89886534ccb
> > Author: Jordan Justen 
> > Date:   Wed Jun 6 01:57:15 2018 -0700
> > 
> > mesa/program_binary: add implicit UseProgram after successful
> > ProgramBinary
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106810
> > Fixes: b4c37ce2140 "i965: Add ARB_get_program_binary support using
> > nir_serialization"
> > Ref: 3fe8d04a6d6 "mesa: don't always set _NEW_PROGRAM when linking"
> > Ref: c505d6d8522 "mesa: use gl_program for CurrentProgram rather than
> > gl_shader_program"
> > Signed-off-by: Jordan Justen 
> > Reviewed-by: Plamena Manolova 
> > Reviewed-by: Timothy Arceri 
> 
> Hi, Tapani, Thank you for your reply. I had tested this case again, the
> patch could resolve this issue.
> Could you give our more information about the root-cause in mesa, thank you.

Chrome browser implements a shader program cache using ARB_get_program_binary,
we had a bug in program binary code. Loading new binary was not binding the
shaders of the binary in to use (so old ones were still used). This is now
fixed.

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[Mesa-dev] [Bug 106881] glUniform4fv does not work

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106881

xinghua  changed:

   What|Removed |Added

 CC||yang...@intel.com,
   ||yunchao...@intel.com

--- Comment #4 from xinghua  ---
(In reply to Tapani Pälli from comment #3)
> IMO this looks like a shader cache issue that got fixed by following commit.
> Please pull the latest Mesa and test again.
> 
> --- 8< ---
> commit e266b320590ebbeadf7c98b0b493d89886534ccb
> Author: Jordan Justen 
> Date:   Wed Jun 6 01:57:15 2018 -0700
> 
> mesa/program_binary: add implicit UseProgram after successful
> ProgramBinary
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106810
> Fixes: b4c37ce2140 "i965: Add ARB_get_program_binary support using
> nir_serialization"
> Ref: 3fe8d04a6d6 "mesa: don't always set _NEW_PROGRAM when linking"
> Ref: c505d6d8522 "mesa: use gl_program for CurrentProgram rather than
> gl_shader_program"
> Signed-off-by: Jordan Justen 
> Reviewed-by: Plamena Manolova 
> Reviewed-by: Timothy Arceri 

Hi, Tapani, Thank you for your reply. I had tested this case again, the patch
could resolve this issue.
Could you give our more information about the root-cause in mesa, thank you.

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Re: [Mesa-dev] [PATCH 2/3] i965: Split merge_inputs and clear_buffers.

[Mathias Fröhlich]

Hi Chris,

Thanks for looking into that!

On Saturday, 2 June 2018 10:02:36 CEST Chris Wilson wrote:
> Quoting mathias.froehl...@gmx.net (2018-05-17 07:38:27)
> > From: Mathias Fröhlich 
> > 
> > The merge_inputs function handles that part that changes when the
> > inputs change. The clear_buffers function triggers when we may need
> > a new upload. Thus the merge_inputs can be limited to be once
> > per brw_draw_prims.
> > 
> > Signed-off-by: Mathias Fröhlich 
> > ---
> >  src/mesa/drivers/dri/i965/brw_draw.c | 30 ++
> >  1 file changed, 22 insertions(+), 8 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
> > b/src/mesa/drivers/dri/i965/brw_draw.c
> > index ae3b7be2dd..2a7562a684 100644
> > --- a/src/mesa/drivers/dri/i965/brw_draw.c
> > +++ b/src/mesa/drivers/dri/i965/brw_draw.c
> > @@ -278,21 +278,34 @@ brw_emit_prim(struct brw_context *brw,
> >  
> >  
> >  static void
> > -brw_merge_inputs(struct brw_context *brw)
> > +brw_clear_buffers(struct brw_context *brw)
> >  {
> > -   const struct gen_device_info *devinfo = &brw->screen->devinfo;
> > -   const struct gl_context *ctx = &brw->ctx;
> > -   GLuint i;
> > -
> > -   for (i = 0; i < brw->vb.nr_buffers; i++) {
> > +   for (unsigned i = 0; i < brw->vb.nr_buffers; ++i) {
> >brw_bo_unreference(brw->vb.buffers[i].bo);
> >brw->vb.buffers[i].bo = NULL;
> > }
> > brw->vb.nr_buffers = 0;
> >  
> > +   for (unsigned i = 0; i < brw->vb.nr_enabled; ++i) {
> > +  brw->vb.enabled[i]->buffer = -1;
> > +   }
> 
> Hmm, can we have an enabled buffer that is not in the set of
> brw->vb.buffers[]?

No, that cannot. The brw_vertex_element::buffer variable is only an integer
index exactly into the brw_vertex_buffer array at vb.buffers[]. So, I would say
by the semantics of the brw_vertex_element::buffer value it cannot refer to
anywhere else than to vb.buffers[].
... I am not sure I got your question right?

best

Mathias


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Re: [Mesa-dev] [PATCH 1/3] i965: Move down genX_upload_sbe in profiles.

[Mathias Fröhlich]

Hi Chris,

thanks for looking into that!

On Saturday, 2 June 2018 09:58:14 CEST Chris Wilson wrote:
> Quoting mathias.froehl...@gmx.net (2018-05-17 07:38:26)
> > From: Mathias Fröhlich 
> > 
> > Avoid looping over all VARYING_SLOT_MAX urb_setup array
> > entries from genX_upload_sbe. Prepare an array indirection
> > to the active entries of urb_setup already in the compile
> > step. On upload only walk the active arrays.
> > 
> > Signed-off-by: Mathias Fröhlich 
> > ---
> >  src/intel/compiler/brw_compiler.h |  7 +++
> >  src/intel/compiler/brw_fs.cpp | 23 +++
> >  src/intel/compiler/brw_fs.h   |  2 ++
> >  src/intel/compiler/brw_fs_visitor.cpp |  1 +
> >  src/mesa/drivers/dri/i965/genX_state_upload.c |  7 +++
> >  5 files changed, 36 insertions(+), 4 deletions(-)
> > 
> > diff --git a/src/intel/compiler/brw_compiler.h 
> > b/src/intel/compiler/brw_compiler.h
> > index 8b4e6fe2e2..a9df45e00d 100644
> > --- a/src/intel/compiler/brw_compiler.h
> > +++ b/src/intel/compiler/brw_compiler.h
> > @@ -743,6 +743,13 @@ struct brw_wm_prog_data {
> >  * For varying slots that are not used by the FS, the value is -1.
> >  */
> > int urb_setup[VARYING_SLOT_MAX];
> > +   /**
> > +* Cache structure into the urb_setup array above that contains the
> > +* attribute numbers of active varyings out of urb_setup.
> > +* The actual count is stored in urb_setup_attribs_count.
> > +*/
> > +   int urb_setup_attribs[VARYING_SLOT_MAX];
> > +   int urb_setup_attribs_count;
> >  };
> >  
> >  struct brw_push_const_block {
> > diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
> > index b21996c168..6930414067 100644
> > --- a/src/intel/compiler/brw_fs.cpp
> > +++ b/src/intel/compiler/brw_fs.cpp
> > @@ -1507,6 +1507,25 @@ fs_visitor::assign_curb_setup()
> > this->first_non_payload_grf = payload.num_regs + 
> > prog_data->curb_read_length;
> >  }
> >  
> > +/*
> > + * Build up an array of indices into the urb_setup array that
> > + * references the active entries of the urb_setup array.
> > + * Used to accelerate walking the active entries of the urb_setup array
> > + * on each upload.
> > + */
> > +void
> > +brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data)
> > +{
> > +   int index = 0;
> > +   for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
> > +  int input_index = wm_prog_data->urb_setup[attr];
> > +  if (input_index < 0)
> > + continue;
> > +  wm_prog_data->urb_setup_attribs[index++] = attr;
> 
> So far the only consumer of this wants the input_index again.
> Does that change, or is it worth including both to avoid the trawl?

Hmm, I don't know too much about the internal requirements of hardware in this 
regard.
But one property of the current code is that the current code orders the
varying slots in urb_setup[] with ascending attribute index.
So if we collapse the urb_setup[] and urb_setup_index[] arrays into something 
like

struct {
   uint8_t attrib;
   uint8_t index;
}  urb_setup[VARYING_SLOT_MAX;
uint8_t urb_setup_count;

do we need to sort that afterwards by attribute before we can use that
in genX_upload_sbe?

> Is uint8_t (with a STATIC_ASSERT) good enough?
Sure, I was catching up with the next declaration beside to stick
with the 'surrounding coding style'. That's changed here in a v2 version.

We could even reach an even smaller cache footprint by using a single uint64_t 
and
iterate that using u_bit_scan64(). But I received some general headwind lately 
from
someone who did not like these bitmask loops. So I apply the bitmask iteration 
only in
places where the bitmasks really provide a larger improvement than just a 
smaller
cache footprint.
What do you think?

best

Mathias


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[Mesa-dev] [PATCH mesa 7/9] vulkan: Add EXT_acquire_xlib_display [v3]

[Keith Packard]

This extension adds the ability to borrow an X RandR output for
temporary use directly by a Vulkan application. For DRM, we use the
Linux resource leasing mechanism.

v2:
Clean up xlib_lease detection

* Use separate temporary '_xlib_lease' variable to hold the
  option value to avoid changin the type of a variable.

* Use boolean expressions instead of additional if statements
  to compute resulting with_xlib_lease value.

* Simplify addition of VK_USE_PLATFORM_XLIB_XRANDR_KHR to
  vulkan_wsi_args

  Suggested-by: Eric Engestrom 

Move mode list from wsi_display to wsi_display_connector

Fix scope for wsi_display_mode and wsi_display_connector allocs

  Suggested-by: Jason Ekstrand 

v3:
Adopt Jason Ekstrand's coding conventions

Declare variables at first use, eliminate extra whitespace
between types and names. Wrap lines to 80 columns.

Explicitly forbid multiple DRM leases. Making the code support
this looks tricky and will require additional thought.

Use xcb_randr_output_t throughout the internals of the
implementation. Convert at the public API
(wsi_get_randr_output_display).

Clean up check for usable active_crtc (possible when only the
desired output is connected to the crtc).

Suggested-by: Jason Ekstrand 

Signed-off-by: Keith Packard 

fixup for acquire

fixup for RROutput type

Signed-off-by: Keith Packard 

fixup
---
 configure.ac|  32 ++
 meson.build |  11 +
 meson_options.txt   |   7 +
 src/vulkan/Makefile.am  |   5 +
 src/vulkan/wsi/meson.build  |   5 +
 src/vulkan/wsi/wsi_common_display.c | 493 
 src/vulkan/wsi/wsi_common_display.h |  17 +
 7 files changed, 570 insertions(+)

diff --git a/configure.ac b/configure.ac
index 75ee1a7c01c..e01d0399681 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1577,6 +1577,7 @@ AM_CONDITIONAL(HAVE_APPLEDRI, test "x$enable_dri" = xyes 
-a "x$dri_platform" = x
 AM_CONDITIONAL(HAVE_LMSENSORS, test "x$enable_lmsensors" = xyes )
 AM_CONDITIONAL(HAVE_GALLIUM_EXTRA_HUD, test "x$enable_gallium_extra_hud" = 
xyes )
 AM_CONDITIONAL(HAVE_WINDOWSDRI, test "x$enable_dri" = xyes -a "x$dri_platform" 
= xwindows )
+AM_CONDITIONAL(HAVE_XLEASE, test "x$have_xlease" = xyes )
 
 AC_ARG_ENABLE([shared-glapi],
 [AS_HELP_STRING([--enable-shared-glapi],
@@ -1879,12 +1880,43 @@ if test x"$enable_dri3" = xyes; then
 fi
 fi
 
+
+if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; then
+have_xlease=yes
+else
+have_xlease=no
+fi
+
+if test x"$have_xlease" = xyes; then
+randr_modules="x11-xcb xcb-randr"
+PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
+fi
+
 AM_CONDITIONAL(HAVE_PLATFORM_X11, echo "$platforms" | grep -q 'x11')
 AM_CONDITIONAL(HAVE_PLATFORM_WAYLAND, echo "$platforms" | grep -q 'wayland')
 AM_CONDITIONAL(HAVE_PLATFORM_DRM, echo "$platforms" | grep -q 'drm')
 AM_CONDITIONAL(HAVE_PLATFORM_SURFACELESS, echo "$platforms" | grep -q 
'surfaceless')
 AM_CONDITIONAL(HAVE_PLATFORM_ANDROID, echo "$platforms" | grep -q 'android')
 
+AC_ARG_ENABLE(xlib-lease,
+[AS_HELP_STRING([--enable-xlib-lease]
+[enable VK_acquire_xlib_display using X leases])],
+[enable_xlib_lease=$enableval], [enable_xlib_lease=auto])
+case "x$enable_xlib_lease" in
+xyes)
+;;
+xno)
+;;
+*)
+if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; 
then
+enable_xlib_lease=yes
+else
+enable_xlib_lease=no
+fi
+esac
+
+AM_CONDITIONAL(HAVE_XLIB_LEASE, test "x$enable_xlib_lease" = xyes)
+
 dnl
 dnl More DRI setup
 dnl
diff --git a/meson.build b/meson.build
index 160bbfa30ba..cb1b14b6c82 100644
--- a/meson.build
+++ b/meson.build
@@ -248,6 +248,13 @@ if _platforms.length() != 0 and _platforms != ['']
   egl_native_platform = _platforms[0]
 endif
 
+_xlib_lease = get_option('xlib-lease')
+if _xlib_lease == 'auto'
+  with_xlib_lease = with_platform_x11 and with_platform_drm
+else
+  with_xlib_lease = _xlib_lease == 'true'
+endif
+
 with_glx = get_option('glx')
 if with_glx == 'auto'
   if with_dri
@@ -1254,6 +1261,7 @@ dep_xcb_present = null_dep
 dep_xcb_sync = null_dep
 dep_xcb_xfixes = null_dep
 dep_xshmfence = null_dep
+dep_xcb_xrandr = null_dep
 if with_platform_x11
   if with_glx == 'xlib' or with_glx == 'gallium-xlib'
 dep_x11 = dependency('x11')
@@ -1300,6 +1308,9 @@ if with_platform_x11
   with_gallium_omx != 'disabled'))
 dep_xcb_xfixes = dependency('xcb-xfixes')
   endif
+  if with_xlib_lease
+dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.12')
+  endif
 endif
 
 if get_option('gallium-extra-hud')
diff --git a/meson_options.txt b/meson_options.txt
index 28e92509198..fa040c9f4fb 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -304,3 +304,10 @@ option(
   choices : 

[Mesa-dev] [PATCH mesa 5/9] anv: Add EXT_direct_mode_display to anv driver [v2]

[Keith Packard]

Add support for the EXT_direct_mode_display extension. This just
provides the vkReleaseDisplayEXT function.

v2: Add extension to list in alphabetical order

Suggested-by:  Jason Ekstrand 

Signed-off-by: Keith Packard 
---
 src/intel/vulkan/anv_extensions.py |  1 +
 src/intel/vulkan/anv_wsi_display.c | 11 +++
 2 files changed, 12 insertions(+)

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 83c09a46741..d63b994b601 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -109,6 +109,7 @@ EXTENSIONS = [
 Extension('VK_KHR_multiview', 1, True),
 Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_debug_report',  8, True),
+Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_external_memory_dma_buf',   1, True),
 Extension('VK_EXT_global_priority',   1,
   'device->has_context_priority'),
diff --git a/src/intel/vulkan/anv_wsi_display.c 
b/src/intel/vulkan/anv_wsi_display.c
index 877b506b924..8e0f8582863 100644
--- a/src/intel/vulkan/anv_wsi_display.c
+++ b/src/intel/vulkan/anv_wsi_display.c
@@ -127,3 +127,14 @@ anv_CreateDisplayPlaneSurfaceKHR(
 
return wsi_create_display_surface(_instance, alloc, create_info, surface);
 }
+
+VkResult
+anv_ReleaseDisplayEXT(VkPhysicalDevice physical_device,
+   VkDisplayKHR display)
+{
+   ANV_FROM_HANDLE(anv_physical_device, pdevice, physical_device);
+
+   return wsi_release_display(physical_device,
+  &pdevice->wsi_device,
+  display);
+}
-- 
2.17.1

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[Mesa-dev] [PATCH mesa 2/9] anv: Add KHR_display extension to anv [v5]

[Keith Packard]

This adds support for the KHR_display extension to the anv Vulkan
driver. The driver now attempts to open the master DRM node when the
KHR_display extension is requested so that the common winsys code can
perform the necessary operations.

v2: Make sure primary fd is usable

When KHR_display is selected, we try to open the primary node
instead of the render node in case the user wants to use
KHR_display for presentation. However, if we're actually going
to end up using RandR leases, then we don't care if the
resulting fd can't be used for display, but the kernel also
prevents us from using it for drawing when someone else has
master.

v3:
Simplify addition of VK_USE_PLATFORM_DISPLAY_KHR to vulkan_wsi_args

Suggested-by: Eric Engestrom 

v4:
Adapt primary node usage to new wsi_device_init API

v5:
Adopt Jason Ekstrand's coding conventions

Declare variables at first use, eliminate extra whitespace between
types and names. Wrap lines to 80 columns.

Remove spurious MM_PER_PIXEL define

Suggested-by: Jason Ekstrand 

Signed-off-by: Keith Packard 

fixup
---
 src/intel/Makefile.sources |   3 +
 src/intel/Makefile.vulkan.am   |   7 ++
 src/intel/vulkan/anv_device.c  |  21 
 src/intel/vulkan/anv_extensions.py |   1 +
 src/intel/vulkan/anv_extensions_gen.py |   5 +-
 src/intel/vulkan/anv_wsi_display.c | 129 +
 src/intel/vulkan/meson.build   |   5 +
 7 files changed, 169 insertions(+), 2 deletions(-)
 create mode 100644 src/intel/vulkan/anv_wsi_display.c

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index f22e727553f..5f6cd96825b 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -254,6 +254,9 @@ VULKAN_WSI_WAYLAND_FILES := \
 VULKAN_WSI_X11_FILES := \
vulkan/anv_wsi_x11.c
 
+VULKAN_WSI_DISPLAY_FILES := \
+   vulkan/anv_wsi_display.c
+
 VULKAN_GEM_FILES := \
vulkan/anv_gem.c
 
diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index 4125cb205ad..9b7fbb74007 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -192,6 +192,13 @@ VULKAN_SOURCES += $(VULKAN_WSI_WAYLAND_FILES)
 VULKAN_LIB_DEPS += $(WAYLAND_CLIENT_LIBS)
 endif
 
+if HAVE_PLATFORM_DRM
+VULKAN_CPPFLAGS += \
+   -DVK_USE_PLATFORM_DISPLAY_KHR
+
+VULKAN_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
+endif
+
 noinst_LTLIBRARIES += vulkan/libvulkan_common.la
 vulkan_libvulkan_common_la_SOURCES = $(VULKAN_SOURCES)
 vulkan_libvulkan_common_la_CFLAGS = $(VULKAN_CFLAGS)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 56e91fe5de1..b3c6d1a8722 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -274,6 +274,7 @@ anv_physical_device_init_uuids(struct anv_physical_device 
*device)
 static VkResult
 anv_physical_device_init(struct anv_physical_device *device,
  struct anv_instance *instance,
+ const char *primary_path,
  const char *path)
 {
VkResult result;
@@ -445,6 +446,25 @@ anv_physical_device_init(struct anv_physical_device 
*device,
anv_physical_device_get_supported_extensions(device,
 &device->supported_extensions);
 
+   if (instance->enabled_extensions.KHR_display) {
+  master_fd = open(path, O_RDWR | O_CLOEXEC);
+  if (master_fd >= 0) {
+ /* prod the device with a GETPARAM call which will fail if
+  * we don't have permission to even render on this device
+  */
+ drm_i915_getparam_t gp;
+ memset(&gp, '\0', sizeof(gp));
+ int devid = 0;
+ gp.param = I915_PARAM_CHIPSET_ID;
+ gp.value = &devid;
+ int ret = drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ if (ret < 0) {
+close(master_fd);
+master_fd = -1;
+ }
+  }
+   }
+
device->local_fd = fd;
device->master_fd = master_fd;
return VK_SUCCESS;
@@ -635,6 +655,7 @@ anv_enumerate_devices(struct anv_instance *instance)
 
  result = anv_physical_device_init(&instance->physicalDevice,
 instance,
+devices[i]->nodes[DRM_NODE_PRIMARY],
 devices[i]->nodes[DRM_NODE_RENDER]);
  if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
 break;
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 8160864685f..83c09a46741 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -107,6 +107,7 @@ EXTENSIONS = [
 Extension('VK_KHR_xcb_surface',   6, 
'VK_USE_PLATFORM_XCB_KHR'),
 Extension('VK_KHR_xlib_surface',  6, 
'VK_USE_PLATFORM_XLIB_KHR'),
 Extension('VK_KHR_multiview', 1, Tr

[Mesa-dev] [PATCH mesa 6/9] radv: Add EXT_direct_mode_display to radv driver

[Keith Packard]

Add support for the EXT_direct_mode_display extension. This just
provides the vkReleaseDisplayEXT function.

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/radv_extensions.py |  1 +
 src/amd/vulkan/radv_wsi_display.c | 11 +++
 2 files changed, 12 insertions(+)

diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index 6f4fc71bfd8..fc545ce2580 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -87,6 +87,7 @@ EXTENSIONS = [
 Extension('VK_KHR_xlib_surface',  6, 
'VK_USE_PLATFORM_XLIB_KHR'),
 Extension('VK_KHR_multiview', 1, True),
 Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_debug_report',  9, True),
 Extension('VK_EXT_depth_range_unrestricted',  1, True),
 Extension('VK_EXT_descriptor_indexing',   2, True),
diff --git a/src/amd/vulkan/radv_wsi_display.c 
b/src/amd/vulkan/radv_wsi_display.c
index c58a6717c66..dfe3434a623 100644
--- a/src/amd/vulkan/radv_wsi_display.c
+++ b/src/amd/vulkan/radv_wsi_display.c
@@ -147,3 +147,14 @@ radv_CreateDisplayPlaneSurfaceKHR(
return wsi_create_display_surface(_instance, alloc,
  create_info, surface);
 }
+
+VkResult
+radv_ReleaseDisplayEXT(VkPhysicalDevice physical_device,
+  VkDisplayKHR display)
+{
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
+
+   return wsi_release_display(physical_device,
+  &pdevice->wsi_device,
+  display);
+}
-- 
2.17.1

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[Mesa-dev] [PATCH mesa 4/9] vulkan: Add EXT_direct_mode_display [v2]

[Keith Packard]

Add support for the EXT_direct_mode_display extension. This just
provides the vkReleaseDisplayEXT function.

v2:
Adopt Jason Ekstrand's coding conventions

Declare variables at first use, eliminate extra whitespace
between types and names. Wrap lines to 80 columns.

Suggested-by: Jason Ekstrand 

Signed-off-by: Keith Packard 
---
 src/vulkan/wsi/wsi_common_display.c | 18 ++
 src/vulkan/wsi/wsi_common_display.h |  5 +
 2 files changed, 23 insertions(+)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index e529d2fc580..7a484c0df95 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -1430,3 +1430,21 @@ wsi_display_finish_wsi(struct wsi_device *wsi_device,
   vk_free(alloc, wsi);
}
 }
+
+/*
+ * Implement vkReleaseDisplay
+ */
+VkResult
+wsi_release_display(VkPhysicalDevicephysical_device,
+struct wsi_device   *wsi_device,
+VkDisplayKHRdisplay)
+{
+   struct wsi_display *wsi =
+  (struct wsi_display *) wsi_device->wsi[VK_ICD_WSI_PLATFORM_DISPLAY];
+
+   if (wsi->fd >= 0) {
+  close(wsi->fd);
+  wsi->fd = -1;
+   }
+   return VK_SUCCESS;
+}
diff --git a/src/vulkan/wsi/wsi_common_display.h 
b/src/vulkan/wsi/wsi_common_display.h
index 4bb86cf2102..dd3a098f80a 100644
--- a/src/vulkan/wsi/wsi_common_display.h
+++ b/src/vulkan/wsi/wsi_common_display.h
@@ -74,4 +74,9 @@ wsi_create_display_surface(VkInstance instance,
const VkDisplaySurfaceCreateInfoKHR *pCreateInfo,
VkSurfaceKHR *pSurface);
 
+VkResult
+wsi_release_display(VkPhysicalDevicephysical_device,
+struct wsi_device   *wsi_device,
+VkDisplayKHRdisplay);
+
 #endif
-- 
2.17.1

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[Mesa-dev] [PATCH mesa 8/9] anv: Add EXT_acquire_xlib_display to anv driver [v3]

[Keith Packard]

This extension adds the ability to borrow an X RandR output for
temporary use directly by a Vulkan application to the anv driver.

v2:
Simplify addition of VK_USE_PLATFORM_XLIB_XRANDR_KHR to
vulkan_wsi_args

Suggested-by: Eric Engestrom 

v3:
Add extension to list in alphabetical order

Suggested-by:  Jason Ekstrand 

Signed-off-by: Keith Packard 
---
 src/intel/Makefile.vulkan.am|  7 ++
 src/intel/vulkan/anv_entrypoints_gen.py |  5 -
 src/intel/vulkan/anv_extensions.py  |  1 +
 src/intel/vulkan/anv_extensions_gen.py  | 10 -
 src/intel/vulkan/anv_wsi_display.c  | 30 +
 src/intel/vulkan/meson.build|  5 +
 6 files changed, 52 insertions(+), 6 deletions(-)

diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index 9b7fbb74007..ae625695814 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -199,6 +199,13 @@ VULKAN_CPPFLAGS += \
 VULKAN_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
 endif
 
+if HAVE_XLIB_LEASE
+VULKAN_CPPFLAGS += \
+   -DVK_USE_PLATFORM_XLIB_XRANDR_EXT \
+   $(XCB_RANDR_CFLAGS)
+VULKAN_LIB_DEPS += $(XCB_RANDR_LIBS)
+endif
+
 noinst_LTLIBRARIES += vulkan/libvulkan_common.la
 vulkan_libvulkan_common_la_SOURCES = $(VULKAN_SOURCES)
 vulkan_libvulkan_common_la_CFLAGS = $(VULKAN_CFLAGS)
diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index 230671d36ae..db350698501 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -513,7 +513,10 @@ def get_entrypoints_defines(doc):
 
 for extension in doc.findall('./extensions/extension[@platform]'):
 platform = extension.attrib['platform']
-define = 'VK_USE_PLATFORM_' + platform.upper() + '_KHR'
+ext = '_KHR'
+if platform.upper() == 'XLIB_XRANDR':
+ext = '_EXT'
+define = 'VK_USE_PLATFORM_' + platform.upper() + ext
 
 for entrypoint in extension.findall('./require/command'):
 fullname = entrypoint.attrib['name']
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index d63b994b601..4bffbcb5a2a 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -108,6 +108,7 @@ EXTENSIONS = [
 Extension('VK_KHR_xlib_surface',  6, 
'VK_USE_PLATFORM_XLIB_KHR'),
 Extension('VK_KHR_multiview', 1, True),
 Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_EXT_acquire_xlib_display',  1, 
'VK_USE_PLATFORM_XLIB_XRANDR_EXT'),
 Extension('VK_EXT_debug_report',  8, True),
 Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_external_memory_dma_buf',   1, True),
diff --git a/src/intel/vulkan/anv_extensions_gen.py 
b/src/intel/vulkan/anv_extensions_gen.py
index 83cbfed82c7..b00c1108273 100644
--- a/src/intel/vulkan/anv_extensions_gen.py
+++ b/src/intel/vulkan/anv_extensions_gen.py
@@ -103,12 +103,12 @@ _TEMPLATE_C = Template(COPYRIGHT + """
 #include "vk_util.h"
 
 /* Convert the VK_USE_PLATFORM_* defines to booleans */
-%for platform in ['ANDROID', 'WAYLAND', 'XCB', 'XLIB', 'DISPLAY']:
-#ifdef VK_USE_PLATFORM_${platform}_KHR
-#   undef VK_USE_PLATFORM_${platform}_KHR
-#   define VK_USE_PLATFORM_${platform}_KHR true
+%for platform in ['ANDROID_KHR', 'WAYLAND_KHR', 'XCB_KHR', 'XLIB_KHR', 
'DISPLAY_KHR', 'XLIB_XRANDR_EXT']:
+#ifdef VK_USE_PLATFORM_${platform}
+#   undef VK_USE_PLATFORM_${platform}
+#   define VK_USE_PLATFORM_${platform} true
 #else
-#   define VK_USE_PLATFORM_${platform}_KHR false
+#   define VK_USE_PLATFORM_${platform} false
 #endif
 %endfor
 
diff --git a/src/intel/vulkan/anv_wsi_display.c 
b/src/intel/vulkan/anv_wsi_display.c
index 8e0f8582863..f749a8d98f7 100644
--- a/src/intel/vulkan/anv_wsi_display.c
+++ b/src/intel/vulkan/anv_wsi_display.c
@@ -138,3 +138,33 @@ anv_ReleaseDisplayEXT(VkPhysicalDevice physical_device,
   &pdevice->wsi_device,
   display);
 }
+
+#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT
+VkResult
+anv_AcquireXlibDisplayEXT(VkPhysicalDevice physical_device,
+   Display  *dpy,
+   VkDisplayKHR display)
+{
+   ANV_FROM_HANDLE(anv_physical_device, pdevice, physical_device);
+
+   return wsi_acquire_xlib_display(physical_device,
+   &pdevice->wsi_device,
+   dpy,
+   display);
+}
+
+VkResult
+anv_GetRandROutputDisplayEXT(VkPhysicalDevice  physical_device,
+  Display   *dpy,
+  RROutput  output,
+  VkDisplayKHR  *display)

[Mesa-dev] [PATCH mesa 3/9] radv: Add KHR_display extension to radv [v4]

[Keith Packard]

This adds support for the KHR_display extension to the radv Vulkan
driver. The driver now attempts to open the master DRM node when the
KHR_display extension is requested so that the common winsys code can
perform the necessary operations.

v2:
* Simplify addition of VK_USE_PLATFORM_DISPLAY_KHR to
  vulkan_wsi_args

Suggested-by: Eric Engestrom 

v3:
Adapt to new wsi_device_init API (added display_fd)

v4:
Adopt Jason Ekstrand's coding conventions

Declare variables at first use, eliminate extra whitespace
between types and names. Wrap lines to 80 columns.

Suggested-by: Jason Ekstrand 

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/Makefile.am|   8 ++
 src/amd/vulkan/Makefile.sources   |   3 +
 src/amd/vulkan/meson.build|   5 +
 src/amd/vulkan/radv_device.c  |  17 
 src/amd/vulkan/radv_extensions.py |   7 +-
 src/amd/vulkan/radv_private.h |   1 +
 src/amd/vulkan/radv_wsi_display.c | 149 ++
 7 files changed, 188 insertions(+), 2 deletions(-)
 create mode 100644 src/amd/vulkan/radv_wsi_display.c

diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index 18f263ab447..f4f99400275 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -80,6 +80,14 @@ VULKAN_LIB_DEPS = \
$(DLOPEN_LIBS) \
-lm
 
+if HAVE_PLATFORM_DRM
+AM_CPPFLAGS += \
+   -DVK_USE_PLATFORM_DISPLAY_KHR
+
+VULKAN_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
+
+endif
+
 if HAVE_PLATFORM_X11
 AM_CPPFLAGS += \
$(XCB_DRI3_CFLAGS) \
diff --git a/src/amd/vulkan/Makefile.sources b/src/amd/vulkan/Makefile.sources
index ccb956a2396..70d56e88cb3 100644
--- a/src/amd/vulkan/Makefile.sources
+++ b/src/amd/vulkan/Makefile.sources
@@ -80,6 +80,9 @@ VULKAN_WSI_WAYLAND_FILES := \
 VULKAN_WSI_X11_FILES := \
radv_wsi_x11.c
 
+VULKAN_WSI_DISPLAY_FILES := \
+   radv_wsi_display.c
+
 VULKAN_GENERATED_FILES := \
radv_entrypoints.c \
radv_entrypoints.h \
diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build
index b5a99fe91e1..15e69d582dd 100644
--- a/src/amd/vulkan/meson.build
+++ b/src/amd/vulkan/meson.build
@@ -115,6 +115,11 @@ if with_platform_wayland
   libradv_files += files('radv_wsi_wayland.c')
 endif
 
+if with_platform_drm
+  radv_flags += '-DVK_USE_PLATFORM_DISPLAY_KHR'
+  libradv_files += files('radv_wsi_display.c')
+endif
+
 libvulkan_radeon = shared_library(
   'vulkan_radeon',
   [libradv_files, radv_entrypoints, radv_extensions_c, vk_format_table_c],
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index ca091ee12ba..59ee503c8c2 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -274,6 +274,23 @@ radv_physical_device_init(struct radv_physical_device 
*device,
goto fail;
}
 
+   if (instance->enabled_extensions.KHR_display) {
+   master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | 
O_CLOEXEC);
+   if (master_fd >= 0) {
+   uint32_t accel_working = 0;
+   struct drm_amdgpu_info request = {
+   .return_pointer = (uintptr_t)&accel_working,
+   .return_size = sizeof(accel_working),
+   .query = AMDGPU_INFO_ACCEL_WORKING
+   };
+
+   if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, 
&request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
+   close(master_fd);
+   master_fd = -1;
+   }
+   }
+   }
+
device->master_fd = master_fd;
device->local_fd = fd;
device->ws->query_info(device->ws, &device->rad_info);
diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index a5b5a8dc34e..6f4fc71bfd8 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -86,6 +86,7 @@ EXTENSIONS = [
 Extension('VK_KHR_xcb_surface',   6, 
'VK_USE_PLATFORM_XCB_KHR'),
 Extension('VK_KHR_xlib_surface',  6, 
'VK_USE_PLATFORM_XLIB_KHR'),
 Extension('VK_KHR_multiview', 1, True),
+Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_debug_report',  9, True),
 Extension('VK_EXT_depth_range_unrestricted',  1, True),
 Extension('VK_EXT_descriptor_indexing',   2, True),
@@ -214,7 +215,7 @@ _TEMPLATE_C = Template(COPYRIGHT + """
 #include "vk_util.h"
 
 /* Convert the VK_USE_PLATFORM_* defines to booleans */
-%for platform in ['ANDROID', 'WAYLAND', 'XCB', 'XLIB']:
+%for platform in ['ANDROID', 'WAYLAND', 'XCB', 'XLIB', 'DISPLAY']:
 #ifdef VK_USE_PLATFORM_${platform}_KHR
 #   undef VK_USE_PLATFORM_${platform}_KHR
 #   define VK_USE_P

[Mesa-dev] [PATCH mesa 9/9] radv: Add EXT_acquire_xlib_display to radv driver [v2]

[Keith Packard]

This extension adds the ability to borrow an X RandR output for
temporary use directly by a Vulkan application to the radv driver.

v2:
Simplify addition of VK_USE_PLATFORM_XLIB_XRANDR_KHR to
vulkan_wsi_args

Suggested-by: Eric Engestrom 

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/Makefile.am |  7 ++
 src/amd/vulkan/meson.build |  5 +
 src/amd/vulkan/radv_entrypoints_gen.py |  5 -
 src/amd/vulkan/radv_extensions.py  | 11 +-
 src/amd/vulkan/radv_wsi_display.c  | 30 ++
 5 files changed, 52 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index f4f99400275..8279fe4a81f 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -85,7 +85,14 @@ AM_CPPFLAGS += \
-DVK_USE_PLATFORM_DISPLAY_KHR
 
 VULKAN_SOURCES += $(VULKAN_WSI_DISPLAY_FILES)
+endif
+
+if HAVE_XLIB_LEASE
+AM_CPPFLAGS += \
+   -DVK_USE_PLATFORM_XLIB_XRANDR_EXT \
+   $(XCB_RANDR_CFLAGS)
 
+VULKAN_LIB_DEPS += $(XCB_RANDR_LIBS)
 endif
 
 if HAVE_PLATFORM_X11
diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build
index 15e69d582dd..bcdf83e0609 100644
--- a/src/amd/vulkan/meson.build
+++ b/src/amd/vulkan/meson.build
@@ -120,6 +120,11 @@ if with_platform_drm
   libradv_files += files('radv_wsi_display.c')
 endif
 
+if with_xlib_lease
+  radv_deps += dep_xcb_xrandr
+  radv_flags += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
+endif
+
 libvulkan_radeon = shared_library(
   'vulkan_radeon',
   [libradv_files, radv_entrypoints, radv_extensions_c, vk_format_table_c],
diff --git a/src/amd/vulkan/radv_entrypoints_gen.py 
b/src/amd/vulkan/radv_entrypoints_gen.py
index a2011429869..bef0c447f68 100644
--- a/src/amd/vulkan/radv_entrypoints_gen.py
+++ b/src/amd/vulkan/radv_entrypoints_gen.py
@@ -449,7 +449,10 @@ def get_entrypoints_defines(doc):
 
 for extension in doc.findall('./extensions/extension[@platform]'):
 platform = extension.attrib['platform']
-define = 'VK_USE_PLATFORM_' + platform.upper() + '_KHR'
+ext = '_KHR'
+if platform.upper() == 'XLIB_XRANDR':
+ext = '_EXT'
+define = 'VK_USE_PLATFORM_' + platform.upper() + ext
 
 for entrypoint in extension.findall('./require/command'):
 fullname = entrypoint.attrib['name']
diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index fc545ce2580..65ce7349016 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -88,6 +88,7 @@ EXTENSIONS = [
 Extension('VK_KHR_multiview', 1, True),
 Extension('VK_KHR_display',  23, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_EXT_acquire_xlib_display',  1, 
'VK_USE_PLATFORM_XLIB_XRANDR_EXT'),
 Extension('VK_EXT_debug_report',  9, True),
 Extension('VK_EXT_depth_range_unrestricted',  1, True),
 Extension('VK_EXT_descriptor_indexing',   2, True),
@@ -216,12 +217,12 @@ _TEMPLATE_C = Template(COPYRIGHT + """
 #include "vk_util.h"
 
 /* Convert the VK_USE_PLATFORM_* defines to booleans */
-%for platform in ['ANDROID', 'WAYLAND', 'XCB', 'XLIB', 'DISPLAY']:
-#ifdef VK_USE_PLATFORM_${platform}_KHR
-#   undef VK_USE_PLATFORM_${platform}_KHR
-#   define VK_USE_PLATFORM_${platform}_KHR true
+%for platform in ['ANDROID_KHR', 'WAYLAND_KHR', 'XCB_KHR', 'XLIB_KHR', 
'DISPLAY_KHR', 'XLIB_XRANDR_EXT']:
+#ifdef VK_USE_PLATFORM_${platform}
+#   undef VK_USE_PLATFORM_${platform}
+#   define VK_USE_PLATFORM_${platform} true
 #else
-#   define VK_USE_PLATFORM_${platform}_KHR false
+#   define VK_USE_PLATFORM_${platform} false
 #endif
 %endfor
 
diff --git a/src/amd/vulkan/radv_wsi_display.c 
b/src/amd/vulkan/radv_wsi_display.c
index dfe3434a623..0f88ce13942 100644
--- a/src/amd/vulkan/radv_wsi_display.c
+++ b/src/amd/vulkan/radv_wsi_display.c
@@ -158,3 +158,33 @@ radv_ReleaseDisplayEXT(VkPhysicalDevice physical_device,
   &pdevice->wsi_device,
   display);
 }
+
+#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT
+VkResult
+radv_AcquireXlibDisplayEXT(VkPhysicalDevice physical_device,
+  Display  *dpy,
+  VkDisplayKHR display)
+{
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
+
+   return wsi_acquire_xlib_display(physical_device,
+   &pdevice->wsi_device,
+   dpy,
+   display);
+}
+
+VkResult
+radv_GetRandROutputDisplayEXT(VkPhysicalDevice  physical_device,
+ Display   *dpy,
+ RROutput  output,
+ VkD

[Mesa-dev] [PATCH mesa 0/0] Vulkan: Add DRM lease support

[Keith Packard]

Here's an updated patch series for DRM lease support using KHR_display
and other standard Vulkan extensions. This series incorporates review
from Eric Engestrom and Jason Ekstrom. Thanks to both of them!

-keith


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[Mesa-dev] [PATCH mesa 1/9] vulkan: Add KHR_display extension using DRM [v8]

[Keith Packard]

This adds support for the KHR_display extension support to the vulkan
WSI layer. Driver support will be added separately.

v2:
* fix double ;; in wsi_common_display.c

* Move mode list from wsi_display to wsi_display_connector

* Fix scope for wsi_display_mode andwsi_display_connector
  allocs

* Switch all allocations to vk_zalloc instead of vk_alloc.

* Fix DRM failure in
  wsi_display_get_physical_device_display_properties

  When DRM fails, or when we don't have a master fd
  (presumably due to application errors), just return 0
  properties from this function, which is at least a valid
  response.

* Use vk_outarray for all property queries

  This is a bit less error-prone than open-coding the same
  stuff.

* Remove VK_COMPOSITE_ALPHA_INHERIT_BIT_KHR from surface caps

  Until we have multi-plane support, we shouldn't pretend to
  have any multi-plane semantics, even if undefined.

Suggested-by: Jason Ekstrand 

* Simplify addition of VK_USE_PLATFORM_DISPLAY_KHR to
  vulkan_wsi_args

Suggested-by: Eric Engestrom 

v3:
Add separate 'display_fd' and 'render_fd' arguments to
wsi_device_init API. This allows drivers to use different FDs
for the different aspects of the device.

Use largest mode as display size when no preferred mode.

If the display doesn't provide a preferred mode, we'll assume
that the largest supported mode is the "physical size" of the
device and report that.

v4:
Make wsi_image_state enumeration values uppercase.
Follow more common mesa conventions.

Remove 'render_fd' from wsi_device_init API.  The
wsi_common_display code doesn't use this fd at all, so stop
passing it in. This avoids any potential confusion over which
fd to use when creating display-relative object handles.

Remove call to wsi_create_prime_image which would never have
been reached as the necessary condition (use_prime_blit) is
never set.

whitespace cleanups in wsi_common_display.c

Suggested-by: Jason Ekstrand 

Add depth/bpp info to available surface formats.  Instead of
hard-coding depth 24 bpp 32 in the drmModeAddFB call, use the
requested format to find suitable values.

Destroy kernel buffers and FBs when swapchain is destroyed. We
were leaking both of these kernel objects across swapchain
destruction.

Note that wsi_display_wait_for_event waits for anything to
happen.  wsi_display_wait_for_event is simply a yield so that
the caller can then check to see if the desired state change
has occurred.

Record swapchain failures in chain for later return. If some
asynchronous swapchain activity fails, we need to tell the
application eventually. Record the failure in the swapchain
and report it at the next acquire_next_image or queue_present
call.

Fix error returns from wsi_display_setup_connector.  If a
malloc failed, then the result should be
VK_ERROR_OUT_OF_HOST_MEMORY. Otherwise, the associated ioctl
failed and we're either VT switched away, or our lease has
been revoked, in which case we should return
VK_ERROR_OUT_OF_DATE_KHR.

Make sure both sides of if/else brace use matches

Note that we assume drmModeSetCrtc is synchronous. Add a
comment explaining why we can idle any previous displayed
image as soon as the mode set returns.

Note that EACCES from drmModePageFlip means VT inactive.  When
vt switched away drmModePageFlip returns EACCES. Poll once a
second waiting until we get some other return value back.

Clean up after alloc failure in
wsi_display_surface_create_swapchain. Destroy any created
images, free the swapchain.

Remove physical_device from wsi_display_init_wsi. We never
need this value, so remove it from the API and from the
internal wsi_display structure.

Use drmModeAddFB2 in wsi_display_image_init.  This takes a drm
format instead of depth/bpp, which provides more control over
the format of the data.

v5:
Set the 'currentStackIndex' member of the
VkDisplayPlanePropertiesKHR record to zero, instead of
indexing across all displays. This value is the stack depth of
the plane within an individual display, and as the current
code supports only a single plane per display, should be set
to zero for all elements

Discovered-by: David Mao 

v6:
Remove 'platform_display' bits from the build and use the
existing 'platform_drm' instead.

v7:
Ensure VK_ICD_WSI_PLATFORM_MAX is large enough by
setting to VK_ICD_WSI_PLATFORM_D

[Mesa-dev] [Bug 106881] glUniform4fv does not work

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106881

--- Comment #3 from Tapani Pälli  ---
IMO this looks like a shader cache issue that got fixed by following commit.
Please pull the latest Mesa and test again.

--- 8< ---
commit e266b320590ebbeadf7c98b0b493d89886534ccb
Author: Jordan Justen 
Date:   Wed Jun 6 01:57:15 2018 -0700

mesa/program_binary: add implicit UseProgram after successful ProgramBinary

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106810
Fixes: b4c37ce2140 "i965: Add ARB_get_program_binary support using
nir_serialization"
Ref: 3fe8d04a6d6 "mesa: don't always set _NEW_PROGRAM when linking"
Ref: c505d6d8522 "mesa: use gl_program for CurrentProgram rather than
gl_shader_program"
Signed-off-by: Jordan Justen 
Reviewed-by: Plamena Manolova 
Reviewed-by: Timothy Arceri 

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[Mesa-dev] [PATCH] anv: implement basic VK_AMD_shader_info support

[Timothy Arceri]

From: Timothy Arceri 

For now this just allows an app to query
VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD which for now only returns
shader-db information. This will allow us to use anv with
vkpipeline-db.

We should add shader disassembly in the future so that RenderDoc
can display it, but that will require a bunch of changes as
currently all the helper functions just fprintf everything to
stderr.
---
 src/intel/vulkan/anv_device.c |  19 +++-
 src/intel/vulkan/anv_extensions.py|   1 +
 src/intel/vulkan/anv_pipeline.c   | 129 --
 src/intel/vulkan/anv_pipeline_cache.c |   1 +
 src/intel/vulkan/anv_private.h|   5 +
 5 files changed, 147 insertions(+), 8 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index b02e1a2749..f140c6e8e5 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -36,6 +36,7 @@
 #include "util/debug.h"
 #include "util/build_id.h"
 #include "util/mesa-sha1.h"
+#include "util/string_buffer.h"
 #include "vk_util.h"
 #include "common/gen_defines.h"
 
@@ -43,7 +44,15 @@
 
 static void
 compiler_debug_log(void *data, const char *fmt, ...)
-{ }
+{
+   struct _mesa_string_buffer *buf = (struct _mesa_string_buffer *)data;
+   va_list args;
+
+   va_start(args, fmt);
+   _mesa_string_buffer_vprintf(buf, fmt, args);
+   _mesa_string_buffer_printf(buf, "\n");
+   va_end(args);
+}
 
 static void
 compiler_perf_log(void *data, const char *fmt, ...)
@@ -1456,6 +1465,8 @@ VkResult anv_CreateDevice(
 
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_DEVICE_CREATE_INFO);
 
+   bool store_shader_info = false;
+
struct anv_device_extension_table enabled_extensions = { };
for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
   int idx;
@@ -1471,6 +1482,11 @@ VkResult anv_CreateDevice(
   if (!physical_device->supported_extensions.extensions[idx])
  return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
 
+  if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
+ VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0) {
+ store_shader_info = true;
+  }
+
   enabled_extensions.extensions[idx] = true;
}
 
@@ -1516,6 +1532,7 @@ VkResult anv_CreateDevice(
device->chipset_id = physical_device->chipset_id;
device->no_hw = physical_device->no_hw;
device->lost = false;
+   device->store_shader_info = store_shader_info;
 
if (pAllocator)
   device->alloc = *pAllocator;
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 8160864685..bcff5e848b 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -68,6 +68,7 @@ MAX_API_VERSION = None # Computed later
 # the those extension strings, then tests dEQP-VK.api.info.instance.extensions
 # and dEQP-VK.api.info.device fail due to the duplicated strings.
 EXTENSIONS = [
+Extension('VK_AMD_shader_info',   1, True),
 Extension('VK_ANDROID_native_buffer', 5, 'ANDROID'),
 Extension('VK_KHR_16bit_storage', 1, 'device->info.gen 
>= 8'),
 Extension('VK_KHR_bind_memory2',  1, True),
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 240bde036d..8be349ed19 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -28,6 +28,7 @@
 #include 
 
 #include "util/mesa-sha1.h"
+#include "util/string_buffer.h"
 #include "common/gen_l3_config.h"
 #include "anv_private.h"
 #include "compiler/brw_nir.h"
@@ -81,6 +82,55 @@ void anv_DestroyShaderModule(
vk_free2(&device->alloc, pAllocator, module);
 }
 
+VkResult anv_GetShaderInfoAMD(
+VkDevice _device,
+VkPipeline _pipeline,
+VkShaderStageFlagBits shaderStage,
+VkShaderInfoTypeAMD infoType,
+size_t* pInfoSize,
+void* pInfo)
+{
+   ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
+
+   gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
+   struct anv_shader_bin *shader = pipeline->shaders[stage];
+   VkResult result = VK_SUCCESS;
+
+   /* Spec doesn't indicate what to do if the stage is invalid, so just
+* return no info for this.
+*/
+   if (!shader)
+  return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
+
+   switch (infoType) {
+  case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD: {
+ /* Need to include the null terminator. */
+ size_t length = strlen(shader->shader_info) + 1;
+
+ if (!pInfo) {
+*pInfoSize = length;
+ } else {
+size_t size = *pInfoSize;
+*pInfoSize = length;
+
+memcpy(pInfo, shader->shader_info, MIN2(size, length));
+
+if (size < length)
+   result = VK_INCOMPLETE;
+ }
+ break;
+  }
+  default:
+ /* VK_SHADER_INFO_TYPE_BINARY_AMD and 
VK_SHADER_INFO_TYPE_STATISTICS_AMD
+  * are unimplemented.
+  */
+ result = VK_ERROR_FE

[Mesa-dev] [PATCH 2/2] vkpipeline-db: add support for anv

[Timothy Arceri]

From: Timothy Arceri 

---
 anv-report.py | 191 ++
 run.c |  75 +---
 2 files changed, 239 insertions(+), 27 deletions(-)
 create mode 100755 anv-report.py

diff --git a/anv-report.py b/anv-report.py
new file mode 100755
index 000..b306220
--- /dev/null
+++ b/anv-report.py
@@ -0,0 +1,191 @@
+#!/usr/bin/env python3
+
+import re
+import argparse
+
+
+def get_results(filename):
+file = open(filename, "r")
+lines = file.read().split('\n')
+
+results = {}
+
+re_match = re.compile(r"(\S+) - (\S+ \S+) shader: (\S*) inst, (\S*) loops, 
(\S*) cycles, (\S*):(\S*) spills:fills")
+for line in lines:
+match = re.search(re_match, line)
+if match is None:
+continue
+
+groups = match.groups()
+inst_count = int(groups[2])
+loop_count = int(groups[3])
+cycle_count = int(groups[4])
+spill_count = int(groups[5])
+fill_count = int(groups[6])
+if inst_count != 0:
+results[(groups[0], groups[1])] = {
+"instructions": inst_count,
+"spills": spill_count,
+"fills": fill_count,
+"cycles": cycle_count,
+"loops": loop_count
+}
+
+return results
+
+
+def format_percent(frac):
+"""Converts a factional value (typically 0.0 to 1.0) to a string as a 
percentage"""
+if abs(frac) > 0.0 and abs(frac) < 0.0001:
+return "<.01%"
+else:
+return "{:.2f}%".format(frac * 100)
+
+
+def get_delta(b, a):
+if b != 0 and a != 0:
+frac = float(a) / float(b) - 1.0
+return ' ({})'.format(format_percent(frac))
+else:
+return ''
+
+
+def change(b, a):
+return str(b) + " -> " + str(a) + get_delta(b, a)
+
+
+def get_result_string(p, b, a):
+p = p + ": "
+while len(p) < 50:
+p = p + ' '
+return p + change(b, a)
+
+def split_list(string):
+return string.split(",")
+
+def main():
+parser = argparse.ArgumentParser()
+parser.add_argument("--measurements", "-m", type=split_list,
+default=["instructions", "cycles", "loops", "spills", 
"fills"],
+help="comma-separated list of measurements to report")
+parser.add_argument("--summary-only", "-s", action="store_true", 
default=False,
+help="do not show the per-shader helped / hurt data")
+parser.add_argument("--changes-only", "-c", action="store_true", 
default=False,
+help="only show measurements that have changes")
+parser.add_argument("before", type=get_results, help="the output of the 
original code")
+parser.add_argument("after", type=get_results, help="the output of the new 
code")
+args = parser.parse_args()
+
+total_before = {}
+total_after = {}
+affected_before = {}
+affected_after = {}
+num_hurt = {}
+num_helped = {}
+
+for m in args.measurements:
+total_before[m] = 0
+total_after[m] = 0
+affected_before[m] = 0
+affected_after[m] = 0
+
+helped = []
+hurt = []
+for p in args.before:
+before_count = args.before[p][m]
+
+if args.after.get(p) is None:
+continue
+
+# If the number of loops changed, then we may have unrolled some
+# loops, in which case other measurements will be misleading.
+if m != "loops" and args.before[p]["loops"] != 
args.after[p]["loops"]:
+continue
+
+after_count = args.after[p][m]
+
+total_before[m] += before_count
+total_after[m] += after_count
+
+if before_count != after_count:
+affected_before[m] += before_count
+affected_after[m] += after_count
+
+if after_count > before_count:
+hurt.append(p)
+else:
+helped.append(p)
+
+if not args.summary_only:
+helped.sort(
+key=lambda k: args.after[k][m] if args.before[k][m] == 0 else 
float(args.before[k][m] - args.after[k][m]) / args.before[k][m])
+for p in helped:
+namestr = p[0] + " " + p[1]
+print(m + " helped:   " + get_result_string(
+namestr, args.before[p][m], args.after[p][m]))
+if helped:
+print("")
+
+hurt.sort(
+key=lambda k: args.after[k][m] if args.before[k][m] == 0 else 
float(args.after[k][m] - args.before[k][m]) / args.before[k][m])
+for p in hurt:
+namestr = p[0] + " " + p[1]
+print(m + " HURT:   " + get_result_string(
+namestr, args.before[p][m], args.after[p][m]))
+if hurt:
+print("")
+
+num_helped[m] = len(helped)
+num_hurt[m] = len(hurt)
+
+
+lost = []
+

[Mesa-dev] [PATCH 1/2] vkpipeline-db: add sType to pipeline info

[Timothy Arceri]

From: Timothy Arceri 

This avoids hitting asserts in anv.
---
 run.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/run.c b/run.c
index eafbd7d..a962887 100644
--- a/run.c
+++ b/run.c
@@ -264,6 +264,7 @@ create_graphics_pipeline(VkDevice device, struct 
pipeline_info *info,
 return result;
 
 /* Graphics pipeline. */
+pipelineInfo.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO;
 pipelineInfo.stageCount = info->stageCount;
 pipelineInfo.pStages = info->pShaderStagesInfo;
 pipelineInfo.pVertexInputState = &info->vertexInputState;
@@ -292,6 +293,7 @@ create_compute_pipeline(VkDevice device, struct 
pipeline_info *info,
 VkComputePipelineCreateInfo pipelineInfo = {};
 
 /* Compute pipeline. */
+pipelineInfo.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO;
 pipelineInfo.stage = *info->pShaderStagesInfo;
 pipelineInfo.layout = layout;
 
-- 
2.17.1

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[Mesa-dev] [PATCH 2/2] vkpipeline-db: add support for anv

[Timothy Arceri]

From: Timothy Arceri 

---
 anv-report.py | 191 ++
 run.c |  75 +---
 2 files changed, 239 insertions(+), 27 deletions(-)
 create mode 100755 anv-report.py

diff --git a/anv-report.py b/anv-report.py
new file mode 100755
index 000..b306220
--- /dev/null
+++ b/anv-report.py
@@ -0,0 +1,191 @@
+#!/usr/bin/env python3
+
+import re
+import argparse
+
+
+def get_results(filename):
+file = open(filename, "r")
+lines = file.read().split('\n')
+
+results = {}
+
+re_match = re.compile(r"(\S+) - (\S+ \S+) shader: (\S*) inst, (\S*) loops, 
(\S*) cycles, (\S*):(\S*) spills:fills")
+for line in lines:
+match = re.search(re_match, line)
+if match is None:
+continue
+
+groups = match.groups()
+inst_count = int(groups[2])
+loop_count = int(groups[3])
+cycle_count = int(groups[4])
+spill_count = int(groups[5])
+fill_count = int(groups[6])
+if inst_count != 0:
+results[(groups[0], groups[1])] = {
+"instructions": inst_count,
+"spills": spill_count,
+"fills": fill_count,
+"cycles": cycle_count,
+"loops": loop_count
+}
+
+return results
+
+
+def format_percent(frac):
+"""Converts a factional value (typically 0.0 to 1.0) to a string as a 
percentage"""
+if abs(frac) > 0.0 and abs(frac) < 0.0001:
+return "<.01%"
+else:
+return "{:.2f}%".format(frac * 100)
+
+
+def get_delta(b, a):
+if b != 0 and a != 0:
+frac = float(a) / float(b) - 1.0
+return ' ({})'.format(format_percent(frac))
+else:
+return ''
+
+
+def change(b, a):
+return str(b) + " -> " + str(a) + get_delta(b, a)
+
+
+def get_result_string(p, b, a):
+p = p + ": "
+while len(p) < 50:
+p = p + ' '
+return p + change(b, a)
+
+def split_list(string):
+return string.split(",")
+
+def main():
+parser = argparse.ArgumentParser()
+parser.add_argument("--measurements", "-m", type=split_list,
+default=["instructions", "cycles", "loops", "spills", 
"fills"],
+help="comma-separated list of measurements to report")
+parser.add_argument("--summary-only", "-s", action="store_true", 
default=False,
+help="do not show the per-shader helped / hurt data")
+parser.add_argument("--changes-only", "-c", action="store_true", 
default=False,
+help="only show measurements that have changes")
+parser.add_argument("before", type=get_results, help="the output of the 
original code")
+parser.add_argument("after", type=get_results, help="the output of the new 
code")
+args = parser.parse_args()
+
+total_before = {}
+total_after = {}
+affected_before = {}
+affected_after = {}
+num_hurt = {}
+num_helped = {}
+
+for m in args.measurements:
+total_before[m] = 0
+total_after[m] = 0
+affected_before[m] = 0
+affected_after[m] = 0
+
+helped = []
+hurt = []
+for p in args.before:
+before_count = args.before[p][m]
+
+if args.after.get(p) is None:
+continue
+
+# If the number of loops changed, then we may have unrolled some
+# loops, in which case other measurements will be misleading.
+if m != "loops" and args.before[p]["loops"] != 
args.after[p]["loops"]:
+continue
+
+after_count = args.after[p][m]
+
+total_before[m] += before_count
+total_after[m] += after_count
+
+if before_count != after_count:
+affected_before[m] += before_count
+affected_after[m] += after_count
+
+if after_count > before_count:
+hurt.append(p)
+else:
+helped.append(p)
+
+if not args.summary_only:
+helped.sort(
+key=lambda k: args.after[k][m] if args.before[k][m] == 0 else 
float(args.before[k][m] - args.after[k][m]) / args.before[k][m])
+for p in helped:
+namestr = p[0] + " " + p[1]
+print(m + " helped:   " + get_result_string(
+namestr, args.before[p][m], args.after[p][m]))
+if helped:
+print("")
+
+hurt.sort(
+key=lambda k: args.after[k][m] if args.before[k][m] == 0 else 
float(args.after[k][m] - args.before[k][m]) / args.before[k][m])
+for p in hurt:
+namestr = p[0] + " " + p[1]
+print(m + " HURT:   " + get_result_string(
+namestr, args.before[p][m], args.after[p][m]))
+if hurt:
+print("")
+
+num_helped[m] = len(helped)
+num_hurt[m] = len(hurt)
+
+
+lost = []
+

[Mesa-dev] [PATCH 1/2] vkpipeline-db: add sType to pipeline info

[Timothy Arceri]

From: Timothy Arceri 

This avoids hitting asserts in anv.
---
 run.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/run.c b/run.c
index eafbd7d..a962887 100644
--- a/run.c
+++ b/run.c
@@ -264,6 +264,7 @@ create_graphics_pipeline(VkDevice device, struct 
pipeline_info *info,
 return result;
 
 /* Graphics pipeline. */
+pipelineInfo.sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO;
 pipelineInfo.stageCount = info->stageCount;
 pipelineInfo.pStages = info->pShaderStagesInfo;
 pipelineInfo.pVertexInputState = &info->vertexInputState;
@@ -292,6 +293,7 @@ create_compute_pipeline(VkDevice device, struct 
pipeline_info *info,
 VkComputePipelineCreateInfo pipelineInfo = {};
 
 /* Compute pipeline. */
+pipelineInfo.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO;
 pipelineInfo.stage = *info->pShaderStagesInfo;
 pipelineInfo.layout = layout;
 
-- 
2.17.1

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Re: [Mesa-dev] [PATCH mesa 07/21] vulkan: Add EXT_acquire_xlib_display [v2]

[Keith Packard]

Jason Ekstrand  writes:

> As with patch 1, I've gone through and made a pile of style changes to
> bring things back under 80 characters.  You can find it on this
> branch:

I've adopted that style across the whole series.

>>  struct wsi_display {
>> @@ -1414,5 +1421,468 @@ wsi_release_display(VkPhysicalDevice
>> physical_device,
>>close(wsi->fd);
>>wsi->fd = -1;
>> }
>> +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT
>> +   wsi_display_connector_from_handle(display)->output = None;
>>
>
> Does this function ever return NULL?

That's a standard handle to pointer macro -- if display is valid, then
the macro will return a valid pointer.

>> +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT
>> +
>> +static struct wsi_display_connector *
>> +wsi_display_find_output(struct wsi_device   *wsi_device,
>> +RROutputoutput)
>>
>
> You're using RROutput here but xcb_rander_output_t elsewhere.  Why not just
> pick one?

The API is specified using Xlib types, but the implementation uses
XCB. They are the "same" underlying type of course; I have switched to
use the xcb types uniformly in the implementation except in the public
API which then casts from RROutput to xcb_randr_output_t.

> Things are going way over the usual 80 character limit.  I'm fixing up
> whitespace as I read and will put a fixup in my branch.

All fixed.

>> +  xcb_randr_query_version_reply_t   *qv_r =
>> xcb_randr_query_version_reply(connection, qv_c, NULL);
>> +  free(qv_r);
>>
>
> What's up with the version query?  We're throwing it away without ever
> using it.  Does this provide us with some error checkint of some sort?

You're required to call the query_version request before doing any other
RandR requests, and this function may well be making the very first
calls to RandR.

In this case, we're about to call a RandR function supported since time
immemorial, so we don't actually care what version the server
reports. You'll note that we *do* check the version before we start
trying to perform any leasing operations.

>> +  if (!connector) {
>>
>
> This is always true.
...
> And this can be merged in.

Yeah, I noticed that this got refactored several times and the
conditions became mixed up (not "wrong", but illogical). I've rewritten
it so that it makes sense again.

>> +for (int o = 0; o < num_outputs; o++)
>> +   if (outputs[o] == output && num_outputs == 1) {
>>
>
> checking for num_outputs == 1 inside the loop is a bit odd.

Thanks. Again, refactoring this code left it looking strange. I've
changed this to:

if (num_outputs == 1 && outputs[0] == output)
   active_crtc = rc[c];

-- 
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Re: [Mesa-dev] [PATCH mesa 05/21] anv: Add EXT_direct_mode_display to anv driver

[Keith Packard]

Jason Ekstrand  writes:

> Alphabetize, please. :-)

They're not actually in alphabetical order; EXT comes after KHR?

I've ordered the EXT extensions within the existing EXT list, and added
the MESA and GOOGLE extensions at the end.

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Re: [Mesa-dev] [PATCH mesa 04/21] vulkan: Add EXT_direct_mode_display

[Keith Packard]

Jason Ekstrand  writes:

> This seems a bit odd.  Why is the FD not stored in the display?  What if
> you acquire multiple displays for two-player VR?  If the master FD passed
> in is not -1, we could just create a VkDisplayKHR object containing
> it.

You want to share the master_fd passed in at init_wsi time among all
VkDisplayKHR objects, so you need to leave that FD in the global
structure. However, you're right that when you use
EXT_acquire_xlib_display, then you get a separate master_fd for each DRM
output and need to have one per display.

However, extending this code to support multiple master FDs looks tricky
-- in the case where you have a single master_fd, then enumerating the
DRM resources for that gives you all of the available
connectors. However, if you have one DRM master per connector, then you
need to enumerate each independently to get the complete set of
available resources. For APIs which don't explicitly include a
connector, I would have to go find a suitable master FD for each
resource.

How about I just disallow multiple leases for now? If you want multiple
outputs, I think you'd want them on the same DRM master anyways, and we
could get that by creating a new extension which had the application
pass in a DRM master that had all of the resources you want to access.

   /* XXX no support for multiple leases yet */
   if (wsi->fd >= 0)
  return VK_ERROR_OUT_OF_DATE_KHR;

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Re: [Mesa-dev] [PATCH mesa 02/21] anv: Add KHR_display extension to anv [v4]

[Keith Packard]

Jason Ekstrand  writes:

>> +#define MM_PER_PIXEL (1.0/96.0 * 25.4)
>>
>
> I don't think you need this. :-)

Now you have me wondering when it was needed :-)

> Other than that and the comment on patch 1 about stuff that should probably
> go here, this looks good to me.

Yeah, if you're not confused by the patch series, I'm not all that
excited about refactoring these bits. Let me know what you think.

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Re: [Mesa-dev] [PATCH 05/48] gallium: fix ddebug on windows

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Mon, Jun 11, 2018 at 6:55 PM, Dylan Baker  wrote:

> by including the proper headers for getpid and for mkdir.
> ---
>  src/gallium/auxiliary/driver_ddebug/dd_util.h | 6 +-
>  src/gallium/auxiliary/meson.build | 6 ++
>  2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/driver_ddebug/dd_util.h
> b/src/gallium/auxiliary/driver_ddebug/dd_util.h
> index 8953e34d588..bcf026f2ef9 100644
> --- a/src/gallium/auxiliary/driver_ddebug/dd_util.h
> +++ b/src/gallium/auxiliary/driver_ddebug/dd_util.h
> @@ -37,9 +37,13 @@
>  #include "util/u_debug.h"
>
>  #include "pipe/p_config.h"
> -#ifdef PIPE_OS_UNIX
> +#if defined(PIPE_OS_UNIX)
>  #include 
>  #include 
> +#elif defined(PIPE_OS_WINDOWS)
> +#include 
> +#include 
> +#define mkdir(dir, mode) _mkdir(dir)
>  #endif
>
>
> diff --git a/src/gallium/auxiliary/meson.build
> b/src/gallium/auxiliary/meson.build
> index 92cfb8f7af5..48f3ef9b8ea 100644
> --- a/src/gallium/auxiliary/meson.build
> +++ b/src/gallium/auxiliary/meson.build
> @@ -106,6 +106,12 @@ files_libgallium = files(
>'driver_trace/tr_screen.h',
>'driver_trace/tr_texture.c',
>'driver_trace/tr_texture.h',
> +  'driver_ddebug/dd_context.c',
> +  'driver_ddebug/dd_draw.c',
> +  'driver_ddebug/dd_pipe.h',
> +  'driver_ddebug/dd_public.h',
> +  'driver_ddebug/dd_screen.c',
> +  'driver_ddebug/dd_util.h',
>'hud/font.c',
>'hud/font.h',
>'hud/hud_context.c',
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH mesa 01/21] vulkan: Add KHR_display extension using DRM [v4]

[Keith Packard]

Jason Ekstrand  writes:

> Sorry for the multitude of replies. :-(

It's all the same to me; you've been busy!

>>radv_wsi_proc_addr,
>> -  &physical_device->instance->alloc);
>> +  &physical_device->instance->alloc,
>> +  physical_device->master_fd);
>>
>
> We can just pass -1 in here and move the rest of the anv/radv stuff into
> patches 1 and 2.  That would make 1 and 2 a bit easier to review but it
> doesn't really matter now that I've found this bit of code. :)

I don't quite understand, but if you think the series is OK as-is, I'm
going to leave it.

-- 
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Re: [Mesa-dev] [PATCH mesa 01/21] vulkan: Add KHR_display extension using DRM [v4]

[Keith Packard]

Jason Ekstrand  writes:

> If you move the VK_OUTARRAY_MAKE up higher, both of the "goto bail"s can be
> "return vk_outarray_status(&conn)".  Not a big deal though; what you have
> is probably fine.

I'll leave it then.

>> +prop->currentStackIndex = stack_index++;
>>
>
> In your branch, this is 0.  Why the change?

I was doing it wrong -- this value shows the stacking order of the
plane within the connector. As I'm only (currently) listing a single
plane per connector, each one is on the top (and bottom) of the stack,
hence the constant value.

>> +prop->currentDisplay = NULL;
>>
>
> This should probably be VK_NULL_HANDLE

Yeah, compiling on 32-bits caught this with a compiler warning. Fixed.

>> +  vk_outarray_append(&conn, present) {
>> + *present = available_present_modes[c];
>> +  }
>> +   }
>>
>
> I don't think the array is helpful here.  We can just do a
> vk_outarray_append with FIFO and call it good.  If anything, it's probably
> worse since other present modes will probably be dependent on things such
> as whether or not the driver exposes ASYNC.

Good point. I had listed MAILBOX originally, but until the kernel
actually supports replacing a queued buffer, it's kinda lying to report
that on any DRM-based system, so I removed it.

> This may overflow if the provide a large value that is not UINT64_MAX.  We
> should do something such as
>
> uint64_t current = wsi_get_current_monotonic();
> if (timeout + current < timeout)
>timeout = UINT64_MAX;
> else
>timeout += current;

Yeah, they could well pass something ridiculous and we might as well
deal with it correctly. I've adapted similar code from the radv driver
instead of the above though; trusting the compiler to actually treat
integers as a finite field has bitten me in the past.

static uint64_t wsi_rel_to_abs_time(uint64_t rel_time)
{
   uint64_t current_time = wsi_get_current_monotonic();

   /* check for overflow */
   if (rel_time > UINT64_MAX - current_time)
  return UINT64_MAX;

   return current_time + rel_time;
}

> This could be crtc_id && wsi_display_crtc_solo(...)

Yes, but the formatting actually looks a bit cleaner this way to me;
with both tests in the same if, the line is too long and you need to
wrap the expression.

>> +   if (wsi->fd < 0)
>> +  return VK_ERROR_INITIALIZATION_FAILED;
>>
>
> Is this even possible?  I don't think it is.  If it isn't, maybe an assert
> would be better?  If it is, it should be VK_ERROR_OUT_OF_DATE_KHR.

I think it is possible - the application might have released the display
before cleaning up the swapchain. OUT_OF_DATE seems right to me; the
application would need to re-acquire the display and then re-create the
swapchain to get back to working.

>> +if (result != VK_SUCCESS) {
>> +   image->state = WSI_IMAGE_IDLE;
>>
>
> Would QUEUED be more appropreate here?  wsi_display_setup_connector will
> have returned either OUT_OF_MEMORY or OUT_OF_DATE so it probably doesn't
> matter.  I guess that begs the question, why are we even bothering to mess
> around with the image's state?

QUEUED would mean that the image was still waiting to be displayed, and
I think the correct result here is to abandon attempts to display this
image, so I mark the image as IDLE.


> If ret != 0, we continue on and go around the loop again and we try inside
> the "if (connector->active)" block.  It seems like we can get into an
> infinite loop if drmModeSetCrtc keeps returning -EINVAL.  At some point,
> don't we want ot throw OUT_OF_DATE and bail?

Good catch. The drmModeSetCrtc "should" never return -EINVAL as we're
careful to pick only a valid configuration, but of course there's no
trusting the kernel to not have some other random problem.

The idea is that drmModePageFlip may return -EINVAL if something has
changed in the configuration (like DPMS off, or VT switch), and in that
case (and in the case of having not set a mode yet), we want to do the
mode set instead.

If the mode set fails with EACCES, then we need to wait for the VT to
become active again (done by polling once a second).

If the mode set fails for any other reason, then I think we just want to
give up and report an error back to the client. Something bad happened.

So, now the code looks like this:

ret = page_flip
if (ret == 0) {
image->state = FLIPPING;
return success
}

if (ret == -EINVAL) {
ret = mode_set
if (ret == 0) {
image->state = DISPLAYING;
return success;
}
}
if (ret != -EACCES) {
give up!

> Again, why are we setting it to IDLE instead of leaving it in QUEUED?  This
> doesn't seem to do anything useful.

It doesn't really matter -- the swapchain is probably broken at this
point anyways. I set it to idle because this way the system doesn't even
bother to try to display it again.

Re: [Mesa-dev] [PATCH 2/2] nir: add lowering for gl_HelperInvocation

[Roland Scheidegger]

Am 12.06.2018 um 01:17 schrieb Rob Clark:
> On Mon, Jun 11, 2018 at 6:59 PM, Roland Scheidegger  
> wrote:
>> Am 12.06.2018 um 00:32 schrieb Jason Ekstrand:
>>> On Wed, Jun 6, 2018 at 7:43 AM, Rob Clark >> > wrote:
>>>
>>> Signed-off-by: Rob Clark >> >
>>> ---
>>> I can't say for sure that this will work on all drivers, but it is
>>> what the blob driver does, and it seems to make deqp happy.  I could
>>> move this to it's own pass inside ir3, but that seemed like overkill
>>>
>>>  src/compiler/nir/nir.h  | 10 ++
>>>  src/compiler/nir/nir_lower_system_values.c  | 17 +
>>>  src/gallium/drivers/freedreno/ir3/ir3_nir.c |  1 +
>>>  3 files changed, 28 insertions(+)
>>>
>>> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
>>> index 073ab4e82ea..de3d55d83af 100644
>>> --- a/src/compiler/nir/nir.h
>>> +++ b/src/compiler/nir/nir.h
>>> @@ -1963,6 +1963,16 @@ typedef struct nir_shader_compiler_options {
>>>  */
>>> bool lower_base_vertex;
>>>
>>> +   /**
>>> +* If enabled, gl_HelperInvocation will be lowered as:
>>> +*
>>> +*   !((1 << gl_SampleID) & gl_SampleMaskIN[0]))
>>>
>>>
>>> This only works for multi-sampling.  What about the single-sampled case?
>> It doesn't make sense to me for msaa neither.
>> gl_SampleID forces per-sample execution, which clearly isn't what you
>> want.
> 
> open to suggestions about how to try and force blob to do something
> different.. I tried a few things and the blob popped out shader code
> that worked the same way in all cases, but ofc I could have missed
> something.
> 
>> Plus, gl_SampleMaskIN is specified to only contain bits for the
>> current shader invocation, so for msaa with forced per-sample execution
>> that would only contain the single bit corresponding to gl_SampleID
>> anyway (that is my interpretation at least - I know hw sample mask
>> inputs will probably always contains all the bits from rasterization,
>> regardless of gl_SampleID), so the "1 << gl_SampleID &" part will do
>> nothing at all. So I think that part is more about lowering the hw
>> rasterization sample mask to gl_SampleMaskIN rather than lowering to
>> gl_HelperInvocation.
>> But yes, !gl_SampleMaskIN should give gl_HelperInvocation - I think all
>> hw can give you raster sample mask even without msaa but I'm not
>> entirely sure if it's guaranteed to work in GL with single sampling
>> (similar for sample id, which should just be stuck at 0). But using the
>> gl names here looks very, very fishy to me here.
> 
> I *guess* this is relying on behaviour that gl does not guarantee, but
> also doesn't prohibit, but the hw happens work that way and it works
> out..
> 
> Maybe the answer is to simply better document the assumptions that
> this lowering depends on?
Well I think if you have a nir shader which uses sample id but is
supposed to not be run per-sample that is quite confusing (I'd just
assume that adrenos will use sample id 0 just like in single sampled
case). Hopefully noone will deduce shader frequency from the nir shader...
I'm definitely no NIR expert but there's quite a lot of hacky
assumptions in there:
- sample id in nir doesn't cause per-sample execution (and needs to be 0
in case of msaa but no per-sample execution)
- sampleMaskIn is available in single-sampled
- sampleMaskIn doesn't actually have gl semantics but hw ones (so simply
the mask from rasterization, not taking into account the sample id
already if there's per-sample execution (for legitimate reasons),
although as mentioned I think there's still some debate about this and
not all drivers may actually agree what the semantics of it are in case
of per-sample execution)

As such I'm not sure it really makes sense to do that as a generic
lowering pass? Albeit you're quite right that it might work for a lot of
hw... But some comments would at the very least imho definitely be required.

Roland



> 
> BR,
> -R
> 
>>
>> Roland
>>
>>
>>
>>
>>>
>>> --Jason
>>>
>>>
>>>
>>> +*
>>> +* TODO any hw w/ more than 32 samples?  For them (if they
>>> +* used this option), a bit more math would be involved.
>>> +*/
>>> +   bool lower_helper_invocation;
>>> +
>>> bool lower_cs_local_index_from_id;
>>>
>>> bool lower_device_index_to_zero;
>>> diff --git a/src/compiler/nir/nir_lower_system_values.c
>>> b/src/compiler/nir/nir_lower_system_values.c
>>> index 487da042620..6668cbb5dcd 100644
>>> --- a/src/compiler/nir/nir_lower_system_values.c
>>> +++ b/src/compiler/nir/nir_lower_system_values.c
>>> @@ -136,6 +136,23 @@ convert_block(nir_block *block, nir_builder *b)
>>>nir_load_first_vertex(b));
>>>   break;
>>>
>>> +  case SYSTEM_VALUE_HELPER_INVOCATION:
>>> + if (b->shader->options->lower_hel

Re: [Mesa-dev] [PATCH mesa 01/21] vulkan: Add KHR_display extension using DRM [v4]

[Keith Packard]

Jason Ekstrand  writes:

> I apologize for how nit-picky this is going to get but it's starting to
> bother me...

I'm glad you showed me what you wanted; always nice to have help! I've
reformatted and restructured the code along the lines that you've
suggested here for the entire series. In particular:

 * 80 column limit. Just make it work.
 * Declare variables at first use; loop control variables inside the
   loop
 * Add the nice list iterators and use list_ versions of the list macros

I think this touched pretty much every patch in the series, but the
result is more consistent looking, and doesn't require a 200 column
emacs window to see the code.

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[Mesa-dev] [PATCH 09/23] intel/eu: Use descriptor constructors for pixel interpolator messages.

[Francisco Jerez]

---
 src/intel/compiler/brw_eu.h  | 12 
 src/intel/compiler/brw_eu_emit.c | 23 ++-
 2 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index f595f5c6726..230be6026be 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -340,6 +340,18 @@ brw_dp_write_desc(const struct gen_device_info *devinfo,
   send_commit_msg << 15);
 }
 
+/**
+ * Construct a message descriptor immediate with the specified pixel
+ * interpolator function controls.
+ */
+static inline uint32_t
+brw_pixel_interp_desc(const struct gen_device_info *devinfo,
+  unsigned msg_type,
+  bool noperspective,
+  unsigned simd_mode) {
+   return msg_type << 12 | !!noperspective << 14 | simd_mode << 16;
+}
+
 void brw_urb_WRITE(struct brw_codegen *p,
   struct brw_reg dest,
   unsigned msg_reg_nr,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index b931d87ccfa..6446a6eaa53 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3253,24 +3253,21 @@ brw_pixel_interpolator_query(struct brw_codegen *p,
  unsigned response_length)
 {
const struct gen_device_info *devinfo = p->devinfo;
-   struct brw_inst *insn;
const uint16_t exec_size = brw_get_default_exec_size(p);
+   const unsigned simd_mode = (exec_size == BRW_EXECUTE_16);
+   const unsigned desc =
+  brw_message_desc(devinfo, msg_length, response_length, false) |
+  brw_pixel_interp_desc(devinfo, mode, noperspective, simd_mode);
 
/* brw_send_indirect_message will automatically use a direct send message
 * if data is actually immediate.
 */
-   insn = brw_send_indirect_message(p,
-GEN7_SFID_PIXEL_INTERPOLATOR,
-dest,
-mrf,
-vec1(data), 0);
-   brw_inst_set_mlen(devinfo, insn, msg_length);
-   brw_inst_set_rlen(devinfo, insn, response_length);
-
-   brw_inst_set_pi_simd_mode(devinfo, insn, exec_size == BRW_EXECUTE_16);
-   brw_inst_set_pi_slot_group(devinfo, insn, 0); /* zero unless 32/64px 
dispatch */
-   brw_inst_set_pi_nopersp(devinfo, insn, noperspective);
-   brw_inst_set_pi_message_type(devinfo, insn, mode);
+   brw_send_indirect_message(p,
+ GEN7_SFID_PIXEL_INTERPOLATOR,
+ dest,
+ mrf,
+ vec1(data),
+ desc);
 }
 
 void
-- 
2.16.1

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[Mesa-dev] [PATCH 05/23] intel/eu: Provide desc immediate argument up front to brw_send_indirect_message().

[Francisco Jerez]

The current approach of returning a setup instruction where additional
descriptor fields can be specified is still supported in order to keep
things working, but it will be removed later in this series.
---
 src/intel/compiler/brw_eu.h   |  3 ++-
 src/intel/compiler/brw_eu_emit.c  | 11 ++-
 src/intel/compiler/brw_fs_generator.cpp   |  6 +++---
 src/intel/compiler/brw_vec4_generator.cpp |  4 ++--
 4 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index b2b20713e45..dc7cb500137 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -324,7 +324,8 @@ brw_send_indirect_message(struct brw_codegen *p,
   unsigned sfid,
   struct brw_reg dst,
   struct brw_reg payload,
-  struct brw_reg desc);
+  struct brw_reg desc,
+  unsigned desc_imm);
 
 void brw_ff_sync(struct brw_codegen *p,
   struct brw_reg dest,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 9f449fb9d34..2d7d8c61927 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2525,7 +2525,8 @@ brw_send_indirect_message(struct brw_codegen *p,
   unsigned sfid,
   struct brw_reg dst,
   struct brw_reg payload,
-  struct brw_reg desc)
+  struct brw_reg desc,
+  unsigned desc_imm)
 {
const struct gen_device_info *devinfo = p->devinfo;
struct brw_inst *send;
@@ -2544,7 +2545,7 @@ brw_send_indirect_message(struct brw_codegen *p,
if (desc.file == BRW_IMMEDIATE_VALUE) {
   setup = p->nr_insn;
   send = next_insn(p, BRW_OPCODE_SEND);
-  brw_set_src1(p, send, desc);
+  brw_set_desc(p, send, desc.ud | desc_imm);
 
} else {
   struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD);
@@ -2560,7 +2561,7 @@ brw_send_indirect_message(struct brw_codegen *p,
* brw_set_*_message() helper functions.
*/
   setup = p->nr_insn;
-  brw_OR(p, addr, desc, brw_imm_ud(0));
+  brw_OR(p, addr, desc, brw_imm_ud(desc_imm));
 
   brw_pop_insn_state(p);
 
@@ -2613,7 +2614,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
   surface = addr;
}
 
-   insn = brw_send_indirect_message(p, sfid, dst, payload, surface);
+   insn = brw_send_indirect_message(p, sfid, dst, payload, surface, 0);
brw_inst_set_mlen(devinfo, insn, message_len);
brw_inst_set_rlen(devinfo, insn, response_len);
brw_inst_set_header_present(devinfo, insn, header_present);
@@ -3370,7 +3371,7 @@ brw_pixel_interpolator_query(struct brw_codegen *p,
 GEN7_SFID_PIXEL_INTERPOLATOR,
 dest,
 mrf,
-vec1(data));
+vec1(data), 0);
brw_inst_set_mlen(devinfo, insn, msg_length);
brw_inst_set_rlen(devinfo, insn, response_length);
 
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 09839d0b4da..2f6258977dc 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1184,7 +1184,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
 
   /* dst = send(offset, a0.0 | ) */
   brw_inst *insn = brw_send_indirect_message(
- p, BRW_SFID_SAMPLER, dst, src, addr);
+ p, BRW_SFID_SAMPLER, dst, src, addr, 0);
   brw_set_sampler_message(p, insn,
   0 /* surface */,
   0 /* sampler */,
@@ -1453,7 +1453,7 @@ 
fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
   brw_inst *insn = brw_send_indirect_message(
  p, GEN6_SFID_DATAPORT_CONSTANT_CACHE,
  retype(dst, BRW_REGISTER_TYPE_UD),
- retype(payload, BRW_REGISTER_TYPE_UD), addr);
+ retype(payload, BRW_REGISTER_TYPE_UD), addr, 0);
   brw_set_dp_read_message(p, insn, 0 /* surface */,
   BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size),
   GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
@@ -1589,7 +1589,7 @@ 
fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
   /* dst = send(offset, a0.0 | ) */
   brw_inst *insn = brw_send_indirect_message(
  p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
- offset, addr);
+ offset, addr, 0);
   brw_set_sampler_message(p, insn,
   0 /* surface */,
   0 /* sampler */,
diff --git a/src/intel/compiler/brw_vec4_generator.cpp 
b/src/intel/compiler/brw_vec4_generator.cpp
inde

[Mesa-dev] [PATCH 23/23] intel/fs: Handle FS_OPCODE_REP_FB_WRITE in implied_mrf_writes().

[Francisco Jerez]

It can have implied MRF writes ATM.
---
 src/intel/compiler/brw_fs.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 314d580cc1f..4625ddc723c 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -1010,6 +1010,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst) const
case SHADER_OPCODE_SAMPLEINFO:
   return 1;
case FS_OPCODE_FB_WRITE:
+   case FS_OPCODE_REP_FB_WRITE:
   return 2;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case SHADER_OPCODE_GEN4_SCRATCH_READ:
-- 
2.16.1

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[Mesa-dev] [PATCH 14/23] intel/eu: Get rid of the return value of brw_send_indirect_surface_message().

[Francisco Jerez]

All users of brw_send_indirect_surface_message() should be providing a
full descriptor immediate up front by now, this isn't necessary
anymore.
---
 src/intel/compiler/brw_eu_emit.c | 16 ++--
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index f414a5753f6..e36cdadc70a 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2475,7 +2475,7 @@ brw_send_indirect_message(struct brw_codegen *p,
return &p->store[setup];
 }
 
-static struct brw_inst *
+static void
 brw_send_indirect_surface_message(struct brw_codegen *p,
   unsigned sfid,
   struct brw_reg dst,
@@ -2483,8 +2483,6 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
   struct brw_reg surface,
   unsigned desc_imm)
 {
-   struct brw_inst *insn;
-
if (surface.file != BRW_IMMEDIATE_VALUE) {
   struct brw_reg addr = retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD);
 
@@ -2497,19 +2495,17 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
   /* Mask out invalid bits from the surface index to avoid hangs e.g. when
* some surface array is accessed out of bounds.
*/
-  insn = brw_AND(p, addr,
- suboffset(vec1(retype(surface, BRW_REGISTER_TYPE_UD)),
-   BRW_GET_SWZ(surface.swizzle, 0)),
- brw_imm_ud(0xff));
+  brw_AND(p, addr,
+  suboffset(vec1(retype(surface, BRW_REGISTER_TYPE_UD)),
+BRW_GET_SWZ(surface.swizzle, 0)),
+  brw_imm_ud(0xff));
 
   brw_pop_insn_state(p);
 
   surface = addr;
}
 
-   insn = brw_send_indirect_message(p, sfid, dst, payload, surface, desc_imm);
-
-   return insn;
+   brw_send_indirect_message(p, sfid, dst, payload, surface, desc_imm);
 }
 
 static bool
-- 
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[Mesa-dev] [PATCH 20/23] intel/eu: Rework opcode description tables to allow efficient look-up by either HW or IR opcode.

[Francisco Jerez]

This rewrites the current opcode description tables as a more compact
flat data structure.  The purpose is to allow efficient constant-time
look-up by either HW or IR opcode, which will allow us to drop the
hard-coded correspondence between HW and IR opcodes -- See the next
commits for the rationale.

brw_eu.c is now built as C++ source so we can take advantage of
pointers to member in order to make the look-up function work
regardless of the opcode_desc member used as look-up key.
---
 src/intel/Makefile.sources  |   2 +-
 src/intel/Makefile.tools.am |   4 +
 src/intel/compiler/{brw_eu.c => brw_eu.cpp} | 414 ++--
 src/intel/compiler/brw_eu.h |  43 +--
 src/intel/compiler/brw_eu_defines.h |   4 +-
 src/intel/compiler/meson.build  |   2 +-
 6 files changed, 170 insertions(+), 299 deletions(-)
 rename src/intel/compiler/{brw_eu.c => brw_eu.cpp} (57%)

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index f22e727553f..33fdf4a26c7 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -43,7 +43,7 @@ COMPILER_FILES = \
compiler/brw_disasm.c \
compiler/brw_disasm_info.c \
compiler/brw_disasm_info.h \
-   compiler/brw_eu.c \
+   compiler/brw_eu.cpp \
compiler/brw_eu_compact.c \
compiler/brw_eu_defines.h \
compiler/brw_eu_emit.c \
diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index b00cc8cc2cb..4f2027cdfd6 100644
--- a/src/intel/Makefile.tools.am
+++ b/src/intel/Makefile.tools.am
@@ -27,6 +27,8 @@ tools_aubinator_SOURCES = \
tools/aubinator.c \
tools/intel_aub.h
 
+nodist_EXTRA_tools_aubinator_SOURCES = dummy.cpp
+
 tools_aubinator_CFLAGS = \
$(AM_CFLAGS) \
$(ZLIB_CFLAGS)
@@ -47,6 +49,8 @@ tools_aubinator_LDADD = \
 tools_aubinator_error_decode_SOURCES = \
tools/aubinator_error_decode.c
 
+nodist_EXTRA_tools_aubinator_error_decode_SOURCES = dummy.cpp
+
 tools_aubinator_error_decode_LDADD = \
common/libintel_common.la \
compiler/libintel_compiler.la \
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.cpp
similarity index 57%
rename from src/intel/compiler/brw_eu.c
rename to src/intel/compiler/brw_eu.cpp
index 80f05240b42..37375005daa 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.cpp
@@ -406,263 +406,87 @@ enum gen {
 #define GEN_GE(gen) (~GEN_LT(gen))
 #define GEN_LE(gen) (GEN_LT(gen) | (gen))
 
-static const struct opcode_desc opcode_10_descs[] = {
-   { .name = "dim",   .nsrc = 1, .ndst = 1, .gens = GEN75 },
-   { .name = "smov",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
-};
-
-static const struct opcode_desc opcode_35_descs[] = {
-   { .name = "iff",   .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
-   { .name = "brc",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7) },
-};
-
-static const struct opcode_desc opcode_38_descs[] = {
-   { .name = "do",.nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
-   { .name = "case",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
-};
-
-static const struct opcode_desc opcode_44_descs[] = {
-   { .name = "msave", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
-   { .name = "call",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
-};
-
-static const struct opcode_desc opcode_45_descs[] = {
-   { .name = "mrest", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
-   { .name = "ret",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
-};
-
-static const struct opcode_desc opcode_46_descs[] = {
-   { .name = "push",  .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
-   { .name = "fork",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
-   { .name = "goto",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
-};
-
-static const struct opcode_desc opcode_descs[128] = {
-   [BRW_OPCODE_ILLEGAL] = {
-  .name = "illegal", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
-   },
-   [BRW_OPCODE_MOV] = {
-  .name = "mov", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
-   },
-   [BRW_OPCODE_SEL] = {
-  .name = "sel", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
-   },
-   [BRW_OPCODE_MOVI] = {
-  .name = "movi",.nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
-   },
-   [BRW_OPCODE_NOT] = {
-  .name = "not", .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
-   },
-   [BRW_OPCODE_AND] = {
-  .name = "and", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
-   },
-   [BRW_OPCODE_OR] = {
-  .name = "or",  .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
-   },
-   [BRW_OPCODE_XOR] = {
-  .name = "xor", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
-   },
-   [BRW_OPCODE_SHR] = {
-  .name = "shr", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
-   },
-   [BRW_OPCODE_SHL] = {
-  .name = "shl", .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
-   },
-   [10] = {
-  .table = opcode_10_descs, .size = ARRAY_SIZE(opcode_10_descs),
-   },
-   /* Reserved - 11 */
-   [BRW_OPCODE_ASR] = {
-  .name = "asr", .nsrc = 2, .ndst

[Mesa-dev] [PATCH 03/23] intel/eu: Use brw_set_desc() along with a helper to set common descriptor controls.

[Francisco Jerez]

This replaces brw_set_message_descriptor() with the composition of
brw_set_desc() and a new inline helper function that packs the common
message descriptor controls into an integer.  The goal is to represent
all message descriptors as a 32-bit integer which is written at once
into the instruction, which is more flexible (SENDS anyone?), robust
(see d2eecf0b0b24d203d0f171807681dffd830d54de fixing an issue
ultimately caused by some bits of the extended message descriptor
being left undefined) and future-proof than the current approach of
specifying the individual descriptor fields directly into the
instruction.

This approach also seems more self-documenting, since it will allow
removing calls to functions with way too many arguments like
brw_set_*_message() and brw_send_indirect_message(), and instead
provide a single descriptor argument constructed from an appropriate
combination of brw_*_desc() helpers.

Note that because brw_set_message_descriptor() was (conditionally?)
overriding fields of the instruction which strictly speaking weren't
part of the message descriptor, this involves calling
brw_inst_set_sfid() and brw_inst_set_eot() in some cases in addition
to brw_set_desc().
---
 src/intel/compiler/brw_eu.h   |  29 +---
 src/intel/compiler/brw_eu_emit.c  | 108 +++---
 src/intel/compiler/brw_vec4_generator.cpp |  17 +++--
 3 files changed, 68 insertions(+), 86 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 5a396339fde..b2b20713e45 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -256,14 +256,6 @@ void brw_set_sampler_message(struct brw_codegen *p,
  unsigned simd_mode,
  unsigned return_format);
 
-void brw_set_message_descriptor(struct brw_codegen *p,
-brw_inst *inst,
-enum brw_message_target sfid,
-unsigned msg_length,
-unsigned response_length,
-bool header_present,
-bool end_of_thread);
-
 void brw_set_dp_read_message(struct brw_codegen *p,
 brw_inst *insn,
 unsigned binding_table_index,
@@ -287,6 +279,27 @@ void brw_set_dp_write_message(struct brw_codegen *p,
  unsigned end_of_thread,
  unsigned send_commit_msg);
 
+/**
+ * Construct a message descriptor immediate with the specified common
+ * descriptor controls.
+ */
+static inline uint32_t
+brw_message_desc(const struct gen_device_info *devinfo,
+ unsigned msg_length,
+ unsigned response_length,
+ bool header_present)
+{
+   if (devinfo->gen >= 5) {
+  return (msg_length << 25 |
+  response_length << 20 |
+  header_present << 19);
+   } else {
+  return (msg_length << 20 |
+  response_length << 16);
+   }
+}
+
+
 void brw_urb_WRITE(struct brw_codegen *p,
   struct brw_reg dest,
   unsigned msg_reg_nr,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ab9af718152..7389e8e3bde 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -359,48 +359,6 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct 
brw_reg reg)
}
 }
 
-/**
- * Set the Message Descriptor and Extended Message Descriptor fields
- * for SEND messages.
- *
- * \note This zeroes out the Function Control bits, so it must be called
- *   \b before filling out any message-specific data.  Callers can
- *   choose not to fill in irrelevant bits; they will be zero.
- */
-void
-brw_set_message_descriptor(struct brw_codegen *p,
-  brw_inst *inst,
-  enum brw_message_target sfid,
-  unsigned msg_length,
-  unsigned response_length,
-  bool header_present,
-  bool end_of_thread)
-{
-   const struct gen_device_info *devinfo = p->devinfo;
-
-   brw_set_src1(p, inst, brw_imm_d(0));
-
-   /* For indirect sends, `inst` will not be the SEND/SENDC instruction
-* itself; instead, it will be a MOV/OR into the address register.
-*
-* In this case, we avoid setting the extended message descriptor bits,
-* since they go on the later SEND/SENDC instead and if set here would
-* instead clobber the conditionalmod bits.
-*/
-   unsigned opcode = brw_inst_opcode(devinfo, inst);
-   if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
-  brw_inst_set_sfid(devinfo, inst, sfid);
-   }
-
-   brw_inst_set_mlen(devinfo, inst, msg_length);
-   brw_inst_set_rlen(devinfo, inst, response_length);
-   brw_inst_set_eot(devinfo, inst, end_of_thread);
-
-   if (devi

[Mesa-dev] [PATCH 16/23] intel/eu: Assert that the instruction is send-like in brw_set_desc_ex().

[Francisco Jerez]

Constructing a descriptor in-place as part of the immediate of an ALU
instruction is no longer supported.
---
 src/intel/compiler/brw_eu_emit.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 86c5c4bb3d2..9649ee00b07 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -368,11 +368,12 @@ brw_set_desc_ex(struct brw_codegen *p, brw_inst *inst,
 unsigned desc, unsigned ex_desc)
 {
const struct gen_device_info *devinfo = p->devinfo;
+   assert(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
+  brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC);
brw_inst_set_src1_file_type(devinfo, inst,
BRW_IMMEDIATE_VALUE, BRW_REGISTER_TYPE_D);
brw_inst_set_send_desc(devinfo, inst, desc);
-   if (devinfo->gen >= 9 && (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND 
||
- brw_inst_opcode(devinfo, inst) == 
BRW_OPCODE_SENDC))
+   if (devinfo->gen >= 9)
   brw_inst_set_send_ex_desc(devinfo, inst, ex_desc);
 }
 
-- 
2.16.1

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[Mesa-dev] [PATCH 12/23] intel/eu: Use descriptor constructors for dataport scattered byte surface messages.

[Francisco Jerez]

---
 src/intel/compiler/brw_eu_emit.c | 60 ++--
 1 file changed, 27 insertions(+), 33 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index c1a1004c033..cdf839d3053 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2919,6 +2919,21 @@ brw_byte_scattered_data_element_from_bit_size(unsigned 
bit_size)
}
 }
 
+static uint32_t
+brw_dp_byte_scattered_desc(struct brw_codegen *p, unsigned bit_size,
+   unsigned msg_type)
+{
+   const struct gen_device_info *devinfo = p->devinfo;
+   unsigned msg_control =
+  brw_byte_scattered_data_element_from_bit_size(bit_size) << 2;
+
+   if (brw_get_default_exec_size(p) == BRW_EXECUTE_16)
+  msg_control |= 1; /* SIMD16 mode */
+   else
+  msg_control |= 0; /* SIMD8 mode */
+
+   return brw_dp_surface_desc(devinfo, msg_type, msg_control);
+}
 
 void
 brw_byte_scattered_read(struct brw_codegen *p,
@@ -2931,26 +2946,15 @@ brw_byte_scattered_read(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
assert(devinfo->gen > 7 || devinfo->is_haswell);
assert(brw_get_default_access_mode(p) == BRW_ALIGN_1);
-   const unsigned sfid =  GEN7_SFID_DATAPORT_DATA_CACHE;
const unsigned response_length =
   brw_surface_payload_size(p, 1, true, true);
const unsigned desc =
-  brw_message_desc(devinfo, msg_length, response_length, false);
-
-   struct brw_inst *insn = brw_send_indirect_surface_message(
-  p, sfid, dst, payload, surface, desc);
-
-   unsigned msg_control =
-  brw_byte_scattered_data_element_from_bit_size(bit_size) << 2;
-
-   if (brw_get_default_exec_size(p) == BRW_EXECUTE_16)
-  msg_control |= 1; /* SIMD16 mode */
-   else
-  msg_control |= 0; /* SIMD8 mode */
+  brw_message_desc(devinfo, msg_length, response_length, false) |
+  brw_dp_byte_scattered_desc(p, bit_size,
+ HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ);
 
-   brw_inst_set_dp_msg_type(devinfo, insn,
-HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ);
-   brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
+   brw_send_indirect_surface_message(p, GEN7_SFID_DATAPORT_DATA_CACHE,
+ dst, payload, surface, desc);
 }
 
 void
@@ -2964,25 +2968,15 @@ brw_byte_scattered_write(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
assert(devinfo->gen > 7 || devinfo->is_haswell);
assert(brw_get_default_access_mode(p) == BRW_ALIGN_1);
-   const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
const unsigned desc =
-  brw_message_desc(devinfo, msg_length, 0, header_present);
-
-   struct brw_inst *insn = brw_send_indirect_surface_message(
-  p, sfid, brw_writemask(brw_null_reg(), WRITEMASK_XYZW),
-  payload, surface, desc);
-
-   unsigned msg_control =
-  brw_byte_scattered_data_element_from_bit_size(bit_size) << 2;
-
-   if (brw_get_default_exec_size(p) == BRW_EXECUTE_16)
-  msg_control |= 1;
-   else
-  msg_control |= 0;
+  brw_message_desc(devinfo, msg_length, 0, header_present) |
+  brw_dp_byte_scattered_desc(p, bit_size,
+ HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE);
 
-   brw_inst_set_dp_msg_type(devinfo, insn,
-HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE);
-   brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
+   brw_send_indirect_surface_message(p, GEN7_SFID_DATAPORT_DATA_CACHE,
+ brw_writemask(brw_null_reg(),
+   WRITEMASK_XYZW),
+ payload, surface, desc);
 }
 
 static void
-- 
2.16.1

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[Mesa-dev] [PATCH 07/23] intel/eu: Use descriptor constructors for dataport read messages.

[Francisco Jerez]

---
 src/intel/compiler/brw_eu.h   | 33 +
 src/intel/compiler/brw_eu_emit.c  | 77 ++-
 src/intel/compiler/brw_fs_generator.cpp   | 32 ++---
 src/intel/compiler/brw_vec4_generator.cpp | 33 +++--
 4 files changed, 80 insertions(+), 95 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 94c005cde55..b31458e5636 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -245,16 +245,6 @@ ROUND(RNDE)
 
 /* Helpers for SEND instruction:
  */
-void brw_set_dp_read_message(struct brw_codegen *p,
-brw_inst *insn,
-unsigned binding_table_index,
-unsigned msg_control,
-unsigned msg_type,
-unsigned target_cache,
-unsigned msg_length,
- bool header_present,
-unsigned response_length);
-
 void brw_set_dp_write_message(struct brw_codegen *p,
  brw_inst *insn,
  unsigned binding_table_index,
@@ -312,6 +302,29 @@ brw_sampler_desc(const struct gen_device_info *devinfo,
   return desc | return_format << 12 | msg_type << 14;
 }
 
+/**
+ * Construct a message descriptor immediate with the specified dataport read
+ * function controls.
+ */
+static inline uint32_t
+brw_dp_read_desc(const struct gen_device_info *devinfo,
+ unsigned binding_table_index,
+ unsigned msg_control,
+ unsigned msg_type,
+ unsigned target_cache)
+{
+   const unsigned desc = (binding_table_index << 0 |
+  msg_control << 8);
+   if (devinfo->gen >= 7)
+  return desc | msg_type << 14;
+   else if (devinfo->gen >= 6)
+  return desc | msg_type << 13;
+   else if (devinfo->gen >= 5 || devinfo->is_g4x)
+  return desc | msg_type << 11 | target_cache << 14;
+   else
+  return desc | msg_type << 12 | target_cache << 14;
+}
+
 void brw_urb_WRITE(struct brw_codegen *p,
   struct brw_reg dest,
   unsigned msg_reg_nr,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 3e2af0d9c25..0287c1b5f0a 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -524,34 +524,6 @@ brw_set_dp_write_message(struct brw_codegen *p,
   brw_inst_set_null_rt(devinfo, insn, false);
 }
 
-void
-brw_set_dp_read_message(struct brw_codegen *p,
-   brw_inst *insn,
-   unsigned binding_table_index,
-   unsigned msg_control,
-   unsigned msg_type,
-   unsigned target_cache,
-   unsigned msg_length,
-bool header_present,
-   unsigned response_length)
-{
-   const struct gen_device_info *devinfo = p->devinfo;
-   const unsigned sfid = (devinfo->gen >= 6 ? target_cache :
-  BRW_SFID_DATAPORT_READ);
-
-   brw_set_desc(p, insn, brw_message_desc(
-   devinfo, msg_length, response_length, header_present));
-
-   const unsigned opcode = brw_inst_opcode(devinfo, insn);
-   if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC)
-  brw_inst_set_sfid(devinfo, insn, sfid);
-   brw_inst_set_binding_table_index(devinfo, insn, binding_table_index);
-   brw_inst_set_dp_read_msg_type(devinfo, insn, msg_type);
-   brw_inst_set_dp_read_msg_control(devinfo, insn, msg_control);
-   if (devinfo->gen < 6)
-  brw_inst_set_dp_read_target_cache(devinfo, insn, target_cache);
-}
-
 static void
 gen7_set_dp_scratch_message(struct brw_codegen *p,
 brw_inst *inst,
@@ -2104,7 +2076,7 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
const unsigned target_cache =
   (devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
-   BRW_DATAPORT_READ_TARGET_RENDER_CACHE);
+   BRW_SFID_DATAPORT_READ);
 
{
   brw_push_insn_state(p);
@@ -2124,6 +2096,7 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
{
   brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
 
+  brw_inst_set_sfid(devinfo, insn, target_cache);
   assert(brw_inst_pred_control(devinfo, insn) == 0);
   brw_inst_set_compression(devinfo, insn, false);
 
@@ -2135,15 +2108,12 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
  brw_inst_set_base_mrf(devinfo, insn, mrf.nr);
   }
 
-  brw_set_dp_read_message(p,
- insn,
-  brw_scratch_surface_idx(p),
- BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_regs * 8),
- BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* 
msg_type */
- targe

[Mesa-dev] [PATCH 15/23] intel/eu: Get rid of the return value of brw_send_indirect_message().

[Francisco Jerez]

The return value is not used anymore.  This allows simplifying the
code slightly, and in addition it should frustrate anybody's attempts
to continue using the obsolete piecemeal approach to construct a
message descriptor in combination with brw_send_indirect_message().
---
 src/intel/compiler/brw_eu.h  |  8 ++--
 src/intel/compiler/brw_eu_emit.c | 17 +++--
 2 files changed, 5 insertions(+), 20 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 05536c3aaff..7ffd3c30665 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -378,13 +378,9 @@ void brw_urb_WRITE(struct brw_codegen *p,
 /**
  * Send message to shared unit \p sfid with a possibly indirect descriptor \p
  * desc.  If \p desc is not an immediate it will be transparently loaded to an
- * address register using an OR instruction.  The returned instruction can be
- * passed as argument to the usual brw_set_*_message() functions in order to
- * specify any additional descriptor bits -- If \p desc is an immediate this
- * will be the SEND instruction itself, otherwise it will be the OR
- * instruction.
+ * address register using an OR instruction.
  */
-struct brw_inst *
+void
 brw_send_indirect_message(struct brw_codegen *p,
   unsigned sfid,
   struct brw_reg dst,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index e36cdadc70a..86c5c4bb3d2 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2416,7 +2416,7 @@ void brw_urb_WRITE(struct brw_codegen *p,
   swizzle);
 }
 
-struct brw_inst *
+void
 brw_send_indirect_message(struct brw_codegen *p,
   unsigned sfid,
   struct brw_reg dst,
@@ -2426,20 +2426,12 @@ brw_send_indirect_message(struct brw_codegen *p,
 {
const struct gen_device_info *devinfo = p->devinfo;
struct brw_inst *send;
-   int setup;
 
dst = retype(dst, BRW_REGISTER_TYPE_UW);
 
assert(desc.type == BRW_REGISTER_TYPE_UD);
 
-   /* We hold on to the setup instruction (the SEND in the direct case, the OR
-* in the indirect case) by its index in the instruction store.  The
-* pointer returned by next_insn() may become invalid if emitting the SEND
-* in the indirect case reallocs the store.
-*/
-
if (desc.file == BRW_IMMEDIATE_VALUE) {
-  setup = p->nr_insn;
   send = next_insn(p, BRW_OPCODE_SEND);
   brw_set_desc(p, send, desc.ud | desc_imm);
 
@@ -2453,10 +2445,9 @@ brw_send_indirect_message(struct brw_codegen *p,
   brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
 
   /* Load the indirect descriptor to an address register using OR so the
-   * caller can specify additional descriptor bits with the usual
-   * brw_set_*_message() helper functions.
+   * caller can specify additional descriptor bits with the desc_imm
+   * immediate.
*/
-  setup = p->nr_insn;
   brw_OR(p, addr, desc, brw_imm_ud(desc_imm));
 
   brw_pop_insn_state(p);
@@ -2471,8 +2462,6 @@ brw_send_indirect_message(struct brw_codegen *p,
brw_set_dest(p, send, dst);
brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
brw_inst_set_sfid(devinfo, send, sfid);
-
-   return &p->store[setup];
 }
 
 static void
-- 
2.16.1

___
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 13/23] intel/eu: Use descriptor constructors for dataport typed surface messages.

[Francisco Jerez]

---
 src/intel/compiler/brw_eu_emit.c | 82 +---
 1 file changed, 35 insertions(+), 47 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index cdf839d3053..f414a5753f6 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2979,38 +2979,35 @@ brw_byte_scattered_write(struct brw_codegen *p,
  payload, surface, desc);
 }
 
-static void
-brw_set_dp_typed_atomic_message(struct brw_codegen *p,
-struct brw_inst *insn,
-unsigned atomic_op,
-bool response_expected)
+static uint32_t
+brw_dp_typed_atomic_desc(struct brw_codegen *p,
+ unsigned atomic_op,
+ bool response_expected)
 {
const struct gen_device_info *devinfo = p->devinfo;
unsigned msg_control =
   atomic_op | /* Atomic Operation Type: BRW_AOP_* */
   (response_expected ? 1 << 5 : 0); /* Return data expected */
+   unsigned msg_type;
 
if (devinfo->gen >= 8 || devinfo->is_haswell) {
   if (brw_get_default_access_mode(p) == BRW_ALIGN_1) {
  if ((brw_get_default_group(p) / 8) % 2 == 1)
 msg_control |= 1 << 4; /* Use high 8 slots of the sample mask */
 
- brw_inst_set_dp_msg_type(devinfo, insn,
-  HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP);
+ msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
   } else {
- brw_inst_set_dp_msg_type(devinfo, insn,
-  
HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2);
+ msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
   }
 
} else {
-  brw_inst_set_dp_msg_type(devinfo, insn,
-   GEN7_DATAPORT_RC_TYPED_ATOMIC_OP);
-
   if ((brw_get_default_group(p) / 8) % 2 == 1)
  msg_control |= 1 << 4; /* Use high 8 slots of the sample mask */
+
+  msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
}
 
-   brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
+   return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 }
 
 void
@@ -3029,25 +3026,24 @@ brw_typed_atomic(struct brw_codegen *p,
const unsigned response_length = brw_surface_payload_size(
   p, response_expected, devinfo->gen >= 8 || devinfo->is_haswell, false);
const unsigned desc =
-  brw_message_desc(devinfo, msg_length, response_length, header_present);
+  brw_message_desc(devinfo, msg_length, response_length, header_present) |
+  brw_dp_typed_atomic_desc(p, atomic_op, response_expected);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* Mask out unused components -- See comment in brw_untyped_atomic(). */
const unsigned mask = align1 ? WRITEMASK_XYZW : WRITEMASK_X;
-   struct brw_inst *insn = brw_send_indirect_surface_message(
-  p, sfid, brw_writemask(dst, mask), payload, surface, desc);
 
-   brw_set_dp_typed_atomic_message(
-  p, insn, atomic_op, response_expected);
+   brw_send_indirect_surface_message(p, sfid, brw_writemask(dst, mask),
+ payload, surface, desc);
 }
 
-static void
-brw_set_dp_typed_surface_read_message(struct brw_codegen *p,
-  struct brw_inst *insn,
-  unsigned num_channels)
+static uint32_t
+brw_dp_typed_surface_read_desc(struct brw_codegen *p,
+   unsigned num_channels)
 {
const struct gen_device_info *devinfo = p->devinfo;
/* Set mask of unused channels. */
unsigned msg_control = 0xf & (0xf << num_channels);
+   unsigned msg_type;
 
if (devinfo->gen >= 8 || devinfo->is_haswell) {
   if (brw_get_default_access_mode(p) == BRW_ALIGN_1) {
@@ -3057,19 +3053,17 @@ brw_set_dp_typed_surface_read_message(struct 
brw_codegen *p,
 msg_control |= 1 << 4; /* Use low 8 slots of the sample mask */
   }
 
-  brw_inst_set_dp_msg_type(devinfo, insn,
-   HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ);
+  msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
} else {
   if (brw_get_default_access_mode(p) == BRW_ALIGN_1) {
  if ((brw_get_default_group(p) / 8) % 2 == 1)
 msg_control |= 1 << 5; /* Use high 8 slots of the sample mask */
   }
 
-  brw_inst_set_dp_msg_type(devinfo, insn,
-   GEN7_DATAPORT_RC_TYPED_SURFACE_READ);
+  msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
}
 
-   brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
+   return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 }
 
 void
@@ -3088,22 +3082,20 @@ brw_typed_surface_read(struct brw_codegen *p,
const unsigned response_length = brw_surface_payload_size(
   p, num_channels, devinfo->gen >= 8 || devinfo->is_haswell, false);
const unsigned desc =
-  brw_

[Mesa-dev] [PATCH 19/23] intel/eu: Fix up various type conversions in brw_eu.c that are illegal C++.

[Francisco Jerez]

---
 src/intel/compiler/brw_eu.c   | 12 ++--
 src/intel/compiler/brw_eu.h   |  6 +++---
 src/intel/compiler/brw_vec4_generator.cpp |  2 +-
 src/intel/compiler/test_eu_compact.cpp|  4 ++--
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index 6ef0a6a577c..80f05240b42 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -39,7 +39,7 @@
 
 /* Returns a conditional modifier that negates the condition. */
 enum brw_conditional_mod
-brw_negate_cmod(uint32_t cmod)
+brw_negate_cmod(enum brw_conditional_mod cmod)
 {
switch (cmod) {
case BRW_CONDITIONAL_Z:
@@ -55,7 +55,7 @@ brw_negate_cmod(uint32_t cmod)
case BRW_CONDITIONAL_LE:
   return BRW_CONDITIONAL_G;
default:
-  return ~0;
+  unreachable("Can't negate this cmod");
}
 }
 
@@ -63,7 +63,7 @@ brw_negate_cmod(uint32_t cmod)
  * src1 in e.g. CMP.
  */
 enum brw_conditional_mod
-brw_swap_cmod(uint32_t cmod)
+brw_swap_cmod(enum brw_conditional_mod cmod)
 {
switch (cmod) {
case BRW_CONDITIONAL_Z:
@@ -150,7 +150,7 @@ brw_set_default_exec_size(struct brw_codegen *p, unsigned 
value)
p->current->exec_size = value;
 }
 
-void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
+void brw_set_default_predicate_control(struct brw_codegen *p, enum 
brw_predicate pc)
 {
p->current->predicate = pc;
 }
@@ -356,14 +356,14 @@ brw_disassemble(const struct gen_device_info *devinfo,
bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
 
for (int offset = start; offset < end;) {
-  const brw_inst *insn = assembly + offset;
+  const brw_inst *insn = (const brw_inst *)((char *)assembly + offset);
   brw_inst uncompacted;
   bool compacted = brw_inst_cmpt_control(devinfo, insn);
   if (0)
  fprintf(out, "0x%08x: ", offset);
 
   if (compacted) {
- brw_compact_inst *compacted = (void *)insn;
+ brw_compact_inst *compacted = (brw_compact_inst *)insn;
 if (dump_hex) {
fprintf(out, "0x%08x 0x%08x   ",
((uint32_t *)insn)[1],
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 7ffd3c30665..0fc32ef0750 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -150,7 +150,7 @@ void brw_inst_set_group(const struct gen_device_info 
*devinfo,
 brw_inst *inst, unsigned group);
 void brw_set_default_group(struct brw_codegen *p, unsigned group);
 void brw_set_default_compression_control(struct brw_codegen *p, enum 
brw_compression c);
-void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc );
+void brw_set_default_predicate_control(struct brw_codegen *p, enum 
brw_predicate pc);
 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool 
predicate_inverse);
 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
@@ -686,8 +686,8 @@ brw_set_desc(struct brw_codegen *p, brw_inst *insn, 
unsigned desc)
 
 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
 
-enum brw_conditional_mod brw_negate_cmod(uint32_t cmod);
-enum brw_conditional_mod brw_swap_cmod(uint32_t cmod);
+enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod);
+enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
 
 /* brw_eu_compact.c */
 void brw_init_compaction_tables(const struct gen_device_info *devinfo);
diff --git a/src/intel/compiler/brw_vec4_generator.cpp 
b/src/intel/compiler/brw_vec4_generator.cpp
index d506b675776..8e08391fd5f 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -1192,7 +1192,7 @@ generate_scratch_write(struct brw_codegen *p,
/* If the instruction is predicated, we'll predicate the send, not
 * the header setup.
 */
-   brw_set_default_predicate_control(p, false);
+   brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
 
gen6_resolve_implied_move(p, &header, inst->base_mrf);
 
diff --git a/src/intel/compiler/test_eu_compact.cpp 
b/src/intel/compiler/test_eu_compact.cpp
index f6924abd368..702762c194a 100644
--- a/src/intel/compiler/test_eu_compact.cpp
+++ b/src/intel/compiler/test_eu_compact.cpp
@@ -243,7 +243,7 @@ gen_f0_0_MOV_GRF_GRF(struct brw_codegen *p)
struct brw_reg g2 = brw_vec8_grf(2, 0);
 
brw_push_insn_state(p);
-   brw_set_default_predicate_control(p, true);
+   brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_MOV(p, g0, g2);
brw_pop_insn_state(p);
 }
@@ -259,7 +259,7 @@ gen_f0_1_MOV_GRF_GRF(struct brw_codegen *p)
struct brw_reg g2 = brw_vec8_grf(2, 0);
 
brw_push_insn_state(p);
-   brw_set_default_predicate_control(p, true);
+   brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_inst *mov = brw_MOV(p, g0, g2);
brw_inst_

[Mesa-dev] [PATCH 18/23] intel/ir: Uncomment definition of several unused hardware opcodes.

[Francisco Jerez]

There are a number of opcode_desc table entries for many of these
unused opcodes.  A symbolic opcode enum will be required in a future
commit in order to keep them in the opcode description tables.  The
alternative would be to remove the unused opcodes from the opcode
description tables.
---
 src/intel/compiler/brw_eu_defines.h | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/intel/compiler/brw_eu_defines.h 
b/src/intel/compiler/brw_eu_defines.h
index ee306a6c2ce..a00f84ca681 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -200,7 +200,7 @@ enum opcode {
BRW_OPCODE_SHR =8,
BRW_OPCODE_SHL =9,
BRW_OPCODE_DIM =10,  /**< Gen7.5 only */ /* Reused */
-   // BRW_OPCODE_SMOV =10,  /**< Gen8+   */ /* Reused */
+   BRW_OPCODE_SMOV =   10,  /**< Gen8+   */ /* Reused */
/* Reserved - 11 */
BRW_OPCODE_ASR =12,
/* Reserved - 13-15 */
@@ -216,27 +216,27 @@ enum opcode {
BRW_OPCODE_BFI2 =   26,  /**< Gen7+ */
/* Reserved - 27-31 */
BRW_OPCODE_JMPI =   32,
-   // BRW_OPCODE_BRD = 33,  /**< Gen7+ */
+   BRW_OPCODE_BRD =33,  /**< Gen7+ */
BRW_OPCODE_IF = 34,
BRW_OPCODE_IFF =35,  /**< Pre-Gen6*/ /* Reused */
-   // BRW_OPCODE_BRC = 35,  /**< Gen7+   */ /* Reused */
+   BRW_OPCODE_BRC =35,  /**< Gen7+   */ /* Reused */
BRW_OPCODE_ELSE =   36,
BRW_OPCODE_ENDIF =  37,
BRW_OPCODE_DO = 38,  /**< Pre-Gen6*/ /* Reused */
-   // BRW_OPCODE_CASE =38,  /**< Gen6 only   */ /* Reused */
+   BRW_OPCODE_CASE =   38,  /**< Gen6 only   */ /* Reused */
BRW_OPCODE_WHILE =  39,
BRW_OPCODE_BREAK =  40,
BRW_OPCODE_CONTINUE = 41,
BRW_OPCODE_HALT =   42,
-   // BRW_OPCODE_CALLA =   43,  /**< Gen7.5+ */
-   // BRW_OPCODE_MSAVE =   44,  /**< Pre-Gen6*/ /* Reused */
-   // BRW_OPCODE_CALL =44,  /**< Gen6+   */ /* Reused */
-   // BRW_OPCODE_MREST =   45,  /**< Pre-Gen6*/ /* Reused */
-   // BRW_OPCODE_RET = 45,  /**< Gen6+   */ /* Reused */
-   // BRW_OPCODE_PUSH =46,  /**< Pre-Gen6*/ /* Reused */
-   // BRW_OPCODE_FORK =46,  /**< Gen6 only   */ /* Reused */
-   // BRW_OPCODE_GOTO =46,  /**< Gen8+   */ /* Reused */
-   // BRW_OPCODE_POP = 47,  /**< Pre-Gen6*/
+   BRW_OPCODE_CALLA =  43,  /**< Gen7.5+ */
+   BRW_OPCODE_MSAVE =  44,  /**< Pre-Gen6*/ /* Reused */
+   BRW_OPCODE_CALL =   44,  /**< Gen6+   */ /* Reused */
+   BRW_OPCODE_MREST =  45,  /**< Pre-Gen6*/ /* Reused */
+   BRW_OPCODE_RET =45,  /**< Gen6+   */ /* Reused */
+   BRW_OPCODE_PUSH =   46,  /**< Pre-Gen6*/ /* Reused */
+   BRW_OPCODE_FORK =   46,  /**< Gen6 only   */ /* Reused */
+   BRW_OPCODE_GOTO =   46,  /**< Gen8+   */ /* Reused */
+   BRW_OPCODE_POP =47,  /**< Pre-Gen6*/
BRW_OPCODE_WAIT =   48,
BRW_OPCODE_SEND =   49,
BRW_OPCODE_SENDC =  50,
@@ -273,7 +273,7 @@ enum opcode {
BRW_OPCODE_PLN =90,  /**< G45+ */
BRW_OPCODE_MAD =91,  /**< Gen6+ */
BRW_OPCODE_LRP =92,  /**< Gen6+ */
-   // BRW_OPCODE_MADM =93,  /**< Gen8+ */
+   BRW_OPCODE_MADM =   93,  /**< Gen8+ */
/* Reserved 94-124 */
BRW_OPCODE_NENOP =  125, /**< G45 only */
BRW_OPCODE_NOP =126,
-- 
2.16.1

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[Mesa-dev] [PATCH 10/23] intel/eu: Provide single descriptor argument to brw_send_indirect_surface_message().

[Francisco Jerez]

Instead of the current message_len, response_len and header_present
arguments.
---
 src/intel/compiler/brw_eu_emit.c | 65 ++--
 1 file changed, 36 insertions(+), 29 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 6446a6eaa53..e442827a634 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2481,11 +2481,8 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
   struct brw_reg dst,
   struct brw_reg payload,
   struct brw_reg surface,
-  unsigned message_len,
-  unsigned response_len,
-  bool header_present)
+  unsigned desc_imm)
 {
-   const struct gen_device_info *devinfo = p->devinfo;
struct brw_inst *insn;
 
if (surface.file != BRW_IMMEDIATE_VALUE) {
@@ -2510,10 +2507,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
   surface = addr;
}
 
-   insn = brw_send_indirect_message(p, sfid, dst, payload, surface, 0);
-   brw_inst_set_mlen(devinfo, insn, message_len);
-   brw_inst_set_rlen(devinfo, insn, response_len);
-   brw_inst_set_header_present(devinfo, insn, header_present);
+   insn = brw_send_indirect_message(p, sfid, dst, payload, surface, desc_imm);
 
return insn;
 }
@@ -2803,6 +2797,10 @@ brw_untyped_atomic(struct brw_codegen *p,
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
   HSW_SFID_DATAPORT_DATA_CACHE_1 :
   GEN7_SFID_DATAPORT_DATA_CACHE);
+   const unsigned response_length = brw_surface_payload_size(
+  p, response_expected, devinfo->gen >= 8 || devinfo->is_haswell, true);
+   const unsigned desc =
+  brw_message_desc(devinfo, msg_length, response_length, header_present);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* Mask out unused components -- This is especially important in Align16
 * mode on generations that don't have native support for SIMD4x2 atomics,
@@ -2812,10 +2810,7 @@ brw_untyped_atomic(struct brw_codegen *p,
 */
const unsigned mask = align1 ? WRITEMASK_XYZW : WRITEMASK_X;
struct brw_inst *insn = brw_send_indirect_surface_message(
-  p, sfid, brw_writemask(dst, mask), payload, surface, msg_length,
-  brw_surface_payload_size(p, response_expected,
-   devinfo->gen >= 8 || devinfo->is_haswell, true),
-  header_present);
+  p, sfid, brw_writemask(dst, mask), payload, surface, desc);
 
brw_set_dp_untyped_atomic_message(
   p, insn, atomic_op, response_expected);
@@ -2856,10 +2851,12 @@ brw_untyped_surface_read(struct brw_codegen *p,
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
   HSW_SFID_DATAPORT_DATA_CACHE_1 :
   GEN7_SFID_DATAPORT_DATA_CACHE);
+   const unsigned response_length =
+  brw_surface_payload_size(p, num_channels, true, true);
+   const unsigned desc =
+  brw_message_desc(devinfo, msg_length, response_length, false);
struct brw_inst *insn = brw_send_indirect_surface_message(
-  p, sfid, dst, payload, surface, msg_length,
-  brw_surface_payload_size(p, num_channels, true, true),
-  false);
+  p, sfid, dst, payload, surface, desc);
 
brw_set_dp_untyped_surface_read_message(
   p, insn, num_channels);
@@ -2905,13 +2902,15 @@ brw_untyped_surface_write(struct brw_codegen *p,
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
   HSW_SFID_DATAPORT_DATA_CACHE_1 :
   GEN7_SFID_DATAPORT_DATA_CACHE);
+   const unsigned desc =
+  brw_message_desc(devinfo, msg_length, 0, header_present);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* Mask out unused components -- See comment in brw_untyped_atomic(). */
const unsigned mask = devinfo->gen == 7 && !devinfo->is_haswell && !align1 ?
   WRITEMASK_X : WRITEMASK_XYZW;
struct brw_inst *insn = brw_send_indirect_surface_message(
   p, sfid, brw_writemask(brw_null_reg(), mask),
-  payload, surface, msg_length, 0, header_present);
+  payload, surface, desc);
 
brw_set_dp_untyped_surface_write_message(
   p, insn, num_channels);
@@ -2945,11 +2944,13 @@ brw_byte_scattered_read(struct brw_codegen *p,
assert(devinfo->gen > 7 || devinfo->is_haswell);
assert(brw_get_default_access_mode(p) == BRW_ALIGN_1);
const unsigned sfid =  GEN7_SFID_DATAPORT_DATA_CACHE;
+   const unsigned response_length =
+  brw_surface_payload_size(p, 1, true, true);
+   const unsigned desc =
+  brw_message_desc(devinfo, msg_length, response_length, false);
 
struct brw_inst *insn = brw_send_indirect_surface_message(
-  p, sfid, dst, pa

[Mesa-dev] [PATCH 06/23] intel/eu: Use descriptor constructors for sampler messages.

[Francisco Jerez]

---
 src/intel/compiler/brw_eu.h   | 34 ++-
 src/intel/compiler/brw_eu_emit.c  | 45 +++
 src/intel/compiler/brw_fs_generator.cpp   | 72 ++-
 src/intel/compiler/brw_vec4_generator.cpp | 59 -
 4 files changed, 88 insertions(+), 122 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index dc7cb500137..94c005cde55 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -245,17 +245,6 @@ ROUND(RNDE)
 
 /* Helpers for SEND instruction:
  */
-void brw_set_sampler_message(struct brw_codegen *p,
- brw_inst *insn,
- unsigned binding_table_index,
- unsigned sampler,
- unsigned msg_type,
- unsigned response_length,
- unsigned msg_length,
- unsigned header_present,
- unsigned simd_mode,
- unsigned return_format);
-
 void brw_set_dp_read_message(struct brw_codegen *p,
 brw_inst *insn,
 unsigned binding_table_index,
@@ -299,6 +288,29 @@ brw_message_desc(const struct gen_device_info *devinfo,
}
 }
 
+/**
+ * Construct a message descriptor immediate with the specified sampler
+ * function controls.
+ */
+static inline uint32_t
+brw_sampler_desc(const struct gen_device_info *devinfo,
+ unsigned binding_table_index,
+ unsigned sampler,
+ unsigned msg_type,
+ unsigned simd_mode,
+ unsigned return_format)
+{
+   const unsigned desc = (binding_table_index << 0 |
+  sampler << 8);
+   if (devinfo->gen >= 7)
+  return desc | msg_type << 12 | simd_mode << 17;
+   else if (devinfo->gen >= 5)
+  return desc | msg_type << 12 | simd_mode << 16;
+   else if (devinfo->is_g4x)
+  return desc | msg_type << 12;
+   else
+  return desc | return_format << 12 | msg_type << 14;
+}
 
 void brw_urb_WRITE(struct brw_codegen *p,
   struct brw_reg dest,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 2d7d8c61927..3e2af0d9c25 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -552,36 +552,6 @@ brw_set_dp_read_message(struct brw_codegen *p,
   brw_inst_set_dp_read_target_cache(devinfo, insn, target_cache);
 }
 
-void
-brw_set_sampler_message(struct brw_codegen *p,
-brw_inst *inst,
-unsigned binding_table_index,
-unsigned sampler,
-unsigned msg_type,
-unsigned response_length,
-unsigned msg_length,
-unsigned header_present,
-unsigned simd_mode,
-unsigned return_format)
-{
-   const struct gen_device_info *devinfo = p->devinfo;
-
-   brw_set_desc(p, inst, brw_message_desc(
-   devinfo, msg_length, response_length, header_present));
-
-   const unsigned opcode = brw_inst_opcode(devinfo, inst);
-   if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC)
-  brw_inst_set_sfid(devinfo, inst, BRW_SFID_SAMPLER);
-   brw_inst_set_binding_table_index(devinfo, inst, binding_table_index);
-   brw_inst_set_sampler(devinfo, inst, sampler);
-   brw_inst_set_sampler_msg_type(devinfo, inst, msg_type);
-   if (devinfo->gen >= 5) {
-  brw_inst_set_sampler_simd_mode(devinfo, inst, simd_mode);
-   } else if (devinfo->gen == 4 && !devinfo->is_g4x) {
-  brw_inst_set_sampler_return_format(devinfo, inst, return_format);
-   }
-}
-
 static void
 gen7_set_dp_scratch_message(struct brw_codegen *p,
 brw_inst *inst,
@@ -2390,6 +2360,7 @@ void brw_SAMPLE(struct brw_codegen *p,
   gen6_resolve_implied_move(p, &src0, msg_reg_nr);
 
insn = next_insn(p, BRW_OPCODE_SEND);
+   brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER);
brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE); /* XXX */
 
/* From the 965 PRM (volume 4, part 1, section 14.2.41):
@@ -2411,15 +2382,11 @@ void brw_SAMPLE(struct brw_codegen *p,
 
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src0);
-   brw_set_sampler_message(p, insn,
-   binding_table_index,
-   sampler,
-   msg_type,
-   response_length,
-   msg_length,
-   header_present,
-   simd_mode,
-   return_format);
+   brw_set_desc(p, insn,
+brw_message_desc(devinfo, msg_length, response_length,
+ header_present) |
+brw_sampler_des

[Mesa-dev] [PATCH 17/23] intel/fs: Initialize mlen for gen7 varying pull constant load messages.

[Francisco Jerez]

This makes the message length available at the IR level, which should
save some guesswork in a future commit.
---
 src/intel/compiler/brw_fs.cpp   |  2 +-
 src/intel/compiler/brw_fs_generator.cpp | 10 --
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index d67c0a41922..314d580cc1f 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -4715,7 +4715,7 @@ lower_varying_pull_constant_logical_send(const fs_builder 
&bld, fs_inst *inst)
   inst->src[1] = tmp;
 
   inst->opcode = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7;
-
+  inst->mlen = inst->exec_size / 8;
} else {
   const fs_reg payload(MRF, FIRST_PULL_LOAD_MRF(devinfo->gen),
BRW_REGISTER_TYPE_UD);
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index fc7545c6242..71a1e09a786 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1534,17 +1534,15 @@ 
fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
 * gen7, so the fact that it's a send message is hidden at the IR level.
 */
assert(inst->header_size == 0);
-   assert(!inst->mlen);
+   assert(inst->mlen);
assert(index.type == BRW_REGISTER_TYPE_UD);
 
-   uint32_t simd_mode, rlen, mlen;
+   uint32_t simd_mode, rlen;
if (inst->exec_size == 16) {
-  mlen = 2;
   rlen = 8;
   simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
} else {
   assert(inst->exec_size == 8);
-  mlen = 1;
   rlen = 4;
   simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
}
@@ -1558,7 +1556,7 @@ 
fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
   brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
   brw_set_src0(p, send, offset);
   brw_set_desc(p, send,
-   brw_message_desc(devinfo, mlen, rlen, false) |
+   brw_message_desc(devinfo, inst->mlen, rlen, false) |
brw_sampler_desc(devinfo, surf_index,
 0, /* LD message ignores sampler unit */
 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
@@ -1584,7 +1582,7 @@ 
fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
   brw_send_indirect_message(
  p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
  offset, addr,
- brw_message_desc(devinfo, mlen, rlen, false) |
+ brw_message_desc(devinfo, inst->mlen, rlen, false) |
  brw_sampler_desc(devinfo,
   0 /* surface */,
   0 /* sampler */,
-- 
2.16.1

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[Mesa-dev] [PATCH 21/23] intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.

[Francisco Jerez]

Change brw_inst_set_opcode() and brw_inst_opcode() to call
brw_opcode_encode/decode() transparently in order to translate between
hardware and IR opcodes, and update the EU compaction code in order to
do the same as needed, so we can eventually drop the one-to-one
correspondence between hardware and IR opcodes.
---
 src/intel/compiler/brw_eu.h | 13 +
 src/intel/compiler/brw_eu_compact.c | 20 +---
 src/intel/compiler/brw_eu_emit.c|  5 +
 src/intel/compiler/brw_eu_validate.c|  2 +-
 src/intel/compiler/brw_inst.h   |  8 
 src/intel/compiler/test_eu_compact.cpp  |  4 ++--
 src/intel/compiler/test_eu_validate.cpp |  2 +-
 7 files changed, 39 insertions(+), 15 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index dcfaffdaa03..ba8ec04a6ac 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -745,6 +745,19 @@ brw_opcode_decode(const struct gen_device_info *devinfo, 
unsigned hw)
return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
 }
 
+static inline void
+brw_inst_set_opcode(const struct gen_device_info *devinfo,
+brw_inst *inst, enum opcode opcode)
+{
+   brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
+}
+
+static inline enum opcode
+brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
+{
+   return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
+}
+
 static inline bool
 is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
 {
diff --git a/src/intel/compiler/brw_eu_compact.c 
b/src/intel/compiler/brw_eu_compact.c
index ae14ef10ec0..31cad792125 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -949,7 +949,7 @@ brw_try_compact_3src_instruction(const struct 
gen_device_info *devinfo,
 #define compact_a16(field) \
brw_compact_inst_set_3src_##field(devinfo, dst, 
brw_inst_3src_a16_##field(devinfo, src))
 
-   compact(opcode);
+   compact(hw_opcode);
 
if (!set_3src_control_index(devinfo, dst, src))
   return false;
@@ -1121,7 +1121,7 @@ brw_try_compact_instruction(const struct gen_device_info 
*devinfo,
 #define compact(field) \
brw_compact_inst_set_##field(devinfo, &temp, brw_inst_##field(devinfo, src))
 
-   compact(opcode);
+   compact(hw_opcode);
compact(debug_control);
 
if (!set_control_index(devinfo, &temp, src))
@@ -1298,7 +1298,7 @@ brw_uncompact_3src_instruction(const struct 
gen_device_info *devinfo,
 #define uncompact_a16(field) \
brw_inst_set_3src_a16_##field(devinfo, dst, 
brw_compact_inst_3src_##field(devinfo, src))
 
-   uncompact(opcode);
+   uncompact(hw_opcode);
 
set_uncompacted_3src_control_index(devinfo, dst, src);
set_uncompacted_3src_source_index(devinfo, dst, src);
@@ -1328,7 +1328,8 @@ brw_uncompact_instruction(const struct gen_device_info 
*devinfo, brw_inst *dst,
memset(dst, 0, sizeof(*dst));
 
if (devinfo->gen >= 8 &&
-   is_3src(devinfo, brw_compact_inst_3src_opcode(devinfo, src))) {
+   is_3src(devinfo, brw_opcode_decode(
+  devinfo, brw_compact_inst_3src_hw_opcode(devinfo, src {
   brw_uncompact_3src_instruction(devinfo, dst, src);
   return;
}
@@ -1336,7 +1337,7 @@ brw_uncompact_instruction(const struct gen_device_info 
*devinfo, brw_inst *dst,
 #define uncompact(field) \
brw_inst_set_##field(devinfo, dst, brw_compact_inst_##field(devinfo, src))
 
-   uncompact(opcode);
+   uncompact(hw_opcode);
uncompact(debug_control);
 
set_uncompacted_control(devinfo, dst, src);
@@ -1578,7 +1579,8 @@ brw_compact_instructions(struct brw_codegen *p, int 
start_offset,
  if ((offset & sizeof(brw_compact_inst)) != 0 && devinfo->is_g4x){
 brw_compact_inst *align = store + offset;
 memset(align, 0, sizeof(*align));
-brw_compact_inst_set_opcode(devinfo, align, BRW_OPCODE_NENOP);
+brw_compact_inst_set_hw_opcode(
+   devinfo, align, brw_opcode_encode(devinfo, BRW_OPCODE_NENOP));
 brw_compact_inst_set_cmpt_control(devinfo, align, true);
 offset += sizeof(brw_compact_inst);
 compacted_count--;
@@ -1682,6 +1684,9 @@ brw_compact_instructions(struct brw_codegen *p, int 
start_offset,
 brw_inst_set_imm_ud(devinfo, insn, jump_compacted << shift);
  }
  break;
+
+  default:
+ break;
   }
}
 
@@ -1693,7 +1698,8 @@ brw_compact_instructions(struct brw_codegen *p, int 
start_offset,
if (p->next_insn_offset & sizeof(brw_compact_inst)) {
   brw_compact_inst *align = store + offset;
   memset(align, 0, sizeof(*align));
-  brw_compact_inst_set_opcode(devinfo, align, BRW_OPCODE_NOP);
+  brw_compact_inst_set_hw_opcode(
+ devinfo, align, brw_opcode_encode(devinfo, BRW_OPCODE_NOP));
   brw_compact_inst_set_cmpt_control(devinfo, align, true);
   p->next_insn_off

[Mesa-dev] [PATCH 08/23] intel/eu: Use descriptor constructors for dataport write messages.

[Francisco Jerez]

---
 src/intel/compiler/brw_eu.h   |  39 
 src/intel/compiler/brw_eu_emit.c  | 100 --
 src/intel/compiler/brw_vec4_generator.cpp |  22 +++
 3 files changed, 63 insertions(+), 98 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index b31458e5636..f595f5c6726 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -245,18 +245,6 @@ ROUND(RNDE)
 
 /* Helpers for SEND instruction:
  */
-void brw_set_dp_write_message(struct brw_codegen *p,
- brw_inst *insn,
- unsigned binding_table_index,
- unsigned msg_control,
- unsigned msg_type,
-  unsigned target_cache,
- unsigned msg_length,
- bool header_present,
- unsigned last_render_target,
- unsigned response_length,
- unsigned end_of_thread,
- unsigned send_commit_msg);
 
 /**
  * Construct a message descriptor immediate with the specified common
@@ -325,6 +313,33 @@ brw_dp_read_desc(const struct gen_device_info *devinfo,
   return desc | msg_type << 12 | target_cache << 14;
 }
 
+/**
+ * Construct a message descriptor immediate with the specified dataport write
+ * function controls.
+ */
+static inline uint32_t
+brw_dp_write_desc(const struct gen_device_info *devinfo,
+  unsigned binding_table_index,
+  unsigned msg_control,
+  unsigned msg_type,
+  unsigned last_render_target,
+  unsigned send_commit_msg)
+{
+   const unsigned desc = (binding_table_index << 0 |
+  msg_control << 8);
+   if (devinfo->gen >= 7)
+  return (desc | last_render_target << 12 |
+  msg_type << 14);
+   else if (devinfo->gen >= 6)
+  return (desc | last_render_target << 12 |
+  msg_type << 13 |
+  send_commit_msg << 17);
+   else
+  return (desc | last_render_target << 11 |
+  msg_type << 12 |
+  send_commit_msg << 15);
+}
+
 void brw_urb_WRITE(struct brw_codegen *p,
   struct brw_reg dest,
   unsigned msg_reg_nr,
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 0287c1b5f0a..b931d87ccfa 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -489,41 +489,6 @@ static void brw_set_urb_message( struct brw_codegen *p,
}
 }
 
-void
-brw_set_dp_write_message(struct brw_codegen *p,
-brw_inst *insn,
-unsigned binding_table_index,
-unsigned msg_control,
-unsigned msg_type,
- unsigned target_cache,
-unsigned msg_length,
-bool header_present,
-unsigned last_render_target,
-unsigned response_length,
-unsigned end_of_thread,
-unsigned send_commit_msg)
-{
-   const struct gen_device_info *devinfo = p->devinfo;
-   const unsigned sfid = (devinfo->gen >= 6 ? target_cache :
-  BRW_SFID_DATAPORT_WRITE);
-
-   brw_set_desc(p, insn, brw_message_desc(
-   devinfo, msg_length, response_length, header_present));
-
-   brw_inst_set_sfid(devinfo, insn, sfid);
-   brw_inst_set_eot(devinfo, insn, !!end_of_thread);
-   brw_inst_set_binding_table_index(devinfo, insn, binding_table_index);
-   brw_inst_set_dp_write_msg_type(devinfo, insn, msg_type);
-   brw_inst_set_dp_write_msg_control(devinfo, insn, msg_control);
-   brw_inst_set_rt_last(devinfo, insn, last_render_target);
-   if (devinfo->gen < 7) {
-  brw_inst_set_dp_write_commit(devinfo, insn, send_commit_msg);
-   }
-
-   if (devinfo->gen >= 11)
-  brw_inst_set_null_rt(devinfo, insn, false);
-}
-
 static void
 gen7_set_dp_scratch_message(struct brw_codegen *p,
 brw_inst *inst,
@@ -1943,7 +1908,7 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
const unsigned target_cache =
   (devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
-   BRW_DATAPORT_READ_TARGET_RENDER_CACHE);
+   BRW_SFID_DATAPORT_WRITE);
uint32_t msg_type;
 
if (devinfo->gen >= 6)
@@ -1984,6 +1949,7 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
   struct brw_reg src_header = retype(brw_vec8_grf(0, 0),
 BRW_REGISTER_TYPE_UW);
 
+  brw_inst_set_sfid(devinfo, insn, target_cache);
   brw_inst_set_compression(devinfo, insn, false);
 
   if (brw_inst_exec_size(devinfo, insn) >= 16)
@@ -2023,18 +1989,12 @@

[Mesa-dev] [PATCH 11/23] intel/eu: Use descriptor constructors for dataport untyped surface messages.

[Francisco Jerez]

---
 src/intel/compiler/brw_eu.h  | 13 ++
 src/intel/compiler/brw_eu_emit.c | 88 +---
 2 files changed, 51 insertions(+), 50 deletions(-)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 230be6026be..05536c3aaff 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -340,6 +340,19 @@ brw_dp_write_desc(const struct gen_device_info *devinfo,
   send_commit_msg << 15);
 }
 
+/**
+ * Construct a message descriptor immediate with the specified dataport
+ * surface function controls.
+ */
+static inline uint32_t
+brw_dp_surface_desc(const struct gen_device_info *devinfo,
+unsigned msg_type,
+unsigned msg_control)
+{
+   assert(devinfo->gen >= 7);
+   return msg_type << 14 | msg_control << 8;
+}
+
 /**
  * Construct a message descriptor immediate with the specified pixel
  * interpolator function controls.
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index e442827a634..c1a1004c033 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2750,37 +2750,34 @@ brw_surface_payload_size(struct brw_codegen *p,
   return num_channels;
 }
 
-static void
-brw_set_dp_untyped_atomic_message(struct brw_codegen *p,
-  brw_inst *insn,
-  unsigned atomic_op,
-  bool response_expected)
+static uint32_t
+brw_dp_untyped_atomic_desc(struct brw_codegen *p,
+   unsigned atomic_op,
+   bool response_expected)
 {
const struct gen_device_info *devinfo = p->devinfo;
unsigned msg_control =
   atomic_op | /* Atomic Operation Type: BRW_AOP_* */
   (response_expected ? 1 << 5 : 0); /* Return data expected */
+   unsigned msg_type;
 
if (devinfo->gen >= 8 || devinfo->is_haswell) {
   if (brw_get_default_access_mode(p) == BRW_ALIGN_1) {
  if (brw_get_default_exec_size(p) != BRW_EXECUTE_16)
 msg_control |= 1 << 4; /* SIMD8 mode */
 
- brw_inst_set_dp_msg_type(devinfo, insn,
-  HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP);
+ msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
   } else {
- brw_inst_set_dp_msg_type(devinfo, insn,
-HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2);
+ msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
   }
} else {
-  brw_inst_set_dp_msg_type(devinfo, insn,
-   GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP);
-
   if (brw_get_default_exec_size(p) != BRW_EXECUTE_16)
  msg_control |= 1 << 4; /* SIMD8 mode */
+
+  msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
}
 
-   brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
+   return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 }
 
 void
@@ -2800,7 +2797,8 @@ brw_untyped_atomic(struct brw_codegen *p,
const unsigned response_length = brw_surface_payload_size(
   p, response_expected, devinfo->gen >= 8 || devinfo->is_haswell, true);
const unsigned desc =
-  brw_message_desc(devinfo, msg_length, response_length, header_present);
+  brw_message_desc(devinfo, msg_length, response_length, header_present) |
+  brw_dp_untyped_atomic_desc(p, atomic_op, response_expected);
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
/* Mask out unused components -- This is especially important in Align16
 * mode on generations that don't have native support for SIMD4x2 atomics,
@@ -2809,19 +2807,19 @@ brw_untyped_atomic(struct brw_codegen *p,
 * uninitialized Y, Z and W coordinates of the payload.
 */
const unsigned mask = align1 ? WRITEMASK_XYZW : WRITEMASK_X;
-   struct brw_inst *insn = brw_send_indirect_surface_message(
-  p, sfid, brw_writemask(dst, mask), payload, surface, desc);
 
-   brw_set_dp_untyped_atomic_message(
-  p, insn, atomic_op, response_expected);
+   brw_send_indirect_surface_message(p, sfid, brw_writemask(dst, mask),
+ payload, surface, desc);
 }
 
-static void
-brw_set_dp_untyped_surface_read_message(struct brw_codegen *p,
-struct brw_inst *insn,
-unsigned num_channels)
+static uint32_t
+brw_dp_untyped_surface_read_desc(struct brw_codegen *p,
+ unsigned num_channels)
 {
const struct gen_device_info *devinfo = p->devinfo;
+   const unsigned msg_type = (devinfo->gen >= 8 || devinfo->is_haswell ?
+  HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ :
+  GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ);
/* Set mask of 32-bit channels to drop. */
unsigned msg_control = 0xf & (0xf << num_channels);
 
@@ -2832,11 +2830,7 @@ brw_set_dp_untyped_surface_read_message(stru

[Mesa-dev] [PATCH 00/23] intel: Assorted code generation improvements.

[Francisco Jerez]

This series contains a few code generation refactors and clean-ups
that are starting to pile up in an internal branch.  By itself this
series shouldn't cause any functional changes, but there's no reason
why it couldn't be reviewed already which would lessen our pain
keeping the branch up-to-date.

Patches 1-16 rework the mechanism used in most of the back-end code
generator to construct message descriptors in-place as part of the
immediate of either a SEND(C) instruction or some other ALU
instruction, which won't work as soon as we introduce support for the
SENDS instruction and has proven to be rather fragile (see
d2eecf0b0b24d203d0f171807681dffd830d54de), among other disadvantages.

Patches 18-22 drop the hard-coded correspondence between i965 IR
opcodes and native hardware opcodes, which can fail horribly if the
back-end compiler ever needs to use more than one of the hardware
instructions with the same opcode (simultaneously or not), or if the
opcode of any instruction is reassigned.  Fixing this involves
reworking the opcode description tables to allow efficient two-way
look-up by either IR or hardware opcode.

src/intel/Makefile.sources  |   2 +-
src/intel/Makefile.tools.am |   4 +
src/intel/compiler/{brw_eu.c => brw_eu.cpp} | 426 
+--
src/intel/compiler/brw_eu.h | 242 
+--
src/intel/compiler/brw_eu_compact.c |  20 ++--
src/intel/compiler/brw_eu_defines.h | 174 
+-
src/intel/compiler/brw_eu_emit.c| 640 
-
src/intel/compiler/brw_eu_validate.c|   2 +-
src/intel/compiler/brw_fs.cpp   |   3 +-
src/intel/compiler/brw_fs_generator.cpp | 110 ++
src/intel/compiler/brw_inst.h   |  86 -
src/intel/compiler/brw_shader.cpp   |   2 +-
src/intel/compiler/brw_vec4_generator.cpp   | 133 +-
src/intel/compiler/meson.build  |   2 +-
src/intel/compiler/test_eu_compact.cpp  |   8 +-
src/intel/compiler/test_eu_validate.cpp |   2 +-
16 files changed, 863 insertions(+), 993 deletions(-)

[PATCH 01/23] intel/eu: Add brw_inst.h helpers for the SEND(C) descriptor and 
extended descriptor.
[PATCH 02/23] intel/eu: Define helper to specify the descriptor immediates of a 
SEND instruction.
[PATCH 03/23] intel/eu: Use brw_set_desc() along with a helper to set common 
descriptor controls.
[PATCH 04/23] TRIVIAL: intel/eu: Use a local devinfo variable in 
brw_shader_time_add().
[PATCH 05/23] intel/eu: Provide desc immediate argument up front to 
brw_send_indirect_message().
[PATCH 06/23] intel/eu: Use descriptor constructors for sampler messages.
[PATCH 07/23] intel/eu: Use descriptor constructors for dataport read messages.
[PATCH 08/23] intel/eu: Use descriptor constructors for dataport write messages.
[PATCH 09/23] intel/eu: Use descriptor constructors for pixel interpolator 
messages.
[PATCH 10/23] intel/eu: Provide single descriptor argument to 
brw_send_indirect_surface_message().
[PATCH 11/23] intel/eu: Use descriptor constructors for dataport untyped 
surface messages.
[PATCH 12/23] intel/eu: Use descriptor constructors for dataport scattered byte 
surface messages.
[PATCH 13/23] intel/eu: Use descriptor constructors for dataport typed surface 
messages.
[PATCH 14/23] intel/eu: Get rid of the return value of 
brw_send_indirect_surface_message().
[PATCH 15/23] intel/eu: Get rid of the return value of 
brw_send_indirect_message().
[PATCH 16/23] intel/eu: Assert that the instruction is send-like in 
brw_set_desc_ex().
[PATCH 17/23] intel/fs: Initialize mlen for gen7 varying pull constant load 
messages.
[PATCH 18/23] intel/ir: Uncomment definition of several unused hardware opcodes.
[PATCH 19/23] intel/eu: Fix up various type conversions in brw_eu.c that are 
illegal C++.
[PATCH 20/23] intel/eu: Rework opcode description tables to allow efficient 
look-up by either HW or IR opcode.
[PATCH 21/23] intel/eu: Encode and decode native instruction opcodes from/to IR 
opcodes.
[PATCH 22/23] intel/ir: Drop hard-coded correspondence between IR and HW 
opcodes.
[PATCH 23/23] intel/fs: Handle FS_OPCODE_REP_FB_WRITE in implied_mrf_writes().
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[Mesa-dev] [PATCH 04/23] TRIVIAL: intel/eu: Use a local devinfo variable in brw_shader_time_add().

[Francisco Jerez]

---
 src/intel/compiler/brw_eu_emit.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 7389e8e3bde..9f449fb9d34 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3633,10 +3633,11 @@ void brw_shader_time_add(struct brw_codegen *p,
  struct brw_reg payload,
  uint32_t surf_index)
 {
-   const unsigned sfid = (p->devinfo->gen >= 8 || p->devinfo->is_haswell ?
+   const struct gen_device_info *devinfo = p->devinfo;
+   const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
   HSW_SFID_DATAPORT_DATA_CACHE_1 :
   GEN7_SFID_DATAPORT_DATA_CACHE);
-   assert(p->devinfo->gen >= 7);
+   assert(devinfo->gen >= 7);
 
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
@@ -3652,9 +3653,9 @@ void brw_shader_time_add(struct brw_codegen *p,
brw_set_src0(p, send, brw_vec1_reg(payload.file,
   payload.nr, 0));
brw_set_src1(p, send, brw_imm_ud(0));
-   brw_set_desc(p, send, brw_message_desc(p->devinfo, 2, 0, false));
-   brw_inst_set_sfid(p->devinfo, send, sfid);
-   brw_inst_set_binding_table_index(p->devinfo, send, surf_index);
+   brw_set_desc(p, send, brw_message_desc(devinfo, 2, 0, false));
+   brw_inst_set_sfid(devinfo, send, sfid);
+   brw_inst_set_binding_table_index(devinfo, send, surf_index);
brw_set_dp_untyped_atomic_message(p, send, BRW_AOP_ADD, false);
 
brw_pop_insn_state(p);
-- 
2.16.1

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[Mesa-dev] [PATCH 22/23] intel/ir: Drop hard-coded correspondence between IR and HW opcodes.

[Francisco Jerez]

Having the IR opcodes locked to their hardware representation is risky
because it causes opcodes as different as BRC and IFF to compare equal
at the IR level (luckily the back-end only ever uses one opcode from
each group, right now), and it prevents us from supporting
instructions that change their hardware representation across
generations, which will become a serious problem in the future.
---
 src/intel/compiler/brw_eu_defines.h | 174 +---
 src/intel/compiler/brw_shader.cpp   |   2 +-
 2 files changed, 83 insertions(+), 93 deletions(-)

diff --git a/src/intel/compiler/brw_eu_defines.h 
b/src/intel/compiler/brw_eu_defines.h
index ff1a3ac2075..02c6090d35d 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -188,98 +188,88 @@ enum PACKED gen10_align1_3src_dst_horizontal_stride {
 /** @} */
 
 enum opcode {
-   /* These are the actual hardware opcodes. */
-   BRW_OPCODE_ILLEGAL = 0,
-   BRW_OPCODE_MOV =1,
-   BRW_OPCODE_SEL =2,
-   BRW_OPCODE_MOVI =   3,   /**< G45+ */
-   BRW_OPCODE_NOT =4,
-   BRW_OPCODE_AND =5,
-   BRW_OPCODE_OR = 6,
-   BRW_OPCODE_XOR =7,
-   BRW_OPCODE_SHR =8,
-   BRW_OPCODE_SHL =9,
-   BRW_OPCODE_DIM =10,  /**< Gen7.5 only */ /* Reused */
-   BRW_OPCODE_SMOV =   10,  /**< Gen8+   */ /* Reused */
-   /* Reserved - 11 */
-   BRW_OPCODE_ASR =12,
-   /* Reserved - 13-15 */
-   BRW_OPCODE_CMP =16,
-   BRW_OPCODE_CMPN =   17,
-   BRW_OPCODE_CSEL =   18,  /**< Gen8+ */
-   BRW_OPCODE_F32TO16 = 19,  /**< Gen7 only */
-   BRW_OPCODE_F16TO32 = 20,  /**< Gen7 only */
-   /* Reserved - 21-22 */
-   BRW_OPCODE_BFREV =  23,  /**< Gen7+ */
-   BRW_OPCODE_BFE =24,  /**< Gen7+ */
-   BRW_OPCODE_BFI1 =   25,  /**< Gen7+ */
-   BRW_OPCODE_BFI2 =   26,  /**< Gen7+ */
-   /* Reserved - 27-31 */
-   BRW_OPCODE_JMPI =   32,
-   BRW_OPCODE_BRD =33,  /**< Gen7+ */
-   BRW_OPCODE_IF = 34,
-   BRW_OPCODE_IFF =35,  /**< Pre-Gen6*/ /* Reused */
-   BRW_OPCODE_BRC =35,  /**< Gen7+   */ /* Reused */
-   BRW_OPCODE_ELSE =   36,
-   BRW_OPCODE_ENDIF =  37,
-   BRW_OPCODE_DO = 38,  /**< Pre-Gen6*/ /* Reused */
-   BRW_OPCODE_CASE =   38,  /**< Gen6 only   */ /* Reused */
-   BRW_OPCODE_WHILE =  39,
-   BRW_OPCODE_BREAK =  40,
-   BRW_OPCODE_CONTINUE = 41,
-   BRW_OPCODE_HALT =   42,
-   BRW_OPCODE_CALLA =  43,  /**< Gen7.5+ */
-   BRW_OPCODE_MSAVE =  44,  /**< Pre-Gen6*/ /* Reused */
-   BRW_OPCODE_CALL =   44,  /**< Gen6+   */ /* Reused */
-   BRW_OPCODE_MREST =  45,  /**< Pre-Gen6*/ /* Reused */
-   BRW_OPCODE_RET =45,  /**< Gen6+   */ /* Reused */
-   BRW_OPCODE_PUSH =   46,  /**< Pre-Gen6*/ /* Reused */
-   BRW_OPCODE_FORK =   46,  /**< Gen6 only   */ /* Reused */
-   BRW_OPCODE_GOTO =   46,  /**< Gen8+   */ /* Reused */
-   BRW_OPCODE_POP =47,  /**< Pre-Gen6*/
-   BRW_OPCODE_WAIT =   48,
-   BRW_OPCODE_SEND =   49,
-   BRW_OPCODE_SENDC =  50,
-   BRW_OPCODE_SENDS =  51,  /**< Gen9+ */
-   BRW_OPCODE_SENDSC = 52,  /**< Gen9+ */
-   /* Reserved 53-55 */
-   BRW_OPCODE_MATH =   56,  /**< Gen6+ */
-   /* Reserved 57-63 */
-   BRW_OPCODE_ADD =64,
-   BRW_OPCODE_MUL =65,
-   BRW_OPCODE_AVG =66,
-   BRW_OPCODE_FRC =67,
-   BRW_OPCODE_RNDU =   68,
-   BRW_OPCODE_RNDD =   69,
-   BRW_OPCODE_RNDE =   70,
-   BRW_OPCODE_RNDZ =   71,
-   BRW_OPCODE_MAC =72,
-   BRW_OPCODE_MACH =   73,
-   BRW_OPCODE_LZD =74,
-   BRW_OPCODE_FBH =75,  /**< Gen7+ */
-   BRW_OPCODE_FBL =76,  /**< Gen7+ */
-   BRW_OPCODE_CBIT =   77,  /**< Gen7+ */
-   BRW_OPCODE_ADDC =   78,  /**< Gen7+ */
-   BRW_OPCODE_SUBB =   79,  /**< Gen7+ */
-   BRW_OPCODE_SAD2 =   80,
-   BRW_OPCODE_SADA2 =  81,
-   /* Reserved 82-83 */
-   BRW_OPCODE_DP4 =84,
-   BRW_OPCODE_DPH =85,
-   BRW_OPCODE_DP3 =86,
-   BRW_OPCODE_DP2 =87,
-   /* Reserved 88 */
-   BRW_OPCODE_LINE =   89,
-   BRW_OPCODE_PLN =90,  /**< G45+ */
-   BRW_OPCODE_MAD =91,  /**< Gen6+ */
-   BRW_OPCODE_LRP =92,  /**< Gen6+ */
-   BRW_OPCODE_MADM =   93,  /**< Gen8+ */
-   /* Reserved 94-124 */
-   BRW_OPCODE_NENOP =  125, /**< G45 only */
-   BRW_OPCODE_NOP =126,
-   /* Reserved 127 */
-
-   NUM_BRW_OPCODES = 128,
+   /* These are the actual hardware instructions. */
+   BRW_OPCODE_ILLEGAL,
+   BRW_OPCODE_MOV,
+   BRW_OPCODE_SEL,
+   BRW_OPCODE_MOVI, /**< G45+ */
+   BRW_OPCODE_NOT,
+   BRW_OPCODE_AND,
+   BRW_OPCODE_OR,
+   BRW_OPCODE_XOR,
+   BRW_OPCODE_SHR,
+   BRW_OPCODE_SHL,
+   BRW_OPCODE_DIM, /**< Gen7.5 only */
+   BRW_OPCODE_SMOV, /**< Gen8+ */
+   BRW_OPCODE_ASR,
+   BRW_OPCODE_CMP,
+   BRW_OPCODE_CMPN,
+   BRW_OPCODE_CSEL, /**< Gen8+ */
+   BRW_OPCODE_F32TO16, /**< Gen7 only */
+   BRW_OPCODE_F16TO32, /**< Gen7 only */
+   BRW_OPCODE_BFREV, /**< Gen7+ */
+   BRW_OPCODE_BFE, /**< Gen7+ */
+   BRW_OPCODE_BFI1, /**< Gen7+ */
+   BRW_OPCODE_BFI2, /**< Gen7+ */
+   BRW_OPCODE_JMPI,
+   BRW_OPCODE_BRD, /**< Gen7+ */
+   BRW_OPCODE_IF,
+   B

[Mesa-dev] [PATCH 02/23] intel/eu: Define helper to specify the descriptor immediates of a SEND instruction.

[Francisco Jerez]

---
 src/intel/compiler/brw_eu.h  |  9 +
 src/intel/compiler/brw_eu_emit.c | 17 +
 2 files changed, 26 insertions(+)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 0f07eeb3d6d..5a396339fde 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -600,6 +600,15 @@ void brw_math_invert( struct brw_codegen *p,
 
 void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
 
+void brw_set_desc_ex(struct brw_codegen *p, brw_inst *insn,
+ unsigned desc, unsigned ex_desc);
+
+static inline void
+brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc)
+{
+   brw_set_desc_ex(p, insn, desc, 0);
+}
+
 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
 
 enum brw_conditional_mod brw_negate_cmod(uint32_t cmod);
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index d3246edde44..ab9af718152 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -401,6 +401,23 @@ brw_set_message_descriptor(struct brw_codegen *p,
}
 }
 
+/**
+ * Specify the descriptor and extended descriptor immediate for a SEND(C)
+ * message instruction.
+ */
+void
+brw_set_desc_ex(struct brw_codegen *p, brw_inst *inst,
+unsigned desc, unsigned ex_desc)
+{
+   const struct gen_device_info *devinfo = p->devinfo;
+   brw_inst_set_src1_file_type(devinfo, inst,
+   BRW_IMMEDIATE_VALUE, BRW_REGISTER_TYPE_D);
+   brw_inst_set_send_desc(devinfo, inst, desc);
+   if (devinfo->gen >= 9 && (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND 
||
+ brw_inst_opcode(devinfo, inst) == 
BRW_OPCODE_SENDC))
+  brw_inst_set_send_ex_desc(devinfo, inst, ex_desc);
+}
+
 static void brw_set_math_message( struct brw_codegen *p,
  brw_inst *inst,
  unsigned function,
-- 
2.16.1

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[Mesa-dev] [PATCH 01/23] intel/eu: Add brw_inst.h helpers for the SEND(C) descriptor and extended descriptor.

[Francisco Jerez]

This introduces helpers that can be used to specify or extract the
whole descriptor of a SEND message instruction at once.  Because the
the instruction encoding of these is rather awkward on some
generations using the generic brw_inst.h macros doesn't seem like an
option.
---
 src/intel/compiler/brw_inst.h | 78 +++
 1 file changed, 78 insertions(+)

diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 8663c1b7f5b..438a473c1cd 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -458,6 +458,84 @@ FC(gen4_pop_count,  115, 112, devinfo->gen < 6)
 /* Message descriptor bits */
 #define MD(x) ((x) + 96)
 
+/**
+ * Set the SEND(C) message descriptor immediate.
+ *
+ * This doesn't include the SFID nor the EOT field that were considered to be
+ * part of the message descriptor by ancient versions of the BSpec, because
+ * they are present in the instruction even if the message descriptor is
+ * provided indirectly in the address register, so we want to specify them
+ * separately.
+ */
+static inline void
+brw_inst_set_send_desc(const struct gen_device_info *devinfo,
+   brw_inst *inst, uint32_t value)
+{
+   if (devinfo->gen >= 9) {
+  brw_inst_set_bits(inst, 126, 96, value);
+  assert(value >> 31 == 0);
+   } else if (devinfo->gen >= 5) {
+  brw_inst_set_bits(inst, 124, 96, value);
+  assert(value >> 29 == 0);
+   } else {
+  brw_inst_set_bits(inst, 119, 96, value);
+  assert(value >> 24 == 0);
+   }
+}
+
+/**
+ * Get the SEND(C) message descriptor immediate.
+ *
+ * \sa brw_inst_set_send_desc().
+ */
+static inline uint32_t
+brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
+{
+   if (devinfo->gen >= 9)
+  return brw_inst_bits(inst, 126, 96);
+   else if (devinfo->gen >= 5)
+  return brw_inst_bits(inst, 124, 96);
+   else
+  return brw_inst_bits(inst, 119, 96);
+}
+
+/**
+ * Set the SEND(C) message extended descriptor immediate.
+ *
+ * This doesn't include the SFID nor the EOT field that were considered to be
+ * part of the extended message descriptor by some versions of the BSpec,
+ * because they are present in the instruction even if the extended message
+ * descriptor is provided indirectly in a register, so we want to specify them
+ * separately.
+ */
+static inline void
+brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
+  brw_inst *inst, uint32_t value)
+{
+   assert(devinfo->gen >= 9);
+   brw_inst_set_bits(inst, 94, 91, (value >> 28) & ((1u << 4) - 1));
+   brw_inst_set_bits(inst, 88, 85, (value >> 24) & ((1u << 4) - 1));
+   brw_inst_set_bits(inst, 83, 80, (value >> 20) & ((1u << 4) - 1));
+   brw_inst_set_bits(inst, 67, 64, (value >> 16) & ((1u << 4) - 1));
+   assert((value & ((1u << 16) - 1)) == 0);
+}
+
+/**
+ * Get the SEND(C) message extended descriptor immediate.
+ *
+ * \sa brw_inst_set_send_ex_desc().
+ */
+static inline uint32_t
+brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
+  const brw_inst *inst)
+{
+   assert(devinfo->gen >= 9);
+   return (brw_inst_bits(inst, 94, 91) << 28 |
+   brw_inst_bits(inst, 88, 85) << 24 |
+   brw_inst_bits(inst, 83, 80) << 20 |
+   brw_inst_bits(inst, 67, 64) << 16);
+}
+
 /**
  * Fields for SEND messages:
  *  @{
-- 
2.16.1

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Re: [Mesa-dev] [PATCH 00/16] Move the Mesa Website to Sphinx

[Rob Clark]

On Mon, Jun 11, 2018 at 6:24 PM, Laura Ekstrand  wrote:
> I really like the rotate on hover effect for the gears.  I would rather that
> we use 2D WebGL for it if we could, though, since Mesa enables WebGL on
> certain platforms.
>

webgl can be a bit heavy for startup time although it might be kinda
nice if clicking the logo enough times launched an interactive webgl
version of the logo where you could rotate the logo..

(and either way, it would be nice to see a mesa-gears version of the
gears+mesa logo in mesa-demos)

BR,
-R


> Stuart, I will try to get the favicon and rtd_theme fixed.  We may have to
> make our Docker image.
>
> Thanks.
>
> Laura
>
> On Fri, Jun 8, 2018 at 7:23 AM, Erik Faye-Lund  wrote:
>>
>> On Fri, Jun 8, 2018 at 4:09 PM Rhys Perry 
>> wrote:
>> >
>> > Might be good to do something like this:
>> > https://codepen.io/anon/pen/ERNdYJ
>> > So that those with NoScript or something won't have gears constantly
>> > rotating on their screen.
>> >
>>
>> Yeah, good point.
>> ___
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>
>
>
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Re: [Mesa-dev] [PATCH 00/16] Move the Mesa Website to Sphinx

[Laura Ekstrand]

It's done already, it was a one-liner:
https://gitlab.freedesktop.org/ldeks/mesa/commits/website1_75_v2

On Mon, Jun 11, 2018 at 5:15 PM, Stuart Young  wrote:

> Laura: Brilliant. Don't let it hang any deployment though. There's so much
> more good in this that losing the favicon for a while is definitely worth
> it.
>
> On Tue, 12 Jun 2018 at 08:27, Laura Ekstrand  wrote:
>
>> I really like the rotate on hover effect for the gears.  I would rather
>> that we use 2D WebGL for it if we could, though, since Mesa enables WebGL
>> on certain platforms.
>>
>> Stuart, I will try to get the favicon and rtd_theme fixed.  We may have
>> to make our Docker image.
>>
>> Thanks.
>>
>> Laura
>>
>> On Fri, Jun 8, 2018 at 7:23 AM, Erik Faye-Lund 
>> wrote:
>>
>>> On Fri, Jun 8, 2018 at 4:09 PM Rhys Perry 
>>> wrote:
>>> >
>>> > Might be good to do something like this: https://codepen.io/anon/pen/
>>> ERNdYJ
>>> > So that those with NoScript or something won't have gears constantly
>>> > rotating on their screen.
>>> >
>>>
>>> Yeah, good point.
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>>>
>>
>> ___
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>
>
> --
> Stuart Young (aka Cefiar)
>
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Re: [Mesa-dev] [PATCH 00/16] Move the Mesa Website to Sphinx

[Stuart Young]

Laura: Brilliant. Don't let it hang any deployment though. There's so much
more good in this that losing the favicon for a while is definitely worth
it.

On Tue, 12 Jun 2018 at 08:27, Laura Ekstrand  wrote:

> I really like the rotate on hover effect for the gears.  I would rather
> that we use 2D WebGL for it if we could, though, since Mesa enables WebGL
> on certain platforms.
>
> Stuart, I will try to get the favicon and rtd_theme fixed.  We may have to
> make our Docker image.
>
> Thanks.
>
> Laura
>
> On Fri, Jun 8, 2018 at 7:23 AM, Erik Faye-Lund 
> wrote:
>
>> On Fri, Jun 8, 2018 at 4:09 PM Rhys Perry 
>> wrote:
>> >
>> > Might be good to do something like this:
>> https://codepen.io/anon/pen/ERNdYJ
>> > So that those with NoScript or something won't have gears constantly
>> > rotating on their screen.
>> >
>>
>> Yeah, good point.
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>>
>
> ___
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-- 
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Re: [Mesa-dev] [PATCH 2/2] nir: add lowering for gl_HelperInvocation

[Rob Clark]

On Mon, Jun 11, 2018 at 6:59 PM, Roland Scheidegger  wrote:
> Am 12.06.2018 um 00:32 schrieb Jason Ekstrand:
>> On Wed, Jun 6, 2018 at 7:43 AM, Rob Clark > > wrote:
>>
>> Signed-off-by: Rob Clark > >
>> ---
>> I can't say for sure that this will work on all drivers, but it is
>> what the blob driver does, and it seems to make deqp happy.  I could
>> move this to it's own pass inside ir3, but that seemed like overkill
>>
>>  src/compiler/nir/nir.h  | 10 ++
>>  src/compiler/nir/nir_lower_system_values.c  | 17 +
>>  src/gallium/drivers/freedreno/ir3/ir3_nir.c |  1 +
>>  3 files changed, 28 insertions(+)
>>
>> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
>> index 073ab4e82ea..de3d55d83af 100644
>> --- a/src/compiler/nir/nir.h
>> +++ b/src/compiler/nir/nir.h
>> @@ -1963,6 +1963,16 @@ typedef struct nir_shader_compiler_options {
>>  */
>> bool lower_base_vertex;
>>
>> +   /**
>> +* If enabled, gl_HelperInvocation will be lowered as:
>> +*
>> +*   !((1 << gl_SampleID) & gl_SampleMaskIN[0]))
>>
>>
>> This only works for multi-sampling.  What about the single-sampled case?
> It doesn't make sense to me for msaa neither.
> gl_SampleID forces per-sample execution, which clearly isn't what you
> want.

open to suggestions about how to try and force blob to do something
different.. I tried a few things and the blob popped out shader code
that worked the same way in all cases, but ofc I could have missed
something.

> Plus, gl_SampleMaskIN is specified to only contain bits for the
> current shader invocation, so for msaa with forced per-sample execution
> that would only contain the single bit corresponding to gl_SampleID
> anyway (that is my interpretation at least - I know hw sample mask
> inputs will probably always contains all the bits from rasterization,
> regardless of gl_SampleID), so the "1 << gl_SampleID &" part will do
> nothing at all. So I think that part is more about lowering the hw
> rasterization sample mask to gl_SampleMaskIN rather than lowering to
> gl_HelperInvocation.
> But yes, !gl_SampleMaskIN should give gl_HelperInvocation - I think all
> hw can give you raster sample mask even without msaa but I'm not
> entirely sure if it's guaranteed to work in GL with single sampling
> (similar for sample id, which should just be stuck at 0). But using the
> gl names here looks very, very fishy to me here.

I *guess* this is relying on behaviour that gl does not guarantee, but
also doesn't prohibit, but the hw happens work that way and it works
out..

Maybe the answer is to simply better document the assumptions that
this lowering depends on?

BR,
-R

>
> Roland
>
>
>
>
>>
>> --Jason
>>
>>
>>
>> +*
>> +* TODO any hw w/ more than 32 samples?  For them (if they
>> +* used this option), a bit more math would be involved.
>> +*/
>> +   bool lower_helper_invocation;
>> +
>> bool lower_cs_local_index_from_id;
>>
>> bool lower_device_index_to_zero;
>> diff --git a/src/compiler/nir/nir_lower_system_values.c
>> b/src/compiler/nir/nir_lower_system_values.c
>> index 487da042620..6668cbb5dcd 100644
>> --- a/src/compiler/nir/nir_lower_system_values.c
>> +++ b/src/compiler/nir/nir_lower_system_values.c
>> @@ -136,6 +136,23 @@ convert_block(nir_block *block, nir_builder *b)
>>nir_load_first_vertex(b));
>>   break;
>>
>> +  case SYSTEM_VALUE_HELPER_INVOCATION:
>> + if (b->shader->options->lower_helper_invocation) {
>> +nir_ssa_def *tmp;
>> +
>> +tmp = nir_ushr(b,
>> +   nir_imm_int(b, 1),
>> +   nir_load_sample_id(b));
>> +
>> +tmp = nir_iand(b,
>> +   nir_load_sample_mask_in(b),
>> +   tmp);
>> +
>> +sysval = nir_inot(b, nir_i2b(b, tmp));
>> + }
>> +
>> + break;
>> +
>>case SYSTEM_VALUE_INSTANCE_INDEX:
>>   sysval = nir_iadd(b,
>> nir_load_instance_id(b),
>> diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
>> b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
>> index cd1f9c526f2..341d990b269 100644
>> --- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
>> +++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
>> @@ -51,6 +51,7 @@ static const nir_shader_compiler_options options = {
>> .lower_extract_byte = true,
>> .lower_extract_word = true,
>> .lower_all_io_to_temps = true,
>> +   .lower_helper_invocation = true,
>>  };
>>
>>  struct nir_shader *
>> --
>> 2.17.0
>>
>> _

Re: [Mesa-dev] [PATCH 2/2] nir: add lowering for gl_HelperInvocation

[Jason Ekstrand]

On Mon, Jun 11, 2018 at 3:59 PM, Roland Scheidegger 
wrote:

> Am 12.06.2018 um 00:32 schrieb Jason Ekstrand:
> > On Wed, Jun 6, 2018 at 7:43 AM, Rob Clark  > > wrote:
> >
> > Signed-off-by: Rob Clark  > >
> > ---
> > I can't say for sure that this will work on all drivers, but it is
> > what the blob driver does, and it seems to make deqp happy.  I could
> > move this to it's own pass inside ir3, but that seemed like overkill
> >
> >  src/compiler/nir/nir.h  | 10 ++
> >  src/compiler/nir/nir_lower_system_values.c  | 17 +
> >  src/gallium/drivers/freedreno/ir3/ir3_nir.c |  1 +
> >  3 files changed, 28 insertions(+)
> >
> > diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> > index 073ab4e82ea..de3d55d83af 100644
> > --- a/src/compiler/nir/nir.h
> > +++ b/src/compiler/nir/nir.h
> > @@ -1963,6 +1963,16 @@ typedef struct nir_shader_compiler_options {
> >  */
> > bool lower_base_vertex;
> >
> > +   /**
> > +* If enabled, gl_HelperInvocation will be lowered as:
> > +*
> > +*   !((1 << gl_SampleID) & gl_SampleMaskIN[0]))
> >
> >
> > This only works for multi-sampling.  What about the single-sampled case?
> It doesn't make sense to me for msaa neither.
> gl_SampleID forces per-sample execution, which clearly isn't what you
> want.


Yes, we do not want gl_HelperInvocation to force per-sample shading.  It
doesn't mean we can't lower to it, it just means that the back-end needs to
be very careful that it decides whether or not to execute per-sample before
it does this lowering.


> Plus, gl_SampleMaskIN is specified to only contain bits for the
> current shader invocation, so for msaa with forced per-sample execution
> that would only contain the single bit corresponding to gl_SampleID
> anyway (that is my interpretation at least - I know hw sample mask
> inputs will probably always contains all the bits from rasterization,
> regardless of gl_SampleID), so the "1 << gl_SampleID &" part will do
> nothing at all.


I think it also relies on gl_SampleMaskIN to give 0 for helper
invocations.  This is likely true but I don't know how well-defined all
this is in the world of helper invocations.


> So I think that part is more about lowering the hw
> rasterization sample mask to gl_SampleMaskIN rather than lowering to
> gl_HelperInvocation.
> But yes, !gl_SampleMaskIN should give gl_HelperInvocation - I think all
> hw can give you raster sample mask even without msaa but I'm not
> entirely sure if it's guaranteed to work in GL with single sampling
> (similar for sample id, which should just be stuck at 0).
>

The GL spec doesn't seem to say.  It does say that gl_SampleID is
guaranteed to be 0 for single-sampled but it says nothing about
gl_SampleMaskIN.

--Jason
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[Mesa-dev] [PATCH 39/48] meson: Set visibility and compat args for graw

[Dylan Baker]

---
 src/gallium/targets/graw-gdi/meson.build  | 1 +
 src/gallium/targets/graw-null/meson.build | 2 ++
 src/gallium/targets/graw-xlib/meson.build | 1 +
 3 files changed, 4 insertions(+)

diff --git a/src/gallium/targets/graw-gdi/meson.build 
b/src/gallium/targets/graw-gdi/meson.build
index e04b454ab53..b742b0a11a2 100644
--- a/src/gallium/targets/graw-gdi/meson.build
+++ b/src/gallium/targets/graw-gdi/meson.build
@@ -21,6 +21,7 @@
 libgraw_gdi = shared_library(
   'graw',
   'graw_gdi.c',
+  c_args : [c_vis_args, c_msvc_compat_args],
   include_directories : [
 inc_include, inc_src, inc_gallium, inc_gallium_aux, inc_gallium_drivers,
 inc_gallium_winsys_sw,
diff --git a/src/gallium/targets/graw-null/meson.build 
b/src/gallium/targets/graw-null/meson.build
index 8a294f41307..0b7c6ff40e6 100644
--- a/src/gallium/targets/graw-null/meson.build
+++ b/src/gallium/targets/graw-null/meson.build
@@ -21,12 +21,14 @@
 libgraw_util = static_library(
   'graw_util',
   ['graw_util.c'],
+  c_args : [c_vis_args, c_msvc_compat_args],
   include_directories : inc_common,
 )
 
 libgraw_null = shared_library(
   'graw_null',
   ['graw_null.c'],
+  c_args : [c_vis_args, c_msvc_compat_args],
   include_directories : inc_common,
   link_with : [libmesa_util, libgallium],
 )
diff --git a/src/gallium/targets/graw-xlib/meson.build 
b/src/gallium/targets/graw-xlib/meson.build
index aab99ba64c1..13567355d2c 100644
--- a/src/gallium/targets/graw-xlib/meson.build
+++ b/src/gallium/targets/graw-xlib/meson.build
@@ -21,6 +21,7 @@
 libgraw_xlib = shared_library(
   'graw_xlib',
   ['graw_xlib.c'],
+  c_args : [c_vis_args],
   include_directories : [inc_common, inc_gallium_drivers, inc_gallium_winsys],
   link_with : [
 libgraw_util, libmesa_util, libgallium, libws_xlib
-- 
2.17.1

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[Mesa-dev] [PATCH 46/48] appveyor: Add support for meson as well as scons

[Dylan Baker]

This currently builds softpipe only
---
 appveyor.yml | 28 +++-
 1 file changed, 19 insertions(+), 9 deletions(-)

diff --git a/appveyor.yml b/appveyor.yml
index bd33e2e9554..06063feba93 100644
--- a/appveyor.yml
+++ b/appveyor.yml
@@ -42,6 +42,9 @@ os: Visual Studio 2015
 environment:
   WINFLEXBISON_ARCHIVE: win_flex_bison-2.5.9.zip
   LLVM_ARCHIVE: llvm-3.3.1-msvc2015-mtd.7z
+  matrix:
+- BUILD_SYSTEM: meson
+- BUILD_SYSTEM: scons
 
 install:
 # Check pip
@@ -49,13 +52,16 @@ install:
 - python -m pip --version
 # Install Mako
 - python -m pip install Mako==1.0.6
-# Install pywin32 extensions, needed by SCons
-- python -m pip install pypiwin32
-# Install python wheels, necessary to install SCons via pip
-- python -m pip install wheel
-# Install SCons
-- python -m pip install scons==2.5.1
-- scons --version
+- if "%BUILD_SYSTEM%"=="scons" python -m pip install pypiwin32 wheel
+- if "%BUILD_SYSTEM%"=="scons" python -m pip install scons==2.5.1
+- if "%BUILD_SYSTEM%"=="scons" scons --version
+- if "%BUILD_SYSTEM%"=="meson" C:\Python36\python.exe -m pip install meson
+- if "%BUILD_SYSTEM%"=="meson" set Path=C:\Python36\Scripts;%Path%
+- if "%BUILD_SYSTEM%"=="meson" set Path=C:\Python27;%Path%
+- if "%BUILD_SYSTEM%"=="meson" meson.py --version
+- if "%BUILD_SYSTEM%"=="meson" cinst -y ninja pkgconfiglite
+- if "%BUILD_SYSTEM%"=="meson" ninja --version
+- if "%BUILD_SYSTEM%"=="meson" call "C:\Program Files (x86)\Microsoft Visual 
Studio 14.0\VC\vcvarsall.bat" x86_amd64
 # Install flex/bison
 - if not exist "%WINFLEXBISON_ARCHIVE%" appveyor DownloadFile 
"https://downloads.sourceforge.net/project/winflexbison/old_versions/%WINFLEXBISON_ARCHIVE%";
 - 7z x -y -owinflexbison\ "%WINFLEXBISON_ARCHIVE%" > nul
@@ -69,10 +75,14 @@ install:
 - set LLVM=%CD%\llvm
 
 build_script:
-- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=14.0 llvm=1
+- if "%BUILD_SYSTEM%"=="scons" scons -j%NUMBER_OF_PROCESSORS% 
MSVC_VERSION=14.0 llvm=1
+- if "%BUILD_SYSTEM%"=="meson" meson builddir -Dbuild-tests=true
+- if "%BUILD_SYSTEM%"=="meson" ninja -C builddir
 
 after_build:
-- scons -j%NUMBER_OF_PROCESSORS% MSVC_VERSION=14.0 llvm=1 check
+- if "%BUILD_SYSTEM%"=="scons" scons -j%NUMBER_OF_PROCESSORS% 
MSVC_VERSION=14.0 llvm=1 check
+# Doesn't work yet, a large number of tests fail
+#- if "%BUILD_SYSTEM%"=="meson" ninja -C builddir test
 
 
 # It's possible to setup notification here, as described in
-- 
2.17.1

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[Mesa-dev] [PATCH 24/48] docs/meson.html: fix numerous issues spotted by xmllint

[Dylan Baker]

---
 docs/meson.html | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/docs/meson.html b/docs/meson.html
index 6697dbb34ef..7541e7a71b0 100644
--- a/docs/meson.html
+++ b/docs/meson.html
@@ -1,9 +1,9 @@
 http://www.w3.org/TR/html4/loose.dtd";>
 
 
-  
+  
   Compilation and Installation using Meson
-  
+  
 
 
 
@@ -247,7 +247,6 @@ is unrelated to the buildtype; setting the 
latter to
 
 
 
-
 
 
 
-- 
2.17.1

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[Mesa-dev] [PATCH 35/48] util/tests: Use define instead of VLA

[Dylan Baker]

To allow the this test to be built with MSVC, which doesn't support
VLAs.
---
 src/util/tests/hash_table/clear.c | 13 +++--
 src/util/tests/hash_table/delete_management.c | 13 +++--
 src/util/tests/hash_table/insert_many.c   | 11 ++-
 src/util/tests/hash_table/meson.build |  1 +
 src/util/tests/hash_table/random_entry.c  |  7 ---
 src/util/tests/string_buffer/meson.build  |  1 +
 6 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/src/util/tests/hash_table/clear.c 
b/src/util/tests/hash_table/clear.c
index 526700bfb0f..19494844608 100644
--- a/src/util/tests/hash_table/clear.c
+++ b/src/util/tests/hash_table/clear.c
@@ -23,6 +23,8 @@
 
 #include "hash_table.h"
 
+#define SIZE 1000
+
 static void *make_key(uint32_t i)
 {
   return (void *)(uintptr_t)(1 + i);
@@ -54,13 +56,12 @@ int main()
 {
struct hash_table *ht;
struct hash_entry *entry;
-   const uint32_t size = 1000;
-   bool flags[size];
+   bool flags[SIZE];
uint32_t i;
 
ht = _mesa_hash_table_create(NULL, key_hash, key_equal);
 
-   for (i = 0; i < size; ++i) {
+   for (i = 0; i < SIZE; ++i) {
   flags[i] = false;
   _mesa_hash_table_insert(ht, make_key(i), &flags[i]);
}
@@ -70,19 +71,19 @@ int main()
 
/* Check that delete_function was called and that repopulating the table
 * works. */
-   for (i = 0; i < size; ++i) {
+   for (i = 0; i < SIZE; ++i) {
   assert(flags[i]);
   flags[i] = false;
   _mesa_hash_table_insert(ht, make_key(i), &flags[i]);
}
 
/* Check that exactly the right set of entries is in the table. */
-   for (i = 0; i < size; ++i) {
+   for (i = 0; i < SIZE; ++i) {
   assert(_mesa_hash_table_search(ht, make_key(i)));
}
 
hash_table_foreach(ht, entry) {
-  assert(key_id(entry->key) < size);
+  assert(key_id(entry->key) < SIZE);
}
 
_mesa_hash_table_destroy(ht, NULL);
diff --git a/src/util/tests/hash_table/delete_management.c 
b/src/util/tests/hash_table/delete_management.c
index 127d81b3ca9..e3be9fb3d99 100644
--- a/src/util/tests/hash_table/delete_management.c
+++ b/src/util/tests/hash_table/delete_management.c
@@ -30,6 +30,8 @@
 #include 
 #include "hash_table.h"
 
+#define SIZE 1
+
 static uint32_t
 key_value(const void *key)
 {
@@ -47,8 +49,7 @@ main(int argc, char **argv)
 {
struct hash_table *ht;
struct hash_entry *entry;
-   unsigned size = 1;
-   uint32_t keys[size];
+   uint32_t keys[SIZE];
uint32_t i;
 
(void) argc;
@@ -56,7 +57,7 @@ main(int argc, char **argv)
 
ht = _mesa_hash_table_create(NULL, key_value, uint32_t_key_equals);
 
-   for (i = 0; i < size; i++) {
+   for (i = 0; i < SIZE; i++) {
   keys[i] = i;
 
   _mesa_hash_table_insert(ht, keys + i, NULL);
@@ -69,7 +70,7 @@ main(int argc, char **argv)
}
 
/* Make sure that all our entries were present at the end. */
-   for (i = size - 100; i < size; i++) {
+   for (i = SIZE - 100; i < SIZE; i++) {
   entry = _mesa_hash_table_search(ht, keys + i);
   assert(entry);
   assert(key_value(entry->key) == i);
@@ -79,8 +80,8 @@ main(int argc, char **argv)
for (entry = _mesa_hash_table_next_entry(ht, NULL);
 entry != NULL;
 entry = _mesa_hash_table_next_entry(ht, entry)) {
-  assert(key_value(entry->key) >= size - 100 &&
- key_value(entry->key) < size);
+  assert(key_value(entry->key) >= SIZE - 100 &&
+ key_value(entry->key) < SIZE);
}
assert(ht->entries == 100);
 
diff --git a/src/util/tests/hash_table/insert_many.c 
b/src/util/tests/hash_table/insert_many.c
index b07e40842bf..6bd35d5c0c7 100644
--- a/src/util/tests/hash_table/insert_many.c
+++ b/src/util/tests/hash_table/insert_many.c
@@ -30,6 +30,8 @@
 #include 
 #include "hash_table.h"
 
+#define SIZE 1
+
 static uint32_t
 key_value(const void *key)
 {
@@ -47,8 +49,7 @@ main(int argc, char **argv)
 {
struct hash_table *ht;
struct hash_entry *entry;
-   unsigned size = 1;
-   uint32_t keys[size];
+   uint32_t keys[SIZE];
uint32_t i;
 
(void) argc;
@@ -56,18 +57,18 @@ main(int argc, char **argv)
 
ht = _mesa_hash_table_create(NULL, key_value, uint32_t_key_equals);
 
-   for (i = 0; i < size; i++) {
+   for (i = 0; i < SIZE; i++) {
   keys[i] = i;
 
   _mesa_hash_table_insert(ht, keys + i, NULL);
}
 
-   for (i = 0; i < size; i++) {
+   for (i = 0; i < SIZE; i++) {
   entry = _mesa_hash_table_search(ht, keys + i);
   assert(entry);
   assert(key_value(entry->key) == i);
}
-   assert(ht->entries == size);
+   assert(ht->entries == SIZE);
 
_mesa_hash_table_destroy(ht, NULL);
 
diff --git a/src/util/tests/hash_table/meson.build 
b/src/util/tests/hash_table/meson.build
index 4bbc5100ea3..38127013044 100644
--- a/src/util/tests/hash_table/meson.build
+++ b/src/util/tests/hash_table/meson.build
@@ -26,6 +26,7 @@ foreach t : ['clear', 'collision', 'delete_and_lookup', 
'delete_management',
 execut

[Mesa-dev] [PATCH 33/48] meson: don't define GLX_USE_TLS for windows

[Dylan Baker]

Because the macros for exporting dll symbols and using TLS are mutually
exclusive.
---
 meson.build | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index bbcfb8ed8cb..a244694fd4a 100644
--- a/meson.build
+++ b/meson.build
@@ -327,7 +327,10 @@ if with_egl and not (with_platform_drm or 
with_platform_surfaceless)
   endif
 endif
 
-pre_args += '-DGLX_USE_TLS'
+if host_machine.system() != 'windows'
+  # On windows Thread local storage and dll export are mutually exclusive
+  pre_args += '-DGLX_USE_TLS'
+endif
 if with_glx != 'disabled'
   if not (with_platform_x11 and with_any_opengl)
 error('Cannot build GLX support without X11 platform support and at least 
one OpenGL API')
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 2/2] nir: add lowering for gl_HelperInvocation

[Roland Scheidegger]

Am 12.06.2018 um 00:32 schrieb Jason Ekstrand:
> On Wed, Jun 6, 2018 at 7:43 AM, Rob Clark  > wrote:
> 
> Signed-off-by: Rob Clark  >
> ---
> I can't say for sure that this will work on all drivers, but it is
> what the blob driver does, and it seems to make deqp happy.  I could
> move this to it's own pass inside ir3, but that seemed like overkill
> 
>  src/compiler/nir/nir.h                      | 10 ++
>  src/compiler/nir/nir_lower_system_values.c  | 17 +
>  src/gallium/drivers/freedreno/ir3/ir3_nir.c |  1 +
>  3 files changed, 28 insertions(+)
> 
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index 073ab4e82ea..de3d55d83af 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -1963,6 +1963,16 @@ typedef struct nir_shader_compiler_options {
>      */
>     bool lower_base_vertex;
> 
> +   /**
> +    * If enabled, gl_HelperInvocation will be lowered as:
> +    *
> +    *   !((1 << gl_SampleID) & gl_SampleMaskIN[0]))
> 
> 
> This only works for multi-sampling.  What about the single-sampled case?
It doesn't make sense to me for msaa neither.
gl_SampleID forces per-sample execution, which clearly isn't what you
want. Plus, gl_SampleMaskIN is specified to only contain bits for the
current shader invocation, so for msaa with forced per-sample execution
that would only contain the single bit corresponding to gl_SampleID
anyway (that is my interpretation at least - I know hw sample mask
inputs will probably always contains all the bits from rasterization,
regardless of gl_SampleID), so the "1 << gl_SampleID &" part will do
nothing at all. So I think that part is more about lowering the hw
rasterization sample mask to gl_SampleMaskIN rather than lowering to
gl_HelperInvocation.
But yes, !gl_SampleMaskIN should give gl_HelperInvocation - I think all
hw can give you raster sample mask even without msaa but I'm not
entirely sure if it's guaranteed to work in GL with single sampling
(similar for sample id, which should just be stuck at 0). But using the
gl names here looks very, very fishy to me here.

Roland




> 
> --Jason
> 
>  
> 
> +    *
> +    * TODO any hw w/ more than 32 samples?  For them (if they
> +    * used this option), a bit more math would be involved.
> +    */
> +   bool lower_helper_invocation;
> +
>     bool lower_cs_local_index_from_id;
> 
>     bool lower_device_index_to_zero;
> diff --git a/src/compiler/nir/nir_lower_system_values.c
> b/src/compiler/nir/nir_lower_system_values.c
> index 487da042620..6668cbb5dcd 100644
> --- a/src/compiler/nir/nir_lower_system_values.c
> +++ b/src/compiler/nir/nir_lower_system_values.c
> @@ -136,6 +136,23 @@ convert_block(nir_block *block, nir_builder *b)
>                                nir_load_first_vertex(b));
>           break;
> 
> +      case SYSTEM_VALUE_HELPER_INVOCATION:
> +         if (b->shader->options->lower_helper_invocation) {
> +            nir_ssa_def *tmp;
> +
> +            tmp = nir_ushr(b,
> +                           nir_imm_int(b, 1),
> +                           nir_load_sample_id(b));
> +
> +            tmp = nir_iand(b,
> +                           nir_load_sample_mask_in(b),
> +                           tmp);
> +
> +            sysval = nir_inot(b, nir_i2b(b, tmp));
> +         }
> +
> +         break;
> +
>        case SYSTEM_VALUE_INSTANCE_INDEX:
>           sysval = nir_iadd(b,
>                             nir_load_instance_id(b),
> diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
> b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
> index cd1f9c526f2..341d990b269 100644
> --- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
> +++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
> @@ -51,6 +51,7 @@ static const nir_shader_compiler_options options = {
>                 .lower_extract_byte = true,
>                 .lower_extract_word = true,
>                 .lower_all_io_to_temps = true,
> +               .lower_helper_invocation = true,
>  };
> 
>  struct nir_shader *
> -- 
> 2.17.0
> 
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> 
> 
> 
> 
> 
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[Mesa-dev] [PATCH 12/48] meson: don't allow glvnd on windows

[Dylan Baker]

---
 meson.build | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 1bdeeb95ec5..fb07c2dd0de 100644
--- a/meson.build
+++ b/meson.build
@@ -354,7 +354,9 @@ endif
 
 with_glvnd = get_option('glvnd')
 if with_glvnd
-  if with_glx == 'xlib' or with_glx == 'gallium-xlib'
+  if with_platform_windows
+error('glvnd cannot be used on Windows')
+  elif with_glx == 'xlib' or with_glx == 'gallium-xlib'
 error('Cannot build glvnd support for GLX that is not DRI based.')
   elif with_glx == 'disabled' and not with_egl
 error('glvnd requires DRI based GLX and/or EGL')
-- 
2.17.1

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[Mesa-dev] [PATCH 45/48] meson: allow python2 to be installed as python

[Dylan Baker]

On mac and Windows it may not be installed as python2, so search for
python as well. Also check that what we find actually is python2
---
 meson.build | 17 -
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index e1b3afbe688..6fd02dd4c6c 100644
--- a/meson.build
+++ b/meson.build
@@ -684,7 +684,22 @@ if with_platform_haiku
   pre_args += '-DHAVE_HAIKU_PLATFORM'
 endif
 
-prog_python2 = find_program('python2')
+if system_has_kms_drm
+  prog_python2 = find_program('python2')
+else
+  # Other OSes (windows and macos) often don't have a python2 binary, MacOS
+  # installs python2 as python, and doesn't provide python3 (thought it can be
+  # installed), and Windows provides neither, and the official packages provide
+  # python.exe for both python 2.x and 3.x.
+  #
+  # Check for both (in case someone has fixed their paths) and assert that the
+  # version is 2.7
+  prog_python2 = find_program('python2', 'python')
+  _py = run_command(prog_python2, ['--version'])
+  if not _py.stderr().contains('2.7')
+error('Python version is not 2.7.x! Actual: ' + _py.stderr())
+  endif
+endif
 has_mako = run_command(prog_python2, '-c', 'import mako')
 if has_mako.returncode() != 0
   error('Python (2.x) mako module required to build mesa.')
-- 
2.17.1

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[Mesa-dev] [PATCH 20/48] meson: build graw-gdi target

[Dylan Baker]

---
 src/gallium/meson.build  |  4 ++-
 src/gallium/targets/graw-gdi/meson.build | 36 
 2 files changed, 39 insertions(+), 1 deletion(-)
 create mode 100644 src/gallium/targets/graw-gdi/meson.build

diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 5019477788b..e4e0b88e7fc 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -197,7 +197,9 @@ if with_platform_windows
 endif
 if with_tests
   subdir('targets/graw-null')
-  if with_glx == 'gallium-xlib'
+  if with_platform_windows
+subdir('targets/graw-gdi')
+  elif with_glx == 'gallium-xlib'
 subdir('targets/graw-xlib')
   endif
   subdir('tests')
diff --git a/src/gallium/targets/graw-gdi/meson.build 
b/src/gallium/targets/graw-gdi/meson.build
new file mode 100644
index 000..e04b454ab53
--- /dev/null
+++ b/src/gallium/targets/graw-gdi/meson.build
@@ -0,0 +1,36 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+libgraw_gdi = shared_library(
+  'graw',
+  'graw_gdi.c',
+  include_directories : [
+inc_include, inc_src, inc_gallium, inc_gallium_aux, inc_gallium_drivers,
+inc_gallium_winsys_sw,
+  ],
+  link_with : [
+libgraw_util, libmesa_util, libgallium, libwsgdi,
+  ],
+  dependencies : [
+dep_ws2_32, driver_swrast,
+  ],
+)
+
+libgraw = libgraw_gdi
-- 
2.17.1

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[Mesa-dev] [PATCH 10/48] meson: Add a platform for windows

[Dylan Baker]

This mirrors the haiku build which uses a platform.
---
 meson.build   | 16 ++--
 meson_options.txt |  1 +
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/meson.build b/meson.build
index 634a7a21758..9c8b9ca9ba5 100644
--- a/meson.build
+++ b/meson.build
@@ -222,14 +222,24 @@ else
   with_dri_platform = 'none'
 endif
 
+with_platform_android = false
+with_platform_haiku = false
+with_platform_windows = false
+with_platform_wayland = false
+with_platform_x11 = false
+with_platform_drm = false
+with_platform_surfaceless = false
+egl_native_platform = ''
 _platforms = get_option('platforms')
 if _platforms.contains('auto')
   if system_has_kms_drm
 _platforms = ['x11', 'wayland', 'drm', 'surfaceless']
-  elif ['darwin', 'windows', 'cygwin'].contains(host_machine.system())
+  elif ['darwin', 'cygwin'].contains(host_machine.system())
 _platforms = ['x11', 'surfaceless']
   elif ['haiku'].contains(host_machine.system())
 _platforms = ['haiku']
+  elif host_machine.system() == 'windows'
+_platforms = ['windows']
   else
 error('Unknown OS. Please pass -Dplatforms to set platforms. Patches 
gladly accepted to fix this.')
   endif
@@ -241,6 +251,7 @@ with_platform_wayland = _platforms.contains('wayland')
 with_platform_drm = _platforms.contains('drm')
 with_platform_haiku = _platforms.contains('haiku')
 with_platform_surfaceless = _platforms.contains('surfaceless')
+with_platform_windows = _platforms.contains('windows')
 
 with_platforms = false
 if _platforms.length() != 0 and _platforms != ['']
@@ -365,7 +376,8 @@ if with_any_vk and (with_platform_x11 and not with_dri3)
   error('Vulkan drivers require dri3 for X11 support')
 endif
 if with_dri or with_gallium
-  if with_glx == 'disabled' and not with_egl and not with_platform_haiku
+  if (with_glx == 'disabled' and not with_egl and not with_platform_haiku and
+  not with_platform_windows)
 error('building dri or gallium drivers require at least one window system')
   endif
 endif
diff --git a/meson_options.txt b/meson_options.txt
index 28e92509198..ad06916fc40 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -24,6 +24,7 @@ option(
   value : ['auto'],
   choices : [
 '', 'auto', 'x11', 'wayland', 'drm', 'surfaceless', 'haiku', 'android',
+'windows',
   ],
   description : 'comma separated list of window systems to support. If this is 
set to auto all platforms applicable to the OS will be enabled.'
 )
-- 
2.17.1

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[Mesa-dev] [PATCH 07/48] glsl: fix general_ir_test with mingw

[Dylan Baker]

Somewhere down in the depths of the mingw headers 'interface' is
defined, change it to iface like a similar patch did.
---
 src/compiler/glsl/tests/general_ir_test.cpp | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/compiler/glsl/tests/general_ir_test.cpp 
b/src/compiler/glsl/tests/general_ir_test.cpp
index 57917f33734..c8bc16b7ad0 100644
--- a/src/compiler/glsl/tests/general_ir_test.cpp
+++ b/src/compiler/glsl/tests/general_ir_test.cpp
@@ -34,7 +34,7 @@ TEST(ir_variable_constructor, interface)
   glsl_struct_field(glsl_type::vec(4), "v")
};
 
-   const glsl_type *const interface =
+   const glsl_type *const iface =
   glsl_type::get_interface_instance(f,
 ARRAY_SIZE(f),
 GLSL_INTERFACE_PACKING_STD140,
@@ -44,12 +44,12 @@ TEST(ir_variable_constructor, interface)
static const char name[] = "named_instance";
 
ir_variable *const v =
-  new(mem_ctx) ir_variable(interface, name, ir_var_uniform);
+  new(mem_ctx) ir_variable(iface, name, ir_var_uniform);
 
EXPECT_STREQ(name, v->name);
EXPECT_NE(name, v->name);
-   EXPECT_EQ(interface, v->type);
-   EXPECT_EQ(interface, v->get_interface_type());
+   EXPECT_EQ(iface, v->type);
+   EXPECT_EQ(iface, v->get_interface_type());
 }
 
 TEST(ir_variable_constructor, interface_array)
@@ -60,7 +60,7 @@ TEST(ir_variable_constructor, interface_array)
   glsl_struct_field(glsl_type::vec(4), "v")
};
 
-   const glsl_type *const interface =
+   const glsl_type *const iface =
   glsl_type::get_interface_instance(f,
 ARRAY_SIZE(f),
 GLSL_INTERFACE_PACKING_STD140,
@@ -68,7 +68,7 @@ TEST(ir_variable_constructor, interface_array)
 "simple_interface");
 
const glsl_type *const interface_array =
-  glsl_type::get_array_instance(interface, 2);
+  glsl_type::get_array_instance(iface, 2);
 
static const char name[] = "array_instance";
 
@@ -78,5 +78,5 @@ TEST(ir_variable_constructor, interface_array)
EXPECT_STREQ(name, v->name);
EXPECT_NE(name, v->name);
EXPECT_EQ(interface_array, v->type);
-   EXPECT_EQ(interface, v->get_interface_type());
+   EXPECT_EQ(iface, v->get_interface_type());
 }
-- 
2.17.1

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[Mesa-dev] [PATCH 44/48] meson: add windows specific linker flags

[Dylan Baker]

---
 meson.build | 21 +
 1 file changed, 21 insertions(+)

diff --git a/meson.build b/meson.build
index a244694fd4a..e1b3afbe688 100644
--- a/meson.build
+++ b/meson.build
@@ -847,6 +847,27 @@ else
   endforeach
 endif
 
+# set linker arguments
+if host_machine.system() == 'windows'
+  if cc.get_id() == 'msvc'
+add_project_link_arguments(
+  '/fixed:no',
+  '/incremental:no',
+  '/dynamicbase',
+  '/nxcompat',
+  language : ['c', 'cpp'],
+)
+  else
+add_project_link_arguments(
+  '-Wl,--nxcompat',
+  '-Wl,--dynamicbase',
+  '-static-libgcc',
+  '-static-libstdc++',
+  language : ['c', 'cpp'],
+)
+  endif
+endif
+
 if host_machine.cpu_family().startswith('x86') and cc.get_id() != 'msvc'
   pre_args += '-DUSE_SSE41'
   with_sse41 = true
-- 
2.17.1

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[Mesa-dev] [PATCH 15/48] meson: Add windows defines to glapi

[Dylan Baker]

These are needed to control the export or symbols due to differences
between the way windows and *nix handle symbol exports.
---
 src/mapi/es1api/meson.build   | 10 +-
 src/mapi/es2api/meson.build   | 10 +-
 src/mapi/glapi/meson.build| 13 -
 src/mapi/shared-glapi/meson.build |  9 -
 4 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/src/mapi/es1api/meson.build b/src/mapi/es1api/meson.build
index 657dc2d9eff..dcf0aa57492 100644
--- a/src/mapi/es1api/meson.build
+++ b/src/mapi/es1api/meson.build
@@ -27,11 +27,19 @@ es1_glapi_mapi_tmp_h = custom_target(
   capture : true,
 )
 
+_es1_c_args = []
+if with_platform_windows
+  _es1_c_args += ['-D_GDI32_', '-DBUILD_GL32']
+endif
+
 libglesv1_cm = shared_library(
   'GLESv1_CM',
   ['../entry.c', es1_glapi_mapi_tmp_h],
   c_args : [
-c_msvc_compat_args, c_vis_args, '-DMAPI_MODE_BRIDGE',
+c_msvc_compat_args,
+c_vis_args,
+_es1_c_args,
+'-DMAPI_MODE_BRIDGE',
 '-DMAPI_ABI_HEADER="@0@"'.format(es1_glapi_mapi_tmp_h.full_path()),
   ],
   link_args : [ld_args_gc_sections],
diff --git a/src/mapi/es2api/meson.build b/src/mapi/es2api/meson.build
index da5198ed6e8..abd633fbb6b 100644
--- a/src/mapi/es2api/meson.build
+++ b/src/mapi/es2api/meson.build
@@ -27,11 +27,19 @@ es2_glapi_mapi_tmp_h = custom_target(
   capture : true,
 )
 
+_es2_c_args = []
+if with_platform_windows
+  _es2_c_args += ['-D_GDI32_', '-DBUILD_GL32']
+endif
+
 libgles2 = shared_library(
   'GLESv2',
   ['../entry.c', es2_glapi_mapi_tmp_h],
   c_args : [
-c_msvc_compat_args, c_vis_args, '-DMAPI_MODE_BRIDGE',
+c_msvc_compat_args,
+c_vis_args,
+_es2_c_args,
+'-DMAPI_MODE_BRIDGE',
 '-DMAPI_ABI_HEADER="@0@"'.format(es2_glapi_mapi_tmp_h.full_path()),
   ],
   link_args : [ld_args_gc_sections],
diff --git a/src/mapi/glapi/meson.build b/src/mapi/glapi/meson.build
index e241d9ed388..854a04e6549 100644
--- a/src/mapi/glapi/meson.build
+++ b/src/mapi/glapi/meson.build
@@ -25,7 +25,7 @@ inc_glapi = include_directories('.')
 static_glapi_files = []
 static_glapi_args = []
 
-if ['apple', 'windows'].contains(with_dri_platform)
+if with_dri and ['apple', 'windows'].contains(with_dri_platform)
   static_glapi_files += [glapi_gentable_c, glapitable_h]
 endif
 
@@ -45,8 +45,19 @@ if with_shared_glapi
 '-DMAPI_MODE_BRIDGE',
 '-DMAPI_ABI_HEADER="@0@"'.format(glapi_mapi_tmp_h.full_path()),
   ]
+  if with_platform_windows
+static_glapi_args += ['-D_GDI32_', '-DBUILD_GL32']
+  endif
 else
   static_glapi_args += '-DMAPI_MODE_UTIL'
+  if with_platform_windows
+static_glapi_args += ['-D_GDI32_', '-DBUILD_GL32', '-DKHRONOS_DLL_EXPORTS']
+if with_gles1 or with_gles2
+  static_glapi_args += '-D_GLAPI_DLL_EXPORTS'
+else
+  static_glapi_args += '-D_GLAPI_NO_EXPORTS'
+endif
+  endif
   static_glapi_files += files(
 'glapi_dispatch.c',
 'glapi_entrypoint.c',
diff --git a/src/mapi/shared-glapi/meson.build 
b/src/mapi/shared-glapi/meson.build
index c7d136ced2c..e1f68691b48 100644
--- a/src/mapi/shared-glapi/meson.build
+++ b/src/mapi/shared-glapi/meson.build
@@ -36,11 +36,18 @@ shared_glapi_mapi_tmp_h = custom_target(
   capture : true,
 )
 
+_glapi_c_args = []
+if with_platform_windows
+  _glapi_c_args += ['-D_GLAPI_DLL_EXPORTS']
+endif
+
 libglapi = shared_library(
   'glapi',
   [files_mapi_glapi, files_mapi_util, shared_glapi_mapi_tmp_h],
   c_args : [
-c_msvc_compat_args, '-DMAPI_MODE_GLAPI',
+_glapi_c_args,
+c_msvc_compat_args,
+'-DMAPI_MODE_GLAPI',
 '-DMAPI_ABI_HEADER="@0@"'.format(shared_glapi_mapi_tmp_h.full_path()),
   ],
   link_args : [ld_args_gc_sections],
-- 
2.17.1

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[Mesa-dev] [PATCH 41/48] meson: Fix gtest linkage on msvc

[Dylan Baker]

We need to add an extra flag (/SUBSYSTEM:CONSOLE) to get the msvc linker
to find main() in a static library.
---
 src/gtest/meson.build | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/gtest/meson.build b/src/gtest/meson.build
index 91a49240416..ed0d6974bd3 100644
--- a/src/gtest/meson.build
+++ b/src/gtest/meson.build
@@ -25,7 +25,14 @@ libgtest = static_library(
   build_by_default : false,
 )
 
+_gtest_link_args = []
+if cpp.get_id() == 'msvc'
+  # required to use main() from a static library
+  _gtest_link_args += '/SUBSYSTEM:CONSOLE'
+endif
+
 idep_gtest = declare_dependency(
   link_with : libgtest,
+  link_args : _gtest_link_args,
   include_directories : include_directories('include', is_system : true),
 )
-- 
2.17.1

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[Mesa-dev] [PATCH 19/48] meson: build libgl-gdi target

[Dylan Baker]

---
 src/gallium/meson.build   |  1 +
 src/gallium/targets/libgl-gdi/meson.build | 44 +++
 2 files changed, 45 insertions(+)
 create mode 100644 src/gallium/targets/libgl-gdi/meson.build

diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index a4f28dc4757..5019477788b 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -193,6 +193,7 @@ if with_gallium_st_nine
 endif
 if with_platform_windows
   subdir('state_trackers/wgl')
+  subdir('targets/libgl-gdi')
 endif
 if with_tests
   subdir('targets/graw-null')
diff --git a/src/gallium/targets/libgl-gdi/meson.build 
b/src/gallium/targets/libgl-gdi/meson.build
new file mode 100644
index 000..63cc40b97bc
--- /dev/null
+++ b/src/gallium/targets/libgl-gdi/meson.build
@@ -0,0 +1,44 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+if cc.get_id() == 'gcc' and host_machine.cpu_family() == 'x86_64'
+  ogldef = files('../../state_trackers/wgl/opengl32.mingw.def')[0]
+else
+  ogldef = files('../../state_trackers/wgl/opengl32.def')[0]
+endif
+
+libopengl32 = shared_library(
+  'opengl32',
+  ['libgl_gdi.c'],
+  vs_module_defs : ogldef,
+  include_directories : [
+inc_common, inc_wgl, inc_gallium_winsys_sw, inc_gallium_drivers,
+  ],
+  link_whole : [libwgl],
+  link_with : [
+libmesa_util, libgallium, libglsl, libmesa_gallium, libwsgdi,
+libglapi_static, libglapi
+  ],
+  dependencies : [
+dep_ws2_32, idep_nir, driver_swrast, driver_swr,
+  ],
+  name_prefix : '',  # otherwise mingw will create libopengl32.dll
+  install : true,
+)
-- 
2.17.1

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[Mesa-dev] [PATCH 16/48] meson: Add necessary defines for mesa_gallium on windows

[Dylan Baker]

---
 src/mesa/meson.build | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/mesa/meson.build b/src/mesa/meson.build
index cba361c0988..c1606b4551e 100644
--- a/src/mesa/meson.build
+++ b/src/mesa/meson.build
@@ -716,11 +716,19 @@ libmesa_classic = static_library(
   build_by_default : false,
 )
 
+_mesa_gallium_args = []
+if with_platform_windows
+  _mesa_gallium_args += ['-D_GDI32_', '-DBUILD_GL32']
+  if not with_gles2
+_mesa_gallium_args += '-D_GLAPI_NO_EXPORTS'
+  endif
+endif
+
 libmesa_gallium = static_library(
   'mesa_gallium',
   [files_libmesa_common, files_libmesa_gallium],
-  c_args : [c_vis_args, c_msvc_compat_args],
-  cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
+  c_args : [c_vis_args, c_msvc_compat_args, _mesa_gallium_args],
+  cpp_args : [cpp_vis_args, cpp_msvc_compat_args, _mesa_gallium_args],
   include_directories : [inc_common, include_directories('main')],
   link_with : [libglsl, libmesa_sse41],
   dependencies : [idep_nir_headers, dep_vdpau],
-- 
2.17.1

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[Mesa-dev] [PATCH 21/48] meson: fix gallium-osmesa to build for windows

[Dylan Baker]

---
 src/gallium/state_trackers/osmesa/meson.build | 12 ++--
 src/gallium/targets/osmesa/meson.build|  9 -
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/src/gallium/state_trackers/osmesa/meson.build 
b/src/gallium/state_trackers/osmesa/meson.build
index 912a6226f74..26ec8084f93 100644
--- a/src/gallium/state_trackers/osmesa/meson.build
+++ b/src/gallium/state_trackers/osmesa/meson.build
@@ -1,4 +1,4 @@
-# Copyright © 2017 Intel Corporation
+# Copyright © 2017-2018 Intel Corporation
 
 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
@@ -18,10 +18,18 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
+osmesa_st_c_args = []
+if with_platform_windows
+  osmesa_st_c_args += ['-DBUILD_GL32', '-DWIN32_LEAN_AND_MEAN']
+  if not with_gles1
+osmesa_st_c_args += ['-D_GLAPI_NO_EXPORTS']
+  endif
+endif
+
 libosmesa_st = static_library(
   'osmesa_st',
   'osmesa.c',
-  c_args : ['-DGALLIUM_SOFTPIPE'],
+  c_args : osmesa_st_c_args,
   include_directories : [
 inc_include, inc_src, inc_gallium, inc_gallium_aux, inc_mapi, inc_mesa,
   ],
diff --git a/src/gallium/targets/osmesa/meson.build 
b/src/gallium/targets/osmesa/meson.build
index b4ae8f4b6ec..1e866124b1d 100644
--- a/src/gallium/targets/osmesa/meson.build
+++ b/src/gallium/targets/osmesa/meson.build
@@ -32,12 +32,19 @@ if with_ld_version_script
   osmesa_link_deps += files('osmesa.sym')
 endif
 
+if cc.get_id() == 'gcc' and host_machine.cpu_family() != 'x86_64'
+  osmesa_def = 'osmesa.mingw.def'
+else
+  osmesa_def = 'osmesa.def'
+endif
+
 libosmesa = shared_library(
   osmesa_lib_name,
   'target.c',
   c_args : [c_vis_args],
   cpp_args : cpp_vis_args,
   link_args : [ld_args_gc_sections, osmesa_link_args],
+  vs_module_defs : osmesa_def,
   include_directories : [
 inc_include, inc_src, inc_gallium, inc_gallium_aux, inc_gallium_winsys,
 inc_gallium_drivers,
@@ -48,7 +55,7 @@ libosmesa = shared_library(
 libmesa_gallium, libgallium, libglapi_static, libws_null, osmesa_link_with,
   ],
   dependencies : [
-dep_selinux, dep_thread, dep_clock, dep_unwind,
+dep_ws2_32, dep_selinux, dep_thread, dep_clock, dep_unwind,
 driver_swrast, driver_swr,
   ],
   version : '8.0.0',
-- 
2.17.1

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[Mesa-dev] [PATCH 18/48] meson: build wgl state tracker

[Dylan Baker]

---
 src/gallium/meson.build|  3 ++
 src/gallium/state_trackers/wgl/meson.build | 50 ++
 2 files changed, 53 insertions(+)
 create mode 100644 src/gallium/state_trackers/wgl/meson.build

diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 7754dbdee3c..a4f28dc4757 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -191,6 +191,9 @@ if with_gallium_st_nine
   subdir('state_trackers/nine')
   subdir('targets/d3dadapter9')
 endif
+if with_platform_windows
+  subdir('state_trackers/wgl')
+endif
 if with_tests
   subdir('targets/graw-null')
   if with_glx == 'gallium-xlib'
diff --git a/src/gallium/state_trackers/wgl/meson.build 
b/src/gallium/state_trackers/wgl/meson.build
new file mode 100644
index 000..d78d2b02e83
--- /dev/null
+++ b/src/gallium/state_trackers/wgl/meson.build
@@ -0,0 +1,50 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+inc_wgl = include_directories('.')
+
+libwgl = static_library(
+  'wgl',
+  files(
+'stw_context.c',
+'stw_device.c',
+'stw_ext_context.c',
+'stw_ext_extensionsstring.c',
+'stw_ext_pbuffer.c',
+'stw_ext_pixelformat.c',
+'stw_ext_rendertexture.c',
+'stw_ext_swapinterval.c',
+'stw_framebuffer.c',
+'stw_getprocaddress.c',
+'stw_nopfuncs.c',
+'stw_nopfuncs.h',
+'stw_pixelformat.c',
+'stw_st.c',
+'stw_tls.c',
+'stw_wgl.c',
+  ),
+  c_args : [
+'-D_GDI32_', '-DBUILD_GL32', '-DWIN32_LEAN_AND_MEAN',
+'-D_GLAPI_NO_EXPORTS', # XXX: only without gles
+  ],
+  include_directories : [
+inc_include, inc_src, inc_gallium, inc_gallium_aux, inc_mapi, inc_mesa,
+  ],
+)
-- 
2.17.1

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[Mesa-dev] [PATCH 17/48] meson: build gallium gdi winsys

[Dylan Baker]

---
 src/gallium/meson.build   |  6 ++
 src/gallium/winsys/sw/gdi/meson.build | 27 +++
 2 files changed, 33 insertions(+)
 create mode 100644 src/gallium/winsys/sw/gdi/meson.build

diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 561af9d339c..7754dbdee3c 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -21,6 +21,7 @@
 
 inc_gallium_drivers = include_directories('drivers')
 inc_gallium_winsys = include_directories('winsys')
+inc_gallium_winsys_sw = include_directories('winsys/sw')
 
 subdir('auxiliary')
 subdir('auxiliary/pipe-loader')
@@ -35,6 +36,11 @@ if with_gallium_drisw_kms
 else
   libswkmsdri = []
 endif
+if with_platform_windows
+  subdir('winsys/sw/gdi')
+else
+  libwsgdi = []
+endif
 subdir('winsys/sw/wrapper')
 if with_platform_haiku
   subdir('winsys/sw/hgl')
diff --git a/src/gallium/winsys/sw/gdi/meson.build 
b/src/gallium/winsys/sw/gdi/meson.build
new file mode 100644
index 000..ac6c7cf0aa2
--- /dev/null
+++ b/src/gallium/winsys/sw/gdi/meson.build
@@ -0,0 +1,27 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+libwsgdi = static_library(
+  'wsgdi',
+  'gdi_sw_winsys.c',
+  include_directories : [
+inc_src, inc_include, inc_gallium, inc_gallium_aux, inc_gallium_drivers,
+  ],
+)
-- 
2.17.1

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[Mesa-dev] [PATCH 48/48] tests/vma: fix build with MSVC

[Dylan Baker]

---
 src/util/tests/vma/vma_random_test.cpp | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/util/tests/vma/vma_random_test.cpp 
b/src/util/tests/vma/vma_random_test.cpp
index de887fead30..26914a56d2c 100644
--- a/src/util/tests/vma/vma_random_test.cpp
+++ b/src/util/tests/vma/vma_random_test.cpp
@@ -34,7 +34,15 @@
 #include 
 #include 
 
+#ifndef _WIN32
 #include 
+#else
+#define errx(code, msg, ...) \
+   do {  \
+  fprintf(stderr, msg, __VA_ARGS__); \
+  exit(code);\
+   } while (0);
+#endif
 
 #include "vma.h"
 
-- 
2.17.1

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[Mesa-dev] [PATCH 37/48] glsl/tests: define ssize_t on windows

[Dylan Baker]

---
 src/compiler/glsl/tests/blob_test.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/compiler/glsl/tests/blob_test.c 
b/src/compiler/glsl/tests/blob_test.c
index 1cc97236e7e..21b8b1efdc1 100644
--- a/src/compiler/glsl/tests/blob_test.c
+++ b/src/compiler/glsl/tests/blob_test.c
@@ -28,6 +28,10 @@
 #include 
 #include 
 #include 
+#ifdef _MSC_VER
+#include 
+typedef SSIZE_T ssize_t;
+#endif
 
 #include "util/ralloc.h"
 #include "blob.h"
-- 
2.17.1

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[Mesa-dev] [PATCH 22/48] meson: Don't check for posix_memalign on windows

[Dylan Baker]

There's a mingw bug for this, it exports __builtin_posix_memalign but
not posix_memalign, so the check will succeed, but compiling will fail.
---
 meson.build | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/meson.build b/meson.build
index ed63276b63e..0b0203bc03d 100644
--- a/meson.build
+++ b/meson.build
@@ -966,13 +966,22 @@ foreach h : ['xlocale.h', 'sys/sysctl.h', 
'linux/futex.h', 'endian.h']
 pre_args += '-DHAVE_@0@'.format(h.to_upper().underscorify())
   endif
 endforeach
-
-foreach f : ['strtof', 'mkostemp', 'posix_memalign', 'timespec_get', 
'memfd_create']
+foreach f : ['strtof', 'mkostemp', 'timespec_get', 'memfd_create']
   if cc.has_function(f)
 pre_args += '-DHAVE_@0@'.format(f.to_upper())
   endif
 endforeach
 
+# MinGW provides a __builtin_posix_memalign function, but not a posix_memalign.
+# This means that this check will succeed, but then compilation will later
+# fail. MSVC doesn't have this function at all, so only check for it on
+# non-windows platforms.
+if host_machine.system() != 'windows'
+  if cc.has_function('posix_memalign')
+pre_args += '-DHAVE_POSIX_MEMALIGN'
+  endif
+endif
+
 # strtod locale support
 if cc.links('''
 #define _GNU_SOURCE
-- 
2.17.1

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[Mesa-dev] [PATCH 23/48] meson: Add support for wrapping llvm

[Dylan Baker]

For building on Windows (when not using cygwin), the assumption is that
LLVM will have to be handled via a binary wrap. In this case the user
wanting to use LLVM is this way will need to create a directory in
subprojects (any name is fine), and pass that name via the -Dllvm-wrap
option (for example, assuming subprojects/llvm, -Dllvm-wrap=llvm), which
must have a meson.build file and the installed LLVM to link with (this
can be either static or dynamic). There is documentation for what this
needs to look like and how to define it.
---
 docs/meson.html   |  66 +
 meson.build   | 128 ++
 meson_options.txt |   6 +
 .../drivers/swr/rasterizer/jitter/meson.build |  13 +-
 4 files changed, 154 insertions(+), 59 deletions(-)

diff --git a/docs/meson.html b/docs/meson.html
index 29907a60a9c..6697dbb34ef 100644
--- a/docs/meson.html
+++ b/docs/meson.html
@@ -132,6 +132,72 @@ dependency interface. It will search $PATH 
(or %PATH%
 llvm-config, so using an LLVM from a non-standard path is as easy as
 PATH=/path/with/llvm-config:$PATH meson build.
 
+
+On windows (and in other cases), using llvm-config is either undesirable
+or impossible. Meson's solution for this is a
+http://mesonbuild.com/Wrap-dependency-system-manual.html";>wrap, in
+this case a "binary wrap". Follow the steps below:
+
+Install the binaries and headers into a directory under the 
$mesa_src/subprojects
+Add a meson build.build file to that directory (more on that 
later)
+add -Dllvm-wrap=$directory to your meson configuration (where 
$directory is the the directory under subprojects
+
+
+The wrap file must define the following:
+
+ext_llvm: a declare_dependency() object with include_directories, 
dependencies, and version set)
+
+
+It may also define:
+
+irbuilder_h: a file() object pointing to llvm/IR/IRBuilder.h (for 
SWR)
+
+
+such a meson.build file might look like:
+
+project('llvm', ['cpp'])
+
+cpp = meson.get_compiler('cpp')
+
+_deps = []
+_search = join_paths(meson.current_source_dir(), 'lib')
+foreach d : ['libLLVMCodeGen', 'libLLVMScalarOpts', 'libLLVMAnalysis',
+ 'libLLVMTransformUtils', 'libLLVMCore', 'libLLVMX86CodeGen',
+ 'libLLVMSelectionDAG', 'libLLVMipo', 'libLLVMAsmPrinter',
+ 'libLLVMInstCombine', 'libLLVMInstrumentation', 'libLLVMMC',
+ 'libLLVMGlobalISel', 'libLLVMObjectYAML', 'libLLVMDebugInfoPDB',
+ 'libLLVMVectorize', 'libLLVMPasses', 'libLLVMSupport',
+ 'libLLVMLTO', 'libLLVMObject', 'libLLVMDebugInfoCodeView',
+ 'libLLVMDebugInfoDWARF', 'libLLVMOrcJIT', 'libLLVMProfileData',
+ 'libLLVMObjCARCOpts', 'libLLVMBitReader', 'libLLVMCoroutines',
+ 'libLLVMBitWriter', 'libLLVMRuntimeDyld', 'libLLVMMIRParser',
+ 'libLLVMX86Desc', 'libLLVMAsmParser', 'libLLVMTableGen',
+ 'libLLVMFuzzMutate', 'libLLVMLinker', 'libLLVMMCParser',
+ 'libLLVMExecutionEngine', 'libLLVMCoverage', 'libLLVMInterpreter',
+ 'libLLVMTarget', 'libLLVMX86AsmParser', 'libLLVMSymbolize',
+ 'libLLVMDebugInfoMSF', 'libLLVMMCJIT', 'libLLVMXRay',
+ 'libLLVMX86AsmPrinter', 'libLLVMX86Disassembler',
+ 'libLLVMMCDisassembler', 'libLLVMOption', 'libLLVMIRReader',
+ 'libLLVMLibDriver', 'libLLVMDlltoolDriver', 'libLLVMDemangle',
+ 'libLLVMBinaryFormat', 'libLLVMLineEditor',
+ 'libLLVMWindowsManifest', 'libLLVMX86Info', 'libLLVMX86Utils']
+  _deps += cpp.find_library(d, dirs : _search)
+endforeach
+
+ext_llvm = declare_dependency(
+  include_directories : include_directories('include'),
+  dependencies : _deps,
+  version : '6.0.0',
+)
+
+irbuilder_h = files('include/llvm/IR/IRBuilder.h')
+
+
+It is very important that version is defined and is accurate, if it is not,
+workarounds for the wrong version of LLVM might be used resulting in build
+failures.
+
+
 
 
 
diff --git a/meson.build b/meson.build
index 0b0203bc03d..67577241953 100644
--- a/meson.build
+++ b/meson.build
@@ -1145,20 +1145,6 @@ if dep_libdrm.found()
   endif
 endif
 
-llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
-if with_amd_vk or with_gallium_radeonsi or with_gallium_r600
-  llvm_modules += ['amdgpu', 'bitreader', 'ipo']
-  if with_gallium_r600
-llvm_modules += 'asmparser'
-  endif
-endif
-if with_gallium_opencl
-  llvm_modules += [
-'all-targets', 'linker', 'coverage', 'instrumentation', 'ipo', 'irreader',
-'lto', 'option', 'objcarcopts', 'profiledata',
-  ]
-  # TODO: optional modules
-endif
 
 if with_amd_vk or with_gallium_radeonsi
   _llvm_version = '>= 5.0.0'
@@ -1171,51 +1157,85 @@ else
 endif
 
 _llvm = get_option('llvm')
-if _llvm == 'auto'
-  dep_llvm = dependency(
-'llvm', version : _llvm_version, modules : llvm_modules,
-required : with_amd_vk or with_gallium_radeonsi or with_gallium_swr or 
with_gall

[Mesa-dev] [PATCH 42/48] meson: disable graw tests on mingw

[Dylan Baker]

I can't figure out why symbols are being exposed that shouldn't.
---
 src/gallium/tests/meson.build | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/gallium/tests/meson.build b/src/gallium/tests/meson.build
index 15b9f549647..1d08da2ac10 100644
--- a/src/gallium/tests/meson.build
+++ b/src/gallium/tests/meson.build
@@ -25,4 +25,8 @@ endif
 if with_gallium_softpipe
   subdir('unit')
 endif
-subdir('graw')
+if host_machine.system() == 'windows' and cpp.get_id() != 'gcc'
+  # This has linking errors I can't figure out with MinGW. works fine with
+  # MSVC, works fine with GCC on Linux.
+  subdir('graw')
+endif
-- 
2.17.1

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[Mesa-dev] [PATCH 27/48] meson: don't look for rt on windows

[Dylan Baker]

---
 meson.build | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 67577241953..42e2540146c 100644
--- a/meson.build
+++ b/meson.build
@@ -1053,7 +1053,9 @@ elif with_dri_i965 and get_option('shader-cache')
 endif
 
 # Determine whether or not the rt library is needed for time functions
-if cc.has_function('clock_gettime')
+if host_machine.system() == 'windows'
+  dep_clock = null_dep
+elif cc.has_function('clock_gettime')
   dep_clock = null_dep
 else
   dep_clock = cc.find_library('rt')
-- 
2.17.1

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[Mesa-dev] [PATCH 47/48] appveyor: use chocolatey (cinst) to isntall winflexbixon

[Dylan Baker]

---
 appveyor.yml | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/appveyor.yml b/appveyor.yml
index 06063feba93..f544314e730 100644
--- a/appveyor.yml
+++ b/appveyor.yml
@@ -34,13 +34,11 @@ branches:
 clone_depth: 100
 
 cache:
-- win_flex_bison-2.5.9.zip
 - llvm-3.3.1-msvc2015-mtd.7z
 
 os: Visual Studio 2015
 
 environment:
-  WINFLEXBISON_ARCHIVE: win_flex_bison-2.5.9.zip
   LLVM_ARCHIVE: llvm-3.3.1-msvc2015-mtd.7z
   matrix:
 - BUILD_SYSTEM: meson
@@ -63,9 +61,7 @@ install:
 - if "%BUILD_SYSTEM%"=="meson" ninja --version
 - if "%BUILD_SYSTEM%"=="meson" call "C:\Program Files (x86)\Microsoft Visual 
Studio 14.0\VC\vcvarsall.bat" x86_amd64
 # Install flex/bison
-- if not exist "%WINFLEXBISON_ARCHIVE%" appveyor DownloadFile 
"https://downloads.sourceforge.net/project/winflexbison/old_versions/%WINFLEXBISON_ARCHIVE%";
-- 7z x -y -owinflexbison\ "%WINFLEXBISON_ARCHIVE%" > nul
-- set Path=%CD%\winflexbison;%Path%
+- cinst -y winflexbison
 - win_flex --version
 - win_bison --version
 # Download and extract LLVM
-- 
2.17.1

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[Mesa-dev] [PATCH 29/48] meson: don't look for nm binary on windows

[Dylan Baker]

---
 meson.build | 5 -
 src/mapi/es1api/meson.build | 2 +-
 src/mapi/es2api/meson.build | 2 +-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/meson.build b/meson.build
index f3e9676f8bf..abe45e933ba 100644
--- a/meson.build
+++ b/meson.build
@@ -1468,8 +1468,11 @@ endif
 
 pkg = import('pkgconfig')
 
+prog_nm = find_program('nm', required : false)
 env_test = environment()
-env_test.set('NM', find_program('nm').path())
+if prog_nm.found()
+  env_test.set('NM', prog_nm.path())
+endif
 
 subdir('include')
 subdir('bin')
diff --git a/src/mapi/es1api/meson.build b/src/mapi/es1api/meson.build
index dcf0aa57492..448cf1c73d2 100644
--- a/src/mapi/es1api/meson.build
+++ b/src/mapi/es1api/meson.build
@@ -59,7 +59,7 @@ pkg.generate(
   libraries_private : gl_priv_libs,
 )
 
-if with_tests
+if with_tests and prog_nm.found()
   test(
 'es1-ABI-check',
 find_program('ABI-check'),
diff --git a/src/mapi/es2api/meson.build b/src/mapi/es2api/meson.build
index abd633fbb6b..cb6a70a2e90 100644
--- a/src/mapi/es2api/meson.build
+++ b/src/mapi/es2api/meson.build
@@ -59,7 +59,7 @@ pkg.generate(
   libraries_private : gl_priv_libs,
 )
 
-if with_tests
+if with_tests and prog_nm.found()
   test(
 'es2-ABI-check',
 find_program('ABI-check'),
-- 
2.17.1

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[Mesa-dev] [PATCH 40/48] meosn: don't build gallium trivial tests on windows

[Dylan Baker]

They require the pipe-loaders, which require xmlconfig, which doesn't
build with msvc.
---
 src/gallium/tests/meson.build | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/tests/meson.build b/src/gallium/tests/meson.build
index 0ee04350c87..15b9f549647 100644
--- a/src/gallium/tests/meson.build
+++ b/src/gallium/tests/meson.build
@@ -18,7 +18,10 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-subdir('trivial')
+if not with_platform_windows
+  # pipe-loader doesn't build on windows.
+  subdir('trivial')
+endif
 if with_gallium_softpipe
   subdir('unit')
 endif
-- 
2.17.1

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[Mesa-dev] [PATCH 38/48] nir/meson: fix c vs cpp args for nir test

[Dylan Baker]

---
 src/compiler/nir/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 598c68aff9f..b6677ae7793 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -231,7 +231,7 @@ if with_tests
 executable(
   'nir_control_flow_test',
   files('tests/control_flow_tests.cpp'),
-  c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
+  cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
   include_directories : [inc_common],
   dependencies : [dep_thread, idep_gtest, idep_nir],
   link_with : libmesa_util,
-- 
2.17.1

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[Mesa-dev] [PATCH 32/48] meson: add switches for SWR with MSVC

[Dylan Baker]

---
 src/gallium/drivers/swr/meson.build | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/meson.build 
b/src/gallium/drivers/swr/meson.build
index b95c8bc1bf8..ec4d80e4bb2 100644
--- a/src/gallium/drivers/swr/meson.build
+++ b/src/gallium/drivers/swr/meson.build
@@ -191,6 +191,7 @@ swr_arch_defines = []
 
 swr_avx_args = cpp.first_supported_argument(
   '-target-cpu=sandybridge', '-mavx', '-march=core-avx', '-tp=sandybridge',
+  '/arch:AVX',
   prefix : '''
 #if !defined(__AVX__)
 # error
@@ -215,7 +216,7 @@ endif
 
 if with_swr_arches.contains('avx2')
   swr_avx2_args = cpp.first_supported_argument(
-'-target-cpu=haswell', '-march=core-avx2', '-tp=haswell',
+'-target-cpu=haswell', '-march=core-avx2', '-tp=haswell', '/arch:AVX2',
 prefix : '''
   #if !defined(__AVX2__)
   # error
-- 
2.17.1

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[Mesa-dev] [PATCH 31/48] meson: disable sse4.1 optimizations with msvc

[Dylan Baker]

There isn't an obvious command line switch here, /arch:AVX *might* be
the right thing, but meson doesn't know what to do here either and
leaves the -msse4.1 and -mstackrealign.
---
 meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index abe45e933ba..bbcfb8ed8cb 100644
--- a/meson.build
+++ b/meson.build
@@ -844,7 +844,7 @@ else
   endforeach
 endif
 
-if host_machine.cpu_family().startswith('x86')
+if host_machine.cpu_family().startswith('x86') and cc.get_id() != 'msvc'
   pre_args += '-DUSE_SSE41'
   with_sse41 = true
   sse41_args = ['-msse4.1']
-- 
2.17.1

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[Mesa-dev] [PATCH 02/48] add a git ignore for subprojects

[Dylan Baker]

---
 subprojects/.gitignore | 3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 subprojects/.gitignore

diff --git a/subprojects/.gitignore b/subprojects/.gitignore
new file mode 100644
index 000..68a882edba6
--- /dev/null
+++ b/subprojects/.gitignore
@@ -0,0 +1,3 @@
+*
+!*.wrap
+!.gitignore
-- 
2.17.1

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[Mesa-dev] [PATCH 34/48] meson: Add idep_getopt for tests

[Dylan Baker]

There are quite a few tests that require getopt, when using MSVC we need
to use the bundled version of getopt since there isn't a system version.
---
 src/compiler/glsl/glcpp/meson.build | 2 +-
 src/compiler/glsl/meson.build   | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/compiler/glsl/glcpp/meson.build 
b/src/compiler/glsl/glcpp/meson.build
index 80f51a3e48e..3ab8ddee7f0 100644
--- a/src/compiler/glsl/glcpp/meson.build
+++ b/src/compiler/glsl/glcpp/meson.build
@@ -58,7 +58,7 @@ libglcpp = static_library(
 glcpp = executable(
   'glcpp',
   'glcpp.c',
-  dependencies : [dep_m],
+  dependencies : [dep_m, idep_getopt],
   include_directories : [inc_common],
   link_with : [libglcpp, libglsl_util],
   c_args : [c_vis_args, no_override_init_args, c_msvc_compat_args],
diff --git a/src/compiler/glsl/meson.build b/src/compiler/glsl/meson.build
index 055a84714c1..238b5815f6f 100644
--- a/src/compiler/glsl/meson.build
+++ b/src/compiler/glsl/meson.build
@@ -222,7 +222,7 @@ libglsl_standalone = static_library(
   cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
   include_directories : [inc_common],
   link_with : [libglsl, libglsl_util, libmesa_util],
-  dependencies : [dep_thread],
+  dependencies : [dep_thread, idep_getopt],
   build_by_default : false,
 )
 
@@ -231,7 +231,7 @@ glsl_compiler = executable(
   'main.cpp',
   c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
   cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
-  dependencies : [dep_clock, dep_thread],
+  dependencies : [dep_clock, dep_thread, idep_getopt],
   include_directories : [inc_common],
   link_with : [libglsl_standalone],
   build_by_default : with_tools.contains('glsl'),
@@ -245,7 +245,7 @@ glsl_test = executable(
   c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
   cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
   include_directories : [inc_common],
-  dependencies : [dep_clock, dep_thread],
+  dependencies : [dep_clock, dep_thread, idep_getopt],
   link_with : [libglsl, libglsl_standalone, libglsl_util],
   build_by_default : with_tools.contains('glsl'),
   install : with_tools.contains('glsl'),
-- 
2.17.1

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[Mesa-dev] [PATCH 26/48] meson: fix pipe-loader compilation for windows

[Dylan Baker]

---
 src/gallium/auxiliary/pipe-loader/meson.build | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/pipe-loader/meson.build 
b/src/gallium/auxiliary/pipe-loader/meson.build
index 32e8188c68b..207e4b0fac4 100644
--- a/src/gallium/auxiliary/pipe-loader/meson.build
+++ b/src/gallium/auxiliary/pipe-loader/meson.build
@@ -27,13 +27,18 @@ files_pipe_loader = files(
 )
 
 libpipe_loader_defines = []
+libpipe_loader_links = []
 
 if dep_libdrm.found()
   files_pipe_loader += files('pipe_loader_drm.c')
+  libpipe_loader_links += libloader
 endif
 if with_gallium_drisw_kms
   libpipe_loader_defines += '-DHAVE_PIPE_LOADER_KMS'
 endif
+if not (with_gallium_st_nine or with_gallium_opencl)
+  libpipe_loader_defines += '-DROP_PIPE_LOADER_MISC=1'
+endif
 
 libpipe_loader_static = static_library(
   'pipe_loader_static',
@@ -46,7 +51,7 @@ libpipe_loader_static = static_library(
 c_vis_args, '-DHAVE_PIPE_LOADER_DRI', '-DGALLIUM_STATIC_TARGETS=1',
 libpipe_loader_defines,
   ],
-  link_with : [libloader, libxmlconfig],
+  link_with : [libpipe_loader_links, libxmlconfig],
   dependencies : [dep_libdrm],
   build_by_default : false,
 )
@@ -64,7 +69,7 @@ libpipe_loader_dynamic = static_library(
   join_paths(get_option('prefix'), get_option('libdir'), 'gallium-pipe')
 )
   ],
-  link_with : [libloader, libxmlconfig],
+  link_with : [libpipe_loader_links, libxmlconfig],
   dependencies : [dep_libdrm],
   build_by_default : false,
 )
-- 
2.17.1

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[Mesa-dev] [PATCH 28/48] meson: Add support for using win_flex and win_bison on windows

[Dylan Baker]

---
 meson.build | 27 +--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/meson.build b/meson.build
index 42e2540146c..f3e9676f8bf 100644
--- a/meson.build
+++ b/meson.build
@@ -1257,8 +1257,31 @@ endif
 
 # pthread stubs. Lets not and say we didn't
 
-prog_bison = find_program('bison', required : with_any_opengl)
-prog_flex = find_program('flex', required : with_any_opengl)
+if host_machine.system() == 'windows'
+  # Prefer the winflexbison versions, they're much easier to install and have
+  # better windows support.
+
+  prog_flex = find_program('win_flex', required : false)
+  if prog_flex.found()
+# windows compatibility (uses  instead of  and _isatty,
+# _fileno functions)
+prog_flex = [prog_flex, '--wincompat']
+  else
+prog_flex = [find_program('lex', 'flex', required : with_any_opengl)]
+  endif
+  # Force flex to use const keyword in prototypes, as relies on __cplusplus or
+  # __STDC__ macro to determine whether it's safe to use const keyword, but
+  # MSVC never defines __STDC__ unless we disable all MSVC extensions.
+  prog_flex += '-DYY_USE_CONST='
+
+  prog_bison = find_program('win_bison', required : false)
+  if not prog_bison.found()
+prog_bison = find_program('yacc', 'bison', required : with_any_opengl)
+  endif
+else
+  prog_bison = find_program('bison', required : with_any_opengl)
+  prog_flex = find_program('flex', required : with_any_opengl)
+endif
 
 dep_selinux = null_dep
 if get_option('selinux')
-- 
2.17.1

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[Mesa-dev] [PATCH 13/48] meson: add windows compiler checks and libraries

[Dylan Baker]

---
 meson.build | 126 ++--
 1 file changed, 82 insertions(+), 44 deletions(-)

diff --git a/meson.build b/meson.build
index fb07c2dd0de..4247d195bc1 100644
--- a/meson.build
+++ b/meson.build
@@ -688,6 +688,8 @@ if has_mako.returncode() != 0
 endif
 
 cc = meson.get_compiler('c')
+cpp = meson.get_compiler('cpp')
+
 if cc.get_id() == 'gcc' and cc.version().version_compare('< 4.4.6')
   error('When using GCC, version 4.4.6 or later is required.')
 endif
@@ -750,63 +752,97 @@ endif
 # TODO: this is very incomplete
 if ['linux', 'cygwin'].contains(host_machine.system())
   pre_args += '-D_GNU_SOURCE'
+elif host_machine.system() == 'windows'
+  pre_args += [
+'-DWIN32', '-D_WINDOWS', '-D_WIN32_WINNT=0x0601', '-D_WINVER=0x0601',
+'-DPIPE_SUBSYSTEM_WINDOWS_USER',
+'-D_USE_MATH_DEFINES',  # XXX: scons doesn't use this for mingw
+  ]
+  if cc.get_id() == 'msvc'
+pre_args += [
+  '-DVC_EXTRALEAN',
+  '-D_CRT_SECURE_NO_WARNINGS',
+  '-D_CRT_SECURE_NO_DEPRECATE',
+  '-D_SCL_SECURE_NO_WARNINGS',
+  '-D_SCL_SECURE_NO_DEPRECATE',
+  '-D_ALLOW_KEYWORD_MACROS',
+  '-D_HAS_EXCEPTIONS=0', # Tell C++ STL to not use exceptions
+]
+  else
+pre_args += ['-D__MSVCRT_VERSION__=0x0700']
+  endif
 endif
 
 # Check for generic C arguments
 c_args = []
-foreach a : ['-Wall', '-Werror=implicit-function-declaration',
- '-Werror=missing-prototypes', '-fno-math-errno',
- '-fno-trapping-math', '-Qunused-arguments']
-  if cc.has_argument(a)
-c_args += a
-  endif
-endforeach
 c_vis_args = []
-if cc.has_argument('-fvisibility=hidden')
-  c_vis_args += '-fvisibility=hidden'
-endif
-
-# Check for generic C++ arguments
-cpp = meson.get_compiler('cpp')
+c_msvc_compat_args = []
+no_override_init_args = []
+cpp_msvc_compat_args = []
+cpp_vis_args = []
 cpp_args = []
-foreach a : ['-Wall', '-fno-math-errno', '-fno-trapping-math',
- '-Qunused-arguments']
-  if cpp.has_argument(a)
-cpp_args += a
+if cc.get_id() == 'msvc'
+  foreach a : ['/wd4018', '/wd4056', '/wd4244', '/wd4246', '/wd4305',
+   '/wd4351', '/wd4756', '/wd4800', '/wd4996']
+if cc.has_argument(a)
+  c_args += a
+endif
+if cpp.has_argument(a)
+  cpp_args += a
+endif
+  endforeach
+  if cc.has_argument('-Wmicrosoft-enum-value')  # Clang
+c_args += '-Wno-microsoft-enum-value'
+cpp_args += '-Wno-microsoft-enum-value'
+  endif
+else
+  foreach a : ['-Wall', '-Werror=implicit-function-declaration',
+   '-Werror=missing-prototypes', '-fno-math-errno',
+   '-fno-trapping-math', '-Qunused-arguments']
+if cc.has_argument(a)
+  c_args += a
+endif
+  endforeach
+  if cc.has_argument('-fvisibility=hidden')
+c_vis_args += '-fvisibility=hidden'
   endif
-endforeach
 
-# For some reason, the test for -Wno-foo always succeeds with gcc, even if the
-# option is not supported. Hence, check for -Wfoo instead.
-if cpp.has_argument('-Wnon-virtual-dtor')
-  cpp_args += '-Wno-non-virtual-dtor'
-endif
+  # Check for generic C++ arguments
+  foreach a : ['-Wall', '-fno-math-errno', '-fno-trapping-math',
+   '-Qunused-arguments']
+if cpp.has_argument(a)
+  cpp_args += a
+endif
+  endforeach
 
-no_override_init_args = []
-foreach a : ['override-init', 'initializer-overrides']
-  if cc.has_argument('-W' + a)
-no_override_init_args += '-Wno-' + a
+  # For some reason, the test for -Wno-foo always succeeds with gcc, even if
+  # the option is not supported. Hence, check for -Wfoo instead.
+  if cpp.has_argument('-Wnon-virtual-dtor')
+cpp_args += '-Wno-non-virtual-dtor'
   endif
-endforeach
 
-cpp_vis_args = []
-if cpp.has_argument('-fvisibility=hidden')
-  cpp_vis_args += '-fvisibility=hidden'
-endif
+  foreach a : ['override-init', 'initializer-overrides']
+if cc.has_argument('-W' + a)
+  no_override_init_args += '-Wno-' + a
+endif
+  endforeach
 
-# Check for C and C++ arguments for MSVC2013 compatibility. These are only used
-# in parts of the mesa code base that need to compile with old versions of
-# MSVC, mainly common code
-c_msvc_compat_args = []
-cpp_msvc_compat_args = []
-foreach a : ['-Werror=pointer-arith', '-Werror=vla']
-  if cc.has_argument(a)
-c_msvc_compat_args += a
-  endif
-  if cpp.has_argument(a)
-cpp_msvc_compat_args += a
+  if cpp.has_argument('-fvisibility=hidden')
+cpp_vis_args += '-fvisibility=hidden'
   endif
-endforeach
+
+  # Check for C and C++ arguments for MSVC2013 compatibility. These are only
+  # used in parts of the mesa code base that need to compile with old versions
+  # of MSVC, mainly common code
+  foreach a : ['-Werror=pointer-arith', '-Werror=vla']
+if cc.has_argument(a)
+  c_msvc_compat_args += a
+endif
+if cpp.has_argument(a)
+  cpp_msvc_compat_args += a
+endif
+  endforeach
+endif
 
 if host_machine.cpu_family().startswith('x86')
   pre_args += '-DUSE_SSE41'
@@ -856,6 

[Mesa-dev] [PATCH 43/48] meson: don't build or run mesa-sha1 test on windows

[Dylan Baker]

It crashes hard (pop-up window and all).
---
 src/util/meson.build | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/util/meson.build b/src/util/meson.build
index c777984e28d..cf1eb64362d 100644
--- a/src/util/meson.build
+++ b/src/util/meson.build
@@ -146,16 +146,19 @@ if with_tests
 )
   )
 
-  test(
-'mesa-sha1',
-executable(
-  'mesa-sha1_test',
-  files('mesa-sha1_test.c'),
-  include_directories : inc_common,
-  link_with : libmesa_util,
-  c_args : [c_msvc_compat_args],
+  if host_machine.system() != 'windows'
+# this test doesn't work on windows
+test(
+  'mesa-sha1',
+  executable(
+'mesa-sha1_test',
+files('mesa-sha1_test.c'),
+include_directories : inc_common,
+link_with : libmesa_util,
+c_args : [c_msvc_compat_args],
+  )
 )
-  )
+  endif
 
   subdir('tests/hash_table')
   subdir('tests/string_buffer')
-- 
2.17.1

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[Mesa-dev] [PATCH 36/48] meson: Don't build glsl cache_test for windows

[Dylan Baker]

---
 src/compiler/glsl/tests/meson.build | 23 +--
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/src/compiler/glsl/tests/meson.build 
b/src/compiler/glsl/tests/meson.build
index fc7b863a278..725bc37438e 100644
--- a/src/compiler/glsl/tests/meson.build
+++ b/src/compiler/glsl/tests/meson.build
@@ -29,18 +29,21 @@ test(
   )
 )
 
-test(
-  'cache_test',
-  executable(
+if host_machine.system() != 'windows'
+  # This test does not compile on windows (use of ftw.h, unistd.h), and
+  # currently shader cache is not used, so just skip this.
+  test(
 'cache_test',
-'cache_test.c',
-c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
-include_directories : [inc_common, inc_glsl],
-link_with : [libglsl],
-dependencies : [dep_clock, dep_thread],
+executable(
+  'cache_test',
+  'cache_test.c',
+  c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
+  include_directories : [inc_common, inc_glsl],
+  link_with : [libglsl],
+  dependencies : [dep_clock, dep_thread],
+)
   )
-)
-
+endif
 
 test(
   'general_ir_test',
-- 
2.17.1

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[Mesa-dev] [PATCH 25/48] util/xmlconfig: include strndup.h for windows

[Dylan Baker]

---
 src/util/xmlconfig.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/util/xmlconfig.c b/src/util/xmlconfig.c
index 60a6331c86c..de3548b6b9d 100644
--- a/src/util/xmlconfig.c
+++ b/src/util/xmlconfig.c
@@ -36,6 +36,7 @@
 #include 
 #include 
 #include 
+#include "strndup.h"
 #include "xmlconfig.h"
 
 #undef GET_PROGRAM_NAME
-- 
2.17.1

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[Mesa-dev] [PATCH 11/48] meson: don't build glx or dri by default on windows

[Dylan Baker]

---
 meson.build | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/meson.build b/meson.build
index 9c8b9ca9ba5..1bdeeb95ec5 100644
--- a/meson.build
+++ b/meson.build
@@ -266,9 +266,13 @@ if with_glx == 'auto'
   elif with_platform_haiku
 with_glx = 'disabled'
   elif with_gallium
-# Even when building just gallium drivers the user probably wants dri
-with_glx = 'dri'
-with_dri = true
+if host_machine.system() == 'windows'
+  with_glx = 'disabled'
+else
+  # Even when building just gallium drivers the user probably wants dri
+  with_glx = 'dri'
+  with_dri = true
+endif
   elif with_platform_x11 and with_any_opengl and not with_any_vk
 # The automatic behavior should not be to turn on xlib based glx when
 # building only vulkan drivers
-- 
2.17.1

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[Mesa-dev] [PATCH 30/48] meson: for incluse of inttypes.h for glcpp with msvc

[Dylan Baker]

Because we provide a copy if MSVC doesn't, and we need it to make flex
do what we want.
---
 src/compiler/glsl/glcpp/meson.build | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/glcpp/meson.build 
b/src/compiler/glsl/glcpp/meson.build
index 09d44ddd687..80f51a3e48e 100644
--- a/src/compiler/glsl/glcpp/meson.build
+++ b/src/compiler/glsl/glcpp/meson.build
@@ -35,13 +35,23 @@ glcpp_lex = custom_target(
   command : [prog_flex, '-o', '@OUTPUT@', '@INPUT@'],
 )
 
+_extra_args = []
+if cpp.get_id() == 'msvc'
+  # Flex relies on __STDC_VERSION__>=199901L to decide when to include C99
+  # inttypes.h.  We always have inttypes.h available with MSVC (either the one
+  # bundled with MSVC 2013, or the one we bundle ourselves), but we can't just
+  # define __STDC_VERSION__ without breaking stuff, as MSVC doesn't fully
+  # support C99.  There's also no way to premptively include stdint.
+  _extra_args += '-FIinttypes.h'
+endif
+
 libglcpp = static_library(
   'glcpp',
   [glcpp_lex, glcpp_parse, files('glcpp.h', 'pp.c')],
   link_with : libmesa_util,
   include_directories : [inc_common],
-  c_args : [c_vis_args, no_override_init_args, c_msvc_compat_args],
-  cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
+  c_args : [c_vis_args, no_override_init_args, c_msvc_compat_args, 
_extra_args],
+  cpp_args : [cpp_vis_args, cpp_msvc_compat_args, _extra_args],
   build_by_default : false,
 )
 
-- 
2.17.1

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