[Mesa-dev] [Bug 106972] vulkan.h:75:35: fatal error: X11/extensions/Xrandr.h: No such file or directory

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106972

Bug ID: 106972
   Summary: vulkan.h:75:35: fatal error: X11/extensions/Xrandr.h:
No such file or directory
   Product: Mesa
   Version: git
  Hardware: All
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: pedretti.fa...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org
CC: kei...@keithp.com

I get the following error since last hours commits.

Full build log and configure options:
https://launchpadlibrarian.net/375236019/buildlog_ubuntu-xenial-amd64.mesa_18.2~git1806200730.dbac8e~oibaf~x_BUILDING.txt.gz

In file included from ../../../src/vulkan/util/vk_alloc.h:29:0,
 from ../../../src/vulkan/wsi/wsi_common.h:29,
 from ../../../src/vulkan/wsi/wsi_common_private.h:26,
 from ../../../src/vulkan/wsi/wsi_common.c:24:
../../../include/vulkan/vulkan.h:75:35: fatal error: X11/extensions/Xrandr.h:
No such file or directory
compilation terminated.
Makefile:742: recipe for target 'wsi/wsi_common.lo' failed
make[4]: *** [wsi/wsi_common.lo] Error 1
make[4]: *** Waiting for unfinished jobs

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Re: [Mesa-dev] [PATCH] radv: Fix flush_bits being used uninitialized.

2018-06-20 Thread Samuel Pitoiset 

Ooops, right.

Reviewed-by: Samuel Pitoiset 

On 06/20/2018 12:29 AM, Bas Nieuwenhuizen wrote:

A case of making things worse while trying to fix something minor ...

Fixes: ef79457004e "radv: Merge the flush bits of CMASK & DCC clear."
---
  src/amd/vulkan/radv_meta_clear.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 14af2560821..e9af0532859 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -994,7 +994,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
const struct radv_image_view *iview = 
fb->attachments[pass_att].attachment;
VkClearColorValue clear_value = clear_att->clearValue.color;
-   uint32_t clear_color[2], flush_bits;
+   uint32_t clear_color[2], flush_bits = 0;
uint32_t cmask_clear_value;
bool ret;
  


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[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106151

--- Comment #19 from Samuel Pitoiset  ---
Thanks, what preset do you use?

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Re: [Mesa-dev] [PATCH 01/24] configure.ac: Add CFLAG -Wno-missing-field-initializers (v5)

2018-06-20 Thread Gert Wollny 
Hi Dylan & Eric, 

are you fine with how the flag is added now in meson? If you don't have
any complaints I'm going to push the changes later today. 

many thanks, 
Gert 

Am Dienstag, den 19.06.2018, 10:07 +0200 schrieb Gert Wollny:
> This warning is misleading: When a struct is partially initialized
> without
> assigning to the structure members by name, then the remaining fields
> will be zeroed out, and this warning will be issued (if enabled). If,
> on the
> other hand, the partial initialization is done by assigning to named
> members,
> the remaining structure elements may hold random data, but the
> warning is not
> issued. Since in Mesa the first approach to initialize structure
> elements is
> used very often, and it is usually assumed that the remaining
> elements are
> zeroed out, heeding this warning would be counter-productive.
> 
> v2: - add -Wno-missing-field-initializers to meson-build
> - fix empty line error
> (both Eric Engestrom)
> 
> v3: * check for -Wmissing-field-initializers warning and then disable
> it
>   because gcc and clang always accept -Wno-* (Dylan Baker)
> * Also disable this warning for C++
> 
> v4: * meson.build add -Wno-missing-field-initializers to
>   c_args instead of no_override_init_args (Eric Engstrom)
> 
> v5: * configure.ac: Correct copy/paste error with CFLAGS/CXXFLAGS
> 
> Reviewed-by: Marek Olšák  (v1)
> Reviewed-by: Emil Velikov  (v2)
> Signed-off-by: Gert Wollny 
> ---
>  configure.ac |  4 
>  meson.build  | 13 ++---
>  2 files changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index 7a0e475420..1529e47c95 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -302,7 +302,10 @@ AX_CHECK_COMPILE_FLAG([-
> Wall], [CFLAGS="$CFLAGS
>  AX_CHECK_COMPILE_FLAG([-Werror=implicit-function-declaration],
> [CFLAGS="$CFLAGS -Werror=implicit-function-declaration"])
>  AX_CHECK_COMPILE_FLAG([-Werror=missing-
> prototypes],[CFLAGS="$CFLAGS -Werror=missing-
> prototypes"])
>  AX_CHECK_COMPILE_FLAG([-Wmissing-
> prototypes],  [CFLAGS="$CFLAGS -Wmissing-
> prototypes"])
> +dnl Dylan Baker: gcc and clang always accepr -Wno-*, hence check for
> the original warning, then set the no-* flag
> +AX_CHECK_COMPILE_FLAG([-Wmissing-field-
> initializers],  [CFLAGS="$CFLAGS -Wno-missing-field-
> initializers"])
>  AX_CHECK_COMPILE_FLAG([-fno-math-
> errno],   [CFLAGS="$CFLAGS -fno-math-errno"])
> +
>  AX_CHECK_COMPILE_FLAG([-fno-trapping-
> math],[CFLAGS="$CFLAGS -fno-trapping-math"])
>  AX_CHECK_COMPILE_FLAG([-
> fvisibility=hidden],   [VISIBILITY_CFLAGS="-
> fvisibility=hidden"])
>  
> @@ -314,6 +317,7 @@ AX_CHECK_COMPILE_FLAG([-
> Wall], [CXXFLAGS="$CXXFL
>  AX_CHECK_COMPILE_FLAG([-fno-math-
> errno],   [CXXFLAGS="$CXXFLAGS -fno-math-errno"])
>  AX_CHECK_COMPILE_FLAG([-fno-trapping-
> math],[CXXFLAGS="$CXXFLAGS -fno-trapping-math"])
>  AX_CHECK_COMPILE_FLAG([-
> fvisibility=hidden],   [VISIBILITY_CXXFLAGS="-
> fvisibility=hidden"])
> +AX_CHECK_COMPILE_FLAG([-Wmissing-field-
> initializers],  [CXXFLAGS="$CXXFLAGS -Wno-missing-field-
> initializers"])
>  AC_LANG_POP([C++])
>  
>  # Flags to help ensure that certain portions of the code -- and only
> those
> diff --git a/meson.build b/meson.build
> index 65ae32172d..c02b3d5c41 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -762,6 +762,10 @@ foreach a : ['-Wall', '-Werror=implicit-
> function-declaration',
>  c_args += a
>endif
>  endforeach
> +if cc.has_argument('-Wmissing-field-initializers')
> +  c_args += '-Wno-missing-field-initializers'
> +endif
> +
>  c_vis_args = []
>  if cc.has_argument('-fvisibility=hidden')
>c_vis_args += '-fvisibility=hidden'
> @@ -778,9 +782,12 @@ endforeach
>  
>  # For some reason, the test for -Wno-foo always succeeds with gcc,
> even if the
>  # option is not supported. Hence, check for -Wfoo instead.
> -if cpp.has_argument('-Wnon-virtual-dtor')
> -  cpp_args += '-Wno-non-virtual-dtor'
> -endif
> +
> +foreach a : ['non-virtual-dtor', 'missing-field-initializers']
> +  if cpp.has_argument('-W' + a)
> +cpp_args += '-Wno-' + a
> +  endif
> +endforeach
>  
>  no_override_init_args = []
>  foreach a : ['override-init', 'initializer-overrides']
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Re: [Mesa-dev] [PATCH 01/24] configure.ac: Add CFLAG -Wno-missing-field-initializers (v5)

2018-06-20 Thread Eric Engestrom 
On Wednesday, 2018-06-20 10:24:51 +0200, Gert Wollny wrote:
> Hi Dylan & Eric, 
> 
> are you fine with how the flag is added now in meson? If you don't have
> any complaints I'm going to push the changes later today. 

Looks good to me, thanks!
Reviewed-by: Eric Engestrom 

> 
> many thanks, 
> Gert 
> 
> Am Dienstag, den 19.06.2018, 10:07 +0200 schrieb Gert Wollny:
> > This warning is misleading: When a struct is partially initialized
> > without
> > assigning to the structure members by name, then the remaining fields
> > will be zeroed out, and this warning will be issued (if enabled). If,
> > on the
> > other hand, the partial initialization is done by assigning to named
> > members,
> > the remaining structure elements may hold random data, but the
> > warning is not
> > issued. Since in Mesa the first approach to initialize structure
> > elements is
> > used very often, and it is usually assumed that the remaining
> > elements are
> > zeroed out, heeding this warning would be counter-productive.
> > 
> > v2: - add -Wno-missing-field-initializers to meson-build
> > - fix empty line error
> > (both Eric Engestrom)
> > 
> > v3: * check for -Wmissing-field-initializers warning and then disable
> > it
> >   because gcc and clang always accept -Wno-* (Dylan Baker)
> > * Also disable this warning for C++
> > 
> > v4: * meson.build add -Wno-missing-field-initializers to
> >   c_args instead of no_override_init_args (Eric Engstrom)
> > 
> > v5: * configure.ac: Correct copy/paste error with CFLAGS/CXXFLAGS
> > 
> > Reviewed-by: Marek Olšák  (v1)
> > Reviewed-by: Emil Velikov  (v2)
> > Signed-off-by: Gert Wollny 
> > ---
> >  configure.ac |  4 
> >  meson.build  | 13 ++---
> >  2 files changed, 14 insertions(+), 3 deletions(-)
> > 
> > diff --git a/configure.ac b/configure.ac
> > index 7a0e475420..1529e47c95 100644
> > --- a/configure.ac
> > +++ b/configure.ac
> > @@ -302,7 +302,10 @@ AX_CHECK_COMPILE_FLAG([-
> > Wall], [CFLAGS="$CFLAGS
> >  AX_CHECK_COMPILE_FLAG([-Werror=implicit-function-declaration],
> > [CFLAGS="$CFLAGS -Werror=implicit-function-declaration"])
> >  AX_CHECK_COMPILE_FLAG([-Werror=missing-
> > prototypes],[CFLAGS="$CFLAGS -Werror=missing-
> > prototypes"])
> >  AX_CHECK_COMPILE_FLAG([-Wmissing-
> > prototypes],  [CFLAGS="$CFLAGS -Wmissing-
> > prototypes"])
> > +dnl Dylan Baker: gcc and clang always accepr -Wno-*, hence check for
> > the original warning, then set the no-* flag
> > +AX_CHECK_COMPILE_FLAG([-Wmissing-field-
> > initializers],  [CFLAGS="$CFLAGS -Wno-missing-field-
> > initializers"])
> >  AX_CHECK_COMPILE_FLAG([-fno-math-
> > errno],   [CFLAGS="$CFLAGS -fno-math-errno"])
> > +
> >  AX_CHECK_COMPILE_FLAG([-fno-trapping-
> > math],[CFLAGS="$CFLAGS -fno-trapping-math"])
> >  AX_CHECK_COMPILE_FLAG([-
> > fvisibility=hidden],   [VISIBILITY_CFLAGS="-
> > fvisibility=hidden"])
> >  
> > @@ -314,6 +317,7 @@ AX_CHECK_COMPILE_FLAG([-
> > Wall], [CXXFLAGS="$CXXFL
> >  AX_CHECK_COMPILE_FLAG([-fno-math-
> > errno],   [CXXFLAGS="$CXXFLAGS -fno-math-errno"])
> >  AX_CHECK_COMPILE_FLAG([-fno-trapping-
> > math],[CXXFLAGS="$CXXFLAGS -fno-trapping-math"])
> >  AX_CHECK_COMPILE_FLAG([-
> > fvisibility=hidden],   [VISIBILITY_CXXFLAGS="-
> > fvisibility=hidden"])
> > +AX_CHECK_COMPILE_FLAG([-Wmissing-field-
> > initializers],  [CXXFLAGS="$CXXFLAGS -Wno-missing-field-
> > initializers"])
> >  AC_LANG_POP([C++])
> >  
> >  # Flags to help ensure that certain portions of the code -- and only
> > those
> > diff --git a/meson.build b/meson.build
> > index 65ae32172d..c02b3d5c41 100644
> > --- a/meson.build
> > +++ b/meson.build
> > @@ -762,6 +762,10 @@ foreach a : ['-Wall', '-Werror=implicit-
> > function-declaration',
> >  c_args += a
> >endif
> >  endforeach
> > +if cc.has_argument('-Wmissing-field-initializers')
> > +  c_args += '-Wno-missing-field-initializers'
> > +endif
> > +
> >  c_vis_args = []
> >  if cc.has_argument('-fvisibility=hidden')
> >c_vis_args += '-fvisibility=hidden'
> > @@ -778,9 +782,12 @@ endforeach
> >  
> >  # For some reason, the test for -Wno-foo always succeeds with gcc,
> > even if the
> >  # option is not supported. Hence, check for -Wfoo instead.
> > -if cpp.has_argument('-Wnon-virtual-dtor')
> > -  cpp_args += '-Wno-non-virtual-dtor'
> > -endif
> > +
> > +foreach a : ['non-virtual-dtor', 'missing-field-initializers']
> > +  if cpp.has_argument('-W' + a)
> > +cpp_args += '-Wno-' + a
> > +  endif
> > +endforeach
> >  
> >  no_override_init_args = []
> >  foreach a : ['override-init', 'initializer-overrides']
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Re: [Mesa-dev] [PATCH 3/3] radv: always initialize the clear depth/stencil values to 0

2018-06-20 Thread Bas Nieuwenhuizen 
Reviewed-by: Bas Nieuwenhuizen 

for the series.

On Tue, Jun 19, 2018 at 4:57 PM, Samuel Pitoiset
 wrote:
> Similar to the clear color values.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 35 ++--
>  src/amd/vulkan/radv_meta_clear.c |  6 +++---
>  src/amd/vulkan/radv_private.h|  8 
>  3 files changed, 27 insertions(+), 22 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index d3a6f623f22..240ca8d6f16 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1217,7 +1217,7 @@ radv_update_bound_fast_clear_ds(struct radv_cmd_buffer 
> *cmd_buffer,
>  /**
>   * Set the clear depth/stencil values to the image's metadata.
>   */
> -void
> +static void
>  radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
>struct radv_image *image,
>VkClearDepthStencilValue ds_clear_value,
> @@ -1229,8 +1229,6 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer 
> *cmd_buffer,
>
> va += image->offset + image->clear_value_offset;
>
> -   assert(radv_image_has_htile(image));
> -
> if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
> ++reg_count;
> } else {
> @@ -1250,6 +1248,20 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer 
> *cmd_buffer,
> radeon_emit(cs, ds_clear_value.stencil);
> if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
> radeon_emit(cs, fui(ds_clear_value.depth));
> +}
> +
> +/**
> + * Update the clear depth/stencil values for this image.
> + */
> +void
> +radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
> + struct radv_image *image,
> + VkClearDepthStencilValue ds_clear_value,
> + VkImageAspectFlags aspects)
> +{
> +   assert(radv_image_has_htile(image));
> +
> +   radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, 
> aspects);
>
> radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
> aspects);
> @@ -3944,9 +3956,11 @@ static void radv_initialize_htile(struct 
> radv_cmd_buffer *cmd_buffer,
> assert(range->levelCount == 1 || range->levelCount == 
> VK_REMAINING_ARRAY_LAYERS);
> unsigned layer_count = radv_get_layerCount(image, range);
> uint64_t size = image->surface.htile_slice_size * layer_count;
> +   VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
> uint64_t offset = image->offset + image->htile_offset +
>   image->surface.htile_slice_size * 
> range->baseArrayLayer;
> struct radv_cmd_state *state = &cmd_buffer->state;
> +   VkClearDepthStencilValue value = {};
>
> state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
>  RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
> @@ -3956,19 +3970,10 @@ static void radv_initialize_htile(struct 
> radv_cmd_buffer *cmd_buffer,
>
> state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
>
> -   /* Initialize the depth clear registers and update the 
> ZRANGE_PRECISION
> -* value for the TC-compat bug (because ZRANGE_PRECISION is 1 by
> -* default). This is only needed whean clearing Z to 0.0f.
> -*/
> -   if (radv_image_is_tc_compat_htile(image) && clear_word == 0) {
> -   VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
> -   VkClearDepthStencilValue value = {};
> -
> -   if (vk_format_is_stencil(image->vk_format))
> -   aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
> +   if (vk_format_is_stencil(image->vk_format))
> +   aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
>
> -   radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
> -   }
> +   radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
>  }
>
>  static void radv_handle_depth_image_transition(struct radv_cmd_buffer 
> *cmd_buffer,
> diff --git a/src/amd/vulkan/radv_meta_clear.c 
> b/src/amd/vulkan/radv_meta_clear.c
> index 44cd0b5c219..075f40e7815 100644
> --- a/src/amd/vulkan/radv_meta_clear.c
> +++ b/src/amd/vulkan/radv_meta_clear.c
> @@ -645,8 +645,8 @@ emit_depthstencil_clear(struct radv_cmd_buffer 
> *cmd_buffer,
> if (depth_view_can_fast_clear(cmd_buffer, iview, aspects,
>   
> subpass->depth_stencil_attachment.layout,
>   clear_rect, clear_value))
> -   radv_set_ds_clear_metadata(cmd_buffer, iview->image,
> -  clear_value, aspects);
> +   radv_update_ds_clear_metadata(cmd_buffer, iview->image,
> + clear_value, aspects);
>
> radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1,

Re: [Mesa-dev] [PATCH 2/2] radv: do not use an user SGPR for the sample position offset

2018-06-20 Thread Bas Nieuwenhuizen 
Reviewed-by: Bas Nieuwenhuizen 

for the series.

On Tue, Jun 19, 2018 at 2:25 PM, Samuel Pitoiset
 wrote:
> We know the number of samples at compile time.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_nir_to_llvm.c | 40 +++
>  src/amd/vulkan/radv_pipeline.c| 29 --
>  src/amd/vulkan/radv_shader.h  |  1 -
>  3 files changed, 30 insertions(+), 40 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index d45af9d0fc..cd8d86603b 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -81,7 +81,6 @@ struct radv_shader_context {
> LLVMValueRef hs_ring_tess_offchip;
> LLVMValueRef hs_ring_tess_factor;
>
> -   LLVMValueRef sample_pos_offset;
> LLVMValueRef persp_sample, persp_center, persp_centroid;
> LLVMValueRef linear_sample, linear_center, linear_centroid;
>
> @@ -1095,10 +1094,6 @@ static void create_function(struct radv_shader_context 
> *ctx,
>previous_stage, &user_sgpr_info,
>&args, &desc_sets);
>
> -   if (ctx->shader_info->info.ps.needs_sample_positions)
> -   add_arg(&args, ARG_SGPR, ctx->ac.i32,
> -   &ctx->sample_pos_offset);
> -
> add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
> add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
> add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
> @@ -1194,10 +1189,6 @@ static void create_function(struct radv_shader_context 
> *ctx,
> set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 
> 1);
> break;
> case MESA_SHADER_FRAGMENT:
> -   if (ctx->shader_info->info.ps.needs_sample_positions) {
> -   set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
> -  &user_sgpr_idx, 1);
> -   }
> break;
> default:
> unreachable("Shader stage not implemented");
> @@ -1627,6 +1618,30 @@ static LLVMValueRef lookup_interp_param(struct 
> ac_shader_abi *abi,
> return NULL;
>  }
>
> +static uint32_t
> +radv_get_sample_pos_offset(uint32_t num_samples)
> +{
> +   uint32_t sample_pos_offset = 0;
> +
> +   switch (num_samples) {
> +   case 2:
> +   sample_pos_offset = 1;
> +   break;
> +   case 4:
> +   sample_pos_offset = 3;
> +   break;
> +   case 8:
> +   sample_pos_offset = 7;
> +   break;
> +   case 16:
> +   sample_pos_offset = 15;
> +   break;
> +   default:
> +   break;
> +   }
> +   return sample_pos_offset;
> +}
> +
>  static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
>  LLVMValueRef sample_id)
>  {
> @@ -1638,7 +1653,12 @@ static LLVMValueRef load_sample_position(struct 
> ac_shader_abi *abi,
> ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
>ac_array_in_const_addr_space(ctx->ac.v2f32), 
> "");
>
> -   sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, 
> ctx->sample_pos_offset, "");
> +   uint32_t sample_pos_offset =
> +   radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
> +
> +   sample_id =
> +   LLVMBuildAdd(ctx->ac.builder, sample_id,
> +LLVMConstInt(ctx->ac.i32, sample_pos_offset, 
> false), "");
> result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
>
> return result;
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index 46cb3dadba..4f794fc9ef 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -2710,35 +2710,6 @@ radv_pipeline_generate_multisample_state(struct 
> radeon_winsys_cs *cs,
>
> radeon_set_context_reg(cs, R_028804_DB_EQAA, ms->db_eqaa);
> radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, 
> ms->pa_sc_mode_cntl_1);
> -
> -   if 
> (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
>  {
> -   uint32_t offset;
> -   struct radv_userdata_info *loc = 
> radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, 
> AC_UD_PS_SAMPLE_POS_OFFSET);
> -   uint32_t base_reg = 
> pipeline->user_data_0[MESA_SHADER_FRAGMENT];
> -   if (loc->sgpr_idx == -1)
> -   return;
> -   assert(loc->num_sgprs == 1);
> -   assert(!loc->indirect);
> -   switch (pipeline->graphics.ms.num_samples) {
> -   default:
> -   offset = 0;
> -   break;
> -   case 2:
> -

Re: [Mesa-dev] [PATCH v2 02/16] intel: aubinator: remove standard input processing option

2018-06-20 Thread Lionel Landwerlin 

On 19/06/18 23:56, Rafael Antognolli wrote:

On Tue, Jun 19, 2018 at 11:40:30AM -0700, Rafael Antognolli wrote:

On Tue, Jun 19, 2018 at 02:45:17PM +0100, Lionel Landwerlin wrote:

Now that we rely on mmap of the data to parse, we can't process the
standard input anymore.

Didn't we rely on mmap of the data since forever?

Oh, I think it's because of patch 04, right? If so, I think we need to
update the message to reflect that this is going to be changed in a
newer commit. And maybe explain it a little more, something like:

"On a follow up commit in this series, we stop copying the data from the
mmap'ed file into our big gtt mmap, and start referencing data in it
directly. So reallocating the read buffer and adding more data from
stdin wouldn't work. For that reason, let's stop supporting stdin
process."

Or something like that, assuming I understood it correclty.

Anyway, this patch is

Reviewed-by: Rafael Antognolli 


Indeed, sorry for the confusion :(





This isn't much of a big deal because we have in-process batch decoder
(run with INTEL_DEBUG=batch) that supports essentially doing the same
thing.

Signed-off-by: Lionel Landwerlin 
---
  src/intel/tools/aubinator.c | 102 +---
  1 file changed, 12 insertions(+), 90 deletions(-)

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 949ba96e556..3f9047e69a8 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -350,17 +350,6 @@ aub_file_open(const char *filename)
 return file;
  }
  
-static struct aub_file *

-aub_file_stdin(void)
-{
-   struct aub_file *file;
-
-   file = calloc(1, sizeof *file);
-   file->stream = stdin;
-
-   return file;
-}
-
  #define TYPE(dw)   (((dw) >> 29) & 7)
  #define OPCODE(dw) (((dw) >> 23) & 0x3f)
  #define SUBOPCODE(dw)  (((dw) >> 16) & 0x7f)
@@ -398,8 +387,7 @@ aub_file_decode_batch(struct aub_file *file)
 uint32_t *p, h, *new_cursor;
 int header_length, bias;
  
-   if (file->end - file->cursor < 1)

-  return AUB_ITEM_DECODE_NEED_MORE_DATA;
+   assert(file->cursor < file->end);
  
 p = file->cursor;

 h = *p;
@@ -421,13 +409,11 @@ aub_file_decode_batch(struct aub_file *file)
  
 new_cursor = p + header_length + bias;

 if ((h & 0x) == MAKE_HEADER(TYPE_AUB, OPCODE_AUB, 
SUBOPCODE_BLOCK)) {
-  if (file->end - file->cursor < 4)
- return AUB_ITEM_DECODE_NEED_MORE_DATA;
+  assert(file->end - file->cursor >= 4);
new_cursor += p[4] / 4;
 }
  
-   if (new_cursor > file->end)

-  return AUB_ITEM_DECODE_NEED_MORE_DATA;
+   assert(new_cursor <= file->end);
  
 switch (h & 0x) {

 case MAKE_HEADER(TYPE_AUB, OPCODE_AUB, SUBOPCODE_HEADER):
@@ -468,48 +454,6 @@ aub_file_more_stuff(struct aub_file *file)
 return file->cursor < file->end || (file->stream && !feof(file->stream));
  }
  
-#define AUB_READ_BUFFER_SIZE (4096)

-#define MAX(a, b) ((a) < (b) ? (b) : (a))
-
-static void
-aub_file_data_grow(struct aub_file *file)
-{
-   size_t old_size = (file->mem_end - file->map) * 4;
-   size_t new_size = MAX(old_size * 2, AUB_READ_BUFFER_SIZE);
-   uint32_t *new_start = realloc(file->map, new_size);
-
-   file->cursor = new_start + (file->cursor - file->map);
-   file->end = new_start + (file->end - file->map);
-   file->map = new_start;
-   file->mem_end = file->map + (new_size / 4);
-}
-
-static bool
-aub_file_data_load(struct aub_file *file)
-{
-   size_t r;
-
-   if (file->stream == NULL)
-  return false;
-
-   /* First remove any consumed data */
-   if (file->cursor > file->map) {
-  memmove(file->map, file->cursor,
-  (file->end - file->cursor) * 4);
-  file->end -= file->cursor - file->map;
-  file->cursor = file->map;
-   }
-
-   /* Then load some new data in */
-   if ((file->mem_end - file->end) < (AUB_READ_BUFFER_SIZE / 4))
-  aub_file_data_grow(file);
-
-   r = fread(file->end, 1, (file->mem_end - file->end) * 4, file->stream);
-   file->end += r / 4;
-
-   return r != 0;
-}
-
  static void
  setup_pager(void)
  {
@@ -541,9 +485,8 @@ static void
  print_help(const char *progname, FILE *file)
  {
 fprintf(file,
-   "Usage: %s [OPTION]... [FILE]\n"
-   "Decode aub file contents from either FILE or the standard 
input.\n\n"
-   "A valid --gen option must be provided.\n\n"
+   "Usage: %s [OPTION]... FILE\n"
+   "Decode aub file contents from FILE.\n\n"
 "  --help display this help and exit\n"
 "  --gen=platform decode for given platform (3 letter platform 
name)\n"
 "  --headers  decode only command headers\n"
@@ -612,14 +555,14 @@ int main(int argc, char *argv[])
}
 }
  
-   if (help || argc == 1) {

+   if (optind < argc)
+  input_file = argv[optind];
+
+   if (help || !input_file) {
print_help(argv[0], stderr);
exit(0);
 }
  
-   if (optind < argc)

-  input_fil

Re: [Mesa-dev] [PATCH v2 07/16] intel/tools/aubinator: aubinate ppgtt aubs

2018-06-20 Thread Lionel Landwerlin 

On 20/06/18 01:00, Rafael Antognolli wrote:

On Tue, Jun 19, 2018 at 02:45:22PM +0100, Lionel Landwerlin wrote:

From: Scott D Phillips 

v2: by Lionel
 Fix memfd_create compilation issue
 Fix pml4 address stored on 32 instead of 64bits
 Return no buffer if first ppgtt page is not mapped

Signed-off-by: Lionel Landwerlin 
---
  src/intel/tools/aubinator.c | 76 -
  1 file changed, 75 insertions(+), 1 deletion(-)

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 962546d360c..3368ac521bd 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -336,6 +336,68 @@ get_ggtt_batch_bo(void *user_data, uint64_t address)
  
 return bo;

  }
+
+static struct phys_mem *
+ppgtt_walk(uint64_t pml4, uint64_t address)
+{
+   uint64_t shift = 39;
+   uint64_t addr = pml4;
+   for (int level = 4; level > 0; level--) {
+  struct phys_mem *table = search_phys_mem(addr);
+  if (!table)
+ return NULL;
+  int index = (address >> shift) & 0x1ff;
+  uint64_t entry = ((uint64_t *)table->data)[index];
+  if (!(entry & 1))
+ return NULL;
+  addr = entry & ~0xfff;
+  shift -= 9;
+   }
+   return search_phys_mem(addr);
+}
+
+static bool
+ppgtt_mapped(uint64_t pml4, uint64_t address)
+{
+   return ppgtt_walk(pml4, address) != NULL;
+}
+
+static struct gen_batch_decode_bo
+get_ppgtt_batch_bo(void *user_data, uint64_t address)
+{
+   struct gen_batch_decode_bo bo = {0};
+   uint64_t pml4 = *(uint64_t *)user_data;
+
+   address &= ~0xfff;
+
+   if (!ppgtt_mapped(pml4, address))
+  return bo;
+
+   /* Map everything until the first gap since we don't know how much the
+* decoder actually needs.
+*/
+   uint64_t end = address;
+   while (ppgtt_mapped(pml4, end))
+  end += 4096;
+
+   bo.addr = address;
+   bo.size = end - address;
+   bo.map = mmap(NULL, bo.size, PROT_READ, MAP_SHARED | MAP_ANONYMOUS, -1, 0);
+   assert(bo.map != MAP_FAILED);
+
+   for (uint64_t page = address; page < end; page += 4096) {
+  struct phys_mem *phys_mem = ppgtt_walk(pml4, page);
+
+  void *res = mmap((uint8_t *)bo.map + (page - bo.addr), 4096, PROT_READ,
+   MAP_SHARED | MAP_FIXED, mem_fd, phys_mem->fd_offset);
+  assert(res != MAP_FAILED);
+   }
+
+   add_gtt_bo_map(bo, true);
+
+   return bo;
+}
+
  #define GEN_ENGINE_RENDER 1
  #define GEN_ENGINE_BLITTER 2
  
@@ -377,6 +439,7 @@ handle_trace_block(uint32_t *p)

}
  
(void)engine; /* TODO */

+  batch_ctx.get_bo = get_ggtt_batch_bo;
gen_print_batch(&batch_ctx, bo.map, bo.size, 0);
  
clear_bo_maps();

@@ -402,7 +465,7 @@ aubinator_init(uint16_t aub_pci_id, const char *app_name)
 batch_flags |= GEN_BATCH_DECODE_FLOATS;
  
 gen_batch_decode_ctx_init(&batch_ctx, &devinfo, outfile, batch_flags,

- xml_path, get_ggtt_batch_bo, NULL, NULL);
+ xml_path, NULL, NULL, NULL);
 batch_ctx.max_vbo_decoded_lines = max_vbo_lines;
  
 char *color = GREEN_HEADER, *reset_color = NORMAL;

@@ -542,12 +605,20 @@ handle_memtrace_reg_write(uint32_t *p)
 uint32_t ring_buffer_head = context[5];
 uint32_t ring_buffer_tail = context[7];
 uint32_t ring_buffer_start = context[9];
+   uint64_t pml4 = (uint64_t)context[49] << 32 | context[51];
  
 struct gen_batch_decode_bo ring_bo = get_ggtt_batch_bo(NULL,

ring_buffer_start);
 assert(ring_bo.size > 0);
 void *commands = (uint8_t *)ring_bo.map + (ring_bo.addr - 
ring_buffer_start);
  
+   if (context_descriptor & 0x100 /* ppgtt */) {

+  batch_ctx.get_bo = get_ppgtt_batch_bo;
+  batch_ctx.user_data = &pml4;
+   } else {
+  batch_ctx.get_bo = get_ggtt_batch_bo;
+   }
+
 (void)engine; /* TODO */
 gen_print_batch(&batch_ctx, commands, ring_buffer_tail - ring_buffer_head,
 0);
@@ -849,6 +920,9 @@ int main(int argc, char *argv[])
  
 list_inithead(&maps);
  
+   mem_fd = memfd_create("phys memory", 0);

+
+

It seems like this memfd_create() got duplicated here (it was added in
the previous patch).


Oops... Dropped locally.




 file = aub_file_open(input_file);
  
 while (aub_file_more_stuff(file) &&

--
2.17.1


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Re: [Mesa-dev] [PATCH v3 3/3] egl/android: Add DRM node probing and filtering

2018-06-20 Thread Robert Foss 

Hey Tomasz,

Thanks for the quick feedback.

On 2018-06-14 08:30, Tomasz Figa wrote:

Hi Rob,

Thanks for sending v3. Please see few more comments inline.

On Sun, Jun 10, 2018 at 2:28 AM Robert Foss  wrote:


This patch both adds support for probing & filtering DRM nodes
and switches away from using the GRALLOC_MODULE_PERFORM_GET_DRM_FD
gralloc call.

Currently the filtering is based just on the driver name,
and the desired name is supplied using the "drm.gpu.vendor_name"
Android property.

Signed-off-by: Robert Foss 
---

Changes since v2:
  - Switch from drmGetDevices2 to manual renderD node iteration
  - Add probe_res enum to communicate probing results better
  - Avoid using _eglError() in internal static functions
  - Avoid actually loading the driver while probing, just verify
that it exists.
  - Replace strlen call with the assumed length PROPERTY_VALUE_MAX


[snip]


+static probe_ret_t
+droid_probe_device(_EGLDisplay *disp, int fd, char *vendor)
+{
+   int ret;
+
+   drmVersionPtr ver = drmGetVersion(fd);
+   if (!ver)
+  return probe_error;
+
+   if (vendor != NULL && ver->name != NULL &&
+   strncmp(vendor, ver->name, PROPERTY_VALUE_MAX) != 0) {


Shouldn't we fail the match if vendor != NULL, but ver->name == NULL? i.e.

if (vendor && (!ver->name || strcmp(...)) { ...



Yeah, overall that if-case is too much. I'll split out the NULL check separate
check that return an error.


+  ret = probe_filtered_out;
+  goto cleanup;
+   }
+
+
+   if (!droid_probe_driver(fd)) {
+  ret = probe_no_driver;
+  goto cleanup;
+   }
+
+   ret = probe_success;
+
+cleanup:
+   drmFreeVersion(ver);
+   return ret;
+}
+
+static int
+droid_open_device(_EGLDisplay *disp)
+{
+   const int MAX_DRM_DEVICES = 32;
+   int prop_set, num_devices;
+   int fd = -1, fallback_fd = -1;
+
+   char *vendor_name = NULL;
+   char vendor_buf[PROPERTY_VALUE_MAX];
+   if (property_get("drm.gpu.vendor_name", vendor_buf, NULL) > 0);
+  vendor_name = vendor_buf;
+
+   const char *drm_dir_name = "/dev/dri";
+   DIR *sysdir = opendir(drm_dir_name);
+   if (!sysdir)
+   return -errno;
+
+   struct dirent *dent;
+   while ((dent = readdir(sysdir))) {
+  char dev_path[128];
+  char *render_dev_prefix = "renderD";
+  size_t prefix_len = strlen(render_dev_prefix);


If a const array like below is used instead

const char render_dev_prefix[] = "renderD";

you can just use sizeof(render_dev_prefix), without the need for strlen().



Ack.


+
+  if (strncmp(render_dev_prefix, dent->d_name, prefix_len) != 0)
+ continue;
+
+  sprintf(dev_path, "%s/%s", drm_dir_name, dent->d_name);


snprintf(dev_path, sizeof(dev_path), ...);



Ack.


+  fd = loader_open_device(dev_path);
+  if (fd == -1) {


nit: Perhaps fd < 0, just to be safe?



Ack.


+ _eglLog(_EGL_WARNING, "%s() Failed to open DRM device %s",
+ __func__, dev_path);
+ continue;
+  }
+
+  int ret = droid_probe_device(disp, fd, vendor_name);
+  switch (ret) {
+  case probe_success:
+ goto success;
+  case probe_filtered_out:
+ goto allow_fallback;


The 2 lines of code at the "allow_fallback" label could be just moved here.



Ack.


+  case probe_error:
+  case probe_no_driver:


Do we need 2 separate cases for these? Just one "probe_fail" should be enough.



Ack.


+ goto next;


If we move the fallback handling to "probe_filtered_out" case, we
could remove the "next" label too and simply "break" here.



Ack.


+  }
+
+allow_fallback:
+  if (fallback_fd == -1)
+ fallback_fd = fd;
+next:
+  if (fallback_fd != fd)
+ close(fd);
+  fd = -1;
+  continue;
+   }
+
+success:
+   closedir(sysdir);
+
+   if (fallback_fd < 0 && fd < 0) {
+  _eglLog(_EGL_WARNING, "Failed to open any DRM device");
+  return -1;
+   }
+
+   if (fd < 0) {
+  _eglLog(_EGL_WARNING, "Failed to open desired DRM device, using 
fallback");
+  return fallback_fd;
+   }
+
+   close(fallback_fd);
+   return fd;
+}


[Leaving context for readability.]

Best regards,
Tomasz


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Re: [Mesa-dev] [PATCH] i965/gen6/gs: Handle case where a GS doesn't allocate VUE

2018-06-20 Thread Iago Toral 
On Tue, 2018-06-19 at 17:06 +0300, Andrii Simiklit wrote:
> We can not use the VUE Dereference flags combination for EOT
> message under ILK and SNB because the threads are not initialized
> there with initial VUE handle unlike Pre-IL.
> So to avoid GPU hangs on SNB and ILK we need
> to avoid usage of the VUE Dereference flags combination.
> (Was tested only on SNB but according to the specification
> SNB Volume 2 Part 1: 1.6.5.3, 1.6.5.6
> the ILK must behave itself in the similar way)
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105399
> 
> Signed-off-by: Andrii Simiklit 
> ---
>  src/intel/compiler/gen6_gs_visitor.cpp | 56
> +-
>  1 file changed, 49 insertions(+), 7 deletions(-)
> 
> diff --git a/src/intel/compiler/gen6_gs_visitor.cpp
> b/src/intel/compiler/gen6_gs_visitor.cpp
> index 66c69fb..ac3ba55 100644
> --- a/src/intel/compiler/gen6_gs_visitor.cpp
> +++ b/src/intel/compiler/gen6_gs_visitor.cpp
> @@ -300,10 +300,11 @@ gen6_gs_visitor::emit_urb_write_opcode(bool
> complete, int base_mrf,
>/* Otherwise we always request to allocate a new VUE handle.
> If this is
> * the last write before the EOT message and the new handle
> never gets
> * used it will be dereferenced when we send the EOT message.
> This is
> -   * necessary to avoid different setups for the EOT message
> (one for the
> +   * necessary to avoid different setups (under Pre-IL only) for
> the EOT message (one for the
> * case when there is no output and another for the case when
> there is)
> * which would require to end the program with an
> IF/ELSE/ENDIF block,
> -   * something we do not want.
> +   * something we do not want. 
> +   * But for ILK and SNB we can not avoid the end the program
> with an IF/ELSE/ENDIF block.
> */
>inst = emit(GS_OPCODE_URB_WRITE_ALLOCATE);
>inst->urb_write_flags = BRW_URB_WRITE_COMPLETE;
> @@ -449,8 +450,11 @@ gen6_gs_visitor::emit_thread_end()
>if (prog->info.has_transform_feedback_varyings)
>   xfb_write();
> }
> -   emit(BRW_OPCODE_ENDIF);
> -
> +   const bool common_eot_approach_can_be_used = (devinfo->gen < 5);

We don't implement GS before gen6, and I don't think there are plans
for it at this point, so I think we can just simplify the patch by
assuming that devinfo->gen is always going to be 6 here (later gens use
a different implementation of GS).

> +   if(common_eot_approach_can_be_used)
> +   {
> +  emit(BRW_OPCODE_ENDIF);  
> +   }
> /* Finally, emit EOT message.
>  *
>  * In gen6 we need to end the thread differently depending on
> whether we have
> @@ -463,8 +467,32 @@ gen6_gs_visitor::emit_thread_end()
>  * VUE handle every time we do a URB WRITE, even for the last
> vertex we emit.
>  * With this we make sure that whether we have emitted at least
> one vertex
>  * or none at all, we have to finish the thread without writing
> to the URB,
> -* which works for both cases by setting the COMPLETE and UNUSED
> flags in
> -* the EOT message.
> +* which works for both cases (but only under Pre-IL) by setting 
> +* the COMPLETE and UNUSED flags in the EOT message.
> +* 
> +* But under ILK or SNB we must not use combination COMPLETE and
> UNUSED 
> +* because this combination could be used only for already
> allocated VUE. 
> +* But unlike Pre-IL in the ILK and SNB 
> +* the initial VUE is not passed to threads. 
> +* This behaver mentioned in specification: 
> +* SNB Volume 2 Part 1:
> +*  "1.6.5.3 VUE Allocation (GS, CLIP) [DevIL]"
> +*  "1.6.5.4 VUE Allocation (GS) [DevSNB+]"
> +* "The threads are not passed an initial handle.  
> +* Instead, they request a first handle (if any) 
> +* via the URB shared function’s FF_SYNC message (see Shared
> Functions). 
> +* If additional handles are required, 
> +* the URB_WRITE allocate mechanism (mentioned above) is
> used."
> +* 
> +* So for ILK and for SNB we must use only UNUSED flag.
> +* This is accepteble combination according to:
> +*SNB Volume 4 Part 2:
> +*   "2.4.2 Message Descriptor"
> +*  "Table lists the valid and invalid combinations of 
> +*   the Complete, Used, Allocate and EOT bits"
> +*  "Thread terminate non-write of URB"
> +*SNB Volume 2 Part 1:
> +*   "1.6.5.6 Thread Termination"
>  */

I am not sure why you conclude all this from the PRM. This is what I
see:

Section 1.6.5.5 VUE Dereference (GS) (vol2, part1) says:

"It is possible and legal for a thread to produce no output
 or subsequently allocate a destination VUE that 
 was not required (e.g., the thread allocated ahead). 
 Therefore, there is a mechanism by which a thread can “give back”  
 (dereference) an a llocated VUE.  This mechanism must  be used if   
 the  VUE is not written before the thread terminates.  A  kernel can

[Mesa-dev] [PATCH] squash! nir/linker: Add gl_nir_link_uniforms()

2018-06-20 Thread Alejandro Piñeiro 
From: Neil Roberts 

Sets var->driver.location if the uniform was found from a previous
stage.
---

Hi Timothy,

thanks for the review of the original patch. Recently we found that we
missed a little thing (one line). As we didn't push it to master yet,
could you take a look to this change, so we could include it now?

BR

 src/compiler/glsl/gl_nir_link_uniforms.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/glsl/gl_nir_link_uniforms.c 
b/src/compiler/glsl/gl_nir_link_uniforms.c
index a8ebde73270..d3a39577177 100644
--- a/src/compiler/glsl/gl_nir_link_uniforms.c
+++ b/src/compiler/glsl/gl_nir_link_uniforms.c
@@ -419,6 +419,7 @@ gl_nir_link_uniforms(struct gl_context *ctx,
  uniform = find_previous_uniform_storage(prog, var->data.location);
  if (uniform) {
 uniform->active_shader_mask |= 1 << shader_type;
+var->data.location = uniform - prog->data->UniformStorage;
 
 continue;
  }
-- 
2.14.1

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[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106151

--- Comment #20 from Samuel Pitoiset  ---
Created attachment 140246
  --> https://bugs.freedesktop.org/attachment.cgi?id=140246&action=edit
possible fix

Does this patch help?

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Re: [Mesa-dev] [PATCH v2 08/21] spirv: translate default-block uniforms

2018-06-20 Thread Alejandro Piñeiro 
Hi Timothy,

thanks for the review of the patches of this series. This patch and the
squash I have just sent are the only patches pending to be reviewed.

Would you mind to take a look to this patch too?

Thanks in advance


On 12/05/18 11:40, Alejandro Piñeiro wrote:
> From: Nicolai Hähnle 
>
> They are supported by SPIR-V for ARB_gl_spirv.
>
> v2 (changes on top of Nicolai's original patch):
>* Handle UniformConstant storage class for uniforms other than
>  samplers and images. (Eduardo Lima)
>* Handle location decoration also for samplers and images. (Eduardo
>  Lima)
>* Rebase update (spirv_to_nir options added, logging changes, and
>  others) (Alejandro Piñeiro)
>
> Signed-off-by: Nicolai Hähnle 
> Signed-off-by: Eduardo Lima 
> Signed-off-by: Alejandro Piñeiro 
> ---
>  src/compiler/spirv/vtn_private.h   |  1 +
>  src/compiler/spirv/vtn_variables.c | 25 +++--
>  2 files changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/src/compiler/spirv/vtn_private.h 
> b/src/compiler/spirv/vtn_private.h
> index b501bbf9b4a..183024e14f4 100644
> --- a/src/compiler/spirv/vtn_private.h
> +++ b/src/compiler/spirv/vtn_private.h
> @@ -402,6 +402,7 @@ enum vtn_variable_mode {
> vtn_variable_mode_local,
> vtn_variable_mode_global,
> vtn_variable_mode_param,
> +   vtn_variable_mode_uniform,
> vtn_variable_mode_ubo,
> vtn_variable_mode_ssbo,
> vtn_variable_mode_push_constant,
> diff --git a/src/compiler/spirv/vtn_variables.c 
> b/src/compiler/spirv/vtn_variables.c
> index fd8ab7f247a..eb8a9ca0084 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1544,8 +1544,11 @@ var_decoration_cb(struct vtn_builder *b, struct 
> vtn_value *val, int member,
>   vtn_var->mode == vtn_variable_mode_output) {
>   is_vertex_input = false;
>   location += vtn_var->patch ? VARYING_SLOT_PATCH0 : 
> VARYING_SLOT_VAR0;
> -  } else {
> - vtn_warn("Location must be on input or output variable");
> +  } else if (vtn_var->mode != vtn_variable_mode_uniform &&
> + vtn_var->mode != vtn_variable_mode_sampler &&
> + vtn_var->mode != vtn_variable_mode_image) {
> + vtn_warn("Location must be on input, output, uniform, sampler or "
> +  "image variable");
>   return;
>}
>  
> @@ -1611,7 +1614,9 @@ vtn_storage_class_to_mode(struct vtn_builder *b,
>   mode = vtn_variable_mode_ssbo;
>   nir_mode = 0;
>} else {
> - vtn_fail("Invalid uniform variable type");
> + /* Default-block uniforms, coming from gl_spirv */
> + mode = vtn_variable_mode_uniform;
> + nir_mode = nir_var_uniform;
>}
>break;
> case SpvStorageClassStorageBuffer:
> @@ -1619,15 +1624,13 @@ vtn_storage_class_to_mode(struct vtn_builder *b,
>nir_mode = 0;
>break;
> case SpvStorageClassUniformConstant:
> -  if (glsl_type_is_image(interface_type->type)) {
> +  if (glsl_type_is_image(interface_type->type))
>   mode = vtn_variable_mode_image;
> - nir_mode = nir_var_uniform;
> -  } else if (glsl_type_is_sampler(interface_type->type)) {
> +  else if (glsl_type_is_sampler(interface_type->type))
>   mode = vtn_variable_mode_sampler;
> - nir_mode = nir_var_uniform;
> -  } else {
> - vtn_fail("Invalid uniform constant variable type");
> -  }
> +  else
> + mode = vtn_variable_mode_uniform;
> +  nir_mode = nir_var_uniform;
>break;
> case SpvStorageClassPushConstant:
>mode = vtn_variable_mode_push_constant;
> @@ -1795,11 +1798,13 @@ vtn_create_variable(struct vtn_builder *b, struct 
> vtn_value *val,
> case vtn_variable_mode_global:
> case vtn_variable_mode_image:
> case vtn_variable_mode_sampler:
> +   case vtn_variable_mode_uniform:
>/* For these, we create the variable normally */
>var->var = rzalloc(b->shader, nir_variable);
>var->var->name = ralloc_strdup(var->var, val->name);
>var->var->type = var->type->type;
>var->var->data.mode = nir_mode;
> +  var->var->data.location = -1;
>  
>switch (var->mode) {
>case vtn_variable_mode_image:

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[Mesa-dev] [PATCH] docs/release-calendar: restore the missing 18.1 column

2018-06-20 Thread Emil Velikov 
From: Emil Velikov 

Earlier commit removed the column, instead of adjusting it's height.

Cc: Dylan Baker 
Fixes: 0d4f338a116 ("docs: Update release-notes and calendar")
Signed-off-by: Emil Velikov 
---
 docs/release-calendar.html | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/release-calendar.html b/docs/release-calendar.html
index af574c6b29b..fbaec2dd0c2 100644
--- a/docs/release-calendar.html
+++ b/docs/release-calendar.html
@@ -39,6 +39,7 @@ if you'd like to nominate a patch in the next stable release.
 Notes
 
 
+18.1
 2018-06-29
 18.1.3
 Dylan Baker
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 1/3] st/mesa/i965: Allow decompressing ETC2 to GL_RGBA

2018-06-20 Thread emil . velikov 
Hi Tomeu,

On Wed, May 23, 2018 at 10:54:06AM +0200, Tomeu Vizoso wrote:

> --- a/src/mesa/main/texcompress_etc.h
> +++ b/src/mesa/main/texcompress_etc.h
> @@ -28,6 +28,7 @@
>  #include "glheader.h"
>  #include "texcompress.h"
>  #include "texstore.h"
> +#include "pipe/p_format.h"
>
Gallium includes should not be present in mesa/main/.
If needed, having it in mesa/state_tracker/ sources is fine.

HTH
Emil
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[Mesa-dev] [Bug 106976] Compilation failure due to missing xcb_randr_lease_t

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106976

Bug ID: 106976
   Summary: Compilation failure due to missing xcb_randr_lease_t
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: Other
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: danylo.pilia...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

Recent commit
https://cgit.freedesktop.org/mesa/mesa/commit/?id=7ab1fffcd2a504024b16e408de329f7a94553ecc
broke Mesa compilation if version of xcb-randr is less than 1.13.

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[Mesa-dev] [PATCH v4 1/3] gallium/util: Fix build error due to cast to different size

2018-06-20 Thread Robert Foss 
Signed-off-by: Robert Foss 
Reviewed-by: Tomasz Figa 
---
Changes since v3:
 - Added r-b from Tomasz

 src/gallium/auxiliary/util/u_debug_stack_android.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_debug_stack_android.cpp 
b/src/gallium/auxiliary/util/u_debug_stack_android.cpp
index b3d56aebe6..395a1fe911 100644
--- a/src/gallium/auxiliary/util/u_debug_stack_android.cpp
+++ b/src/gallium/auxiliary/util/u_debug_stack_android.cpp
@@ -49,10 +49,10 @@ debug_backtrace_capture(debug_stack_frame *mesa_backtrace,
   backtrace_table = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
 _mesa_key_pointer_equal);
 
-   backtrace_entry = _mesa_hash_table_search(backtrace_table, (void*) tid);
+   backtrace_entry = _mesa_hash_table_search(backtrace_table, (void*) 
(uintptr_t)tid);
if (!backtrace_entry) {
   backtrace = Backtrace::Create(getpid(), tid);
-  _mesa_hash_table_insert(backtrace_table, (void*) tid, backtrace);
+  _mesa_hash_table_insert(backtrace_table, (void*) (uintptr_t)tid, 
backtrace);
} else {
   backtrace = (Backtrace *) backtrace_entry->data;
}
-- 
2.17.1

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[Mesa-dev] [PATCH v4 2/3] egl/android: #ifdef out flink name support

2018-06-20 Thread Robert Foss 
From: Rob Herring 

Maintaining both flink names and prime fd support which are provided by
2 different gralloc implementations is problematic because we have a
dependency on a specific gralloc implementation header.

This mostly disables the dependency on the gralloc implementation and
headers. The dependency on GRALLOC_MODULE_PERFORM_GET_DRM_FD remains for
now, but the definition is added locally to remove the header
dependency.

drm_gralloc support can be enabled by setting
BOARD_USES_DRM_GRALLOC=true in BoardConfig.mk.

Signed-off-by: Rob Herring 
Signed-off-by: Robert Foss 
Reviewed-by: Tomasz Figa 
---
Changes since v3:
 - Added r-b from Tomasz

Changes since RFC:
 - Instead of removing code, #ifdef it out

 src/egl/Android.mk  |  6 ++-
 src/egl/drivers/dri2/egl_dri2.h |  2 -
 src/egl/drivers/dri2/platform_android.c | 56 +++--
 3 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/src/egl/Android.mk b/src/egl/Android.mk
index 11818694f4..8412aeb798 100644
--- a/src/egl/Android.mk
+++ b/src/egl/Android.mk
@@ -57,9 +57,13 @@ LOCAL_SHARED_LIBRARIES := \
libhardware \
liblog \
libcutils \
-   libgralloc_drm \
libsync
 
+ifeq ($(BOARD_USES_DRM_GRALLOC),true)
+   LOCAL_CFLAGS += -DHAVE_DRM_GRALLOC
+   LOCAL_SHARED_LIBRARIES += libgralloc_drm
+endif
+
 ifeq ($(filter $(MESA_ANDROID_MAJOR_VERSION), 4 5 6 7),)
 LOCAL_SHARED_LIBRARIES += libnativewindow
 endif
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index adabc527f8..5d8fbfa235 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -67,8 +67,6 @@ struct zwp_linux_dmabuf_v1;
 
 #include 
 #include 
-#include 
-
 #endif /* HAVE_ANDROID_PLATFORM */
 
 #include "eglconfig.h"
diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 1d6ed92bd6..4ba96aad90 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -37,7 +37,11 @@
 #include "loader.h"
 #include "egl_dri2.h"
 #include "egl_dri2_fallbacks.h"
+
+#ifdef HAVE_DRM_GRALLOC
+#include 
 #include "gralloc_drm.h"
+#endif /* HAVE_DRM_GRALLOC */
 
 #define ALIGN(val, align)  (((val) + (align) - 1) & ~((align) - 1))
 
@@ -164,11 +168,13 @@ get_native_buffer_fd(struct ANativeWindowBuffer *buf)
return (handle && handle->numFds) ? handle->data[0] : -1;
 }
 
+#ifdef HAVE_DRM_GRALLOC
 static int
 get_native_buffer_name(struct ANativeWindowBuffer *buf)
 {
return gralloc_drm_get_gem_handle(buf->handle);
 }
+#endif /* HAVE_DRM_GRALLOC */
 
 static EGLBoolean
 droid_window_dequeue_buffer(struct dri2_egl_surface *dri2_surf)
@@ -838,6 +844,7 @@ droid_create_image_from_prime_fd(_EGLDisplay *disp, 
_EGLContext *ctx,
return dri2_create_image_dma_buf(disp, ctx, NULL, attr_list);
 }
 
+#ifdef HAVE_DRM_GRALLOC
 static _EGLImage *
 droid_create_image_from_name(_EGLDisplay *disp, _EGLContext *ctx,
  struct ANativeWindowBuffer *buf)
@@ -881,6 +888,7 @@ droid_create_image_from_name(_EGLDisplay *disp, _EGLContext 
*ctx,
 
return &dri2_img->base;
 }
+#endif /* HAVE_DRM_GRALLOC */
 
 static EGLBoolean
 droid_query_surface(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSurface *surf,
@@ -937,7 +945,11 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp,
if (fd >= 0)
   return droid_create_image_from_prime_fd(disp, ctx, buf, fd);
 
+#ifdef HAVE_DRM_GRALLOC
return droid_create_image_from_name(disp, ctx, buf);
+#else
+   return NULL;
+#endif
 }
 
 static _EGLImage *
@@ -959,6 +971,7 @@ droid_flush_front_buffer(__DRIdrawable * driDrawable, void 
*loaderPrivate)
 {
 }
 
+#ifdef HAVE_DRM_GRALLOC
 static int
 droid_get_buffers_parse_attachments(struct dri2_egl_surface *dri2_surf,
 unsigned int *attachments, int count)
@@ -1034,6 +1047,7 @@ droid_get_buffers_with_format(__DRIdrawable * driDrawable,
 
return dri2_surf->buffers;
 }
+#endif /* HAVE_DRM_GRALLOC */
 
 static unsigned
 droid_get_capability(void *loaderPrivate, enum dri_loader_cap cap)
@@ -1116,6 +1130,14 @@ droid_add_configs_for_visuals(_EGLDriver *drv, 
_EGLDisplay *dpy)
return (config_count != 0);
 }
 
+enum {
+/* perform(const struct gralloc_module_t *mod,
+ * int op,
+ * int *fd);
+ */
+GRALLOC_MODULE_PERFORM_GET_DRM_FD = 0x4002,
+};
+
 static int
 droid_open_device(struct dri2_egl_display *dri2_dpy)
 {
@@ -1158,6 +1180,7 @@ static const struct dri2_egl_display_vtbl 
droid_display_vtbl = {
.get_dri_drawable = dri2_surface_get_dri_drawable,
 };
 
+#ifdef HAVE_DRM_GRALLOC
 static const __DRIdri2LoaderExtension droid_dri2_loader_extension = {
.base = { __DRI_DRI2_LOADER, 4 },
 
@@ -1166,6 +1189,7 @@ static const __DRIdri2LoaderExtension 
droid_dri2_loader_extension = {
.getBuffersWithFormat = droid_get_buffers_with_format,
.getCapability= droid

[Mesa-dev] [PATCH v4 3/3] egl/android: Add DRM node probing and filtering

2018-06-20 Thread Robert Foss 
This patch both adds support for probing & filtering DRM nodes
and switches away from using the GRALLOC_MODULE_PERFORM_GET_DRM_FD
gralloc call.

Currently the filtering is based just on the driver name,
and the desired name is supplied using the "drm.gpu.vendor_name"
Android property.

Signed-off-by: Robert Foss 
---

Changes since v3:
 - Reduced number of probing return codes
 - Simplified driver vendor check in droid_probe_device()
 - Fixed type with ';' prepended to a if-statement
 - Removed a strlen call
 - Switched a sprintf to snprintf
 - Replaced fd == -1 check with < 0
 - Simplified switch+goto statements

Changes since v2:
 - Switch from drmGetDevices2 to manual renderD node iteration
 - Add probe_res enum to communicate probing results better
 - Avoid using _eglError() in internal static functions
 - Avoid actually loading the driver while probing, just verify
   that it exists.
 - Replace strlen call with the assumed length PROPERTY_VALUE_MAX

Changes since v1:
 - Do not rely on libdrm for probing
 - Distinguish between errors and when no drm devices are found

Changes since RFC:
 - Rebased on newer libdrm drmHandleMatch patch
 - Added support for driver probing


 src/egl/drivers/dri2/platform_android.c | 224 ++--
 1 file changed, 171 insertions(+), 53 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_android.c 
b/src/egl/drivers/dri2/platform_android.c
index 4ba96aad90..b9d1862bd1 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -27,12 +27,16 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 
 #include "loader.h"
 #include "egl_dri2.h"
@@ -1130,31 +1134,6 @@ droid_add_configs_for_visuals(_EGLDriver *drv, 
_EGLDisplay *dpy)
return (config_count != 0);
 }
 
-enum {
-/* perform(const struct gralloc_module_t *mod,
- * int op,
- * int *fd);
- */
-GRALLOC_MODULE_PERFORM_GET_DRM_FD = 0x4002,
-};
-
-static int
-droid_open_device(struct dri2_egl_display *dri2_dpy)
-{
-   int fd = -1, err = -EINVAL;
-
-   if (dri2_dpy->gralloc->perform)
- err = dri2_dpy->gralloc->perform(dri2_dpy->gralloc,
-  GRALLOC_MODULE_PERFORM_GET_DRM_FD,
-  &fd);
-   if (err || fd < 0) {
-  _eglLog(_EGL_WARNING, "fail to get drm fd");
-  fd = -1;
-   }
-
-   return (fd >= 0) ? fcntl(fd, F_DUPFD_CLOEXEC, 3) : -1;
-}
-
 static const struct dri2_egl_display_vtbl droid_display_vtbl = {
.authenticate = NULL,
.create_window_surface = droid_create_window_surface,
@@ -1215,6 +1194,170 @@ static const __DRIextension 
*droid_image_loader_extensions[] = {
NULL,
 };
 
+EGLBoolean
+droid_load_driver(_EGLDisplay *disp)
+{
+   struct dri2_egl_display *dri2_dpy = disp->DriverData;
+   const char *err;
+
+   dri2_dpy->driver_name = loader_get_driver_for_fd(dri2_dpy->fd);
+   if (dri2_dpy->driver_name == NULL)
+  return false;
+
+   dri2_dpy->is_render_node = drmGetNodeTypeFromFd(dri2_dpy->fd) == 
DRM_NODE_RENDER;
+
+   if (!dri2_dpy->is_render_node) {
+   #ifdef HAVE_DRM_GRALLOC
+   /* Handle control nodes using __DRI_DRI2_LOADER extension and GEM names
+* for backwards compatibility with drm_gralloc. (Do not use on new
+* systems.) */
+   dri2_dpy->loader_extensions = droid_dri2_loader_extensions;
+   if (!dri2_load_driver(disp)) {
+  err = "DRI2: failed to load driver";
+  goto error;
+   }
+   #else
+   err = "DRI2: handle is not for a render node";
+   goto error;
+   #endif
+   } else {
+   dri2_dpy->loader_extensions = droid_image_loader_extensions;
+   if (!dri2_load_driver_dri3(disp)) {
+  err = "DRI3: failed to load driver";
+  goto error;
+   }
+}
+
+   return true;
+
+error:
+   free(dri2_dpy->driver_name);
+   dri2_dpy->driver_name = NULL;
+   return false;
+}
+
+static bool
+droid_probe_driver(int fd)
+{
+   char *driver_name;
+
+   driver_name = loader_get_driver_for_fd(fd);
+   if (driver_name == NULL)
+  return false;
+
+   free(driver_name);
+   return true;
+}
+
+typedef enum {
+   probe_fail = -1,
+   probe_success = 0,
+   probe_filtered_out = 1,
+} probe_ret_t;
+
+static probe_ret_t
+droid_probe_device(_EGLDisplay *disp, int fd, char *vendor)
+{
+   int ret;
+
+   drmVersionPtr ver = drmGetVersion(fd);
+   if (!ver)
+  return probe_fail;
+
+   if (!ver->name) {
+  ret = probe_fail;
+  goto cleanup;
+   }
+
+   if (vendor && strncmp(vendor, ver->name, PROPERTY_VALUE_MAX) != 0) {
+  ret = probe_filtered_out;
+  goto cleanup;
+   }
+
+   if (!droid_probe_driver(fd)) {
+  ret = probe_fail;
+  goto cleanup;
+   }
+
+   ret = probe_success;
+
+cleanup:
+   drmFreeVersion(ver);
+   return ret;
+}
+
+static int
+droid_open_device(_EGLDisplay *disp)
+{
+   const int M

[Mesa-dev] [PATCH v4 0/3] egl/android: Add DRM node probing and filtering

2018-06-20 Thread Robert Foss 
This series replaces the dependency on
GRALLOC_MODULE_PERFORM_GET_DRM_FD with DRM node
probing and disables the support for drm_gralloc.

The series has been tested on Qemu+AOSP, where a
virtio gpu was successfully probed for and
opened.

The current branch can be found here:
https://gitlab.collabora.com/robertfoss/mesa/tree/drm_probing_v4

Changes since v3:
 - Reduced number of probing return codes
 - Simplified driver vendor check in droid_probe_device()
 - Fixed type with ';' prepended to a if-statement
 - Removed a strlen call
 - Switched a sprintf to snprintf
 - Replaced fd == -1 check with < 0
 - Simplified switch+goto statements

Changes since v2:
 - Fixed whitespace issue
 - Diversified return codes from probing functions
 - Switched away from using drmGetDevices2, to iterating over
   /dev/dir/renderD nodes manually

Changes since v1:
 - Added fix for build issue
 - Do not rely on libdrm for probing
 - Distinguish between errors and when no drm devices are found

Changes since RFC:
 - Rebased work on the libdrm patch [2].
 - Included patch from Rob Herring disabling drm_gralloc/flink
   support by default.
 - Added device handler driver probing.

Rob Herring (1):
  egl/android: #ifdef out flink name support

Robert Foss (2):
  gallium/util: Fix build error due to cast to different size
  egl/android: Add DRM node probing and filtering

 src/egl/Android.mk|   6 +-
 src/egl/drivers/dri2/egl_dri2.h   |   2 -
 src/egl/drivers/dri2/platform_android.c   | 228 +++---
 .../auxiliary/util/u_debug_stack_android.cpp  |   4 +-
 4 files changed, 196 insertions(+), 44 deletions(-)

-- 
2.17.1

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[Mesa-dev] [PATCH] configure.ac: Check for xcb-randr version and xrandr to enable leasing

2018-06-20 Thread Danylo Piliaiev 
VK_USE_PLATFORM_XLIB_XRANDR_EXT requires xlib leasing which requires
xcb-randr >= 1.13. Also xrandr header is required for this extension.
The extension should not be automatically enabled if these dependencies
aren't satisfied.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106976

Signed-off-by: Danylo Piliaiev 
---
 configure.ac | 23 ++-
 1 file changed, 10 insertions(+), 13 deletions(-)

diff --git a/configure.ac b/configure.ac
index 0652410..ab59e06 100644
--- a/configure.ac
+++ b/configure.ac
@@ -97,6 +97,7 @@ XCBDRI2_REQUIRED=1.8
 XCBDRI3_MODIFIERS_REQUIRED=1.13
 XCBGLX_REQUIRED=1.8.1
 XCBPRESENT_MODIFIERS_REQUIRED=1.13
+XCBRANDR_XLEASE_REQUIRED=1.13
 XDAMAGE_REQUIRED=1.1
 XSHMFENCE_REQUIRED=1.1
 XVMC_REQUIRED=1.0.6
@@ -1867,18 +1868,6 @@ if test x"$enable_dri3" = xyes; then
 fi
 fi
 
-
-if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; then
-have_xlease=yes
-else
-have_xlease=no
-fi
-
-if test x"$have_xlease" = xyes; then
-randr_modules="x11-xcb xcb-randr"
-PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
-fi
-
 AM_CONDITIONAL(HAVE_PLATFORM_X11, echo "$platforms" | grep -q 'x11')
 AM_CONDITIONAL(HAVE_PLATFORM_WAYLAND, echo "$platforms" | grep -q 'wayland')
 AM_CONDITIONAL(HAVE_PLATFORM_DRM, echo "$platforms" | grep -q 'drm')
@@ -1896,12 +1885,20 @@ xno)
 ;;
 *)
 if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; 
then
-enable_xlib_lease=yes
+xlease_modules="x11-xcb xcb-randr >= $XCBRANDR_XLEASE_REQUIRED xrandr"
+PKG_CHECK_EXISTS([$xlease_modules], [enable_xlib_lease=yes], 
[enable_xlib_lease=no])
 else
 enable_xlib_lease=no
 fi
 esac
 
+if test x"$enable_xlib_lease" = xyes; then
+randr_modules="x11-xcb xcb-randr >= $XCBRANDR_XLEASE_REQUIRED"
+PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
+xlib_randr_modules="xrandr"
+PKG_CHECK_MODULES([XLIB_RANDR], [$xlib_randr_modules])
+fi
+
 AM_CONDITIONAL(HAVE_XLIB_LEASE, test "x$enable_xlib_lease" = xyes)
 
 dnl
-- 
2.7.4

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[Mesa-dev] [Bug 106976] Compilation failure due to missing xcb_randr_lease_t

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106976

Danylo  changed:

   What|Removed |Added

 CC||danylo.pilia...@gmail.com

--- Comment #1 from Danylo  ---
Sent a patch to fix the issue: https://patchwork.freedesktop.org/patch/230590/

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[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106151

--- Comment #21 from Samuel Pitoiset  ---
If my patch doesn't help, can you try master with "export
RADV_DEBUG=nocompute"?

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Re: [Mesa-dev] [PATCH 1/2] freedreno: a2xx: fix crash on first clear

2018-06-20 Thread Rob Clark 
On Tue, Jun 19, 2018 at 9:02 PM, Jonathan Marek  wrote:
> blend can be NULL, so check for that

hmm, which case are you hitting that?  From a quick look I think
a3xx-a5xx would have the same issue.  Maybe we should just init
ctx->blend to a dummy state obj when the ctx is created?

BR,
-R

>
> Signed-off-by: Jonathan Marek 
> ---
>  src/gallium/drivers/freedreno/a2xx/fd2_emit.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c 
> b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
> index 9c765dfd88..e36eebf98c 100644
> --- a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
> +++ b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
> @@ -303,7 +303,7 @@ fd2_emit_state(struct fd_context *ctx, const enum 
> fd_dirty_3d_state dirty)
> if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) {
> OUT_PKT3(ring, CP_SET_CONSTANT, 2);
> OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
> -   OUT_RING(ring, zsa->rb_colorcontrol | blend->rb_colorcontrol);
> +   OUT_RING(ring, blend ? zsa->rb_colorcontrol | 
> blend->rb_colorcontrol : 0);
> }
>
> if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
> @@ -313,13 +313,13 @@ fd2_emit_state(struct fd_context *ctx, const enum 
> fd_dirty_3d_state dirty)
>
> OUT_PKT3(ring, CP_SET_CONSTANT, 2);
> OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
> -   OUT_RING(ring, blend->rb_blendcontrol_alpha |
> +   OUT_RING(ring, blend ? blend->rb_blendcontrol_alpha |
> COND(has_alpha, blend->rb_blendcontrol_rgb) |
> -   COND(!has_alpha, 
> blend->rb_blendcontrol_no_alpha_rgb));
> +   COND(!has_alpha, blend->rb_blendcontrol_no_alpha_rgb) 
> : 0);
>
> OUT_PKT3(ring, CP_SET_CONSTANT, 2);
> OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
> -   OUT_RING(ring, blend->rb_colormask);
> +   OUT_RING(ring, blend ? blend->rb_colormask : 0xf);
> }
>
> if (dirty & FD_DIRTY_BLEND_COLOR) {
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 1/2] freedreno: a2xx: fix crash on first clear

2018-06-20 Thread Ilia Mirkin 
On Wed, Jun 20, 2018 at 9:56 AM, Rob Clark  wrote:
> On Tue, Jun 19, 2018 at 9:02 PM, Jonathan Marek  wrote:
>> blend can be NULL, so check for that
>
> hmm, which case are you hitting that?  From a quick look I think
> a3xx-a5xx would have the same issue.  Maybe we should just init
> ctx->blend to a dummy state obj when the ctx is created?

This generally happens with clears. A long time ago, st/mesa got
rejiggered slightly, and a glClear() could happen before a blend state
was bound. Many drivers implement clear by doing some amount of
validation, so they have to watch out. I'm sure a3xx+ were already
fixed for this, but not surprising that a2xx still has issues.

  -ilia
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Re: [Mesa-dev] [PATCH 1/2] freedreno: a2xx: fix crash on first clear

2018-06-20 Thread Rob Clark 
On Wed, Jun 20, 2018 at 10:01 AM, Ilia Mirkin  wrote:
> On Wed, Jun 20, 2018 at 9:56 AM, Rob Clark  wrote:
>> On Tue, Jun 19, 2018 at 9:02 PM, Jonathan Marek  wrote:
>>> blend can be NULL, so check for that
>>
>> hmm, which case are you hitting that?  From a quick look I think
>> a3xx-a5xx would have the same issue.  Maybe we should just init
>> ctx->blend to a dummy state obj when the ctx is created?
>
> This generally happens with clears. A long time ago, st/mesa got
> rejiggered slightly, and a glClear() could happen before a blend state
> was bound. Many drivers implement clear by doing some amount of
> validation, so they have to watch out. I'm sure a3xx+ were already
> fixed for this, but not surprising that a2xx still has issues.
>

ahh, ok.. that makes more sense.. a5xx uses hw blitter for clears, and
a3xx-a4xx use u_blitter.. a2xx is doing something a bit more custom
since (iirc) I didn't know how to write depth from frag shader..

BR,
-R
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[Mesa-dev] [PATCH 2/2] radv: set EVENT_WRITE_EOP.INT_SEL = wait for write confirmation

2018-06-20 Thread Samuel Pitoiset 
Ported from RadeonSI.
Not sure why this is needed but AMDVLK does something similar.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/si_cmd_buffer.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index d6b073c783..e350bccae3 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -686,11 +686,17 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
EVENT_INDEX(5) |
event_flags;
unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
+   unsigned sel = EOP_DATA_SEL(data_sel);
+
+   /* Wait for write confirmation before writing data, but don't send
+* an interrupt. */
+   if (data_sel != EOP_DATA_SEL_DISCARD)
+   sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
 
if (chip_class >= GFX9 || is_gfx8_mec) {
radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, 
predicated));
radeon_emit(cs, op);
-   radeon_emit(cs, EOP_DATA_SEL(data_sel));
+   radeon_emit(cs, sel);
radeon_emit(cs, va);/* address lo */
radeon_emit(cs, va >> 32);  /* address hi */
radeon_emit(cs, new_fence); /* immediate data lo */
@@ -707,7 +713,7 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 
predicated));
radeon_emit(cs, op);
radeon_emit(cs, va);
-   radeon_emit(cs, ((va >> 32) & 0x) | 
EOP_DATA_SEL(data_sel));
+   radeon_emit(cs, ((va >> 32) & 0x) | sel);
radeon_emit(cs, old_fence); /* immediate data */
radeon_emit(cs, 0); /* unused */
}
@@ -715,7 +721,7 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
radeon_emit(cs, op);
radeon_emit(cs, va);
-   radeon_emit(cs, ((va >> 32) & 0x) | EOP_DATA_SEL(data_sel));
+   radeon_emit(cs, ((va >> 32) & 0x) | sel);
radeon_emit(cs, new_fence); /* immediate data */
radeon_emit(cs, 0); /* unused */
}
-- 
2.17.1

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[Mesa-dev] [PATCH 1/2] radv: use EOP_DATA_SEL_* instead of magic numbers

2018-06-20 Thread Samuel Pitoiset 
Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_cmd_buffer.c | 2 +-
 src/amd/vulkan/radv_query.c  | 9 ++---
 src/amd/vulkan/si_cmd_buffer.c   | 7 +--
 3 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 2afb35292a..8bd41bc41a 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4241,7 +4241,7 @@ static void write_event(struct radv_cmd_buffer 
*cmd_buffer,
   
cmd_buffer->device->physical_device->rad_info.chip_class,
   radv_cmd_buffer_uses_mec(cmd_buffer),
   V_028A90_BOTTOM_OF_PIPE_TS, 0,
-  1, va, 2, value);
+  EOP_DATA_SEL_VALUE_32BIT, va, 2, value);
 
assert(cmd_buffer->cs->cdw <= cdw_max);
 }
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 559b7cd49d..e1c91630ff 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1169,7 +1169,8 @@ static void emit_end_query(struct radv_cmd_buffer 
*cmd_buffer,
   
cmd_buffer->device->physical_device->rad_info.chip_class,
   radv_cmd_buffer_uses_mec(cmd_buffer),
   V_028A90_BOTTOM_OF_PIPE_TS, 0,
-  1, avail_va, 0, 1);
+  EOP_DATA_SEL_VALUE_32BIT,
+  avail_va, 0, 1);
break;
default:
unreachable("ending unhandled query type");
@@ -1292,13 +1293,15 @@ void radv_CmdWriteTimestamp(
   
cmd_buffer->device->physical_device->rad_info.chip_class,
   mec,
   V_028A90_BOTTOM_OF_PIPE_TS, 
0,
-  3, query_va, 0, 0);
+  EOP_DATA_SEL_TIMESTAMP,
+  query_va, 0, 0);
si_cs_emit_write_event_eop(cs,
   false,
   
cmd_buffer->device->physical_device->rad_info.chip_class,
   mec,
   V_028A90_BOTTOM_OF_PIPE_TS, 
0,
-  1, avail_va, 0, 1);
+  EOP_DATA_SEL_VALUE_32BIT,
+  avail_va, 0, 1);
break;
}
query_va += pool->stride;
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index a663d2add6..d6b073c783 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -799,7 +799,9 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
   chip_class,
   is_mec,
   
V_028A90_FLUSH_AND_INV_CB_DATA_TS,
-  0, 0, 0, 0, 0);
+  0,
+  EOP_DATA_SEL_DISCARD,
+  0, 0, 0);
}
}
if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
@@ -867,7 +869,8 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
assert(flush_cnt);
uint32_t old_fence = (*flush_cnt)++;
 
-   si_cs_emit_write_event_eop(cs, false, chip_class, false, 
cb_db_event, tc_flags, 1,
+   si_cs_emit_write_event_eop(cs, false, chip_class, false, 
cb_db_event, tc_flags,
+  EOP_DATA_SEL_VALUE_32BIT,
   flush_va, old_fence, *flush_cnt);
si_emit_wait_fence(cs, false, flush_va, *flush_cnt, 0x);
}
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] virgl: add ARB_texture_view support

2018-06-20 Thread Gert Wollny 
Looks good to me 
Reviewed-By: Gert Wollny 

Am Freitag, den 08.06.2018, 11:20 +1000 schrieb Dave Airlie:
> From: Dave Airlie 
> 
> ---
>  docs/features.txt| 2 +-
>  src/gallium/drivers/virgl/virgl_encode.c | 7 +--
>  src/gallium/drivers/virgl/virgl_hw.h | 1 +
>  src/gallium/drivers/virgl/virgl_screen.c | 3 ++-
>  4 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/docs/features.txt b/docs/features.txt
> index 6e5cbc8b11e..118ed8a76ae 100644
> --- a/docs/features.txt
> +++ b/docs/features.txt
> @@ -187,7 +187,7 @@ GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0,
> r600, radeonsi
>GL_ARB_texture_buffer_range   DONE
> (freedreno, nv50, i965, llvmpipe, virgl)
>GL_ARB_texture_query_levels   DONE (all
> drivers that support GLSL 1.30)
>GL_ARB_texture_storage_multisampleDONE (all
> drivers that support GL_ARB_texture_multisample)
> -  GL_ARB_texture_view   DONE
> (freedreno, i965, nv50, llvmpipe, softpipe, swr)
> +  GL_ARB_texture_view   DONE
> (freedreno, i965, nv50, llvmpipe, softpipe, swr, virgl)
>GL_ARB_vertex_attrib_binding  DONE (all
> drivers)
>  
>  
> diff --git a/src/gallium/drivers/virgl/virgl_encode.c
> b/src/gallium/drivers/virgl/virgl_encode.c
> index f3cbd1ca4b0..373f1d494e0 100644
> --- a/src/gallium/drivers/virgl/virgl_encode.c
> +++ b/src/gallium/drivers/virgl/virgl_encode.c
> @@ -585,12 +585,15 @@ int virgl_encode_sampler_view(struct
> virgl_context *ctx,
>   const struct pipe_sampler_view *state)
>  {
> unsigned elem_size = util_format_get_blocksize(state->format);
> -
> +   struct virgl_screen *rs = virgl_screen(ctx->base.screen);
> uint32_t tmp;
> +   uint32_t dword_fmt_target = state->format;
> virgl_encoder_write_cmd_dword(ctx,
> VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_SAMPLER_VIEW,
> VIRGL_OBJ_SAMPLER_VIEW_SIZE));
> virgl_encoder_write_dword(ctx->cbuf, handle);
> virgl_encoder_write_res(ctx, res);
> -   virgl_encoder_write_dword(ctx->cbuf, state->format);
> +   if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW)
> + dword_fmt_target |= (state->target << 24);
> +   virgl_encoder_write_dword(ctx->cbuf, dword_fmt_target);
> if (res->u.b.target == PIPE_BUFFER) {
>virgl_encoder_write_dword(ctx->cbuf, state->u.buf.offset /
> elem_size);
>virgl_encoder_write_dword(ctx->cbuf, (state->u.buf.offset +
> state->u.buf.size) / elem_size - 1);
> diff --git a/src/gallium/drivers/virgl/virgl_hw.h
> b/src/gallium/drivers/virgl/virgl_hw.h
> index ee58520f9bb..d338051d9b3 100644
> --- a/src/gallium/drivers/virgl/virgl_hw.h
> +++ b/src/gallium/drivers/virgl/virgl_hw.h
> @@ -200,6 +200,7 @@ enum virgl_formats {
>  /* These are used by the capability_bits field in virgl_caps_v2. */
>  #define VIRGL_CAP_NONE 0
>  #define VIRGL_CAP_TGSI_INVARIANT   (1 << 0)
> +#define VIRGL_CAP_TEXTURE_VIEW (1 << 1)
>  
>  #define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
>  #define VIRGL_BIND_RENDER_TARGET (1 << 1)
> diff --git a/src/gallium/drivers/virgl/virgl_screen.c
> b/src/gallium/drivers/virgl/virgl_screen.c
> index e8d1c751779..03014c63319 100644
> --- a/src/gallium/drivers/virgl/virgl_screen.c
> +++ b/src/gallium/drivers/virgl/virgl_screen.c
> @@ -213,6 +213,8 @@ virgl_get_param(struct pipe_screen *screen, enum
> pipe_cap param)
>return vscreen-
> >caps.caps.v1.bset.transform_feedback_overflow_query;
> case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
>return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
> +   case PIPE_CAP_SAMPLER_VIEW_TARGET:
> +  return vscreen->caps.caps.v2.capability_bits &
> VIRGL_CAP_TEXTURE_VIEW;
> case PIPE_CAP_TEXTURE_GATHER_SM5:
> case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
> case PIPE_CAP_FAKE_SW_MSAA:
> @@ -221,7 +223,6 @@ virgl_get_param(struct pipe_screen *screen, enum
> pipe_cap param)
> case PIPE_CAP_MULTI_DRAW_INDIRECT:
> case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
> case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
> -   case PIPE_CAP_SAMPLER_VIEW_TARGET:
> case PIPE_CAP_CLIP_HALFZ:
> case PIPE_CAP_VERTEXID_NOBASE:
> case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
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[Mesa-dev] [PATCH] radv: remove unused 'predicated' param from some functions

2018-06-20 Thread Samuel Pitoiset 
It's always false.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_cmd_buffer.c |  3 +--
 src/amd/vulkan/radv_private.h|  2 --
 src/amd/vulkan/radv_query.c  |  7 ++-
 src/amd/vulkan/si_cmd_buffer.c   | 28 
 4 files changed, 15 insertions(+), 25 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8bd41bc41a..8ea780dcb2 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4237,7 +4237,6 @@ static void write_event(struct radv_cmd_buffer 
*cmd_buffer,
 * the stage mask. */
 
si_cs_emit_write_event_eop(cs,
-  cmd_buffer->state.predicating,
   
cmd_buffer->device->physical_device->rad_info.chip_class,
   radv_cmd_buffer_uses_mec(cmd_buffer),
   V_028A90_BOTTOM_OF_PIPE_TS, 0,
@@ -4289,7 +4288,7 @@ void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
 
MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws, cs, 7);
 
-   si_emit_wait_fence(cs, false, va, 1, 0x);
+   si_emit_wait_fence(cs, va, 1, 0x);
assert(cmd_buffer->cs->cdw <= cdw_max);
}
 
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index c77a8b297f..a97ec53fb2 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1061,7 +1061,6 @@ uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
   bool instanced_draw, bool indirect_draw,
   uint32_t draw_vertex_count);
 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
-   bool predicated,
enum chip_class chip_class,
bool is_mec,
unsigned event, unsigned event_flags,
@@ -1071,7 +1070,6 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
uint32_t new_fence);
 
 void si_emit_wait_fence(struct radeon_cmdbuf *cs,
-   bool predicated,
uint64_t va, uint32_t ref,
uint32_t mask);
 void si_cs_emit_cache_flush(struct radeon_cmdbuf *cs,
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index e1c91630ff..3920dcb376 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -992,7 +992,7 @@ void radv_CmdCopyQueryPoolResults(
uint64_t avail_va = va + 
pool->availability_offset + 4 * query;
 
/* This waits on the ME. All copies below are 
done on the ME */
-   si_emit_wait_fence(cs, false, avail_va, 1, 
0x);
+   si_emit_wait_fence(cs, avail_va, 1, 0x);
}
}
radv_query_shader(cmd_buffer, 
cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
@@ -1015,7 +1015,7 @@ void radv_CmdCopyQueryPoolResults(
uint64_t avail_va = va + 
pool->availability_offset + 4 * query;
 
/* This waits on the ME. All copies below are 
done on the ME */
-   si_emit_wait_fence(cs, false, avail_va, 1, 
0x);
+   si_emit_wait_fence(cs, avail_va, 1, 0x);
}
if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
uint64_t avail_va = va + 
pool->availability_offset + 4 * query;
@@ -1165,7 +1165,6 @@ static void emit_end_query(struct radv_cmd_buffer 
*cmd_buffer,
radeon_emit(cs, va >> 32);
 
si_cs_emit_write_event_eop(cs,
-  false,
   
cmd_buffer->device->physical_device->rad_info.chip_class,
   radv_cmd_buffer_uses_mec(cmd_buffer),
   V_028A90_BOTTOM_OF_PIPE_TS, 0,
@@ -1289,14 +1288,12 @@ void radv_CmdWriteTimestamp(
break;
default:
si_cs_emit_write_event_eop(cs,
-  false,
   
cmd_buffer->device->physical_device->rad_info.chip_class,
   mec,
   V_028A90_BOTTOM_OF_PIPE_TS, 
0,
   EOP_DATA_SEL_TIMESTAMP,
   query_va, 0, 0);
si_cs_emit_write_event_eop(cs,
-  false,

Re: [Mesa-dev] [PATCH mesa 1/2] intel/aubinator: fix mem leak

2018-06-20 Thread Lionel Landwerlin 

Reviewed-by: Lionel Landwerlin 

On 19/06/18 16:05, Eric Engestrom wrote:

Signed-off-by: Eric Engestrom 
---
  src/intel/tools/aubinator.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index c8d79ae377d68285bd1e..e4fb8adada354253143c 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -671,6 +671,7 @@ int main(int argc, char *argv[])
 /* close the stdout which is opened to write the output */
 close(1);
 free(xml_path);
+   free(file);
  
 wait(NULL);
  



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[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106151

--- Comment #22 from pritzl3...@gmail.com ---
I am away travelling and I wont be able to try the patch until late next week.
I will try the patch when I'm back and get back with the results.

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[Mesa-dev] [PATCH v2] anv, radv: Add support for VK_KHR_get_display_properties2

2018-06-20 Thread Jason Ekstrand 
Cc: Keith Packard 
---
 src/amd/vulkan/radv_extensions.py   |   1 +
 src/amd/vulkan/radv_wsi_display.c   |  57 +
 src/intel/vulkan/anv_extensions.py  |   1 +
 src/intel/vulkan/anv_wsi_display.c  |  56 +
 src/vulkan/wsi/wsi_common_display.c | 175 +---
 src/vulkan/wsi/wsi_common_display.h |  27 +
 6 files changed, 301 insertions(+), 16 deletions(-)

diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index 65ce7349016..5eb63a7d5dc 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -66,6 +66,7 @@ EXTENSIONS = [
 Extension('VK_KHR_external_semaphore',1, 
'device->rad_info.has_syncobj'),
 Extension('VK_KHR_external_semaphore_capabilities',   1, True),
 Extension('VK_KHR_external_semaphore_fd', 1, 
'device->rad_info.has_syncobj'),
+Extension('VK_KHR_get_display_properties2',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_KHR_get_memory_requirements2',  1, True),
 Extension('VK_KHR_get_physical_device_properties2',   1, True),
 Extension('VK_KHR_get_surface_capabilities2', 1, 
'RADV_HAS_SURFACE'),
diff --git a/src/amd/vulkan/radv_wsi_display.c 
b/src/amd/vulkan/radv_wsi_display.c
index 84431019dbb..764180ec7b5 100644
--- a/src/amd/vulkan/radv_wsi_display.c
+++ b/src/amd/vulkan/radv_wsi_display.c
@@ -56,6 +56,20 @@ radv_GetPhysicalDeviceDisplayPropertiesKHR(VkPhysicalDevice 
physical_device,
properties);
 }
 
+VkResult
+radv_GetPhysicalDeviceDisplayProperties2KHR(VkPhysicalDevice physical_device,
+uint32_t *property_count,
+VkDisplayProperties2KHR 
*properties)
+{
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
+
+   return wsi_display_get_physical_device_display_properties2(
+   physical_device,
+   &pdevice->wsi_device,
+   property_count,
+   properties);
+}
+
 VkResult
 radv_GetPhysicalDeviceDisplayPlanePropertiesKHR(
VkPhysicalDevice physical_device,
@@ -71,6 +85,21 @@ radv_GetPhysicalDeviceDisplayPlanePropertiesKHR(
properties);
 }
 
+VkResult
+radv_GetPhysicalDeviceDisplayPlaneProperties2KHR(
+   VkPhysicalDevice physical_device,
+   uint32_t *property_count,
+   VkDisplayPlaneProperties2KHR *properties)
+{
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
+
+   return wsi_display_get_physical_device_display_plane_properties2(
+   physical_device,
+   &pdevice->wsi_device,
+   property_count,
+   properties);
+}
+
 VkResult
 radv_GetDisplayPlaneSupportedDisplaysKHR(VkPhysicalDevice physical_device,
  uint32_t plane_index,
@@ -103,6 +132,21 @@ radv_GetDisplayModePropertiesKHR(VkPhysicalDevice 
physical_device,
   properties);
 }
 
+VkResult
+radv_GetDisplayModeProperties2KHR(VkPhysicalDevice physical_device,
+  VkDisplayKHR display,
+  uint32_t *property_count,
+  VkDisplayModeProperties2KHR *properties)
+{
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
+
+   return wsi_display_get_display_mode_properties2(physical_device,
+   &pdevice->wsi_device,
+   display,
+   property_count,
+   properties);
+}
+
 VkResult
 radv_CreateDisplayModeKHR(VkPhysicalDevice physical_device,
   VkDisplayKHR display,
@@ -135,6 +179,19 @@ radv_GetDisplayPlaneCapabilitiesKHR(VkPhysicalDevice 
physical_device,
  capabilities);
 }
 
+VkResult
+radv_GetDisplayPlaneCapabilities2KHR(VkPhysicalDevice physical_device,
+ const VkDisplayPlaneInfo2KHR 
*pDisplayPlaneInfo,
+ VkDisplayPlaneCapabilities2KHR 
*capabilities)
+{
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
+
+   return wsi_get_display_plane_capabilities2(physical_device,
+  &pdevice->wsi_device,
+  pDisplayPlaneInfo,
+  capabilities);
+}
+
 VkResult
 radv_CreateDisplayPlaneSurfaceKHR(
VkInstance _instance,
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index 2bba4ee4d2b..e3e996ad136 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -88,6 +88,7 @@ EXTENSIONS = [
 Extensi

Re: [Mesa-dev] [PATCH] anv, radv: Add support for VK_KHR_get_display_properties2

2018-06-20 Thread Jason Ekstrand 
On Tue, Jun 19, 2018 at 10:05 PM, Keith Packard  wrote:

> Jason Ekstrand  writes:
>
> > Thoughts?
>
> You've looked at the code more closely than I have; please feel free to
> leave it if you think it would seem worse as separate functions.
>

I just sent a v2 which allocates a temporary array, calls properties2, and
then copies it back over.  It doesn't duplicate the iteration code and
instead just leverages propertie2.  On the down side, it's a bit more
allocation and data motion but, compared to the ioctl that properties2 is
doing, it shouldn't be noticeable.  Let me know what you think of that
version.

--Jason
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Re: [Mesa-dev] [PATCH] docs/release-calendar: restore the missing 18.1 column

2018-06-20 Thread Dylan Baker 
Quoting Emil Velikov (2018-06-20 05:33:48)
> From: Emil Velikov 
> 
> Earlier commit removed the column, instead of adjusting it's height.
> 
> Cc: Dylan Baker 
> Fixes: 0d4f338a116 ("docs: Update release-notes and calendar")
> Signed-off-by: Emil Velikov 
> ---
>  docs/release-calendar.html | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/docs/release-calendar.html b/docs/release-calendar.html
> index af574c6b29b..fbaec2dd0c2 100644
> --- a/docs/release-calendar.html
> +++ b/docs/release-calendar.html
> @@ -39,6 +39,7 @@ if you'd like to nominate a patch in the next stable 
> release.
>  Notes
>  
>  
> +18.1
>  2018-06-29
>  18.1.3
>  Dylan Baker
> -- 
> 2.17.1
> 

Reviewed-by: Dylan Baker 

I'll be glad for the sphinx stuff to land and not have to hand edit html :/

Dylan


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Re: [Mesa-dev] [PATCH 01/24] configure.ac: Add CFLAG -Wno-missing-field-initializers (v5)

2018-06-20 Thread Dylan Baker 
Quoting Gert Wollny (2018-06-20 01:24:51)
> Hi Dylan & Eric, 
> 
> are you fine with how the flag is added now in meson? If you don't have
> any complaints I'm going to push the changes later today. 
> 
> many thanks, 
> Gert 
> 
> Am Dienstag, den 19.06.2018, 10:07 +0200 schrieb Gert Wollny:
> > This warning is misleading: When a struct is partially initialized
> > without
> > assigning to the structure members by name, then the remaining fields
> > will be zeroed out, and this warning will be issued (if enabled). If,
> > on the
> > other hand, the partial initialization is done by assigning to named
> > members,
> > the remaining structure elements may hold random data, but the
> > warning is not
> > issued. Since in Mesa the first approach to initialize structure
> > elements is
> > used very often, and it is usually assumed that the remaining
> > elements are
> > zeroed out, heeding this warning would be counter-productive.
> > 
> > v2: - add -Wno-missing-field-initializers to meson-build
> > - fix empty line error
> > (both Eric Engestrom)
> > 
> > v3: * check for -Wmissing-field-initializers warning and then disable
> > it
> >   because gcc and clang always accept -Wno-* (Dylan Baker)
> > * Also disable this warning for C++
> > 
> > v4: * meson.build add -Wno-missing-field-initializers to
> >   c_args instead of no_override_init_args (Eric Engstrom)
> > 
> > v5: * configure.ac: Correct copy/paste error with CFLAGS/CXXFLAGS
> > 
> > Reviewed-by: Marek Ol\u0161ák  (v1)
> > Reviewed-by: Emil Velikov  (v2)
> > Signed-off-by: Gert Wollny 
> > ---
> >  configure.ac |  4 
> >  meson.build  | 13 ++---
> >  2 files changed, 14 insertions(+), 3 deletions(-)
> > 
> > diff --git a/configure.ac b/configure.ac
> > index 7a0e475420..1529e47c95 100644
> > --- a/configure.ac
> > +++ b/configure.ac
> > @@ -302,7 +302,10 @@ AX_CHECK_COMPILE_FLAG([-
> > Wall], [CFLAGS="$CFLAGS
> >  AX_CHECK_COMPILE_FLAG([-Werror=implicit-function-declaration],
> > [CFLAGS="$CFLAGS -Werror=implicit-function-declaration"])
> >  AX_CHECK_COMPILE_FLAG([-Werror=missing-
> > prototypes],[CFLAGS="$CFLAGS -Werror=missing-
> > prototypes"])
> >  AX_CHECK_COMPILE_FLAG([-Wmissing-
> > prototypes],  [CFLAGS="$CFLAGS -Wmissing-
> > prototypes"])
> > +dnl Dylan Baker: gcc and clang always accepr -Wno-*, hence check for
> > the original warning, then set the no-* flag
> > +AX_CHECK_COMPILE_FLAG([-Wmissing-field-
> > initializers],  [CFLAGS="$CFLAGS -Wno-missing-field-
> > initializers"])
> >  AX_CHECK_COMPILE_FLAG([-fno-math-
> > errno],   [CFLAGS="$CFLAGS -fno-math-errno"])
> > +
> >  AX_CHECK_COMPILE_FLAG([-fno-trapping-
> > math],[CFLAGS="$CFLAGS -fno-trapping-math"])
> >  AX_CHECK_COMPILE_FLAG([-
> > fvisibility=hidden],   [VISIBILITY_CFLAGS="-
> > fvisibility=hidden"])
> >  
> > @@ -314,6 +317,7 @@ AX_CHECK_COMPILE_FLAG([-
> > Wall], [CXXFLAGS="$CXXFL
> >  AX_CHECK_COMPILE_FLAG([-fno-math-
> > errno],   [CXXFLAGS="$CXXFLAGS -fno-math-errno"])
> >  AX_CHECK_COMPILE_FLAG([-fno-trapping-
> > math],[CXXFLAGS="$CXXFLAGS -fno-trapping-math"])
> >  AX_CHECK_COMPILE_FLAG([-
> > fvisibility=hidden],   [VISIBILITY_CXXFLAGS="-
> > fvisibility=hidden"])
> > +AX_CHECK_COMPILE_FLAG([-Wmissing-field-
> > initializers],  [CXXFLAGS="$CXXFLAGS -Wno-missing-field-
> > initializers"])
> >  AC_LANG_POP([C++])
> >  
> >  # Flags to help ensure that certain portions of the code -- and only
> > those
> > diff --git a/meson.build b/meson.build
> > index 65ae32172d..c02b3d5c41 100644
> > --- a/meson.build
> > +++ b/meson.build
> > @@ -762,6 +762,10 @@ foreach a : ['-Wall', '-Werror=implicit-
> > function-declaration',
> >  c_args += a
> >endif
> >  endforeach
> > +if cc.has_argument('-Wmissing-field-initializers')
> > +  c_args += '-Wno-missing-field-initializers'
> > +endif
> > +
> >  c_vis_args = []
> >  if cc.has_argument('-fvisibility=hidden')
> >c_vis_args += '-fvisibility=hidden'
> > @@ -778,9 +782,12 @@ endforeach
> >  
> >  # For some reason, the test for -Wno-foo always succeeds with gcc,
> > even if the
> >  # option is not supported. Hence, check for -Wfoo instead.
> > -if cpp.has_argument('-Wnon-virtual-dtor')
> > -  cpp_args += '-Wno-non-virtual-dtor'
> > -endif
> > +
> > +foreach a : ['non-virtual-dtor', 'missing-field-initializers']
> > +  if cpp.has_argument('-W' + a)
> > +cpp_args += '-Wno-' + a
> > +  endif
> > +endforeach
> >  
> >  no_override_init_args = []
> >  foreach a : ['override-init', 'initializer-overrides']

looks good to me,

Reviewed-by: Dylan Baker 


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Re: [Mesa-dev] [PATCH] i965/gen6/gs: Handle case where a GS doesn't allocate VUE

2018-06-20 Thread andrii.simiklit 

Hello, Thanks for your feedback.


We don't implement GS before gen6, and I don't think there are plans
for it at this point, so I think we can just simplify the patch by
assuming that devinfo->gen is always going to be 6 here (later gens use
a different implementation of GS).

Got it. I will fix it as soon as we validate this idea)

Section 1.6.5.5 VUE Dereference (GS) (vol2, part1) says:

"It is possible and legal for a thread to produce no output
  or subsequently allocate a destination VUE that
  was not required*(e.g., the thread allocated ahead)*.
  *Therefore, there is a mechanism by which a thread can “give back” 
(dereference) **an allocated VUE*.  This mechanism must  be used if

  the  VUE is not written before the thread terminates.  A  kernel can
  explicitly dereference a VUE by issuing a URB_WRITE message
  (specifying the to-be-dereference handle) with the Complete
  bit set and the Used bit clear."

This is explicitly saying that COMPLETE + UNUSED is a valid
combination, and one that is in fact created for this very purpose.
Nothing in that text states that this is Pre-ILK or that this is only
for thread pre-allocated VUEs alone.
Yes I agree that it is valid combination but this is valid only for an 
allocated VUE (e.g., the thread allocated ahead). As far as I 
understand, this line explicitly saying that this combination only for 
an allocated VUEs: " Therefore, there is a mechanism by which a thread 
can 'give back' (dereference) *an allocated VUE.* "


So according to that and to following section:  Section 1.6.5.4 VUE Allocation:
 " The following description is applicable only to the GS stage.
   The threads are not passed an initial handle.
   In stead, they request a first handle (if any) via the URB
   shared function’s FF_SYNC message (see Shared Functions).
   If additional handles are required,
   the URB_WRITE allocate mechanism (mentioned above) is used."If GS doesn't allocate/request VUEs then GS shouldn't use the 
Dereference (COMPLETE + UNUSED) message. So when GS produces no output 
GS doesn't allocate VUEs at all and GS shouldn't use Dereference message.

Then in 2.4.2 Message Descriptor (vol4, part2), it says:

" Used:
   If set, this signals that the URB entry(s) referenced by
   the handle(s) are valid outputs of the thread.  In
   all likelihood this means that that entry(s) contains
   complete & valid data to be subject to further
   processing by the pipeline.
   If clear, this signals that the URB entry(s) referenced by
   the handle(s) are not valid outputs of the thread.
   Use of this setting will result in the handle(s)
   being immediately*dereferenced*  by the owning FF unit.
   This setting is to be used by GS or CLIP threads to
   dereference handles it obtained (either in the initial
   thread payload or subsequent allocation writebacks)
   but subsequently determined were not required  (e.g.,
   the object was completely clipped out)."

Again, there is no mention of this being Pre-ILK only and on top of
that, the text explicitly states that this combination is used to
deference handles obtained  either in the initial thread payload or
subsequent allocation writebacks.


So, according to section 1.6.5.5 VUE Dereference (GS) (vol2, part1)
this combination is the Dereference operation and we shouldn't use it
in case GS produces no output (see my first comment above).


And finally, it also says the following:

"Complete: (...)
Programming Notes:
The following message descriptor fields are only valid when
Complete is set:  Used"

Which I understand means that 'Used' is only applicable when Complete
is set, or in other words, that the only possible combinations where
Used is accounted for are those in which we we also have Complete set.


According to
Section 1.6.5.6 Thread Termination (vol2, part1)
 " All threads must explicitly terminate
   by executing a SEND instruction
   with the EOT bit set.  (See EU chapters).
   When a thread spawned by a 3D FF unit terminates,
   the spawning FF unit detects
   this termination as a part of Thread Management.
   This allows the FF units to manage the number of
   concurrent threads it has spawned and also manage
   the resources (e.g., scratch space) allocated to those threads.

   Programming Note:*[Pre-DevIL]*  GS and Clip threads*must terminate by 
sending a URB_WRITE message (with EOT set) with the Complete bit*  also
   set (therein returning a URB handle marked as either used or un-used). "

Only Pre-DevIL architectures must specify the Complete=1.

And finally according to all comments above we shouldn't use
the Dereference operation for the no output case and we know
that we able to set Complete=0 because the Complete=1 value is mandatory only 
for Pre-DevIL.

I hope, that I was understandable) Could you please let me know if you agree 
with me)

Regards, Andrii.


On 20.06.18 15:19, Iago Toral wrote:

On Tue, 2018-06-19 at 17:06 +0300, Andrii Simiklit wrote:

We can not use the VUE Dereference flags co

Re: [Mesa-dev] [PATCH 7/8] radeonsi: always put persistent buffers into GTT on radeon

2018-06-20 Thread Dylan Baker 
Quoting Marek Olšák (2018-06-08 20:16:54)
> From: Marek Olšák 
> 
> This improves performance for certain games.
> 
> Cc: 18.1 
> ---
>  src/gallium/drivers/radeonsi/si_buffer.c | 6 +-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/src/gallium/drivers/radeonsi/si_buffer.c 
> b/src/gallium/drivers/radeonsi/si_buffer.c
> index 2d68edc3404..0546fa9d336 100644
> --- a/src/gallium/drivers/radeonsi/si_buffer.c
> +++ b/src/gallium/drivers/radeonsi/si_buffer.c
> @@ -144,22 +144,26 @@ void si_init_resource_fields(struct si_screen *sscreen,
> if (res->b.b.target == PIPE_BUFFER &&
> res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
>   PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
> /* Use GTT for all persistent mappings with older
>  * kernels, because they didn't always flush the HDP
>  * cache before CS execution.
>  *
>  * Write-combined CPU mappings are fine, the kernel
>  * ensures all CPU writes finish before the GPU
>  * executes a command stream.
> +*
> +* radeon doesn't have good BO move throttling, so put all
> +* persistent buffers into GTT to prevent VRAM CPU page 
> faults.
>  */
> -   if (!sscreen->info.kernel_flushes_hdp_before_ib)
> +   if (!sscreen->info.kernel_flushes_hdp_before_ib ||
> +   sscreen->info.drm_major == 2)
> res->domains = RADEON_DOMAIN_GTT;
> }
>  
> /* Tiled textures are unmappable. Always put them in VRAM. */
> if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
> res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
> res->domains = RADEON_DOMAIN_VRAM;
> res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
>  RADEON_FLAG_GTT_WC;
> }
> -- 
> 2.17.1
> 
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Hi Marek,

This doesn't apply cleanly to 18.1, since
b81149e258a492ed0c81058fb535f6bfdacb36da isn't in 18.1; would you like me to
pull that commit as well, or do something else?

Dylan


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Re: [Mesa-dev] [PATCH 7/8] radeonsi: always put persistent buffers into GTT on radeon

2018-06-20 Thread Marek Olšák 
On Wed, Jun 20, 2018 at 11:26 AM, Dylan Baker  wrote:
> Quoting Marek Olšák (2018-06-08 20:16:54)
>> From: Marek Olšák 
>>
>> This improves performance for certain games.
>>
>> Cc: 18.1 
>> ---
>>  src/gallium/drivers/radeonsi/si_buffer.c | 6 +-
>>  1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/drivers/radeonsi/si_buffer.c 
>> b/src/gallium/drivers/radeonsi/si_buffer.c
>> index 2d68edc3404..0546fa9d336 100644
>> --- a/src/gallium/drivers/radeonsi/si_buffer.c
>> +++ b/src/gallium/drivers/radeonsi/si_buffer.c
>> @@ -144,22 +144,26 @@ void si_init_resource_fields(struct si_screen *sscreen,
>> if (res->b.b.target == PIPE_BUFFER &&
>> res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
>>   PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
>> /* Use GTT for all persistent mappings with older
>>  * kernels, because they didn't always flush the HDP
>>  * cache before CS execution.
>>  *
>>  * Write-combined CPU mappings are fine, the kernel
>>  * ensures all CPU writes finish before the GPU
>>  * executes a command stream.
>> +*
>> +* radeon doesn't have good BO move throttling, so put all
>> +* persistent buffers into GTT to prevent VRAM CPU page 
>> faults.
>>  */
>> -   if (!sscreen->info.kernel_flushes_hdp_before_ib)
>> +   if (!sscreen->info.kernel_flushes_hdp_before_ib ||
>> +   sscreen->info.drm_major == 2)
>> res->domains = RADEON_DOMAIN_GTT;
>> }
>>
>> /* Tiled textures are unmappable. Always put them in VRAM. */
>> if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
>> res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
>> res->domains = RADEON_DOMAIN_VRAM;
>> res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
>>  RADEON_FLAG_GTT_WC;
>> }
>> --
>> 2.17.1
>>
>> ___
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>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
> Hi Marek,
>
> This doesn't apply cleanly to 18.1, since
> b81149e258a492ed0c81058fb535f6bfdacb36da isn't in 18.1; would you like me to
> pull that commit as well, or do something else?

Yes, you can pull that commit too. Thanks!

Marek
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Re: [Mesa-dev] [PATCH 2/2] radv: set EVENT_WRITE_EOP.INT_SEL = wait for write confirmation

2018-06-20 Thread Bas Nieuwenhuizen 
Reviewed-by: Bas Nieuwenhuizen 

for the series.

On Wed, Jun 20, 2018 at 4:10 PM, Samuel Pitoiset
 wrote:
> Ported from RadeonSI.
> Not sure why this is needed but AMDVLK does something similar.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/si_cmd_buffer.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index d6b073c783..e350bccae3 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -686,11 +686,17 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf 
> *cs,
> EVENT_INDEX(5) |
> event_flags;
> unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
> +   unsigned sel = EOP_DATA_SEL(data_sel);
> +
> +   /* Wait for write confirmation before writing data, but don't send
> +* an interrupt. */
> +   if (data_sel != EOP_DATA_SEL_DISCARD)
> +   sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
>
> if (chip_class >= GFX9 || is_gfx8_mec) {
> radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, 
> predicated));
> radeon_emit(cs, op);
> -   radeon_emit(cs, EOP_DATA_SEL(data_sel));
> +   radeon_emit(cs, sel);
> radeon_emit(cs, va);/* address lo */
> radeon_emit(cs, va >> 32);  /* address hi */
> radeon_emit(cs, new_fence); /* immediate data lo */
> @@ -707,7 +713,7 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 
> predicated));
> radeon_emit(cs, op);
> radeon_emit(cs, va);
> -   radeon_emit(cs, ((va >> 32) & 0x) | 
> EOP_DATA_SEL(data_sel));
> +   radeon_emit(cs, ((va >> 32) & 0x) | sel);
> radeon_emit(cs, old_fence); /* immediate data */
> radeon_emit(cs, 0); /* unused */
> }
> @@ -715,7 +721,7 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated));
> radeon_emit(cs, op);
> radeon_emit(cs, va);
> -   radeon_emit(cs, ((va >> 32) & 0x) | 
> EOP_DATA_SEL(data_sel));
> +   radeon_emit(cs, ((va >> 32) & 0x) | sel);
> radeon_emit(cs, new_fence); /* immediate data */
> radeon_emit(cs, 0); /* unused */
> }
> --
> 2.17.1
>
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[Mesa-dev] [Bug 106976] Compilation failure due to missing xcb_randr_lease_t

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106976

--- Comment #2 from Bas Nieuwenhuizen  ---
I think this patch already on the list should also fix it?

https://patchwork.freedesktop.org/patch/230449/

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[Mesa-dev] [Bug 106910] Primus Segfaults after updating Mesa to 18.1.1

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106910

--- Comment #2 from Daniel Serpell  ---
There is a backtrace in
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=901701:


Thread 2.3 "glxgears" received signal SIGSEGV, Segmentation fault.
[Switching to Thread 0x7fffee092700 (LWP 10545)]
0x702914a7 in do_blit_drawpixels (pixels=0x0, unpack=0x7fffe0150ac8,
type=5121, format=32993, height=1080, width=1920, y=0, x=0, ctx=0x7fffe0147540)
at ../../../../../../src/mesa/drivers/dri/i965/intel_pixel_draw.c:80
80  ../../../../../../src/mesa/drivers/dri/i965/intel_pixel_draw.c: Toks
failas ar aplankas neegzistuoja.
#0  0x702914a7 in do_blit_drawpixels (pixels=0x0,
unpack=0x7fffe0150ac8, type=5121, format=32993, height=1080, width=1920, y=0,
x=0, ctx=0x7fffe0147540) at
../../../../../../src/mesa/drivers/dri/i965/intel_pixel_draw.c:80
src_offset = 
src_buffer = 
dst_format = 3761243984
src_stride = 
src_flip = 
pbo_mt = 0x0
rb = 
src_format = MESA_FORMAT_B8G8R8A8_UNORM
#1  intelDrawPixels (ctx=0x7fffe0147540, x=0, y=0, width=1920, height=1080,
format=32993, type=5121, unpack=0x7fffe0150ac8, pixels=0x0) at
../../../../../../src/mesa/drivers/dri/i965/intel_pixel_draw.c:167
__func__ = "intelDrawPixels"
#2  0x7fffefedaf33 in _mesa_DrawPixels (width=1920, height=1080,
format=32993, type=5121, pixels=0x0) at ../../../src/mesa/main/drawpix.c:162
err = 
ctx = 0x7fffe0147540
#3  0x776b8345 in test_drawpixels_fast (dconfig=,
ctx=0x7fffe00239c0, dpy=0x7fffeb20) at libglfork.cpp:362
pbo = 1
end = 8568.4529074310012
iters = 0
is_fast = 
width = 1920
height = 1080
pbattrs = {32833, 1920, 32832, 1080, 32795, 1, 0}
pbuffer = 146800642
pixeldata = 
#4  display_work (vd=) at libglfork.cpp:402
drawable = 144703490
width = 300
height = 300
quad_vertex_coords = {-1, -1, -1, 1, 1, 1, 1, -1}
quad_texture_coords = {0, 0, 0, 1, 1, 1, 1, 0}
textures = {0, 0}
pbos = {0, 0}
ctex = 0
state_names = {0x776c1244 "wait", 0x776c1249 "upload",
0x776c1250 "draw+swap", 0x0}
profiler = {name = 0x776c1203 "display", state_names =
0x778d12e0 , state_time = {0, 0, 0, 0, 0,
0}, prev_timestamp = 8568.2315354050006, print_timestamp = 8568.2315354050006,
state = 0, nframes = 0, width = 0, height = 0}
ddpy = 0x7fffeb20
__PRETTY_FUNCTION__ = "void* display_work(void*)"
dconfigs = 0x7fffe000fff0
context = 0x7fffe00239c0
use_textures = 
#5  0x762455aa in start_thread (arg=0x7fffee092700) at
pthread_create.c:463
pd = 0x7fffee092700
now = 
unwind_buf = {cancel_jmp_buf = {{jmp_buf = {140737186965248,
6747949740819525267, 140737488347470, 140737488347471, 140737488347472, 0,
-6747988065853329773, -6747970307990442349}, mask_was_saved = 0}}, priv = {pad
= {0x0, 0x0, 0x0, 0x0}, data = {prev = 0x0, cleanup = 0x0, canceltype = 0}}}
not_first_call = 
#6  0x76aebcbf in clone () at
../sysdeps/unix/sysv/linux/x86_64/clone.S:95


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Re: [Mesa-dev] [PATCH 7/8] radeonsi: always put persistent buffers into GTT on radeon

2018-06-20 Thread Dylan Baker 
Quoting Marek Olšák (2018-06-20 08:58:05)
> On Wed, Jun 20, 2018 at 11:26 AM, Dylan Baker  wrote:
> > Quoting Marek Olšák (2018-06-08 20:16:54)
> >> From: Marek Olšák 
> >>
> >> This improves performance for certain games.
> >>
> >> Cc: 18.1 
> >> ---
> >>  src/gallium/drivers/radeonsi/si_buffer.c | 6 +-
> >>  1 file changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/src/gallium/drivers/radeonsi/si_buffer.c 
> >> b/src/gallium/drivers/radeonsi/si_buffer.c
> >> index 2d68edc3404..0546fa9d336 100644
> >> --- a/src/gallium/drivers/radeonsi/si_buffer.c
> >> +++ b/src/gallium/drivers/radeonsi/si_buffer.c
> >> @@ -144,22 +144,26 @@ void si_init_resource_fields(struct si_screen 
> >> *sscreen,
> >> if (res->b.b.target == PIPE_BUFFER &&
> >> res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
> >>   PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
> >> /* Use GTT for all persistent mappings with older
> >>  * kernels, because they didn't always flush the HDP
> >>  * cache before CS execution.
> >>  *
> >>  * Write-combined CPU mappings are fine, the kernel
> >>  * ensures all CPU writes finish before the GPU
> >>  * executes a command stream.
> >> +*
> >> +* radeon doesn't have good BO move throttling, so put all
> >> +* persistent buffers into GTT to prevent VRAM CPU page 
> >> faults.
> >>  */
> >> -   if (!sscreen->info.kernel_flushes_hdp_before_ib)
> >> +   if (!sscreen->info.kernel_flushes_hdp_before_ib ||
> >> +   sscreen->info.drm_major == 2)
> >> res->domains = RADEON_DOMAIN_GTT;
> >> }
> >>
> >> /* Tiled textures are unmappable. Always put them in VRAM. */
> >> if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
> >> res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
> >> res->domains = RADEON_DOMAIN_VRAM;
> >> res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
> >>  RADEON_FLAG_GTT_WC;
> >> }
> >> --
> >> 2.17.1
> >>
> >> ___
> >> mesa-dev mailing list
> >> mesa-dev@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> >
> > Hi Marek,
> >
> > This doesn't apply cleanly to 18.1, since
> > b81149e258a492ed0c81058fb535f6bfdacb36da isn't in 18.1; would you like me to
> > pull that commit as well, or do something else?
> 
> Yes, you can pull that commit too. Thanks!
> 
> Marek

Both pulled into the 18.1-proposed branch

There was a very minor conflict in the b811 commit (git being stupid really),
which I resolved. You can look at it here:
https://cgit.freedesktop.org/~dbaker/mesa/commit/?h=18.1-proposed&id=e979b79cecb347b045c3b3eca8678c30bf450fa6.
Let me know if anything looks off.

Dylan


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Re: [Mesa-dev] [PATCH 7/8] radeonsi: always put persistent buffers into GTT on radeon

2018-06-20 Thread Marek Olšák 
It looks good. Thanks!

Marek

On Wed, Jun 20, 2018 at 12:47 PM, Dylan Baker  wrote:
> Quoting Marek Olšák (2018-06-20 08:58:05)
>> On Wed, Jun 20, 2018 at 11:26 AM, Dylan Baker  wrote:
>> > Quoting Marek Olšák (2018-06-08 20:16:54)
>> >> From: Marek Olšák 
>> >>
>> >> This improves performance for certain games.
>> >>
>> >> Cc: 18.1 
>> >> ---
>> >>  src/gallium/drivers/radeonsi/si_buffer.c | 6 +-
>> >>  1 file changed, 5 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git a/src/gallium/drivers/radeonsi/si_buffer.c 
>> >> b/src/gallium/drivers/radeonsi/si_buffer.c
>> >> index 2d68edc3404..0546fa9d336 100644
>> >> --- a/src/gallium/drivers/radeonsi/si_buffer.c
>> >> +++ b/src/gallium/drivers/radeonsi/si_buffer.c
>> >> @@ -144,22 +144,26 @@ void si_init_resource_fields(struct si_screen 
>> >> *sscreen,
>> >> if (res->b.b.target == PIPE_BUFFER &&
>> >> res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
>> >>   PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
>> >> /* Use GTT for all persistent mappings with older
>> >>  * kernels, because they didn't always flush the HDP
>> >>  * cache before CS execution.
>> >>  *
>> >>  * Write-combined CPU mappings are fine, the kernel
>> >>  * ensures all CPU writes finish before the GPU
>> >>  * executes a command stream.
>> >> +*
>> >> +* radeon doesn't have good BO move throttling, so put all
>> >> +* persistent buffers into GTT to prevent VRAM CPU page 
>> >> faults.
>> >>  */
>> >> -   if (!sscreen->info.kernel_flushes_hdp_before_ib)
>> >> +   if (!sscreen->info.kernel_flushes_hdp_before_ib ||
>> >> +   sscreen->info.drm_major == 2)
>> >> res->domains = RADEON_DOMAIN_GTT;
>> >> }
>> >>
>> >> /* Tiled textures are unmappable. Always put them in VRAM. */
>> >> if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) 
>> >> ||
>> >> res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
>> >> res->domains = RADEON_DOMAIN_VRAM;
>> >> res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
>> >>  RADEON_FLAG_GTT_WC;
>> >> }
>> >> --
>> >> 2.17.1
>> >>
>> >> ___
>> >> mesa-dev mailing list
>> >> mesa-dev@lists.freedesktop.org
>> >> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>> >
>> > Hi Marek,
>> >
>> > This doesn't apply cleanly to 18.1, since
>> > b81149e258a492ed0c81058fb535f6bfdacb36da isn't in 18.1; would you like me 
>> > to
>> > pull that commit as well, or do something else?
>>
>> Yes, you can pull that commit too. Thanks!
>>
>> Marek
>
> Both pulled into the 18.1-proposed branch
>
> There was a very minor conflict in the b811 commit (git being stupid really),
> which I resolved. You can look at it here:
> https://cgit.freedesktop.org/~dbaker/mesa/commit/?h=18.1-proposed&id=e979b79cecb347b045c3b3eca8678c30bf450fa6.
> Let me know if anything looks off.
>
> Dylan
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Re: [Mesa-dev] [PATCH v4 1/3] gallium/util: Fix build error due to cast to different size

2018-06-20 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek

On Wed, Jun 20, 2018 at 9:26 AM, Robert Foss  wrote:
> Signed-off-by: Robert Foss 
> Reviewed-by: Tomasz Figa 
> ---
> Changes since v3:
>  - Added r-b from Tomasz
>
>  src/gallium/auxiliary/util/u_debug_stack_android.cpp | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_debug_stack_android.cpp 
> b/src/gallium/auxiliary/util/u_debug_stack_android.cpp
> index b3d56aebe6..395a1fe911 100644
> --- a/src/gallium/auxiliary/util/u_debug_stack_android.cpp
> +++ b/src/gallium/auxiliary/util/u_debug_stack_android.cpp
> @@ -49,10 +49,10 @@ debug_backtrace_capture(debug_stack_frame *mesa_backtrace,
>backtrace_table = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
>  _mesa_key_pointer_equal);
>
> -   backtrace_entry = _mesa_hash_table_search(backtrace_table, (void*) tid);
> +   backtrace_entry = _mesa_hash_table_search(backtrace_table, (void*) 
> (uintptr_t)tid);
> if (!backtrace_entry) {
>backtrace = Backtrace::Create(getpid(), tid);
> -  _mesa_hash_table_insert(backtrace_table, (void*) tid, backtrace);
> +  _mesa_hash_table_insert(backtrace_table, (void*) (uintptr_t)tid, 
> backtrace);
> } else {
>backtrace = (Backtrace *) backtrace_entry->data;
> }
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 6/7] anv: add VK_EXT_display_control to anv driver [v2]

2018-06-20 Thread Jason Ekstrand 
On Tue, Jun 19, 2018 at 10:31 PM, Keith Packard  wrote:

> Jason Ekstrand  writes:
>
> >> +   if (allocator)
> >> + alloc = allocator;
> >> +   else
> >> + alloc = &device->instance->alloc;
> >>
> >
> > This is what vk_alloc2 is for. :-)
> ...
> > And vk_free2
> ...
> > This isn't needed if you're using vk_alloc2
>
> Yeah, but I need to pass the allocator down to the wsi common code, and
> that doesn't have any way to touch the device driver allocator
> pointer. I bet I'm just missing something here. Help?
>

I believe that the WSI common code should be capable of fishing the
instance allocator out of the wsi_display so we need only pass the
allocator argument unmodified through to the core WSI code.  Make sense?
Yeah, Vulkan allocator fishing is weird.

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Re: [Mesa-dev] [PATCH mesa] vulkan: EXT_acquire_xlib_display requires libXrandr headers to build

2018-06-20 Thread Eric Engestrom 
On Tuesday, 2018-06-19 16:06:14 -0700, Keith Packard wrote:
> When VK_USE_PLATFORM_XLIB_XRANDR_EXT is defined, vulkan.h includes
> X11/extensions/Xrandr.h for the RROutput typedef which is used in
> the vkGetRandROutputDisplayEXT interface.
> 
> Make sure we have the required header by checking during the build,
> and also set CFLAGS to point at the right directory.
> 
> We don't need to link against the library as we don't use any
> functions from there, so don't add the _LIBS value in the autotools
> build.
> 
> Signed-off-by: Keith Packard 

Fixes: dbac8e25f851ed44c51f "radv: Add EXT_acquire_xlib_display to radv driver 
[v2]"
Reviewed-by: Eric Engestrom 

> ---
>  configure.ac | 2 ++
>  meson.build  | 2 ++
>  src/amd/vulkan/Makefile.am   | 3 ++-
>  src/amd/vulkan/meson.build   | 2 +-
>  src/intel/Makefile.vulkan.am | 3 ++-
>  src/intel/vulkan/meson.build | 2 +-
>  src/vulkan/Makefile.am   | 2 ++
>  src/vulkan/wsi/meson.build   | 2 +-
>  8 files changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index 06524107786..e4320e8da7a 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -1877,6 +1877,8 @@ fi
>  if test x"$have_xlease" = xyes; then
>  randr_modules="x11-xcb xcb-randr"
>  PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
> +xlib_randr_modules="xrandr"
> +PKG_CHECK_MODULES([XLIB_RANDR], [$xlib_randr_modules])
>  fi
>  
>  AM_CONDITIONAL(HAVE_PLATFORM_X11, echo "$platforms" | grep -q 'x11')
> diff --git a/meson.build b/meson.build
> index ce54393fded..82279aad26c 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -1301,6 +1301,7 @@ dep_xcb_sync = null_dep
>  dep_xcb_xfixes = null_dep
>  dep_xshmfence = null_dep
>  dep_xcb_xrandr = null_dep
> +dep_xlib_xrandr = null_dep
>  if with_platform_x11
>if with_glx == 'xlib' or with_glx == 'gallium-xlib'
>  dep_x11 = dependency('x11')
> @@ -1349,6 +1350,7 @@ if with_platform_x11
>endif
>if with_xlib_lease
>  dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.12')
> +dep_xlib_xrandr = dependency('xrandr', version : '>= 1.3')
>endif
>  endif
>  
> diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
> index 8279fe4a81f..f9d3622f744 100644
> --- a/src/amd/vulkan/Makefile.am
> +++ b/src/amd/vulkan/Makefile.am
> @@ -90,7 +90,8 @@ endif
>  if HAVE_XLIB_LEASE
>  AM_CPPFLAGS += \
>   -DVK_USE_PLATFORM_XLIB_XRANDR_EXT \
> - $(XCB_RANDR_CFLAGS)
> + $(XCB_RANDR_CFLAGS) \
> + $(XLIB_RANDR_CFLAGS)
>  
>  VULKAN_LIB_DEPS += $(XCB_RANDR_LIBS)
>  endif
> diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build
> index bcdf83e0609..22857926fa1 100644
> --- a/src/amd/vulkan/meson.build
> +++ b/src/amd/vulkan/meson.build
> @@ -121,7 +121,7 @@ if with_platform_drm
>  endif
>  
>  if with_xlib_lease
> -  radv_deps += dep_xcb_xrandr
> +  radv_deps += [dep_xcb_xrandr, dep_xlib_xrandr]
>radv_flags += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
>  endif
>  
> diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
> index ae625695814..4a80c3ae412 100644
> --- a/src/intel/Makefile.vulkan.am
> +++ b/src/intel/Makefile.vulkan.am
> @@ -202,7 +202,8 @@ endif
>  if HAVE_XLIB_LEASE
>  VULKAN_CPPFLAGS += \
>   -DVK_USE_PLATFORM_XLIB_XRANDR_EXT \
> - $(XCB_RANDR_CFLAGS)
> + $(XCB_RANDR_CFLAGS) \
> + $(XLIB_RANDR_CFLAGS)
>  VULKAN_LIB_DEPS += $(XCB_RANDR_LIBS)
>  endif
>  
> diff --git a/src/intel/vulkan/meson.build b/src/intel/vulkan/meson.build
> index 4b0652f757b..e427c7471f4 100644
> --- a/src/intel/vulkan/meson.build
> +++ b/src/intel/vulkan/meson.build
> @@ -170,7 +170,7 @@ if with_platform_drm
>  endif
>  
>  if with_xlib_lease
> -  anv_deps += dep_xcb_xrandr
> +  anv_deps += [dep_xcb_xrandr, dep_xlib_xrandr]
>anv_flags += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
>  endif
>  
> diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am
> index 9deb6e18ff0..ce1a79d0c48 100644
> --- a/src/vulkan/Makefile.am
> +++ b/src/vulkan/Makefile.am
> @@ -63,6 +63,8 @@ endif
>  
>  if HAVE_XLIB_LEASE
>  AM_CPPFLAGS += \
> + $(XCB_RANDR_CFLAGS) \
> + $(XLIB_RANDR_CFLAGS) \
>   -DVK_USE_PLATFORM_XLIB_XRANDR_EXT
>  endif
>  
> diff --git a/src/vulkan/wsi/meson.build b/src/vulkan/wsi/meson.build
> index 3501a864e18..d073b23dc25 100644
> --- a/src/vulkan/wsi/meson.build
> +++ b/src/vulkan/wsi/meson.build
> @@ -68,7 +68,7 @@ if with_platform_drm
>  endif
>  
>  if with_xlib_lease
> -  vulkan_wsi_deps += dep_xcb_xrandr
> +  vulkan_wsi_deps += [dep_xcb_xrandr, dep_xlib_xrandr]
>vulkan_wsi_args += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
>  endif
>  
> -- 
> 2.17.1
> 
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[Mesa-dev] [PATCH v4 0/7] mesa/i965: Add support for INTEL_blackhole_render

2018-06-20 Thread Lionel Landwerlin 
Hi all,

This is a respin of the blackhole render extension with Haswell
disabled. After digging a bit I found out that the kernel command
parser drops our batch when it contains a write to INSTPM.
Unfortunately I have to land those patches to be able to land the
kernel ones.

Cheers,

Lionel Landwerlin (7):
  i965: add force posted register load
  i965: add a skylake only pipe control recommendation
  i965: pipecontrol: allow NULL bo for writing registers
  intel: genxml: add Force Posted field to MI_LRI
  include: bump GL/GLES headers & registry
  mesa: add INTEL_blackhole_render
  i965: enable INTEL_blackhole_render

 include/GL/glcorearb.h|   52 +-
 include/GL/glext.h|   65 +-
 include/GL/glxext.h   |   20 +-
 include/GL/wglext.h   |6 +-
 include/GLES/gl.h |   15 +-
 include/GLES/glext.h  |   33 +-
 include/GLES2/gl2.h   |6 +-
 include/GLES2/gl2ext.h|  143 +-
 include/GLES3/gl3.h   |6 +-
 src/intel/genxml/gen10.xml|1 +
 src/intel/genxml/gen11.xml|1 +
 src/intel/genxml/gen7.xml |1 +
 src/intel/genxml/gen75.xml|1 +
 src/intel/genxml/gen8.xml |1 +
 src/intel/genxml/gen9.xml |1 +
 src/mapi/glapi/registry/gl.xml| 3995 -
 src/mesa/drivers/dri/i965/brw_clear.c |3 +
 src/mesa/drivers/dri/i965/brw_context.h   |4 +
 src/mesa/drivers/dri/i965/brw_defines.h   |9 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c|   56 +
 src/mesa/drivers/dri/i965/brw_pipe_control.c  |   19 +
 src/mesa/drivers/dri/i965/brw_state.h |4 +
 src/mesa/drivers/dri/i965/brw_state_upload.c  |2 +
 src/mesa/drivers/dri/i965/genX_state_upload.c |4 +
 src/mesa/drivers/dri/i965/intel_batchbuffer.c |   13 +
 src/mesa/drivers/dri/i965/intel_extensions.c  |8 +
 src/mesa/drivers/dri/i965/intel_fbo.c |6 +
 src/mesa/drivers/dri/i965/intel_pixel_read.c  |3 +
 src/mesa/drivers/dri/i965/intel_tex_copy.c|3 +
 src/mesa/drivers/dri/i965/intel_tex_image.c   |5 +
 src/mesa/main/enable.c|   14 +
 src/mesa/main/extensions_table.h  |1 +
 src/mesa/main/mtypes.h|8 +
 33 files changed, 3213 insertions(+), 1296 deletions(-)

--
2.17.1
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[Mesa-dev] [PATCH v4 4/7] intel: genxml: add Force Posted field to MI_LRI

2018-06-20 Thread Lionel Landwerlin 
The kernel uses it. It's not recommended to use it in the batchbuffer,
but the hardware doesn't seem to complain.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/genxml/gen10.xml | 1 +
 src/intel/genxml/gen11.xml | 1 +
 src/intel/genxml/gen7.xml  | 1 +
 src/intel/genxml/gen75.xml | 1 +
 src/intel/genxml/gen8.xml  | 1 +
 src/intel/genxml/gen9.xml  | 1 +
 6 files changed, 6 insertions(+)

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 541e4405716..e5e79d2c661 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -2974,6 +2974,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index bd3800e4b79..41b5bf099d5 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -2963,6 +2963,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 6dde7973e69..e09e336d0cd 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2018,6 +2018,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 5b01fd45400..613168e6f45 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2378,6 +2378,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 4ed41d15612..c8320c6ed63 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2605,6 +2605,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 318ae89d5e7..6181b893334 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2892,6 +2892,7 @@
 
 
 
+
 
 
 
-- 
2.17.1

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[Mesa-dev] [PATCH v4 7/7] i965: enable INTEL_blackhole_render

2018-06-20 Thread Lionel Landwerlin 
v2: condition the extension on context isolation support from the
kernel (Chris)

v3: (Lionel)

The initial version of this change used a feature of the Gen7+
command parser to turn the primitive instructions into no-ops.
Unfortunately this doesn't play well with how we're using the
hardware outside of the user submitted commands. For example
resolves are implicit operations which should not be turned into
no-ops as part of the previously submitted commands (before
blackhole_render is enabled) might not be disabled. For example
this sequence :

   glClear();
   glEnable(GL_BLACKHOLE_RENDER_INTEL);
   glDrawArrays(...);
   glReadPixels(...);
   glDisable(GL_BLACKHOLE_RENDER_INTEL);

While clear has been emitted outside the blackhole render, it
should still be resolved properly in the read pixels. Hence we
need to be more selective and only disable user submitted
commands.

This v3 manually turns primitives into MI_NOOP if blackhole render
is enabled. This lets us enable this feature on any platform.

v4: Limit support to gen7.5+ (Lionel)

v5: Enable Gen7.5 support again, requires a kernel update of the
command parser (Lionel)

v6: Disable Gen7.5 again... Kernel devs want these patches landed
before they accept the kernel patches to whitelist INSTPM (Lionel)

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_clear.c |  3 +
 src/mesa/drivers/dri/i965/brw_context.h   |  2 +
 src/mesa/drivers/dri/i965/brw_defines.h   |  8 ++-
 src/mesa/drivers/dri/i965/brw_misc_state.c| 56 +++
 src/mesa/drivers/dri/i965/brw_state.h |  4 ++
 src/mesa/drivers/dri/i965/brw_state_upload.c  |  2 +
 src/mesa/drivers/dri/i965/genX_state_upload.c |  4 ++
 src/mesa/drivers/dri/i965/intel_extensions.c  |  8 +++
 src/mesa/drivers/dri/i965/intel_fbo.c |  6 ++
 src/mesa/drivers/dri/i965/intel_pixel_read.c  |  3 +
 src/mesa/drivers/dri/i965/intel_tex_copy.c|  3 +
 src/mesa/drivers/dri/i965/intel_tex_image.c   |  5 ++
 12 files changed, 103 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index b097dfe346c..d3e360b3e23 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -247,6 +247,9 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
if (!_mesa_check_conditional_render(ctx))
   return;
 
+   if (ctx->IntelBlackholeRender)
+  return;
+
if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
   brw->front_buffer_dirty = true;
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 0880d18b6f0..23602df2138 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -218,6 +218,7 @@ enum brw_state_id {
BRW_STATE_CONSERVATIVE_RASTERIZATION,
BRW_STATE_DRAW_CALL,
BRW_STATE_AUX,
+   BRW_STATE_CS_NOOP,
BRW_NUM_STATE_BITS
 };
 
@@ -309,6 +310,7 @@ enum brw_state_id {
 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << 
BRW_STATE_CONSERVATIVE_RASTERIZATION)
 #define BRW_NEW_DRAW_CALL   (1ull << BRW_STATE_DRAW_CALL)
 #define BRW_NEW_AUX_STATE   (1ull << BRW_STATE_AUX)
+#define BRW_NEW_CS_NOOP (1ull << BRW_STATE_CS_NOOP)
 
 struct brw_state_flags {
/** State update flags signalled by mesa internals */
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 320426d6944..4e2d6acc706 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1651,11 +1651,17 @@ enum brw_pixel_shader_coverage_mask_mode {
 #define GEN10_CACHE_MODE_SS0x0e420
 #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
 
-#define INSTPM 0x20c0
+#define INSTPM 0x20c0 /* Gen6-8 */
 # define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6)
+# define INSTPM_GLOBAL_DEBUG_ENABLE(1 << 4)
+# define INSTPM_MEDIA_INSTRUCTION_DISABLE  (1 << 3)
+# define INSTPM_3D_RENDERER_INSTRUCTION_DISABLE(1 << 2)
+# define INSTPM_3D_STATE_INSTRUCTION_DISABLE   (1 << 1)
 
 #define CS_DEBUG_MODE2 0x20d8 /* Gen9+ */
 # define CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 4)
+# define CSDBG2_MEDIA_INSTRUCTION_DISABLE  (1 << 1)
+# define CSDBG2_3D_RENDERER_INSTRUCTION_DISABLE(1 << 0)
 
 #define GEN7_RPSTAT1   0xA01C
 #define  GEN7_RPSTAT1_CURR_GT_FREQ_SHIFT   7
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 9a663b1d61c..baf64757b93 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -811,3 +811,59 @@ brw_upload_state_base_address(struct brw_context *brw)
brw->ctx.

[Mesa-dev] [PATCH v4 6/7] mesa: add INTEL_blackhole_render

2018-06-20 Thread Lionel Landwerlin 
v2: Implement missing Enable/Disable (Emil)

v3: Drop unused NewIntelBlackholeRender (Ken)

v4: Bring back NewIntelBlackholeRender as i965 implementation uses it
again (Lionel)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Kenneth Graunke 
---
 src/mesa/main/enable.c   | 14 ++
 src/mesa/main/extensions_table.h |  1 +
 src/mesa/main/mtypes.h   |  8 
 3 files changed, 23 insertions(+)

diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index d1b2f3a9625..7b482bdf5db 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -1137,6 +1137,16 @@ _mesa_set_enable(struct gl_context *ctx, GLenum cap, 
GLboolean state)
  ctx->Color.BlendCoherent = state;
  break;
 
+  case GL_BLACKHOLE_RENDER_INTEL:
+ if (!_mesa_has_INTEL_blackhole_render(ctx))
+goto invalid_enum_error;
+ if (ctx->IntelBlackholeRender == state)
+return;
+ FLUSH_VERTICES(ctx, 0);
+ ctx->NewDriverState |= ctx->DriverFlags.NewIntelBlackholeRender;
+ ctx->IntelBlackholeRender = state;
+ break;
+
   default:
  goto invalid_enum_error;
}
@@ -1776,6 +1786,10 @@ _mesa_IsEnabled( GLenum cap )
  CHECK_EXTENSION(MESA_tile_raster_order);
  return ctx->TileRasterOrderIncreasingY;
 
+  case GL_BLACKHOLE_RENDER_INTEL:
+ CHECK_EXTENSION(INTEL_blackhole_render);
+ return ctx->IntelBlackholeRender;
+
   default:
  goto invalid_enum_error;
}
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 1c55df8a228..cb41aa8be4a 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -309,6 +309,7 @@ EXT(IBM_texture_mirrored_repeat , dummy_true
 
 EXT(INGR_blend_func_separate, EXT_blend_func_separate  
  , GLL,  x ,  x ,  x , 1999)
 
+EXT(INTEL_blackhole_render  , INTEL_blackhole_render   
  ,  30,  30,  x , ES2, 2018)
 EXT(INTEL_conservative_rasterization, INTEL_conservative_rasterization 
  ,  x , GLC,  x ,  31, 2013)
 EXT(INTEL_performance_query , INTEL_performance_query  
  , GLL, GLC,  x , ES2, 2013)
 
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 220751ba7bb..605b4973f13 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -4240,6 +4240,7 @@ struct gl_extensions
GLboolean ATI_fragment_shader;
GLboolean ATI_separate_stencil;
GLboolean GREMEDY_string_marker;
+   GLboolean INTEL_blackhole_render;
GLboolean INTEL_conservative_rasterization;
GLboolean INTEL_performance_query;
GLboolean KHR_blend_equation_advanced;
@@ -4585,6 +4586,11 @@ struct gl_driver_flags
 
/** Programmable sample location state for gl_context::DrawBuffer */
uint64_t NewSampleLocations;
+
+   /**
+* gl_context::IntelBlackholeRender
+*/
+   uint64_t NewIntelBlackholeRender;
 };
 
 struct gl_buffer_binding
@@ -5006,6 +5012,8 @@ struct gl_context
GLfloat ConservativeRasterDilate;
GLenum16 ConservativeRasterMode;
 
+   GLboolean IntelBlackholeRender; /**< GL_INTEL_blackhole_render */
+
/** Does glVertexAttrib(0) alias glVertex()? */
bool _AttribZeroAliasesVertex;
 
-- 
2.17.1

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[Mesa-dev] [PATCH v4 1/7] i965: add force posted register load

2018-06-20 Thread Lionel Landwerlin 
Inspired by what is already in the kernel.

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_context.h   |  2 ++
 src/mesa/drivers/dri/i965/brw_defines.h   |  1 +
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 13 +
 3 files changed, 16 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 2613b9fda22..0880d18b6f0 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1410,6 +1410,8 @@ void brw_store_register_mem64(struct brw_context *brw,
   struct brw_bo *bo, uint32_t reg, uint32_t 
offset);
 void brw_load_register_imm32(struct brw_context *brw,
  uint32_t reg, uint32_t imm);
+void brw_load_register_imm32_force_posted(struct brw_context *brw,
+  uint32_t reg, uint32_t imm);
 void brw_load_register_imm64(struct brw_context *brw,
  uint32_t reg, uint64_t imm);
 void brw_load_register_reg(struct brw_context *brw, uint32_t src,
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 855f1c7d744..320426d6944 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1428,6 +1428,7 @@ enum brw_pixel_shader_coverage_mask_mode {
 
 #define MI_STORE_DATA_IMM  (CMD_MI | (0x20 << 23))
 #define MI_LOAD_REGISTER_IMM   (CMD_MI | (0x22 << 23))
+#define  MI_LOAD_REGISTER_IMM_FORCE_POSTED  (1 << 12)
 #define MI_LOAD_REGISTER_REG   (CMD_MI | (0x2A << 23))
 
 #define MI_FLUSH_DW(CMD_MI | (0x26 << 23))
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index df999ffeb1d..250a8e812e5 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -1192,6 +1192,19 @@ brw_load_register_imm32(struct brw_context *brw, 
uint32_t reg, uint32_t imm)
ADVANCE_BATCH();
 }
 
+void
+brw_load_register_imm32_force_posted(struct brw_context *brw, uint32_t reg, 
uint32_t imm)
+{
+   assert(brw->screen->devinfo.gen >= 6);
+
+   BEGIN_BATCH(3);
+   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2) |
+ MI_LOAD_REGISTER_IMM_FORCE_POSTED);
+   OUT_BATCH(reg);
+   OUT_BATCH(imm);
+   ADVANCE_BATCH();
+}
+
 /*
  * Write a 64-bit register using immediate data.
  */
-- 
2.17.1

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[Mesa-dev] [PATCH v4 2/7] i965: add a skylake only pipe control recommendation

2018-06-20 Thread Lionel Landwerlin 
Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_pipe_control.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 122ac260703..1b89e55c396 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -158,6 +158,19 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t 
flags,
  }
   }
 
+  /* Project: SKL
+   *
+   * "PIPECONTROL command with “Command Streamer Stall Enable” must be
+   * programmed prior to programming a PIPECONTROL command with LRI Post
+   * Sync Operation in GPGPU mode of operation (i.e when PIPELINE_SELECT
+   * command is set to GPGPU mode of operation)."
+   */
+  if (devinfo->is_skylake &&
+  brw->last_pipeline == BRW_COMPUTE_PIPELINE &&
+  (flags & PIPE_CONTROL_LRI_WRITE_IMMEDIATE)) {
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
+  }
+
   if (devinfo->gen == 10)
  gen10_add_rcpfe_workaround_bits(&flags);
 
-- 
2.17.1

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[Mesa-dev] [PATCH v4 3/7] i965: pipecontrol: allow NULL bo for writing registers

2018-06-20 Thread Lionel Landwerlin 
When doing a LRI Post Sync operation, you can put the register offset
in the lower 32bits of the address but won't need a BO.

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_pipe_control.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 1b89e55c396..874e9f0a9e8 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -179,6 +179,9 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t 
flags,
   OUT_BATCH(flags);
   if (bo) {
  OUT_RELOC64(bo, RELOC_WRITE, offset);
+  } else if ((flags & PIPE_CONTROL_LRI_WRITE_IMMEDIATE) != 0) {
+ OUT_BATCH(offset);
+ OUT_BATCH(0);
   } else {
  OUT_BATCH(0);
  OUT_BATCH(0);
@@ -210,6 +213,9 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t 
flags,
   OUT_BATCH(flags);
   if (bo) {
  OUT_RELOC(bo, RELOC_WRITE | RELOC_NEEDS_GGTT, gen6_gtt | offset);
+  } else if (devinfo->gen >= 7 &&
+ (flags & PIPE_CONTROL_LRI_WRITE_IMMEDIATE) != 0) {
+ OUT_BATCH(offset);
   } else {
  OUT_BATCH(0);
   }
-- 
2.17.1

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Re: [Mesa-dev] [PATCH mesa] vulkan: EXT_acquire_xlib_display requires libXrandr headers to build

2018-06-20 Thread Keith Packard 
Eric Engestrom  writes:

> On Tuesday, 2018-06-19 16:06:14 -0700, Keith Packard wrote:
>> When VK_USE_PLATFORM_XLIB_XRANDR_EXT is defined, vulkan.h includes
>> X11/extensions/Xrandr.h for the RROutput typedef which is used in
>> the vkGetRandROutputDisplayEXT interface.
>> 
>> Make sure we have the required header by checking during the build,
>> and also set CFLAGS to point at the right directory.
>> 
>> We don't need to link against the library as we don't use any
>> functions from there, so don't add the _LIBS value in the autotools
>> build.
>> 
>> Signed-off-by: Keith Packard 
>
> Fixes: dbac8e25f851ed44c51f "radv: Add EXT_acquire_xlib_display to radv 
> driver [v2]"
> Reviewed-by: Eric Engestrom 

Thanks for testing. I've pushed this to master.

-- 
-keith


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[Mesa-dev] [Bug 106976] Compilation failure due to missing xcb_randr_lease_t

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106976

--- Comment #3 from Danylo  ---
https://patchwork.freedesktop.org/patch/230449/ fixes meson build and only adds
dependency on xrandr to autoconf. Meanwhile I fixed autoconf build.

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Re: [Mesa-dev] [PATCH v2 06/16] intel: aubinator: handle GGTT mappings

2018-06-20 Thread Rafael Antognolli 
On Tue, Jun 19, 2018 at 02:45:21PM +0100, Lionel Landwerlin wrote:
> We use memfd to store physical pages as they get read/written to and
> the GGTT entries translating virtual address to physical pages.
> 
> Based on a commit by Scott Phillips.
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/tools/aubinator.c | 256 ++--
>  1 file changed, 243 insertions(+), 13 deletions(-)
> 
> diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
> index f70038376be..962546d360c 100644
> --- a/src/intel/tools/aubinator.c
> +++ b/src/intel/tools/aubinator.c
> @@ -39,12 +39,23 @@
>  
>  #include "util/list.h"
>  #include "util/macros.h"
> +#include "util/rb_tree.h"
>  
>  #include "common/gen_decoder.h"
>  #include "common/gen_disasm.h"
>  #include "common/gen_gem.h"
>  #include "intel_aub.h"
>  
> +#ifndef HAVE_MEMFD_CREATE
> +#include 
> +
> +static inline int
> +memfd_create(const char *name, unsigned int flags)
> +{
> +   return syscall(SYS_memfd_create, name, flags);
> +}
> +#endif
> +
>  /* Below is the only command missing from intel_aub.h in libdrm
>   * So, reuse intel_aub.h from libdrm and #define the
>   * AUB_MI_BATCH_BUFFER_END as below
> @@ -73,9 +84,27 @@ struct gen_batch_decode_ctx batch_ctx;
>  struct bo_map {
> struct list_head link;
> struct gen_batch_decode_bo bo;
> +   bool unmap_after_use;
> +};
> +
> +struct ggtt_entry {
> +   struct rb_node node;
> +   uint64_t virt_addr;
> +   uint64_t phys_addr;
> +};
> +
> +struct phys_mem {
> +   struct rb_node node;
> +   uint64_t fd_offset;
> +   uint64_t phys_addr;
> +   uint8_t *data;
>  };
>  
>  static struct list_head maps;
> +static struct rb_tree ggtt = {NULL};
> +static struct rb_tree mem = {NULL};
> +int mem_fd = -1;
> +off_t mem_fd_len = 0;
>  
>  FILE *outfile;
>  
> @@ -92,11 +121,12 @@ field(uint32_t value, int start, int end)
>  struct brw_instruction;
>  
>  static void
> -add_gtt_bo_map(struct gen_batch_decode_bo bo)
> +add_gtt_bo_map(struct gen_batch_decode_bo bo, bool unmap_after_use)
>  {
> struct bo_map *m = calloc(1, sizeof(*m));
>  
> m->bo = bo;
> +   m->unmap_after_use = unmap_after_use;
> list_add(&m->link, &maps);
>  }
>  
> @@ -104,21 +134,208 @@ static void
>  clear_bo_maps(void)
>  {
> list_for_each_entry_safe(struct bo_map, i, &maps, link) {
> +  if (i->unmap_after_use)
> + munmap((void *)i->bo.map, i->bo.size);
>list_del(&i->link);
>free(i);
> }
>  }
>  
> +static inline struct ggtt_entry *
> +ggtt_entry_next(struct ggtt_entry *entry)
> +{
> +   if (!entry)
> +  return NULL;
> +   struct rb_node *node = rb_node_next(&entry->node);
> +   if (!node)
> +  return NULL;
> +   return rb_node_data(struct ggtt_entry, node, node);
> +}
> +
> +static inline int
> +cmp_uint64(uint64_t a, uint64_t b)
> +{
> +   if (a < b)
> +  return -1;
> +   if (a > b)
> +  return 1;
> +   return 0;
> +}
> +
> +static inline int
> +cmp_ggtt_entry(const struct rb_node *node, const void *addr)
> +{
> +   struct ggtt_entry *entry = rb_node_data(struct ggtt_entry, node, node);
> +   return cmp_uint64(entry->virt_addr, *(uint64_t *)addr);
> +}
> +
> +static struct ggtt_entry *
> +ensure_ggtt_entry(struct rb_tree *tree, uint64_t virt_addr)
> +{
> +   struct rb_node *node = rb_tree_search_sloppy(&ggtt, &virt_addr,
> +cmp_ggtt_entry);
> +   int cmp = 0;
> +   if (!node || (cmp = cmp_ggtt_entry(node, &virt_addr))) {
> +  struct ggtt_entry *new_entry = calloc(1, sizeof(*new_entry));
> +  new_entry->virt_addr = virt_addr;
> +  rb_tree_insert_at(&ggtt, node, &new_entry->node, cmp > 0);
> +  node = &new_entry->node;
> +   }
> +
> +   return rb_node_data(struct ggtt_entry, node, node);
> +}
> +
> +static struct ggtt_entry *
> +search_ggtt_entry(uint64_t virt_addr)
> +{
> +   virt_addr &= ~0xfff;
> +
> +   struct rb_node *node = rb_tree_search(&ggtt, &virt_addr, cmp_ggtt_entry);
> +
> +   if (!node)
> +  return NULL;
> +
> +   return rb_node_data(struct ggtt_entry, node, node);
> +}
> +
> +static inline int
> +cmp_phys_mem(const struct rb_node *node, const void *addr)
> +{
> +   struct phys_mem *mem = rb_node_data(struct phys_mem, node, node);
> +   return cmp_uint64(mem->phys_addr, *(uint64_t *)addr);
> +}
> +
> +static struct phys_mem *
> +ensure_phys_mem(uint64_t phys_addr)
> +{
> +   struct rb_node *node = rb_tree_search_sloppy(&mem, &phys_addr, 
> cmp_phys_mem);
> +   int cmp = 0;
> +   if (!node || (cmp = cmp_phys_mem(node, &phys_addr))) {
> +  struct phys_mem *new_mem = calloc(1, sizeof(*new_mem));
> +  new_mem->phys_addr = phys_addr;
> +  new_mem->fd_offset = mem_fd_len;
> +
> +  int ftruncate_res = ftruncate(mem_fd, mem_fd_len += 4096);
> +  assert(ftruncate_res == 0);
> +
> +  new_mem->data = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED,
> +   mem_fd, new_mem->fd_offset);
> +  assert(new_mem->data != MAP_FAI

Re: [Mesa-dev] [PATCH v2 07/16] intel/tools/aubinator: aubinate ppgtt aubs

2018-06-20 Thread Rafael Antognolli 
On Wed, Jun 20, 2018 at 11:03:32AM +0100, Lionel Landwerlin wrote:
> On 20/06/18 01:00, Rafael Antognolli wrote:
> > On Tue, Jun 19, 2018 at 02:45:22PM +0100, Lionel Landwerlin wrote:
> > > From: Scott D Phillips 
> > > 
> > > v2: by Lionel
> > >  Fix memfd_create compilation issue

I guess this memfd_create was supposed to be on patch 05, right?

With this and the extra memfd_create() removed, this patch is

Reviewed-by: Rafael Antognolli 

> > >  Fix pml4 address stored on 32 instead of 64bits
> > >  Return no buffer if first ppgtt page is not mapped
> > > 
> > > Signed-off-by: Lionel Landwerlin 
> > > ---
> > >   src/intel/tools/aubinator.c | 76 -
> > >   1 file changed, 75 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
> > > index 962546d360c..3368ac521bd 100644
> > > --- a/src/intel/tools/aubinator.c
> > > +++ b/src/intel/tools/aubinator.c
> > > @@ -336,6 +336,68 @@ get_ggtt_batch_bo(void *user_data, uint64_t address)
> > >  return bo;
> > >   }
> > > +
> > > +static struct phys_mem *
> > > +ppgtt_walk(uint64_t pml4, uint64_t address)
> > > +{
> > > +   uint64_t shift = 39;
> > > +   uint64_t addr = pml4;
> > > +   for (int level = 4; level > 0; level--) {
> > > +  struct phys_mem *table = search_phys_mem(addr);
> > > +  if (!table)
> > > + return NULL;
> > > +  int index = (address >> shift) & 0x1ff;
> > > +  uint64_t entry = ((uint64_t *)table->data)[index];
> > > +  if (!(entry & 1))
> > > + return NULL;
> > > +  addr = entry & ~0xfff;
> > > +  shift -= 9;
> > > +   }
> > > +   return search_phys_mem(addr);
> > > +}
> > > +
> > > +static bool
> > > +ppgtt_mapped(uint64_t pml4, uint64_t address)
> > > +{
> > > +   return ppgtt_walk(pml4, address) != NULL;
> > > +}
> > > +
> > > +static struct gen_batch_decode_bo
> > > +get_ppgtt_batch_bo(void *user_data, uint64_t address)
> > > +{
> > > +   struct gen_batch_decode_bo bo = {0};
> > > +   uint64_t pml4 = *(uint64_t *)user_data;
> > > +
> > > +   address &= ~0xfff;
> > > +
> > > +   if (!ppgtt_mapped(pml4, address))
> > > +  return bo;
> > > +
> > > +   /* Map everything until the first gap since we don't know how much the
> > > +* decoder actually needs.
> > > +*/
> > > +   uint64_t end = address;
> > > +   while (ppgtt_mapped(pml4, end))
> > > +  end += 4096;
> > > +
> > > +   bo.addr = address;
> > > +   bo.size = end - address;
> > > +   bo.map = mmap(NULL, bo.size, PROT_READ, MAP_SHARED | MAP_ANONYMOUS, 
> > > -1, 0);
> > > +   assert(bo.map != MAP_FAILED);
> > > +
> > > +   for (uint64_t page = address; page < end; page += 4096) {
> > > +  struct phys_mem *phys_mem = ppgtt_walk(pml4, page);
> > > +
> > > +  void *res = mmap((uint8_t *)bo.map + (page - bo.addr), 4096, 
> > > PROT_READ,
> > > +   MAP_SHARED | MAP_FIXED, mem_fd, 
> > > phys_mem->fd_offset);
> > > +  assert(res != MAP_FAILED);
> > > +   }
> > > +
> > > +   add_gtt_bo_map(bo, true);
> > > +
> > > +   return bo;
> > > +}
> > > +
> > >   #define GEN_ENGINE_RENDER 1
> > >   #define GEN_ENGINE_BLITTER 2
> > > @@ -377,6 +439,7 @@ handle_trace_block(uint32_t *p)
> > > }
> > > (void)engine; /* TODO */
> > > +  batch_ctx.get_bo = get_ggtt_batch_bo;
> > > gen_print_batch(&batch_ctx, bo.map, bo.size, 0);
> > > clear_bo_maps();
> > > @@ -402,7 +465,7 @@ aubinator_init(uint16_t aub_pci_id, const char 
> > > *app_name)
> > >  batch_flags |= GEN_BATCH_DECODE_FLOATS;
> > >  gen_batch_decode_ctx_init(&batch_ctx, &devinfo, outfile, batch_flags,
> > > - xml_path, get_ggtt_batch_bo, NULL, NULL);
> > > + xml_path, NULL, NULL, NULL);
> > >  batch_ctx.max_vbo_decoded_lines = max_vbo_lines;
> > >  char *color = GREEN_HEADER, *reset_color = NORMAL;
> > > @@ -542,12 +605,20 @@ handle_memtrace_reg_write(uint32_t *p)
> > >  uint32_t ring_buffer_head = context[5];
> > >  uint32_t ring_buffer_tail = context[7];
> > >  uint32_t ring_buffer_start = context[9];
> > > +   uint64_t pml4 = (uint64_t)context[49] << 32 | context[51];
> > >  struct gen_batch_decode_bo ring_bo = get_ggtt_batch_bo(NULL,
> > > 
> > > ring_buffer_start);
> > >  assert(ring_bo.size > 0);
> > >  void *commands = (uint8_t *)ring_bo.map + (ring_bo.addr - 
> > > ring_buffer_start);
> > > +   if (context_descriptor & 0x100 /* ppgtt */) {
> > > +  batch_ctx.get_bo = get_ppgtt_batch_bo;
> > > +  batch_ctx.user_data = &pml4;
> > > +   } else {
> > > +  batch_ctx.get_bo = get_ggtt_batch_bo;
> > > +   }
> > > +
> > >  (void)engine; /* TODO */
> > >  gen_print_batch(&batch_ctx, commands, ring_buffer_tail - 
> > > ring_buffer_head,
> > >  0);
> > > @@ -849,6 +920,9 @@ int main(int argc, char *argv[])
> > >  list_inith

Re: [Mesa-dev] [PATCH v2 07/16] intel/tools/aubinator: aubinate ppgtt aubs

2018-06-20 Thread Rafael Antognolli 
On Wed, Jun 20, 2018 at 12:01:28PM -0700, Rafael Antognolli wrote:
> On Wed, Jun 20, 2018 at 11:03:32AM +0100, Lionel Landwerlin wrote:
> > On 20/06/18 01:00, Rafael Antognolli wrote:
> > > On Tue, Jun 19, 2018 at 02:45:22PM +0100, Lionel Landwerlin wrote:
> > > > From: Scott D Phillips 
> > > > 
> > > > v2: by Lionel
> > > >  Fix memfd_create compilation issue
> 
> I guess this memfd_create was supposed to be on patch 05, right?

Oops, I meant patch 06 :P

> 
> With this and the extra memfd_create() removed, this patch is
> 
> Reviewed-by: Rafael Antognolli 
> 
> > > >  Fix pml4 address stored on 32 instead of 64bits
> > > >  Return no buffer if first ppgtt page is not mapped
> > > > 
> > > > Signed-off-by: Lionel Landwerlin 
> > > > ---
> > > >   src/intel/tools/aubinator.c | 76 -
> > > >   1 file changed, 75 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
> > > > index 962546d360c..3368ac521bd 100644
> > > > --- a/src/intel/tools/aubinator.c
> > > > +++ b/src/intel/tools/aubinator.c
> > > > @@ -336,6 +336,68 @@ get_ggtt_batch_bo(void *user_data, uint64_t 
> > > > address)
> > > >  return bo;
> > > >   }
> > > > +
> > > > +static struct phys_mem *
> > > > +ppgtt_walk(uint64_t pml4, uint64_t address)
> > > > +{
> > > > +   uint64_t shift = 39;
> > > > +   uint64_t addr = pml4;
> > > > +   for (int level = 4; level > 0; level--) {
> > > > +  struct phys_mem *table = search_phys_mem(addr);
> > > > +  if (!table)
> > > > + return NULL;
> > > > +  int index = (address >> shift) & 0x1ff;
> > > > +  uint64_t entry = ((uint64_t *)table->data)[index];
> > > > +  if (!(entry & 1))
> > > > + return NULL;
> > > > +  addr = entry & ~0xfff;
> > > > +  shift -= 9;
> > > > +   }
> > > > +   return search_phys_mem(addr);
> > > > +}
> > > > +
> > > > +static bool
> > > > +ppgtt_mapped(uint64_t pml4, uint64_t address)
> > > > +{
> > > > +   return ppgtt_walk(pml4, address) != NULL;
> > > > +}
> > > > +
> > > > +static struct gen_batch_decode_bo
> > > > +get_ppgtt_batch_bo(void *user_data, uint64_t address)
> > > > +{
> > > > +   struct gen_batch_decode_bo bo = {0};
> > > > +   uint64_t pml4 = *(uint64_t *)user_data;
> > > > +
> > > > +   address &= ~0xfff;
> > > > +
> > > > +   if (!ppgtt_mapped(pml4, address))
> > > > +  return bo;
> > > > +
> > > > +   /* Map everything until the first gap since we don't know how much 
> > > > the
> > > > +* decoder actually needs.
> > > > +*/
> > > > +   uint64_t end = address;
> > > > +   while (ppgtt_mapped(pml4, end))
> > > > +  end += 4096;
> > > > +
> > > > +   bo.addr = address;
> > > > +   bo.size = end - address;
> > > > +   bo.map = mmap(NULL, bo.size, PROT_READ, MAP_SHARED | MAP_ANONYMOUS, 
> > > > -1, 0);
> > > > +   assert(bo.map != MAP_FAILED);
> > > > +
> > > > +   for (uint64_t page = address; page < end; page += 4096) {
> > > > +  struct phys_mem *phys_mem = ppgtt_walk(pml4, page);
> > > > +
> > > > +  void *res = mmap((uint8_t *)bo.map + (page - bo.addr), 4096, 
> > > > PROT_READ,
> > > > +   MAP_SHARED | MAP_FIXED, mem_fd, 
> > > > phys_mem->fd_offset);
> > > > +  assert(res != MAP_FAILED);
> > > > +   }
> > > > +
> > > > +   add_gtt_bo_map(bo, true);
> > > > +
> > > > +   return bo;
> > > > +}
> > > > +
> > > >   #define GEN_ENGINE_RENDER 1
> > > >   #define GEN_ENGINE_BLITTER 2
> > > > @@ -377,6 +439,7 @@ handle_trace_block(uint32_t *p)
> > > > }
> > > > (void)engine; /* TODO */
> > > > +  batch_ctx.get_bo = get_ggtt_batch_bo;
> > > > gen_print_batch(&batch_ctx, bo.map, bo.size, 0);
> > > > clear_bo_maps();
> > > > @@ -402,7 +465,7 @@ aubinator_init(uint16_t aub_pci_id, const char 
> > > > *app_name)
> > > >  batch_flags |= GEN_BATCH_DECODE_FLOATS;
> > > >  gen_batch_decode_ctx_init(&batch_ctx, &devinfo, outfile, 
> > > > batch_flags,
> > > > - xml_path, get_ggtt_batch_bo, NULL, NULL);
> > > > + xml_path, NULL, NULL, NULL);
> > > >  batch_ctx.max_vbo_decoded_lines = max_vbo_lines;
> > > >  char *color = GREEN_HEADER, *reset_color = NORMAL;
> > > > @@ -542,12 +605,20 @@ handle_memtrace_reg_write(uint32_t *p)
> > > >  uint32_t ring_buffer_head = context[5];
> > > >  uint32_t ring_buffer_tail = context[7];
> > > >  uint32_t ring_buffer_start = context[9];
> > > > +   uint64_t pml4 = (uint64_t)context[49] << 32 | context[51];
> > > >  struct gen_batch_decode_bo ring_bo = get_ggtt_batch_bo(NULL,
> > > > 
> > > > ring_buffer_start);
> > > >  assert(ring_bo.size > 0);
> > > >  void *commands = (uint8_t *)ring_bo.map + (ring_bo.addr - 
> > > > ring_buffer_start);
> > > > +   if (context_descriptor & 0x100 /* ppgtt */) {
> > > > +  batch_ctx.get_bo = get_ppgtt_batch_bo;
> >

[Mesa-dev] [PATCH] radeonsi: use shifts for sign extension

2018-06-20 Thread Grazvydas Ignotas 
Avoids a branch and reduces code size a tiny bit:
text   data bss  dechex filename
10804563 398653 2070368 13273584 ca89f0 /tmp/radeonsi_dri.so.old
10804499 398653 2070368 13273520 ca89b0 /tmp/radeonsi_dri.so
---
 src/gallium/drivers/radeonsi/si_descriptors.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 57a3124..f368ea6 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -98,12 +98,12 @@ static uint64_t si_desc_extract_buffer_address(const 
uint32_t *desc)
 {
uint64_t va = desc[0] |
  ((uint64_t)G_008F04_BASE_ADDRESS_HI(desc[1]) << 32);
 
/* Sign-extend the 48-bit address. */
-   if (va & (1ull << 47))
-   va |= 0xull << 48;
+   va <<= 16;
+   va = (int64_t)va >> 16;
return va;
 }
 
 static void si_init_descriptor_list(uint32_t *desc_list,
unsigned element_dw_size,
-- 
2.7.4

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[Mesa-dev] [PATCH] radeonsi: add a debug flag to zero vram allocations

2018-06-20 Thread Grazvydas Ignotas 
This allows to avoid having to see garbage in Dying Light loading screen
at least, which probably expects Windows/NV behavior of all allocations
being zeroed by default.

Analogous to radv flag with the same name.
---
 src/gallium/drivers/radeonsi/si_pipe.c| 1 +
 src/gallium/drivers/radeonsi/si_pipe.h| 1 +
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 3 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 1 +
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 1 +
 5 files changed, 7 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index cc871b1..1c3405f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -80,10 +80,11 @@ static const struct debug_named_value debug_options[] = {
{ "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations 
when possible." },
{ "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
{ "nowc", DBG(NO_WC), "Disable GTT write combining" },
{ "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
{ "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per 
context." },
+   { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
 
/* 3D engine options: */
{ "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on 
end-of-packet." },
{ "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order 
rasterization" },
{ "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index eb0c226..60dc8b0 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -139,10 +139,11 @@ enum {
DBG_FORCE_DMA,
DBG_NO_ASYNC_DMA,
DBG_NO_WC,
DBG_CHECK_VM,
DBG_RESERVE_VMID,
+   DBG_ZERO_VRAM,
 
/* 3D engine options: */
DBG_SWITCH_ON_EOP,
DBG_NO_OUT_OF_ORDER,
DBG_NO_DPBB,
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index df8b829..15916ad 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -426,10 +426,13 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
amdgpu_winsys *ws,
if (flags & RADEON_FLAG_GTT_WC)
   request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
ws->info.has_local_buffers)
   request.flags |= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID;
+   if (ws->zero_all_vram_allocs &&
+   (request.preferred_heap & AMDGPU_GEM_DOMAIN_VRAM))
+  request.flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
 
r = amdgpu_bo_alloc(ws->dev, &request, &buf_handle);
if (r) {
   fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
   fprintf(stderr, "amdgpu:size  : %"PRIu64" bytes\n", size);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index caa7991..44429e2 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -60,10 +60,11 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
}
 
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != 
NULL;
ws->debug_all_bos = debug_get_option_all_bos();
ws->reserve_vmid = strstr(debug_get_option("R600_DEBUG", ""), 
"reserve_vmid") != NULL;
+   ws->zero_all_vram_allocs = strstr(debug_get_option("R600_DEBUG", ""), 
"zerovram") != NULL;
 
return true;
 
 fail:
amdgpu_device_deinitialize(ws->dev);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index a6784e8..8079255 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -77,10 +77,11 @@ struct amdgpu_winsys {
ADDR_HANDLE addrlib;
 
bool check_vm;
bool debug_all_bos;
bool reserve_vmid;
+   bool zero_all_vram_allocs;
 
/* List of all allocated buffers */
simple_mtx_t global_bo_list_lock;
struct list_head global_bo_list;
unsigned num_buffers;
-- 
2.7.4

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[Mesa-dev] [Bug 105699] s3tc fbo-generatemipmap-formats tests fail unless optimized

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=105699

--- Comment #3 from Nanley Chery  ---
Is this still an issue? I'm not able to reproduce this on my SKL.

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Re: [Mesa-dev] [PATCH] swr: bump minimum supported LLVM version to 5.0

2018-06-20 Thread Cherniak, Bruce 

> On Jun 18, 2018, at 9:23 AM, Juan A. Suarez Romero  
> wrote:
> 
> RADV now requires LLVM 5.0 or greater, and thus we can't build dist
> tarball because swr requires LLVM 4.0.
> 
> Let's bump required LLVM to 5.0 in swr too.

Sorry, I didn't see this sooner.  We are fine with bumping the swr minimum 
requirement
to LLVM 5.0.  It generates better code anyway.

> Fixes: f9eb1ef870 ("amd: remove support for LLVM 4.0")
> Cc: George Kyriazis 
> Cc: Tim Rowley 
> Cc: Emil Velikov 
> Cc: Dylan Baker 
> Cc: Eric Engestrom 
> ---
> .travis.yml | 12 ++--
> configure.ac|  7 ---
> meson.build |  4 +---
> src/gallium/drivers/swr/Makefile.am |  6 +++---
> src/gallium/drivers/swr/SConscript  |  4 ++--
> 5 files changed, 16 insertions(+), 17 deletions(-)
> 
> diff --git a/.travis.yml b/.travis.yml
> index b1fc7de9587..c9a30fa0ef5 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -92,7 +92,7 @@ matrix:
> - BUILD=make
> - MAKEFLAGS="-j4"
> - MAKE_CHECK_COMMAND="true"
> -- LLVM_VERSION=4.0
> +- LLVM_VERSION=5.0
> - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> - OVERRIDE_CC="gcc-4.8"
> - OVERRIDE_CXX="g++-4.8"
> @@ -105,12 +105,12 @@ matrix:
>   addons:
> apt:
>   sources:
> -- llvm-toolchain-trusty-4.0
> +- llvm-toolchain-trusty-5.0
>   packages:
> # LLVM packaging is broken and misses these dependencies
> - libedit-dev
> # From sources above
> -- llvm-4.0-dev
> +- llvm-5.0-dev
> # Common
> - xz-utils
> - x11proto-xf86vidmode-dev
> @@ -432,7 +432,7 @@ matrix:
> - BUILD=scons
> - SCONSFLAGS="-j4"
> - SCONS_TARGET="swr=1"
> -- LLVM_VERSION=4.0
> +- LLVM_VERSION=5.0
> - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> # Keep it symmetrical to the make build. There's no actual SWR, yet.
> - SCONS_CHECK_COMMAND="true"
> @@ -441,13 +441,13 @@ matrix:
>   addons:
> apt:
>   sources:
> -- llvm-toolchain-trusty-4.0
> +- llvm-toolchain-trusty-5.0
>   packages:
> - scons
> # LLVM packaging is broken and misses these dependencies
> - libedit-dev
> # From sources above
> -- llvm-4.0-dev
> +- llvm-5.0-dev
> # Common
> - xz-utils
> - x11proto-xf86vidmode-dev
> diff --git a/configure.ac b/configure.ac
> index 7a0e4754208..543b6fe061b 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -110,7 +110,7 @@ LLVM_REQUIRED_OPENCL=3.9.0
> LLVM_REQUIRED_R600=3.9.0
> LLVM_REQUIRED_RADEONSI=5.0.0
> LLVM_REQUIRED_RADV=5.0.0
> -LLVM_REQUIRED_SWR=4.0.0
> +LLVM_REQUIRED_SWR=5.0.0
> 
> dnl Check for progs
> AC_PROG_CPP
> @@ -2755,8 +2755,9 @@ if test -n "$with_gallium_drivers"; then
> fi
> 
> # XXX: Keep in sync with LLVM_REQUIRED_SWR
> -AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x4.0.0 -a \
> -  "x$LLVM_VERSION" != x4.0.1)
> +AM_CONDITIONAL(SWR_INVALID_LLVM_VERSION, test "x$LLVM_VERSION" != x5.0.0 -a \
> +  "x$LLVM_VERSION" != x5.0.1 -a \
> +  "x$LLVM_VERSION" != x5.0.2)
> 
> if test "x$enable_llvm" = "xyes" -a "$with_gallium_drivers"; then
> llvm_require_version $LLVM_REQUIRED_GALLIUM "gallium"
> diff --git a/meson.build b/meson.build
> index 65ae32172d2..a5662160d66 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -1130,10 +1130,8 @@ if with_gallium_opencl
>   llvm_optional_modules += ['coroutines', 'opencl']
> endif
> 
> -if with_amd_vk or with_gallium_radeonsi
> +if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
>   _llvm_version = '>= 5.0.0'
> -elif with_gallium_swr
> -  _llvm_version = '>= 4.0.0'
> elif with_gallium_opencl or with_gallium_r600
>   _llvm_version = '>= 3.9.0'
> else
> diff --git a/src/gallium/drivers/swr/Makefile.am 
> b/src/gallium/drivers/swr/Makefile.am
> index 8b3150288e6..5cc3f77478a 100644
> --- a/src/gallium/drivers/swr/Makefile.am
> +++ b/src/gallium/drivers/swr/Makefile.am
> @@ -374,9 +374,9 @@ include $(top_srcdir)/install-gallium-links.mk
> # created with the oldest supported version of LLVM.
> dist-hook:
> if SWR_INVALID_LLVM_VERSION
> - @echo "***"
> - @echo "LLVM 4.0.0 or LLVM 4.0.1 required to create the tarball"
> - @echo "***"
> + @echo "*"
> + @echo "LLVM 5.0.x required to create the tarball"
> + @echo "*"
>   @test
> endif
> 
> diff --git a/src/gallium/drivers/swr/SConscript 
> b/src/gallium/drivers/swr/SConscript
> index 528cfac

[Mesa-dev] [PATCH] st/nir: Disable varying packing when doing transform feedback.

2018-06-20 Thread Eric Anholt 
If one of the TF variables got varying-packed, it would end up with a new
driver_location, despite the pipe_stream_output already being set up for
the old driver location.  This left the gallium driver with no way to work
back to what varying was referenced by pipe_stream_output.

Fixes these tests on V3D:
dEQP-GLES3.functional.transform_feedback.random.separate.points.3
dEQP-GLES3.functional.transform_feedback.random.separate.points.7
dEQP-GLES3.functional.transform_feedback.random.separate.points.9
dEQP-GLES3.functional.transform_feedback.random.separate.triangles.3
dEQP-GLES3.functional.transform_feedback.random.separate.triangles.8
---
 src/mesa/state_tracker/st_glsl_to_nir.cpp | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index d24944c6af51..6d19bb0dfb8a 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -739,7 +739,15 @@ st_link_nir(struct gl_context *ctx,
   shader->Program->info = nir->info;
 
   if (prev != -1) {
- 
nir_compact_varyings(shader_program->_LinkedShaders[prev]->Program->nir,
+ struct gl_program *prev_shader =
+shader_program->_LinkedShaders[prev]->Program;
+
+ /* We can't use nir_compact_varyings with transform feedback, since
+  * the pipe_stream_output->output_register field is based on the
+  * pre-compacted driver_locations.
+  */
+ if (!prev_shader->sh.LinkedTransformFeedback)
+
nir_compact_varyings(shader_program->_LinkedShaders[prev]->Program->nir,
   nir, ctx->API != API_OPENGL_COMPAT);
   }
   prev = i;
-- 
2.17.0

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Re: [Mesa-dev] [PATCH v2 06/16] intel: aubinator: handle GGTT mappings

2018-06-20 Thread Lionel Landwerlin 

On 20/06/18 19:19, Rafael Antognolli wrote:

On Tue, Jun 19, 2018 at 02:45:21PM +0100, Lionel Landwerlin wrote:

We use memfd to store physical pages as they get read/written to and
the GGTT entries translating virtual address to physical pages.

Based on a commit by Scott Phillips.

Signed-off-by: Lionel Landwerlin 
---
  src/intel/tools/aubinator.c | 256 ++--
  1 file changed, 243 insertions(+), 13 deletions(-)

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index f70038376be..962546d360c 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -39,12 +39,23 @@
  
  #include "util/list.h"

  #include "util/macros.h"
+#include "util/rb_tree.h"
  
  #include "common/gen_decoder.h"

  #include "common/gen_disasm.h"
  #include "common/gen_gem.h"
  #include "intel_aub.h"
  
+#ifndef HAVE_MEMFD_CREATE

+#include 
+
+static inline int
+memfd_create(const char *name, unsigned int flags)
+{
+   return syscall(SYS_memfd_create, name, flags);
+}
+#endif
+
  /* Below is the only command missing from intel_aub.h in libdrm
   * So, reuse intel_aub.h from libdrm and #define the
   * AUB_MI_BATCH_BUFFER_END as below
@@ -73,9 +84,27 @@ struct gen_batch_decode_ctx batch_ctx;
  struct bo_map {
 struct list_head link;
 struct gen_batch_decode_bo bo;
+   bool unmap_after_use;
+};
+
+struct ggtt_entry {
+   struct rb_node node;
+   uint64_t virt_addr;
+   uint64_t phys_addr;
+};
+
+struct phys_mem {
+   struct rb_node node;
+   uint64_t fd_offset;
+   uint64_t phys_addr;
+   uint8_t *data;
  };
  
  static struct list_head maps;

+static struct rb_tree ggtt = {NULL};
+static struct rb_tree mem = {NULL};
+int mem_fd = -1;
+off_t mem_fd_len = 0;
  
  FILE *outfile;
  
@@ -92,11 +121,12 @@ field(uint32_t value, int start, int end)

  struct brw_instruction;
  
  static void

-add_gtt_bo_map(struct gen_batch_decode_bo bo)
+add_gtt_bo_map(struct gen_batch_decode_bo bo, bool unmap_after_use)
  {
 struct bo_map *m = calloc(1, sizeof(*m));
  
 m->bo = bo;

+   m->unmap_after_use = unmap_after_use;
 list_add(&m->link, &maps);
  }
  
@@ -104,21 +134,208 @@ static void

  clear_bo_maps(void)
  {
 list_for_each_entry_safe(struct bo_map, i, &maps, link) {
+  if (i->unmap_after_use)
+ munmap((void *)i->bo.map, i->bo.size);
list_del(&i->link);
free(i);
 }
  }
  
+static inline struct ggtt_entry *

+ggtt_entry_next(struct ggtt_entry *entry)
+{
+   if (!entry)
+  return NULL;
+   struct rb_node *node = rb_node_next(&entry->node);
+   if (!node)
+  return NULL;
+   return rb_node_data(struct ggtt_entry, node, node);
+}
+
+static inline int
+cmp_uint64(uint64_t a, uint64_t b)
+{
+   if (a < b)
+  return -1;
+   if (a > b)
+  return 1;
+   return 0;
+}
+
+static inline int
+cmp_ggtt_entry(const struct rb_node *node, const void *addr)
+{
+   struct ggtt_entry *entry = rb_node_data(struct ggtt_entry, node, node);
+   return cmp_uint64(entry->virt_addr, *(uint64_t *)addr);
+}
+
+static struct ggtt_entry *
+ensure_ggtt_entry(struct rb_tree *tree, uint64_t virt_addr)
+{
+   struct rb_node *node = rb_tree_search_sloppy(&ggtt, &virt_addr,
+cmp_ggtt_entry);
+   int cmp = 0;
+   if (!node || (cmp = cmp_ggtt_entry(node, &virt_addr))) {
+  struct ggtt_entry *new_entry = calloc(1, sizeof(*new_entry));
+  new_entry->virt_addr = virt_addr;
+  rb_tree_insert_at(&ggtt, node, &new_entry->node, cmp > 0);
+  node = &new_entry->node;
+   }
+
+   return rb_node_data(struct ggtt_entry, node, node);
+}
+
+static struct ggtt_entry *
+search_ggtt_entry(uint64_t virt_addr)
+{
+   virt_addr &= ~0xfff;
+
+   struct rb_node *node = rb_tree_search(&ggtt, &virt_addr, cmp_ggtt_entry);
+
+   if (!node)
+  return NULL;
+
+   return rb_node_data(struct ggtt_entry, node, node);
+}
+
+static inline int
+cmp_phys_mem(const struct rb_node *node, const void *addr)
+{
+   struct phys_mem *mem = rb_node_data(struct phys_mem, node, node);
+   return cmp_uint64(mem->phys_addr, *(uint64_t *)addr);
+}
+
+static struct phys_mem *
+ensure_phys_mem(uint64_t phys_addr)
+{
+   struct rb_node *node = rb_tree_search_sloppy(&mem, &phys_addr, 
cmp_phys_mem);
+   int cmp = 0;
+   if (!node || (cmp = cmp_phys_mem(node, &phys_addr))) {
+  struct phys_mem *new_mem = calloc(1, sizeof(*new_mem));
+  new_mem->phys_addr = phys_addr;
+  new_mem->fd_offset = mem_fd_len;
+
+  int ftruncate_res = ftruncate(mem_fd, mem_fd_len += 4096);
+  assert(ftruncate_res == 0);
+
+  new_mem->data = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED,
+   mem_fd, new_mem->fd_offset);
+  assert(new_mem->data != MAP_FAILED);
+
+  rb_tree_insert_at(&mem, node, &new_mem->node, cmp > 0);
+  node = &new_mem->node;
+   }
+
+   return rb_node_data(struct phys_mem, node, node);
+}
+
+static struct phys_mem *
+search_phys_mem(uint64_t phys_addr)
+{
+   phys_addr

Re: [Mesa-dev] [PATCH v2] anv, radv: Add support for VK_KHR_get_display_properties2

2018-06-20 Thread Keith Packard 
Jason Ekstrand  writes:

All looks good to me.

Reviewed-by: Keith Packard 

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Re: [Mesa-dev] [PATCH] anv, radv: Add support for VK_KHR_get_display_properties2

2018-06-20 Thread Keith Packard 
Jason Ekstrand  writes:

> I just sent a v2 which allocates a temporary array, calls properties2, and
> then copies it back over.  It doesn't duplicate the iteration code and
> instead just leverages propertie2.  On the down side, it's a bit more
> allocation and data motion but, compared to the ioctl that properties2 is
> doing, it shouldn't be noticeable.  Let me know what you think of that
> version.

Seems a bit better; this is not exactly a high-use API and clearer
counts for a lot.

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Re: [Mesa-dev] [PATCH v2 11/16] intel: tools: update intel_aub.h

2018-06-20 Thread Rafael Antognolli 
On Tue, Jun 19, 2018 at 02:45:26PM +0100, Lionel Landwerlin wrote:
> Scott added new stuff in IGT.
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/tools/intel_aub.h | 26 ++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/src/intel/tools/intel_aub.h b/src/intel/tools/intel_aub.h
> index 5f0aba8e68e..9ca548edaf3 100644
> --- a/src/intel/tools/intel_aub.h
> +++ b/src/intel/tools/intel_aub.h
> @@ -49,6 +49,12 @@
>  #define CMD_AUB  (7 << 29)
>  
>  #define CMD_AUB_HEADER   (CMD_AUB | (1 << 23) | (0x05 << 16))
> +
> +#define CMD_MEM_TRACE_REGISTER_POLL  (CMD_AUB | (0x2e << 23) | (0x02 << 16))
> +#define CMD_MEM_TRACE_REGISTER_WRITE (CMD_AUB | (0x2e << 23) | (0x03 << 16))
> +#define CMD_MEM_TRACE_MEMORY_WRITE   (CMD_AUB | (0x2e << 23) | (0x06 << 16))
> +#define CMD_MEM_TRACE_VERSION(CMD_AUB | (0x2e << 23) | (0x0e 
> << 16))
> +
>  /* DW1 */
>  # define AUB_HEADER_MAJOR_SHIFT  24
>  # define AUB_HEADER_MINOR_SHIFT  16
> @@ -92,8 +98,28 @@
>  #define AUB_TRACE_MEMTYPE_PCI(3 << 16)
>  #define AUB_TRACE_MEMTYPE_GTT_ENTRY (4 << 16)
>  
> +#define AUB_MEM_TRACE_VERSION_FILE_VERSION   1
> +
>  /* DW2 */
>  
> +#define AUB_MEM_TRACE_VERSION_DEVICE_MASK0xff00
> +#define AUB_MEM_TRACE_VERSION_DEVICE_CNL (15 << 8)
> +
> +#define AUB_MEM_TRACE_VERSION_METHOD_MASK0x000c
> +#define AUB_MEM_TRACE_VERSION_METHOD_PHY (1 << 18)
> +
> +#define AUB_MEM_TRACE_REGISTER_SIZE_MASK 0x000f
> +#define AUB_MEM_TRACE_REGISTER_SIZE_DWORD(2 << 16)
> +
> +#define AUB_MEM_TRACE_REGISTER_SPACE_MASK0xf000
> +#define AUB_MEM_TRACE_REGISTER_SPACE_MMIO(0 << 28)
> +
> +/* DW3 */
> +
> +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_MASK  0xf000
> +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL (1 << 28)
> +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY(4 << 28)
> +

Cool, we can use these last ones in aubinator's
handle_memtrace_mem_write(). That could be done later though.

Reviewed-by: Rafael Antognolli 

>  /**
>   * aub_state_struct_type enum values are encoded with the top 16 bits
>   * representing the type to be delivered to the .aub file, and the bottom 16
> -- 
> 2.17.1
> 
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Re: [Mesa-dev] [PATCH 5/7] vulkan: add VK_EXT_display_control [v5]

2018-06-20 Thread Jason Ekstrand 
On Tue, Jun 19, 2018 at 9:44 PM, Keith Packard  wrote:

> Jason Ekstrand  writes:
>
>
> >> +  if (!prop)
> >> + continue;
> >> +  if (prop->flags & DRM_MODE_PROP_ENUM) {
> >> + if (!strcmp(prop->name, "DPMS"))
> >> +connector->dpms_property = drm_connector->props[p];
> >>
> >
> > break?
>
> Not break; I need to free the property. However, an early exit from the
> loop seems reasonable. How about:
>
>for (int p = 0; connector->dpms_property == 0 && p <
> drm_connector->count_props; p++) {
>
> This skips the whole sequence if the property has already been found, or
> stops as soon as it has.
>

That seems good to me.  Unless, of course, DPMS is something we expect to
change over time somehow.  Then again, we don't handle that at all right
now so meh.  Let's go with what you wrote above for now.


> >> +static bool
> >> +wsi_display_fence_wait(struct wsi_fence *fence_wsi,
> >> +   bool absolute,
> >> +   uint64_t timeout)
> >>
> >
> > Would it make more sense for this function to return a VkResult?  Then
> you
> > could tell the difference between success, timeout, and some other
> > failure.  I guess the only other thing to return would be
> > VK_ERROR_DEVICE_LOST which seems pretty harsh but, then again,
> > pthread_timed_wait just failed so that's also really bad.
>
> That's a good idea. The boolean return is pretty ambiguous. I copied
> that from the radv internal fence API, which could also benefit from
> this change. I've changed the API and adjusted the anv and radv code to
> match. It reads a lot better now.
>

Cool.


> >> +   if (!absolute)
> >> +  timeout = wsi_rel_to_abs_time(timeout);
> >>
> >
> > Are relative times really useful?  I suspect it doesn't save you more
> than
> > a couple of lines and it makes the interface weird.
>
> No. Relative timeouts aren't actually used anywhere either. I've removed
> them.
>

Sounds good.


> I did catch a mistake in the anv driver looking at this -- the !waitAll
> code wasn't bothering to check the fences if the time had already
> passed, so an application polling would never catch the fences being
> ready. I've changed the while (current_time < timeout) {} to a do {}
> while (current_time < timeout) loop.
>

Yeah, that was going to be a problem for someone if they ever decided to
busy-loop in the app. :-)


> >> +static void
> >> +wsi_display_fence_destroy(struct wsi_fence *fence_wsi)
> >> +{
> >> +   struct wsi_display_fence *fence = (struct wsi_display_fence *)
> >> fence_wsi;
> >> +
> >>
> >
> > An assert(!fence->destroyed) in here might be useful to guard against
> > double-frees.
>
> Sure. I was under the impression that application bugs weren't supposed
> to be rigorously checked in the implementation though? When should I be
> checking API usage issues?
>

They shouldn't be and that's why I'm a fan of making them asserts which get
compiled out instead of actual checks.  Also, I find this pseudo reference
counting to be somewhat confusing and adding asserts informs the reader of
the assumptions made.


> >> +  if (!ret)
> >> + return VK_SUCCESS;
> >> +
> >> +  if (errno != ENOMEM) {
> >> + wsi_display_debug("queue vblank event %lu failed\n",
> >> fence->sequence);
> >> + struct timespec delay = {
> >> +.tv_sec = 0,
> >> +.tv_nsec = 1ull,
> >> + };
> >> + nanosleep(&delay, NULL);
> >> + return VK_ERROR_OUT_OF_HOST_MEMORY;
> >>
> >
> > Why are we sleeping for 0.1s before we return?  That seems fishy.
>
> Yeah, the kernel API is not great. There's a finite queue which can be
> consumed with both flip events and vblank wait events. If that fills,
> we'll get an error back. The only way to empty it is to have some events
> get delivered, and those will only get delivered after a vblank happens.
>
> It's an application bug that triggers this -- requesting too many vblank
> events. Throttling the application so it doesn't just spin makes it
> possible to stop it.
>
> >> +  pthread_mutex_lock(&wsi->wait_mutex);
> >> +  ret = wsi_display_wait_for_event(wsi, wsi_rel_to_abs_time(
> >> 1ull));
> >>
> >
> > What's with the magic number?
>
> 0.1s -- a value which is longer than any display time, but short enough
> to catch things like DPMS off or VT switch without unduly delaying the
> application.
>
> >> +VkResult
> >> +wsi_register_device_event(VkDevice device,
> >> +  struct wsi_device *wsi_device,
> >> +  const VkDeviceEventInfoEXT
> *device_event_info,
> >> +  const VkAllocationCallbacks *allocator,
> >> +  struct wsi_fence **fence_p)
> >> +{
> >> +   return VK_ERROR_FEATURE_NOT_PRESENT;
> >>
> >
> > I don't think we're allowed to just not implemnet this.  At the very
> least,
> > we should accept the event and never trigger it.  Better would be to
> > actually wire up hotplug det

[Mesa-dev] [Bug 106910] Primus Segfaults after updating Mesa to 18.1.1

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106910

Daniel Serpell  changed:

   What|Removed |Added

   Assignee|mesa-dev@lists.freedesktop. |intel-3d-bugs@lists.freedes
   |org |ktop.org
 QA Contact|mesa-dev@lists.freedesktop. |intel-3d-bugs@lists.freedes
   |org |ktop.org
  Component|Other   |Drivers/DRI/i965

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Re: [Mesa-dev] [PATCH v2 12/16] intel: tools: import intel_aubdump

2018-06-20 Thread Rafael Antognolli 
diff -u --ignore-all-space shows that this and the original file are
roughly the same, except for some macros, some includes and how we check
for hardware gen.

Acked-by: Rafael Antognolli 

On Tue, Jun 19, 2018 at 02:45:27PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/Makefile.am |2 +
>  src/intel/tools/intel_dump_gpu.c  | 1313 +
>  src/intel/tools/intel_dump_gpu.in |  107 +++
>  src/intel/tools/meson.build   |   18 +
>  4 files changed, 1440 insertions(+)
>  create mode 100644 src/intel/tools/intel_dump_gpu.c
>  create mode 100755 src/intel/tools/intel_dump_gpu.in
> 
> diff --git a/src/intel/Makefile.am b/src/intel/Makefile.am
> index 3e098a7ac9b..8448640983f 100644
> --- a/src/intel/Makefile.am
> +++ b/src/intel/Makefile.am
> @@ -71,6 +71,8 @@ EXTRA_DIST = \
>   isl/meson.build \
>   tools/intel_sanitize_gpu.c \
>   tools/intel_sanitize_gpu.in \
> + tools/intel_dump_gpu.c \
> + tools/intel_dump_gpu.in \
>   tools/meson.build \
>   vulkan/meson.build \
>   meson.build
> diff --git a/src/intel/tools/intel_dump_gpu.c 
> b/src/intel/tools/intel_dump_gpu.c
> new file mode 100644
> index 000..86c133da433
> --- /dev/null
> +++ b/src/intel/tools/intel_dump_gpu.c
> @@ -0,0 +1,1313 @@
> +/*
> + * Copyright © 2015 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "intel_aub.h"
> +
> +#include "dev/gen_device_info.h"
> +#include "util/macros.h"
> +
> +#ifndef ALIGN
> +#define ALIGN(x, y) (((x) + (y)-1) & ~((y)-1))
> +#endif
> +
> +#define MI_LOAD_REGISTER_IMM_n(n) ((0x22 << 23) | (2 * (n) - 1))
> +#define MI_LRI_FORCE_POSTED   (1<<12)
> +
> +#define MI_BATCH_BUFFER_END (0xA << 23)
> +
> +#define min(a, b) ({\
> + __typeof(a) _a = (a);  \
> + __typeof(b) _b = (b);  \
> + _a < _b ? _a : _b; \
> +  })
> +
> +#define HWS_PGA_RCSUNIT  0x02080
> +#define HWS_PGA_VCSUNIT0   0x12080
> +#define HWS_PGA_BCSUNIT  0x22080
> +
> +#define GFX_MODE_RCSUNIT   0x0229c
> +#define GFX_MODE_VCSUNIT0   0x1229c
> +#define GFX_MODE_BCSUNIT   0x2229c
> +
> +#define EXECLIST_SUBMITPORT_RCSUNIT   0x02230
> +#define EXECLIST_SUBMITPORT_VCSUNIT0   0x12230
> +#define EXECLIST_SUBMITPORT_BCSUNIT   0x22230
> +
> +#define EXECLIST_STATUS_RCSUNIT  0x02234
> +#define EXECLIST_STATUS_VCSUNIT0   0x12234
> +#define EXECLIST_STATUS_BCSUNIT  0x22234
> +
> +#define EXECLIST_SQ_CONTENTS0_RCSUNIT   0x02510
> +#define EXECLIST_SQ_CONTENTS0_VCSUNIT0   0x12510
> +#define EXECLIST_SQ_CONTENTS0_BCSUNIT   0x22510
> +
> +#define EXECLIST_CONTROL_RCSUNIT   0x02550
> +#define EXECLIST_CONTROL_VCSUNIT0   0x12550
> +#define EXECLIST_CONTROL_BCSUNIT   0x22550
> +
> +#define MEMORY_MAP_SIZE (64 /* MiB */ * 1024 * 1024)
> +
> +#define PTE_SIZE 4
> +#define GEN8_PTE_SIZE 8
> +
> +#define NUM_PT_ENTRIES (ALIGN(MEMORY_MAP_SIZE, 4096) / 4096)
> +#define PT_SIZE ALIGN(NUM_PT_ENTRIES * GEN8_PTE_SIZE, 4096)
> +
> +#define RING_SIZE (1 * 4096)
> +#define PPHWSP_SIZE (1 * 4096)
> +#define GEN10_LR_CONTEXT_RENDER_SIZE   (19 * 4096)
> +#define GEN8_LR_CONTEXT_OTHER_SIZE   (2 * 4096)
> +
> +#define STATIC_GGTT_MAP_START 0
> +
> +#define RENDER_RING_ADDR STATIC_GGTT_MAP_START
> +#define RENDER_CONTEXT_ADDR (RENDER_RING_ADDR + RING_SIZE)
> +
> +#define BLITTER_RING_ADDR (RENDER_CONTEXT_ADDR + PPHWSP_SIZE + 
> GEN10_LR_CONTEXT_RENDER_SIZE)
> +#define BLITTER_CONTEXT_ADDR (BLITTER_RING_ADDR + RING_SIZE)
> +
> +#define VIDEO_RING_ADDR (BLITTER_CONTEXT_ADDR +

Re: [Mesa-dev] [PATCH v2 13/16] intel: tools: dump-gpu: dump 48-bit addresses

2018-06-20 Thread Rafael Antognolli 
On Tue, Jun 19, 2018 at 02:45:28PM +0100, Lionel Landwerlin wrote:
> From: Scott D Phillips 
> 
> For gen8+, write out PPGTT tables in aub files so that full 48-bit
> addresses can be serialized.
> 
> v2: Fix handling of `end` index in map_ppgtt
> 
> Signed-off-by: Scott D Phillips 
> Signed-off-by: Lionel Landwerlin 
> Cc: Jordan Justen 
> ---
>  src/intel/tools/intel_aub.h  |   3 +-
>  src/intel/tools/intel_dump_gpu.c | 315 +++
>  2 files changed, 151 insertions(+), 167 deletions(-)
> 
> diff --git a/src/intel/tools/intel_aub.h b/src/intel/tools/intel_aub.h
> index 9ca548edaf3..2888515048f 100644
> --- a/src/intel/tools/intel_aub.h
> +++ b/src/intel/tools/intel_aub.h
> @@ -117,7 +117,8 @@
>  /* DW3 */
>  
>  #define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_MASK  0xf000
> -#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_LOCAL (1 << 28)
> +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT  (0 << 28)
> +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_PHYSICAL  (2 << 28)
>  #define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_GGTT_ENTRY(4 << 28)
>  
>  /**
> diff --git a/src/intel/tools/intel_dump_gpu.c 
> b/src/intel/tools/intel_dump_gpu.c
> index 86c133da433..bfff481ba5e 100644
> --- a/src/intel/tools/intel_dump_gpu.c
> +++ b/src/intel/tools/intel_dump_gpu.c
> @@ -51,6 +51,8 @@
>  #define MI_LOAD_REGISTER_IMM_n(n) ((0x22 << 23) | (2 * (n) - 1))
>  #define MI_LRI_FORCE_POSTED   (1<<12)
>  
> +#define MI_BATCH_NON_SECURE_I965 (1 << 8)
> +
>  #define MI_BATCH_BUFFER_END (0xA << 23)
>  
>  #define min(a, b) ({\
> @@ -59,6 +61,12 @@
>   _a < _b ? _a : _b; \
>})
>  
> +#define max(a, b) ({\
> + __typeof(a) _a = (a);  \
> + __typeof(b) _b = (b);  \
> + _a > _b ? _a : _b; \
> +  })
> +
>  #define HWS_PGA_RCSUNIT  0x02080
>  #define HWS_PGA_VCSUNIT0   0x12080
>  #define HWS_PGA_BCSUNIT  0x22080
> @@ -93,8 +101,12 @@
>  
>  #define RING_SIZE (1 * 4096)
>  #define PPHWSP_SIZE (1 * 4096)
> -#define GEN10_LR_CONTEXT_RENDER_SIZE   (19 * 4096)
> -#define GEN8_LR_CONTEXT_OTHER_SIZE   (2 * 4096)
> +#define GEN11_LR_CONTEXT_RENDER_SIZE(14 * 4096)
> +#define GEN10_LR_CONTEXT_RENDER_SIZE(19 * 4096)
> +#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * 4096)
> +#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * 4096)
> +#define GEN8_LR_CONTEXT_OTHER_SIZE  (2 * 4096)
> +
>  
>  #define STATIC_GGTT_MAP_START 0
>  
> @@ -110,14 +122,19 @@
>  #define STATIC_GGTT_MAP_END (VIDEO_CONTEXT_ADDR + PPHWSP_SIZE + 
> GEN8_LR_CONTEXT_OTHER_SIZE)
>  #define STATIC_GGTT_MAP_SIZE (STATIC_GGTT_MAP_END - STATIC_GGTT_MAP_START)
>  
> -#define CONTEXT_FLAGS (0x229)   /* Normal Priority | L3-LLC Coherency |
> -   Legacy Context with no 64 bit VA support 
> | Valid */
> +#define PML4_PHYS_ADDR ((uint64_t)(STATIC_GGTT_MAP_END))
> +
> +#define CONTEXT_FLAGS (0x339)   /* Normal Priority | L3-LLC Coherency |
> + * PPGTT Enabled |
> + * Legacy Context with 64 bit VA support |
> + * Valid
> + */
>  
> -#define RENDER_CONTEXT_DESCRIPTOR  ((uint64_t)1 << 32 | RENDER_CONTEXT_ADDR  
> | CONTEXT_FLAGS)
> -#define BLITTER_CONTEXT_DESCRIPTOR ((uint64_t)2 << 32 | BLITTER_CONTEXT_ADDR 
> | CONTEXT_FLAGS)
> -#define VIDEO_CONTEXT_DESCRIPTOR   ((uint64_t)3 << 32 | VIDEO_CONTEXT_ADDR   
> | CONTEXT_FLAGS)
> +#define RENDER_CONTEXT_DESCRIPTOR  ((uint64_t)1 << 62 | RENDER_CONTEXT_ADDR  
> | CONTEXT_FLAGS)
> +#define BLITTER_CONTEXT_DESCRIPTOR ((uint64_t)2 << 62 | BLITTER_CONTEXT_ADDR 
> | CONTEXT_FLAGS)
> +#define VIDEO_CONTEXT_DESCRIPTOR   ((uint64_t)3 << 62 | VIDEO_CONTEXT_ADDR   
> | CONTEXT_FLAGS)
>  
> -static const uint32_t render_context_init[GEN10_LR_CONTEXT_RENDER_SIZE /
> +static const uint32_t render_context_init[GEN9_LR_CONTEXT_RENDER_SIZE / /* 
> Choose the largest */
>sizeof(uint32_t)] = {
> 0 /* MI_NOOP */,
> MI_LOAD_REGISTER_IMM_n(14) | MI_LRI_FORCE_POSTED,
> @@ -147,8 +164,8 @@ static const uint32_t 
> render_context_init[GEN10_LR_CONTEXT_RENDER_SIZE /
> 0x2280 /* PDP2_LDW */,  0,
> 0x227C /* PDP1_UDW */,  0,
> 0x2278 /* PDP1_LDW */,  0,
> -   0x2274 /* PDP0_UDW */,  0,
> -   0x2270 /* PDP0_LDW */,  0,
> +   0x2274 /* PDP0_UDW */,  PML4_PHYS_ADDR >> 32,
> +   0x2270 /* PDP0_LDW */,  PML4_PHYS_ADDR,
> /* MI_NOOP */
> 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
>  
> @@ -185,8 +202,8 @@ static const uint32_t 
> blitter_context_init[GEN8_LR_CONTEXT_OTHER_SIZE /
> 0x22280 /* PDP2_LDW */,  0,
> 0x2227C /* PDP1_UDW */,  0,
> 0x22278 /* PDP1_LDW */,  0,
> -   0x22274 /* PDP0_UDW */,  0,
> -   0x22270 /* PDP0_LDW */,  0,
> +   0x22274 /* PD

Re: [Mesa-dev] [PATCH] squash! nir/linker: Add gl_nir_link_uniforms()

2018-06-20 Thread Timothy Arceri 

Reviewed-by: Timothy Arceri 

On 20/06/18 22:27, Alejandro Piñeiro wrote:

From: Neil Roberts 

Sets var->driver.location if the uniform was found from a previous
stage.
---

Hi Timothy,

thanks for the review of the original patch. Recently we found that we
missed a little thing (one line). As we didn't push it to master yet,
could you take a look to this change, so we could include it now?

BR

  src/compiler/glsl/gl_nir_link_uniforms.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/src/compiler/glsl/gl_nir_link_uniforms.c 
b/src/compiler/glsl/gl_nir_link_uniforms.c
index a8ebde73270..d3a39577177 100644
--- a/src/compiler/glsl/gl_nir_link_uniforms.c
+++ b/src/compiler/glsl/gl_nir_link_uniforms.c
@@ -419,6 +419,7 @@ gl_nir_link_uniforms(struct gl_context *ctx,
   uniform = find_previous_uniform_storage(prog, var->data.location);
   if (uniform) {
  uniform->active_shader_mask |= 1 << shader_type;
+var->data.location = uniform - prog->data->UniformStorage;
  
  continue;

   }


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Re: [Mesa-dev] [PATCH v2 08/21] spirv: translate default-block uniforms

2018-06-20 Thread Timothy Arceri 

Reviewed-by: Timothy Arceri 

On 12/05/18 19:40, Alejandro Piñeiro wrote:

From: Nicolai Hähnle 

They are supported by SPIR-V for ARB_gl_spirv.

v2 (changes on top of Nicolai's original patch):
* Handle UniformConstant storage class for uniforms other than
  samplers and images. (Eduardo Lima)
* Handle location decoration also for samplers and images. (Eduardo
  Lima)
* Rebase update (spirv_to_nir options added, logging changes, and
  others) (Alejandro Piñeiro)

Signed-off-by: Nicolai Hähnle 
Signed-off-by: Eduardo Lima 
Signed-off-by: Alejandro Piñeiro 
---
  src/compiler/spirv/vtn_private.h   |  1 +
  src/compiler/spirv/vtn_variables.c | 25 +++--
  2 files changed, 16 insertions(+), 10 deletions(-)

diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index b501bbf9b4a..183024e14f4 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -402,6 +402,7 @@ enum vtn_variable_mode {
 vtn_variable_mode_local,
 vtn_variable_mode_global,
 vtn_variable_mode_param,
+   vtn_variable_mode_uniform,
 vtn_variable_mode_ubo,
 vtn_variable_mode_ssbo,
 vtn_variable_mode_push_constant,
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index fd8ab7f247a..eb8a9ca0084 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1544,8 +1544,11 @@ var_decoration_cb(struct vtn_builder *b, struct 
vtn_value *val, int member,
   vtn_var->mode == vtn_variable_mode_output) {
   is_vertex_input = false;
   location += vtn_var->patch ? VARYING_SLOT_PATCH0 : VARYING_SLOT_VAR0;
-  } else {
- vtn_warn("Location must be on input or output variable");
+  } else if (vtn_var->mode != vtn_variable_mode_uniform &&
+ vtn_var->mode != vtn_variable_mode_sampler &&
+ vtn_var->mode != vtn_variable_mode_image) {
+ vtn_warn("Location must be on input, output, uniform, sampler or "
+  "image variable");
   return;
}
  
@@ -1611,7 +1614,9 @@ vtn_storage_class_to_mode(struct vtn_builder *b,

   mode = vtn_variable_mode_ssbo;
   nir_mode = 0;
} else {
- vtn_fail("Invalid uniform variable type");
+ /* Default-block uniforms, coming from gl_spirv */
+ mode = vtn_variable_mode_uniform;
+ nir_mode = nir_var_uniform;
}
break;
 case SpvStorageClassStorageBuffer:
@@ -1619,15 +1624,13 @@ vtn_storage_class_to_mode(struct vtn_builder *b,
nir_mode = 0;
break;
 case SpvStorageClassUniformConstant:
-  if (glsl_type_is_image(interface_type->type)) {
+  if (glsl_type_is_image(interface_type->type))
   mode = vtn_variable_mode_image;
- nir_mode = nir_var_uniform;
-  } else if (glsl_type_is_sampler(interface_type->type)) {
+  else if (glsl_type_is_sampler(interface_type->type))
   mode = vtn_variable_mode_sampler;
- nir_mode = nir_var_uniform;
-  } else {
- vtn_fail("Invalid uniform constant variable type");
-  }
+  else
+ mode = vtn_variable_mode_uniform;
+  nir_mode = nir_var_uniform;
break;
 case SpvStorageClassPushConstant:
mode = vtn_variable_mode_push_constant;
@@ -1795,11 +1798,13 @@ vtn_create_variable(struct vtn_builder *b, struct 
vtn_value *val,
 case vtn_variable_mode_global:
 case vtn_variable_mode_image:
 case vtn_variable_mode_sampler:
+   case vtn_variable_mode_uniform:
/* For these, we create the variable normally */
var->var = rzalloc(b->shader, nir_variable);
var->var->name = ralloc_strdup(var->var, val->name);
var->var->type = var->type->type;
var->var->data.mode = nir_mode;
+  var->var->data.location = -1;
  
switch (var->mode) {

case vtn_variable_mode_image:


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[Mesa-dev] [Bug 106980] Basemark GPU vulkan benchmark fails.

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106980

Bug ID: 106980
   Summary: Basemark GPU vulkan benchmark fails.
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: b...@basnieuwenhuizen.nl
QA Contact: mesa-dev@lists.freedesktop.org

basemark: https://www.basemark.com/products/basemark-gpu/

to run you need some old libraries:
https://packages.ubuntu.com/bionic/amd64/libcurl3/download
https://packages.ubuntu.com/bionic/amd64/libssl1.0.0/download

just download, extract and use LD_LIBRARY_PATH

it aborts with

extra entries in SSA def uses:
0x7ff0281861a0


Christoph Haag tested without nir_validate and for him it hung.

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Re: [Mesa-dev] [PATCH 6/7] anv: add VK_EXT_display_control to anv driver [v2]

2018-06-20 Thread Keith Packard 
Jason Ekstrand  writes:

> I believe that the WSI common code should be capable of fishing the
> instance allocator out of the wsi_display so we need only pass the
> allocator argument unmodified through to the core WSI code.  Make sense?

Thanks, I think I've sorted it out. I've pushed an updated series with
this change.

> Yeah, Vulkan allocator fishing is weird.

Allowing custom allocators is one of the bad parts of the Vulkan spec;
it will "never" get used, and the chances of it working correctly in any
driver are pretty small. But, we do what we can to implement it.

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Re: [Mesa-dev] [PATCH 5/7] vulkan: add VK_EXT_display_control [v5]

2018-06-20 Thread Keith Packard 
Jason Ekstrand  writes:

> That seems good to me.  Unless, of course, DPMS is something we expect to
> change over time somehow.  Then again, we don't handle that at all right
> now so meh.  Let's go with what you wrote above for now.

It's not even the dpms value, it's the dpms property itself, which
DRM never changes.

> They shouldn't be and that's why I'm a fan of making them asserts which get
> compiled out instead of actual checks.  Also, I find this pseudo reference
> counting to be somewhat confusing and adding asserts informs the reader of
> the assumptions made.

Ok, I've added this.

> What test suite?  Honestly, I know of no code anywhere that actually uses
> this API for anything other than VR headsets.
>
> I guess it's kind-of a question of how much effort we want to put into
> this.  One option would be to add VK_KHR_display support to vkcube and make
> it automatically show up on all your displays using hotplug events.
>
> If we're going to not care, returning VK_ERROR_FEATURE_NOT_PRESENT is
> probably the best thing to do since at least the app has feedback.

Not caring seems best to me -- the Vulkan display API isn't capable of
supporting a "real" window system; for that, you'd really want to use
DRM directly and create some way to share that with Vulkan like the
extension I wrote to pass the DRM master FD into the driver at init time.

> Awesome.  I think we're really close on this one.

I'll send out the current series and you can see if you like it.

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[Mesa-dev] [PATCH mesa 0/4] Add EXT_display_control [v8]

2018-06-20 Thread Keith Packard 
Here's the latest version of this series with only a few minor
changes. It adapts to the API changes for surface_get_capabilities and
changes how the allocator is found for fences.


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[Mesa-dev] [PATCH mesa 4/4] radv: add VK_EXT_display_control to radv driver [v5]

2018-06-20 Thread Keith Packard 
This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.

v2:
Rework fence integration into the driver so that waiting for
any of a mixture of fence types (wsi, driver or syncobjs)
causes the driver to poll, while a list of just syncobjs or
just driver fences will block. When we get syncobjs for wsi
fences, we'll adapt to use them.

v3: Adopt Jason Ekstrand's coding conventions

Declare variables at first use, eliminate extra whitespace between
types and names. Wrap lines to 80 columns.

Suggested-by: Jason Ekstrand 

v4: Adapt to WSI fence API change. It now returns VkResult and
no longer has an option for relative timeouts.

v5: wsi_register_display_event and wsi_register_device_event now
use the default allocator when NULL is provided, so remove the
computation of 'alloc' here.

Signed-off-by: Keith Packard 
---
 src/amd/vulkan/radv_device.c  |  70 -
 src/amd/vulkan/radv_extensions.py |   1 +
 src/amd/vulkan/radv_private.h |   1 +
 src/amd/vulkan/radv_wsi_display.c | 101 ++
 4 files changed, 158 insertions(+), 15 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index ffeb6450b33..b560f1c3085 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3241,6 +3241,7 @@ VkResult radv_CreateFence(
if (!fence)
return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 
+   fence->fence_wsi = NULL;
fence->submitted = false;
fence->signalled = !!(pCreateInfo->flags & 
VK_FENCE_CREATE_SIGNALED_BIT);
fence->temp_syncobj = 0;
@@ -3285,6 +3286,8 @@ void radv_DestroyFence(
device->ws->destroy_syncobj(device->ws, fence->syncobj);
if (fence->fence)
device->ws->destroy_fence(fence->fence);
+   if (fence->fence_wsi)
+   fence->fence_wsi->destroy(fence->fence_wsi);
vk_free2(&device->alloc, pAllocator, fence);
 }
 
@@ -3310,7 +3313,19 @@ static bool radv_all_fences_plain_and_submitted(uint32_t 
fenceCount, const VkFen
 {
for (uint32_t i = 0; i < fenceCount; ++i) {
RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
-   if (fence->syncobj || fence->temp_syncobj || (!fence->signalled 
&& !fence->submitted))
+   if (fence->fence == NULL || fence->syncobj ||
+   fence->temp_syncobj ||
+   (!fence->signalled && !fence->submitted))
+   return false;
+   }
+   return true;
+}
+
+static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence 
*pFences)
+{
+   for (uint32_t i = 0; i < fenceCount; ++i) {
+   RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
+   if (fence->syncobj == 0 && fence->temp_syncobj == 0)
return false;
}
return true;
@@ -3326,7 +3341,9 @@ VkResult radv_WaitForFences(
RADV_FROM_HANDLE(radv_device, device, _device);
timeout = radv_get_absolute_timeout(timeout);
 
-   if (device->always_use_syncobj) {
+   if (device->always_use_syncobj &&
+   radv_all_fences_syncobj(fenceCount, pFences))
+   {
uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
if (!handles)
return vk_error(device->instance, 
VK_ERROR_OUT_OF_HOST_MEMORY);
@@ -3396,21 +3413,34 @@ VkResult radv_WaitForFences(
if (fence->signalled)
continue;
 
-   if (!fence->submitted) {
-   while(radv_get_current_time() <= timeout && 
!fence->submitted)
-   /* Do nothing */;
+   if (fence->fence) {
+   if (!fence->submitted) {
+   while(radv_get_current_time() <= timeout &&
+ !fence->submitted)
+   /* Do nothing */;
 
-   if (!fence->submitted)
-   return VK_TIMEOUT;
+   if (!fence->submitted)
+   return VK_TIMEOUT;
+
+   /* Recheck as it may have been set by
+* submitting operations. */
 
-   /* Recheck as it may have been set by submitting 
operations. */
-   if (fence->signalled)
-   continue;
+   if (fence->signalled)
+   continue;
+   }
+
+   expired = device->ws->fence_wait(device->ws,
+fence->fence,
+

[Mesa-dev] [PATCH mesa 1/4] anv: Support wait for heterogeneous list of fences [v3]

2018-06-20 Thread Keith Packard 
Handle the case where the set of fences to wait for is not all of the
same type by either waiting for them sequentially (waitAll), or
polling them until the timer has expired (!waitAll). We hope the
latter case is not common.

While the current code makes sure that it always has fences of only
one type, that will not be true when we add WSI fences. Split out this
refactoring to make merging that clearer.

v2: Adopt Jason Ekstrand's coding conventions

Declare variables at first use, eliminate extra whitespace between
types and names. Wrap lines to 80 columns.

Suggested-by: Jason Ekstrand 

v2:
Cast INT64_MAX to uint64_t to make of its use as the maximum
possible timeout clearly unsigned to the reader.

Suggested-by: Jason Ekstrand 

Make anv_wait_for_fences with !waitAll check all fences at least
once, even if the requested timeout has already passed.

Signed-off-by: Keith Packard 
Reviewed-by: Jason Ekstrand 
---
 src/intel/vulkan/anv_queue.c | 108 +--
 1 file changed, 90 insertions(+), 18 deletions(-)

diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index 6fe04a0a19d..6e275629e14 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -459,12 +459,33 @@ gettime_ns(void)
return (uint64_t)current.tv_sec * NSEC_PER_SEC + current.tv_nsec;
 }
 
+static uint64_t anv_get_absolute_timeout(uint64_t timeout)
+{
+   if (timeout == 0)
+  return 0;
+   uint64_t current_time = gettime_ns();
+   uint64_t max_timeout = (uint64_t) INT64_MAX - current_time;
+
+   timeout = MIN2(max_timeout, timeout);
+
+   return (current_time + timeout);
+}
+
+static int64_t anv_get_relative_timeout(uint64_t abs_timeout)
+{
+   uint64_t now = gettime_ns();
+
+   if (abs_timeout < now)
+  return 0;
+   return abs_timeout - now;
+}
+
 static VkResult
 anv_wait_for_syncobj_fences(struct anv_device *device,
 uint32_t fenceCount,
 const VkFence *pFences,
 bool waitAll,
-uint64_t _timeout)
+uint64_t abs_timeout_ns)
 {
uint32_t *syncobjs = vk_zalloc(&device->alloc,
   sizeof(*syncobjs) * fenceCount, 8,
@@ -484,19 +505,6 @@ anv_wait_for_syncobj_fences(struct anv_device *device,
   syncobjs[i] = impl->syncobj;
}
 
-   int64_t abs_timeout_ns = 0;
-   if (_timeout > 0) {
-  uint64_t current_ns = gettime_ns();
-
-  /* Add but saturate to INT32_MAX */
-  if (current_ns + _timeout < current_ns)
- abs_timeout_ns = INT64_MAX;
-  else if (current_ns + _timeout > INT64_MAX)
- abs_timeout_ns = INT64_MAX;
-  else
- abs_timeout_ns = current_ns + _timeout;
-   }
-
/* The gem_syncobj_wait ioctl may return early due to an inherent
 * limitation in the way it computes timeouts.  Loop until we've actually
 * passed the timeout.
@@ -539,7 +547,7 @@ anv_wait_for_bo_fences(struct anv_device *device,
 * best we can do is to clamp the timeout to INT64_MAX.  This limits the
 * maximum timeout from 584 years to 292 years - likely not a big deal.
 */
-   int64_t timeout = MIN2(_timeout, INT64_MAX);
+   int64_t timeout = MIN2(_timeout, (uint64_t) INT64_MAX);
 
VkResult result = VK_SUCCESS;
uint32_t pending_fences = fenceCount;
@@ -665,6 +673,67 @@ done:
return result;
 }
 
+static VkResult
+anv_wait_for_fences(struct anv_device *device,
+uint32_t fenceCount,
+const VkFence *pFences,
+bool waitAll,
+uint64_t abs_timeout)
+{
+   VkResult result = VK_SUCCESS;
+
+   if (fenceCount <= 1 || waitAll) {
+  for (uint32_t i = 0; i < fenceCount; i++) {
+ ANV_FROM_HANDLE(anv_fence, fence, pFences[i]);
+ switch (fence->permanent.type) {
+ case ANV_FENCE_TYPE_BO:
+result = anv_wait_for_bo_fences(
+   device, 1, &pFences[i], true,
+   anv_get_relative_timeout(abs_timeout));
+break;
+ case ANV_FENCE_TYPE_SYNCOBJ:
+result = anv_wait_for_syncobj_fences(device, 1, &pFences[i],
+ true, abs_timeout);
+break;
+ case ANV_FENCE_TYPE_NONE:
+result = VK_SUCCESS;
+break;
+ }
+ if (result != VK_SUCCESS)
+return result;
+  }
+   } else {
+  do {
+ for (uint32_t i = 0; i < fenceCount; i++) {
+if (anv_wait_for_fences(device, 1, &pFences[i], true, 0) == 
VK_SUCCESS)
+   return VK_SUCCESS;
+ }
+  } while (gettime_ns() < abs_timeout);
+  result = VK_TIMEOUT;
+   }
+   return result;
+}
+
+static bool anv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
+{
+   for (uint32_t i = 0; i < fenceCount; ++i) {
+  ANV_FROM_HANDLE(anv_fence, fence, pFences[i]);
+

[Mesa-dev] [PATCH mesa 2/4] vulkan: add VK_EXT_display_control [v8]

2018-06-20 Thread Keith Packard 
This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.

v2: Remove DRM_CRTC_SEQUENCE_FIRST_PIXEL_OUT flag. This has
been removed from the proposed kernel API.

Add NULL parameter to drmCrtcQueueSequence ioctl as we
don't care what sequence the event was actually queued to.

v3: Adapt to pthread clock switch to MONOTONIC

v4: Fix scope for wsi_display_mode andwsi_display_connector allocs

Suggested-by: Jason Ekstrand 

v5: Adopt Jason Ekstrand's coding conventions

Declare variables at first use, eliminate extra whitespace between
types and names. Wrap lines to 80 columns.

Use wsi_rel_to_abs_time helper function to convert relative
timeouts to absolute timeouts without causing overflow.

Suggested-by: Jason Ekstrand 

v6:
Change WSI fence wait function to return VkResult instead of
bool. This makes the meaning of the return value easier to
understand, and allows for the indication of failure.

Also change the WSI fence wait function to take only absolute
timeouts and not provide an option for a relative timeout. No
users wanted relative timeouts, and it's simpler if that option
isn't available.

Terminate the DPMS property loop once we've found the property.

Assert that the fence hasn't already been destroyed in
wsi_display_fence_destroy.

Rearrange the event handler function order in the file to place
routines in an easier to find order.

Suggested-by: Jason Ekstrand 

v7:
Adapt to API changes for surface_get_capabilities

v8:
Use wsi->alloc in register_display_event so that callers
don't have to dig out an allocator for us.

Signed-off-by: Keith Packard 
---
 src/vulkan/wsi/wsi_common.h |  10 +
 src/vulkan/wsi/wsi_common_display.c | 329 +++-
 src/vulkan/wsi/wsi_common_display.h |  29 +++
 3 files changed, 366 insertions(+), 2 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common.h b/src/vulkan/wsi/wsi_common.h
index 07d5e8353b0..33e4f849ac9 100644
--- a/src/vulkan/wsi/wsi_common.h
+++ b/src/vulkan/wsi/wsi_common.h
@@ -73,6 +73,16 @@ struct wsi_surface_supported_counters {
const void *pNext;
 
VkSurfaceCounterFlagsEXT supported_surface_counters;
+
+};
+
+struct wsi_fence {
+   VkDevice device;
+   const struct wsi_device  *wsi_device;
+   VkDisplayKHR display;
+   const VkAllocationCallbacks  *alloc;
+   VkResult (*wait)(struct wsi_fence *fence, uint64_t 
abs_timeout);
+   void (*destroy)(struct wsi_fence *fence);
 };
 
 struct wsi_interface;
diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index 01150ffbb1b..c786d8befe5 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -79,6 +79,7 @@ typedef struct wsi_display_connector {
struct list_head display_modes;
wsi_display_mode *current_mode;
drmModeModeInfo  current_drm_mode;
+   uint32_t dpms_property;
 #ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT
xcb_randr_output_t   output;
 #endif
@@ -132,6 +133,15 @@ struct wsi_display_swapchain {
struct wsi_display_image images[0];
 };
 
+struct wsi_display_fence {
+   struct wsi_fence base;
+   bool event_received;
+   bool destroyed;
+   uint64_t sequence;
+};
+
+static uint64_t fence_sequence;
+
 ICD_DEFINE_NONDISP_HANDLE_CASTS(wsi_display_mode, VkDisplayModeKHR)
 ICD_DEFINE_NONDISP_HANDLE_CASTS(wsi_display_connector, VkDisplayKHR)
 
@@ -307,6 +317,19 @@ wsi_display_get_connector(struct wsi_device *wsi_device,
 
connector->connected = drm_connector->connection != DRM_MODE_DISCONNECTED;
 
+   /* Look for a DPMS property if we haven't already found one */
+   for (int p = 0; connector->dpms_property == 0 && p < 
drm_connector->count_props; p++) {
+  drmModePropertyPtr prop = drmModeGetProperty(wsi->fd,
+   drm_connector->props[p]);
+  if (!prop)
+ continue;
+  if (prop->flags & DRM_MODE_PROP_ENUM) {
+ if (!strcmp(prop->name, "DPMS"))
+connector->dpms_property = drm_connector->props[p];
+  }
+  drmModeFreeProperty(prop);
+   }
+
/* Mark all connector modes as invalid */
wsi_display_invalidate_connector_modes(wsi_device, connector);
 
@@ -673,15 +696,37 @@ wsi_display_surface_get_capabilities(VkIcdSurfaceBase 
*surface_base,
return VK_SUCCESS;
 }
 
+static VkResult
+wsi_display_surface_get_surface_counters(
+   VkIcdSurfaceBase *surface_base,
+   VkSurfaceCounterFlagsEXT *counters)
+{
+   *counters = VK_SURFACE_COUNTER_VBLANK_EXT;
+   return VK_SUCCESS;
+}
+
 static VkResult
 wsi_display_surface_get_capabilities2(VkIcdSurfaceBase *i

[Mesa-dev] [PATCH mesa 3/4] anv: add VK_EXT_display_control to anv driver [v4]

2018-06-20 Thread Keith Packard 
This extension provides fences and frame count information to direct
display contexts. It uses new kernel ioctls to provide 64-bits of
vblank sequence and nanosecond resolution.

v2: Adopt Jason Ekstrand's coding conventions

Declare variables at first use, eliminate extra whitespace between
types and names. Wrap lines to 80 columns.

Add extension to list in alphabetical order

Suggested-by: Jason Ekstrand 

v3: Adapt to WSI fence API change. It now returns VkResult and
no longer has an option for relative timeouts.

v4: wsi_register_display_event and wsi_register_device_event now
use the default allocator when NULL is provided, so remove the
computation of 'alloc' here.

Signed-off-by: Keith Packard 
---
 src/intel/vulkan/anv_extensions.py |  1 +
 src/intel/vulkan/anv_private.h |  4 ++
 src/intel/vulkan/anv_queue.c   | 18 +++
 src/intel/vulkan/anv_wsi_display.c | 85 ++
 4 files changed, 108 insertions(+)

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index ecef1b254bf..0f99f58ecb1 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -113,6 +113,7 @@ EXTENSIONS = [
 Extension('VK_EXT_acquire_xlib_display',  1, 
'VK_USE_PLATFORM_XLIB_XRANDR_EXT'),
 Extension('VK_EXT_debug_report',  8, True),
 Extension('VK_EXT_direct_mode_display',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
+Extension('VK_EXT_display_control',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_display_surface_counter',   1, 
'VK_USE_PLATFORM_DISPLAY_KHR'),
 Extension('VK_EXT_external_memory_dma_buf',   1, True),
 Extension('VK_EXT_global_priority',   1,
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index edc5317bac4..510471da602 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2134,6 +2134,7 @@ enum anv_fence_type {
ANV_FENCE_TYPE_NONE = 0,
ANV_FENCE_TYPE_BO,
ANV_FENCE_TYPE_SYNCOBJ,
+   ANV_FENCE_TYPE_WSI,
 };
 
 enum anv_bo_fence_state {
@@ -2168,6 +2169,9 @@ struct anv_fence_impl {
 
   /** DRM syncobj handle for syncobj-based fences */
   uint32_t syncobj;
+
+  /** WSI fence */
+  struct wsi_fence *fence_wsi;
};
 };
 
diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index 6e275629e14..e0c0a42069f 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -324,6 +324,10 @@ anv_fence_impl_cleanup(struct anv_device *device,
   anv_gem_syncobj_destroy(device, impl->syncobj);
   break;
 
+   case ANV_FENCE_TYPE_WSI:
+  impl->fence_wsi->destroy(impl->fence_wsi);
+  break;
+
default:
   unreachable("Invalid fence type");
}
@@ -673,6 +677,17 @@ done:
return result;
 }
 
+static VkResult
+anv_wait_for_wsi_fence(struct anv_device *device,
+   const VkFence _fence,
+   uint64_t abs_timeout)
+{
+   ANV_FROM_HANDLE(anv_fence, fence, _fence);
+   struct anv_fence_impl *impl = &fence->permanent;
+
+   return impl->fence_wsi->wait(impl->fence_wsi, abs_timeout);
+}
+
 static VkResult
 anv_wait_for_fences(struct anv_device *device,
 uint32_t fenceCount,
@@ -695,6 +710,9 @@ anv_wait_for_fences(struct anv_device *device,
 result = anv_wait_for_syncobj_fences(device, 1, &pFences[i],
  true, abs_timeout);
 break;
+ case ANV_FENCE_TYPE_WSI:
+result = anv_wait_for_wsi_fence(device, pFences[i], abs_timeout);
+break;
  case ANV_FENCE_TYPE_NONE:
 result = VK_SUCCESS;
 break;
diff --git a/src/intel/vulkan/anv_wsi_display.c 
b/src/intel/vulkan/anv_wsi_display.c
index ed679e85e13..6e1cb43aa35 100644
--- a/src/intel/vulkan/anv_wsi_display.c
+++ b/src/intel/vulkan/anv_wsi_display.c
@@ -174,3 +174,88 @@ anv_GetRandROutputDisplayEXT(VkPhysicalDevice  
physical_device,
display);
 }
 #endif /* VK_USE_PLATFORM_XLIB_XRANDR_EXT */
+
+/* VK_EXT_display_control */
+
+VkResult
+anv_DisplayPowerControlEXT(VkDevice_device,
+VkDisplayKHRdisplay,
+const VkDisplayPowerInfoEXT *display_power_info)
+{
+   ANV_FROM_HANDLE(anv_device, device, _device);
+
+   return wsi_display_power_control(
+  _device, &device->instance->physicalDevice.wsi_device,
+  display, display_power_info);
+}
+
+VkResult
+anv_RegisterDeviceEventEXT(VkDevice _device,
+const VkDeviceEventInfoEXT *device_event_info,
+const VkAllocationCallbacks *allocator,
+VkFence *_fence)
+{
+   ANV_FROM_HANDLE(anv_device, device, _device);
+

Re: [Mesa-dev] [PATCH] st/nir: Disable varying packing when doing transform feedback.

2018-06-20 Thread Timothy Arceri 

nir_compact_varyings() is meant to skip over varyings used by xfb:

 /* We can't repack xfb varyings. */
 if (var->data.always_active_io)
continue;

Any idea why that isn't working in this case?

On 21/06/18 06:30, Eric Anholt wrote:

If one of the TF variables got varying-packed, it would end up with a new
driver_location, despite the pipe_stream_output already being set up for
the old driver location.  This left the gallium driver with no way to work
back to what varying was referenced by pipe_stream_output.

Fixes these tests on V3D:
dEQP-GLES3.functional.transform_feedback.random.separate.points.3
dEQP-GLES3.functional.transform_feedback.random.separate.points.7
dEQP-GLES3.functional.transform_feedback.random.separate.points.9
dEQP-GLES3.functional.transform_feedback.random.separate.triangles.3
dEQP-GLES3.functional.transform_feedback.random.separate.triangles.8
---
  src/mesa/state_tracker/st_glsl_to_nir.cpp | 10 +-
  1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index d24944c6af51..6d19bb0dfb8a 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -739,7 +739,15 @@ st_link_nir(struct gl_context *ctx,
shader->Program->info = nir->info;
  
if (prev != -1) {

- 
nir_compact_varyings(shader_program->_LinkedShaders[prev]->Program->nir,
+ struct gl_program *prev_shader =
+shader_program->_LinkedShaders[prev]->Program;
+
+ /* We can't use nir_compact_varyings with transform feedback, since
+  * the pipe_stream_output->output_register field is based on the
+  * pre-compacted driver_locations.
+  */
+ if (!prev_shader->sh.LinkedTransformFeedback)
+
nir_compact_varyings(shader_program->_LinkedShaders[prev]->Program->nir,
nir, ctx->API != API_OPENGL_COMPAT);
}
prev = i;


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[Mesa-dev] [Bug 106980] Basemark GPU vulkan benchmark fails.

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106980

--- Comment #1 from Bas Nieuwenhuizen  ---
with some print debugging, it looks like the failing validate is here:

https://gitlab.freedesktop.org/mesa/mesa/blob/master/src/amd/vulkan/radv_shader.c#L233

which is directly after spirv_to_nir. I think it is a reasonable assumption
that this is a spirv_to_nir bug.

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[Mesa-dev] [Bug 106980] Basemark GPU vulkan benchmark fails.

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106980

Bas Nieuwenhuizen  changed:

   What|Removed |Added

  Component|Drivers/Vulkan/radeon   |Drivers/Vulkan/Common
 QA Contact|mesa-dev@lists.freedesktop. |
   |org |
 CC||airl...@freedesktop.org,
   ||chadvers...@chromium.org,
   ||dan...@fooishbar.org,
   ||ja...@jlekstrand.net

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[Mesa-dev] [Bug 106980] Basemark GPU vulkan benchmark fails.

2018-06-20 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=106980

--- Comment #2 from Bas Nieuwenhuizen  ---
Created attachment 140254
  --> https://bugs.freedesktop.org/attachment.cgi?id=140254&action=edit
Miscompiled shader

Attached is the failing shader. spirv2nir is enough to trigger if you add a
nir_validate_shader call at the end.

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Re: [Mesa-dev] [PATCH v2] anv, radv: Add support for VK_KHR_get_display_properties2

2018-06-20 Thread Jordan Justen 
features.txt? It looks like some others have been missed recently.

-Jordan

On 2018-06-20 08:07:20, Jason Ekstrand wrote:
> Cc: Keith Packard 
> ---
>  src/amd/vulkan/radv_extensions.py   |   1 +
>  src/amd/vulkan/radv_wsi_display.c   |  57 +
>  src/intel/vulkan/anv_extensions.py  |   1 +
>  src/intel/vulkan/anv_wsi_display.c  |  56 +
>  src/vulkan/wsi/wsi_common_display.c | 175 +---
>  src/vulkan/wsi/wsi_common_display.h |  27 +
>  6 files changed, 301 insertions(+), 16 deletions(-)
> 
> diff --git a/src/amd/vulkan/radv_extensions.py 
> b/src/amd/vulkan/radv_extensions.py
> index 65ce7349016..5eb63a7d5dc 100644
> --- a/src/amd/vulkan/radv_extensions.py
> +++ b/src/amd/vulkan/radv_extensions.py
> @@ -66,6 +66,7 @@ EXTENSIONS = [
>  Extension('VK_KHR_external_semaphore',1, 
> 'device->rad_info.has_syncobj'),
>  Extension('VK_KHR_external_semaphore_capabilities',   1, True),
>  Extension('VK_KHR_external_semaphore_fd', 1, 
> 'device->rad_info.has_syncobj'),
> +Extension('VK_KHR_get_display_properties2',   1, 
> 'VK_USE_PLATFORM_DISPLAY_KHR'),
>  Extension('VK_KHR_get_memory_requirements2',  1, True),
>  Extension('VK_KHR_get_physical_device_properties2',   1, True),
>  Extension('VK_KHR_get_surface_capabilities2', 1, 
> 'RADV_HAS_SURFACE'),
> diff --git a/src/amd/vulkan/radv_wsi_display.c 
> b/src/amd/vulkan/radv_wsi_display.c
> index 84431019dbb..764180ec7b5 100644
> --- a/src/amd/vulkan/radv_wsi_display.c
> +++ b/src/amd/vulkan/radv_wsi_display.c
> @@ -56,6 +56,20 @@ 
> radv_GetPhysicalDeviceDisplayPropertiesKHR(VkPhysicalDevice physical_device,
> properties);
>  }
>  
> +VkResult
> +radv_GetPhysicalDeviceDisplayProperties2KHR(VkPhysicalDevice physical_device,
> +uint32_t *property_count,
> +VkDisplayProperties2KHR 
> *properties)
> +{
> +   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
> +
> +   return wsi_display_get_physical_device_display_properties2(
> +   physical_device,
> +   &pdevice->wsi_device,
> +   property_count,
> +   properties);
> +}
> +
>  VkResult
>  radv_GetPhysicalDeviceDisplayPlanePropertiesKHR(
> VkPhysicalDevice physical_device,
> @@ -71,6 +85,21 @@ radv_GetPhysicalDeviceDisplayPlanePropertiesKHR(
> properties);
>  }
>  
> +VkResult
> +radv_GetPhysicalDeviceDisplayPlaneProperties2KHR(
> +   VkPhysicalDevice physical_device,
> +   uint32_t *property_count,
> +   VkDisplayPlaneProperties2KHR *properties)
> +{
> +   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
> +
> +   return wsi_display_get_physical_device_display_plane_properties2(
> +   physical_device,
> +   &pdevice->wsi_device,
> +   property_count,
> +   properties);
> +}
> +
>  VkResult
>  radv_GetDisplayPlaneSupportedDisplaysKHR(VkPhysicalDevice physical_device,
>   uint32_t plane_index,
> @@ -103,6 +132,21 @@ radv_GetDisplayModePropertiesKHR(VkPhysicalDevice 
> physical_device,
>properties);
>  }
>  
> +VkResult
> +radv_GetDisplayModeProperties2KHR(VkPhysicalDevice physical_device,
> +  VkDisplayKHR display,
> +  uint32_t *property_count,
> +  VkDisplayModeProperties2KHR *properties)
> +{
> +   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
> +
> +   return wsi_display_get_display_mode_properties2(physical_device,
> +   &pdevice->wsi_device,
> +   display,
> +   property_count,
> +   properties);
> +}
> +
>  VkResult
>  radv_CreateDisplayModeKHR(VkPhysicalDevice physical_device,
>VkDisplayKHR display,
> @@ -135,6 +179,19 @@ radv_GetDisplayPlaneCapabilitiesKHR(VkPhysicalDevice 
> physical_device,
>   capabilities);
>  }
>  
> +VkResult
> +radv_GetDisplayPlaneCapabilities2KHR(VkPhysicalDevice physical_device,
> + const VkDisplayPlaneInfo2KHR 
> *pDisplayPlaneInfo,
> + VkDisplayPlaneCapabilities2KHR 
> *capabilities)
> +{
> +   RADV_FROM_HANDLE(radv_physical_device, pdevice, physical_device);
> +
> +   return wsi_get_display_plane_capabilities2(physical_device,
> +  &pdevice->wsi_device,
> +  pDisplayPlaneInfo,
> +

[Mesa-dev] [PATCH 1/2] mesa: add ARB_viewport_array display list support

2018-06-20 Thread Timothy Arceri 
---
 src/mesa/main/dlist.c | 211 ++
 1 file changed, 211 insertions(+)

diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index 57ece6c30e0..8b1ddb05038 100644
--- a/src/mesa/main/dlist.c
+++ b/src/mesa/main/dlist.c
@@ -290,6 +290,15 @@ typedef enum
OPCODE_TRANSLATE,
OPCODE_VIEWPORT,
OPCODE_WINDOW_POS,
+   /* ARB_viewport_array */
+   OPCODE_VIEWPORT_ARRAY_V,
+   OPCODE_VIEWPORT_INDEXED_F,
+   OPCODE_VIEWPORT_INDEXED_FV,
+   OPCODE_SCISSOR_ARRAY_V,
+   OPCODE_SCISSOR_INDEXED,
+   OPCODE_SCISSOR_INDEXED_V,
+   OPCODE_DEPTH_ARRAY_V,
+   OPCODE_DEPTH_INDEXED,
/* GL_ARB_multitexture */
OPCODE_ACTIVE_TEXTURE,
/* GL_ARB_texture_compression */
@@ -1164,6 +1173,9 @@ _mesa_delete_list(struct gl_context *ctx, struct 
gl_display_list *dlist)
  case OPCODE_PIXEL_MAP:
 free(get_pointer(&n[3]));
 break;
+ case OPCODE_VIEWPORT_ARRAY_V:
+ case OPCODE_SCISSOR_ARRAY_V:
+ case OPCODE_DEPTH_ARRAY_V:
  case OPCODE_UNIFORM_SUBROUTINES:
  case OPCODE_WINDOW_RECTANGLES:
 free(get_pointer(&n[3]));
@@ -4612,6 +4624,154 @@ save_Viewport(GLint x, GLint y, GLsizei width, GLsizei 
height)
}
 }
 
+static void GLAPIENTRY
+save_ViewportIndexedf(GLuint index, GLfloat x, GLfloat y, GLfloat width,
+  GLfloat height)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   Node *n;
+   ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
+   n = alloc_instruction(ctx, OPCODE_VIEWPORT_INDEXED_F, 5);
+   if (n) {
+  n[1].ui = index;
+  n[2].f = x;
+  n[3].f = y;
+  n[4].f = width;
+  n[5].f = height;
+   }
+   if (ctx->ExecuteFlag) {
+  CALL_ViewportIndexedf(ctx->Exec, (index, x, y, width, height));
+   }
+}
+
+static void GLAPIENTRY
+save_ViewportIndexedfv(GLuint index, const GLfloat *v)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   Node *n;
+   ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
+   n = alloc_instruction(ctx, OPCODE_VIEWPORT_INDEXED_FV, 5);
+   if (n) {
+  n[1].ui = index;
+  n[2].f = v[0];
+  n[3].f = v[1];
+  n[4].f = v[2];
+  n[5].f = v[3];
+   }
+   if (ctx->ExecuteFlag) {
+  CALL_ViewportIndexedfv(ctx->Exec, (index, v));
+   }
+}
+
+static void GLAPIENTRY
+save_ViewportArrayv(GLuint first, GLsizei count, const GLfloat *v)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   Node *n;
+   ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
+   n = alloc_instruction(ctx, OPCODE_VIEWPORT_ARRAY_V, 2 + POINTER_DWORDS);
+   if (n) {
+  n[1].ui = first;
+  n[2].si = count;
+  save_pointer(&n[3], memdup(v, count * 4 * sizeof(GLfloat)));
+   }
+   if (ctx->ExecuteFlag) {
+  CALL_ViewportArrayv(ctx->Exec, (first, count, v));
+   }
+}
+
+static void GLAPIENTRY
+save_ScissorIndexed(GLuint index, GLint left, GLint bottom, GLsizei width,
+GLsizei height)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   Node *n;
+   ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
+   n = alloc_instruction(ctx, OPCODE_SCISSOR_INDEXED, 5);
+   if (n) {
+  n[1].ui = index;
+  n[2].i = left;
+  n[3].i = bottom;
+  n[4].si = width;
+  n[5].si = height;
+   }
+   if (ctx->ExecuteFlag) {
+  CALL_ScissorIndexed(ctx->Exec, (index, left, bottom, width, height));
+   }
+}
+
+static void GLAPIENTRY
+save_ScissorIndexedv(GLuint index, const GLint *v)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   Node *n;
+   ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
+   n = alloc_instruction(ctx, OPCODE_SCISSOR_INDEXED_V, 5);
+   if (n) {
+  n[1].ui = index;
+  n[2].i = v[0];
+  n[3].i = v[1];
+  n[4].si = v[2];
+  n[5].si = v[3];
+   }
+   if (ctx->ExecuteFlag) {
+  CALL_ScissorIndexedv(ctx->Exec, (index, v));
+   }
+}
+
+static void GLAPIENTRY
+save_ScissorArrayv(GLuint first, GLsizei count, const GLint *v)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   Node *n;
+   ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
+   n = alloc_instruction(ctx, OPCODE_SCISSOR_ARRAY_V, 2 + POINTER_DWORDS);
+   if (n) {
+  n[1].ui = first;
+  n[2].si = count;
+  save_pointer(&n[3], memdup(v, count * 4 * sizeof(GLint)));
+   }
+   if (ctx->ExecuteFlag) {
+  CALL_ScissorArrayv(ctx->Exec, (first, count, v));
+   }
+}
+
+static void GLAPIENTRY
+save_DepthRangeIndexed(GLuint index, GLclampd n, GLclampd f)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   Node *node;
+   ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
+   node = alloc_instruction(ctx, OPCODE_DEPTH_INDEXED, 3);
+   if (node) {
+  node[1].ui = index;
+  /* Mesa stores these as floats internally so we deliberately convert
+   * them to a float here.
+   */
+  node[2].f = n;
+  node[3].f = f;
+   }
+   if (ctx->ExecuteFlag) {
+  CALL_DepthRangeIndexed(ctx->Exec, (index, n, f));
+   }
+}
+
+static void GLAPIENTRY
+save_DepthRangeArrayv(GLuint first, GLsizei count, const GLclampd *v)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   Node *n;
+   ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
+   n = alloc_instruction

[Mesa-dev] [PATCH 2/2] mesa: enable ARB_viewport_array in compat profile

2018-06-20 Thread Timothy Arceri 
---
 src/mapi/glapi/gen/apiexec.py| 16 
 src/mesa/main/extensions_table.h |  2 +-
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/mapi/glapi/gen/apiexec.py b/src/mapi/glapi/gen/apiexec.py
index e69c6b4df16..1a91785d375 100644
--- a/src/mapi/glapi/gen/apiexec.py
+++ b/src/mapi/glapi/gen/apiexec.py
@@ -131,14 +131,14 @@ functions = {
 #
 # Mesa does not support either of the geometry shader extensions, so
 # OpenGL 3.2 is required.
-"ViewportArrayv": exec_info(core=32, es2=31),
-"ViewportIndexedf": exec_info(core=32, es2=31),
-"ViewportIndexedfv": exec_info(core=32, es2=31),
-"ScissorArrayv": exec_info(core=32, es2=31),
-"ScissorIndexed": exec_info(core=32, es2=31),
-"ScissorIndexedv": exec_info(core=32, es2=31),
-"DepthRangeArrayv": exec_info(core=32),
-"DepthRangeIndexed": exec_info(core=32),
+"ViewportArrayv": exec_info(compatibility=32, core=32, es2=31),
+"ViewportIndexedf": exec_info(compatibility=32, core=32, es2=31),
+"ViewportIndexedfv": exec_info(compatibility=32, core=32, es2=31),
+"ScissorArrayv": exec_info(compatibility=32, core=32, es2=31),
+"ScissorIndexed": exec_info(compatibility=32, core=32, es2=31),
+"ScissorIndexedv": exec_info(compatibility=32, core=32, es2=31),
+"DepthRangeArrayv": exec_info(compatibility=32, core=32),
+"DepthRangeIndexed": exec_info(compatibility=32, core=32),
 # GetFloati_v also GL_ARB_shader_atomic_counters
 # GetDoublei_v also GL_ARB_shader_atomic_counters
 
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index eed5bc451d8..bc1f21a2926 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -182,7 +182,7 @@ EXT(ARB_vertex_program  , 
ARB_vertex_program
 EXT(ARB_vertex_shader   , ARB_vertex_shader
  , GLL, GLC,  x ,  x , 2002)
 EXT(ARB_vertex_type_10f_11f_11f_rev , ARB_vertex_type_10f_11f_11f_rev  
  , GLL, GLC,  x ,  x , 2013)
 EXT(ARB_vertex_type_2_10_10_10_rev  , ARB_vertex_type_2_10_10_10_rev   
  , GLL, GLC,  x ,  x , 2009)
-EXT(ARB_viewport_array  , ARB_viewport_array   
  ,  x , GLC,  x ,  x , 2010)
+EXT(ARB_viewport_array  , ARB_viewport_array   
  , GLL, GLC,  x ,  x , 2010)
 EXT(ARB_window_pos  , dummy_true   
  , GLL,  x ,  x ,  x , 2001)
 
 EXT(ATI_blend_equation_separate , EXT_blend_equation_separate  
  , GLL, GLC,  x ,  x , 2003)
-- 
2.17.1

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[Mesa-dev] [PATCH 3/2] mesa: expose some ARB_viewport_array dependent extensions in compat

2018-06-20 Thread Timothy Arceri 
---
 src/mesa/main/extensions_table.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index bc1f21a2926..b1ee0214d6c 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -16,7 +16,7 @@ EXT(AMD_seamless_cubemap_per_texture, 
AMD_seamless_cubemap_per_texture
 EXT(AMD_shader_stencil_export   , ARB_shader_stencil_export
  , GLL, GLC,  x ,  x , 2009)
 EXT(AMD_shader_trinary_minmax   , dummy_true   
  , GLL, GLC,  x ,  x , 2012)
 EXT(AMD_vertex_shader_layer , AMD_vertex_shader_layer  
  , GLL, GLC,  x ,  x , 2012)
-EXT(AMD_vertex_shader_viewport_index, AMD_vertex_shader_viewport_index 
  ,  x , GLC,  x ,  x , 2012)
+EXT(AMD_vertex_shader_viewport_index, AMD_vertex_shader_viewport_index 
  , GLL, GLC,  x ,  x , 2012)
 
 EXT(ANDROID_extension_pack_es31a, ANDROID_extension_pack_es31a 
  ,  x ,  x ,  x ,  31, 2014)
 
@@ -64,7 +64,7 @@ EXT(ARB_enhanced_layouts, 
ARB_enhanced_layouts
 EXT(ARB_explicit_attrib_location, ARB_explicit_attrib_location 
  , GLL, GLC,  x ,  x , 2009)
 EXT(ARB_explicit_uniform_location   , ARB_explicit_uniform_location
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_fragment_coord_conventions  , ARB_fragment_coord_conventions   
  , GLL, GLC,  x ,  x , 2009)
-EXT(ARB_fragment_layer_viewport , ARB_fragment_layer_viewport  
  ,  x , GLC,  x ,  x , 2012)
+EXT(ARB_fragment_layer_viewport , ARB_fragment_layer_viewport  
  , GLL, GLC,  x ,  x , 2012)
 EXT(ARB_fragment_program, ARB_fragment_program 
  , GLL,  x ,  x ,  x , 2002)
 EXT(ARB_fragment_program_shadow , ARB_fragment_program_shadow  
  , GLL,  x ,  x ,  x , 2003)
 EXT(ARB_fragment_shader , ARB_fragment_shader  
  , GLL, GLC,  x ,  x , 2002)
-- 
2.17.1

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[Mesa-dev] [PATCH] Plumb invariant output attrib thru TGSI

2018-06-20 Thread Robert Tarasov 
From: "Joe M. Kniss" 

Add support for glsl 'invariant' modifier for output data declarations.
Gallium drivers that use TGSI serialization currently loose invariant
modifiers in glsl shaders.

v2: use boolean for invariant instead of unsigned.

Change-Id: Ieac8639116def45233513b6867a847cf7fda2f55
Tested: chromiumos on qemu with virglrenderer.
---
 src/gallium/auxiliary/tgsi/tgsi_strings.c  |  2 ++
 src/gallium/auxiliary/tgsi/tgsi_strings.h  |  2 ++
 src/gallium/auxiliary/tgsi/tgsi_text.c | 18 ++
 src/gallium/auxiliary/tgsi/tgsi_ureg.c | 28 +++---
 src/gallium/auxiliary/tgsi/tgsi_ureg.h |  4 +++-
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp |  8 +--
 6 files changed, 46 insertions(+), 16 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c 
b/src/gallium/auxiliary/tgsi/tgsi_strings.c
index 4f28b49ce8a..434871273f2 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c
@@ -185,6 +185,8 @@ const char 
*tgsi_interpolate_locations[TGSI_INTERPOLATE_LOC_COUNT] =
"SAMPLE",
 };
 
+const char *tgsi_invariant_name = "INVARIANT";
+
 const char *tgsi_primitive_names[PIPE_PRIM_MAX] =
 {
"POINTS",
diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.h 
b/src/gallium/auxiliary/tgsi/tgsi_strings.h
index bb2d3458dde..20e3f7127f6 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.h
@@ -52,6 +52,8 @@ extern const char 
*tgsi_interpolate_names[TGSI_INTERPOLATE_COUNT];
 
 extern const char *tgsi_interpolate_locations[TGSI_INTERPOLATE_LOC_COUNT];
 
+extern const char *tgsi_invariant_name;
+
 extern const char *tgsi_primitive_names[PIPE_PRIM_MAX];
 
 extern const char *tgsi_fs_coord_origin_names[2];
diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c 
b/src/gallium/auxiliary/tgsi/tgsi_text.c
index 02241a66bfe..815b1ee65db 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -1586,10 +1586,6 @@ static boolean parse_declaration( struct translate_ctx 
*ctx )
 break;
  }
   }
-  if (i == TGSI_INTERPOLATE_COUNT) {
- report_error( ctx, "Expected semantic or interpolate attribute" );
- return FALSE;
-  }
}
 
cur = ctx->cur;
@@ -1609,6 +1605,20 @@ static boolean parse_declaration( struct translate_ctx 
*ctx )
   }
}
 
+   cur = ctx->cur;
+   eat_opt_white( &cur );
+   if (*cur == ',' && !is_vs_input) {
+  cur++;
+  eat_opt_white( &cur );
+  if (str_match_nocase_whole( &cur, tgsi_invariant_name )) {
+ decl.Declaration.Invariant = 1;
+ ctx->cur = cur;
+  } else {
+ report_error( ctx, "Expected semantic, interpolate attribute, or 
invariant ");
+ return FALSE;
+  }
+   }
+   
advance = tgsi_build_full_declaration(
   &decl,
   ctx->tokens_cur,
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c 
b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index 7d2b9af140d..f1bebe1e155 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -140,6 +140,7 @@ struct ureg_program
   unsigned first;
   unsigned last;
   unsigned array_id;
+  boolean invariant;
} output[UREG_MAX_OUTPUT];
unsigned nr_outputs, nr_output_regs;
 
@@ -427,7 +428,8 @@ ureg_DECL_output_layout(struct ureg_program *ureg,
 unsigned index,
 unsigned usage_mask,
 unsigned array_id,
-unsigned array_size)
+unsigned array_size,
+boolean invariant)
 {
unsigned i;
 
@@ -455,6 +457,7 @@ ureg_DECL_output_layout(struct ureg_program *ureg,
   ureg->output[i].first = index;
   ureg->output[i].last = index + array_size - 1;
   ureg->output[i].array_id = array_id;
+  ureg->output[i].invariant = invariant;
   ureg->nr_output_regs = MAX2(ureg->nr_output_regs, index + array_size);
   ureg->nr_outputs++;
}
@@ -480,7 +483,8 @@ ureg_DECL_output_masked(struct ureg_program *ureg,
 unsigned array_size)
 {
return ureg_DECL_output_layout(ureg, name, index, 0,
-  ureg->nr_output_regs, usage_mask, array_id, 
array_size);
+  ureg->nr_output_regs, usage_mask, array_id,
+  array_size, FALSE);
 }
 
 
@@ -1512,7 +1516,8 @@ emit_decl_semantic(struct ureg_program *ureg,
unsigned semantic_index,
unsigned streams,
unsigned usage_mask,
-   unsigned array_id)
+   unsigned array_id,
+   boolean invariant)
 {
union tgsi_any_token *out = get_tokens(ureg, DOMAIN_DECL, array_id ? 4 : 3);
 
@@ -1523,7 +1528,8 @@ emit_decl_semantic(struct ureg_program *ureg,
out[0].decl.UsageMask = usage_mask;
out[0].decl.Semantic = 1;

Re: [Mesa-dev] [PATCH 1/6] mesa: add Uniform*d support to display lists

2018-06-20 Thread Timothy Arceri 

On 20/06/18 15:16, Mathias Fröhlich wrote:

Hi,

It seems that dlist.c is getting popular again, but can't we generate
most of dlist.c using the api files?
Probably saves a lot of typing, copying and pasting in the long run.
Should also be less error prone in the long run.
Not that I think code generation is required, but I believe it would
help, especially as lots of that is already in place for generating
the api tables.


Yes I thought about this but the effort required to write/test any 
generation is too high vs the number of extensions left that require 
dlist support.


I've just sent a series to add ARB_viewport_array display list support, 
with that we have maybe 3 more extension to go for GL 4.5 support. As 
for errors I've been creating extensive piglit tests (which should be 
done either way) and I expect the code I'm adding to be as error free as 
any generated code would be.




There is one comment inline below.



On Wednesday, 20 June 2018 03:58:34 CEST Timothy Arceri wrote:

This is required so we can enable fp64 support in compat profile.
---
  src/mapi/glapi/gen/apiexec.py |  36 +--
  src/mesa/main/dlist.c | 493 ++
  2 files changed, 511 insertions(+), 18 deletions(-)

diff --git a/src/mapi/glapi/gen/apiexec.py b/src/mapi/glapi/gen/apiexec.py
index 20d6239ba14..00c80171274 100644
--- a/src/mapi/glapi/gen/apiexec.py
+++ b/src/mapi/glapi/gen/apiexec.py
@@ -85,24 +85,24 @@ functions = {
  # OpenGL 4.0 / GL_ARB_gpu_shader_fp64.  The extension spec says:
  #
  # "OpenGL 3.2 and GLSL 1.50 are required."
-"Uniform1d": exec_info(core=32),
-"Uniform2d": exec_info(core=32),
-"Uniform3d": exec_info(core=32),
-"Uniform4d": exec_info(core=32),
-"Uniform1dv": exec_info(core=32),
-"Uniform2dv": exec_info(core=32),
-"Uniform3dv": exec_info(core=32),
-"Uniform4dv": exec_info(core=32),
-"UniformMatrix2dv": exec_info(core=32),
-"UniformMatrix3dv": exec_info(core=32),
-"UniformMatrix4dv": exec_info(core=32),
-"UniformMatrix2x3dv": exec_info(core=32),
-"UniformMatrix2x4dv": exec_info(core=32),
-"UniformMatrix3x2dv": exec_info(core=32),
-"UniformMatrix3x4dv": exec_info(core=32),
-"UniformMatrix4x2dv": exec_info(core=32),
-"UniformMatrix4x3dv": exec_info(core=32),
-"GetUniformdv": exec_info(core=32),
+"Uniform1d": exec_info(compatibility=32, core=32),
+"Uniform2d": exec_info(compatibility=32, core=32),
+"Uniform3d": exec_info(compatibility=32, core=32),
+"Uniform4d": exec_info(compatibility=32, core=32),
+"Uniform1dv": exec_info(compatibility=32, core=32),
+"Uniform2dv": exec_info(compatibility=32, core=32),
+"Uniform3dv": exec_info(compatibility=32, core=32),
+"Uniform4dv": exec_info(compatibility=32, core=32),
+"UniformMatrix2dv": exec_info(compatibility=32, core=32),
+"UniformMatrix3dv": exec_info(compatibility=32, core=32),
+"UniformMatrix4dv": exec_info(compatibility=32, core=32),
+"UniformMatrix2x3dv": exec_info(compatibility=32,core=32),
+"UniformMatrix2x4dv": exec_info(compatibility=32, core=32),
+"UniformMatrix3x2dv": exec_info(compatibility=32, core=32),
+"UniformMatrix3x4dv": exec_info(compatibility=32, core=32),
+"UniformMatrix4x2dv": exec_info(compatibility=32, core=32),
+"UniformMatrix4x3dv": exec_info(compatibility=32, core=32),
+"GetUniformdv": exec_info(compatibility=32, core=32),
  
  # OpenGL 4.1 / GL_ARB_vertex_attrib_64bit.  The extension spec says:

  #
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index 4fc451000b5..b0fbc17d017 100644
--- a/src/mesa/main/dlist.c
+++ b/src/mesa/main/dlist.c
@@ -365,6 +365,25 @@ typedef enum
 OPCODE_UNIFORM_3UIV,
 OPCODE_UNIFORM_4UIV,
  
+   /* GL_ARB_gpu_shader_fp64 */

+   OPCODE_UNIFORM_1D,
+   OPCODE_UNIFORM_2D,
+   OPCODE_UNIFORM_3D,
+   OPCODE_UNIFORM_4D,
+   OPCODE_UNIFORM_1DV,
+   OPCODE_UNIFORM_2DV,
+   OPCODE_UNIFORM_3DV,
+   OPCODE_UNIFORM_4DV,
+   OPCODE_UNIFORM_MATRIX22D,
+   OPCODE_UNIFORM_MATRIX33D,
+   OPCODE_UNIFORM_MATRIX44D,
+   OPCODE_UNIFORM_MATRIX23D,
+   OPCODE_UNIFORM_MATRIX32D,
+   OPCODE_UNIFORM_MATRIX24D,
+   OPCODE_UNIFORM_MATRIX42D,
+   OPCODE_UNIFORM_MATRIX34D,
+   OPCODE_UNIFORM_MATRIX43D,
+
 /* OpenGL 4.0 / GL_ARB_tessellation_shader */
 OPCODE_PATCH_PARAMETER_I,
 OPCODE_PATCH_PARAMETER_FV_INNER,
@@ -606,6 +625,22 @@ union uint64_pair
  };
  
  
+union float64_pair

+{
+   GLdouble d;
+   GLfloat f[2];
+};


May be you want to use GLuint ui[2] instead of GLfloat f[2].
The reason is that you may end up with bit patterns that stem
from finite double values but generate NaN's or infs when split
into two floats in this way. Now if your application traps on NaN's
I am not sure if the move operation already traps.
If you use something integer values to transport arbitrary bit patterns
to compose doubles form those it is guaranteed not to trap in any case.


Right, I'll rework this thanks for

[Mesa-dev] [PATCH 4/4] ac/surface: disallow rotated micro tile mode

2018-06-20 Thread Marek Olšák 
From: Marek Olšák 

---
 src/amd/common/ac_surface.c | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 618b755afc7..6a335111314 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -429,20 +429,21 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
surf->htile_size = AddrHtileOut->htileBytes;
surf->htile_slice_size = AddrHtileOut->sliceSize;
surf->htile_alignment = AddrHtileOut->baseAlign;
}
}
 
return 0;
 }
 
 #define   G_009910_MICRO_TILE_MODE(x)  (((x) >> 0) & 0x03)
+#define V_009910_ADDR_SURF_THICK_MICRO_TILING   0x03
 #define   G_009910_MICRO_TILE_MODE_NEW(x)  (((x) >> 22) & 0x07)
 
 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
 const struct radeon_info *info)
 {
uint32_t tile_mode = 
info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
 
if (info->chip_class >= CIK)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
else
@@ -943,20 +944,31 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 
surf->htile_size = (total_pixels / htile_block_size) *
   htile_element_size;
surf->htile_size = align(surf->htile_size, 
surf->htile_alignment);
}
 
surf->is_linear = surf->u.legacy.level[0].mode == 
RADEON_SURF_MODE_LINEAR_ALIGNED;
surf->is_displayable = surf->is_linear ||
   surf->micro_tile_mode == 
RADEON_MICRO_MODE_DISPLAY ||
   surf->micro_tile_mode == 
RADEON_MICRO_MODE_ROTATED;
+
+   /* The rotated micro tile mode doesn't work if both CMASK and RB+ are
+* used at the same time. This case is not currently expected to occur
+* because we don't use rotated. Enforce this restriction on all chips
+* to facilitate testing.
+*/
+   if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) {
+   assert(!"rotate micro tile mode is unsupported");
+   return ADDR_ERROR;
+   }
+
return 0;
 }
 
 /* This is only called when expecting a tiled layout. */
 static int
 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
bool is_fmask, unsigned flags,
AddrSwizzleMode *swizzle_mode)
 {
@@ -1483,22 +1495,27 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
/* R = rotated. */
case ADDR_SW_256B_R:
case ADDR_SW_4KB_R:
case ADDR_SW_64KB_R:
case ADDR_SW_VAR_R:
case ADDR_SW_64KB_R_T:
case ADDR_SW_4KB_R_X:
case ADDR_SW_64KB_R_X:
case ADDR_SW_VAR_R_X:
-   surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED;
-   break;
+   /* The rotated micro tile mode doesn't work if both 
CMASK and RB+ are
+* used at the same time. This case is not currently 
expected to occur
+* because we don't use rotated. Enforce this 
restriction on all chips
+* to facilitate testing.
+*/
+   assert(!"rotate micro tile mode is unsupported");
+   return ADDR_ERROR;
 
/* Z = depth. */
case ADDR_SW_4KB_Z:
case ADDR_SW_64KB_Z:
case ADDR_SW_VAR_Z:
case ADDR_SW_64KB_Z_T:
case ADDR_SW_4KB_Z_X:
case ADDR_SW_64KB_Z_X:
case ADDR_SW_VAR_Z_X:
surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
-- 
2.17.1

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[Mesa-dev] [PATCH 2/4] radeonsi: handle non-clearable DCC buffers as MSAA resolve dst

2018-06-20 Thread Marek Olšák 
From: Marek Olšák 

This is reproducible on Stoney, but other chips may be affected too.

Cc 18.1 
---
 src/gallium/drivers/radeonsi/si_blit.c  | 5 +
 src/gallium/drivers/radeonsi/si_clear.c | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 1506d6ba8d1..23c543adbbf 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -1154,20 +1154,25 @@ static bool do_hardware_msaa_resolve(struct 
pipe_context *ctx,
/* Resolving into a surface with DCC is unsupported. Since
 * it's being overwritten anyway, clear it to uncompressed.
 * This is still the fastest codepath even with this clear.
 */
if (vi_dcc_enabled(dst, info->dst.level)) {
/* TODO: Implement per-level DCC clears for GFX9. */
if (sctx->chip_class >= GFX9 &&
info->dst.resource->last_level != 0)
goto resolve_to_temp;
 
+   /* This can happen with mipmapping. */
+   if (sctx->chip_class == VI &&
+   
!dst->surface.u.legacy.level[info->dst.level].dcc_fast_clear_size)
+   goto resolve_to_temp;
+
vi_dcc_clear_level(sctx, dst, info->dst.level,
   0x);
dst->dirty_level_mask &= ~(1 << info->dst.level);
}
 
/* Resolve directly from src to dst. */
si_do_CB_resolve(sctx, info, info->dst.resource,
 info->dst.level, info->dst.box.z, format);
return true;
}
diff --git a/src/gallium/drivers/radeonsi/si_clear.c 
b/src/gallium/drivers/radeonsi/si_clear.c
index 80a4a081672..050bbf3c181 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -470,21 +470,21 @@ static void si_do_fast_color_clear(struct si_context 
*sctx,
}
 
/* Try to clear DCC first, otherwise try CMASK. */
if (vi_dcc_enabled(tex, 0)) {
uint32_t reset_value;
bool eliminate_needed;
 
if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
continue;
 
-   /* This can only occur with MSAA. */
+   /* This can happen with mipmapping or MSAA. */
if (sctx->chip_class == VI &&

!tex->surface.u.legacy.level[level].dcc_fast_clear_size)
continue;
 
if 
(!vi_get_fast_clear_parameters(tex->buffer.b.b.format,
  fb->cbufs[i]->format,
  color, &reset_value,
  &eliminate_needed))
continue;
 
-- 
2.17.1

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[Mesa-dev] [PATCH O/4] RadeonSI fixes for Stoney

2018-06-20 Thread Marek Olšák 
These were all discovered on Stoney except for the last patch, which is a 
precaution.

Please review.

Thanks,
Marek
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[Mesa-dev] [PATCH 1/4] radeonsi: disable DCC MSAA for 128bpp formats on Stoney

2018-06-20 Thread Marek Olšák 
From: Marek Olšák 

Cc: 18.1 
---
 src/gallium/drivers/radeonsi/si_texture.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_texture.c 
b/src/gallium/drivers/radeonsi/si_texture.c
index b46208be252..05d5d1b8a6d 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -266,20 +266,25 @@ static int si_init_surface(struct si_screen *sscreen,
if (is_stencil)
flags |= RADEON_SURF_SBUFFER;
}
 
if (sscreen->info.chip_class >= VI &&
(ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC ||
 ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
 (ptex->nr_samples >= 2 && !sscreen->dcc_msaa_allowed)))
flags |= RADEON_SURF_DISABLE_DCC;
 
+   /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
+   if (sscreen->info.family == CHIP_STONEY &&
+   bpe == 16 && ptex->nr_samples >= 2)
+   flags |= RADEON_SURF_DISABLE_DCC;
+
/* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
if (sscreen->info.chip_class == VI &&
num_color_samples >= 4 &&
ptex->array_size > 1)
flags |= RADEON_SURF_DISABLE_DCC;
 
/* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
if (sscreen->info.chip_class >= GFX9 &&
num_color_samples >= 4)
flags |= RADEON_SURF_DISABLE_DCC;
-- 
2.17.1

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[Mesa-dev] [PATCH 3/4] radeonsi: fix occlusion queries with 16x AA without FBO attachments on Stoney

2018-06-20 Thread Marek Olšák 
From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_state.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index cfe32bc7f5e..a7377f38745 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1371,23 +1371,31 @@ static void si_emit_db_render_state(struct si_context 
*sctx)
S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
}
 
/* DB_COUNT_CONTROL (occlusion queries) */
if (sctx->num_occlusion_queries > 0 &&
!sctx->occlusion_queries_disabled) {
bool perfect = sctx->num_perfect_occlusion_queries > 0;
 
if (sctx->chip_class >= CIK) {
+   unsigned log_sample_rate = 
sctx->framebuffer.log_samples;
+
+   /* Stoney doesn't increment occlusion query counters
+* if the sample rate is 16x. Use 8x sample rate 
instead.
+*/
+   if (sctx->family == CHIP_STONEY)
+   log_sample_rate = MIN2(log_sample_rate, 3);
+
db_count_control =
S_028004_PERFECT_ZPASS_COUNTS(perfect) |
-   
S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
+   S_028004_SAMPLE_RATE(log_sample_rate) |
S_028004_ZPASS_ENABLE(1) |
S_028004_SLICE_EVEN_ENABLE(1) |
S_028004_SLICE_ODD_ENABLE(1);
} else {
db_count_control =
S_028004_PERFECT_ZPASS_COUNTS(perfect) |

S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
}
} else {
/* Disable occlusion queries. */
-- 
2.17.1

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[Mesa-dev] [PATCH] mesa: fix glGetInteger64v for arrays of integers

2018-06-20 Thread Marek Olšák 
From: Marek Olšák 

Cc: 18.1 
---
 src/mesa/main/get.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 772ca00da1f..db0079beb51 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -1996,21 +1996,21 @@ _mesa_GetInteger64v(GLenum pname, GLint64 *params)
case TYPE_ENUM:
   params[0] = ((GLint *) p)[0];
   break;
 
case TYPE_ENUM16:
   params[0] = ((GLenum16 *) p)[0];
   break;
 
case TYPE_INT_N:
   for (i = 0; i < v.value_int_n.n; i++)
- params[i] = INT_TO_BOOLEAN(v.value_int_n.ints[i]);
+ params[i] = v.value_int_n.ints[i];
   break;
 
case TYPE_UINT_4:
   params[3] = ((GLuint *) p)[3];
case TYPE_UINT_3:
   params[2] = ((GLuint *) p)[2];
case TYPE_UINT_2:
   params[1] = ((GLuint *) p)[1];
case TYPE_UINT:
   params[0] = ((GLuint *) p)[0];
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] Plumb invariant output attrib thru TGSI

2018-06-20 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek

On Wed, Jun 20, 2018 at 8:55 PM, Robert Tarasov
 wrote:
> From: "Joe M. Kniss" 
>
> Add support for glsl 'invariant' modifier for output data declarations.
> Gallium drivers that use TGSI serialization currently loose invariant
> modifiers in glsl shaders.
>
> v2: use boolean for invariant instead of unsigned.
>
> Change-Id: Ieac8639116def45233513b6867a847cf7fda2f55
> Tested: chromiumos on qemu with virglrenderer.
> ---
>  src/gallium/auxiliary/tgsi/tgsi_strings.c  |  2 ++
>  src/gallium/auxiliary/tgsi/tgsi_strings.h  |  2 ++
>  src/gallium/auxiliary/tgsi/tgsi_text.c | 18 ++
>  src/gallium/auxiliary/tgsi/tgsi_ureg.c | 28 +++---
>  src/gallium/auxiliary/tgsi/tgsi_ureg.h |  4 +++-
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp |  8 +--
>  6 files changed, 46 insertions(+), 16 deletions(-)
>
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c 
> b/src/gallium/auxiliary/tgsi/tgsi_strings.c
> index 4f28b49ce8a..434871273f2 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_strings.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c
> @@ -185,6 +185,8 @@ const char 
> *tgsi_interpolate_locations[TGSI_INTERPOLATE_LOC_COUNT] =
> "SAMPLE",
>  };
>
> +const char *tgsi_invariant_name = "INVARIANT";
> +
>  const char *tgsi_primitive_names[PIPE_PRIM_MAX] =
>  {
> "POINTS",
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.h 
> b/src/gallium/auxiliary/tgsi/tgsi_strings.h
> index bb2d3458dde..20e3f7127f6 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_strings.h
> +++ b/src/gallium/auxiliary/tgsi/tgsi_strings.h
> @@ -52,6 +52,8 @@ extern const char 
> *tgsi_interpolate_names[TGSI_INTERPOLATE_COUNT];
>
>  extern const char *tgsi_interpolate_locations[TGSI_INTERPOLATE_LOC_COUNT];
>
> +extern const char *tgsi_invariant_name;
> +
>  extern const char *tgsi_primitive_names[PIPE_PRIM_MAX];
>
>  extern const char *tgsi_fs_coord_origin_names[2];
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c 
> b/src/gallium/auxiliary/tgsi/tgsi_text.c
> index 02241a66bfe..815b1ee65db 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_text.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
> @@ -1586,10 +1586,6 @@ static boolean parse_declaration( struct translate_ctx 
> *ctx )
>  break;
>   }
>}
> -  if (i == TGSI_INTERPOLATE_COUNT) {
> - report_error( ctx, "Expected semantic or interpolate attribute" );
> - return FALSE;
> -  }
> }
>
> cur = ctx->cur;
> @@ -1609,6 +1605,20 @@ static boolean parse_declaration( struct translate_ctx 
> *ctx )
>}
> }
>
> +   cur = ctx->cur;
> +   eat_opt_white( &cur );
> +   if (*cur == ',' && !is_vs_input) {
> +  cur++;
> +  eat_opt_white( &cur );
> +  if (str_match_nocase_whole( &cur, tgsi_invariant_name )) {
> + decl.Declaration.Invariant = 1;
> + ctx->cur = cur;
> +  } else {
> + report_error( ctx, "Expected semantic, interpolate attribute, or 
> invariant ");
> + return FALSE;
> +  }
> +   }
> +
> advance = tgsi_build_full_declaration(
>&decl,
>ctx->tokens_cur,
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c 
> b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
> index 7d2b9af140d..f1bebe1e155 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
> @@ -140,6 +140,7 @@ struct ureg_program
>unsigned first;
>unsigned last;
>unsigned array_id;
> +  boolean invariant;
> } output[UREG_MAX_OUTPUT];
> unsigned nr_outputs, nr_output_regs;
>
> @@ -427,7 +428,8 @@ ureg_DECL_output_layout(struct ureg_program *ureg,
>  unsigned index,
>  unsigned usage_mask,
>  unsigned array_id,
> -unsigned array_size)
> +unsigned array_size,
> +boolean invariant)
>  {
> unsigned i;
>
> @@ -455,6 +457,7 @@ ureg_DECL_output_layout(struct ureg_program *ureg,
>ureg->output[i].first = index;
>ureg->output[i].last = index + array_size - 1;
>ureg->output[i].array_id = array_id;
> +  ureg->output[i].invariant = invariant;
>ureg->nr_output_regs = MAX2(ureg->nr_output_regs, index + array_size);
>ureg->nr_outputs++;
> }
> @@ -480,7 +483,8 @@ ureg_DECL_output_masked(struct ureg_program *ureg,
>  unsigned array_size)
>  {
> return ureg_DECL_output_layout(ureg, name, index, 0,
> -  ureg->nr_output_regs, usage_mask, 
> array_id, array_size);
> +  ureg->nr_output_regs, usage_mask, array_id,
> +  array_size, FALSE);
>  }
>
>
> @@ -1512,7 +1516,8 @@ emit_decl_semantic(struct ureg_program *ureg,
> unsigned semantic_index,
> unsigned streams,
> unsigned usage_mask,
> -

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