Re: [Mesa-dev] [PATCH] nir: cleanup oversized arrays in nir_swizzle calls

[Jason Ekstrand]

On Thu, Jul 12, 2018 at 7:20 PM Karol Herbst  wrote:

> On Fri, Jul 13, 2018 at 4:04 AM, Jason Ekstrand 
> wrote:
> > On Thu, Jul 12, 2018 at 6:48 PM Karol Herbst  wrote:
> >>
> >> There are no fixed sized array arguments in C, those are simply pointers
> >> to unsized arrays and as the size is passed in anyway, just rely on
> that.
> >>
> >> where possible calls are replaced by nir_channel and nir_channels.
> >>
> >> Signed-off-by: Karol Herbst 
> >> ---
> >>  src/amd/vulkan/radv_meta_blit2d.c   |  9 +++--
> >>  src/amd/vulkan/radv_meta_buffer.c   |  4 ++--
> >>  src/amd/vulkan/radv_query.c |  6 ++
> >>  src/compiler/nir/nir_builder.h  |  8 
> >>  src/compiler/nir/nir_lower_drawpixels.c |  7 ++-
> >>  src/compiler/nir/nir_lower_tex.c| 11 +--
> >>  src/compiler/spirv/spirv_to_nir.c   |  3 +--
> >>  src/compiler/spirv/vtn_glsl450.c| 10 +-
> >>  8 files changed, 24 insertions(+), 34 deletions(-)
> >>
> >> diff --git a/src/amd/vulkan/radv_meta_blit2d.c
> >> b/src/amd/vulkan/radv_meta_blit2d.c
> >> index 85e2d4678e9..cac0a4dd55f 100644
> >> --- a/src/amd/vulkan/radv_meta_blit2d.c
> >> +++ b/src/amd/vulkan/radv_meta_blit2d.c
> >> @@ -608,8 +608,7 @@ build_nir_copy_fragment_shader(struct radv_device
> >> *device,
> >> }
> >>
> >> nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(,
> >> tex_pos_in));
> >> -   unsigned swiz[4] = { 0, 1 };
> >> -   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
> >> +   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
> >>
> >> nir_ssa_def *color = txf_func(, device, tex_pos, is_3d,
> >> is_multisampled);
> >> nir_store_var(, color_out, color, 0xf);
> >> @@ -642,8 +641,7 @@ build_nir_copy_fragment_shader_depth(struct
> >> radv_device *device,
> >> }
> >>
> >> nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(,
> >> tex_pos_in));
> >> -   unsigned swiz[4] = { 0, 1 };
> >> -   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
> >> +   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
> >>
> >> nir_ssa_def *color = txf_func(, device, tex_pos, is_3d,
> >> is_multisampled);
> >> nir_store_var(, color_out, color, 0x1);
> >> @@ -676,8 +674,7 @@ build_nir_copy_fragment_shader_stencil(struct
> >> radv_device *device,
> >> }
> >>
> >> nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(,
> >> tex_pos_in));
> >> -   unsigned swiz[4] = { 0, 1 };
> >> -   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
> >> +   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
> >>
> >> nir_ssa_def *color = txf_func(, device, tex_pos, is_3d,
> >> is_multisampled);
> >> nir_store_var(, color_out, color, 0x1);
> >> diff --git a/src/amd/vulkan/radv_meta_buffer.c
> >> b/src/amd/vulkan/radv_meta_buffer.c
> >> index c8558216bf1..6c6d1cc41d7 100644
> >> --- a/src/amd/vulkan/radv_meta_buffer.c
> >> +++ b/src/amd/vulkan/radv_meta_buffer.c
> >> @@ -25,7 +25,7 @@ build_buffer_fill_shader(struct radv_device *dev)
> >> nir_ssa_def *global_id = nir_iadd(, nir_imul(, wg_id,
> >> block_size), invoc_id);
> >>
> >> nir_ssa_def *offset = nir_imul(, global_id, nir_imm_int(,
> >> 16));
> >> -   offset = nir_swizzle(, offset, (unsigned[]) {0, 0, 0, 0}, 1,
> >> false);
> >> +   offset = nir_channel(, offset, 0);
> >>
> >> nir_intrinsic_instr *dst_buf =
> >> nir_intrinsic_instr_create(b.shader,
> >>
> >> nir_intrinsic_vulkan_resource_index);
> >> @@ -77,7 +77,7 @@ build_buffer_copy_shader(struct radv_device *dev)
> >> nir_ssa_def *global_id = nir_iadd(, nir_imul(, wg_id,
> >> block_size), invoc_id);
> >>
> >> nir_ssa_def *offset = nir_imul(, global_id, nir_imm_int(,
> >> 16));
> >> -   offset = nir_swizzle(, offset, (unsigned[]) {0, 0, 0, 0}, 1,
> >> false);
> >> +   offset = nir_channel(, offset, 0);
> >>
> >> nir_intrinsic_instr *dst_buf =
> >> nir_intrinsic_instr_create(b.shader,
> >>
> >> nir_intrinsic_vulkan_resource_index);
> >> diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
> >> index 16c39aa135d..e3229ab59bb 100644
> >> --- a/src/amd/vulkan/radv_query.c
> >> +++ b/src/amd/vulkan/radv_query.c
> >> @@ -188,10 +188,8 @@ build_occlusion_query_shader(struct radv_device
> >> *device) {
> >> load->num_components = 2;
> >> nir_builder_instr_insert(, >instr);
> >>
> >> -   const unsigned swizzle0[] = {0,0,0,0};
> >> -   const unsigned swizzle1[] = {1,1,1,1};
> >> -   nir_store_var(, start, nir_swizzle(, >dest.ssa,
> >> swizzle0, 1, false), 0x1);
> >> -   nir_store_var(, end, nir_swizzle(, >dest.ssa,
> swizzle1,
> >> 1, false), 0x1);
> >> +   nir_store_var(, start, nir_channel(, >dest.ssa, 0),
> >> 0x1);
> >> +   nir_store_var(, end, nir_channel(, >dest.ssa, 1),
> 0x1);
> >>
> >> nir_ssa_def *start_done = nir_ilt(, nir_load_var(, start),
> >> 

Re: [Mesa-dev] [PATCH] nir: cleanup oversized arrays in nir_swizzle calls

[Karol Herbst]

On Fri, Jul 13, 2018 at 4:04 AM, Jason Ekstrand  wrote:
> On Thu, Jul 12, 2018 at 6:48 PM Karol Herbst  wrote:
>>
>> There are no fixed sized array arguments in C, those are simply pointers
>> to unsized arrays and as the size is passed in anyway, just rely on that.
>>
>> where possible calls are replaced by nir_channel and nir_channels.
>>
>> Signed-off-by: Karol Herbst 
>> ---
>>  src/amd/vulkan/radv_meta_blit2d.c   |  9 +++--
>>  src/amd/vulkan/radv_meta_buffer.c   |  4 ++--
>>  src/amd/vulkan/radv_query.c |  6 ++
>>  src/compiler/nir/nir_builder.h  |  8 
>>  src/compiler/nir/nir_lower_drawpixels.c |  7 ++-
>>  src/compiler/nir/nir_lower_tex.c| 11 +--
>>  src/compiler/spirv/spirv_to_nir.c   |  3 +--
>>  src/compiler/spirv/vtn_glsl450.c| 10 +-
>>  8 files changed, 24 insertions(+), 34 deletions(-)
>>
>> diff --git a/src/amd/vulkan/radv_meta_blit2d.c
>> b/src/amd/vulkan/radv_meta_blit2d.c
>> index 85e2d4678e9..cac0a4dd55f 100644
>> --- a/src/amd/vulkan/radv_meta_blit2d.c
>> +++ b/src/amd/vulkan/radv_meta_blit2d.c
>> @@ -608,8 +608,7 @@ build_nir_copy_fragment_shader(struct radv_device
>> *device,
>> }
>>
>> nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(,
>> tex_pos_in));
>> -   unsigned swiz[4] = { 0, 1 };
>> -   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
>> +   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
>>
>> nir_ssa_def *color = txf_func(, device, tex_pos, is_3d,
>> is_multisampled);
>> nir_store_var(, color_out, color, 0xf);
>> @@ -642,8 +641,7 @@ build_nir_copy_fragment_shader_depth(struct
>> radv_device *device,
>> }
>>
>> nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(,
>> tex_pos_in));
>> -   unsigned swiz[4] = { 0, 1 };
>> -   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
>> +   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
>>
>> nir_ssa_def *color = txf_func(, device, tex_pos, is_3d,
>> is_multisampled);
>> nir_store_var(, color_out, color, 0x1);
>> @@ -676,8 +674,7 @@ build_nir_copy_fragment_shader_stencil(struct
>> radv_device *device,
>> }
>>
>> nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(,
>> tex_pos_in));
>> -   unsigned swiz[4] = { 0, 1 };
>> -   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
>> +   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
>>
>> nir_ssa_def *color = txf_func(, device, tex_pos, is_3d,
>> is_multisampled);
>> nir_store_var(, color_out, color, 0x1);
>> diff --git a/src/amd/vulkan/radv_meta_buffer.c
>> b/src/amd/vulkan/radv_meta_buffer.c
>> index c8558216bf1..6c6d1cc41d7 100644
>> --- a/src/amd/vulkan/radv_meta_buffer.c
>> +++ b/src/amd/vulkan/radv_meta_buffer.c
>> @@ -25,7 +25,7 @@ build_buffer_fill_shader(struct radv_device *dev)
>> nir_ssa_def *global_id = nir_iadd(, nir_imul(, wg_id,
>> block_size), invoc_id);
>>
>> nir_ssa_def *offset = nir_imul(, global_id, nir_imm_int(,
>> 16));
>> -   offset = nir_swizzle(, offset, (unsigned[]) {0, 0, 0, 0}, 1,
>> false);
>> +   offset = nir_channel(, offset, 0);
>>
>> nir_intrinsic_instr *dst_buf =
>> nir_intrinsic_instr_create(b.shader,
>>
>> nir_intrinsic_vulkan_resource_index);
>> @@ -77,7 +77,7 @@ build_buffer_copy_shader(struct radv_device *dev)
>> nir_ssa_def *global_id = nir_iadd(, nir_imul(, wg_id,
>> block_size), invoc_id);
>>
>> nir_ssa_def *offset = nir_imul(, global_id, nir_imm_int(,
>> 16));
>> -   offset = nir_swizzle(, offset, (unsigned[]) {0, 0, 0, 0}, 1,
>> false);
>> +   offset = nir_channel(, offset, 0);
>>
>> nir_intrinsic_instr *dst_buf =
>> nir_intrinsic_instr_create(b.shader,
>>
>> nir_intrinsic_vulkan_resource_index);
>> diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
>> index 16c39aa135d..e3229ab59bb 100644
>> --- a/src/amd/vulkan/radv_query.c
>> +++ b/src/amd/vulkan/radv_query.c
>> @@ -188,10 +188,8 @@ build_occlusion_query_shader(struct radv_device
>> *device) {
>> load->num_components = 2;
>> nir_builder_instr_insert(, >instr);
>>
>> -   const unsigned swizzle0[] = {0,0,0,0};
>> -   const unsigned swizzle1[] = {1,1,1,1};
>> -   nir_store_var(, start, nir_swizzle(, >dest.ssa,
>> swizzle0, 1, false), 0x1);
>> -   nir_store_var(, end, nir_swizzle(, >dest.ssa, swizzle1,
>> 1, false), 0x1);
>> +   nir_store_var(, start, nir_channel(, >dest.ssa, 0),
>> 0x1);
>> +   nir_store_var(, end, nir_channel(, >dest.ssa, 1), 0x1);
>>
>> nir_ssa_def *start_done = nir_ilt(, nir_load_var(, start),
>> nir_imm_int64(, 0));
>> nir_ssa_def *end_done = nir_ilt(, nir_load_var(, end),
>> nir_imm_int64(, 0));
>> diff --git a/src/compiler/nir/nir_builder.h
>> b/src/compiler/nir/nir_builder.h
>> index ae64e72663c..ed61771150a 100644
>> --- a/src/compiler/nir/nir_builder.h
>> +++ 

Re: [Mesa-dev] [PATCH] nir: cleanup oversized arrays in nir_swizzle calls

[Jason Ekstrand]

On Thu, Jul 12, 2018 at 6:48 PM Karol Herbst  wrote:

> There are no fixed sized array arguments in C, those are simply pointers
> to unsized arrays and as the size is passed in anyway, just rely on that.
>
> where possible calls are replaced by nir_channel and nir_channels.
>
> Signed-off-by: Karol Herbst 
> ---
>  src/amd/vulkan/radv_meta_blit2d.c   |  9 +++--
>  src/amd/vulkan/radv_meta_buffer.c   |  4 ++--
>  src/amd/vulkan/radv_query.c |  6 ++
>  src/compiler/nir/nir_builder.h  |  8 
>  src/compiler/nir/nir_lower_drawpixels.c |  7 ++-
>  src/compiler/nir/nir_lower_tex.c| 11 +--
>  src/compiler/spirv/spirv_to_nir.c   |  3 +--
>  src/compiler/spirv/vtn_glsl450.c| 10 +-
>  8 files changed, 24 insertions(+), 34 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta_blit2d.c
> b/src/amd/vulkan/radv_meta_blit2d.c
> index 85e2d4678e9..cac0a4dd55f 100644
> --- a/src/amd/vulkan/radv_meta_blit2d.c
> +++ b/src/amd/vulkan/radv_meta_blit2d.c
> @@ -608,8 +608,7 @@ build_nir_copy_fragment_shader(struct radv_device
> *device,
> }
>
> nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(, tex_pos_in));
> -   unsigned swiz[4] = { 0, 1 };
> -   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
> +   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
>
> nir_ssa_def *color = txf_func(, device, tex_pos, is_3d,
> is_multisampled);
> nir_store_var(, color_out, color, 0xf);
> @@ -642,8 +641,7 @@ build_nir_copy_fragment_shader_depth(struct
> radv_device *device,
> }
>
> nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(, tex_pos_in));
> -   unsigned swiz[4] = { 0, 1 };
> -   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
> +   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
>
> nir_ssa_def *color = txf_func(, device, tex_pos, is_3d,
> is_multisampled);
> nir_store_var(, color_out, color, 0x1);
> @@ -676,8 +674,7 @@ build_nir_copy_fragment_shader_stencil(struct
> radv_device *device,
> }
>
> nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(, tex_pos_in));
> -   unsigned swiz[4] = { 0, 1 };
> -   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
> +   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
>
> nir_ssa_def *color = txf_func(, device, tex_pos, is_3d,
> is_multisampled);
> nir_store_var(, color_out, color, 0x1);
> diff --git a/src/amd/vulkan/radv_meta_buffer.c
> b/src/amd/vulkan/radv_meta_buffer.c
> index c8558216bf1..6c6d1cc41d7 100644
> --- a/src/amd/vulkan/radv_meta_buffer.c
> +++ b/src/amd/vulkan/radv_meta_buffer.c
> @@ -25,7 +25,7 @@ build_buffer_fill_shader(struct radv_device *dev)
> nir_ssa_def *global_id = nir_iadd(, nir_imul(, wg_id,
> block_size), invoc_id);
>
> nir_ssa_def *offset = nir_imul(, global_id, nir_imm_int(, 16));
> -   offset = nir_swizzle(, offset, (unsigned[]) {0, 0, 0, 0}, 1,
> false);
> +   offset = nir_channel(, offset, 0);
>
> nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
>
> nir_intrinsic_vulkan_resource_index);
> @@ -77,7 +77,7 @@ build_buffer_copy_shader(struct radv_device *dev)
> nir_ssa_def *global_id = nir_iadd(, nir_imul(, wg_id,
> block_size), invoc_id);
>
> nir_ssa_def *offset = nir_imul(, global_id, nir_imm_int(, 16));
> -   offset = nir_swizzle(, offset, (unsigned[]) {0, 0, 0, 0}, 1,
> false);
> +   offset = nir_channel(, offset, 0);
>
> nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
>
> nir_intrinsic_vulkan_resource_index);
> diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
> index 16c39aa135d..e3229ab59bb 100644
> --- a/src/amd/vulkan/radv_query.c
> +++ b/src/amd/vulkan/radv_query.c
> @@ -188,10 +188,8 @@ build_occlusion_query_shader(struct radv_device
> *device) {
> load->num_components = 2;
> nir_builder_instr_insert(, >instr);
>
> -   const unsigned swizzle0[] = {0,0,0,0};
> -   const unsigned swizzle1[] = {1,1,1,1};
> -   nir_store_var(, start, nir_swizzle(, >dest.ssa,
> swizzle0, 1, false), 0x1);
> -   nir_store_var(, end, nir_swizzle(, >dest.ssa, swizzle1,
> 1, false), 0x1);
> +   nir_store_var(, start, nir_channel(, >dest.ssa, 0), 0x1);
> +   nir_store_var(, end, nir_channel(, >dest.ssa, 1), 0x1);
>
> nir_ssa_def *start_done = nir_ilt(, nir_load_var(, start),
> nir_imm_int64(, 0));
> nir_ssa_def *end_done = nir_ilt(, nir_load_var(, end),
> nir_imm_int64(, 0));
> diff --git a/src/compiler/nir/nir_builder.h
> b/src/compiler/nir/nir_builder.h
> index ae64e72663c..ed61771150a 100644
> --- a/src/compiler/nir/nir_builder.h
> +++ b/src/compiler/nir/nir_builder.h
> @@ -430,12 +430,13 @@ nir_imov_alu(nir_builder *build, nir_alu_src src,
> unsigned num_components)
>   * Construct an fmov or imov that reswizzles the source's components.
>   */
>  

[Mesa-dev] [PATCH] nir: cleanup oversized arrays in nir_swizzle calls

[Karol Herbst]

There are no fixed sized array arguments in C, those are simply pointers
to unsized arrays and as the size is passed in anyway, just rely on that.

where possible calls are replaced by nir_channel and nir_channels.

Signed-off-by: Karol Herbst 
---
 src/amd/vulkan/radv_meta_blit2d.c   |  9 +++--
 src/amd/vulkan/radv_meta_buffer.c   |  4 ++--
 src/amd/vulkan/radv_query.c |  6 ++
 src/compiler/nir/nir_builder.h  |  8 
 src/compiler/nir/nir_lower_drawpixels.c |  7 ++-
 src/compiler/nir/nir_lower_tex.c| 11 +--
 src/compiler/spirv/spirv_to_nir.c   |  3 +--
 src/compiler/spirv/vtn_glsl450.c| 10 +-
 8 files changed, 24 insertions(+), 34 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_blit2d.c 
b/src/amd/vulkan/radv_meta_blit2d.c
index 85e2d4678e9..cac0a4dd55f 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -608,8 +608,7 @@ build_nir_copy_fragment_shader(struct radv_device *device,
}
 
nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(, tex_pos_in));
-   unsigned swiz[4] = { 0, 1 };
-   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
+   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
 
nir_ssa_def *color = txf_func(, device, tex_pos, is_3d, 
is_multisampled);
nir_store_var(, color_out, color, 0xf);
@@ -642,8 +641,7 @@ build_nir_copy_fragment_shader_depth(struct radv_device 
*device,
}
 
nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(, tex_pos_in));
-   unsigned swiz[4] = { 0, 1 };
-   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
+   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
 
nir_ssa_def *color = txf_func(, device, tex_pos, is_3d, 
is_multisampled);
nir_store_var(, color_out, color, 0x1);
@@ -676,8 +674,7 @@ build_nir_copy_fragment_shader_stencil(struct radv_device 
*device,
}
 
nir_ssa_def *pos_int = nir_f2i32(, nir_load_var(, tex_pos_in));
-   unsigned swiz[4] = { 0, 1 };
-   nir_ssa_def *tex_pos = nir_swizzle(, pos_int, swiz, 2, false);
+   nir_ssa_def *tex_pos = nir_channels(, pos_int, 0x3);
 
nir_ssa_def *color = txf_func(, device, tex_pos, is_3d, 
is_multisampled);
nir_store_var(, color_out, color, 0x1);
diff --git a/src/amd/vulkan/radv_meta_buffer.c 
b/src/amd/vulkan/radv_meta_buffer.c
index c8558216bf1..6c6d1cc41d7 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -25,7 +25,7 @@ build_buffer_fill_shader(struct radv_device *dev)
nir_ssa_def *global_id = nir_iadd(, nir_imul(, wg_id, block_size), 
invoc_id);
 
nir_ssa_def *offset = nir_imul(, global_id, nir_imm_int(, 16));
-   offset = nir_swizzle(, offset, (unsigned[]) {0, 0, 0, 0}, 1, false);
+   offset = nir_channel(, offset, 0);
 
nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
  
nir_intrinsic_vulkan_resource_index);
@@ -77,7 +77,7 @@ build_buffer_copy_shader(struct radv_device *dev)
nir_ssa_def *global_id = nir_iadd(, nir_imul(, wg_id, block_size), 
invoc_id);
 
nir_ssa_def *offset = nir_imul(, global_id, nir_imm_int(, 16));
-   offset = nir_swizzle(, offset, (unsigned[]) {0, 0, 0, 0}, 1, false);
+   offset = nir_channel(, offset, 0);
 
nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
  
nir_intrinsic_vulkan_resource_index);
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 16c39aa135d..e3229ab59bb 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -188,10 +188,8 @@ build_occlusion_query_shader(struct radv_device *device) {
load->num_components = 2;
nir_builder_instr_insert(, >instr);
 
-   const unsigned swizzle0[] = {0,0,0,0};
-   const unsigned swizzle1[] = {1,1,1,1};
-   nir_store_var(, start, nir_swizzle(, >dest.ssa, swizzle0, 1, 
false), 0x1);
-   nir_store_var(, end, nir_swizzle(, >dest.ssa, swizzle1, 1, 
false), 0x1);
+   nir_store_var(, start, nir_channel(, >dest.ssa, 0), 0x1);
+   nir_store_var(, end, nir_channel(, >dest.ssa, 1), 0x1);
 
nir_ssa_def *start_done = nir_ilt(, nir_load_var(, start), 
nir_imm_int64(, 0));
nir_ssa_def *end_done = nir_ilt(, nir_load_var(, end), 
nir_imm_int64(, 0));
diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index ae64e72663c..ed61771150a 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -430,12 +430,13 @@ nir_imov_alu(nir_builder *build, nir_alu_src src, 
unsigned num_components)
  * Construct an fmov or imov that reswizzles the source's components.
  */
 static inline nir_ssa_def *
-nir_swizzle(nir_builder *build, nir_ssa_def *src, const unsigned swiz[4],

[Mesa-dev] [Bug 107211] Write access request: Mesa

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107211

Jason Ekstrand  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from Jason Ekstrand  ---
$ git shortlog --author=Caio
Caio Marcelo de Oliveira Filho (21):
  spirv: Import 1.2 rev 3 headers and grammar from Khronos
  spirv: Add SpvCapabilityShaderViewportIndexLayerEXT
  anv/pipeline: fail if TCS/TES compile fail
  anv/pipeline: set active_stages early
  nir/dead_cf: rephrase definition of a dead loop node
  nir/dead_cf: also remove useless ifs
  anv/pipeline: use less instructions for multiview
  anv/pipeline: don't pass constant view index in multiview
  nir: rename variables in nir_lower_io_to_temporaries for clarity
  nir/vars_to_ssa: Rework register_variable_uses()
  nir/vars_to_ssa: Remove an unnecessary deref_arry_type check
  nir/vars_to_ssa: Simplify node matching code
  anv: enable VK_EXT_shader_viewport_index_layer
  intel/genxml: recognize 0x, 0o and 0b when setting default value
  util/set: add a basic unit test
  util/set: add a clone function
  util/set: helper to remove entry by key
  i965: fix typo (wrong gen number) in comment
  glsl: slim the kill_entry struct used in const propagation
  glsl: remove struct kill_entry in constant propagation
  nir: delete not needed for reinserted nir_cf_list

Good enough for me.  Access granted.  Please use responsibly.

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Re: [Mesa-dev] [PATCH] nir/lower_tex: Use nir_format_srgb_to_linear

[Jason Ekstrand]

Eric, I can't test this patch because it only affects your driver.

On Thu, Jul 12, 2018 at 6:23 PM Jason Ekstrand  wrote:

> A while ago, we added a bunch of format conversion helpers; we should
> use them instead of hand-rolling sRGB conversions.
> ---
>  src/compiler/nir/nir_lower_tex.c | 21 +++--
>  1 file changed, 3 insertions(+), 18 deletions(-)
>
> diff --git a/src/compiler/nir/nir_lower_tex.c
> b/src/compiler/nir/nir_lower_tex.c
> index 1ccd253320c..4da025a9e34 100644
> --- a/src/compiler/nir/nir_lower_tex.c
> +++ b/src/compiler/nir/nir_lower_tex.c
> @@ -37,6 +37,7 @@
>
>  #include "nir.h"
>  #include "nir_builder.h"
> +#include "nir_format_convert.h"
>
>  static void
>  project_src(nir_builder *b, nir_tex_instr *tex)
> @@ -711,24 +712,8 @@ linearize_srgb_result(nir_builder *b, nir_tex_instr
> *tex)
>
> b->cursor = nir_after_instr(>instr);
>
> -   static const unsigned swiz[4] = {0, 1, 2, 0};
> -   nir_ssa_def *comp = nir_swizzle(b, >dest.ssa, swiz, 3, true);
> -
> -   /* Formula is:
> -*(comp <= 0.04045) ?
> -*  (comp / 12.92) :
> -*  pow((comp + 0.055) / 1.055, 2.4)
> -*/
> -   nir_ssa_def *low  = nir_fmul(b, comp, nir_imm_float(b, 1.0 / 12.92));
> -   nir_ssa_def *high = nir_fpow(b,
> -nir_fmul(b,
> - nir_fadd(b,
> -  comp,
> -  nir_imm_float(b,
> 0.055)),
> - nir_imm_float(b, 1.0 / 1.055)),
> -nir_imm_float(b, 2.4));
> -   nir_ssa_def *cond = nir_fge(b, nir_imm_float(b, 0.04045), comp);
> -   nir_ssa_def *rgb  = nir_bcsel(b, cond, low, high);
> +   nir_ssa_def *rgb =
> +  nir_format_srgb_to_linear(b, nir_channels(b, >dest.ssa, 0x7));
>
> /* alpha is untouched: */
> nir_ssa_def *result = nir_vec4(b,
> --
> 2.17.1
>
>
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[Mesa-dev] [PATCH] nir/lower_tex: Use nir_format_srgb_to_linear

[Jason Ekstrand]

A while ago, we added a bunch of format conversion helpers; we should
use them instead of hand-rolling sRGB conversions.
---
 src/compiler/nir/nir_lower_tex.c | 21 +++--
 1 file changed, 3 insertions(+), 18 deletions(-)

diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c
index 1ccd253320c..4da025a9e34 100644
--- a/src/compiler/nir/nir_lower_tex.c
+++ b/src/compiler/nir/nir_lower_tex.c
@@ -37,6 +37,7 @@
 
 #include "nir.h"
 #include "nir_builder.h"
+#include "nir_format_convert.h"
 
 static void
 project_src(nir_builder *b, nir_tex_instr *tex)
@@ -711,24 +712,8 @@ linearize_srgb_result(nir_builder *b, nir_tex_instr *tex)
 
b->cursor = nir_after_instr(>instr);
 
-   static const unsigned swiz[4] = {0, 1, 2, 0};
-   nir_ssa_def *comp = nir_swizzle(b, >dest.ssa, swiz, 3, true);
-
-   /* Formula is:
-*(comp <= 0.04045) ?
-*  (comp / 12.92) :
-*  pow((comp + 0.055) / 1.055, 2.4)
-*/
-   nir_ssa_def *low  = nir_fmul(b, comp, nir_imm_float(b, 1.0 / 12.92));
-   nir_ssa_def *high = nir_fpow(b,
-nir_fmul(b,
- nir_fadd(b,
-  comp,
-  nir_imm_float(b, 0.055)),
- nir_imm_float(b, 1.0 / 1.055)),
-nir_imm_float(b, 2.4));
-   nir_ssa_def *cond = nir_fge(b, nir_imm_float(b, 0.04045), comp);
-   nir_ssa_def *rgb  = nir_bcsel(b, cond, low, high);
+   nir_ssa_def *rgb =
+  nir_format_srgb_to_linear(b, nir_channels(b, >dest.ssa, 0x7));
 
/* alpha is untouched: */
nir_ssa_def *result = nir_vec4(b,
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] util/hash_table: add helper to remove entry by key

[Eric Anholt]

Caio Marcelo de Oliveira Filho  writes:

> And the corresponding test case.

Reviewed-by: Eric Anholt 


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Re: [Mesa-dev] [PATCH] anv: Restrict the nuber of color regions to those actually written

[Caio Marcelo de Oliveira Filho]

On Thu, Jul 12, 2018 at 12:54:54PM -0700, Jason Ekstrand wrote:
> On Thu, Jul 12, 2018 at 10:28 AM Caio Marcelo de Oliveira Filho <
> caio.olive...@intel.com> wrote:
> 
> > > > Question: earlier in the code we call
> > > >
> > > >populate_wm_prog_key(pipeline, info, );
> > > >
> > > > which does
> > > >
> > > >key->nr_color_regions = pipeline->subpass->color_count;
> > > >
> > > >key->replicate_alpha = key->nr_color_regions > 1 &&
> > > >   info->pMultisampleState &&
> > > >
> >  info->pMultisampleState->alphaToCoverageEnable;
> > > >
> > > > so key->replicate_alpha is calculated based on the old value. Should
> > > > this be (re)calculated using the new value?
> > > >
> > >
> > > We could but it would have no effect.  100% of the uses of
> > replicate_alpha
> > > in the back-end have it ANDed with inst->target > 0.
> >
> > If it's not effectful, maybe we could remove the
> > "key->nr_color_regions > 1 &&" from the definition of replicate_alpha
> > then?
> >
> 
> We could but that might result in more cache misses.  By setting it to
> false when nr_color_regions <= 1, we avoid extra cache misses of you
> compile the same single-output shader twice once with alphaToCoverage and
> once without.

Got it, thanks for the explanation.
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[Mesa-dev] [PATCH 1/2] egl/surfaceless: Define DRI_SWRastLoader extension when using swrast.

[David Riley]

Signed-off-by: David Riley 

---
 src/egl/drivers/dri2/platform_surfaceless.c | 28 +++-
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_surfaceless.c 
b/src/egl/drivers/dri2/platform_surfaceless.c
index a0348a5..f5fe711 100644
--- a/src/egl/drivers/dri2/platform_surfaceless.c
+++ b/src/egl/drivers/dri2/platform_surfaceless.c
@@ -260,6 +260,13 @@ static const __DRIimageLoaderExtension 
image_loader_extension = {
.flushFrontBuffer = surfaceless_flush_front_buffer,
 };
 
+static const __DRIswrastLoaderExtension swrast_loader_extension = {
+   .base= { __DRI_SWRAST_LOADER, 1 },
+   .getDrawableInfo = NULL,
+   .putImage= NULL,
+   .getImage= NULL,
+};
+
 #define DRM_RENDER_DEV_NAME  "%s/renderD%d"
 
 static const __DRIextension *image_loader_extensions[] = {
@@ -269,6 +276,14 @@ static const __DRIextension *image_loader_extensions[] = {
NULL,
 };
 
+static const __DRIextension *swrast_loader_extensions[] = {
+   _loader_extension.base,
+   _loader_extension.base,
+   _lookup_extension.base,
+   _invalidate.base,
+   NULL,
+};
+
 static bool
 surfaceless_probe_device(_EGLDisplay *dpy, bool swrast)
 {
@@ -288,23 +303,28 @@ surfaceless_probe_device(_EGLDisplay *dpy, bool swrast)
   if (fd < 0)
  continue;
 
-  if (swrast)
+  if (swrast) {
  dri2_dpy->driver_name = strdup("kms_swrast");
-  else
+ dri2_dpy->loader_extensions = swrast_loader_extensions;
+  } else {
  dri2_dpy->driver_name = loader_get_driver_for_fd(fd);
+ dri2_dpy->loader_extensions = image_loader_extensions;
+  }
   if (!dri2_dpy->driver_name) {
  close(fd);
  continue;
   }
 
   dri2_dpy->fd = fd;
-  if (dri2_load_driver_dri3(dpy))
+  if (dri2_load_driver_dri3(dpy)) {
  return true;
+  }
 
   close(fd);
   dri2_dpy->fd = -1;
   free(dri2_dpy->driver_name);
   dri2_dpy->driver_name = NULL;
+  dri2_dpy->loader_extensions = NULL;
}
 
return false;
@@ -338,8 +358,6 @@ dri2_initialize_surfaceless(_EGLDriver *drv, _EGLDisplay 
*disp)
   goto cleanup;
}
 
-   dri2_dpy->loader_extensions = image_loader_extensions;
-
if (!dri2_create_screen(disp)) {
   err = "DRI2: failed to create screen";
   goto cleanup;
-- 
2.7.4

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[Mesa-dev] [PATCH 2/2] egl/surfaceless: Allow DRMless fallback.

[David Riley]

Allow platform_surfaceless to use swrast even if DRM is not available.
To be used to allow a fuzzer for virgl to be run on a jailed VM without
hardware GL or DRM support.

Signed-off-by: David Riley 
---
 src/egl/drivers/dri2/platform_surfaceless.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/src/egl/drivers/dri2/platform_surfaceless.c 
b/src/egl/drivers/dri2/platform_surfaceless.c
index f5fe711..3b17e95 100644
--- a/src/egl/drivers/dri2/platform_surfaceless.c
+++ b/src/egl/drivers/dri2/platform_surfaceless.c
@@ -293,6 +293,7 @@ surfaceless_probe_device(_EGLDisplay *dpy, bool swrast)
int fd;
int i;
 
+   // Attempt to find DRM device.
for (i = 0; i < limit; ++i) {
   char *card_path;
   if (asprintf(_path, DRM_RENDER_DEV_NAME, DRM_DIR_NAME, base + i) < 
0)
@@ -327,6 +328,25 @@ surfaceless_probe_device(_EGLDisplay *dpy, bool swrast)
   dri2_dpy->loader_extensions = NULL;
}
 
+   // No DRM device, so attempt to fall back to software path w/o DRM.
+   if (swrast) {
+  _eglLog(_EGL_DEBUG, "Falling back to surfaceless swrast without DRM.");
+  dri2_dpy->fd = -1;
+  dri2_dpy->driver_name = strdup("swrast");
+  if (!dri2_dpy->driver_name) {
+ return false;
+  }
+
+  if (dri2_load_driver_swrast(dpy)) {
+ dri2_dpy->loader_extensions = swrast_loader_extensions;
+ return true;
+  }
+
+  dri2_dpy->fd = -1;
+  free(dri2_dpy->driver_name);
+  dri2_dpy->driver_name = NULL;
+   }
+
return false;
 }
 
-- 
2.7.4

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[Mesa-dev] [PATCH 2/2] intel/blorp: Handle 3-component formats in clears

[Jason Ekstrand]

This fixes a nasty hang in Batman: Arkham City which apparently calls
vkCmdClearColorImage on a linear RGB image.

cc: mesa-sta...@lists.freedesktop.org
---
 src/intel/blorp/blorp_blit.c  |  2 +-
 src/intel/blorp/blorp_clear.c | 98 +++
 src/intel/blorp/blorp_priv.h  |  3 ++
 3 files changed, 92 insertions(+), 11 deletions(-)

diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 66f58344ef6..d0ae9ee2621 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1701,7 +1701,7 @@ get_red_format_for_rgb_format(enum isl_format format)
}
 }
 
-static void
+void
 surf_fake_rgb_with_red(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info)
 {
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 4d3125aade8..b4c744020d9 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -38,17 +38,20 @@ struct brw_blorp_const_color_prog_key
 {
enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_CLEAR */
bool use_simd16_replicated_data;
+   bool clear_rgb_as_red;
bool pad[3];
 };
 
 static bool
 blorp_params_get_clear_kernel(struct blorp_context *blorp,
   struct blorp_params *params,
-  bool use_replicated_data)
+  bool use_replicated_data,
+  bool clear_rgb_as_red)
 {
const struct brw_blorp_const_color_prog_key blorp_key = {
   .shader_type = BLORP_SHADER_TYPE_CLEAR,
   .use_simd16_replicated_data = use_replicated_data,
+  .clear_rgb_as_red = clear_rgb_as_red,
};
 
if (blorp->lookup_shader(blorp, _key, sizeof(blorp_key),
@@ -63,13 +66,34 @@ blorp_params_get_clear_kernel(struct blorp_context *blorp,
 
nir_variable *v_color =
   BLORP_CREATE_NIR_INPUT(b.shader, clear_color, glsl_vec4_type());
+   nir_ssa_def *color = nir_load_var(, v_color);
+
+   if (clear_rgb_as_red) {
+  nir_variable *frag_coord =
+ nir_variable_create(b.shader, nir_var_shader_in,
+ glsl_vec4_type(), "gl_FragCoord");
+  frag_coord->data.location = VARYING_SLOT_POS;
+  frag_coord->data.origin_upper_left = true;
+
+  nir_ssa_def *pos = nir_f2i32(, nir_load_var(, frag_coord));
+  nir_ssa_def *comp = nir_umod(, nir_channel(, pos, 0),
+   nir_imm_int(, 3));
+  nir_ssa_def *color_component =
+ nir_bcsel(, nir_ieq(, comp, nir_imm_int(, 0)),
+   nir_channel(, color, 0),
+   nir_bcsel(, nir_ieq(, comp, nir_imm_int(, 1)),
+ nir_channel(, color, 1),
+ nir_channel(, color, 2)));
+
+  nir_ssa_def *u = nir_ssa_undef(, 1, 32);
+  color = nir_vec4(, color_component, u, u, u);
+   }
 
nir_variable *frag_color = nir_variable_create(b.shader, nir_var_shader_out,
   glsl_vec4_type(),
   "gl_FragColor");
frag_color->data.location = FRAG_RESULT_COLOR;
-
-   nir_copy_var(, frag_color, v_color);
+   nir_store_var(, frag_color, color, 0xf);
 
struct brw_wm_prog_key wm_key;
brw_blorp_init_wm_prog_key(_key);
@@ -327,7 +351,7 @@ blorp_fast_clear(struct blorp_batch *batch,
get_fast_clear_rect(batch->blorp->isl_dev, surf->aux_surf,
, , , );
 
-   if (!blorp_params_get_clear_kernel(batch->blorp, , true))
+   if (!blorp_params_get_clear_kernel(batch->blorp, , true, false))
   return;
 
brw_blorp_surface_info_init(batch->blorp, , surf, level,
@@ -378,6 +402,7 @@ blorp_clear(struct blorp_batch *batch,
clear_color = swizzle_color_value(clear_color, swizzle);
swizzle = ISL_SWIZZLE_IDENTITY;
 
+   bool clear_rgb_as_red = false;
if (format == ISL_FORMAT_R9G9B9E5_SHAREDEXP) {
   clear_color.u32[0] = float3_to_rgb9e5(clear_color.f32);
   format = ISL_FORMAT_R32_UINT;
@@ -391,6 +416,13 @@ blorp_clear(struct blorp_batch *batch,
   const struct isl_swizzle ARGB = ISL_SWIZZLE(ALPHA, RED, GREEN, BLUE);
   clear_color = swizzle_color_value(clear_color, ARGB);
   format = ISL_FORMAT_B4G4R4A4_UNORM;
+   } else if (isl_format_get_layout(format)->bpb % 3 == 0) {
+  clear_rgb_as_red = true;
+  if (format == ISL_FORMAT_R8G8B8_UNORM_SRGB) {
+ clear_color.f32[0] = 
util_format_linear_to_srgb_float(clear_color.f32[0]);
+ clear_color.f32[1] = 
util_format_linear_to_srgb_float(clear_color.f32[1]);
+ clear_color.f32[2] = 
util_format_linear_to_srgb_float(clear_color.f32[2]);
+  }
}
 
memcpy(_inputs.clear_color, clear_color.f32, sizeof(float) * 4);
@@ -422,7 +454,8 @@ blorp_clear(struct blorp_batch *batch,
}
 
if (!blorp_params_get_clear_kernel(batch->blorp, ,
-  

[Mesa-dev] [PATCH 1/2] intel/blorp: Fix blits to R8G8B8_UNORM_SRGB

[Jason Ekstrand]

In this case, the surface faking will give us a R8_UNORM surface and we
need to do an sRGB conversion in the shader.

cc: mesa-sta...@lists.freedesktop.org
---
 src/intel/blorp/blorp_blit.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 0045275a550..66f58344ef6 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1954,6 +1954,10 @@ try_blorp_blit(struct blorp_batch *batch,
   params->x0 *= 3;
   params->x1 *= 3;
 
+  /* If it happens to be sRGB, we need to force a conversion */
+  if (params->dst.view.format == ISL_FORMAT_R8G8B8_UNORM_SRGB)
+ wm_prog_key->dst_format = ISL_FORMAT_R9G9B9E5_SHAREDEXP;
+
   surf_fake_rgb_with_red(batch->blorp->isl_dev, >dst);
 
   wm_prog_key->dst_rgb = true;
-- 
2.17.1

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[Mesa-dev] [Bug 107211] Write access request: Mesa

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107211

Caio Marcelo de Oliveira Filho  changed:

   What|Removed |Added

   Assignee|mesa-dev@lists.freedesktop. |ja...@jlekstrand.net
   |org |

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[Mesa-dev] [Bug 107211] Write access request: Mesa

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107211

Bug ID: 107211
   Summary: Write access request: Mesa
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Other
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: caio.olive...@intel.com
QA Contact: mesa-dev@lists.freedesktop.org

I already have a gitlab account (cmarcelo).

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[Mesa-dev] [Bug 107156] earth tessellation bug

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107156

--- Comment #8 from Timothy Arceri  ---
(In reply to Samuel Pitoiset from comment #7)
> Really nice, thanks! Closing.

I don't think that's right. I don't think the bug was even in the 18.1 release
to begin with going by the dates given in the initial report. ximik are you
able to bisect? Is this still a problem in git?

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Re: [Mesa-dev] [PATCH 9/9] winsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0

[Marek Olšák]

On Thu, Jul 12, 2018 at 7:07 AM, Michel Dänzer  wrote:
> On 2018-07-12 12:12 PM, Timothy Arceri wrote:
>>
>>
>> On 12/07/18 19:00, Michel Dänzer wrote:
>>> On 2018-07-12 07:26 AM, Marek Olšák wrote:
 From: Marek Olšák 

 TODO: requires latest libdrm for amdgpu_bo_handle_type_kms_noimport
 ---
   src/gallium/winsys/amdgpu/drm/amdgpu_bo.c |  6 +++
   src/gallium/winsys/amdgpu/drm/amdgpu_bo.h |  2 +
   src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 54 +--
   3 files changed, 58 insertions(+), 4 deletions(-)

 diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
 b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
 index e3d56613dfa..eba8d6e8b3d 100644
 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
 +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
 @@ -473,20 +473,22 @@ static struct amdgpu_winsys_bo
 *amdgpu_create_bo(struct amdgpu_winsys *ws,
  bo->u.real.va_handle = va_handle;
  bo->initial_domain = initial_domain;
  bo->unique_id = __sync_fetch_and_add(>next_bo_unique_id, 1);
  bo->is_local = !!(request.flags &
 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID);
if (initial_domain & RADEON_DOMAIN_VRAM)
 ws->allocated_vram += align64(size, ws->info.gart_page_size);
  else if (initial_domain & RADEON_DOMAIN_GTT)
 ws->allocated_gtt += align64(size, ws->info.gart_page_size);
   +   amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms_noimport,
 >u.real.kms_handle);
>>>
>>> How does using amdgpu_bo_handle_type_kms instead affect the numbers?
>>>
>>
>> The stats are in the cover letter but I think it would be worth Marek
>> adding them to the commit messages of the patches in some form for
>> future reference.
>>
>> The maximum glxgears FPS improves as follows.
>>
>> Initially: 13285
>> 8 patches: 14403 (+8.4% vs initial)
>> + patch 9: 15498 (+16.6% vs initial)
>
> I'm asking what the final number is when using amdgpu_bo_handle_type_kms
> instead of amdgpu_bo_handle_type_kms_noimport in the last patch.

My intent is not to thrash the hash table in libdrm. I don't plan to
measure the numbers between type_kms and type_kms_noimport. All I need
to know is that noimport is not slower (i.e. there is no risk), and
any improvement above that is just a bonus. Many trivial performance
improvements in the driver were done with little to no measurements.

Marek
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Re: [Mesa-dev] [PATCH 7/9] radeonsi: rework RADEON_PRIO flags to be <= 31

[Marek Olšák]

On Thu, Jul 12, 2018 at 2:24 AM, Timothy Arceri  wrote:
> Two suggestions below.
>
>
> On 12/07/18 15:26, Marek Olšák wrote:
>>
>> From: Marek Olšák 
>>
>> This decreases sizeof(struct amdgpu_cs_buffer) from 24 to 16 bytes.
>> ---
>>   src/gallium/drivers/radeon/radeon_winsys.h| 39 ++-
>>   src/gallium/drivers/radeonsi/si_debug.c   |  2 +-
>>   src/gallium/winsys/amdgpu/drm/amdgpu_cs.c |  6 +--
>>   src/gallium/winsys/amdgpu/drm/amdgpu_cs.h |  4 +-
>>   src/gallium/winsys/radeon/drm/radeon_drm_cs.c |  2 +-
>>   src/gallium/winsys/radeon/drm/radeon_drm_cs.h |  2 +-
>>   6 files changed, 28 insertions(+), 27 deletions(-)
>>
>> diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
>> b/src/gallium/drivers/radeon/radeon_winsys.h
>> index bcd6831ed35..10c63ae4d82 100644
>> --- a/src/gallium/drivers/radeon/radeon_winsys.h
>> +++ b/src/gallium/drivers/radeon/radeon_winsys.h
>> @@ -108,63 +108,64 @@ enum radeon_value_id {
>>   RADEON_VRAM_USAGE,
>>   RADEON_VRAM_VIS_USAGE,
>>   RADEON_GTT_USAGE,
>>   RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
>>   RADEON_CURRENT_SCLK,
>>   RADEON_CURRENT_MCLK,
>>   RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
>>   RADEON_CS_THREAD_TIME,
>>   };
>>   -/* Each group of four has the same priority. */
>>   enum radeon_bo_priority {
>> +/* Each group of two has the same priority. */
>>   RADEON_PRIO_FENCE = 0,
>>   RADEON_PRIO_TRACE,
>> -RADEON_PRIO_SO_FILLED_SIZE,
>> +
>> +RADEON_PRIO_SO_FILLED_SIZE = 2,
>>   RADEON_PRIO_QUERY,
>> RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
>>   RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
>> -RADEON_PRIO_DRAW_INDIRECT,
>> +
>> +RADEON_PRIO_DRAW_INDIRECT = 6,
>>   RADEON_PRIO_INDEX_BUFFER,
>>   -RADEON_PRIO_CP_DMA = 12,
>> +RADEON_PRIO_CP_DMA = 8,
>> +RADEON_PRIO_BORDER_COLORS,
>>   -RADEON_PRIO_CONST_BUFFER = 16,
>> +RADEON_PRIO_CONST_BUFFER = 10,
>>   RADEON_PRIO_DESCRIPTORS,
>> -RADEON_PRIO_BORDER_COLORS,
>>   -RADEON_PRIO_SAMPLER_BUFFER = 20,
>> +RADEON_PRIO_SAMPLER_BUFFER = 12,
>>   RADEON_PRIO_VERTEX_BUFFER,
>>   -RADEON_PRIO_SHADER_RW_BUFFER = 24,
>> +RADEON_PRIO_SHADER_RW_BUFFER = 14,
>>   RADEON_PRIO_COMPUTE_GLOBAL,
>>   -RADEON_PRIO_SAMPLER_TEXTURE = 28,
>> +RADEON_PRIO_SAMPLER_TEXTURE = 16,
>>   RADEON_PRIO_SHADER_RW_IMAGE,
>>   -RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,
>> -
>> -RADEON_PRIO_COLOR_BUFFER = 36,
>> +RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 18,
>> +RADEON_PRIO_COLOR_BUFFER,
>>   -RADEON_PRIO_DEPTH_BUFFER = 40,
>> +RADEON_PRIO_DEPTH_BUFFER = 20,
>>   -RADEON_PRIO_COLOR_BUFFER_MSAA = 44,
>> +RADEON_PRIO_COLOR_BUFFER_MSAA = 22,
>>   -RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,
>> +RADEON_PRIO_DEPTH_BUFFER_MSAA = 24,
>>   -RADEON_PRIO_SEPARATE_META = 52,
>> +RADEON_PRIO_SEPARATE_META = 26,
>>   RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache
>> misses */
>>   -RADEON_PRIO_SHADER_RINGS = 56,
>> +RADEON_PRIO_SHADER_RINGS = 28,
>>   -RADEON_PRIO_SCRATCH_BUFFER = 60,
>> +RADEON_PRIO_SCRATCH_BUFFER = 30,
>>   /* 63 is the maximum value */
>
>
> 31 is the maximum value ???

Yes. Thanks.

>
>
>
>
>
>>   };
>> struct winsys_handle;
>>   struct radeon_winsys_ctx;
>> struct radeon_cmdbuf_chunk {
>>   unsigned cdw;  /* Number of used dwords. */
>>   unsigned max_dw; /* Maximum number of dwords. */
>>   uint32_t *buf; /* The base pointer of the chunk. */
>> @@ -216,21 +217,21 @@ struct radeon_bo_metadata {
>>   };
>> enum radeon_feature_id {
>>   RADEON_FID_R300_HYPERZ_ACCESS, /* ZMask + HiZ */
>>   RADEON_FID_R300_CMASK_ACCESS,
>>   };
>> struct radeon_bo_list_item {
>>   uint64_t bo_size;
>>   uint64_t vm_address;
>> -uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
>> +uint32_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
>>   };
>> struct radeon_winsys {
>>   /**
>>* The screen object this winsys was created for
>>*/
>>   struct pipe_screen *screen;
>> /**
>>* Decrement the winsys reference count.
>> diff --git a/src/gallium/drivers/radeonsi/si_debug.c
>> b/src/gallium/drivers/radeonsi/si_debug.c
>> index 50375ce7cbe..d6207e68d12 100644
>> --- a/src/gallium/drivers/radeonsi/si_debug.c
>> +++ b/src/gallium/drivers/radeonsi/si_debug.c
>> @@ -562,21 +562,21 @@ static void si_dump_bo_list(struct si_context *sctx,
>> (va - previous_va_end) /
>> page_size);
>> }
>> }
>> /* Print the buffer. */
>> fprintf(f, "  %10"PRIu64"0x%013"PRIX64"
>> 0x%013"PRIX64"   ",
>> size / page_size, va / page_size, (va + size) /
>> page_size);
>> /* Print the usage. */
>> for (j = 0; j < 64; j++) {
>
>
>

[Mesa-dev] [PATCH] util/hash_table: add helper to remove entry by key

[Caio Marcelo de Oliveira Filho]

And the corresponding test case.
---
 src/util/hash_table.c  |  9 
 src/util/hash_table.h  |  2 +
 src/util/tests/hash_table/.gitignore   |  1 +
 src/util/tests/hash_table/Makefile.am  |  1 +
 src/util/tests/hash_table/meson.build  |  3 +-
 src/util/tests/hash_table/remove_key.c | 63 ++
 6 files changed, 78 insertions(+), 1 deletion(-)
 create mode 100644 src/util/tests/hash_table/remove_key.c

diff --git a/src/util/hash_table.c b/src/util/hash_table.c
index f8d5d0f88aa..7ee9e18a1fc 100644
--- a/src/util/hash_table.c
+++ b/src/util/hash_table.c
@@ -420,6 +420,15 @@ _mesa_hash_table_remove(struct hash_table *ht,
ht->deleted_entries++;
 }
 
+/**
+ * Removes the entry with the corresponding key, if exists.
+ */
+void _mesa_hash_table_remove_key(struct hash_table *ht,
+ const void *key)
+{
+   _mesa_hash_table_remove(ht, _mesa_hash_table_search(ht, key));
+}
+
 /**
  * This function is an iterator over the hash table.
  *
diff --git a/src/util/hash_table.h b/src/util/hash_table.h
index 3846dad4b4a..40ff041e94b 100644
--- a/src/util/hash_table.h
+++ b/src/util/hash_table.h
@@ -88,6 +88,8 @@ _mesa_hash_table_search_pre_hashed(struct hash_table *ht, 
uint32_t hash,
   const void *key);
 void _mesa_hash_table_remove(struct hash_table *ht,
  struct hash_entry *entry);
+void _mesa_hash_table_remove_key(struct hash_table *ht,
+ const void *key);
 
 struct hash_entry *_mesa_hash_table_next_entry(struct hash_table *ht,
struct hash_entry *entry);
diff --git a/src/util/tests/hash_table/.gitignore 
b/src/util/tests/hash_table/.gitignore
index a0d50ab82ce..5f2315b32a3 100644
--- a/src/util/tests/hash_table/.gitignore
+++ b/src/util/tests/hash_table/.gitignore
@@ -6,6 +6,7 @@ insert_and_lookup
 insert_many
 null_destroy
 random_entry
+remove_key
 remove_null
 replacement
 clear
diff --git a/src/util/tests/hash_table/Makefile.am 
b/src/util/tests/hash_table/Makefile.am
index 6b9221f8589..526454cb1ed 100644
--- a/src/util/tests/hash_table/Makefile.am
+++ b/src/util/tests/hash_table/Makefile.am
@@ -38,6 +38,7 @@ TESTS = \
insert_many \
null_destroy \
random_entry \
+   remove_key \
remove_null \
replacement \
$()
diff --git a/src/util/tests/hash_table/meson.build 
b/src/util/tests/hash_table/meson.build
index 4bbc5100ea3..c7b03f19c56 100644
--- a/src/util/tests/hash_table/meson.build
+++ b/src/util/tests/hash_table/meson.build
@@ -20,7 +20,8 @@
 
 foreach t : ['clear', 'collision', 'delete_and_lookup', 'delete_management',
  'destroy_callback', 'insert_and_lookup', 'insert_many',
- 'null_destroy', 'random_entry', 'remove_null', 'replacement']
+ 'null_destroy', 'random_entry', 'remove_key', 'remove_null',
+ 'replacement']
   test(
 t,
 executable(
diff --git a/src/util/tests/hash_table/remove_key.c 
b/src/util/tests/hash_table/remove_key.c
new file mode 100644
index 000..906de67998b
--- /dev/null
+++ b/src/util/tests/hash_table/remove_key.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include "hash_table.h"
+
+int
+main(int argc, char **argv)
+{
+   struct hash_table *ht;
+   const char *str1 = "test1";
+   const char *str2 = "test2";
+   struct hash_entry *entry;
+
+   (void) argc;
+   (void) argv;
+
+   ht = _mesa_hash_table_create(NULL, _mesa_key_hash_string, 
_mesa_key_string_equal);
+
+   _mesa_hash_table_insert(ht, str1, NULL);
+   _mesa_hash_table_insert(ht, str2, NULL);
+
+   entry = _mesa_hash_table_search(ht, str2);
+   assert(strcmp(entry->key, str2) == 0);
+
+   entry = 

[Mesa-dev] [Bug 106644] [llvmpipe] Mesa 18.1.2 fails lp_test_format, lp_test_arit, lp_test_blend, lp_test_printf, lp_test_conv tests

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106644

--- Comment #35 from erhar...@mailbox.org ---
Created attachment 140612
  --> https://bugs.freedesktop.org/attachment.cgi?id=140612=edit
output from lp_test_* (ppc64)

Here's the ouptut from my other G5's ppc64 BE setup.

I will certainly try ppc64 LE on Talos II, but the G5 can't do LE, neither my
laptop, a PowerBook G4. ;)

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Re: [Mesa-dev] [PATCH 3/3] i965/miptree: Use the correct BLT pitch

[Nanley Chery]

On Thu, Jul 12, 2018 at 06:35:06PM +0100, Chris Wilson wrote:
> Quoting Nanley Chery (2018-07-12 18:28:16)
> > Retile miptrees to a linear tiling less often. Retiling can cause issues
> > with imported BOs.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106738
> > Suggested-by: Chris Wilson 
> > Cc: 
> Reviewed-by: Chris Wilson 
> -Chris

Thanks for the review! Pushed. Hopefully in time for the next stable
release.

-Nanley

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Re: [Mesa-dev] [PATCH] anv: Restrict the nuber of color regions to those actually written

[Jason Ekstrand]

On Thu, Jul 12, 2018 at 10:29 AM Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:

> On Sat, Jul 07, 2018 at 09:35:52AM -0700, Jason Ekstrand wrote:
> > On Thu, Jul 5, 2018 at 6:34 PM Caio Marcelo de Oliveira Filho <
> > caio.olive...@intel.com> wrote:
> >
> > > On Wed, Jun 27, 2018 at 07:00:56PM -0700, Jason Ekstrand wrote:
> > > > The back-end compiler emits the number of color writes specified by
> > > > wm_prog_key::nr_color_regions regardless of what nir_store_outputs we
> > > > have.  Once we've gone through and figured out which render targets
> > > > actually exist and are written by the shader, we should restrict the
> key
> > > > to avoid extra RT write messages.
> > > > ---
> > > >  src/intel/vulkan/anv_pipeline.c | 5 +
> > > >  1 file changed, 5 insertions(+)
>
> Minor: there's a typo in the commit title.
>

Thanks!  Fixed.
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Re: [Mesa-dev] [PATCH] anv: Restrict the nuber of color regions to those actually written

[Jason Ekstrand]

On Thu, Jul 12, 2018 at 10:28 AM Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:

> > > Question: earlier in the code we call
> > >
> > >populate_wm_prog_key(pipeline, info, );
> > >
> > > which does
> > >
> > >key->nr_color_regions = pipeline->subpass->color_count;
> > >
> > >key->replicate_alpha = key->nr_color_regions > 1 &&
> > >   info->pMultisampleState &&
> > >
>  info->pMultisampleState->alphaToCoverageEnable;
> > >
> > > so key->replicate_alpha is calculated based on the old value. Should
> > > this be (re)calculated using the new value?
> > >
> >
> > We could but it would have no effect.  100% of the uses of
> replicate_alpha
> > in the back-end have it ANDed with inst->target > 0.
>
> If it's not effectful, maybe we could remove the
> "key->nr_color_regions > 1 &&" from the definition of replicate_alpha
> then?
>

We could but that might result in more cache misses.  By setting it to
false when nr_color_regions <= 1, we avoid extra cache misses of you
compile the same single-output shader twice once with alphaToCoverage and
once without.
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Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9

[Dylan Baker]

Quoting Samuel Pitoiset (2018-07-11 02:55:55)
> A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
> counters) must immediately precede every timestamp event to
> prevent a GPU hang on GFX9.
> 
> Signed-off-by: Samuel Pitoiset 
> Cc: 18.1 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 15 +--
>  src/amd/vulkan/radv_device.c |  4 ++--
>  src/amd/vulkan/radv_private.h|  7 +--
>  src/amd/vulkan/radv_query.c  |  9 ++---
>  src/amd/vulkan/si_cmd_buffer.c   | 26 +-
>  5 files changed, 47 insertions(+), 14 deletions(-)
> 
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 9da42fe03e..325e1993f8 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -319,11 +319,21 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer 
> *cmd_buffer)
> }
>  
> if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) 
> {
> +   unsigned num_db = 
> cmd_buffer->device->physical_device->rad_info.num_render_backends;
> +   unsigned eop_bug_offset;
> void *fence_ptr;
> +
> radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
>  _buffer->gfx9_fence_offset,
>  _ptr);
> cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
> +
> +   /* Allocate a buffer for the EOP bug on GFX9. */
> +   radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
> +_bug_offset, _ptr);
> +   cmd_buffer->gfx9_eop_bug_va =
> +   radv_buffer_get_va(cmd_buffer->upload.upload_bo);
> +   cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
> }
>  
> cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
> @@ -473,7 +483,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer 
> *cmd_buffer,
>
> cmd_buffer->device->physical_device->rad_info.chip_class,
>ptr, va,
>radv_cmd_buffer_uses_mec(cmd_buffer),
> -  flags);
> +  flags, cmd_buffer->gfx9_eop_bug_va);
> }
>  
> if (unlikely(cmd_buffer->device->trace_bo))
> @@ -4318,7 +4328,8 @@ static void write_event(struct radv_cmd_buffer 
> *cmd_buffer,
>
> cmd_buffer->device->physical_device->rad_info.chip_class,
>
> radv_cmd_buffer_uses_mec(cmd_buffer),
>V_028A90_BOTTOM_OF_PIPE_TS, 0,
> -  EOP_DATA_SEL_VALUE_32BIT, va, 2, 
> value);
> +  EOP_DATA_SEL_VALUE_32BIT, va, 2, 
> value,
> +  cmd_buffer->gfx9_eop_bug_va);
> }
>  
> assert(cmd_buffer->cs->cdw <= cdw_max);
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 73c48cef1f..1c0a50c82f 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -2240,7 +2240,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
>RADV_CMD_FLAG_INV_SMEM_L1 |
>RADV_CMD_FLAG_INV_VMEM_L1 |
>RADV_CMD_FLAG_INV_GLOBAL_L2 |
> -  
> RADV_CMD_FLAG_START_PIPELINE_STATS);
> +  
> RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
> } else if (i == 1) {
> si_cs_emit_cache_flush(cs,
>
> queue->device->physical_device->rad_info.chip_class,
> @@ -2251,7 +2251,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
>RADV_CMD_FLAG_INV_SMEM_L1 |
>RADV_CMD_FLAG_INV_VMEM_L1 |
>RADV_CMD_FLAG_INV_GLOBAL_L2 |
> -  
> RADV_CMD_FLAG_START_PIPELINE_STATS);
> +  
> RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
> }
>  
> if (!queue->device->ws->cs_finalize(cs))
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 4e4b3a6037..96218f4be2 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1041,6 +1041,7 @@ struct radv_cmd_buffer {
> uint32_t gfx9_fence_offset;
> struct radeon_winsys_bo *gfx9_fence_bo;
> uint32_t gfx9_fence_idx;
> +   uint64_t gfx9_eop_bug_va;
>  
> /**
>  * Whether a query pool has been 

Re: [Mesa-dev] [PATCH] meson: Move xvmc test tools from unit tests to installed tools.

[Dylan Baker]

Reviewed-by: Dylan Baker 

Quoting Eric Anholt (2018-07-12 11:44:45)
> These are not unit tests, as they rely on the host's XVMC and some user
> configuration.  Switch them over to being general installed tools, to fix
> unit testing.
> 
> Fixes: 22a817af8a89 ("meson: build gallium xvmc state tracker")
> ---
>  meson.build |  2 +-
>  meson_options.txt   |  2 +-
>  src/gallium/state_trackers/xvmc/meson.build | 30 +
>  3 files changed, 15 insertions(+), 19 deletions(-)
> 
> diff --git a/meson.build b/meson.build
> index 7d12af3d5108..e05645cbf39b 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -58,7 +58,7 @@ with_osmesa = get_option('osmesa')
>  with_swr_arches = get_option('swr-arches')
>  with_tools = get_option('tools')
>  if with_tools.contains('all')
> -  with_tools = ['freedreno', 'glsl', 'intel', 'nir', 'nouveau']
> +  with_tools = ['freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'xvmc']
>  endif
>  
>  dri_drivers_path = get_option('dri-drivers-path')
> diff --git a/meson_options.txt b/meson_options.txt
> index 5de73536bf7d..5bb560b61fb0 100644
> --- a/meson_options.txt
> +++ b/meson_options.txt
> @@ -295,7 +295,7 @@ option(
>'tools',
>type : 'array',
>value : [],
> -  choices : ['freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'all'],
> +  choices : ['freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'xvmc', 'all'],
>description : 'List of tools to build.',
>  )
>  option(
> diff --git a/src/gallium/state_trackers/xvmc/meson.build 
> b/src/gallium/state_trackers/xvmc/meson.build
> index 2c98b0290d99..d120d533eef6 100644
> --- a/src/gallium/state_trackers/xvmc/meson.build
> +++ b/src/gallium/state_trackers/xvmc/meson.build
> @@ -27,31 +27,27 @@ libxvmc_st = static_library(
>  )
>  
>  # These tests will not work without a working xvmc configuration. 
> -if with_tests
> +if with_tools.contains('xvmc')
>dep_xvmcw = cc.find_library('XvMCW')
>dep_real_xvmc = dependency('xvmc')
>foreach x : ['context', 'surface', 'subpicture', 'blocks', 'rendering']
>  _name = 'xvmc_@0@'.format(x)
> -test(
> -  _name,
> -  executable(
> -_name,
> -files('tests/test_@0@.c'.format(x), 'tests/testlib.c'), 
> -dependencies : [
> -  dep_real_xvmc, dep_x11_xcb, dep_xcb, dep_xcb_dri2, dep_xcb_dri3, 
> dep_xvmcw,
> -],
> -  )
> -)
> -  endforeach
> -
> -  test(
> -'xvmc_bench',
>  executable(
> -  'xvmc_bench',
> -  files('tests/xvmc_bench.c', 'tests/testlib.c'), 
> +  _name,
> +  files('tests/test_@0@.c'.format(x), 'tests/testlib.c'),
>dependencies : [
>  dep_real_xvmc, dep_x11_xcb, dep_xcb, dep_xcb_dri2, dep_xcb_dri3, 
> dep_xvmcw,
>],
> +  install: true,
>  )
> +  endforeach
> +
> +  executable(
> +'xvmc_bench',
> +files('tests/xvmc_bench.c', 'tests/testlib.c'),
> +dependencies : [
> +  dep_real_xvmc, dep_x11_xcb, dep_xcb, dep_xcb_dri2, dep_xcb_dri3, 
> dep_xvmcw,
> +],
> +install: true,
>)
>  endif
> -- 
> 2.18.0
> 


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Re: [Mesa-dev] [PATCH v2] vulkan: Fix compilation on older platforms

[Dylan Baker]

Quoting Danylo Piliaiev (2018-07-12 06:09:57)
> Make xlease automatically enabled only if xcb-randr >= 1.13,
> check its version if manually enabled.
> 
> Enable VK_EXT_display_control only when libdrm >= 2.4.89
> 
> Check for DRM_EVENT_CONTEXT_VERSION >= 4 to use sequence_handler.
> 
> Add support for 'protect' attribute to anv_entrypoints_gen.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107170
>   https://bugs.freedesktop.org/show_bug.cgi?id=106972
>   https://bugs.freedesktop.org/show_bug.cgi?id=107176
> 
> v2: - Add 'protect="VK_USE_DISPLAY_CONTROL"' attribute to
>VK_EXT_display_control in vk.xml
> - Add support for 'protect' attribute to anv_entrypoints_gen
>(copied from radv_entrypoints_gen)
> - Turn #if into #ifdef
> - Remove unnecessary pkg-config call from meson build (Dylan Baker)
> 
> Signed-off-by: Danylo Piliaiev 
> ---
> Other vulkan extensions are gated behind platforms: wayland, xlib, ...
> This one depends on library version and I hope I handled it right,
> did I took the right approach?
> 
> Also what if extension requires both platform and libary version?
> Should *_entrypoints_gen be able to support several defines per extension?
> 
>  configure.ac| 29 -
>  meson.build | 10 -
>  src/amd/vulkan/radv_extensions.py   |  9 +++-
>  src/amd/vulkan/radv_wsi_display.c   |  5 ++---
>  src/intel/vulkan/anv_entrypoints_gen.py |  7 ++
>  src/intel/vulkan/anv_extensions.py  |  2 +-
>  src/intel/vulkan/anv_extensions_gen.py  |  7 ++
>  src/intel/vulkan/anv_wsi_display.c  |  4 ++--
>  src/vulkan/registry/vk.xml  |  2 +-
>  src/vulkan/wsi/wsi_common_display.c |  8 +--
>  src/vulkan/wsi/wsi_common_display.h |  3 ++-
>  11 files changed, 59 insertions(+), 27 deletions(-)
> 
> diff --git a/configure.ac b/configure.ac
> index f135d05736..0b04525014 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -82,6 +82,8 @@ LIBDRM_FREEDRENO_REQUIRED=2.4.92
>  LIBDRM_ETNAVIV_REQUIRED=2.4.89
>  LIBDRM_VC4_REQUIRED=2.4.89
>  
> +LIBDRM_CRT_SEQUENCE_REQUIRED=2.4.89
> +
>  dnl Versions for external dependencies
>  DRI2PROTO_REQUIRED=2.8
>  GLPROTO_REQUIRED=1.4.14
> @@ -97,6 +99,7 @@ XCBDRI2_REQUIRED=1.8
>  XCBDRI3_MODIFIERS_REQUIRED=1.13
>  XCBGLX_REQUIRED=1.8.1
>  XCBPRESENT_MODIFIERS_REQUIRED=1.13
> +XCBRANDR_XLEASE_REQUIRED=1.13
>  XDAMAGE_REQUIRED=1.1
>  XSHMFENCE_REQUIRED=1.1
>  XVMC_REQUIRED=1.0.6
> @@ -1874,20 +1877,6 @@ if test x"$enable_dri3" = xyes; then
>  fi
>  fi
>  
> -
> -if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; 
> then
> -have_xlease=yes
> -else
> -have_xlease=no
> -fi
> -
> -if test x"$have_xlease" = xyes; then
> -randr_modules="x11-xcb xcb-randr"
> -PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
> -xlib_randr_modules="xrandr"
> -PKG_CHECK_MODULES([XLIB_RANDR], [$xlib_randr_modules])
> -fi
> -
>  AM_CONDITIONAL(HAVE_PLATFORM_X11, echo "$platforms" | grep -q 'x11')
>  AM_CONDITIONAL(HAVE_PLATFORM_WAYLAND, echo "$platforms" | grep -q 'wayland')
>  AM_CONDITIONAL(HAVE_PLATFORM_DRM, echo "$platforms" | grep -q 'drm')
> @@ -1905,14 +1894,24 @@ xno)
>  ;;
>  *)
>  if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 
> 'drm'; then
> -enable_xlib_lease=yes
> +xlease_modules="x11-xcb xcb-randr >= $XCBRANDR_XLEASE_REQUIRED 
> xrandr"
> +PKG_CHECK_EXISTS([$xlease_modules], [enable_xlib_lease=yes], 
> [enable_xlib_lease=no])
>  else
>  enable_xlib_lease=no
>  fi
>  esac
>  
> +if test x"$enable_xlib_lease" = xyes; then
> +randr_modules="x11-xcb xcb-randr >= $XCBRANDR_XLEASE_REQUIRED"
> +PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
> +xlib_randr_modules="xrandr"
> +PKG_CHECK_MODULES([XLIB_RANDR], [$xlib_randr_modules])
> +fi
> +
>  AM_CONDITIONAL(HAVE_XLIB_LEASE, test "x$enable_xlib_lease" = xyes)
>  
> +PKG_CHECK_EXISTS([libdrm >= $LIBDRM_CRT_SEQUENCE_REQUIRED], 
> [DEFINES="${DEFINES} -DVK_USE_DISPLAY_CONTROL"], [])
> +
>  dnl
>  dnl More DRI setup
>  dnl
> diff --git a/meson.build b/meson.build
> index 7d12af3d51..902074819c 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -1088,6 +1088,8 @@ _drm_freedreno_ver = '2.4.92'
>  _drm_intel_ver = '2.4.75'
>  _drm_ver = '2.4.75'
>  
> +_drm_crt_sequence_ver = '2.4.89'
> +
>  _libdrm_checks = [
>['intel', with_dri_i915 or with_gallium_i915],
>['amdgpu', with_amd_vk or with_gallium_radeonsi],
> @@ -1361,11 +1363,17 @@ if with_platform_x11
>  dep_xcb_xfixes = dependency('xcb-xfixes')
>endif
>if with_xlib_lease
> -dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.12')
> +dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.13')
>  dep_xlib_xrandr = dependency('xrandr', version : '>= 1.3')
>endif
>  endif
>  
> +if with_any_vk
> +  if dep_libdrm.version().version_compare('>= ' + 

Re: [Mesa-dev] [PATCH 2/2] u_blitter: Add an option to draw the triangles using an index buffer.

[Eric Anholt]

Roland Scheidegger  writes:

> Am 12.07.2018 um 00:05 schrieb Eric Anholt:
>> For V3D, the HW will interpolate slightly differently along the shared
>> edge of the trifan.  The conformance tests manage to catch this in the
>> nearest_consistency_* group.  To get interpolation to match, we need the
>> last vertex of the triangle to be shared.
>> 
>> I first tried implementing draw_rectangle to do triangles instead, but
>> that was quite a bit (147 lines) of code duplication from u_blitter, and
>> this seems much simpler and less likely to break as u_blitter changes.
>
> I'm curious, how does interpolation work on that hw?
> Does it use the provoking vertex as some sort of reference? If so would
> it actually work if you switched to provoking vertex first (if you can)?
> (But I'm really just curious, the patch looks alright to me.)

As far as I know, provoking vertex is just about where flat shading
comes from.  I tried forcing it on/off, and got no change in
rasterization.


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[Mesa-dev] [PATCH] intel: tools: Fix uninitialized variable warnings in intel_dump_gpu.

[Eric Anholt]

---
 src/intel/tools/intel_dump_gpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/tools/intel_dump_gpu.c b/src/intel/tools/intel_dump_gpu.c
index 1201fa35ae0c..766ba662d910 100644
--- a/src/intel/tools/intel_dump_gpu.c
+++ b/src/intel/tools/intel_dump_gpu.c
@@ -728,6 +728,8 @@ aub_dump_execlist(uint64_t batch_offset, int ring_flag)
   status_reg = EXECLIST_STATUS_BCSUNIT;
   control_reg = EXECLIST_CONTROL_BCSUNIT;
   break;
+   default:
+  unreachable("unknown ring");
}
 
mem_trace_memory_write_header_out(ring_addr, 16,
-- 
2.18.0

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[Mesa-dev] [PATCH] meson: Move xvmc test tools from unit tests to installed tools.

[Eric Anholt]

These are not unit tests, as they rely on the host's XVMC and some user
configuration.  Switch them over to being general installed tools, to fix
unit testing.

Fixes: 22a817af8a89 ("meson: build gallium xvmc state tracker")
---
 meson.build |  2 +-
 meson_options.txt   |  2 +-
 src/gallium/state_trackers/xvmc/meson.build | 30 +
 3 files changed, 15 insertions(+), 19 deletions(-)

diff --git a/meson.build b/meson.build
index 7d12af3d5108..e05645cbf39b 100644
--- a/meson.build
+++ b/meson.build
@@ -58,7 +58,7 @@ with_osmesa = get_option('osmesa')
 with_swr_arches = get_option('swr-arches')
 with_tools = get_option('tools')
 if with_tools.contains('all')
-  with_tools = ['freedreno', 'glsl', 'intel', 'nir', 'nouveau']
+  with_tools = ['freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'xvmc']
 endif
 
 dri_drivers_path = get_option('dri-drivers-path')
diff --git a/meson_options.txt b/meson_options.txt
index 5de73536bf7d..5bb560b61fb0 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -295,7 +295,7 @@ option(
   'tools',
   type : 'array',
   value : [],
-  choices : ['freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'all'],
+  choices : ['freedreno', 'glsl', 'intel', 'nir', 'nouveau', 'xvmc', 'all'],
   description : 'List of tools to build.',
 )
 option(
diff --git a/src/gallium/state_trackers/xvmc/meson.build 
b/src/gallium/state_trackers/xvmc/meson.build
index 2c98b0290d99..d120d533eef6 100644
--- a/src/gallium/state_trackers/xvmc/meson.build
+++ b/src/gallium/state_trackers/xvmc/meson.build
@@ -27,31 +27,27 @@ libxvmc_st = static_library(
 )
 
 # These tests will not work without a working xvmc configuration. 
-if with_tests
+if with_tools.contains('xvmc')
   dep_xvmcw = cc.find_library('XvMCW')
   dep_real_xvmc = dependency('xvmc')
   foreach x : ['context', 'surface', 'subpicture', 'blocks', 'rendering']
 _name = 'xvmc_@0@'.format(x)
-test(
-  _name,
-  executable(
-_name,
-files('tests/test_@0@.c'.format(x), 'tests/testlib.c'), 
-dependencies : [
-  dep_real_xvmc, dep_x11_xcb, dep_xcb, dep_xcb_dri2, dep_xcb_dri3, 
dep_xvmcw,
-],
-  )
-)
-  endforeach
-
-  test(
-'xvmc_bench',
 executable(
-  'xvmc_bench',
-  files('tests/xvmc_bench.c', 'tests/testlib.c'), 
+  _name,
+  files('tests/test_@0@.c'.format(x), 'tests/testlib.c'),
   dependencies : [
 dep_real_xvmc, dep_x11_xcb, dep_xcb, dep_xcb_dri2, dep_xcb_dri3, 
dep_xvmcw,
   ],
+  install: true,
 )
+  endforeach
+
+  executable(
+'xvmc_bench',
+files('tests/xvmc_bench.c', 'tests/testlib.c'),
+dependencies : [
+  dep_real_xvmc, dep_x11_xcb, dep_xcb, dep_xcb_dri2, dep_xcb_dri3, 
dep_xvmcw,
+],
+install: true,
   )
 endif
-- 
2.18.0

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Re: [Mesa-dev] [PATCH 2/3] i965/miptree: Drop an if case from retile_as_linear

[Chris Wilson]

Quoting Nanley Chery (2018-07-12 18:28:15)
> Drop an if statement whose predicate never evaluates to true. row_pitch
> belongs to a surface with non-linear tiling. According to
> isl_calc_tiled_min_row_pitch, the pitch is a multiple of the tile width.
> By looking at isl_tiling_get_info, we see that non-linear tilings have
> widths greater than or equal to 128B.

Yup, we only have non-linear at this point and pitch has to a multiple
of tiles.
 
> Cc: 
Reviewed-by: Chris Wilson 
-Chris
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Re: [Mesa-dev] [PATCH 3/3] i965/miptree: Use the correct BLT pitch

[Chris Wilson]

Quoting Nanley Chery (2018-07-12 18:28:16)
> Retile miptrees to a linear tiling less often. Retiling can cause issues
> with imported BOs.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106738
> Suggested-by: Chris Wilson 
> Cc: 
Reviewed-by: Chris Wilson 
-Chris
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Re: [Mesa-dev] [PATCH 1/3] i965: Make blt_pitch public

[Chris Wilson]

Quoting Nanley Chery (2018-07-12 18:28:14)
> We'd like to reuse this helper.
> 
> Cc: 
Reviewed-by: Chris Wilson 
-Chris
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Re: [Mesa-dev] [PATCH] anv: Restrict the nuber of color regions to those actually written

[Caio Marcelo de Oliveira Filho]

On Sat, Jul 07, 2018 at 09:35:52AM -0700, Jason Ekstrand wrote:
> On Thu, Jul 5, 2018 at 6:34 PM Caio Marcelo de Oliveira Filho <
> caio.olive...@intel.com> wrote:
> 
> > On Wed, Jun 27, 2018 at 07:00:56PM -0700, Jason Ekstrand wrote:
> > > The back-end compiler emits the number of color writes specified by
> > > wm_prog_key::nr_color_regions regardless of what nir_store_outputs we
> > > have.  Once we've gone through and figured out which render targets
> > > actually exist and are written by the shader, we should restrict the key
> > > to avoid extra RT write messages.
> > > ---
> > >  src/intel/vulkan/anv_pipeline.c | 5 +
> > >  1 file changed, 5 insertions(+)

Minor: there's a typo in the commit title.
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[Mesa-dev] [PATCH 1/3] i965: Make blt_pitch public

[Nanley Chery]

We'd like to reuse this helper.

Cc: 
---
 src/mesa/drivers/dri/i965/intel_blit.c| 12 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 10 ++
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index dcecab677e4..ec875c8fa23 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -121,15 +121,6 @@ set_blitter_tiling(struct brw_context *brw,
  SET_BLITTER_TILING(brw, false, false); \
   ADVANCE_BATCH()
 
-static int
-blt_pitch(struct intel_mipmap_tree *mt)
-{
-   int pitch = mt->surf.row_pitch;
-   if (mt->surf.tiling != ISL_TILING_LINEAR)
-  pitch /= 4;
-   return pitch;
-}
-
 bool
 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
 {
@@ -403,7 +394,8 @@ emit_miptree_blit(struct brw_context *brw,
 * for linear surfaces and DWords for tiled surfaces.  So the maximum
 * pitch is 32k linear and 128k tiled.
 */
-   if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
+   if (intel_miptree_blt_pitch(src_mt) >= 32768 ||
+   intel_miptree_blt_pitch(dst_mt) >= 32768) {
   perf_debug("Falling back due to >= 32k/128k pitch\n");
   return false;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 241832f686f..13a9cb9b605 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -741,6 +741,16 @@ intel_miptree_set_depth_clear_value(struct brw_context 
*brw,
 struct intel_mipmap_tree *mt,
 float clear_value);
 
+
+static inline int
+intel_miptree_blt_pitch(struct intel_mipmap_tree *mt)
+{
+   int pitch = mt->surf.row_pitch;
+   if (mt->surf.tiling != ISL_TILING_LINEAR)
+  pitch /= 4;
+   return pitch;
+}
+
 #ifdef __cplusplus
 }
 #endif
-- 
2.18.0

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[Mesa-dev] [PATCH 2/3] i965/miptree: Drop an if case from retile_as_linear

[Nanley Chery]

Drop an if statement whose predicate never evaluates to true. row_pitch
belongs to a surface with non-linear tiling. According to
isl_calc_tiled_min_row_pitch, the pitch is a multiple of the tile width.
By looking at isl_tiling_get_info, we see that non-linear tilings have
widths greater than or equal to 128B.

Cc: 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index af67191b985..53e01120a92 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -518,10 +518,6 @@ need_to_retile_as_linear(struct brw_context *brw, unsigned 
row_pitch,
if (tiling == ISL_TILING_LINEAR)
   return false;
 
-/* If the width is much smaller than a tile, don't bother tiling. */
-   if (row_pitch < 64)
-  return true;
-
if (ALIGN(row_pitch, 512) >= 32768) {
   perf_debug("row pitch %u too large to blit, falling back to untiled",
  row_pitch);
-- 
2.18.0

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[Mesa-dev] [PATCH 3/3] i965/miptree: Use the correct BLT pitch

[Nanley Chery]

Retile miptrees to a linear tiling less often. Retiling can cause issues
with imported BOs.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106738
Suggested-by: Chris Wilson 
Cc: 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 53e01120a92..1ddb945b085 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -509,7 +509,7 @@ free_aux_state_map(enum isl_aux_state **state)
 }
 
 static bool
-need_to_retile_as_linear(struct brw_context *brw, unsigned row_pitch,
+need_to_retile_as_linear(struct brw_context *brw, unsigned blt_pitch,
  enum isl_tiling tiling, unsigned samples)
 {
if (samples > 1)
@@ -518,9 +518,9 @@ need_to_retile_as_linear(struct brw_context *brw, unsigned 
row_pitch,
if (tiling == ISL_TILING_LINEAR)
   return false;
 
-   if (ALIGN(row_pitch, 512) >= 32768) {
-  perf_debug("row pitch %u too large to blit, falling back to untiled",
- row_pitch);
+   if (blt_pitch >= 32768) {
+  perf_debug("blt pitch %u too large to blit, falling back to untiled",
+ blt_pitch);
   return true;
}
 
@@ -600,7 +600,7 @@ make_surface(struct brw_context *brw, GLenum target, 
mesa_format format,
bool is_depth_stencil =
   mt->surf.usage & (ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_DEPTH_BIT);
if (!is_depth_stencil) {
-  if (need_to_retile_as_linear(brw, mt->surf.row_pitch,
+  if (need_to_retile_as_linear(brw, intel_miptree_blt_pitch(mt),
mt->surf.tiling, mt->surf.samples)) {
  init_info.tiling_flags = 1u << ISL_TILING_LINEAR;
  if (!isl_surf_init_s(>isl_dev, >surf, _info))
@@ -3577,7 +3577,7 @@ can_blit_slice(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int slice)
 {
/* See intel_miptree_blit() for details on the 32k pitch limit. */
-   if (mt->surf.row_pitch >= 32768)
+   if (intel_miptree_blt_pitch(mt) >= 32768)
   return false;
 
return true;
-- 
2.18.0

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Re: [Mesa-dev] [PATCH] anv: Restrict the nuber of color regions to those actually written

[Caio Marcelo de Oliveira Filho]

> > Question: earlier in the code we call
> >
> >populate_wm_prog_key(pipeline, info, );
> >
> > which does
> >
> >key->nr_color_regions = pipeline->subpass->color_count;
> >
> >key->replicate_alpha = key->nr_color_regions > 1 &&
> >   info->pMultisampleState &&
> >   info->pMultisampleState->alphaToCoverageEnable;
> >
> > so key->replicate_alpha is calculated based on the old value. Should
> > this be (re)calculated using the new value?
> >
> 
> We could but it would have no effect.  100% of the uses of replicate_alpha
> in the back-end have it ANDed with inst->target > 0.

If it's not effectful, maybe we could remove the
"key->nr_color_regions > 1 &&" from the definition of replicate_alpha
then?


Thanks,
Caio
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Re: [Mesa-dev] [PATCH 1/3] egl/android: Delete set_damage_region from egl dri vtbl

[Harish Krupo]

Eric Anholt  writes:

> Harish Krupo  writes:
>
>> Hi Eric,
>>
>> Eric Anholt  writes:
>>
>>> Harish Krupo  writes:
>>>
 The intension of the KHR_partial_update was not to send the damage back
 to the platform but to send the damage to the driver to ensure that the
 following rendering could be restricted to those regions.
 This patch removes the set_damage_region from the egl_dri vtbl and all
 the platfrom_*.c files.
 Then upcomming patches add a new dri2 interface for the drivers to
 implement

 Signed-off-by: Harish Krupo 
>>>
>>> Why shouldn't the platform know about the damage region in a swap, if
>>> it's available?  It looks like it was successfully used for Android, and
>>> we should be using it for Present as well.
>>
>> From the spec [1], the damage region referred to by partial_update spec is
>> the damaged part of the buffer when it is used again. The damage that the
>> compositor/platform needs to know is the damage between the (n-1)th
>> frame and the nth frame. Quoting from the spec:
>> "   The surface damage for frame n is the difference between frame n and 
>> frame
>> (n-1), and represents the area that a compositor must recompose."
>> This is the damage referred to by the swap_buffers_with_damage spec [2],
>> whereas the partial_update damage region's objective is to restrict the 
>> subsequent
>> rendering operations on the back buffer, to only those regions which have 
>> changed since
>> that buffer was last used. This information is available as the buffer
>> age. Some more information: [3].
>
> OK, let's document that in the new internal API you're adding then.
> Things I'd want to know as an implementer of the hook:
>
> 1) Am I guaranteed that it's called before the frame is started?
>

No. When no damage region is set, the whole surface should be considered
damaged. As a matter of fact, the damage region is set to full surface
when the frame boundary is reached (i.e. swapbuffersXXX is called).

> 2) Is the behavior if the client draws outside of the partial update
> damage region defined?  (is it "the driver must not change pixels
> outside of the partial region" or "the driver might not change pixels
> outside of the partial region")
>

If I have understood the spec correctly, then the damage regions set are
a hint to the driver so that it can optimize the rendering by
restricting the client's drawing commands to only the damaged region.
In the current implementation, although the damage regions are sent back
to the compositor instead of sending it to the driver, no issues are
observed with the rendered output and it passes deqp tests. This
supports the argument that the damages are only a hint.

> 3) Is the client guaranteed to fully initialize pixels in the partial
> update region, or might it depend on previous contents?

If the above argument is right then it means that the client would
actually initialize the pixels of the full buffer but expect that the
driver renders only the damaged regions.

Thank you
Regards
Harish Krupo
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Re: [Mesa-dev] [PATCH] util/rb_tree: Fix a compiler warning

[Caio Marcelo de Oliveira Filho]

Reviewed-by: Caio Marcelo de Oliveira Filho 

On Wed, Jul 11, 2018 at 10:49:49PM -0700, Jason Ekstrand wrote:
> Gcc 8 warns "cast to pointer from integer of different size" in 32-bit
> builds.
> ---
>  src/util/rb_tree.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/util/rb_tree.h b/src/util/rb_tree.h
> index e8750b32d0e..c77e9255ea2 100644
> --- a/src/util/rb_tree.h
> +++ b/src/util/rb_tree.h
> @@ -55,7 +55,7 @@ struct rb_node {
>  static inline struct rb_node *
>  rb_node_parent(struct rb_node *n)
>  {
> -return (struct rb_node *)(n->parent & ~1ull);
> +return (struct rb_node *)(n->parent & ~(uintptr_t)1);
>  }
>  
>  /** A red-black tree
> -- 
> 2.17.1
> 
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[Mesa-dev] [Bug 107022] [RADV] The Witcher 3: Trembling of trees

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107022

--- Comment #14 from Samuel Pitoiset  ---
See https://bugs.freedesktop.org/show_bug.cgi?id=107156#c5

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Re: [Mesa-dev] [PATCH 2/2] intel/blorp: Take an explicit filter parameter in blorp_blit

[Jason Ekstrand]

On Wed, Jun 27, 2018 at 6:08 PM Chad Versace 
wrote:

> On Tue 26 Jun 2018, Jason Ekstrand wrote:
> > This lets us move the glBlitFramebuffer nonsense into the GL driver and
> > make the usage of BLORP mutch more explicit and obvious as to what it's
> > doing.
> > ---
> >  src/intel/blorp/blorp.h   |  3 +-
> >  src/intel/blorp/blorp_blit.c  | 44 ++-
> >  src/intel/vulkan/anv_blorp.c  | 34 +++
> >  src/mesa/drivers/dri/i965/brw_blorp.c | 63 ++-
> >  4 files changed, 93 insertions(+), 51 deletions(-)
>
> > @@ -2253,39 +2250,6 @@ blorp_blit(struct blorp_batch *batch,
> >wm_prog_key.x_scale = 2.0f;
> > wm_prog_key.y_scale = params.src.surf.samples / wm_prog_key.x_scale;
> >
> > -   const bool bilinear_filter = filter == GL_LINEAR &&
> > -params.src.surf.samples <= 1 &&
> > -params.dst.surf.samples <= 1;
> > -
> > -   /* We are downsampling a non-integer color buffer, so blend.
> > -*
> > -* Regarding integer color buffers, the OpenGL ES 3.2 spec says:
> > -*
> > -*"If the source formats are integer types or stencil values, a
> > -*single sample's value is selected for each pixel."
> > -*
> > -* This implies we should not blend in that case.
> > -*/
> > -   const bool blend =
> > -  (params.src.surf.usage & ISL_SURF_USAGE_DEPTH_BIT) == 0 &&
> > -  (params.src.surf.usage & ISL_SURF_USAGE_STENCIL_BIT) == 0 &&
> > -  !isl_format_has_int_channel(params.src.surf.format) &&
> > -  params.src.surf.samples > 1 &&
> > -  params.dst.surf.samples <= 1;
> > -
> > -   if (blend && !blit_scaled) {
> > -  wm_prog_key.filter = BLORP_FILTER_AVERAGE;
> > -   } else if (blend && blit_scaled) {
> > -  wm_prog_key.filter = BLORP_FILTER_BILINEAR;
> > -   } else if (bilinear_filter) {
> > -  wm_prog_key.filter = BLORP_FILTER_BILINEAR;
> > -   } else {
> > -  if (params.src.surf.samples > 1)
> > - wm_prog_key.filter = BLORP_FILTER_SAMPLE_0;
> > -  else
> > - wm_prog_key.filter = BLORP_FILTER_NEAREST;
> > -   }
> > -
> > params.wm_inputs.rect_grid.x1 =
> >minify(params.src.surf.logical_level0_px.width, src_level) *
> >wm_prog_key.x_scale - 1.0f;
>
> Crazy GL silliness, be gone! You are not welcome here, in this clean,
> pure, do-what-i-say-not-what-i-mean Vulkan driver! Be banished to GL
> silly-land forever!
>
> [snip]
>
> The following two hunks, combined, are large improvements.  It's crazy
> that blorp correctly applied average filtering for multisampled
> non-integer color attachments here *despite* the hardcoded GL_NEAREST in
> hunk #1.
>
> > @@ -1181,7 +1182,7 @@ resolve_surface(struct blorp_batch *batch,
> >ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
> >src_x, src_y, src_x + width, src_y + height,
> >dst_x, dst_y, dst_x + width, dst_y + height,
> > -  0x2600 /* GL_NEAREST */, false, false);
> > +  filter, false, false);
> >  }
> >
> >  static void
> > @@ -1220,13 +1221,22 @@ resolve_image(struct anv_device *device,
> >  dst_surf.aux_usage,
> >  dst_level, dst_layer, 1);
> >
> > +  enum blorp_filter filter;
> > +  if ((src_surf.surf->usage & ISL_SURF_USAGE_DEPTH_BIT) ||
> > +  (src_surf.surf->usage & ISL_SURF_USAGE_STENCIL_BIT) ||
> > +  isl_format_has_int_channel(src_surf.surf->format)) {
> > + filter = BLORP_FILTER_SAMPLE_0;
> > +  } else {
> > + filter = BLORP_FILTER_AVERAGE;
> > +  }
> > +
> >assert(!src_image->format->can_ycbcr);
> >assert(!dst_image->format->can_ycbcr);
> >
> >resolve_surface(batch,
> >_surf, src_level, src_layer,
> >_surf, dst_level, dst_layer,
> > -  src_x, src_y, dst_x, dst_y, width, height);
> > +  src_x, src_y, dst_x, dst_y, width, height,
> filter);
> > }
> >  }
> >
> > @@ -1341,6 +1351,13 @@ anv_cmd_buffer_resolve_subpass(struct
> anv_cmd_buffer *cmd_buffer)
> >   assert(src_iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT &&
> >  dst_iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT);
> >
> > + enum blorp_filter filter;
> > + if
> (isl_format_has_int_channel(src_iview->planes[0].isl.format)) {
> > +filter = BLORP_FILTER_SAMPLE_0;
> > + } else {
> > +filter = BLORP_FILTER_AVERAGE;
> > + }
> > +
> >   struct blorp_surf src_surf, dst_surf;
> >   get_blorp_surf_for_anv_image(cmd_buffer->device,
> src_iview->image,
> >VK_IMAGE_ASPECT_COLOR_BIT,
>
> [snip]
>
> > @@ -324,6 +324,65 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> >src_format = dst_format = MESA_FORMAT_R_FLOAT32;
> >  

Re: [Mesa-dev] [PATCH 1/2] intel/blorp: Add a blorp_filter enum for use in blorp_blit

[Jason Ekstrand]

On Wed, Jun 27, 2018 at 5:55 PM Chad Versace 
wrote:

> On Tue 26 Jun 2018, Jason Ekstrand wrote:
> > At the moment, this is entirely internal but we'll expose it to clients
> > of the BLORP API in the next commit.
> > ---
> >  src/intel/blorp/blorp.h  |   8 ++
> >  src/intel/blorp/blorp_blit.c | 212 +++
> >  src/intel/blorp/blorp_priv.h |  12 +-
> >  3 files changed, 123 insertions(+), 109 deletions(-)
>
> Yup, I still read this list.
>

\o/


> This patch makes the code easier to reason about. I like it.
>
> [snip]
>
> > +   case BLORP_FILTER_BILINEAR:
> > +  assert(!key->src_tiled_w);
> > +  assert(key->tex_samples == key->src_samples);
> > +  assert(key->tex_layout == key->src_layout);
>
> What guarantees !key->src_tiled_w ? I can't deduce it from the patch.
>

That's stencil and you can't do a filtered scaled blit with stencil, only
nearest.  I believe this is required/checked fairly high up in the GL API
area.


> From my understanding of the patch, the patch allows the deduction
> below. What is the missing step to !key->src_tiled_w? Does GL not allow
> GL_LINEAR on stencil buffers? (If it does, though, then GL is dumb).
>

Correct.  Which means that !stencil || LINEAR -> !stencil


> (key.filter == BLORP_FILTER_BILINEAR) <-> ((blend && blit_scaled) ||
> bilinear_filter)
>-> (blend || bilinear_filter)
>-> (!(src_surf.usage &
> ISL_SURF_USAGE_STENCIL_BIT) || (gl_filter == GL_LINEAR))
>?
>-> !stencil
>-> !key->src_tiled_w
> [snip]
>
> > +   case BLORP_FILTER_AVERAGE:
> > +  assert(!key->src_tiled_w);
> > +  assert(key->tex_samples == key->src_samples);
> > +  assert(key->tex_layout == key->src_layout);
> > +
>
> I expected to see assert(key->src_samples > 1) in this case.
> Just an observation.
>
> [snip]
>
> > +   /* We are downsampling a non-integer color buffer, so blend.
>
> This phrase is no longer inside an if.  It should say "If we are...,
> then blend.". Or "Blend if we are...".
>

I've changed it to "If we are..."


> > +*
> > +* Regarding integer color buffers, the OpenGL ES 3.2 spec says:
> > +*
> > +*"If the source formats are integer types or stencil values, a
> > +*single sample's value is selected for each pixel."
> > +*
> > +* This implies we should not blend in that case.
> > +*/
> > +   const bool blend =
> > +  (params.src.surf.usage & ISL_SURF_USAGE_DEPTH_BIT) == 0 &&
> > +  (params.src.surf.usage & ISL_SURF_USAGE_STENCIL_BIT) == 0 &&
> > +  !isl_format_has_int_channel(params.src.surf.format) &&
> > +  params.src.surf.samples > 1 &&
> > +  params.dst.surf.samples <= 1;
>
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Re: [Mesa-dev] [PATCH 2/3] docs/features: Move the Vulkan 1.1 extensions to the 1.1 section

[Bas Nieuwenhuizen]

On Thu, Jul 12, 2018 at 5:26 PM, Jason Ekstrand  wrote:
> On Thu, Jul 12, 2018 at 2:30 AM Bas Nieuwenhuizen 
> wrote:
>>
>> On Thu, Jul 12, 2018 at 1:03 AM, Jason Ekstrand 
>> wrote:
>> > While we're at it, add some extensions we missed along the way like the
>> > VK_KHR_maintenanceN extensions.
>> > ---
>> >  docs/features.txt | 39 +--
>> >  1 file changed, 25 insertions(+), 14 deletions(-)
>> >
>> > diff --git a/docs/features.txt b/docs/features.txt
>> > index 0705ff9974b..61ca4d2da65 100644
>> > --- a/docs/features.txt
>> > +++ b/docs/features.txt
>> > @@ -354,39 +354,50 @@ we DO NOT WANT implementations of these extensions
>> > for Mesa.
>> >
>> >  Vulkan 1.0 -- all DONE: anv, radv
>> >
>> > -Khronos extensions that are not part of any Vulkan version:
>> > +Vulkan 1.1 -- all DONE: anv, radv
>> > +
>> >VK_KHR_16bit_storage  in progress
>> > (Alejandro)
>> > -  VK_KHR_android_surfacenot started
>> > +  VK_KHR_bind_memory2   DONE (anv,
>> > radv)
>> >VK_KHR_dedicated_allocation   DONE (anv,
>> > radv)
>> >VK_KHR_descriptor_update_template DONE (anv,
>> > radv)
>> > -  VK_KHR_displayDONE (anv,
>> > radv)
>> > -  VK_KHR_display_swapchain  DONE (anv,
>> > radv)
>> > +  VK_KHR_device_group   not started
>> > +  VK_KHR_device_group_creation  not started
>> >VK_KHR_external_fence DONE (anv,
>> > radv)
>> >VK_KHR_external_fence_capabilitiesDONE (anv,
>> > radv)
>> > -  VK_KHR_external_fence_fd  DONE (anv,
>> > radv)
>> > -  VK_KHR_external_fence_win32   not started
>> >VK_KHR_external_memoryDONE (anv,
>> > radv)
>> >VK_KHR_external_memory_capabilities   DONE (anv,
>> > radv)
>> > -  VK_KHR_external_memory_fd DONE (anv,
>> > radv)
>> > -  VK_KHR_external_memory_win32  not started
>> >VK_KHR_external_semaphore DONE (anv,
>> > radv)
>> >VK_KHR_external_semaphore_capabilitiesDONE (anv,
>> > radv)
>> > -  VK_KHR_external_semaphore_fd  DONE (anv,
>> > radv)
>> > -  VK_KHR_external_semaphore_win32   not started
>> >VK_KHR_get_memory_requirements2   DONE (anv,
>> > radv)
>> >VK_KHR_get_physical_device_properties2DONE (anv,
>> > radv)
>> > +  VK_KHR_maintenance1   DONE (anv,
>> > radv)
>> > +  VK_KHR_maintenance2   DONE (anv,
>> > radv)
>> > +  VK_KHR_maintenance3   DONE (anv,
>> > radv)
>> > +  VK_KHR_multiview  DONE (anv,
>> > radv)
>> > +  VK_KHR_relaxed_block_layout   DONE (anv,
>> > radv)
>> > +  VK_KHR_sampler_ycbcr_conversion   DONE (anv,
>> > radv)
>>
>> Does it make sense to put radv here? Technically we implemented the
>> extension, but all we implemented was the bit to say "no we don't
>> support that".
>
>
> Probably not.  I'll drop it to just anv.  I figured you had implemented at
> least some features but I guess I guessed wrong. :)  Unfortunately,
> features.txt doesn't map as nicely to Vulkan as it does to GL. :(

Okay, with the errors in patch 3 that I replied to earlier also fixed
this series
is

Reviewed-by: Bas Nieuwenhuizen 

Thanks!

>
>>
>> > +  VK_KHR_shader_draw_parameters DONE (anv,
>> > radv)
>> > +  VK_KHR_storage_buffer_storage_class   DONE (anv,
>> > radv)
>> > +  VK_KHR_variable_pointers  DONE (anv,
>> > radv)
>> > +
>> > +Khronos extensions that are not part of any Vulkan version:
>> > +  VK_KHR_android_surfacenot started
>> > +  VK_KHR_displayDONE (anv,
>> > radv)
>> > +  VK_KHR_display_swapchain  DONE (anv,
>> > radv)
>> > +  VK_KHR_external_fence_fd  DONE (anv,
>> > radv)
>> > +  VK_KHR_external_fence_win32   not started
>> > +  VK_KHR_external_memory_fd DONE (anv,
>> > radv)
>> > +  VK_KHR_external_memory_win32  not started
>> > +  VK_KHR_external_semaphore_fd  DONE (anv,
>> > radv)
>> > +  VK_KHR_external_semaphore_win32   not started
>> >VK_KHR_get_surface_capabilities2  DONE (anv,
>> > radv)
>> >VK_KHR_incremental_presentDONE (anv,
>> > radv)
>> > -  VK_KHR_maintenance1 

[Mesa-dev] [Bug 107022] [RADV] The Witcher 3: Trembling of trees

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107022

--- Comment #13 from zefkerri...@gmail.com ---
(In reply to Samuel Pitoiset from comment #12)
> Bisecting the issue can help.

And what do we need to do for this?

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[Mesa-dev] [Bug 107022] [RADV] The Witcher 3: Trembling of trees

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107022

--- Comment #12 from Samuel Pitoiset  ---
Bisecting the issue can help.

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Re: [Mesa-dev] [PATCH 2/3] docs/features: Move the Vulkan 1.1 extensions to the 1.1 section

[Jason Ekstrand]

On Thu, Jul 12, 2018 at 2:30 AM Bas Nieuwenhuizen 
wrote:

> On Thu, Jul 12, 2018 at 1:03 AM, Jason Ekstrand 
> wrote:
> > While we're at it, add some extensions we missed along the way like the
> > VK_KHR_maintenanceN extensions.
> > ---
> >  docs/features.txt | 39 +--
> >  1 file changed, 25 insertions(+), 14 deletions(-)
> >
> > diff --git a/docs/features.txt b/docs/features.txt
> > index 0705ff9974b..61ca4d2da65 100644
> > --- a/docs/features.txt
> > +++ b/docs/features.txt
> > @@ -354,39 +354,50 @@ we DO NOT WANT implementations of these extensions
> for Mesa.
> >
> >  Vulkan 1.0 -- all DONE: anv, radv
> >
> > -Khronos extensions that are not part of any Vulkan version:
> > +Vulkan 1.1 -- all DONE: anv, radv
> > +
> >VK_KHR_16bit_storage  in progress
> (Alejandro)
> > -  VK_KHR_android_surfacenot started
> > +  VK_KHR_bind_memory2   DONE (anv, radv)
> >VK_KHR_dedicated_allocation   DONE (anv, radv)
> >VK_KHR_descriptor_update_template DONE (anv, radv)
> > -  VK_KHR_displayDONE (anv, radv)
> > -  VK_KHR_display_swapchain  DONE (anv, radv)
> > +  VK_KHR_device_group   not started
> > +  VK_KHR_device_group_creation  not started
> >VK_KHR_external_fence DONE (anv, radv)
> >VK_KHR_external_fence_capabilitiesDONE (anv, radv)
> > -  VK_KHR_external_fence_fd  DONE (anv, radv)
> > -  VK_KHR_external_fence_win32   not started
> >VK_KHR_external_memoryDONE (anv, radv)
> >VK_KHR_external_memory_capabilities   DONE (anv, radv)
> > -  VK_KHR_external_memory_fd DONE (anv, radv)
> > -  VK_KHR_external_memory_win32  not started
> >VK_KHR_external_semaphore DONE (anv, radv)
> >VK_KHR_external_semaphore_capabilitiesDONE (anv, radv)
> > -  VK_KHR_external_semaphore_fd  DONE (anv, radv)
> > -  VK_KHR_external_semaphore_win32   not started
> >VK_KHR_get_memory_requirements2   DONE (anv, radv)
> >VK_KHR_get_physical_device_properties2DONE (anv, radv)
> > +  VK_KHR_maintenance1   DONE (anv, radv)
> > +  VK_KHR_maintenance2   DONE (anv, radv)
> > +  VK_KHR_maintenance3   DONE (anv, radv)
> > +  VK_KHR_multiview  DONE (anv, radv)
> > +  VK_KHR_relaxed_block_layout   DONE (anv, radv)
> > +  VK_KHR_sampler_ycbcr_conversion   DONE (anv, radv)
>
> Does it make sense to put radv here? Technically we implemented the
> extension, but all we implemented was the bit to say "no we don't
> support that".
>

Probably not.  I'll drop it to just anv.  I figured you had implemented at
least some features but I guess I guessed wrong. :)  Unfortunately,
features.txt doesn't map as nicely to Vulkan as it does to GL. :(


> > +  VK_KHR_shader_draw_parameters DONE (anv, radv)
> > +  VK_KHR_storage_buffer_storage_class   DONE (anv, radv)
> > +  VK_KHR_variable_pointers  DONE (anv, radv)
> > +
> > +Khronos extensions that are not part of any Vulkan version:
> > +  VK_KHR_android_surfacenot started
> > +  VK_KHR_displayDONE (anv, radv)
> > +  VK_KHR_display_swapchain  DONE (anv, radv)
> > +  VK_KHR_external_fence_fd  DONE (anv, radv)
> > +  VK_KHR_external_fence_win32   not started
> > +  VK_KHR_external_memory_fd DONE (anv, radv)
> > +  VK_KHR_external_memory_win32  not started
> > +  VK_KHR_external_semaphore_fd  DONE (anv, radv)
> > +  VK_KHR_external_semaphore_win32   not started
> >VK_KHR_get_surface_capabilities2  DONE (anv, radv)
> >VK_KHR_incremental_presentDONE (anv, radv)
> > -  VK_KHR_maintenance1   DONE (anv, radv)
> >VK_KHR_mir_surfacenot started
> >VK_KHR_push_descriptorDONE (anv, radv)
> >VK_KHR_sampler_mirror_clamp_to_edge   DONE (anv, radv)
> > -  VK_KHR_shader_draw_parameters DONE (anv, radv)
> >VK_KHR_shared_presentable_image   not started
> > -  

Re: [Mesa-dev] [PATCH] gallium: Check pipe_screen::resource_changed before dereferencing it

[Lucas Stach]

Am Donnerstag, den 12.07.2018, 16:33 +0200 schrieb Michel Dänzer:
> > From: Michel Dänzer 
> 
> It's optional, only implemented by the etnaviv driver so far.
> 
> Fixes: 501d0edeca32 "st/mesa: call resource_changed when binding a
>  EGLImage to a texture"
> Fixes: a37cf630b4d1 "gallium: add pipe_screen::resource_changed callback
>  wrappers"
> Signed-off-by: Michel Dänzer 

Urgh, thanks for fixing this up.

Reviewed-by: Lucas Stach 

> ---
>  src/gallium/auxiliary/driver_ddebug/dd_screen.c | 3 ++-
>  src/gallium/auxiliary/driver_rbug/rbug_screen.c | 3 ++-
>  src/gallium/auxiliary/driver_trace/tr_screen.c  | 3 ++-
>  src/mesa/state_tracker/st_cb_eglimage.c | 3 ++-
>  4 files changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/src/gallium/auxiliary/driver_ddebug/dd_screen.c 
> b/src/gallium/auxiliary/driver_ddebug/dd_screen.c
> index 5b2be28a969..5f922d884fe 100644
> --- a/src/gallium/auxiliary/driver_ddebug/dd_screen.c
> +++ b/src/gallium/auxiliary/driver_ddebug/dd_screen.c
> @@ -284,7 +284,8 @@ dd_screen_resource_changed(struct pipe_screen *_screen,
>  {
> struct pipe_screen *screen = dd_screen(_screen)->screen;
>  
> -   screen->resource_changed(screen, res);
> +   if (screen->resource_changed)
> +  screen->resource_changed(screen, res);
>  }
>  
>  static void
> diff --git a/src/gallium/auxiliary/driver_rbug/rbug_screen.c 
> b/src/gallium/auxiliary/driver_rbug/rbug_screen.c
> index 2477edbadf0..a1a77add734 100644
> --- a/src/gallium/auxiliary/driver_rbug/rbug_screen.c
> +++ b/src/gallium/auxiliary/driver_rbug/rbug_screen.c
> @@ -222,7 +222,8 @@ rbug_screen_resource_changed(struct pipe_screen *_screen,
> struct pipe_screen *screen = rb_screen->screen;
> struct pipe_resource *resource = rb_resource->resource;
>  
> -   screen->resource_changed(screen, resource);
> +   if (screen->resource_changed)
> +  screen->resource_changed(screen, resource);
>  }
>  
>  static void
> diff --git a/src/gallium/auxiliary/driver_trace/tr_screen.c 
> b/src/gallium/auxiliary/driver_trace/tr_screen.c
> index d5a81249b51..704b2a3c72d 100644
> --- a/src/gallium/auxiliary/driver_trace/tr_screen.c
> +++ b/src/gallium/auxiliary/driver_trace/tr_screen.c
> @@ -444,7 +444,8 @@ trace_screen_resource_changed(struct pipe_screen *_screen,
> trace_dump_arg(ptr, screen);
> trace_dump_arg(ptr, resource);
>  
> -   screen->resource_changed(screen, resource);
> +   if (screen->resource_changed)
> +  screen->resource_changed(screen, resource);
>  
> trace_dump_call_end();
>  }
> diff --git a/src/mesa/state_tracker/st_cb_eglimage.c 
> b/src/mesa/state_tracker/st_cb_eglimage.c
> index 4f33cb4bb06..0db2efc01cf 100644
> --- a/src/mesa/state_tracker/st_cb_eglimage.c
> +++ b/src/mesa/state_tracker/st_cb_eglimage.c
> @@ -229,7 +229,8 @@ st_bind_egl_image(struct gl_context *ctx,
> pipe_resource_reference(>pt, stimg->texture);
> st_texture_release_all_sampler_views(st, stObj);
> pipe_resource_reference(>pt, stObj->pt);
> -   st->pipe->screen->resource_changed(st->pipe->screen, stImage->pt);
> +   if (st->pipe->screen->resource_changed)
> +  st->pipe->screen->resource_changed(st->pipe->screen, stImage->pt);
>  
> stObj->surface_format = stimg->format;
> stObj->level_override = stimg->level;
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[Mesa-dev] [Bug 107022] [RADV] The Witcher 3: Trembling of trees

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107022

--- Comment #11 from zefkerri...@gmail.com ---
(In reply to Samuel Pitoiset from comment #10)
> Definitely not enough of caffeine today. Apparently, the issue is
> SI-specific which means I can't do anything because I don't have the
> hardware. It works fine on Polaris/Vega.

But, can I help you in any way? Or are we finally lost any hope?

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Re: [Mesa-dev] [PATCH] radeonsi: add support for Vega20

[Alex Deucher]

On Wed, Jul 11, 2018 at 4:11 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> ---
>  include/pci_ids/radeonsi_pci_ids.h  | 7 +++
>  src/amd/addrlib/amdgpu_asic_addr.h  | 2 ++
>  src/amd/addrlib/gfx9/gfx9addrlib.cpp| 3 ++-
>  src/amd/addrlib/gfx9/gfx9addrlib.h  | 1 +
>  src/amd/common/ac_llvm_util.c   | 4 +++-
>  src/amd/common/ac_surface.c | 4 
>  src/amd/common/amd_family.h | 1 +
>  src/amd/common/gfx9d.h  | 1 +
>  src/gallium/drivers/radeonsi/si_get.c   | 1 +
>  src/gallium/drivers/radeonsi/si_pipe.c  | 3 ++-
>  src/gallium/drivers/radeonsi/si_state.c | 1 +
>  src/gallium/drivers/radeonsi/si_state_binning.c | 1 +
>  12 files changed, 26 insertions(+), 3 deletions(-)

Reviewed-by: Alex Deucher 

>
> diff --git a/include/pci_ids/radeonsi_pci_ids.h 
> b/include/pci_ids/radeonsi_pci_ids.h
> index 6386d21a19f..c8d30597230 100644
> --- a/include/pci_ids/radeonsi_pci_ids.h
> +++ b/include/pci_ids/radeonsi_pci_ids.h
> @@ -228,11 +228,18 @@ CHIPSET(0x6867, VEGA10)
>  CHIPSET(0x6868, VEGA10)
>  CHIPSET(0x687F, VEGA10)
>  CHIPSET(0x686C, VEGA10)
>
>  CHIPSET(0x69A0, VEGA12)
>  CHIPSET(0x69A1, VEGA12)
>  CHIPSET(0x69A2, VEGA12)
>  CHIPSET(0x69A3, VEGA12)
>  CHIPSET(0x69AF, VEGA12)
>
> +CHIPSET(0x66A0, VEGA20)
> +CHIPSET(0x66A1, VEGA20)
> +CHIPSET(0x66A2, VEGA20)
> +CHIPSET(0x66A3, VEGA20)
> +CHIPSET(0x66A7, VEGA20)
> +CHIPSET(0x66AF, VEGA20)
> +
>  CHIPSET(0x15DD, RAVEN)
> diff --git a/src/amd/addrlib/amdgpu_asic_addr.h 
> b/src/amd/addrlib/amdgpu_asic_addr.h
> index b4b8aecd42d..e5838d42a3c 100644
> --- a/src/amd/addrlib/amdgpu_asic_addr.h
> +++ b/src/amd/addrlib/amdgpu_asic_addr.h
> @@ -80,20 +80,21 @@
>  #define AMDGPU_POLARIS11_RANGE  0x5A, 0x64
>  #define AMDGPU_POLARIS12_RANGE  0x64, 0x6E
>  #define AMDGPU_VEGAM_RANGE  0x6E, 0xFF
>
>  #define AMDGPU_CARRIZO_RANGE0x01, 0x21
>  #define AMDGPU_BRISTOL_RANGE0x10, 0x21
>  #define AMDGPU_STONEY_RANGE 0x61, 0xFF
>
>  #define AMDGPU_VEGA10_RANGE 0x01, 0x14
>  #define AMDGPU_VEGA12_RANGE 0x14, 0x28
> +#define AMDGPU_VEGA20_RANGE 0x28, 0xFF
>
>  #define AMDGPU_RAVEN_RANGE  0x01, 0x81
>
>  #define AMDGPU_EXPAND_FIX(x) x
>  #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
>  #define AMDGPU_IN_RANGE(val, ...)   
> AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
>
>
>  // ASICREV_IS(eRevisionId, revisionName)
>  #define ASICREV_IS(r, rn)  AMDGPU_IN_RANGE(r, 
> AMDGPU_##rn##_RANGE)
> @@ -121,14 +122,15 @@
>  #define ASICREV_IS_VEGAM_P(r)  ASICREV_IS(r, VEGAM)
>
>  #define ASICREV_IS_CARRIZO(r)  ASICREV_IS(r, CARRIZO)
>  #define ASICREV_IS_CARRIZO_BRISTOL(r)  ASICREV_IS(r, BRISTOL)
>  #define ASICREV_IS_STONEY(r)   ASICREV_IS(r, STONEY)
>
>  #define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10)
>  #define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10)
>  #define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
>  #define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
> +#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
>
>  #define ASICREV_IS_RAVEN(r)ASICREV_IS(r, RAVEN)
>
>  #endif // _AMDGPU_ASIC_ADDR_H
> diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp 
> b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> index b88d3243228..ef86c3bc7b5 100644
> --- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> +++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> @@ -1223,20 +1223,21 @@ BOOL_32 Gfx9Lib::HwlInitGlobalParams(
>  ADDR_ASSERT((m_blockVarSizeLog2 == 0) ||
>  ((m_blockVarSizeLog2 >= 17u) && (m_blockVarSizeLog2 <= 
> 20u)));
>  m_blockVarSizeLog2 = Min(Max(17u, m_blockVarSizeLog2), 20u);
>
>  if ((m_rbPerSeLog2 == 1) &&
>  (((m_pipesLog2 == 1) && ((m_seLog2 == 2) || (m_seLog2 == 3))) ||
>   ((m_pipesLog2 == 2) && ((m_seLog2 == 1) || (m_seLog2 == 2)
>  {
>  ADDR_ASSERT(m_settings.isVega10 == FALSE);
>  ADDR_ASSERT(m_settings.isRaven == FALSE);
> +ADDR_ASSERT(m_settings.isVega20 == FALSE);
>
>  if (m_settings.isVega12)
>  {
>  m_settings.htileCacheRbConflict = 1;
>  }
>  }
>  }
>  else
>  {
>  valid = FALSE;
> @@ -1266,21 +1267,21 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
>  UINT_32 uChipRevision)  ///< [in] chip revision defined in 
> "asic_family"_id.h
>  {
>  ChipFamily family = ADDR_CHIP_FAMILY_AI;
>
>  switch (uChipFamily)
>  {
>  case FAMILY_AI:
>  m_settings.isArcticIsland = 1;
>  m_settings.isVega10= ASICREV_IS_VEGA10_P(uChipRevision);
>  m_settings.isVega12= ASICREV_IS_VEGA12_P(uChipRevision);
> -
> +m_settings.isVega20= ASICREV_IS_VEGA20_P(uChipRevision);
>  m_settings.isDce12 = 1;
>
>  

[Mesa-dev] [Bug 107022] [RADV] The Witcher 3: Trembling of trees

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107022

--- Comment #10 from Samuel Pitoiset  ---
Definitely not enough of caffeine today. Apparently, the issue is SI-specific
which means I can't do anything because I don't have the hardware. It works
fine on Polaris/Vega.

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[Mesa-dev] [PATCH] gallium: Check pipe_screen::resource_changed before dereferencing it

[Michel Dänzer]

From: Michel Dänzer 

It's optional, only implemented by the etnaviv driver so far.

Fixes: 501d0edeca32 "st/mesa: call resource_changed when binding a
 EGLImage to a texture"
Fixes: a37cf630b4d1 "gallium: add pipe_screen::resource_changed callback
 wrappers"
Signed-off-by: Michel Dänzer 
---
 src/gallium/auxiliary/driver_ddebug/dd_screen.c | 3 ++-
 src/gallium/auxiliary/driver_rbug/rbug_screen.c | 3 ++-
 src/gallium/auxiliary/driver_trace/tr_screen.c  | 3 ++-
 src/mesa/state_tracker/st_cb_eglimage.c | 3 ++-
 4 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/gallium/auxiliary/driver_ddebug/dd_screen.c 
b/src/gallium/auxiliary/driver_ddebug/dd_screen.c
index 5b2be28a969..5f922d884fe 100644
--- a/src/gallium/auxiliary/driver_ddebug/dd_screen.c
+++ b/src/gallium/auxiliary/driver_ddebug/dd_screen.c
@@ -284,7 +284,8 @@ dd_screen_resource_changed(struct pipe_screen *_screen,
 {
struct pipe_screen *screen = dd_screen(_screen)->screen;
 
-   screen->resource_changed(screen, res);
+   if (screen->resource_changed)
+  screen->resource_changed(screen, res);
 }
 
 static void
diff --git a/src/gallium/auxiliary/driver_rbug/rbug_screen.c 
b/src/gallium/auxiliary/driver_rbug/rbug_screen.c
index 2477edbadf0..a1a77add734 100644
--- a/src/gallium/auxiliary/driver_rbug/rbug_screen.c
+++ b/src/gallium/auxiliary/driver_rbug/rbug_screen.c
@@ -222,7 +222,8 @@ rbug_screen_resource_changed(struct pipe_screen *_screen,
struct pipe_screen *screen = rb_screen->screen;
struct pipe_resource *resource = rb_resource->resource;
 
-   screen->resource_changed(screen, resource);
+   if (screen->resource_changed)
+  screen->resource_changed(screen, resource);
 }
 
 static void
diff --git a/src/gallium/auxiliary/driver_trace/tr_screen.c 
b/src/gallium/auxiliary/driver_trace/tr_screen.c
index d5a81249b51..704b2a3c72d 100644
--- a/src/gallium/auxiliary/driver_trace/tr_screen.c
+++ b/src/gallium/auxiliary/driver_trace/tr_screen.c
@@ -444,7 +444,8 @@ trace_screen_resource_changed(struct pipe_screen *_screen,
trace_dump_arg(ptr, screen);
trace_dump_arg(ptr, resource);
 
-   screen->resource_changed(screen, resource);
+   if (screen->resource_changed)
+  screen->resource_changed(screen, resource);
 
trace_dump_call_end();
 }
diff --git a/src/mesa/state_tracker/st_cb_eglimage.c 
b/src/mesa/state_tracker/st_cb_eglimage.c
index 4f33cb4bb06..0db2efc01cf 100644
--- a/src/mesa/state_tracker/st_cb_eglimage.c
+++ b/src/mesa/state_tracker/st_cb_eglimage.c
@@ -229,7 +229,8 @@ st_bind_egl_image(struct gl_context *ctx,
pipe_resource_reference(>pt, stimg->texture);
st_texture_release_all_sampler_views(st, stObj);
pipe_resource_reference(>pt, stObj->pt);
-   st->pipe->screen->resource_changed(st->pipe->screen, stImage->pt);
+   if (st->pipe->screen->resource_changed)
+  st->pipe->screen->resource_changed(st->pipe->screen, stImage->pt);
 
stObj->surface_format = stimg->format;
stObj->level_override = stimg->level;
-- 
2.18.0

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Re: [Mesa-dev] [PATCH 2/2] radv/winsys: use alloca() when creating the buffer object list

[Bas Nieuwenhuizen]

Not really a fan of this one, we can literally have thousands of
entries which seems largish when considering the stacks for heavily
threaded stuff are often much smaller.

On Thu, Jul 12, 2018 at 4:26 PM, Samuel Pitoiset
 wrote:
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 16 +++-
>  1 file changed, 3 insertions(+), 13 deletions(-)
>
> diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
> b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
> index c94c0f339f..e7ad9d7f6b 100644
> --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
> +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
> @@ -605,11 +605,7 @@ static int radv_amdgpu_create_bo_list(struct 
> radv_amdgpu_winsys *ws,
>
> pthread_mutex_lock(>global_bo_list_lock);
>
> -   handles = malloc(sizeof(handles[0]) * ws->num_buffers);
> -   if (!handles) {
> -   pthread_mutex_unlock(>global_bo_list_lock);
> -   return -ENOMEM;
> -   }
> +   handles = alloca(sizeof(handles[0]) * ws->num_buffers);
>
> LIST_FOR_EACH_ENTRY(bo, >global_bo_list, 
> global_list_item) {
> assert(num < ws->num_buffers);
> @@ -619,7 +615,7 @@ static int radv_amdgpu_create_bo_list(struct 
> radv_amdgpu_winsys *ws,
> r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
>   handles, NULL,
>   bo_list);
> -   free(handles);
> +
> pthread_mutex_unlock(>global_bo_list_lock);
> } else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list 
> &&
>!radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
> @@ -652,11 +648,7 @@ static int radv_amdgpu_create_bo_list(struct 
> radv_amdgpu_winsys *ws,
> *bo_list = 0;
> return 0;
> }
> -   amdgpu_bo_handle *handles = malloc(sizeof(amdgpu_bo_handle) * 
> total_buffer_count);
> -   if (!handles) {
> -   free(handles);
> -   return -ENOMEM;
> -   }
> +   amdgpu_bo_handle *handles = alloca(sizeof(amdgpu_bo_handle) * 
> total_buffer_count);
>
> for (unsigned i = 0; i < num_extra_bo; i++) {
> handles[i] = extra_bo_array[i]->bo;
> @@ -735,8 +727,6 @@ static int radv_amdgpu_create_bo_list(struct 
> radv_amdgpu_winsys *ws,
> } else {
> *bo_list = 0;
> }
> -
> -   free(handles);
> }
>
> return r;
> --
> 2.18.0
>
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[Mesa-dev] [Bug 107022] [RADV] The Witcher 3: Trembling of trees

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107022

--- Comment #9 from zefkerri...@gmail.com ---
(In reply to Samuel Pitoiset from comment #8)
> Yeah sorry, I took the decision too quickly... Can you upload the savegame
> where you recorded the video please?

I already did this before I created this bug report. Please just follow the
link, there are all these files.

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[Mesa-dev] [PATCH 2/2] radv/winsys: use alloca() when creating the buffer object list

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 16 +++-
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index c94c0f339f..e7ad9d7f6b 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -605,11 +605,7 @@ static int radv_amdgpu_create_bo_list(struct 
radv_amdgpu_winsys *ws,
 
pthread_mutex_lock(>global_bo_list_lock);
 
-   handles = malloc(sizeof(handles[0]) * ws->num_buffers);
-   if (!handles) {
-   pthread_mutex_unlock(>global_bo_list_lock);
-   return -ENOMEM;
-   }
+   handles = alloca(sizeof(handles[0]) * ws->num_buffers);
 
LIST_FOR_EACH_ENTRY(bo, >global_bo_list, global_list_item) {
assert(num < ws->num_buffers);
@@ -619,7 +615,7 @@ static int radv_amdgpu_create_bo_list(struct 
radv_amdgpu_winsys *ws,
r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,
  handles, NULL,
  bo_list);
-   free(handles);
+
pthread_mutex_unlock(>global_bo_list_lock);
} else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list &&
   !radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
@@ -652,11 +648,7 @@ static int radv_amdgpu_create_bo_list(struct 
radv_amdgpu_winsys *ws,
*bo_list = 0;
return 0;
}
-   amdgpu_bo_handle *handles = malloc(sizeof(amdgpu_bo_handle) * 
total_buffer_count);
-   if (!handles) {
-   free(handles);
-   return -ENOMEM;
-   }
+   amdgpu_bo_handle *handles = alloca(sizeof(amdgpu_bo_handle) * 
total_buffer_count);
 
for (unsigned i = 0; i < num_extra_bo; i++) {
handles[i] = extra_bo_array[i]->bo;
@@ -735,8 +727,6 @@ static int radv_amdgpu_create_bo_list(struct 
radv_amdgpu_winsys *ws,
} else {
*bo_list = 0;
}
-
-   free(handles);
}
 
return r;
-- 
2.18.0

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[Mesa-dev] [PATCH 1/2] radv/winsys: use alloca() for semaphore dependencies

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 5824a29b9e..c94c0f339f 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -1376,12 +1376,9 @@ static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx 
*ctx,
}
 
if (sem_info->wait.sem_count && sem_info->cs_emit_wait) {
-   sem_dependencies = malloc(sizeof(struct 
drm_amdgpu_cs_chunk_dep) * sem_info->wait.sem_count);
-   if (!sem_dependencies) {
-   r = -ENOMEM;
-   goto error_out;
-   }
+   sem_dependencies = alloca(sizeof(struct 
drm_amdgpu_cs_chunk_dep) * sem_info->wait.sem_count);
int sem_count = 0;
+
for (unsigned j = 0; j < sem_info->wait.sem_count; j++) {
sem = (struct amdgpu_cs_fence *)sem_info->wait.sem[j];
if (!sem->context)
@@ -1420,7 +1417,6 @@ static int radv_amdgpu_cs_submit(struct radv_amdgpu_ctx 
*ctx,
 chunks,
 >seq_no);
 error_out:
-   free(sem_dependencies);
free(wait_syncobj);
free(signal_syncobj);
return r;
-- 
2.18.0

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[Mesa-dev] [Bug 107022] [RADV] The Witcher 3: Trembling of trees

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107022

--- Comment #8 from Samuel Pitoiset  ---
Yeah sorry, I took the decision too quickly... Can you upload the savegame
where you recorded the video please?

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[Mesa-dev] [Bug 107022] [RADV] The Witcher 3: Trembling of trees

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107022

zefkerri...@gmail.com changed:

   What|Removed |Added

 Status|RESOLVED|REOPENED
 Resolution|FIXED   |---

--- Comment #7 from zefkerri...@gmail.com ---
(In reply to Samuel Pitoiset from comment #6)
> Really nice, thanks! Closing.

Samuel, I do not agree with your decision to close this bug report.
If this bug was not in Mesa 18.1, but it appeared in Mesa-git 18.2, it means
that some patch in Mesa-git 18.2 was added, which led to this regression.
Therefore, if this regression will not fixed, it will later become part of the
Mesa 18.2 stable version.
And so I think that it would be better to find the real cause of this
regression instead of closing the bug report without fixing this bug.
Regards. Thank you.

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[Mesa-dev] [PATCH v2] vulkan: Fix compilation on older platforms

[Danylo Piliaiev]

Make xlease automatically enabled only if xcb-randr >= 1.13,
check its version if manually enabled.

Enable VK_EXT_display_control only when libdrm >= 2.4.89

Check for DRM_EVENT_CONTEXT_VERSION >= 4 to use sequence_handler.

Add support for 'protect' attribute to anv_entrypoints_gen.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107170
  https://bugs.freedesktop.org/show_bug.cgi?id=106972
  https://bugs.freedesktop.org/show_bug.cgi?id=107176

v2: - Add 'protect="VK_USE_DISPLAY_CONTROL"' attribute to
   VK_EXT_display_control in vk.xml
- Add support for 'protect' attribute to anv_entrypoints_gen
   (copied from radv_entrypoints_gen)
- Turn #if into #ifdef
- Remove unnecessary pkg-config call from meson build (Dylan Baker)

Signed-off-by: Danylo Piliaiev 
---
Other vulkan extensions are gated behind platforms: wayland, xlib, ...
This one depends on library version and I hope I handled it right,
did I took the right approach?

Also what if extension requires both platform and libary version?
Should *_entrypoints_gen be able to support several defines per extension?

 configure.ac| 29 -
 meson.build | 10 -
 src/amd/vulkan/radv_extensions.py   |  9 +++-
 src/amd/vulkan/radv_wsi_display.c   |  5 ++---
 src/intel/vulkan/anv_entrypoints_gen.py |  7 ++
 src/intel/vulkan/anv_extensions.py  |  2 +-
 src/intel/vulkan/anv_extensions_gen.py  |  7 ++
 src/intel/vulkan/anv_wsi_display.c  |  4 ++--
 src/vulkan/registry/vk.xml  |  2 +-
 src/vulkan/wsi/wsi_common_display.c |  8 +--
 src/vulkan/wsi/wsi_common_display.h |  3 ++-
 11 files changed, 59 insertions(+), 27 deletions(-)

diff --git a/configure.ac b/configure.ac
index f135d05736..0b04525014 100644
--- a/configure.ac
+++ b/configure.ac
@@ -82,6 +82,8 @@ LIBDRM_FREEDRENO_REQUIRED=2.4.92
 LIBDRM_ETNAVIV_REQUIRED=2.4.89
 LIBDRM_VC4_REQUIRED=2.4.89
 
+LIBDRM_CRT_SEQUENCE_REQUIRED=2.4.89
+
 dnl Versions for external dependencies
 DRI2PROTO_REQUIRED=2.8
 GLPROTO_REQUIRED=1.4.14
@@ -97,6 +99,7 @@ XCBDRI2_REQUIRED=1.8
 XCBDRI3_MODIFIERS_REQUIRED=1.13
 XCBGLX_REQUIRED=1.8.1
 XCBPRESENT_MODIFIERS_REQUIRED=1.13
+XCBRANDR_XLEASE_REQUIRED=1.13
 XDAMAGE_REQUIRED=1.1
 XSHMFENCE_REQUIRED=1.1
 XVMC_REQUIRED=1.0.6
@@ -1874,20 +1877,6 @@ if test x"$enable_dri3" = xyes; then
 fi
 fi
 
-
-if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; then
-have_xlease=yes
-else
-have_xlease=no
-fi
-
-if test x"$have_xlease" = xyes; then
-randr_modules="x11-xcb xcb-randr"
-PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
-xlib_randr_modules="xrandr"
-PKG_CHECK_MODULES([XLIB_RANDR], [$xlib_randr_modules])
-fi
-
 AM_CONDITIONAL(HAVE_PLATFORM_X11, echo "$platforms" | grep -q 'x11')
 AM_CONDITIONAL(HAVE_PLATFORM_WAYLAND, echo "$platforms" | grep -q 'wayland')
 AM_CONDITIONAL(HAVE_PLATFORM_DRM, echo "$platforms" | grep -q 'drm')
@@ -1905,14 +1894,24 @@ xno)
 ;;
 *)
 if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; 
then
-enable_xlib_lease=yes
+xlease_modules="x11-xcb xcb-randr >= $XCBRANDR_XLEASE_REQUIRED xrandr"
+PKG_CHECK_EXISTS([$xlease_modules], [enable_xlib_lease=yes], 
[enable_xlib_lease=no])
 else
 enable_xlib_lease=no
 fi
 esac
 
+if test x"$enable_xlib_lease" = xyes; then
+randr_modules="x11-xcb xcb-randr >= $XCBRANDR_XLEASE_REQUIRED"
+PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
+xlib_randr_modules="xrandr"
+PKG_CHECK_MODULES([XLIB_RANDR], [$xlib_randr_modules])
+fi
+
 AM_CONDITIONAL(HAVE_XLIB_LEASE, test "x$enable_xlib_lease" = xyes)
 
+PKG_CHECK_EXISTS([libdrm >= $LIBDRM_CRT_SEQUENCE_REQUIRED], 
[DEFINES="${DEFINES} -DVK_USE_DISPLAY_CONTROL"], [])
+
 dnl
 dnl More DRI setup
 dnl
diff --git a/meson.build b/meson.build
index 7d12af3d51..902074819c 100644
--- a/meson.build
+++ b/meson.build
@@ -1088,6 +1088,8 @@ _drm_freedreno_ver = '2.4.92'
 _drm_intel_ver = '2.4.75'
 _drm_ver = '2.4.75'
 
+_drm_crt_sequence_ver = '2.4.89'
+
 _libdrm_checks = [
   ['intel', with_dri_i915 or with_gallium_i915],
   ['amdgpu', with_amd_vk or with_gallium_radeonsi],
@@ -1361,11 +1363,17 @@ if with_platform_x11
 dep_xcb_xfixes = dependency('xcb-xfixes')
   endif
   if with_xlib_lease
-dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.12')
+dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.13')
 dep_xlib_xrandr = dependency('xrandr', version : '>= 1.3')
   endif
 endif
 
+if with_any_vk
+  if dep_libdrm.version().version_compare('>= ' + _drm_crt_sequence_ver)
+pre_args += '-DVK_USE_DISPLAY_CONTROL'
+  endif
+endif
+
 if get_option('gallium-extra-hud')
   pre_args += '-DHAVE_GALLIUM_EXTRA_HUD=1'
 endif
diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index 094ed3bce3..35b49243a3 100644
--- a/src/amd/vulkan/radv_extensions.py

[Mesa-dev] [Bug 107022] [RADV] The Witcher 3: Trembling of trees

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107022

Samuel Pitoiset  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #6 from Samuel Pitoiset  ---
Really nice, thanks! Closing.

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[Mesa-dev] [Bug 107156] earth tessellation bug

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107156

Samuel Pitoiset  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEEDINFO|RESOLVED

--- Comment #7 from Samuel Pitoiset  ---
Really nice, thanks! Closing.

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[Mesa-dev] [PATCH v2] intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.

[Sergii Romantsov]

SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats
why we got segmentation fault when used INTEL_DEBUG=bat.
Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT
of VS, GS and PS structures.

v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml

Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190
Signed-off-by: Sergii Romantsov 
---
 src/intel/genxml/gen6.xml | 38 ++-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 12 -
 2 files changed, 20 insertions(+), 30 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index c2967cd..62d2574 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -622,6 +622,17 @@
 
   
 
+  
+
+
+
+
+
+
+
+
+  
+
   
 
 
@@ -633,14 +644,7 @@
 
 
 
-
-
-
-
-
-
-
-
+
   
 
   
@@ -654,14 +658,7 @@
 
 
 
-
-
-
-
-
-
-
-
+
   
 
   
@@ -675,14 +672,7 @@
 
 
 
-
-
-
-
-
-
-
-
+
   
 
   
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 7fe1288..a4e395c 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -1879,8 +1879,8 @@ genX(upload_wm)(struct brw_context *brw)
  /* Pointer to the WM constant buffer.  Covered by the set of
   * state flags from gen6_upload_wm_push_constants.
   */
- wmcp.PointertoPSConstantBuffer0 = stage_state->push_const_offset;
- wmcp.PSConstantBuffer0ReadLength = stage_state->push_const_size - 1;
+ wmcp.ConstantBody.PointertoConstantBuffer0 = 
stage_state->push_const_offset;
+ wmcp.ConstantBody.ConstantBuffer0ReadLength = 
stage_state->push_const_size - 1;
   }
}
 #endif
@@ -2215,8 +2215,8 @@ genX(upload_vs_state)(struct brw_context *brw)
brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), cvs) {
   if (stage_state->push_const_size != 0) {
  cvs.Buffer0Valid = true;
- cvs.PointertoVSConstantBuffer0 = stage_state->push_const_offset;
- cvs.VSConstantBuffer0ReadLength = stage_state->push_const_size - 1;
+ cvs.ConstantBody.PointertoConstantBuffer0 = 
stage_state->push_const_offset;
+ cvs.ConstantBody.ConstantBuffer0ReadLength = 
stage_state->push_const_size - 1;
   }
}
 #endif
@@ -2707,8 +2707,8 @@ genX(upload_gs_state)(struct brw_context *brw)
brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_GS), cgs) {
   if (active && stage_state->push_const_size != 0) {
  cgs.Buffer0Valid = true;
- cgs.PointertoGSConstantBuffer0 = stage_state->push_const_offset;
- cgs.GSConstantBuffer0ReadLength = stage_state->push_const_size - 1;
+ cgs.ConstantBody.PointertoConstantBuffer0 = 
stage_state->push_const_offset;
+ cgs.ConstantBody.ConstantBuffer0ReadLength = 
stage_state->push_const_size - 1;
   }
}
 #endif
-- 
2.7.4

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[Mesa-dev] [Bug 107022] [RADV] The Witcher 3: Trembling of trees

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107022

--- Comment #5 from ximik  ---
After installing a stable driver version, this bug is gone. maybe you help too
mesa 18.1.3-1 archlinux

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[Mesa-dev] [Bug 107156] earth tessellation bug

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107156

--- Comment #6 from ximik  ---
after installing a stable version of this bug disappeared.
mesa 18.1.3-1

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Re: [Mesa-dev] [PATCH] i965/fs: unspills shoudn't use grf127 as dest since Gen8+

[Chema Casanova]

El 12/07/18 a las 03:23, Caio Marcelo de Oliveira Filho escribió:
> On Wed, Jul 11, 2018 at 06:03:05PM +0200, Jose Maria Casanova Crespo wrote:
>> At 232ed8980217dd65ab0925df28156f565b94b2e5 "i965/fs: Register allocator
>> shoudn't use grf127 for sends dest" we didn't take into account the case
>> of SEND instructions that are not send_from_grf. But since Gen7+ although
>> the backend still uses MRFs internally for sends they are finally asigned
>> to a GRFs.
> 
> Typo "assigned".

Fixed.

>> In the case of unspills the backend assigns directly as source its
>> destination because it is suppose to be available. So we always have a
>> source-destination overlap. If the reg_allocator asigns registers that
> 
> Typo "assigns".

Fixed.

>> include de grf127 we fail the validation rule that affects Gen8+
> 
> Typo "the".

Fixed.

>> "r127 must not be used for return address when there is a src and dest
>> overlap in send instruction."
>>
>> So this patch activates the grf127_send_hack_node for Gen8+ and if we have
>> any register spilled we add interferences to the destination of the unspill
>> operations.
> 
> I've spent some time testing why this patch was still not covering all
> the cases yet. The opt_bank_conflicts() optimization, that runs after
> the register allocation, was moving things around, causing the r127 to
> be used in the condition we were avoiding it.
> 
> The code there already has the idea of not touching certain registers,
> so we should add something like
> 
>   /* At Intel Broadwell PRM, vol 07, section "Instruction Set Reference",
>* subsection "EUISA Instructions", Send Message (page 990):
>*
>* "r127 must not be used for return address when there is a src and
>* dest overlap in send instruction."
>*
>* Register allocation ensures that, so don't move 127 around to avoid
>* breaking that property.
>*/ 
>   if (v->devinfo->gen >= 8)
>  constrained[p.atom_of_reg(127)] = true;
> 
> to function shader_reg_constraints() in
> brw_fs_bank_conflicts.cpp. This fixes the crashes I was seeing in
> shader-db.
> 
> With the change to bank conflicts and the typos/style fixed, this
> patch is


Good finding. I like the clean and simple solution. At that point of
optimizing back conflicts I don't find a better way to don't mess with
grf127, although we are forbidding legal permutations when not SEND
instructions are in place. I've just putting the your code after the
constrains for reg0 and reg1.

I've also confirmed that that that I run a full shader-db without
crashes caused by this validation rule and the performance impact of the
patch doesn't seem to be too much taking into account that we are
avoiding generating instructions with undefined return values.

total instructions in shared programs: 14867211 -> 14867218 (<.01%)
instructions in affected programs: 5314 -> 5321 (0.13%)
helped: 1
HURT: 1

total cycles in shared programs: 537925161 -> 537923248 (<.01%)
cycles in affected programs: 44939136 -> 44937223 (<.01%)
helped: 10
HURT: 23

total spills in shared programs: 7789 -> 7790 (0.01%)
spills in affected programs: 107 -> 108 (0.93%)
helped: 0
HURT: 1

total fills in shared programs: 10555 -> 10557 (0.02%)
fills in affected programs: 155 -> 157 (1.29%)
helped: 0
HURT: 1

> Reviewed-by: Caio Marcelo de Oliveira Filho 

Thanks for the review.

Chema

> 
> Reviewed-by: Caio Marcelo de Oliveira Filho 
> 
> 
>> +  if (spilled_any_registers) {
>> + foreach_block_and_inst(block, fs_inst, inst, cfg) {
>> +if ((inst->opcode == SHADER_OPCODE_GEN7_SCRATCH_READ ||
>> +inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_READ) &&
>> +inst->dst.file ==VGRF) {
> 
> Missing space after the "==".
> 
>> +   ra_add_node_interference(g, inst->dst.nr, 
>> grf127_send_hack_node);
>> +}
>>   }
>>}
>> }
>>  
>> +
> 
> Extra newline?
> 
> 
> Thanks,
> Caio
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[Mesa-dev] [PATCH 0/6] More OpenCL preparation for nir

[Karol Herbst]

This time all of the patches can be reviewed independently.

Karol Herbst (5):
  nir/spirv: print id for unsupported builtins
  nir: add builtin builder
  nir: fix printing of vec16 type
  nir: prepare for bumping up max components to 16
  nir/spirv: handle functions with scalar and vector params

Rob Clark (1):
  nir/spirv: implement BuiltInWorkDim

 src/compiler/Makefile.sources |  2 +
 src/compiler/nir/meson.build  |  2 +
 src/compiler/nir/nir.c| 16 ++--
 src/compiler/nir/nir.h| 34 
 src/compiler/nir/nir_builder.h| 18 +++--
 src/compiler/nir/nir_builtin_builder.c| 67 
 src/compiler/nir/nir_builtin_builder.h| 79 +++
 src/compiler/nir/nir_intrinsics.py|  1 +
 src/compiler/nir/nir_lower_alu_to_scalar.c|  6 +-
 src/compiler/nir/nir_lower_io_to_scalar.c |  4 +-
 .../nir/nir_lower_load_const_to_scalar.c  |  2 +-
 src/compiler/nir/nir_opt_constant_folding.c   |  2 +-
 src/compiler/nir/nir_opt_copy_prop_vars.c |  4 +-
 src/compiler/nir/nir_print.c  |  9 ++-
 src/compiler/nir/nir_search.c |  8 +-
 src/compiler/nir/nir_validate.c   |  6 +-
 src/compiler/shader_enums.c   |  1 +
 src/compiler/shader_enums.h   |  1 +
 src/compiler/spirv/spirv_to_nir.c |  4 +-
 src/compiler/spirv/vtn_alu.c  |  2 +-
 src/compiler/spirv/vtn_cfg.c  | 25 --
 src/compiler/spirv/vtn_glsl450.c  | 58 +++---
 src/compiler/spirv/vtn_variables.c|  6 +-
 23 files changed, 251 insertions(+), 106 deletions(-)
 create mode 100644 src/compiler/nir/nir_builtin_builder.c
 create mode 100644 src/compiler/nir/nir_builtin_builder.h

-- 
2.17.1

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[Mesa-dev] [PATCH 1/6] nir/spirv: print id for unsupported builtins

[Karol Herbst]

Signed-off-by: Karol Herbst 
---
 src/compiler/spirv/vtn_variables.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index c86416495b6..67b4d59b9fe 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1213,7 +1213,7 @@ vtn_get_builtin_location(struct vtn_builder *b,
   set_mode_system_value(b, mode);
   break;
default:
-  vtn_fail("unsupported builtin");
+  vtn_fail("unsupported builtin: %u", builtin);
}
 }
 
-- 
2.17.1

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[Mesa-dev] [PATCH 4/6] nir: fix printing of vec16 type

[Karol Herbst]

Fixes: 2f181c8c183cc8b4d0450789bb20c2be48d32db3
   "glsl_types: vec8/vec16 support"

Signed-off-by: Karol Herbst 
---
 src/compiler/nir/nir_print.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
index 18860db0058..4fa12d2d207 100644
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -88,6 +88,7 @@ print_register(nir_register *reg, print_state *state)
 
 static const char *sizes[] = { "error", "vec1", "vec2", "vec3", "vec4",
"error", "error", "error", "vec8",
+   "error", "error", "error", "error",
"error", "error", "error", "vec16"};
 
 static void
-- 
2.17.1

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[Mesa-dev] [PATCH 6/6] nir/spirv: handle functions with scalar and vector params

[Karol Herbst]

Signed-off-by: Karol Herbst 
---
 src/compiler/spirv/vtn_cfg.c | 25 ++---
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index ed1ab5d1c2c..2b01ede6f81 100644
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -90,7 +90,10 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
   }
 
   for (unsigned i = 0; i < func_type->length; i++) {
- if (func_type->params[i]->base_type == vtn_base_type_sampled_image) {
+ enum vtn_base_type base_type = func_type->params[i]->base_type;
+ const struct glsl_type *type = func_type->params[i]->type;
+
+ if (base_type == vtn_base_type_sampled_image) {
 /* Sampled images are two pointer parameters */
 func->params[idx++] = (nir_parameter) {
.num_components = 1, .bit_size = 32,
@@ -98,14 +101,22 @@ vtn_cfg_handle_prepass_instruction(struct vtn_builder *b, 
SpvOp opcode,
 func->params[idx++] = (nir_parameter) {
.num_components = 1, .bit_size = 32,
 };
- } else if (func_type->params[i]->base_type == vtn_base_type_pointer &&
-func_type->params[i]->type != NULL) {
+ } else if (base_type == vtn_base_type_pointer && type != NULL) {
 /* Pointers with as storage class get passed by-value */
-assert(glsl_type_is_vector_or_scalar(func_type->params[i]->type));
+assert(glsl_type_is_vector_or_scalar(type));
+func->params[idx++] = (nir_parameter) {
+   .num_components = glsl_get_vector_elements(type),
+   .bit_size = glsl_get_bit_size(type),
+};
+ } else if (base_type == vtn_base_type_scalar) {
+func->params[idx++] = (nir_parameter) {
+   .num_components = 1,
+   .bit_size = glsl_get_bit_size(type),
+};
+ } else if (base_type == vtn_base_type_vector) {
 func->params[idx++] = (nir_parameter) {
-   .num_components =
-  glsl_get_vector_elements(func_type->params[i]->type),
-   .bit_size = glsl_get_bit_size(func_type->params[i]->type),
+   .num_components = glsl_get_components(type),
+   .bit_size = glsl_get_bit_size(type),
 };
  } else {
 /* Everything else is a regular pointer */
-- 
2.17.1

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[Mesa-dev] [PATCH 5/6] nir: prepare for bumping up max components to 16

[Karol Herbst]

OpenCL knows vector of size 8 and 16.

Signed-off-by: Karol Herbst 
---
 src/compiler/nir/nir.c| 14 
 src/compiler/nir/nir.h| 34 ++-
 src/compiler/nir/nir_builder.h| 18 ++
 src/compiler/nir/nir_lower_alu_to_scalar.c|  6 ++--
 src/compiler/nir/nir_lower_io_to_scalar.c |  4 +--
 .../nir/nir_lower_load_const_to_scalar.c  |  2 +-
 src/compiler/nir/nir_opt_constant_folding.c   |  2 +-
 src/compiler/nir/nir_opt_copy_prop_vars.c |  4 +--
 src/compiler/nir/nir_print.c  |  8 ++---
 src/compiler/nir/nir_search.c |  8 ++---
 src/compiler/nir/nir_validate.c   |  6 ++--
 src/compiler/spirv/spirv_to_nir.c |  4 +--
 src/compiler/spirv/vtn_alu.c  |  2 +-
 13 files changed, 59 insertions(+), 53 deletions(-)

diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index ca89a46f7d4..bc7f05b3e86 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -251,7 +251,7 @@ nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
nir_src_copy(>src, >src, >instr);
dest->abs = src->abs;
dest->negate = src->negate;
-   for (unsigned i = 0; i < 4; i++)
+   for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
   dest->swizzle[i] = src->swizzle[i];
 }
 
@@ -421,10 +421,8 @@ alu_src_init(nir_alu_src *src)
 {
src_init(>src);
src->abs = src->negate = false;
-   src->swizzle[0] = 0;
-   src->swizzle[1] = 1;
-   src->swizzle[2] = 2;
-   src->swizzle[3] = 3;
+   for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
+  src->swizzle[i] = i;
 }
 
 nir_alu_instr *
@@ -1426,10 +1424,10 @@ nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, 
nir_src new_src,
   nir_if_rewrite_condition(use_src->parent_if, new_src);
 }
 
-uint8_t
+nir_component_mask_t
 nir_ssa_def_components_read(const nir_ssa_def *def)
 {
-   uint8_t read_mask = 0;
+   nir_component_mask_t read_mask = 0;
nir_foreach_use(use, def) {
   if (use->parent_instr->type == nir_instr_type_alu) {
  nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
@@ -1437,7 +1435,7 @@ nir_ssa_def_components_read(const nir_ssa_def *def)
  int src_idx = alu_src - >src[0];
  assert(src_idx >= 0 && src_idx < nir_op_infos[alu->op].num_inputs);
 
- for (unsigned c = 0; c < 4; c++) {
+ for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; c++) {
 if (!nir_alu_instr_channel_used(alu, src_idx, c))
continue;
 
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 92ab3a699cc..d3e63be091f 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -57,6 +57,8 @@ extern "C" {
 
 #define NIR_FALSE 0u
 #define NIR_TRUE (~0u)
+#define NIR_MAX_VEC_COMPONENTS 4
+typedef uint8_t nir_component_mask_t;
 
 /** Defines a cast function
  *
@@ -115,16 +117,16 @@ typedef enum {
 } nir_rounding_mode;
 
 typedef union {
-   float f32[4];
-   double f64[4];
-   int8_t i8[4];
-   uint8_t u8[4];
-   int16_t i16[4];
-   uint16_t u16[4];
-   int32_t i32[4];
-   uint32_t u32[4];
-   int64_t i64[4];
-   uint64_t u64[4];
+   float f32[NIR_MAX_VEC_COMPONENTS];
+   double f64[NIR_MAX_VEC_COMPONENTS];
+   int8_t i8[NIR_MAX_VEC_COMPONENTS];
+   uint8_t u8[NIR_MAX_VEC_COMPONENTS];
+   int16_t i16[NIR_MAX_VEC_COMPONENTS];
+   uint16_t u16[NIR_MAX_VEC_COMPONENTS];
+   int32_t i32[NIR_MAX_VEC_COMPONENTS];
+   uint32_t u32[NIR_MAX_VEC_COMPONENTS];
+   int64_t i64[NIR_MAX_VEC_COMPONENTS];
+   uint64_t u64[NIR_MAX_VEC_COMPONENTS];
 } nir_const_value;
 
 typedef struct nir_constant {
@@ -135,7 +137,7 @@ typedef struct nir_constant {
 * by the type associated with the \c nir_variable.  Constants may be
 * scalars, vectors, or matrices.
 */
-   nir_const_value values[4];
+   nir_const_value values[NIR_MAX_VEC_COMPONENTS];
 
/* we could get this from the var->type but makes clone *much* easier to
 * not have to care about the type.
@@ -697,7 +699,7 @@ typedef struct {
 * a statement like "foo.xzw = bar.zyx" would have a writemask of 1101b and
 * a swizzle of {2, x, 1, 0} where x means "don't care."
 */
-   uint8_t swizzle[4];
+   uint8_t swizzle[NIR_MAX_VEC_COMPONENTS];
 } nir_alu_src;
 
 typedef struct {
@@ -712,7 +714,7 @@ typedef struct {
 
bool saturate;
 
-   unsigned write_mask : 4; /* ignored if dest.is_ssa is true */
+   unsigned write_mask : NIR_MAX_VEC_COMPONENTS; /* ignored if dest.is_ssa is 
true */
 } nir_alu_dest;
 
 typedef enum {
@@ -841,14 +843,14 @@ typedef struct {
/**
 * The number of components in each input
 */
-   unsigned input_sizes[4];
+   unsigned input_sizes[NIR_MAX_VEC_COMPONENTS];
 
/**
 * The type of vector that each input takes. Note that negate and
 * absolute value are only allowed on inputs with int or float type and
 * behave differently on the two.
 */
-   nir_alu_type input_types[4];
+   nir_alu_type 

[Mesa-dev] [PATCH 3/6] nir: add builtin builder

[Karol Herbst]

also move some of the GLSL builtins over we will need for implementing
some OpenCL builtins

Signed-off-by: Karol Herbst 
---
 src/compiler/Makefile.sources  |  2 +
 src/compiler/nir/meson.build   |  2 +
 src/compiler/nir/nir_builtin_builder.c | 67 ++
 src/compiler/nir/nir_builtin_builder.h | 79 ++
 src/compiler/spirv/vtn_glsl450.c   | 58 +--
 5 files changed, 163 insertions(+), 45 deletions(-)
 create mode 100644 src/compiler/nir/nir_builtin_builder.c
 create mode 100644 src/compiler/nir/nir_builtin_builder.h

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index db4dd1e89f4..cc147218c4e 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -203,6 +203,8 @@ NIR_FILES = \
nir/nir.c \
nir/nir.h \
nir/nir_builder.h \
+   nir/nir_builtin_builder.c \
+   nir/nir_builtin_builder.h \
nir/nir_clone.c \
nir/nir_constant_expressions.h \
nir/nir_control_flow.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 28aa8de7014..a1bb19356ce 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -87,6 +87,8 @@ files_libnir = files(
   'nir.c',
   'nir.h',
   'nir_builder.h',
+  'nir_builtin_builder.c',
+  'nir_builtin_builder.h',
   'nir_clone.c',
   'nir_constant_expressions.h',
   'nir_control_flow.c',
diff --git a/src/compiler/nir/nir_builtin_builder.c 
b/src/compiler/nir/nir_builtin_builder.c
new file mode 100644
index 000..c8cc3fa4aac
--- /dev/null
+++ b/src/compiler/nir/nir_builtin_builder.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright © 2018 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_builtin_builder.h"
+
+#define NIR_IMM_FP(n, s, v) (s->bit_size == 64 ? nir_imm_double(n, v) : 
nir_imm_float(n, v))
+
+nir_ssa_def*
+nir_cross(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
+{
+   unsigned yzx[4] = { 1, 2, 0, 0 };
+   unsigned zxy[4] = { 2, 0, 1, 0 };
+
+   return nir_fsub(b, nir_fmul(b, nir_swizzle(b, x, yzx, 3, true),
+  nir_swizzle(b, y, zxy, 3, true)),
+  nir_fmul(b, nir_swizzle(b, x, zxy, 3, true),
+  nir_swizzle(b, y, yzx, 3, true)));
+}
+
+nir_ssa_def*
+nir_fast_length(nir_builder *b, nir_ssa_def *vec)
+{
+   switch (vec->num_components) {
+   case 1: return nir_fsqrt(b, nir_fmul(b, vec, vec));
+   case 2: return nir_fsqrt(b, nir_fdot2(b, vec, vec));
+   case 3: return nir_fsqrt(b, nir_fdot3(b, vec, vec));
+   case 4: return nir_fsqrt(b, nir_fdot4(b, vec, vec));
+   default:
+  unreachable("Invalid number of components");
+   }
+}
+
+nir_ssa_def*
+nir_smoothstep(nir_builder *b, nir_ssa_def *edge0, nir_ssa_def *edge1, 
nir_ssa_def *x)
+{
+   nir_ssa_def *f2 = NIR_IMM_FP(b, x, 2.0);
+   nir_ssa_def *f3 = NIR_IMM_FP(b, x, 3.0);
+
+   /* t = clamp((x - edge0) / (edge1 - edge0), 0, 1) */
+   nir_ssa_def *t =
+  nir_fsat(b, nir_fdiv(b, nir_fsub(b, x, edge0),
+  nir_fsub(b, edge1, edge0)));
+
+   /* result = t * t * (3 - 2 * t) */
+   return nir_fmul(b, t, nir_fmul(b, t, nir_fsub(b, f3, nir_fmul(b, f2, t;
+}
diff --git a/src/compiler/nir/nir_builtin_builder.h 
b/src/compiler/nir/nir_builtin_builder.h
new file mode 100644
index 000..5b76d012c85
--- /dev/null
+++ b/src/compiler/nir/nir_builtin_builder.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright © 2018 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom 

[Mesa-dev] [PATCH 2/6] nir/spirv: implement BuiltInWorkDim

[Karol Herbst]

From: Rob Clark 

Signed-off-by: Karol Herbst 
---
 src/compiler/nir/nir.c | 2 ++
 src/compiler/nir/nir_intrinsics.py | 1 +
 src/compiler/shader_enums.c| 1 +
 src/compiler/shader_enums.h| 1 +
 src/compiler/spirv/vtn_variables.c | 4 
 5 files changed, 9 insertions(+)

diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index c515a30b626..ca89a46f7d4 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -1758,6 +1758,8 @@ nir_intrinsic_from_system_value(gl_system_value val)
   return nir_intrinsic_load_local_group_size;
case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
   return nir_intrinsic_load_global_invocation_id;
+   case SYSTEM_VALUE_WORK_DIM:
+  return nir_intrinsic_load_work_dim;
default:
   unreachable("system value does not directly correspond to intrinsic");
}
diff --git a/src/compiler/nir/nir_intrinsics.py 
b/src/compiler/nir/nir_intrinsics.py
index 919aa609f8a..1a03a6aa30f 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -452,6 +452,7 @@ system_value("num_subgroups", 1)
 system_value("subgroup_id", 1)
 system_value("local_group_size", 3)
 system_value("global_invocation_id", 3)
+system_value("work_dim", 1)
 
 # Blend constant color values.  Float values are clamped.#
 system_value("blend_const_color_r_float", 1)
diff --git a/src/compiler/shader_enums.c b/src/compiler/shader_enums.c
index 4eade256604..a874083a0b7 100644
--- a/src/compiler/shader_enums.c
+++ b/src/compiler/shader_enums.c
@@ -240,6 +240,7 @@ gl_system_value_name(gl_system_value sysval)
  ENUM(SYSTEM_VALUE_NUM_WORK_GROUPS),
  ENUM(SYSTEM_VALUE_LOCAL_GROUP_SIZE),
  ENUM(SYSTEM_VALUE_GLOBAL_GROUP_SIZE),
+ ENUM(SYSTEM_VALUE_WORK_DIM),
  ENUM(SYSTEM_VALUE_DEVICE_INDEX),
  ENUM(SYSTEM_VALUE_VIEW_INDEX),
  ENUM(SYSTEM_VALUE_VERTEX_CNT),
diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h
index 280bf1d2835..f8e22925f35 100644
--- a/src/compiler/shader_enums.h
+++ b/src/compiler/shader_enums.h
@@ -586,6 +586,7 @@ typedef enum
SYSTEM_VALUE_NUM_WORK_GROUPS,
SYSTEM_VALUE_LOCAL_GROUP_SIZE,
SYSTEM_VALUE_GLOBAL_GROUP_SIZE,
+   SYSTEM_VALUE_WORK_DIM,
/*@}*/
 
/** Required for VK_KHR_device_group */
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 67b4d59b9fe..6bd7aa1b0d5 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1208,6 +1208,10 @@ vtn_get_builtin_location(struct vtn_builder *b,
   *location = FRAG_RESULT_STENCIL;
   vtn_assert(*mode == nir_var_shader_out);
   break;
+   case SpvBuiltInWorkDim:
+  *location = SYSTEM_VALUE_WORK_DIM;
+  set_mode_system_value(b, mode);
+  break;
case SpvBuiltInGlobalSize:
   *location = SYSTEM_VALUE_GLOBAL_GROUP_SIZE;
   set_mode_system_value(b, mode);
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 9/9] winsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0

[Michel Dänzer]

On 2018-07-12 12:12 PM, Timothy Arceri wrote:
> 
> 
> On 12/07/18 19:00, Michel Dänzer wrote:
>> On 2018-07-12 07:26 AM, Marek Olšák wrote:
>>> From: Marek Olšák 
>>>
>>> TODO: requires latest libdrm for amdgpu_bo_handle_type_kms_noimport
>>> ---
>>>   src/gallium/winsys/amdgpu/drm/amdgpu_bo.c |  6 +++
>>>   src/gallium/winsys/amdgpu/drm/amdgpu_bo.h |  2 +
>>>   src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 54 +--
>>>   3 files changed, 58 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
>>> b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
>>> index e3d56613dfa..eba8d6e8b3d 100644
>>> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
>>> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
>>> @@ -473,20 +473,22 @@ static struct amdgpu_winsys_bo
>>> *amdgpu_create_bo(struct amdgpu_winsys *ws,
>>>  bo->u.real.va_handle = va_handle;
>>>  bo->initial_domain = initial_domain;
>>>  bo->unique_id = __sync_fetch_and_add(>next_bo_unique_id, 1);
>>>  bo->is_local = !!(request.flags &
>>> AMDGPU_GEM_CREATE_VM_ALWAYS_VALID);
>>>    if (initial_domain & RADEON_DOMAIN_VRAM)
>>>     ws->allocated_vram += align64(size, ws->info.gart_page_size);
>>>  else if (initial_domain & RADEON_DOMAIN_GTT)
>>>     ws->allocated_gtt += align64(size, ws->info.gart_page_size);
>>>   +   amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms_noimport,
>>> >u.real.kms_handle);
>>
>> How does using amdgpu_bo_handle_type_kms instead affect the numbers?
>>
> 
> The stats are in the cover letter but I think it would be worth Marek
> adding them to the commit messages of the patches in some form for
> future reference.
> 
> The maximum glxgears FPS improves as follows.
> 
> Initially: 13285
> 8 patches: 14403 (+8.4% vs initial)
> + patch 9: 15498 (+16.6% vs initial)

I'm asking what the final number is when using amdgpu_bo_handle_type_kms
instead of amdgpu_bo_handle_type_kms_noimport in the last patch.


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[Mesa-dev] [PATCH] virgl: Allow RGB32* textures only as buffer objects

[Gert Wollny]

When requesting a texture of the internal format GL_RGB32F Gallium will
try to allocate a renderable texture and returns RGBA32F or RGBX32F, but
when one requests GL_RGB32I or GL_RGB32UI the according 3-component
texture will be returned. This leads to problems later, when one wants
to use glCopyImageSubData to copy data between these textures that should
be compatible, but given the way virgl and Gallium  handle this the latter
fails with an assertion, because the per-texel bit size is different.

By allowing the GL_RGB32* only for texture buffers these problems are avoided
without losing the ARB_tbo_rgb32 extension (thanks Ilia Mirkin).

Signed-off-by: Gert Wollny 
---
 src/gallium/drivers/virgl/virgl_screen.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index 2a340b004f..1dbd88dee8 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -496,6 +496,13 @@ virgl_is_format_supported( struct pipe_screen *screen,
   return virgl_is_vertex_format_supported(screen, format);
}
 
+   /* Allow 3-comp 32 bit texturs only for TBOs (needed for ARB_tbo_rgb32) */
+   if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
+   format == PIPE_FORMAT_R32G32B32_SINT ||
+   format == PIPE_FORMAT_R32G32B32_UINT) &&
+   target != PIPE_BUFFER)
+  return FALSE;
+
if (bind & PIPE_BIND_RENDER_TARGET) {
   if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
  return FALSE;
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 9/9] winsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0

[Timothy Arceri]

On 12/07/18 19:00, Michel Dänzer wrote:

On 2018-07-12 07:26 AM, Marek Olšák wrote:

From: Marek Olšák 

TODO: requires latest libdrm for amdgpu_bo_handle_type_kms_noimport
---
  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c |  6 +++
  src/gallium/winsys/amdgpu/drm/amdgpu_bo.h |  2 +
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 54 +--
  3 files changed, 58 insertions(+), 4 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index e3d56613dfa..eba8d6e8b3d 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -473,20 +473,22 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
amdgpu_winsys *ws,
 bo->u.real.va_handle = va_handle;
 bo->initial_domain = initial_domain;
 bo->unique_id = __sync_fetch_and_add(>next_bo_unique_id, 1);
 bo->is_local = !!(request.flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID);
  
 if (initial_domain & RADEON_DOMAIN_VRAM)

ws->allocated_vram += align64(size, ws->info.gart_page_size);
 else if (initial_domain & RADEON_DOMAIN_GTT)
ws->allocated_gtt += align64(size, ws->info.gart_page_size);
  
+   amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms_noimport, >u.real.kms_handle);


How does using amdgpu_bo_handle_type_kms instead affect the numbers?



The stats are in the cover letter but I think it would be worth Marek 
adding them to the commit messages of the patches in some form for 
future reference.


The maximum glxgears FPS improves as follows.

Initially: 13285
8 patches: 14403 (+8.4% vs initial)
+ patch 9: 15498 (+16.6% vs initial)
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Re: [Mesa-dev] [PATCH 1/3] docs/features: Mark some Vulkan extensions as done

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Thu, Jul 12, 2018 at 1:03 AM, Jason Ekstrand  wrote:
> ---
>  docs/features.txt | 18 +-
>  1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/docs/features.txt b/docs/features.txt
> index 81fe8d0e751..0705ff9974b 100644
> --- a/docs/features.txt
> +++ b/docs/features.txt
> @@ -359,23 +359,23 @@ Khronos extensions that are not part of any Vulkan 
> version:
>VK_KHR_android_surfacenot started
>VK_KHR_dedicated_allocation   DONE (anv, radv)
>VK_KHR_descriptor_update_template DONE (anv, radv)
> -  VK_KHR_displaynot started
> -  VK_KHR_display_swapchain  not started
> -  VK_KHR_external_fence not started
> -  VK_KHR_external_fence_capabilitiesnot started
> -  VK_KHR_external_fence_fd  not started
> +  VK_KHR_displayDONE (anv, radv)
> +  VK_KHR_display_swapchain  DONE (anv, radv)
> +  VK_KHR_external_fence DONE (anv, radv)
> +  VK_KHR_external_fence_capabilitiesDONE (anv, radv)
> +  VK_KHR_external_fence_fd  DONE (anv, radv)
>VK_KHR_external_fence_win32   not started
>VK_KHR_external_memoryDONE (anv, radv)
>VK_KHR_external_memory_capabilities   DONE (anv, radv)
>VK_KHR_external_memory_fd DONE (anv, radv)
>VK_KHR_external_memory_win32  not started
> -  VK_KHR_external_semaphore DONE (radv)
> -  VK_KHR_external_semaphore_capabilitiesDONE (radv)
> -  VK_KHR_external_semaphore_fd  DONE (radv)
> +  VK_KHR_external_semaphore DONE (anv, radv)
> +  VK_KHR_external_semaphore_capabilitiesDONE (anv, radv)
> +  VK_KHR_external_semaphore_fd  DONE (anv, radv)
>VK_KHR_external_semaphore_win32   not started
>VK_KHR_get_memory_requirements2   DONE (anv, radv)
>VK_KHR_get_physical_device_properties2DONE (anv, radv)
> -  VK_KHR_get_surface_capabilities2  DONE (anv)
> +  VK_KHR_get_surface_capabilities2  DONE (anv, radv)
>VK_KHR_incremental_presentDONE (anv, radv)
>VK_KHR_maintenance1   DONE (anv, radv)
>VK_KHR_mir_surfacenot started
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH 3/3] docs/features: Add the missing KHR extensions

[Bas Nieuwenhuizen]

On Thu, Jul 12, 2018 at 1:03 AM, Jason Ekstrand  wrote:
> ---
>  docs/features.txt | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/docs/features.txt b/docs/features.txt
> index 61ca4d2da65..a70e1d1cc68 100644
> --- a/docs/features.txt
> +++ b/docs/features.txt
> @@ -381,16 +381,21 @@ Vulkan 1.1 -- all DONE: anv, radv
>VK_KHR_variable_pointers  DONE (anv, radv)
>
>  Khronos extensions that are not part of any Vulkan version:
> +  VK_KHR_8bit_storage   DONE (anv)
>VK_KHR_android_surfacenot started
> +  VK_KHR_create_renderpass2 DONE (anv)

done for radv too.

>VK_KHR_displayDONE (anv, radv)
>VK_KHR_display_swapchain  DONE (anv, radv)
> +  VK_KHR_draw_indirect_countnot started

done for radv.

With those two this patch is

Reviewed-by: Bas Nieuwenhuizen 
>VK_KHR_external_fence_fd  DONE (anv, radv)
>VK_KHR_external_fence_win32   not started
>VK_KHR_external_memory_fd DONE (anv, radv)
>VK_KHR_external_memory_win32  not started
>VK_KHR_external_semaphore_fd  DONE (anv, radv)
>VK_KHR_external_semaphore_win32   not started
> +  VK_KHR_get_display_properties2DONE (anv, radv)
>VK_KHR_get_surface_capabilities2  DONE (anv, radv)
> +  VK_KHR_image_format_list  DONE (anv, radv)
>VK_KHR_incremental_presentDONE (anv, radv)
>VK_KHR_mir_surfacenot started
>VK_KHR_push_descriptorDONE (anv, radv)
> --
> 2.17.1
>
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[Mesa-dev] [Bug 107116] [OpenCL] [llvm-svn] [meson] build failure C++ library 'clangCodeGen' not found

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107116

LoneVVolf  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from LoneVVolf  ---
Problem was with meson, builds fine with meson 0.47.1 .

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Re: [Mesa-dev] [PATCH 2/3] docs/features: Move the Vulkan 1.1 extensions to the 1.1 section

[Bas Nieuwenhuizen]

On Thu, Jul 12, 2018 at 1:03 AM, Jason Ekstrand  wrote:
> While we're at it, add some extensions we missed along the way like the
> VK_KHR_maintenanceN extensions.
> ---
>  docs/features.txt | 39 +--
>  1 file changed, 25 insertions(+), 14 deletions(-)
>
> diff --git a/docs/features.txt b/docs/features.txt
> index 0705ff9974b..61ca4d2da65 100644
> --- a/docs/features.txt
> +++ b/docs/features.txt
> @@ -354,39 +354,50 @@ we DO NOT WANT implementations of these extensions for 
> Mesa.
>
>  Vulkan 1.0 -- all DONE: anv, radv
>
> -Khronos extensions that are not part of any Vulkan version:
> +Vulkan 1.1 -- all DONE: anv, radv
> +
>VK_KHR_16bit_storage  in progress 
> (Alejandro)
> -  VK_KHR_android_surfacenot started
> +  VK_KHR_bind_memory2   DONE (anv, radv)
>VK_KHR_dedicated_allocation   DONE (anv, radv)
>VK_KHR_descriptor_update_template DONE (anv, radv)
> -  VK_KHR_displayDONE (anv, radv)
> -  VK_KHR_display_swapchain  DONE (anv, radv)
> +  VK_KHR_device_group   not started
> +  VK_KHR_device_group_creation  not started
>VK_KHR_external_fence DONE (anv, radv)
>VK_KHR_external_fence_capabilitiesDONE (anv, radv)
> -  VK_KHR_external_fence_fd  DONE (anv, radv)
> -  VK_KHR_external_fence_win32   not started
>VK_KHR_external_memoryDONE (anv, radv)
>VK_KHR_external_memory_capabilities   DONE (anv, radv)
> -  VK_KHR_external_memory_fd DONE (anv, radv)
> -  VK_KHR_external_memory_win32  not started
>VK_KHR_external_semaphore DONE (anv, radv)
>VK_KHR_external_semaphore_capabilitiesDONE (anv, radv)
> -  VK_KHR_external_semaphore_fd  DONE (anv, radv)
> -  VK_KHR_external_semaphore_win32   not started
>VK_KHR_get_memory_requirements2   DONE (anv, radv)
>VK_KHR_get_physical_device_properties2DONE (anv, radv)
> +  VK_KHR_maintenance1   DONE (anv, radv)
> +  VK_KHR_maintenance2   DONE (anv, radv)
> +  VK_KHR_maintenance3   DONE (anv, radv)
> +  VK_KHR_multiview  DONE (anv, radv)
> +  VK_KHR_relaxed_block_layout   DONE (anv, radv)
> +  VK_KHR_sampler_ycbcr_conversion   DONE (anv, radv)

Does it make sense to put radv here? Technically we implemented the
extension, but all we implemented was the bit to say "no we don't
support that".

> +  VK_KHR_shader_draw_parameters DONE (anv, radv)
> +  VK_KHR_storage_buffer_storage_class   DONE (anv, radv)
> +  VK_KHR_variable_pointers  DONE (anv, radv)
> +
> +Khronos extensions that are not part of any Vulkan version:
> +  VK_KHR_android_surfacenot started
> +  VK_KHR_displayDONE (anv, radv)
> +  VK_KHR_display_swapchain  DONE (anv, radv)
> +  VK_KHR_external_fence_fd  DONE (anv, radv)
> +  VK_KHR_external_fence_win32   not started
> +  VK_KHR_external_memory_fd DONE (anv, radv)
> +  VK_KHR_external_memory_win32  not started
> +  VK_KHR_external_semaphore_fd  DONE (anv, radv)
> +  VK_KHR_external_semaphore_win32   not started
>VK_KHR_get_surface_capabilities2  DONE (anv, radv)
>VK_KHR_incremental_presentDONE (anv, radv)
> -  VK_KHR_maintenance1   DONE (anv, radv)
>VK_KHR_mir_surfacenot started
>VK_KHR_push_descriptorDONE (anv, radv)
>VK_KHR_sampler_mirror_clamp_to_edge   DONE (anv, radv)
> -  VK_KHR_shader_draw_parameters DONE (anv, radv)
>VK_KHR_shared_presentable_image   not started
> -  VK_KHR_storage_buffer_storage_class   DONE (anv, radv)
>VK_KHR_surfaceDONE (anv, radv)
>VK_KHR_swapchain  DONE (anv, radv)
> -  VK_KHR_variable_pointers  DONE (anv, radv)
>VK_KHR_wayland_surfaceDONE (anv, radv)
>VK_KHR_win32_keyed_mutex 

Re: [Mesa-dev] [PATCH 9/9] winsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0

[Michel Dänzer]

On 2018-07-12 07:26 AM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> TODO: requires latest libdrm for amdgpu_bo_handle_type_kms_noimport
> ---
>  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c |  6 +++
>  src/gallium/winsys/amdgpu/drm/amdgpu_bo.h |  2 +
>  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 54 +--
>  3 files changed, 58 insertions(+), 4 deletions(-)
> 
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
> b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> index e3d56613dfa..eba8d6e8b3d 100644
> --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
> @@ -473,20 +473,22 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
> amdgpu_winsys *ws,
> bo->u.real.va_handle = va_handle;
> bo->initial_domain = initial_domain;
> bo->unique_id = __sync_fetch_and_add(>next_bo_unique_id, 1);
> bo->is_local = !!(request.flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID);
>  
> if (initial_domain & RADEON_DOMAIN_VRAM)
>ws->allocated_vram += align64(size, ws->info.gart_page_size);
> else if (initial_domain & RADEON_DOMAIN_GTT)
>ws->allocated_gtt += align64(size, ws->info.gart_page_size);
>  
> +   amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms_noimport, 
> >u.real.kms_handle);

How does using amdgpu_bo_handle_type_kms instead affect the numbers?


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Re: [Mesa-dev] [PATCH 5/5] radv: simplify the logic in radv_set_descriptor_set()

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

for the series.

On Tue, Jul 10, 2018 at 4:13 PM, Samuel Pitoiset
 wrote:
> Now that 'set' can't be NULL because the meta operations no
> longer bind a NULL descriptor, the logic can be simplified
> a little bit.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 6 ++
>  1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 11f4c29db4..e85a9d7c98 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -518,10 +518,8 @@ void radv_set_descriptor_set(struct radv_cmd_buffer 
> *cmd_buffer,
> radv_get_descriptors_state(cmd_buffer, bind_point);
>
> descriptors_state->sets[idx] = set;
> -   if (set)
> -   descriptors_state->valid |= (1u << idx);
> -   else
> -   descriptors_state->valid &= ~(1u << idx);
> +
> +   descriptors_state->valid |= (1u << idx); /* active descriptors */
> descriptors_state->dirty |= (1u << idx);
>  }
>
> --
> 2.18.0
>
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Re: [Mesa-dev] [PATCH 8/9] winsys/amdgpu: clean up error handling in amdgpu_cs_submit_ib

[Samuel Pitoiset]

With Timothy suggestions applied, patches 1-8 are:

Reviewed-by: Samuel Pitoiset 

On 07/12/2018 07:26 AM, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 17 -
  1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 872e67a790a..ac7160a5e51 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -1305,31 +1305,28 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
LIST_FOR_EACH_ENTRY(bo, >global_bo_list, u.real.global_list_item) {
   assert(num < ws->num_buffers);
   handles[num++] = bo->bo;
}
  
r = amdgpu_bo_list_create(ws->dev, ws->num_buffers,

  handles, NULL, _list);
simple_mtx_unlock(>global_bo_list_lock);
if (r) {
   fprintf(stderr, "amdgpu: buffer list creation failed (%d)\n", r);
- amdgpu_fence_signalled(cs->fence);
- cs->error_code = r;
   goto cleanup;
}
 } else {
unsigned num_handles;
  
if (!amdgpu_add_sparse_backing_buffers(cs)) {

   fprintf(stderr, "amdgpu: amdgpu_add_sparse_backing_buffers 
failed\n");
- amdgpu_fence_signalled(cs->fence);
- cs->error_code = -ENOMEM;
+ r = -ENOMEM;
   goto cleanup;
}
  
amdgpu_bo_handle *handles = alloca(sizeof(*handles) * cs->num_real_buffers);

uint8_t *flags = alloca(sizeof(*flags) * cs->num_real_buffers);
  
num_handles = 0;

for (i = 0; i < cs->num_real_buffers; ++i) {
   struct amdgpu_cs_buffer *buffer = >real_buffers[i];
  
@@ -1341,22 +1338,20 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)

   handles[num_handles] = buffer->bo->bo;
   flags[num_handles] = (util_last_bit(buffer->u.real.priority_usage) - 
1) / 2;
 ++num_handles;
}
  
if (num_handles) {

   r = amdgpu_bo_list_create(ws->dev, num_handles,
 handles, flags, _list);
   if (r) {
  fprintf(stderr, "amdgpu: buffer list creation failed (%d)\n", r);
-amdgpu_fence_signalled(cs->fence);
-cs->error_code = r;
  goto cleanup;
   }
}
 }
  
 if (acs->ring_type == RING_GFX)

ws->gfx_bo_list_counter += cs->num_real_buffers;
  
 if (acs->ctx->num_rejected_cs) {

r = -ECANCELED;
@@ -1451,48 +1446,52 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
   chunks[num_chunks].chunk_data = (uintptr_t)sem_chunk;
   num_chunks++;
}
  
assert(num_chunks <= ARRAY_SIZE(chunks));
  
r = amdgpu_cs_submit_raw(ws->dev, acs->ctx->ctx, bo_list,

 num_chunks, chunks, _no);
 }
  
-   cs->error_code = r;

 if (r) {
if (r == -ENOMEM)
   fprintf(stderr, "amdgpu: Not enough memory for command 
submission.\n");
else if (r == -ECANCELED)
   fprintf(stderr, "amdgpu: The CS has been cancelled because the context is 
lost.\n");
else
   fprintf(stderr, "amdgpu: The CS has been rejected, "
   "see dmesg for more information (%i).\n", r);
  
-  amdgpu_fence_signalled(cs->fence);

-
acs->ctx->num_rejected_cs++;
ws->num_total_rejected_cs++;
 } else {
/* Success. */
uint64_t *user_fence = NULL;
  
if (has_user_fence)

   user_fence = acs->ctx->user_fence_cpu_address_base + acs->ring_type;
amdgpu_fence_submitted(cs->fence, seq_no, user_fence);
 }
  
 /* Cleanup. */

 if (bo_list)
amdgpu_bo_list_destroy(bo_list);
  
  cleanup:

+   /* If there was an error, signal the fence, because it won't be signalled
+* by the hardware. */
+   if (r)
+  amdgpu_fence_signalled(cs->fence);
+
+   cs->error_code = r;
+
 for (i = 0; i < cs->num_real_buffers; i++)
p_atomic_dec(>real_buffers[i].bo->num_active_ioctls);
 for (i = 0; i < cs->num_slab_buffers; i++)
p_atomic_dec(>slab_buffers[i].bo->num_active_ioctls);
 for (i = 0; i < cs->num_sparse_buffers; i++)
p_atomic_dec(>sparse_buffers[i].bo->num_active_ioctls);
  
 amdgpu_cs_context_cleanup(cs);

  }
  


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Re: [Mesa-dev] [PATCH 9/9] winsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0

[Samuel Pitoiset]

On 07/12/2018 08:21 AM, Timothy Arceri wrote:

On 12/07/18 15:26, Marek Olšák wrote:

From: Marek Olšák 

TODO: requires latest libdrm for amdgpu_bo_handle_type_kms_noimport



Forgot to bump this?


libdrm doesn't seem to contain the required function. I guess Marek has 
some local patches and he will release a new libdrm when it's ready.



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[Mesa-dev] [Bug 107169] [regression] Upgrade from 18.0.4 to 18.1.0 causes severe stuttering in games

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107169

--- Comment #4 from Denis  ---
>GPU: Ati Radeon HD3000
oh... my bad, yesterday I was sure that I saw here Intel HD3000 :( And I had
exactly that GPU... Do you have any intel card to check the issue (whether it
actual or not on it?)

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Re: [Mesa-dev] [Mesa-stable] [PATCH v3] radv: make sure to wait for CP DMA when needed

[Samuel Pitoiset]

On 07/11/2018 06:52 PM, Dylan Baker wrote:

Quoting Samuel Pitoiset (2018-07-09 09:02:58)

This might fix some synchronization issues. I don't know if
that will affect performance but it's required for correctness.

v3: - wait for CP DMA in CmdPipelineBarrier()
 - clear the busy value when CP_DMA_SYNC is requested
v2: - wait for CP DMA in CmdWaitEvents()
 - track if CP DMA is used

CC: 
Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_cmd_buffer.c | 15 +
  src/amd/vulkan/radv_private.h|  5 +
  src/amd/vulkan/si_cmd_buffer.c   | 36 
  3 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 9da42fe03e..5dbdb3d996 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2596,6 +2596,11 @@ VkResult radv_EndCommandBuffer(
 si_emit_cache_flush(cmd_buffer);
 }
  
+   /* Make sure CP DMA is idle at the end of IBs because the kernel

+* doesn't wait for it.
+*/
+   si_cp_dma_wait_for_idle(cmd_buffer);
+
 vk_free(_buffer->pool->alloc, cmd_buffer->state.attachments);
  
 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))

@@ -4242,6 +4247,11 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer,
  0);
 }
  
+   /* Make sure CP DMA is idle because the driver might have performed a

+* DMA operation for copying or filling buffers/images.
+*/
+   si_cp_dma_wait_for_idle(cmd_buffer);
+
 cmd_buffer->state.flush_bits |= dst_flush_bits;
  }
  
@@ -4292,6 +4302,11 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,

 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
  
+   /* Make sure CP DMA is idle because the driver might have performed a

+* DMA operation for copying or filling buffers/images.
+*/
+   si_cp_dma_wait_for_idle(cmd_buffer);
+
 /* TODO: Emit EOS events for syncing PS/CS stages. */
  
 if (!(stageMask & ~top_of_pipe_flags)) {

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 4e4b3a6037..2400de49a2 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -979,6 +979,9 @@ struct radv_cmd_state {
 uint32_t last_num_instances;
 uint32_t last_first_instance;
 uint32_t last_vertex_offset;
+
+   /* Whether CP DMA is busy/idle. */
+   bool dma_is_busy;
  };
  
  struct radv_cmd_pool {

@@ -1091,6 +1094,8 @@ void si_cp_dma_prefetch(struct radv_cmd_buffer 
*cmd_buffer, uint64_t va,
  unsigned size);
  void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 uint64_t size, unsigned value);
+void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer);
+
  void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
  bool
  radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 454fd8c39c..6d566a918d 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1040,7 +1040,6 @@ static void si_emit_cp_dma(struct radv_cmd_buffer 
*cmd_buffer,
 struct radeon_cmdbuf *cs = cmd_buffer->cs;
 uint32_t header = 0, command = 0;
  
-   assert(size);

 assert(size <= cp_dma_max_byte_count(cmd_buffer));
  
 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9);

@@ -1099,9 +1098,14 @@ static void si_emit_cp_dma(struct radv_cmd_buffer 
*cmd_buffer,
  * indices. If we wanted to execute CP DMA in PFP, this packet
  * should precede it.
  */
-   if ((flags & CP_DMA_SYNC) && cmd_buffer->queue_family_index == 
RADV_QUEUE_GENERAL) {
-   radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 
cmd_buffer->state.predicating));
-   radeon_emit(cs, 0);
+   if (flags & CP_DMA_SYNC) {
+   if (cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
+   radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 
cmd_buffer->state.predicating));
+   radeon_emit(cs, 0);
+   }
+
+   /* CP will see the sync flag and wait for all DMAs to complete. 
*/
+   cmd_buffer->state.dma_is_busy = false;
 }
  
 if (unlikely(cmd_buffer->device->trace_bo))

@@ -1165,6 +1169,8 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer 
*cmd_buffer,
 uint64_t main_src_va, main_dest_va;
 uint64_t skipped_size = 0, realign_size = 0;
  
+   /* Assume that we are not going to sync after the last DMA operation. */

+   cmd_buffer->state.dma_is_busy = true;
  
 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||

 

Re: [Mesa-dev] [PATCH] vulkan: Fix compilation on older platforms

[Danylo Piliaiev]

On 11.07.18 20:43, Dylan Baker wrote:

Quoting Danylo Piliaiev (2018-07-11 04:26:03)

diff --git a/meson.build b/meson.build
index 7d12af3d51..2683060827 100644
--- a/meson.build
+++ b/meson.build
@@ -1088,6 +1088,8 @@ _drm_freedreno_ver = '2.4.92'
  _drm_intel_ver = '2.4.75'
  _drm_ver = '2.4.75'
  
+_drm_crt_sequence_ver = '2.4.89'

+
  _libdrm_checks = [
['intel', with_dri_i915 or with_gallium_i915],
['amdgpu', with_amd_vk or with_gallium_radeonsi],
@@ -1361,11 +1363,18 @@ if with_platform_x11
  dep_xcb_xfixes = dependency('xcb-xfixes')
endif
if with_xlib_lease
-dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.12')
+dep_xcb_xrandr = dependency('xcb-randr', version : '>= 1.13')
  dep_xlib_xrandr = dependency('xrandr', version : '>= 1.3')
endif
  endif
  
+if with_any_vk

+  dep_drm_crt_sequence = dependency('libdrm', version : '>=' + 
_drm_crt_sequence_ver, required : false)
+  if dep_drm_crt_sequence.found()
+pre_args += '-DVK_USE_DISPLAY_CONTROL'
+  endif
+endif
+

Instead of calling into pkg-config again, how about in the "if
dep_libdrm.found()" check around line 1131, we add:

if with_any_vk
   if dep_libdrm.version().version_compare('>= ' + _drm_crt_sequence_ver):
 pre_args += '-DVK_USE_DISPLAY_CONTROL'
   endif
endif

You are right, this would be better.

Or (since radv always requires libdrm > 2.4.89), why don't we just set the set
the minimum to 2.4.89 if vulkan is enabled and be done with it?

It's also affects anv which requires only libdrm >= 2.4.75


Dylan


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Re: [Mesa-dev] [PATCH 7/9] radeonsi: rework RADEON_PRIO flags to be <= 31

[Timothy Arceri]

Two suggestions below.

On 12/07/18 15:26, Marek Olšák wrote:

From: Marek Olšák 

This decreases sizeof(struct amdgpu_cs_buffer) from 24 to 16 bytes.
---
  src/gallium/drivers/radeon/radeon_winsys.h| 39 ++-
  src/gallium/drivers/radeonsi/si_debug.c   |  2 +-
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.c |  6 +--
  src/gallium/winsys/amdgpu/drm/amdgpu_cs.h |  4 +-
  src/gallium/winsys/radeon/drm/radeon_drm_cs.c |  2 +-
  src/gallium/winsys/radeon/drm/radeon_drm_cs.h |  2 +-
  6 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index bcd6831ed35..10c63ae4d82 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -108,63 +108,64 @@ enum radeon_value_id {
  RADEON_VRAM_USAGE,
  RADEON_VRAM_VIS_USAGE,
  RADEON_GTT_USAGE,
  RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
  RADEON_CURRENT_SCLK,
  RADEON_CURRENT_MCLK,
  RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
  RADEON_CS_THREAD_TIME,
  };
  
-/* Each group of four has the same priority. */

  enum radeon_bo_priority {
+/* Each group of two has the same priority. */
  RADEON_PRIO_FENCE = 0,
  RADEON_PRIO_TRACE,
-RADEON_PRIO_SO_FILLED_SIZE,
+
+RADEON_PRIO_SO_FILLED_SIZE = 2,
  RADEON_PRIO_QUERY,
  
  RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */

  RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
-RADEON_PRIO_DRAW_INDIRECT,
+
+RADEON_PRIO_DRAW_INDIRECT = 6,
  RADEON_PRIO_INDEX_BUFFER,
  
-RADEON_PRIO_CP_DMA = 12,

+RADEON_PRIO_CP_DMA = 8,
+RADEON_PRIO_BORDER_COLORS,
  
-RADEON_PRIO_CONST_BUFFER = 16,

+RADEON_PRIO_CONST_BUFFER = 10,
  RADEON_PRIO_DESCRIPTORS,
-RADEON_PRIO_BORDER_COLORS,
  
-RADEON_PRIO_SAMPLER_BUFFER = 20,

+RADEON_PRIO_SAMPLER_BUFFER = 12,
  RADEON_PRIO_VERTEX_BUFFER,
  
-RADEON_PRIO_SHADER_RW_BUFFER = 24,

+RADEON_PRIO_SHADER_RW_BUFFER = 14,
  RADEON_PRIO_COMPUTE_GLOBAL,
  
-RADEON_PRIO_SAMPLER_TEXTURE = 28,

+RADEON_PRIO_SAMPLER_TEXTURE = 16,
  RADEON_PRIO_SHADER_RW_IMAGE,
  
-RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 32,

-
-RADEON_PRIO_COLOR_BUFFER = 36,
+RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 18,
+RADEON_PRIO_COLOR_BUFFER,
  
-RADEON_PRIO_DEPTH_BUFFER = 40,

+RADEON_PRIO_DEPTH_BUFFER = 20,
  
-RADEON_PRIO_COLOR_BUFFER_MSAA = 44,

+RADEON_PRIO_COLOR_BUFFER_MSAA = 22,
  
-RADEON_PRIO_DEPTH_BUFFER_MSAA = 48,

+RADEON_PRIO_DEPTH_BUFFER_MSAA = 24,
  
-RADEON_PRIO_SEPARATE_META = 52,

+RADEON_PRIO_SEPARATE_META = 26,
  RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses 
*/
  
-RADEON_PRIO_SHADER_RINGS = 56,

+RADEON_PRIO_SHADER_RINGS = 28,
  
-RADEON_PRIO_SCRATCH_BUFFER = 60,

+RADEON_PRIO_SCRATCH_BUFFER = 30,
  /* 63 is the maximum value */


31 is the maximum value ???





  };
  
  struct winsys_handle;

  struct radeon_winsys_ctx;
  
  struct radeon_cmdbuf_chunk {

  unsigned cdw;  /* Number of used dwords. */
  unsigned max_dw; /* Maximum number of dwords. */
  uint32_t *buf; /* The base pointer of the chunk. */
@@ -216,21 +217,21 @@ struct radeon_bo_metadata {
  };
  
  enum radeon_feature_id {

  RADEON_FID_R300_HYPERZ_ACCESS, /* ZMask + HiZ */
  RADEON_FID_R300_CMASK_ACCESS,
  };
  
  struct radeon_bo_list_item {

  uint64_t bo_size;
  uint64_t vm_address;
-uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
+uint32_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
  };
  
  struct radeon_winsys {

  /**
   * The screen object this winsys was created for
   */
  struct pipe_screen *screen;
  
  /**

   * Decrement the winsys reference count.
diff --git a/src/gallium/drivers/radeonsi/si_debug.c 
b/src/gallium/drivers/radeonsi/si_debug.c
index 50375ce7cbe..d6207e68d12 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -562,21 +562,21 @@ static void si_dump_bo_list(struct si_context *sctx,
(va - previous_va_end) / page_size);
}
}
  
  		/* Print the buffer. */

fprintf(f, "  %10"PRIu64"0x%013"PRIX64"   0x%013"PRIX64" 
  ",
size / page_size, va / page_size, (va + size) / 
page_size);
  
  		/* Print the usage. */

for (j = 0; j < 64; j++) {


   for (j = 0; j < 32; j++) {


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Re: [Mesa-dev] [PATCH 9/9] winsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0

[Timothy Arceri]

On 12/07/18 15:26, Marek Olšák wrote:

From: Marek Olšák 

TODO: requires latest libdrm for amdgpu_bo_handle_type_kms_noimport



Forgot to bump this?
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