[Mesa-dev] [PATCH 2/2] util: add drirc workarounds for RAGE

[Timothy Arceri]

This allows the game to run on wine (tested on radeonsi where we
have compat profile support).
---
 src/util/drirc | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/util/drirc b/src/util/drirc
index c4f9e060f3a..ad59efba50b 100644
--- a/src/util/drirc
+++ b/src/util/drirc
@@ -100,6 +100,14 @@ TODO: document the other workarounds.
 
 
 
+
+
+
+
+
+
+
+
 
 
 
-- 
2.17.1

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[Mesa-dev] [PATCH 1/2] util: better handle program names from wine

[Timothy Arceri]

For some reason wine will sometimes give us a windows style path
for an application. For example when running the 64bit version
of Rage wine gives a Unix style path, but when running the 32bit
version is gives a windows style path.

If we detect no '/' in the path at all it should be safe to
assume we have a wine application and instead look for a '\'.
---
 src/util/u_process.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/util/u_process.c b/src/util/u_process.c
index 5bf3f56db4e..e8da10ffcad 100644
--- a/src/util/u_process.c
+++ b/src/util/u_process.c
@@ -40,11 +40,19 @@ extern char *program_invocation_name, 
*program_invocation_short_name;
 static const char *
 __getProgramName()
 {
-char * arg = strrchr(program_invocation_name, '/');
-if (arg)
-return arg+1;
-else
-return program_invocation_name;
+   char * arg = strrchr(program_invocation_name, '/');
+   if (arg) {
+  return arg+1;
+   } else {
+  /* If there was no '/' at all we likely have a windows like path from
+   * a wine application.
+   */
+  char * arg = strrchr(program_invocation_name, '\\');
+  if (arg)
+ return arg+1;
+
+  return program_invocation_name;
+   }
 }
 #define GET_PROGRAM_NAME() __getProgramName()
 #elif defined(__CYGWIN__)
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 1/9] util/dynarray: add a clone function

[Thomas Helland]

2018-08-15 23:56 GMT+02:00 Caio Marcelo de Oliveira Filho
:
> ---
>  src/util/u_dynarray.h | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/util/u_dynarray.h b/src/util/u_dynarray.h
> index dcbbc06d161..4920fe04b67 100644
> --- a/src/util/u_dynarray.h
> +++ b/src/util/u_dynarray.h
> @@ -102,6 +102,15 @@ util_dynarray_resize(struct util_dynarray *buf, unsigned 
> newsize)
> return p;
>  }
>
> +static inline void
> +util_dynarray_clone(struct util_dynarray *buf, struct util_dynarray *mem_ctx,

I think we should keep the mem_ctx a void *.
Apart from that this patch is:

Reviewed-by: Thomas Helland 

> +struct util_dynarray *from_buf)
> +{
> +   util_dynarray_init(buf, mem_ctx);
> +   util_dynarray_resize(buf, from_buf->size);
> +   memcpy(buf->data, from_buf->data, from_buf->size);
> +}
> +
>  static inline void *
>  util_dynarray_grow(struct util_dynarray *buf, int diff)
>  {
> --
> 2.18.0
>
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[Mesa-dev] [Bug 106955] Mesa 18.1.2 not tagged in git

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106955

--- Comment #3 from Daniel Stone  ---
The tag is there: https://cgit.freedesktop.org/mesa/mesa/refs/tags

We were failing to push tags for a while but it was fixed some time ago.

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Re: [Mesa-dev] [PATCH] glsl: Avoid calling get_array_element for scalar constants

[Tapani Pälli]

On 08/16/2018 02:21 AM, Andres Gomez wrote:

Danylo, should we also include this in the stable queues ?


Yep makes sense, it's simple and fixes a crasher.



On Mon, 2018-08-13 at 18:57 +0300, Danylo Piliaiev wrote:

Accessing scalar constant as an array in function call or
initializer list triggered assert in get_array_element.
Examples:
func(0[0]);
vec2 t = { 0[0], 0 };

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107550

Signed-off-by: Danylo Piliaiev 
---
  src/compiler/glsl/ir_constant_expression.cpp | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/glsl/ir_constant_expression.cpp 
b/src/compiler/glsl/ir_constant_expression.cpp
index 4a0aff72c6..c9788c7053 100644
--- a/src/compiler/glsl/ir_constant_expression.cpp
+++ b/src/compiler/glsl/ir_constant_expression.cpp
@@ -826,7 +826,7 @@ ir_dereference_array::constant_expression_value(void 
*mem_ctx,
   const unsigned component = idx->value.u[0];
  
   return new(mem_ctx) ir_constant(array, component);

-  } else {
+  } else if (array->type->is_array()) {
   const unsigned index = idx->value.u[0];
   return array->get_array_element(index)->clone(mem_ctx, NULL);
}

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Re: [Mesa-dev] [PATCH] radv: Possible demand compilation fix.

[Timothy Arceri]

Thanks fixes steamvr for me :)

Tested-by: Timothy Arceri 
Reviewed-by: Timothy Arceri 

On 16/08/18 00:25, Bas Nieuwenhuizen wrote:

Seems that in a single case we use the renderpass before checking
the pipeline, so check the renderpass before we use it.

Fixes: fbcd1673144 "radv: Add on-demand compilation of built-in shaders."
---
  src/amd/vulkan/radv_meta_resolve_fs.c | 8 
  1 file changed, 8 insertions(+)

diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c 
b/src/amd/vulkan/radv_meta_resolve_fs.c
index 21a5922f5df..af4a6fe7a66 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -463,6 +463,14 @@ void radv_meta_resolve_fragment_image(struct 
radv_cmd_buffer *cmd_buffer,
radv_decompress_resolve_src(cmd_buffer, src_image, src_image_layout,
region_count, regions);
  
+	if (!device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout]) {

+   VkResult ret = create_resolve_pipeline(device, samples_log2, 
radv_fs_key_format_exemplars[fs_key]);
+   if (ret != VK_SUCCESS) {
+   cmd_buffer->record_result = ret;
+   return;
+   }
+   }
+
rp = 
device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout];
  
  	radv_meta_save(_state, cmd_buffer,



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Re: [Mesa-dev] [PATCH 1/3] freedreno: Fix warnings

[Kristian Høgsberg]

The remaining two patches are stuck in moderation for being too big.
They update the generated headers and adds the a6xx backend. They're
in this branch:

  https://gitlab.freedesktop.org/krh/mesa/commits/wip/a6xx-rebase-3

for reference.

Kristian

On Wed, Aug 15, 2018 at 9:18 AM Kristian H. Kristensen
 wrote:
>
> From: "Kristian H. Kristensen" 
>
> Signed-off-by: Kristian H. Kristensen 
> ---
>  src/gallium/drivers/freedreno/a5xx/fd5_compute.c   | 2 +-
>  src/gallium/drivers/freedreno/freedreno_resource.c | 8 
>  src/gallium/drivers/freedreno/ir3/ir3.h| 8 ++--
>  src/gallium/drivers/freedreno/ir3/ir3_cmdline.c| 2 +-
>  src/gallium/drivers/freedreno/ir3/ir3_shader.h | 4 +---
>  5 files changed, 9 insertions(+), 15 deletions(-)
>
> diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c 
> b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
> index 8e2c228e90..66ed7a4af5 100644
> --- a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
> +++ b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
> @@ -181,7 +181,7 @@ static void
>  fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
>  {
> struct fd5_compute_stateobj *so = ctx->compute;
> -   struct ir3_shader_key key = {0};
> +   struct ir3_shader_key key = {};
> struct ir3_shader_variant *v;
> struct fd_ringbuffer *ring = ctx->batch->draw;
> unsigned i, nglobal = 0;
> diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c 
> b/src/gallium/drivers/freedreno/freedreno_resource.c
> index 3fbf50003e..f882cf5a8b 100644
> --- a/src/gallium/drivers/freedreno/freedreno_resource.c
> +++ b/src/gallium/drivers/freedreno/freedreno_resource.c
> @@ -211,7 +211,7 @@ fd_try_shadow_resource(struct fd_context *ctx, struct 
> fd_resource *rsc,
>
> mtx_unlock(>screen->lock);
>
> -   struct pipe_blit_info blit = {0};
> +   struct pipe_blit_info blit = {};
> blit.dst.resource = prsc;
> blit.dst.format   = prsc->format;
> blit.src.resource = pshadow;
> @@ -305,7 +305,7 @@ static void
>  fd_blit_from_staging(struct fd_context *ctx, struct fd_transfer *trans)
>  {
> struct pipe_resource *dst = trans->base.resource;
> -   struct pipe_blit_info blit = {0};
> +   struct pipe_blit_info blit = {};
>
> blit.dst.resource = dst;
> blit.dst.format   = dst->format;
> @@ -325,7 +325,7 @@ static void
>  fd_blit_to_staging(struct fd_context *ctx, struct fd_transfer *trans)
>  {
> struct pipe_resource *src = trans->base.resource;
> -   struct pipe_blit_info blit = {0};
> +   struct pipe_blit_info blit = {};
>
> blit.src.resource = src;
> blit.src.format   = src->format;
> @@ -372,7 +372,7 @@ flush_resource(struct fd_context *ctx, struct fd_resource 
> *rsc, unsigned usage)
> fd_batch_reference(_batch, rsc->write_batch);
>
> if (usage & PIPE_TRANSFER_WRITE) {
> -   struct fd_batch *batch, *batches[32] = {0};
> +   struct fd_batch *batch, *batches[32] = {};
> uint32_t batch_mask;
>
> /* This is a bit awkward, probably a fd_batch_flush_locked()
> diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h 
> b/src/gallium/drivers/freedreno/ir3/ir3.h
> index 8bac91660b..63215cefc9 100644
> --- a/src/gallium/drivers/freedreno/ir3/ir3.h
> +++ b/src/gallium/drivers/freedreno/ir3/ir3.h
> @@ -445,14 +445,12 @@ struct ir3 {
>  #endif
>  };
>
> -typedef struct nir_register nir_register;
> -
>  struct ir3_array {
> struct list_head node;
> unsigned length;
> unsigned id;
>
> -   nir_register *r;
> +   struct nir_register *r;
>
> /* To avoid array write's from getting DCE'd, keep track of the
>  * most recent write.  Any array access depends on the most
> @@ -470,13 +468,11 @@ struct ir3_array {
>
>  struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
>
> -typedef struct nir_block nir_block;
> -
>  struct ir3_block {
> struct list_head node;
> struct ir3 *shader;
>
> -   const nir_block *nblock;
> +   const struct nir_block *nblock;
>
> struct list_head instr_list;  /* list of ir3_instruction */
>
> diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c 
> b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
> index 23d5006352..b41c32d375 100644
> --- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
> +++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
> @@ -379,7 +379,7 @@ int main(int argc, char **argv)
>
> while (n < argc) {
> char *filename = argv[n];
> -   char *ext = rindex(filename, '.');
> +   char *ext = strrchr(filename, '.');
>
> if (strcmp(ext, ".tgsi") == 0) {
> if (num_files != 0)
> diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h 
> b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
> index 507e89c473..288e9fa4e7 100644
> --- 

Re: [Mesa-dev] [PATCH] meson: fix build for egl platform_x11

[Matt Turner]

On Wed, Aug 15, 2018 at 1:54 PM Alexander Tsoy  wrote:
>
> platform_x11 needs inc_loader:
>
> ../mesa-18.2.0-rc2/src/egl/drivers/dri2/platform_x11.c:48:10: fatal
> error: loader.h: No such file or directory
>  #include "loader.h"
>   ^~
> ---

Thank you.

I know this patch is to fix a reported bug, but others don't, so please put

Bugzilla: https://bugs.gentoo.org/663534

in the patch.

Also, it's required to have some description of the problem that
explains how to reproduce. In this case from the bug report I know
that disabling gbm and dri3 is enough to cause it.

Reviewed-by: Matt Turner 

I will add the Bugzilla tag and an appropriate commit message, tag it
for stable, and commit it.

Thanks for the patch!
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Re: [Mesa-dev] [PATCH] glsl: Avoid calling get_array_element for scalar constants

[Andres Gomez]

Danylo, should we also include this in the stable queues ?


On Mon, 2018-08-13 at 18:57 +0300, Danylo Piliaiev wrote:
> Accessing scalar constant as an array in function call or
> initializer list triggered assert in get_array_element.
> Examples:
>func(0[0]);
>vec2 t = { 0[0], 0 };
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107550
> 
> Signed-off-by: Danylo Piliaiev 
> ---
>  src/compiler/glsl/ir_constant_expression.cpp | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/compiler/glsl/ir_constant_expression.cpp 
> b/src/compiler/glsl/ir_constant_expression.cpp
> index 4a0aff72c6..c9788c7053 100644
> --- a/src/compiler/glsl/ir_constant_expression.cpp
> +++ b/src/compiler/glsl/ir_constant_expression.cpp
> @@ -826,7 +826,7 @@ ir_dereference_array::constant_expression_value(void 
> *mem_ctx,
>   const unsigned component = idx->value.u[0];
>  
>   return new(mem_ctx) ir_constant(array, component);
> -  } else {
> +  } else if (array->type->is_array()) {
>   const unsigned index = idx->value.u[0];
>   return array->get_array_element(index)->clone(mem_ctx, NULL);
>}
-- 
Br,

Andres
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Re: [Mesa-dev] [PATCH] Revert "intel/nir: Call nir_lower_io_to_scalar_early"

[Jason Ekstrand]

On Wed, Aug 15, 2018 at 5:36 PM Timothy Arceri 
wrote:

> On 16/08/18 02:10, Jason Ekstrand wrote:
> > On Tue, Aug 14, 2018 at 7:25 PM Timothy Arceri  > > wrote:
> >
> > On 09/08/18 05:05, Jason Ekstrand wrote:
> >  > Commit 4434591bf56a6b0 caused substantially more URB messages in
> >  > geometry and tessellation shaders.  Before we can really enable
> this
> >  > sort of optimization,  We either need some way of combining them
> back
> >  > together into vectors or we need to do cross-stage vector element
> >  > elimination without splitting everything into scalars.
> >
> > You should be calling:
> >
> > nir_compact_varyings() after remove_unused_varyings this should do
> most
> > of what you want.
> >
> >
> > Does that turn things back into vectors?  The problem we're hitting is
> > not that things aren't compacted, it's that we want to read/write whole
> > vectors at a time as much as possible.  Just reverting the patch isn't
> > quite the proper solution because we want to be able to compact things
> > and it would be nice if we could load two variables at a time if they're
> > packed side-by-side in one vec4.  However, it does solve the perf
> > regression for now.
>
> Yes. nir_compact_varyings() compacts everything into vec4s. The only
> thing it doesn't currently do is compact the locations (the nir->llvm
> pass does this for radeonsi anyway).
>

I think I was unclear.  nir_compact_varyings does pack things tightly but
it doesn't turn each set of 4 scalar vars into a single vec4 var which is
what we would need in order for it to fix the perf problem caused by these
patches.
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Re: [Mesa-dev] [PATCH] Revert "intel/nir: Call nir_lower_io_to_scalar_early"

[Mark Janes]

This corrects all of the performance regressions that I can see on our
perf CI.

Please make sure to add the fixes tag before pushing.

Tested-by: Mark Janes 

Jason Ekstrand  writes:

> Commit 4434591bf56a6b0 caused substantially more URB messages in
> geometry and tessellation shaders.  Before we can really enable this
> sort of optimization,  We either need some way of combining them back
> together into vectors or we need to do cross-stage vector element
> elimination without splitting everything into scalars.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107510
> ---
>  src/intel/compiler/brw_nir.c | 17 +
>  1 file changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
> index 31ffbe613ec..29ad68fdb2a 100644
> --- a/src/intel/compiler/brw_nir.c
> +++ b/src/intel/compiler/brw_nir.c
> @@ -713,18 +713,6 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
> nir_validate_shader(*producer);
> nir_validate_shader(*consumer);
>  
> -   const bool p_is_scalar =
> -  compiler->scalar_stage[(*producer)->info.stage];
> -   const bool c_is_scalar =
> -  compiler->scalar_stage[(*consumer)->info.stage];
> -
> -   if (p_is_scalar && c_is_scalar) {
> -  NIR_PASS_V(*producer, nir_lower_io_to_scalar_early, 
> nir_var_shader_out);
> -  NIR_PASS_V(*consumer, nir_lower_io_to_scalar_early, nir_var_shader_in);
> -  *producer = brw_nir_optimize(*producer, compiler, p_is_scalar);
> -  *consumer = brw_nir_optimize(*consumer, compiler, c_is_scalar);
> -   }
> -
> NIR_PASS_V(*producer, nir_remove_dead_variables, nir_var_shader_out);
> NIR_PASS_V(*consumer, nir_remove_dead_variables, nir_var_shader_in);
>  
> @@ -741,7 +729,12 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
>NIR_PASS_V(*consumer, nir_lower_indirect_derefs,
>   brw_nir_no_indirect_mask(compiler, 
> (*consumer)->info.stage));
>  
> +  const bool p_is_scalar =
> + compiler->scalar_stage[(*producer)->info.stage];
>*producer = brw_nir_optimize(*producer, compiler, p_is_scalar);
> +
> +  const bool c_is_scalar =
> + compiler->scalar_stage[(*consumer)->info.stage];
>*consumer = brw_nir_optimize(*consumer, compiler, c_is_scalar);
> }
>  }
> -- 
> 2.17.1
>
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Re: [Mesa-dev] [PATCH] Revert "intel/nir: Call nir_lower_io_to_scalar_early"

[Timothy Arceri]

On 16/08/18 02:10, Jason Ekstrand wrote:
On Tue, Aug 14, 2018 at 7:25 PM Timothy Arceri > wrote:


On 09/08/18 05:05, Jason Ekstrand wrote:
 > Commit 4434591bf56a6b0 caused substantially more URB messages in
 > geometry and tessellation shaders.  Before we can really enable this
 > sort of optimization,  We either need some way of combining them back
 > together into vectors or we need to do cross-stage vector element
 > elimination without splitting everything into scalars.

You should be calling:

nir_compact_varyings() after remove_unused_varyings this should do most
of what you want.


Does that turn things back into vectors?  The problem we're hitting is 
not that things aren't compacted, it's that we want to read/write whole 
vectors at a time as much as possible.  Just reverting the patch isn't 
quite the proper solution because we want to be able to compact things 
and it would be nice if we could load two variables at a time if they're 
packed side-by-side in one vec4.  However, it does solve the perf 
regression for now.


Yes. nir_compact_varyings() compacts everything into vec4s. The only 
thing it doesn't currently do is compact the locations (the nir->llvm 
pass does this for radeonsi anyway).




--Jason

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[Mesa-dev] [PATCH 4/9] nir: Give end_block its own index

[Caio Marcelo de Oliveira Filho]

Since there's no particular reason for the index to be 0, choose an
index that is not used by other block.  This is convenient when we
store "per-block" data in an array AND look for the successors
data (e.g. any kind of backwards data-flow analysis).
---
 src/compiler/nir/nir.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index e12aa5d80f5..1a5cfc27b74 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -1641,7 +1641,7 @@ nir_index_blocks(nir_function_impl *impl)
   block->index = index++;
}
 
-   impl->num_blocks = index;
+   impl->num_blocks = impl->end_block->index = index;
 }
 
 static bool
-- 
2.18.0

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[Mesa-dev] [PATCH 5/9] nir: Add a local dead write vars removal pass

[Caio Marcelo de Oliveira Filho]

Instead of doing this as part of the existing (local) copy prop vars
pass.  This is an intermediate step before changing both the dead
write and the copy prop vars to act on the whole program instead of on
local blocks.  The nature of data we store and the way we iterate is
different enough that would be awkward keeping those together.
---
 src/compiler/Makefile.sources  |   1 +
 src/compiler/nir/meson.build   |   1 +
 src/compiler/nir/nir.h |   2 +
 src/compiler/nir/nir_opt_dead_write_vars.c | 243 +
 4 files changed, 247 insertions(+)
 create mode 100644 src/compiler/nir/nir_opt_dead_write_vars.c

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 27a54e0be09..fa93ad08a16 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -274,6 +274,7 @@ NIR_FILES = \
nir/nir_opt_cse.c \
nir/nir_opt_dce.c \
nir/nir_opt_dead_cf.c \
+   nir/nir_opt_dead_write_vars.c \
nir/nir_opt_gcm.c \
nir/nir_opt_global_to_local.c \
nir/nir_opt_if.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 8708f9b069c..1c164a548a7 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -158,6 +158,7 @@ files_libnir = files(
   'nir_opt_cse.c',
   'nir_opt_dce.c',
   'nir_opt_dead_cf.c',
+  'nir_opt_dead_write_vars.c',
   'nir_opt_gcm.c',
   'nir_opt_global_to_local.c',
   'nir_opt_if.c',
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index d0fa693884b..becf6e351c3 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2968,6 +2968,8 @@ bool nir_opt_dce(nir_shader *shader);
 
 bool nir_opt_dead_cf(nir_shader *shader);
 
+bool nir_opt_dead_write_vars(nir_shader *shader);
+
 bool nir_opt_gcm(nir_shader *shader, bool value_number);
 
 bool nir_opt_if(nir_shader *shader);
diff --git a/src/compiler/nir/nir_opt_dead_write_vars.c 
b/src/compiler/nir/nir_opt_dead_write_vars.c
new file mode 100644
index 000..822bfa5595d
--- /dev/null
+++ b/src/compiler/nir/nir_opt_dead_write_vars.c
@@ -0,0 +1,243 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_builder.h"
+#include "nir_deref.h"
+
+#include "util/u_dynarray.h"
+
+struct state {
+   void *mem_ctx;
+
+   /* Maps nir_deref_instr to a corresponding nir_deref_path.  Avoids
+* rebuilding the paths for the same deref. */
+   struct hash_table *paths;
+   void *path_lin_ctx;
+};
+
+static nir_deref_path *
+get_path(struct state *state, nir_deref_instr *deref)
+{
+   struct hash_entry *entry = _mesa_hash_table_search(state->paths, deref);
+   if (!entry) {
+  nir_deref_path *path = linear_zalloc_child(state->path_lin_ctx, 
sizeof(nir_deref_path));
+  nir_deref_path_init(path, deref, state->mem_ctx);
+  _mesa_hash_table_insert(state->paths, deref, path);
+  return path;
+   } else {
+  return entry->data;
+   }
+}
+
+/* Entry for unused_writes arrays. */
+struct write_entry {
+   /* If NULL indicates the entry is free to be reused. */
+   nir_intrinsic_instr *intrin;
+   uintptr_t mask;
+   nir_deref_path *path;
+};
+
+static void
+clear_unused_for_modes(struct util_dynarray *unused_writes, nir_variable_mode 
modes)
+{
+   util_dynarray_foreach(unused_writes, struct write_entry, entry) {
+  if (!entry->intrin)
+ continue;
+  nir_variable *var = entry->path->path[0]->var;
+  if (var->data.mode & modes)
+ entry->intrin = NULL;
+   }
+}
+
+static void
+clear_unused_for_src(struct util_dynarray *unused_writes, nir_deref_path 
*src_path)
+{
+   util_dynarray_foreach(unused_writes, struct write_entry, entry) {
+  if (!entry->intrin)
+ continue;
+  if (nir_compare_deref_paths(src_path, entry->path) & 
nir_derefs_may_alias_bit)
+ 

[Mesa-dev] [PATCH 8/9] freedreno/ir3: Use the new dead write vars pass

[Caio Marcelo de Oliveira Filho]

---
 src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c 
b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
index db1d74fdee7..d5f42f2a231 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
@@ -94,6 +94,7 @@ ir3_optimize_loop(nir_shader *s)
 
OPT_V(s, nir_lower_vars_to_ssa);
progress |= OPT(s, nir_opt_copy_prop_vars);
+   progress |= OPT(s, nir_opt_dead_write_vars);
progress |= OPT(s, nir_lower_alu_to_scalar);
progress |= OPT(s, nir_lower_phis_to_scalar);
 
-- 
2.18.0

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[Mesa-dev] [PATCH 9/9] nir: Remove handling of dead writes from copy_prop_vars

[Caio Marcelo de Oliveira Filho]

These are handled by a separate pass now.
---
 src/compiler/nir/nir_opt_copy_prop_vars.c | 67 +--
 1 file changed, 3 insertions(+), 64 deletions(-)

diff --git a/src/compiler/nir/nir_opt_copy_prop_vars.c 
b/src/compiler/nir/nir_opt_copy_prop_vars.c
index 9fecaf0eeec..b6a5b9c2bb4 100644
--- a/src/compiler/nir/nir_opt_copy_prop_vars.c
+++ b/src/compiler/nir/nir_opt_copy_prop_vars.c
@@ -38,10 +38,7 @@
  *  1) Copy-propagation on variables that have indirect access.  This includes
  * propagating from indirect stores into indirect loads.
  *
- *  2) Dead code elimination of store_var and copy_var intrinsics based on
- * killed destination values.
- *
- *  3) Removal of redundant load_deref intrinsics.  We can't trust regular CSE
+ *  2) Removal of redundant load_deref intrinsics.  We can't trust regular CSE
  * to do this because it isn't aware of variable writes that may alias the
  * value and make the former load invalid.
  *
@@ -51,6 +48,8 @@
  * rapidly get out of hand.  Fortunately, for anything that is only ever
  * accessed directly, we get SSA based copy-propagation which is extremely
  * powerful so this isn't that great a loss.
+ *
+ * Removal of dead writes to variables is handled by another pass.
  */
 
 struct value {
@@ -66,7 +65,6 @@ struct copy_entry {
 
nir_instr *store_instr[4];
 
-   unsigned comps_may_be_read;
struct value src;
 
nir_deref_instr *dst;
@@ -114,44 +112,6 @@ copy_entry_remove(struct copy_prop_var_state *state, 
struct copy_entry *entry)
list_add(>link, >copy_free_list);
 }
 
-static void
-remove_dead_writes(struct copy_prop_var_state *state,
-   struct copy_entry *entry, unsigned write_mask)
-{
-   /* We're overwriting another entry.  Some of it's components may not
-* have been read yet and, if that's the case, we may be able to delete
-* some instructions but we have to be careful.
-*/
-   unsigned dead_comps = write_mask & ~entry->comps_may_be_read;
-
-   for (unsigned mask = dead_comps; mask;) {
-  unsigned i = u_bit_scan();
-
-  nir_instr *instr = entry->store_instr[i];
-
-  /* We may have already deleted it on a previous iteration */
-  if (!instr)
- continue;
-
-  /* See if this instr is used anywhere that it's not dead */
-  bool keep = false;
-  for (unsigned j = 0; j < 4; j++) {
- if (entry->store_instr[j] == instr) {
-if (dead_comps & (1 << j)) {
-   entry->store_instr[j] = NULL;
-} else {
-   keep = true;
-}
- }
-  }
-
-  if (!keep) {
- nir_instr_remove(instr);
- state->progress = true;
-  }
-   }
-}
-
 static struct copy_entry *
 lookup_entry_for_deref(struct copy_prop_var_state *state,
nir_deref_instr *deref,
@@ -165,16 +125,6 @@ lookup_entry_for_deref(struct copy_prop_var_state *state,
return NULL;
 }
 
-static void
-mark_aliased_entries_as_read(struct copy_prop_var_state *state,
- nir_deref_instr *deref, unsigned components)
-{
-   list_for_each_entry(struct copy_entry, iter, >copies, link) {
-  if (nir_compare_derefs(iter->dst, deref) & nir_derefs_may_alias_bit)
- iter->comps_may_be_read |= components;
-   }
-}
-
 static struct copy_entry *
 get_entry_and_kill_aliases(struct copy_prop_var_state *state,
nir_deref_instr *deref,
@@ -191,11 +141,6 @@ get_entry_and_kill_aliases(struct copy_prop_var_state 
*state,
   }
 
   nir_deref_compare_result comp = nir_compare_derefs(iter->dst, deref);
-  /* This is a store operation.  If we completely overwrite some value, we
-   * want to delete any dead writes that may be present.
-   */
-  if (comp & nir_derefs_b_contains_a_bit)
- remove_dead_writes(state, iter, write_mask);
 
   if (comp & nir_derefs_equal_bit) {
  assert(entry == NULL);
@@ -231,7 +176,6 @@ store_to_entry(struct copy_prop_var_state *state, struct 
copy_entry *entry,
const struct value *value, unsigned write_mask,
nir_instr *store_instr)
 {
-   entry->comps_may_be_read &= ~write_mask;
if (value->is_ssa) {
   entry->src.is_ssa = true;
   /* Only overwrite the written components */
@@ -490,9 +434,6 @@ copy_prop_vars_block(struct copy_prop_var_state *state,
   case nir_intrinsic_load_deref: {
  nir_deref_instr *src = nir_src_as_deref(intrin->src[0]);
 
- uint8_t comps_read = nir_ssa_def_components_read(>dest.ssa);
- mark_aliased_entries_as_read(state, src, comps_read);
-
  struct copy_entry *src_entry =
 lookup_entry_for_deref(state, src, nir_derefs_a_contains_b_bit);
  struct value value;
@@ -579,8 +520,6 @@ copy_prop_vars_block(struct copy_prop_var_state *state,
 continue;
  }
 
- mark_aliased_entries_as_read(state, src, 0xf);
-
  struct copy_entry *src_entry =
   

[Mesa-dev] [PATCH 6/9] nir: Make dead_write_vars pass global

[Caio Marcelo de Oliveira Filho]

The pass will remove not only writes that are proven to be dead in
block, but also writes that can only be considered dead by looking at
multiple blocks.  Such global analysis is necessary to remove dead
writes such as the one marked below:

int total = gl_VertexIndex * 10;
float r = gl_VertexIndex;

for (int i = 0; i < total; i++) {
arr[i] = i; /* DEAD WRITE. */
if ((i % 2) == 0) {
arr[i] = i * 3.0;
} else {
arr[i] = i * 5.0;
}
r = arr[i];
}

out_color = vec4(r,r,r,r);

Without knowing that both sucessor blocks will overwrite the value,
it was not possible to remove the the "arr[i] = i" write.

The local pass was incremented with some extra data collected to allow
a iterative (backward) data-flow analysis to run.  The analysis is
used to find out, for each block, what derefs are used after the
block.  This information is then used to decide what unused writes in
the end of the block can be removed.  In a local-only analysis we
couldn't remove any, because they could be used later.
---
 src/compiler/nir/nir_opt_dead_write_vars.c | 546 -
 1 file changed, 532 insertions(+), 14 deletions(-)

diff --git a/src/compiler/nir/nir_opt_dead_write_vars.c 
b/src/compiler/nir/nir_opt_dead_write_vars.c
index 822bfa5595d..fe72ab784a8 100644
--- a/src/compiler/nir/nir_opt_dead_write_vars.c
+++ b/src/compiler/nir/nir_opt_dead_write_vars.c
@@ -27,6 +27,85 @@
 
 #include "util/u_dynarray.h"
 
+/**
+ * Elimination of dead writes based on derefs.
+ *
+ * Dead writes are stores and copies that write to a deref, which then gets
+ * another write before it was used (read or sourced for a copy).  Those
+ * writes can be removed since they don't affect anything.
+ *
+ * For derefs that refer to a memory area that can be read after the program,
+ * the last write is considered used.  The presence of certain instructions
+ * may also cause writes to be considered used, e.g. memory barrier (in this 
case
+ * the value must be written as other thread might use it).
+ *
+ * The write mask for store instructions is considered, so it is possible that
+ * a store is removed because of the combination of other stores overwritten
+ * its value.
+ *
+ * The pass works in three steps:
+ *
+ * (1) For each block, perform a local dead write removal.  Removing only
+ * writes we are sure are dead, so keeping around the last unused writes
+ * at the end of the block.  These last unused will be revisited in (3).
+ *
+ * (2) Perform a data-flow analysis to identify for each block the "uses
+ * before write" of successor blocks.  E.g. given the blocks below (block0
+ * precedes block1, that precedes block2)
+ *
+ *   block0:block1:block2:
+ * write Aload B load D
+ * write Bwrite Cload E
+ * write Cload C
+ * write Dwrite D
+ * write E
+ * load A
+ *
+ *the goal is know that B and E are "used before write" after block0; D
+ *and E are "used before write" after block1.  Note that usage of E
+ *doesn't come from an immediate succesor of block0.  The "used before
+ *written" information will decided later what unused writes are removed.
+ *
+ *The data-flow analysis is implemented by starting with per-block sets
+ *and iterate fixing the content in those sets.  The nature of the
+ *"fixing" ensures that the sets get stable (i.e. no infinite loops).
+ *Each block gets two sets representing its local information:
+ *
+ *- GEN: the derefs used before write by the block.  E.g. GEN(block1) = {B}
+ *- KILL: the derefs overwritten by the block.  E.g. KILL(block1) = {C, D}
+ *
+ *And two other sets representing its current state:
+ *
+ *- IN: the derefs used before write for this block and all successors.
+ *  E.g. at the end of the analysis, IN(block1) = {B, E}.  Note how E is
+ *  present but not D.
+ *- OUT: the derefs used before write for the successors of the block.
+ *
+ *In this pass the iteration happens "backwards", so a block uses the
+ *succesor information to improve its own information.  The IN and OUT
+ *sets are updated as follows:
+ *
+ *OUT = union IN of all successors
+ *IN  = GEN union (OUT minus KILL)
+ *
+ * 3) Remove the last unused writes for each block that are not used by
+ *successor blocks.  After the analysis in (2), this information is
+ *available in the OUT set of each block.
+ *
+ * One extra factor in play is that not trivial to decide whether two derefs
+ * are referring to the same storage or not.  Currently array indirects are
+ * assumed to alias with each other, i.e. "write A[i]" is considered used by a
+ * later "load A[j]".  This logic is mostly handled as part of
+ * nir_compare_deref_paths() function.  This prevents us from representing the

[Mesa-dev] [PATCH 7/9] intel/nir: Use the new dead write vars pass

[Caio Marcelo de Oliveira Filho]

---
 src/intel/compiler/brw_nir.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 31ffbe613ec..afc73e58c71 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -543,6 +543,7 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler 
*compiler,
   progress = false;
   OPT(nir_lower_vars_to_ssa);
   OPT(nir_opt_copy_prop_vars);
+  OPT(nir_opt_dead_write_vars);
 
   if (is_scalar) {
  OPT(nir_lower_alu_to_scalar);
-- 
2.18.0

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[Mesa-dev] [PATCH 1/9] util/dynarray: add a clone function

[Caio Marcelo de Oliveira Filho]

---
 src/util/u_dynarray.h | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/util/u_dynarray.h b/src/util/u_dynarray.h
index dcbbc06d161..4920fe04b67 100644
--- a/src/util/u_dynarray.h
+++ b/src/util/u_dynarray.h
@@ -102,6 +102,15 @@ util_dynarray_resize(struct util_dynarray *buf, unsigned 
newsize)
return p;
 }
 
+static inline void
+util_dynarray_clone(struct util_dynarray *buf, struct util_dynarray *mem_ctx,
+struct util_dynarray *from_buf)
+{
+   util_dynarray_init(buf, mem_ctx);
+   util_dynarray_resize(buf, from_buf->size);
+   memcpy(buf->data, from_buf->data, from_buf->size);
+}
+
 static inline void *
 util_dynarray_grow(struct util_dynarray *buf, int diff)
 {
-- 
2.18.0

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[Mesa-dev] [PATCH 3/9] nir: Skip common instructions when comparing deref paths

[Caio Marcelo de Oliveira Filho]

Deref paths may share the same deref instructions in their chains,
e.g.

ssa_100 = deref_var A
ssa_101 = deref_struct "array_field" of ssa_100
ssa_102 = deref_array "[1]" of ssa_101
ssa_103 = deref_struct "field_a" of ssa_102
ssa_104 = deref_struct "field_a" of ssa_103

when comparing the two last deref instructions, their paths will share
a common sequence ssa_100, ssa_101, ssa_102.  This patch skips to next
iteration if the deref instructions are the same.  Path[0] (the var)
is still handled specially, so in the case above, only ssa_101 and
ssa_102 will be skipped.
---
 src/compiler/nir/nir_deref.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/compiler/nir/nir_deref.c b/src/compiler/nir/nir_deref.c
index d013b423a8b..c8851688f9d 100644
--- a/src/compiler/nir/nir_deref.c
+++ b/src/compiler/nir/nir_deref.c
@@ -294,6 +294,9 @@ nir_compare_deref_paths(nir_deref_path *a_path,
   nir_deref_instr *a_tail = *(a_p++);
   nir_deref_instr *b_tail = *(b_p++);
 
+  if (a_tail == b_tail)
+ continue;
+
   switch (a_tail->deref_type) {
   case nir_deref_type_array:
   case nir_deref_type_array_wildcard: {
-- 
2.18.0

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[Mesa-dev] [PATCH 0/9] Global dead write vars removal pass

[Caio Marcelo de Oliveira Filho]

Our code currently only remove dead writes to vars for each block, but
doesn't tackle cases that involve multiple blocks.  This series will
add a pass that use an iterative data-flow analysis to cover those
cases.  Commit message for patch 6 has a detailed example.

I'm working on a subsequent series for adding global capabilities to
copy propagation.  While those optimizations can be done locally
together (as we currently do), the way we iterate the blocks for
data-flow analysis is different (dead write uses backward, copy
propagation uses forward), so it helps keeping them separate.

The motivation for this series (and the upcoming copy propagation)
work is to improve our generated code when we move other memory
accesses (e.g. SSBOs) to use derefs.

Patches 1-4 are small and are worth regardless the series -- I have
other series locally that use some of those.  So I intend to land them
earlier as they get reviewed.

Caio Marcelo de Oliveira Filho (9):
  util/dynarray: add a clone function
  nir: Export deref comparison functions
  nir: Skip common instructions when comparing deref paths
  nir: Give end_block its own index
  nir: Add a local dead write vars removal pass
  nir: Make dead_write_vars pass global
  intel/nir: Use the new dead write vars pass
  freedreno/ir3: Use the new dead write vars pass
  nir: Remove handling of dead writes from copy_prop_vars

 src/compiler/Makefile.sources   |   1 +
 src/compiler/nir/meson.build|   1 +
 src/compiler/nir/nir.c  |   2 +-
 src/compiler/nir/nir.h  |   2 +
 src/compiler/nir/nir_deref.c| 112 +++
 src/compiler/nir/nir_deref.h|  10 +
 src/compiler/nir/nir_opt_copy_prop_vars.c   | 208 +-
 src/compiler/nir/nir_opt_dead_write_vars.c  | 761 
 src/gallium/drivers/freedreno/ir3/ir3_nir.c |   1 +
 src/intel/compiler/brw_nir.c|   1 +
 src/util/u_dynarray.h   |   9 +
 11 files changed, 913 insertions(+), 195 deletions(-)
 create mode 100644 src/compiler/nir/nir_opt_dead_write_vars.c

-- 
2.18.0

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[Mesa-dev] [PATCH 2/9] nir: Export deref comparison functions

[Caio Marcelo de Oliveira Filho]

Reviewed-by: Timothy Arceri 
---
 src/compiler/nir/nir_deref.c  | 109 
 src/compiler/nir/nir_deref.h  |  10 ++
 src/compiler/nir/nir_opt_copy_prop_vars.c | 145 ++
 3 files changed, 132 insertions(+), 132 deletions(-)

diff --git a/src/compiler/nir/nir_deref.c b/src/compiler/nir/nir_deref.c
index c03acf83597..d013b423a8b 100644
--- a/src/compiler/nir/nir_deref.c
+++ b/src/compiler/nir/nir_deref.c
@@ -270,3 +270,112 @@ nir_fixup_deref_modes(nir_shader *shader)
   }
}
 }
+
+/** Returns true if the storage referrenced to by deref completely contains
+ * the storage referenced by sub.
+ */
+nir_deref_compare_result
+nir_compare_deref_paths(nir_deref_path *a_path,
+nir_deref_path *b_path)
+{
+   if (a_path->path[0]->var != b_path->path[0]->var)
+  return 0;
+
+   /* Start off assuming they fully compare.  We ignore equality for now.  In
+* the end, we'll determine that by containment.
+*/
+   nir_deref_compare_result result = nir_derefs_may_alias_bit |
+ nir_derefs_a_contains_b_bit |
+ nir_derefs_b_contains_a_bit;
+
+   nir_deref_instr **a_p = _path->path[1];
+   nir_deref_instr **b_p = _path->path[1];
+   while (*a_p != NULL && *b_p != NULL) {
+  nir_deref_instr *a_tail = *(a_p++);
+  nir_deref_instr *b_tail = *(b_p++);
+
+  switch (a_tail->deref_type) {
+  case nir_deref_type_array:
+  case nir_deref_type_array_wildcard: {
+ assert(b_tail->deref_type == nir_deref_type_array ||
+b_tail->deref_type == nir_deref_type_array_wildcard);
+
+ if (a_tail->deref_type == nir_deref_type_array_wildcard) {
+if (b_tail->deref_type != nir_deref_type_array_wildcard)
+   result &= ~nir_derefs_b_contains_a_bit;
+ } else if (b_tail->deref_type == nir_deref_type_array_wildcard) {
+if (a_tail->deref_type != nir_deref_type_array_wildcard)
+   result &= ~nir_derefs_a_contains_b_bit;
+ } else {
+assert(a_tail->deref_type == nir_deref_type_array &&
+   b_tail->deref_type == nir_deref_type_array);
+assert(a_tail->arr.index.is_ssa && b_tail->arr.index.is_ssa);
+
+nir_const_value *a_index_const =
+   nir_src_as_const_value(a_tail->arr.index);
+nir_const_value *b_index_const =
+   nir_src_as_const_value(b_tail->arr.index);
+if (a_index_const && b_index_const) {
+   /* If they're both direct and have different offsets, they
+* don't even alias much less anything else.
+*/
+   if (a_index_const->u32[0] != b_index_const->u32[0])
+  return 0;
+} else if (a_tail->arr.index.ssa == b_tail->arr.index.ssa) {
+   /* They're the same indirect, continue on */
+} else {
+   /* They're not the same index so we can't prove anything about
+* containment.
+*/
+   result &= ~(nir_derefs_a_contains_b_bit | 
nir_derefs_b_contains_a_bit);
+}
+ }
+ break;
+  }
+
+  case nir_deref_type_struct: {
+ /* If they're different struct members, they don't even alias */
+ if (a_tail->strct.index != b_tail->strct.index)
+return 0;
+ break;
+  }
+
+  default:
+ unreachable("Invalid deref type");
+  }
+   }
+
+   /* If a is longer than b, then it can't contain b */
+   if (*a_p != NULL)
+  result &= ~nir_derefs_a_contains_b_bit;
+   if (*b_p != NULL)
+  result &= ~nir_derefs_b_contains_a_bit;
+
+   /* If a contains b and b contains a they must be equal. */
+   if ((result & nir_derefs_a_contains_b_bit) && (result & 
nir_derefs_b_contains_a_bit))
+  result |= nir_derefs_equal_bit;
+
+   return result;
+}
+
+nir_deref_compare_result
+nir_compare_derefs(nir_deref_instr *a, nir_deref_instr *b)
+{
+   if (a == b) {
+  return nir_derefs_equal_bit | nir_derefs_may_alias_bit |
+ nir_derefs_a_contains_b_bit | nir_derefs_b_contains_a_bit;
+   }
+
+   nir_deref_path a_path, b_path;
+   nir_deref_path_init(_path, a, NULL);
+   nir_deref_path_init(_path, b, NULL);
+   assert(a_path.path[0]->deref_type == nir_deref_type_var);
+   assert(b_path.path[0]->deref_type == nir_deref_type_var);
+
+   nir_deref_compare_result result = nir_compare_deref_paths(_path, _path);
+
+   nir_deref_path_finish(_path);
+   nir_deref_path_finish(_path);
+
+   return result;
+}
diff --git a/src/compiler/nir/nir_deref.h b/src/compiler/nir/nir_deref.h
index 6f4141aaf82..c61c3f9366f 100644
--- a/src/compiler/nir/nir_deref.h
+++ b/src/compiler/nir/nir_deref.h
@@ -54,6 +54,16 @@ unsigned nir_deref_instr_get_const_offset(nir_deref_instr 
*deref,
 nir_ssa_def *nir_build_deref_offset(nir_builder *b, nir_deref_instr *deref,
   

[Mesa-dev] [Bug 107565] TypeError: __init__() got an unexpected keyword argument 'future_imports'

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107565

Dylan Baker  changed:

   What|Removed |Added

   Assignee|mesa-dev@lists.freedesktop. |baker.dyla...@gmail.com
   |org |

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[Mesa-dev] [Bug 107502] Newest libdrm is required by amdgpu, but drm_intel error is emitted

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107502

Dylan Baker  changed:

   What|Removed |Added

   Assignee|mesa-dev@lists.freedesktop. |baker.dyla...@gmail.com
   |org |
 CC||baker.dyla...@gmail.com

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[Mesa-dev] [Bug 107478] Regression: Mesa compile broken (snprintf) with Visual Studio 2013 (vs2013)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107478

Dylan Baker  changed:

   What|Removed |Added

   Assignee|mesa-dev@lists.freedesktop. |baker.dyla...@gmail.com
   |org |

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[Mesa-dev] [Bug 107478] Regression: Mesa compile broken (snprintf) with Visual Studio 2013 (vs2013)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107478

Dylan Baker  changed:

   What|Removed |Added

Version|unspecified |18.1
 CC||baker.dyla...@gmail.com

--- Comment #1 from Dylan Baker  ---
9d220fa950850d751fbbbc2cd4ec24d024fcad70 is in the 18.1.6 release. Can you test
again with 18.1.6 and confirm the issue is fixed?

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[Mesa-dev] [Bug 106411] Invalid gl_InstanceID value with combination of gl_DrawIDARB under OpenGL

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106411

Dylan Baker  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |WONTFIX

--- Comment #5 from Dylan Baker  ---
This bug cannot be reproduced on a supported version of mesa, closing.

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Re: [Mesa-dev] [Mesa-stable] [PATCH 1/8] radv: don't flush src stages when dstStageMask == BOTTOM_OF_PIPE

[Fredrik Höglund]

On Thursday 09 August 2018, Andres Gomez wrote:
> Fredrik, which is the status of this series? Several patches got R-b
> but nothing has landed so far. Are you in need of more reviews for the
> rest of the patches in the series?

The master branch has diverged quite a bit as a result of the
VK_KHR_create_renderpass2 support, so most of the patches
need to be reworked (and re-tested).

I hope to get to that in the next couple of days.

> On Tue, 2018-06-26 at 23:49 +0200, Fredrik Höglund wrote:
> > The Vulkan specification says:
> > 
> >"An execution dependency with only VK_PIPELINE_STAGE_BOTTOM_OF_-
> > PIPE_BIT in the destination stage mask [...] does not delay
> > processing of subsequent commands."
> > 
> > Cc: 
> > Signed-off-by: Fredrik Höglund 
> > ---
> >  src/amd/vulkan/radv_cmd_buffer.c | 3 ++-
> >  src/amd/vulkan/radv_pass.c   | 6 --
> >  2 files changed, 6 insertions(+), 3 deletions(-)
> > 
> > diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> > b/src/amd/vulkan/radv_cmd_buffer.c
> > index 110a9a960a9..5bfcba28d83 100644
> > --- a/src/amd/vulkan/radv_cmd_buffer.c
> > +++ b/src/amd/vulkan/radv_cmd_buffer.c
> > @@ -4197,7 +4197,8 @@ void radv_CmdPipelineBarrier(
> > image);
> > }
> >  
> > -   radv_stage_flush(cmd_buffer, srcStageMask);
> > +   if (destStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
> > +   radv_stage_flush(cmd_buffer, srcStageMask);
> > cmd_buffer->state.flush_bits |= src_flush_bits;
> >  
> > for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
> > diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c
> > index 15fee444cdc..7a0dca09496 100644
> > --- a/src/amd/vulkan/radv_pass.c
> > +++ b/src/amd/vulkan/radv_pass.c
> > @@ -174,11 +174,13 @@ VkResult radv_CreateRenderPass(
> > for (unsigned i = 0; i < pCreateInfo->dependencyCount; ++i) {
> > uint32_t dst = pCreateInfo->pDependencies[i].dstSubpass;
> > if (dst == VK_SUBPASS_EXTERNAL) {
> > -   pass->end_barrier.src_stage_mask = 
> > pCreateInfo->pDependencies[i].srcStageMask;
> > +   if (pCreateInfo->pDependencies[i].dstStageMask != 
> > VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
> > +   pass->end_barrier.src_stage_mask = 
> > pCreateInfo->pDependencies[i].srcStageMask;
> > pass->end_barrier.src_access_mask = 
> > pCreateInfo->pDependencies[i].srcAccessMask;
> > pass->end_barrier.dst_access_mask = 
> > pCreateInfo->pDependencies[i].dstAccessMask;
> > } else {
> > -   pass->subpasses[dst].start_barrier.src_stage_mask = 
> > pCreateInfo->pDependencies[i].srcStageMask;
> > +   if (pCreateInfo->pDependencies[i].dstStageMask != 
> > VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
> > +   
> > pass->subpasses[dst].start_barrier.src_stage_mask = 
> > pCreateInfo->pDependencies[i].srcStageMask;
> > pass->subpasses[dst].start_barrier.src_access_mask = 
> > pCreateInfo->pDependencies[i].srcAccessMask;
> > pass->subpasses[dst].start_barrier.dst_access_mask = 
> > pCreateInfo->pDependencies[i].dstAccessMask;
> > }
> 

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[Mesa-dev] [Bug 107313] Meson instructions on web site are non-optimal

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107313

Dylan Baker  changed:

   What|Removed |Added

   Assignee|mesa-dev@lists.freedesktop. |baker.dyla...@gmail.com
   |org |
 Status|NEW |ASSIGNED

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Re: [Mesa-dev] [PATCH 2/2] nir: Add a global dead write var removal pass

[Caio Marcelo de Oliveira Filho]

Disregard this patch. I'm sending a replacement for it.

For the record:

> The pass works by walking through the control flow nodes, and traverse
> the instructions keeping track of the write instructions whose
> destination were not overwritten by other instructions (called "live
> writes"). Reading from the destinations cause the writes to be marked
> as "used". If statements and loops are handled specially to take into
> account the different codepaths. The writes that are not "used" are
> removed.

(...)

> +   case nir_cf_node_loop: {
> +  nir_loop *loop = nir_cf_node_as_loop(cf_node);
> +
> +  /* For tracking used variables in a loop, there are three cases: (a) 
> the
> +   * body is not entered; (b) the body is executed once; (c) the body is
> +   * executed more than once.
> +   *
> +   * The case (c) is exemplified below:
> +   *
> +   * c = x
> +   * while condition
> +   * use(c)
> +   * c = y
> +   * c = z
> +   * use(c)
> +   *
> +   * All writes to c must be considered used.  This is achieved by
> +   * performing a second pass in the loop body, with the live write table
> +   * produced by a first pass on it.
> +   */
> +
> +  struct hash_table *loop_live_writes = 
> _mesa_hash_table_clone(live_writes, mem_ctx);
> +  for (int i = 0; i < 2; i++) {
> + foreach_list_typed_safe(nir_cf_node, cf_node, node, >body)
> +mark_used_writes_in_node(mem_ctx, loop_live_writes, cf_node);
> +  }

Doing two iterations here has a bad consequence: the number of times
we execute blocks will blows up, since if there's a loop inside the
loop, we'll execute each block in the inner loop 4 times, and so on.

I've tried other approaches to do this "following the CFG", but for
the case at hand (eliminate dead writes) all them ended up pointing
towards doing the analysis considering the block graph (preds/succs).
So that's what I've done in the new patch.


Thanks,
Caio



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[Mesa-dev] [Bug 107275] NIR segfaults after spirv-opt

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107275

Dylan Baker  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #4 from Dylan Baker  ---
The patch for this was merged, this should be fixed.

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[Mesa-dev] [PATCH v3] anv: add VK_EXT_sampler_filter_minmax support

[Yunchao He]

This extension can be supported on SKL+. With this patch,
all corresponding tests (6K+) in CTS can pass. No test fails.

I verified CTS with the command below:
deqp-vk --deqp-case=dEQP-VK.pipeline.sampler.view_type.*reduce*

v2: 1) support all depth formats, not depth-only formats, 2) fix
a wrong indention (Jason).

v3: fix a few nits (Lionel).
---
 src/intel/vulkan/anv_device.c  |  8 
 src/intel/vulkan/anv_extensions.py |  1 +
 src/intel/vulkan/anv_formats.c |  6 ++
 src/intel/vulkan/genX_state.c  | 26 ++
 4 files changed, 41 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 04fd6a829e..e45ba4b3af 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1116,6 +1116,14 @@ void anv_GetPhysicalDeviceProperties2(
  break;
   }
 
+  case 
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
+ VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
+(VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
+ properties->filterMinmaxImageComponentMapping = pdevice->info.gen >= 
9;
+ properties->filterMinmaxSingleComponentFormats = true;
+ break;
+  }
+
   case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
  VkPhysicalDeviceSubgroupProperties *properties = (void *)ext;
 
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index ea837744b4..e165bd371d 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -125,6 +125,7 @@ EXTENSIONS = [
 Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen 
>= 9'),
 Extension('VK_EXT_vertex_attribute_divisor',  2, True),
 Extension('VK_EXT_post_depth_coverage',   1, 'device->info.gen 
>= 9'),
+Extension('VK_EXT_sampler_filter_minmax', 1, 'device->info.gen 
>= 9'),
 ]
 
 class VkVersion:
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 815b320a82..33faf7cc37 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -489,6 +489,9 @@ get_image_format_features(const struct gen_device_info 
*devinfo,
   if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT || devinfo->gen >= 8)
  flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
 
+  if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
   flags |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
VK_FORMAT_FEATURE_BLIT_DST_BIT |
VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
@@ -521,6 +524,9 @@ get_image_format_features(const struct gen_device_info 
*devinfo,
if (isl_format_supports_sampling(devinfo, plane_format.isl_format)) {
   flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
 
+  if (devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
   if (isl_format_supports_filtering(devinfo, plane_format.isl_format))
  flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
}
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index b1014d9e79..f075272acd 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -245,6 +245,14 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = {
[VK_COMPARE_OP_ALWAYS]   = PREFILTEROPNEVER,
 };
 
+#if GEN_GEN >= 9
+static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
+   [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
+   [VK_SAMPLER_REDUCTION_MODE_MIN_EXT]  = MINIMUM,
+   [VK_SAMPLER_REDUCTION_MODE_MAX_EXT]  = MAXIMUM,
+};
+#endif
+
 VkResult genX(CreateSampler)(
 VkDevice_device,
 const VkSamplerCreateInfo*  pCreateInfo,
@@ -266,6 +274,10 @@ VkResult genX(CreateSampler)(
uint32_t border_color_offset = device->border_colors.offset +
   pCreateInfo->borderColor * 64;
 
+#if GEN_GEN >= 9
+   unsigned sampler_reduction_mode = STD_FILTER;
+#endif
+
vk_foreach_struct(ext, pCreateInfo->pNext) {
   switch (ext->sType) {
   case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
@@ -281,6 +293,15 @@ VkResult genX(CreateSampler)(
  sampler->conversion = conversion;
  break;
   }
+#if GEN_GEN >= 9
+  case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
+ struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
+(struct VkSamplerReductionModeCreateInfoEXT *) ext;
+ sampler_reduction_mode =
+vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode];
+ break;
+  }
+#endif
   default:
  anv_debug_ignored_stype(ext->sType);
  break;
@@ -348,6 +369,11 @@ VkResult 

[Mesa-dev] [Bug 106976] Compilation failure due to missing xcb_randr_lease_t

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106976

Dylan Baker  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #4 from Dylan Baker  ---
I'm marking this as fixed, please re-open if that is incorrect.

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[Mesa-dev] [PATCH] intel/eu: print bytes instead of 32 bit hex value

[Sagar Ghuge]

INTEL_DEBUG=hex prints 32 bit hex value
and due to endianness of CPU byte order is
reversed. In order to disassemble binary
files, print each byte instead of 32 bit hex
value.

Signed-off-by: Sagar Ghuge 
---
 src/intel/compiler/brw_eu.c | 24 
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index 6ef0a6a577..223e561dff 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -365,9 +365,14 @@ brw_disassemble(const struct gen_device_info *devinfo,
   if (compacted) {
  brw_compact_inst *compacted = (void *)insn;
 if (dump_hex) {
-   fprintf(out, "0x%08x 0x%08x   ",
-   ((uint32_t *)insn)[1],
-   ((uint32_t *)insn)[0]);
+   unsigned char * insn_ptr = ((unsigned char *)[0]);
+   for (int i = 0 ; i < 8; i = i + 4) {
+  fprintf(out, "%02x %02x %02x %02x ",
+  insn_ptr[i],
+  insn_ptr[i + 1],
+  insn_ptr[i + 2],
+  insn_ptr[i + 3]);
+   }
 }
 
 brw_uncompact_instruction(devinfo, , compacted);
@@ -375,11 +380,14 @@ brw_disassemble(const struct gen_device_info *devinfo,
 offset += 8;
   } else {
 if (dump_hex) {
-   fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
-   ((uint32_t *)insn)[3],
-   ((uint32_t *)insn)[2],
-   ((uint32_t *)insn)[1],
-   ((uint32_t *)insn)[0]);
+   unsigned char * insn_ptr = ((unsigned char *)[0]);
+   for (int i = 0 ; i < 16; i = i + 4) {
+  fprintf(out, "%02x %02x %02x %02x ",
+  insn_ptr[i],
+  insn_ptr[i + 1],
+  insn_ptr[i + 2],
+  insn_ptr[i + 3]);
+   }
 }
 offset += 16;
   }
-- 
2.17.1

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[Mesa-dev] [Bug 106955] Mesa 18.1.2 not tagged in git

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106955

Dylan Baker  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |INVALID

--- Comment #2 from Dylan Baker  ---
Tag is definitely there. Closing

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[Mesa-dev] [PATCH] meson: fix build for egl platform_x11

[Alexander Tsoy]

platform_x11 needs inc_loader:

../mesa-18.2.0-rc2/src/egl/drivers/dri2/platform_x11.c:48:10: fatal
error: loader.h: No such file or directory
 #include "loader.h"
  ^~
---
 src/egl/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/egl/meson.build b/src/egl/meson.build
index 1d63f0f087..c7c22d3637 100644
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -99,10 +99,10 @@ endif
 
 if with_platform_x11
   files_egl += files('drivers/dri2/platform_x11.c')
+  incs_for_egl += inc_loader
   if with_dri3
 files_egl += files('drivers/dri2/platform_x11_dri3.c')
 link_for_egl += libloader_dri3_helper
-incs_for_egl += inc_loader
   endif
   deps_for_egl += [dep_x11_xcb, dep_xcb_dri2, dep_xcb_xfixes]
 endif
-- 
2.16.4

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Re: [Mesa-dev] [PATCH v2 5/5] scons: Check for mako 0.8.0

[Jose Fonseca]

On 15/08/18 17:18, Dylan Baker wrote:

v2: - Use distutils to do the version checking

Bugzilla: 
https://na01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugs.freedesktop.org%2Fshow_bug.cgi%3Fid%3D107565data=02%7C01%7Cjfonseca%40vmware.com%7C49a58211ac9747678b9608d602cad13d%7Cb39138ca3cee4b4aa4d6cd83d9dd62f0%7C1%7C0%7C636699467450929937sdata=iPzSf8AUDqDbXxxrjmkwenq%2F4805Abd4axrr5cV%2Bkdg%3Dreserved=0
---
  scons/gallium.py | 13 +
  1 file changed, 13 insertions(+)

diff --git a/scons/gallium.py b/scons/gallium.py
index 659da72c1c3..aa7201a9715 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -29,6 +29,7 @@ Frontend-tool for Gallium3D architecture.
  # SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  #
  
+from __future__ import print_function
  
  import distutils.version

  import os
@@ -677,6 +678,18 @@ def generate(env):
  env.PkgCheckModules('XF86VIDMODE', ['xxf86vm'])
  env.PkgCheckModules('DRM', ['libdrm >= 2.4.75'])
  
+if not os.path.exists("src/util/format_srgb.c"):

+print("Checking for Python Mako module (>= 0.8.0)... ", end='')
+try:
+import mako
+except ImportError:
+print("no")
+exit(1)
+if distutils.version.StrictVersion(mako.__version__) < 
distutils.version.StrictVersion('0.8.0'):
+print("no")
+exit(1)
+print("yes")
+
  if env['x11']:
  env.Append(CPPPATH = env['X11_CPPPATH'])
  



Series looks good to me.

Reviewed-by: Jose Fonseca 

Jose
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[Mesa-dev] [Bug 83785] Shader branches excluded by uniform values are not optimized out

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=83785

Dylan Baker  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |NOTABUG

--- Comment #4 from Dylan Baker  ---
This doesn't seem like a real bug, just a lack of optimization. I'm gong to
close this. Feel free to re-open if you disagree.

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[Mesa-dev] [Bug 103078] MATLAB broken with mesa software rendering

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103078

Dylan Baker  changed:

   What|Removed |Added

 Resolution|--- |NOTOURBUG
 Status|NEW |RESOLVED

--- Comment #15 from Dylan Baker  ---
It sounds like this was actually a jogl bug, thus not our bug. Please re-open
if I've misunderstood.

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Re: [Mesa-dev] [PATCH v2] anv: add VK_EXT_sampler_filter_minmax support

[Jason Ekstrand]

On August 15, 2018 14:43:08 Lionel Landwerlin 
 wrote:



Hey there,

Just a few nits below.

Thanks!

-
Lionel

On 15/08/18 18:42, Yunchao He wrote:

This extension can be supported on SKL+. With this patch,
all corresponding tests (6K+) in CTS can pass. No test fails.

I verified CTS with the command below:
deqp-vk --deqp-case=dEQP-VK.pipeline.sampler.view_type.*reduce*

v2: 1) support all depth formats, not depth-only formats, 2) fix
a wrong indention (Jason).
---
src/intel/vulkan/anv_device.c  |  8 
src/intel/vulkan/anv_extensions.py |  1 +
src/intel/vulkan/anv_formats.c |  6 ++
src/intel/vulkan/genX_state.c  | 27 +++
4 files changed, 42 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 04fd6a829e..e45ba4b3af 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1116,6 +1116,14 @@ void anv_GetPhysicalDeviceProperties2(
  break;
}

+  case 
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {

+ VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
+(VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
+ properties->filterMinmaxImageComponentMapping = pdevice->info.gen 
>= 9;


I guess you can turn pdevice->info.gen >= 9 into true since the
extension is only available on Gen9.


I think I'd rather keep it. That way, if someone blindly queries, they get 
there right value.  Also, if it ever becomes core (not that likely), we 
already do the right thing on the query.





+ properties->filterMinmaxSingleComponentFormats = true;
+ break;
+  }
+
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
  VkPhysicalDeviceSubgroupProperties *properties = (void *)ext;

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py

index ea837744b4..e165bd371d 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -125,6 +125,7 @@ EXTENSIONS = [
Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen 
>= 9'),

Extension('VK_EXT_vertex_attribute_divisor',  2, True),
Extension('VK_EXT_post_depth_coverage',   1, 'device->info.gen 
>= 9'),
+Extension('VK_EXT_sampler_filter_minmax', 1, 
'device->info.gen >= 9'),

]

class VkVersion:
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 815b320a82..33faf7cc37 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -489,6 +489,9 @@ get_image_format_features(const struct gen_device_info 
*devinfo,

if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT || devinfo->gen >= 8)
  flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;

+  if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
flags |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
VK_FORMAT_FEATURE_BLIT_DST_BIT |
VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
@@ -521,6 +524,9 @@ get_image_format_features(const struct gen_device_info 
*devinfo,

if (isl_format_supports_sampling(devinfo, plane_format.isl_format)) {
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;

+  if (devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
if (isl_format_supports_filtering(devinfo, plane_format.isl_format))
  flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
}
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index b1014d9e79..e095cb4cc0 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -245,6 +245,14 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = {
[VK_COMPARE_OP_ALWAYS]   = PREFILTEROPNEVER,
};

+#if GEN_GEN >= 9
+static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
+   [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
+   [VK_SAMPLER_REDUCTION_MODE_MIN_EXT]  = MINIMUM,
+   [VK_SAMPLER_REDUCTION_MODE_MAX_EXT]  = MAXIMUM,
+};
+#endif
+
VkResult genX(CreateSampler)(
VkDevice_device,
const VkSamplerCreateInfo*  pCreateInfo,
@@ -266,6 +274,10 @@ VkResult genX(CreateSampler)(
uint32_t border_color_offset = device->border_colors.offset +
   pCreateInfo->borderColor * 64;

+#if GEN_GEN >= 9
+   unsigned sampler_reduction_mode = STD_FILTER;
+#endif
+
vk_foreach_struct(ext, pCreateInfo->pNext) {
switch (ext->sType) {
case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
@@ -281,6 +293,16 @@ VkResult genX(CreateSampler)(
  sampler->conversion = conversion;
  break;
}
+#if GEN_GEN >= 9
+  case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
+   struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
+  (struct VkSamplerReductionModeCreateInfoEXT *) ext;


You can drop that if below. If you've 

Re: [Mesa-dev] [PATCH] mesa/st: fix array indices off-by-one error in remapping

[Dave Airlie]

Reviewed-by: Dave Airlie 
On Thu, 16 Aug 2018 at 03:31, Gert Wollny  wrote:
>
> When moving the array sizes from the old list to the new one it was
> not taken into account that the array indices start with one, but the
> array_size array started at index zero, which resulted in incorrect array
> sizes when arrays were merged. Correct this by copying the array_size
> values of the retained arrays with an offset of -1.
>
> Also fix whitespaces for the replaced lines.
>
> Fixes: d8c2119f9b0b257a23ceb398f6d0d78da916417e
>   mesa/st/glsl_to_tgsi: Expose array live range tracking and merging
> Signed-off-by: Gert Wollny 
> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp |  2 +-
>  src/mesa/state_tracker/st_glsl_to_tgsi_array_merge.cpp | 10 +-
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 2b9183abbb..bbb28b0d7b 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -5601,7 +5601,7 @@ glsl_to_tgsi_visitor::merge_registers(void)
> if (this->next_array > 0) {
>arr_live_ranges = new array_live_range[this->next_array];
>for (unsigned i = 0; i < this->next_array; ++i)
> -arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i+1]);
> + arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i]);
> }
>
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi_array_merge.cpp 
> b/src/mesa/state_tracker/st_glsl_to_tgsi_array_merge.cpp
> index f95b1fac7b..1431824369 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi_array_merge.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi_array_merge.cpp
> @@ -587,10 +587,10 @@ int remap_arrays(int narrays, unsigned *array_sizes,
> /* re-calculate arrays */
>  #if __cplusplus < 201402L
> int *idx_map = new int[narrays + 1];
> -   unsigned *old_sizes = new unsigned[narrays + 1];
> +   unsigned *old_sizes = new unsigned[narrays];
>  #else
> unique_ptr idx_map = make_unique(narrays + 1);
> -   unique_ptr old_sizes = make_unique(narrays + 1);
> +   unique_ptr old_sizes = make_unique(narrays);
>  #endif
>
> memcpy(_sizes[0], _sizes[0], sizeof(unsigned) * narrays);
> @@ -599,9 +599,9 @@ int remap_arrays(int narrays, unsigned *array_sizes,
> int new_narrays = 0;
> for (int i = 1; i <= narrays; ++i) {
>if (!map[i].is_valid()) {
> -++new_narrays;
> -idx_map[i] = new_narrays;
> -array_sizes[new_narrays] = old_sizes[i];
> + ++new_narrays;
> + array_sizes[new_narrays-1] = old_sizes[i-1];
> + idx_map[i] = new_narrays;
>}
> }
>
> --
> 2.16.4
>
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[Mesa-dev] [Bug 107457] [Tracker] Mesa 18.2 release tracker

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107457

Mark Janes  changed:

   What|Removed |Added

 Depends on||107359


Referenced Bugs:

https://bugs.freedesktop.org/show_bug.cgi?id=107359
[Bug 107359] [Regression] [bisected] [OpenGL CTS] [SKL,BDW]
KHR-GL46.texture_barrier*-texels,
GTF-GL46.gtf21.GL2FixedTests.buffer_corners.buffer_corners, and
GTF-GL46.gtf21.GL2FixedTests.stencil_plane_corners.stencil_plane_corners fail
with some configuration
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Re: [Mesa-dev] [PATCH v2] anv: add VK_EXT_sampler_filter_minmax support

[Lionel Landwerlin]

Hey there,

Just a few nits below.

Thanks!

-
Lionel

On 15/08/18 18:42, Yunchao He wrote:

This extension can be supported on SKL+. With this patch,
all corresponding tests (6K+) in CTS can pass. No test fails.

I verified CTS with the command below:
deqp-vk --deqp-case=dEQP-VK.pipeline.sampler.view_type.*reduce*

v2: 1) support all depth formats, not depth-only formats, 2) fix
a wrong indention (Jason).
---
  src/intel/vulkan/anv_device.c  |  8 
  src/intel/vulkan/anv_extensions.py |  1 +
  src/intel/vulkan/anv_formats.c |  6 ++
  src/intel/vulkan/genX_state.c  | 27 +++
  4 files changed, 42 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 04fd6a829e..e45ba4b3af 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1116,6 +1116,14 @@ void anv_GetPhysicalDeviceProperties2(
   break;
}
  
+  case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {

+ VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
+(VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
+ properties->filterMinmaxImageComponentMapping = pdevice->info.gen >= 
9;


I guess you can turn pdevice->info.gen >= 9 into true since the 
extension is only available on Gen9.



+ properties->filterMinmaxSingleComponentFormats = true;
+ break;
+  }
+
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
   VkPhysicalDeviceSubgroupProperties *properties = (void *)ext;
  
diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py

index ea837744b4..e165bd371d 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -125,6 +125,7 @@ EXTENSIONS = [
  Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen 
>= 9'),
  Extension('VK_EXT_vertex_attribute_divisor',  2, True),
  Extension('VK_EXT_post_depth_coverage',   1, 'device->info.gen 
>= 9'),
+Extension('VK_EXT_sampler_filter_minmax', 1, 'device->info.gen 
>= 9'),
  ]
  
  class VkVersion:

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 815b320a82..33faf7cc37 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -489,6 +489,9 @@ get_image_format_features(const struct gen_device_info 
*devinfo,
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT || devinfo->gen >= 8)
   flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
  
+  if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && devinfo->gen >= 9)

+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
flags |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
 VK_FORMAT_FEATURE_BLIT_DST_BIT |
 VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
@@ -521,6 +524,9 @@ get_image_format_features(const struct gen_device_info 
*devinfo,
 if (isl_format_supports_sampling(devinfo, plane_format.isl_format)) {
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
  
+  if (devinfo->gen >= 9)

+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
if (isl_format_supports_filtering(devinfo, plane_format.isl_format))
   flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
 }
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index b1014d9e79..e095cb4cc0 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -245,6 +245,14 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = {
 [VK_COMPARE_OP_ALWAYS]   = PREFILTEROPNEVER,
  };
  
+#if GEN_GEN >= 9

+static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
+   [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
+   [VK_SAMPLER_REDUCTION_MODE_MIN_EXT]  = MINIMUM,
+   [VK_SAMPLER_REDUCTION_MODE_MAX_EXT]  = MAXIMUM,
+};
+#endif
+
  VkResult genX(CreateSampler)(
  VkDevice_device,
  const VkSamplerCreateInfo*  pCreateInfo,
@@ -266,6 +274,10 @@ VkResult genX(CreateSampler)(
 uint32_t border_color_offset = device->border_colors.offset +
pCreateInfo->borderColor * 64;
  
+#if GEN_GEN >= 9

+   unsigned sampler_reduction_mode = STD_FILTER;
+#endif
+
 vk_foreach_struct(ext, pCreateInfo->pNext) {
switch (ext->sType) {
case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
@@ -281,6 +293,16 @@ VkResult genX(CreateSampler)(
   sampler->conversion = conversion;
   break;
}
+#if GEN_GEN >= 9
+  case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
+struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
+   (struct VkSamplerReductionModeCreateInfoEXT *) ext;


You can drop that if below. If you've reach this 

[Mesa-dev] [Bug 107563] [RADV] Broken rendering in Unity demos

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107563

--- Comment #6 from Alexander Tsoy  ---
Not sure if I did it right:
https://www.dropbox.com/s/glc70mfzirow9c5/CorridorLightingExample.rdc.xz?dl=0

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Re: [Mesa-dev] [PATCH 3/8] mesa: expose AMD_multi_draw_indirect

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 08/08/2018 07:12 PM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> because the closed driver exposes it.
> This is equivalent to the ARB extension.
> ---
>  docs/relnotes/18.3.0.html|  1 +
>  src/mapi/glapi/gen/ARB_draw_indirect.xml | 20 
>  src/mesa/main/extensions_table.h |  1 +
>  3 files changed, 22 insertions(+)
> 
> diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
> index 840a336d41a..cf3bb80ceae 100644
> --- a/docs/relnotes/18.3.0.html
> +++ b/docs/relnotes/18.3.0.html
> @@ -46,20 +46,21 @@ TBD.
>  
>  New features
>  
>  
>  Note: some of the new features are only available with certain drivers.
>  
>  
>  
>  GL_AMD_framebuffer_multisample_advanced on radeonsi.
>  GL_AMD_gpu_shader_int64 on i965, nvc0, radeonsi.
> +GL_AMD_multi_draw_indirect on all GL 4.x drivers.
>  GL_EXT_window_rectangles on radeonsi.
>  
>  
>  Bug fixes
>  
>  
>  TBD
>  
>  
>  Changes
> diff --git a/src/mapi/glapi/gen/ARB_draw_indirect.xml 
> b/src/mapi/glapi/gen/ARB_draw_indirect.xml
> index 3b29d6b8674..b4399f1e8b6 100644
> --- a/src/mapi/glapi/gen/ARB_draw_indirect.xml
> +++ b/src/mapi/glapi/gen/ARB_draw_indirect.xml
> @@ -35,11 +35,31 @@
>  
>  
>  
>  
>  
>  
>  
>  
>  
>  
> +
> +
> + alias="MultiDrawArraysIndirect">
> +
> +
> +
> +
> +
> +
> + alias="MultiDrawElementsIndirect">
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
>  
> diff --git a/src/mesa/main/extensions_table.h 
> b/src/mesa/main/extensions_table.h
> index 326fa6dc473..cc996d5d254 100644
> --- a/src/mesa/main/extensions_table.h
> +++ b/src/mesa/main/extensions_table.h
> @@ -5,20 +5,21 @@
>  #define ES1 0
>  #define ES2 0
>  #define  x ~0
>  
>  EXT(3DFX_texture_compression_FXT1   , TDFX_texture_compression_FXT1  
> , GLL, GLC,  x ,  x , 1999)
>  
>  EXT(AMD_conservative_depth  , ARB_conservative_depth 
> , GLL, GLC,  x ,  x , 2009)
>  EXT(AMD_draw_buffers_blend  , ARB_draw_buffers_blend 
> , GLL, GLC,  x ,  x , 2009)
>  EXT(AMD_framebuffer_multisample_advanced, 
> AMD_framebuffer_multisample_advanced   , GLL, GLC,  x , ES2, 2018)
>  EXT(AMD_gpu_shader_int64, ARB_gpu_shader_int64   
> ,  x , GLC,  x ,  x , 2015)
> +EXT(AMD_multi_draw_indirect , ARB_draw_indirect  
> , GLL, GLC,  x ,  x , 2011)
>  EXT(AMD_performance_monitor , AMD_performance_monitor
> , GLL, GLC,  x , ES2, 2007)
>  EXT(AMD_pinned_memory   , AMD_pinned_memory  
> , GLL, GLC,  x ,  x , 2013)
>  EXT(AMD_seamless_cubemap_per_texture, 
> AMD_seamless_cubemap_per_texture   , GLL, GLC,  x ,  x , 2009)
>  EXT(AMD_shader_stencil_export   , ARB_shader_stencil_export  
> , GLL, GLC,  x ,  x , 2009)
>  EXT(AMD_shader_trinary_minmax   , dummy_true 
> , GLL, GLC,  x ,  x , 2012)
>  EXT(AMD_vertex_shader_layer , AMD_vertex_shader_layer
> , GLL, GLC,  x ,  x , 2012)
>  EXT(AMD_vertex_shader_viewport_index, 
> AMD_vertex_shader_viewport_index   , GLL, GLC,  x ,  x , 2012)
>  
>  EXT(ANDROID_extension_pack_es31a, ANDROID_extension_pack_es31a   
> ,  x ,  x ,  x ,  31, 2014)
>  
> 

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Re: [Mesa-dev] [PATCH 4/8] mesa: expose AMD_query_buffer_object

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 08/08/2018 07:12 PM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> it's a subset of the ARB extension.
> ---
>  docs/relnotes/18.3.0.html| 1 +
>  src/mesa/main/extensions_table.h | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
> index cf3bb80ceae..c0132311a25 100644
> --- a/docs/relnotes/18.3.0.html
> +++ b/docs/relnotes/18.3.0.html
> @@ -47,20 +47,21 @@ TBD.
>  New features
>  
>  
>  Note: some of the new features are only available with certain drivers.
>  
>  
>  
>  GL_AMD_framebuffer_multisample_advanced on radeonsi.
>  GL_AMD_gpu_shader_int64 on i965, nvc0, radeonsi.
>  GL_AMD_multi_draw_indirect on all GL 4.x drivers.
> +GL_AMD_query_buffer_object on i965, nvc0, r600, radeonsi.
>  GL_EXT_window_rectangles on radeonsi.
>  
>  
>  Bug fixes
>  
>  
>  TBD
>  
>  
>  Changes
> diff --git a/src/mesa/main/extensions_table.h 
> b/src/mesa/main/extensions_table.h
> index cc996d5d254..34d7fa96bae 100644
> --- a/src/mesa/main/extensions_table.h
> +++ b/src/mesa/main/extensions_table.h
> @@ -8,20 +8,21 @@
>  
>  EXT(3DFX_texture_compression_FXT1   , TDFX_texture_compression_FXT1  
> , GLL, GLC,  x ,  x , 1999)
>  
>  EXT(AMD_conservative_depth  , ARB_conservative_depth 
> , GLL, GLC,  x ,  x , 2009)
>  EXT(AMD_draw_buffers_blend  , ARB_draw_buffers_blend 
> , GLL, GLC,  x ,  x , 2009)
>  EXT(AMD_framebuffer_multisample_advanced, 
> AMD_framebuffer_multisample_advanced   , GLL, GLC,  x , ES2, 2018)
>  EXT(AMD_gpu_shader_int64, ARB_gpu_shader_int64   
> ,  x , GLC,  x ,  x , 2015)
>  EXT(AMD_multi_draw_indirect , ARB_draw_indirect  
> , GLL, GLC,  x ,  x , 2011)
>  EXT(AMD_performance_monitor , AMD_performance_monitor
> , GLL, GLC,  x , ES2, 2007)
>  EXT(AMD_pinned_memory   , AMD_pinned_memory  
> , GLL, GLC,  x ,  x , 2013)
> +EXT(AMD_query_buffer_object , ARB_query_buffer_object
> , GLL, GLC,  x ,  x , 2012)
>  EXT(AMD_seamless_cubemap_per_texture, 
> AMD_seamless_cubemap_per_texture   , GLL, GLC,  x ,  x , 2009)
>  EXT(AMD_shader_stencil_export   , ARB_shader_stencil_export  
> , GLL, GLC,  x ,  x , 2009)
>  EXT(AMD_shader_trinary_minmax   , dummy_true 
> , GLL, GLC,  x ,  x , 2012)
>  EXT(AMD_vertex_shader_layer , AMD_vertex_shader_layer
> , GLL, GLC,  x ,  x , 2012)
>  EXT(AMD_vertex_shader_viewport_index, 
> AMD_vertex_shader_viewport_index   , GLL, GLC,  x ,  x , 2012)
>  
>  EXT(ANDROID_extension_pack_es31a, ANDROID_extension_pack_es31a   
> ,  x ,  x ,  x ,  31, 2014)
>  
>  EXT(ANGLE_texture_compression_dxt3  , ANGLE_texture_compression_dxt  
> , GLL, GLC, ES1, ES2, 2011)
>  EXT(ANGLE_texture_compression_dxt5  , ANGLE_texture_compression_dxt  
> , GLL, GLC, ES1, ES2, 2011)
> 

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Re: [Mesa-dev] [PATCH 5/8] mesa: expose AMD_texture_texture4

[Ian Romanick]

On 08/08/2018 07:12 PM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> because the closed driver exposes it.

Aside from AMD_texture_texture4 being really, really under-specified,
there is one big difference between the two extensions.

7)  Can both texture *AND* texture4 built-in functions
sample from the same sampler in a shader?

No.

vs.

(5) Can both texture *AND* textureGather built-in functions
sample from the same sampler in a shader?

   RESOLVED: Yes.

Of course, the AMD_texture_texture4 spec doesn't say what "no" means.
Compile error?  Garbage results?  A kitten dies?  Zero guidance from the
spec.  We should imitate whatever the closed driver does... unless a
kitten dies.  Don't do that.

> ---
>  docs/relnotes/18.3.0.html|  1 +
>  src/compiler/glsl/builtin_functions.cpp  | 10 ++
>  src/compiler/glsl/glsl_parser_extras.cpp |  1 +
>  src/compiler/glsl/glsl_parser_extras.h   |  2 ++
>  src/mesa/main/extensions_table.h |  1 +
>  5 files changed, 15 insertions(+)
> 
> diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
> index c0132311a25..8b067b55d3c 100644
> --- a/docs/relnotes/18.3.0.html
> +++ b/docs/relnotes/18.3.0.html
> @@ -48,20 +48,21 @@ TBD.
>  
>  
>  Note: some of the new features are only available with certain drivers.
>  
>  
>  
>  GL_AMD_framebuffer_multisample_advanced on radeonsi.
>  GL_AMD_gpu_shader_int64 on i965, nvc0, radeonsi.
>  GL_AMD_multi_draw_indirect on all GL 4.x drivers.
>  GL_AMD_query_buffer_object on i965, nvc0, r600, radeonsi.
> +GL_AMD_texture_texture4 on i965, nvc0, r600, radeonsi.
>  GL_EXT_window_rectangles on radeonsi.
>  
>  
>  Bug fixes
>  
>  
>  TBD
>  
>  
>  Changes
> diff --git a/src/compiler/glsl/builtin_functions.cpp 
> b/src/compiler/glsl/builtin_functions.cpp
> index e37d96c4636..c778b65c6cd 100644
> --- a/src/compiler/glsl/builtin_functions.cpp
> +++ b/src/compiler/glsl/builtin_functions.cpp
> @@ -411,20 +411,26 @@ texture_query_lod(const _mesa_glsl_parse_state *state)
>  static bool
>  texture_gather_cube_map_array(const _mesa_glsl_parse_state *state)
>  {
> return state->is_version(400, 320) ||
>state->ARB_texture_gather_enable ||
>state->ARB_gpu_shader5_enable ||
>state->EXT_texture_cube_map_array_enable ||
>state->OES_texture_cube_map_array_enable;
>  }
>  
> +static bool
> +texture_texture4(const _mesa_glsl_parse_state *state)
> +{
> +   return state->AMD_texture_texture4_enable;
> +}
> +
>  static bool
>  texture_gather_or_es31(const _mesa_glsl_parse_state *state)
>  {
> return state->is_version(400, 310) ||
>state->ARB_texture_gather_enable ||
>state->ARB_gpu_shader5_enable;
>  }
>  
>  /* Only ARB_texture_gather but not GLSL 4.0 or ARB_gpu_shader5.
>   * used for relaxation of const offset requirements.
> @@ -2824,20 +2830,24 @@ builtin_builder::create_builtins()
>  NULL);
>  
> add_function("shadow2DRectGradARB",
>  _texture(ir_txd, shader_texture_lod_and_rect, 
> glsl_type::vec4_type,  glsl_type::sampler2DRectShadow_type, 
> glsl_type::vec3_type),
>  NULL);
>  
> add_function("shadow2DRectProjGradARB",
>  _texture(ir_txd, shader_texture_lod_and_rect, 
> glsl_type::vec4_type,  glsl_type::sampler2DRectShadow_type, 
> glsl_type::vec4_type, TEX_PROJECT),
>  NULL);
>  
> +   add_function("texture4",
> +_texture(ir_tg4, texture_texture4, glsl_type::vec4_type, 
> glsl_type::sampler2D_type, glsl_type::vec2_type),
> +NULL);
> +
> add_function("textureGather",
>  _texture(ir_tg4, texture_gather_or_es31, 
> glsl_type::vec4_type, glsl_type::sampler2D_type, glsl_type::vec2_type),
>  _texture(ir_tg4, texture_gather_or_es31, 
> glsl_type::ivec4_type, glsl_type::isampler2D_type, glsl_type::vec2_type),
>  _texture(ir_tg4, texture_gather_or_es31, 
> glsl_type::uvec4_type, glsl_type::usampler2D_type, glsl_type::vec2_type),
>  
>  _texture(ir_tg4, gpu_shader5, glsl_type::vec4_type, 
> glsl_type::sampler2DRect_type, glsl_type::vec2_type),
>  _texture(ir_tg4, gpu_shader5, glsl_type::ivec4_type, 
> glsl_type::isampler2DRect_type, glsl_type::vec2_type),
>  _texture(ir_tg4, gpu_shader5, glsl_type::uvec4_type, 
> glsl_type::usampler2DRect_type, glsl_type::vec2_type),
>  
>  _texture(ir_tg4, texture_gather_or_es31, 
> glsl_type::vec4_type, glsl_type::sampler2DArray_type, glsl_type::vec3_type),
> diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
> b/src/compiler/glsl/glsl_parser_extras.cpp
> index a455dde122a..9dbaef8f729 100644
> --- a/src/compiler/glsl/glsl_parser_extras.cpp
> +++ b/src/compiler/glsl/glsl_parser_extras.cpp
> @@ -694,20 +694,21 @@ static const _mesa_glsl_extension 
> _mesa_glsl_supported_extensions[] = {
> EXT(OES_texture_cube_map_array),
> 

Re: [Mesa-dev] [PATCH 6/8] mesa: expose EXT_vertex_attrib_64bit

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 08/08/2018 07:12 PM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> because the closed driver exposes it.
> It's the same as the ARB extension.
> ---
>  docs/relnotes/18.3.0.html |  1 +
>  .../glapi/gen/EXT_vertex_attrib_64bit.xml | 70 +++
>  src/mapi/glapi/gen/gl_API.xml |  2 +
>  src/mesa/main/extensions_table.h  |  1 +
>  4 files changed, 74 insertions(+)
>  create mode 100644 src/mapi/glapi/gen/EXT_vertex_attrib_64bit.xml
> 
> diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
> index 8b067b55d3c..3d6081708b5 100644
> --- a/docs/relnotes/18.3.0.html
> +++ b/docs/relnotes/18.3.0.html
> @@ -49,20 +49,21 @@ TBD.
>  
>  Note: some of the new features are only available with certain drivers.
>  
>  
>  
>  GL_AMD_framebuffer_multisample_advanced on radeonsi.
>  GL_AMD_gpu_shader_int64 on i965, nvc0, radeonsi.
>  GL_AMD_multi_draw_indirect on all GL 4.x drivers.
>  GL_AMD_query_buffer_object on i965, nvc0, r600, radeonsi.
>  GL_AMD_texture_texture4 on i965, nvc0, r600, radeonsi.
> +GL_EXT_vertex_attrib_64bit on i965, nvc0, radeonsi.
>  GL_EXT_window_rectangles on radeonsi.
>  
>  
>  Bug fixes
>  
>  
>  TBD
>  
>  
>  Changes
> diff --git a/src/mapi/glapi/gen/EXT_vertex_attrib_64bit.xml 
> b/src/mapi/glapi/gen/EXT_vertex_attrib_64bit.xml
> new file mode 100644
> index 000..6b63b122fc1
> --- /dev/null
> +++ b/src/mapi/glapi/gen/EXT_vertex_attrib_64bit.xml
> @@ -0,0 +1,70 @@
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> +
> diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
> index a45fdc5ed98..41454b212df 100644
> --- a/src/mapi/glapi/gen/gl_API.xml
> +++ b/src/mapi/glapi/gen/gl_API.xml
> @@ -12932,20 +12932,22 @@
>  
>  
>  
>  
>  
>  
>  
> xmlns:xi="http://www.w3.org/2001/XInclude"/>
>  
> + xmlns:xi="http://www.w3.org/2001/XInclude"/>
> +
>  
>  
>  
>  
>  
>  
>  
>  
>  
>  
> diff --git a/src/mesa/main/extensions_table.h 
> b/src/mesa/main/extensions_table.h
> index 629a42f64e0..de1e796bc5d 100644
> --- a/src/mesa/main/extensions_table.h
> +++ b/src/mesa/main/extensions_table.h
> @@ -297,20 +297,21 @@ EXT(EXT_texture_sRGB, 
> EXT_texture_sRGB
>  EXT(EXT_texture_sRGB_decode , EXT_texture_sRGB_decode
> , GLL, GLC,  x ,  30, 2006)
>  EXT(EXT_texture_shared_exponent , EXT_texture_shared_exponent
> , GLL, GLC,  x ,  x , 2004)
>  EXT(EXT_texture_snorm   , EXT_texture_snorm  
> , GLL, GLC,  x ,  x , 2009)
>  EXT(EXT_texture_swizzle , EXT_texture_swizzle
> , GLL, GLC,  x ,  x , 2008)
>  EXT(EXT_texture_type_2_10_10_10_REV , 
> EXT_texture_type_2_10_10_10_REV,  x ,  x ,  x , ES2, 2008)
>  EXT(EXT_timer_query , EXT_timer_query
> , GLL, GLC,  x ,  x , 2006)
>  EXT(EXT_transform_feedback  , EXT_transform_feedback 
> , GLL, GLC,  x ,  x , 2011)
>  EXT(EXT_unpack_subimage , dummy_true 
> ,  x ,  x ,  x , ES2, 2011)
>  EXT(EXT_vertex_array, dummy_true 
> , GLL,  x ,  x ,  x , 1995)
>  EXT(EXT_vertex_array_bgra   , EXT_vertex_array_bgra  
> , GLL, GLC,  x ,  x , 2008)
> +EXT(EXT_vertex_attrib_64bit , ARB_vertex_attrib_64bit
> ,  32, GLC,  x ,  x , 2010)
>  EXT(EXT_window_rectangles   , EXT_window_rectangles  
> , GLL, GLC,  x ,  30, 2016)
>  
>  EXT(GREMEDY_string_marker   , GREMEDY_string_marker  
> , GLL, GLC,  x ,  x , 2007)
>  
>  EXT(IBM_multimode_draw_arrays   , dummy_true 
> , GLL, GLC,  x ,  x , 1998)
>  EXT(IBM_rasterpos_clip  , dummy_true 
> , GLL,  x ,  x ,  x , 1996)
>  EXT(IBM_texture_mirrored_repeat , dummy_true 
> , GLL,  x ,  x ,  x , 1998)
>  
>  EXT(INGR_blend_func_separate, EXT_blend_func_separate
> , GLL,  x ,  x ,  x , 1999)
>  
> 

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Re: [Mesa-dev] [PATCH 15/21] mesa: move legacy dri config option texture_units

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

I think that's the last one that I'm going to do right now.  If nobody
beats me to it, I'll try to look at the others later.

On 08/15/2018 03:13 AM, Timothy Arceri wrote:
> ---
>  src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
>  src/util/xmlpool/ca.po  | 4 
>  src/util/xmlpool/de.po  | 4 
>  src/util/xmlpool/es.po  | 4 
>  src/util/xmlpool/fr.po  | 4 
>  src/util/xmlpool/nl.po  | 4 
>  src/util/xmlpool/sv.po  | 4 
>  src/util/xmlpool/t_options.h| 5 -
>  8 files changed, 5 insertions(+), 29 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c 
> b/src/mesa/drivers/dri/radeon/radeon_screen.c
> index 2dd29aeab09..e19945318b7 100644
> --- a/src/mesa/drivers/dri/radeon/radeon_screen.c
> +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
> @@ -75,6 +75,11 @@ DRI_CONF_OPT_BEGIN_B(hyperz, def) \
>  DRI_CONF_DESC(en,"Use HyperZ to boost performance") \
>  DRI_CONF_OPT_END
>  
> +#define DRI_CONF_MAX_TEXTURE_UNITS(def,min,max) \
> +DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
> +DRI_CONF_DESC(en,"Number of texture units used") \
> +DRI_CONF_OPT_END
> +
>  #if defined(RADEON_R100) /* R100 */
>  static const __DRIconfigOptionsExtension radeon_config_options = {
> .base = { __DRI_CONFIG_OPTIONS, 1 },
> diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
> index 36e44a21553..5f78915b544 100644
> --- a/src/util/xmlpool/ca.po
> +++ b/src/util/xmlpool/ca.po
> @@ -207,10 +207,6 @@ msgstr ""
>  "Sempre sincronitza amb el refresc vertical, l'aplicació tria l'interval "
>  "mínim d'intercanvi"
>  
> -#: t_options.h:281
> -msgid "Number of texture units used"
> -msgstr "Nombre d'unitats de textura utilitzades"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr "Miscel·lània"
> diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
> index 0b7a29980a6..2ef0607cbb2 100644
> --- a/src/util/xmlpool/de.po
> +++ b/src/util/xmlpool/de.po
> @@ -182,10 +182,6 @@ msgstr ""
>  "Immer mit der Bildwiederholung synchronisieren, Anwendung wählt das 
> minimale "
>  "Bildintervall"
>  
> -#: t_options.h:281
> -msgid "Number of texture units used"
> -msgstr "Anzahl der benutzten Textureinheiten"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
> index 1230194c14c..cfb6c0eb18d 100644
> --- a/src/util/xmlpool/es.po
> +++ b/src/util/xmlpool/es.po
> @@ -191,10 +191,6 @@ msgstr ""
>  "Sincronizar siempre con el refresco vertical, la aplicación elige el "
>  "intervalo de intercambio mínimo"
>  
> -#: t_options.h:281
> -msgid "Number of texture units used"
> -msgstr "Número de unidades de textura usadas"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr "Misceláneos"
> diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
> index 92d31e54488..94a248069a0 100644
> --- a/src/util/xmlpool/fr.po
> +++ b/src/util/xmlpool/fr.po
> @@ -180,10 +180,6 @@ msgstr ""
>  "Toujours synchroniser avec le balayage vertical, l'application choisit "
>  "l'intervalle minimal"
>  
> -#: t_options.h:281
> -msgid "Number of texture units used"
> -msgstr "Nombre d'unités de texture"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
> index 80f162c5e58..9beafb42224 100644
> --- a/src/util/xmlpool/nl.po
> +++ b/src/util/xmlpool/nl.po
> @@ -179,10 +179,6 @@ msgstr ""
>  "Synchroniseer altijd met verticale verversing, de applicatie kiest het "
>  "minimum omwisselingsinterval"
>  
> -#: t_options.h:281
> -msgid "Number of texture units used"
> -msgstr "Aantal textuureenheden in gebruik"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
> index f26332777bc..d952d5d8388 100644
> --- a/src/util/xmlpool/sv.po
> +++ b/src/util/xmlpool/sv.po
> @@ -190,10 +190,6 @@ msgstr ""
>  "Synkronisera alltid med vertikal uppdatering, programmet väljer den minsta "
>  "växlingsintervallen"
>  
> -#: t_options.h:281
> -msgid "Number of texture units used"
> -msgstr "Antal använda texturenheter"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
> index 4beb03824af..eed7dc4f315 100644
> --- a/src/util/xmlpool/t_options.h
> +++ b/src/util/xmlpool/t_options.h
> @@ -251,11 +251,6 @@ DRI_CONF_OPT_BEGIN_V(vblank_mode,enum,def,"0:3") \
>  DRI_CONF_DESC_END \
>  DRI_CONF_OPT_END
>  
> -#define DRI_CONF_MAX_TEXTURE_UNITS(def,min,max) \
> -DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
> -DRI_CONF_DESC(en,gettext("Number of texture units used")) \
> -DRI_CONF_OPT_END
> -
>  #define DRI_CONF_MESA_GLTHREAD(def) \
>  

Re: [Mesa-dev] [PATCH 14/21] mesa: remove unused dri config option texture_heaps

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 08/15/2018 03:13 AM, Timothy Arceri wrote:
> This seems to have only been used by DRI1 drivers which were
> removed with e4344161bde2.
> ---
>  src/util/xmlpool/ca.po   | 16 
>  src/util/xmlpool/de.po   | 16 
>  src/util/xmlpool/es.po   | 16 
>  src/util/xmlpool/fr.po   | 16 
>  src/util/xmlpool/nl.po   | 16 
>  src/util/xmlpool/sv.po   | 16 
>  src/util/xmlpool/t_options.h | 12 
>  7 files changed, 108 deletions(-)
> 
> diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
> index 363464c927f..36e44a21553 100644
> --- a/src/util/xmlpool/ca.po
> +++ b/src/util/xmlpool/ca.po
> @@ -211,22 +211,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Nombre d'unitats de textura utilitzades"
>  
> -#: t_options.h:294
> -msgid "Used types of texture memory"
> -msgstr "Tipus utilitzats de memòria de textura"
> -
> -#: t_options.h:295
> -msgid "All available memory"
> -msgstr "Tota la memòria disponible"
> -
> -#: t_options.h:296
> -msgid "Only card memory (if available)"
> -msgstr "Només memòria de targeta (si està disponible)"
> -
> -#: t_options.h:297
> -msgid "Only GART (AGP/PCIE) memory (if available)"
> -msgstr "Només memòria GART (AGP/PCIE) (si està disponible)"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr "Miscel·lània"
> diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
> index 3e1b70f8b37..0b7a29980a6 100644
> --- a/src/util/xmlpool/de.po
> +++ b/src/util/xmlpool/de.po
> @@ -186,22 +186,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Anzahl der benutzten Textureinheiten"
>  
> -#: t_options.h:294
> -msgid "Used types of texture memory"
> -msgstr "Benutzte Arten von Texturspeicher"
> -
> -#: t_options.h:295
> -msgid "All available memory"
> -msgstr "Aller verfügbarer Speicher"
> -
> -#: t_options.h:296
> -msgid "Only card memory (if available)"
> -msgstr "Nur Grafikspeicher (falls verfügbar)"
> -
> -#: t_options.h:297
> -msgid "Only GART (AGP/PCIE) memory (if available)"
> -msgstr "Nur GART-Speicher (AGP/PCIE) (falls verfügbar)"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
> index 01d3ca3c178..1230194c14c 100644
> --- a/src/util/xmlpool/es.po
> +++ b/src/util/xmlpool/es.po
> @@ -195,22 +195,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Número de unidades de textura usadas"
>  
> -#: t_options.h:294
> -msgid "Used types of texture memory"
> -msgstr "Tipos de memoria de textura usados"
> -
> -#: t_options.h:295
> -msgid "All available memory"
> -msgstr "Toda la memoria disponible"
> -
> -#: t_options.h:296
> -msgid "Only card memory (if available)"
> -msgstr "Solo memoria de tarjeta (si está disponible)"
> -
> -#: t_options.h:297
> -msgid "Only GART (AGP/PCIE) memory (if available)"
> -msgstr "Solo memoria GART (AGP/PCIE) (si está disponible)"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr "Misceláneos"
> diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
> index 7c631fce9e6..92d31e54488 100644
> --- a/src/util/xmlpool/fr.po
> +++ b/src/util/xmlpool/fr.po
> @@ -184,22 +184,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Nombre d'unités de texture"
>  
> -#: t_options.h:294
> -msgid "Used types of texture memory"
> -msgstr "Types de mémoire de texture"
> -
> -#: t_options.h:295
> -msgid "All available memory"
> -msgstr "Utiliser toute la mémoire disponible"
> -
> -#: t_options.h:296
> -msgid "Only card memory (if available)"
> -msgstr "Utiliser uniquement la mémoire graphique (si disponible)"
> -
> -#: t_options.h:297
> -msgid "Only GART (AGP/PCIE) memory (if available)"
> -msgstr "Utiliser uniquement la mémoire GART (AGP/PCIE) (si disponible)"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
> index ddd7a24a0e0..80f162c5e58 100644
> --- a/src/util/xmlpool/nl.po
> +++ b/src/util/xmlpool/nl.po
> @@ -183,22 +183,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Aantal textuureenheden in gebruik"
>  
> -#: t_options.h:294
> -msgid "Used types of texture memory"
> -msgstr "Gebruikte soorten textuurgeheugen"
> -
> -#: t_options.h:295
> -msgid "All available memory"
> -msgstr "Al het beschikbaar geheugen"
> -
> -#: t_options.h:296
> -msgid "Only card memory (if available)"
> -msgstr "Alleen geheugen op de kaart (als het aanwezig is)"
> -
> -#: t_options.h:297
> -msgid "Only GART (AGP/PCIE) memory (if available)"
> -msgstr "Alleen GART (AGP/PCIE) geheugen (als het aanwezig is)"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
> index bc4f5326afa..f26332777bc 100644
> --- a/src/util/xmlpool/sv.po
> +++ b/src/util/xmlpool/sv.po
> @@ -194,22 +194,6 @@ msgstr ""
>  msgid 

Re: [Mesa-dev] [PATCH 13/21] mesa: move legacy dri config option texture_blend_quality

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 08/15/2018 03:13 AM, Timothy Arceri wrote:
> ---
>  src/mesa/drivers/dri/radeon/radeon_screen.c | 6 ++
>  src/util/xmlpool/ca.po  | 6 --
>  src/util/xmlpool/de.po  | 6 --
>  src/util/xmlpool/es.po  | 6 --
>  src/util/xmlpool/fr.po  | 5 -
>  src/util/xmlpool/nl.po  | 6 --
>  src/util/xmlpool/sv.po  | 6 --
>  src/util/xmlpool/t_options.h| 5 -
>  8 files changed, 6 insertions(+), 40 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c 
> b/src/mesa/drivers/dri/radeon/radeon_screen.c
> index 0a6aa5109b4..2dd29aeab09 100644
> --- a/src/mesa/drivers/dri/radeon/radeon_screen.c
> +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
> @@ -98,6 +98,12 @@ DRI_CONF_END
>  };
>  
>  #elif defined(RADEON_R200)
> +
> +#define DRI_CONF_TEXTURE_BLEND_QUALITY(def,range) \
> +DRI_CONF_OPT_BEGIN_V(texture_blend_quality,float,def,range) \
> +   DRI_CONF_DESC(en,"Texture filtering quality vs. speed, AKA 
> “brilinear” texture filtering") \
> +DRI_CONF_OPT_END
> +
>  static const __DRIconfigOptionsExtension radeon_config_options = {
> .base = { __DRI_CONFIG_OPTIONS, 1 },
> .xml =
> diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
> index 0351ff16355..363464c927f 100644
> --- a/src/util/xmlpool/ca.po
> +++ b/src/util/xmlpool/ca.po
> @@ -211,12 +211,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Nombre d'unitats de textura utilitzades"
>  
> -#: t_options.h:286
> -msgid "Texture filtering quality vs. speed, AKA “brilinear” texture 
> filtering"
> -msgstr ""
> -"Qualitat vs. velocitat de filtració de textura, àlies filtració \"brilinear"
> -"\" de textura"
> -
>  #: t_options.h:294
>  msgid "Used types of texture memory"
>  msgstr "Tipus utilitzats de memòria de textura"
> diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
> index 5b30d890b40..3e1b70f8b37 100644
> --- a/src/util/xmlpool/de.po
> +++ b/src/util/xmlpool/de.po
> @@ -186,12 +186,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Anzahl der benutzten Textureinheiten"
>  
> -#: t_options.h:286
> -msgid "Texture filtering quality vs. speed, AKA “brilinear” texture 
> filtering"
> -msgstr ""
> -"Texturfilterqualität versus -geschwindigkeit, auch bekannt als „brilineare“ 
> "
> -"Texturfilterung"
> -
>  #: t_options.h:294
>  msgid "Used types of texture memory"
>  msgstr "Benutzte Arten von Texturspeicher"
> diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
> index a223da041eb..01d3ca3c178 100644
> --- a/src/util/xmlpool/es.po
> +++ b/src/util/xmlpool/es.po
> @@ -195,12 +195,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Número de unidades de textura usadas"
>  
> -#: t_options.h:286
> -msgid "Texture filtering quality vs. speed, AKA “brilinear” texture 
> filtering"
> -msgstr ""
> -"Calidad de filtrado de textura vs. velocidad, alias filtrado \"brilinear\" "
> -"de textura"
> -
>  #: t_options.h:294
>  msgid "Used types of texture memory"
>  msgstr "Tipos de memoria de textura usados"
> diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
> index e4a963af62e..7c631fce9e6 100644
> --- a/src/util/xmlpool/fr.po
> +++ b/src/util/xmlpool/fr.po
> @@ -184,11 +184,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Nombre d'unités de texture"
>  
> -#: t_options.h:286
> -msgid "Texture filtering quality vs. speed, AKA “brilinear” texture 
> filtering"
> -msgstr ""
> -"Qualité/performance du filtrage trilinéaire de texture (filtrage 
> brilinéaire)"
> -
>  #: t_options.h:294
>  msgid "Used types of texture memory"
>  msgstr "Types de mémoire de texture"
> diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
> index a91ad89ac4a..ddd7a24a0e0 100644
> --- a/src/util/xmlpool/nl.po
> +++ b/src/util/xmlpool/nl.po
> @@ -183,12 +183,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Aantal textuureenheden in gebruik"
>  
> -#: t_options.h:286
> -msgid "Texture filtering quality vs. speed, AKA “brilinear” texture 
> filtering"
> -msgstr ""
> -"Textuurfilterkwaliteit versus -snelheid, ookwel bekend als “brilineaire” "
> -"textuurfiltering"
> -
>  #: t_options.h:294
>  msgid "Used types of texture memory"
>  msgstr "Gebruikte soorten textuurgeheugen"
> diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
> index c2d640b2141..bc4f5326afa 100644
> --- a/src/util/xmlpool/sv.po
> +++ b/src/util/xmlpool/sv.po
> @@ -194,12 +194,6 @@ msgstr ""
>  msgid "Number of texture units used"
>  msgstr "Antal använda texturenheter"
>  
> -#: t_options.h:286
> -msgid "Texture filtering quality vs. speed, AKA “brilinear” texture 
> filtering"
> -msgstr ""
> -"Texturfiltreringskvalitet mot hastighet, även kallad \"brilinear\"-"
> -"texturfiltrering"
> -
>  #: t_options.h:294
>  msgid "Used types of texture memory"
>  msgstr "Använda 

Re: [Mesa-dev] [PATCH 12/21] util: remove unused S3TC translation for dri config

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 08/15/2018 03:13 AM, Timothy Arceri wrote:
> ---
>  src/util/xmlpool/ca.po | 7 ---
>  src/util/xmlpool/de.po | 7 ---
>  src/util/xmlpool/es.po | 7 ---
>  src/util/xmlpool/fr.po | 6 --
>  src/util/xmlpool/nl.po | 7 ---
>  src/util/xmlpool/sv.po | 5 -
>  6 files changed, 39 deletions(-)
> 
> diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
> index 6177e416b56..0351ff16355 100644
> --- a/src/util/xmlpool/ca.po
> +++ b/src/util/xmlpool/ca.po
> @@ -112,13 +112,6 @@ msgstr ""
>  "Prohibeix una parcialitat negativa del Nivell de Detalle (LOD) de les "
>  "textures"
>  
> -#: t_options.h:153
> -msgid ""
> -"Enable S3TC texture compression even if software support is not available"
> -msgstr ""
> -"Habilita la compressió de textures S3TC encara que el suport de programari "
> -"no estigui disponible"
> -
>  #: t_options.h:170
>  msgid "Color rounding method"
>  msgstr "Mètode d'arrodoniment de color"
> diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
> index aeead969c28..5b30d890b40 100644
> --- a/src/util/xmlpool/de.po
> +++ b/src/util/xmlpool/de.po
> @@ -87,13 +87,6 @@ msgstr "Initialer Maximalwert für anisotropische 
> Texturfilterung"
>  msgid "Forbid negative texture LOD bias"
>  msgstr "Verbiete negative Textur-Detailgradverschiebung"
>  
> -#: t_options.h:153
> -msgid ""
> -"Enable S3TC texture compression even if software support is not available"
> -msgstr ""
> -"Aktiviere S3TC Texturkomprimierung auch wenn die nötige "
> -"Softwareunterstützung fehlt"
> -
>  #: t_options.h:170
>  msgid "Color rounding method"
>  msgstr "Farbrundungsmethode"
> diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
> index eb52a60204e..a223da041eb 100644
> --- a/src/util/xmlpool/es.po
> +++ b/src/util/xmlpool/es.po
> @@ -94,13 +94,6 @@ msgstr "Valor máximo inicial para filtrado anisotrópico de 
> textura"
>  msgid "Forbid negative texture LOD bias"
>  msgstr "Prohibir valores negativos de Nivel De Detalle (LOD) de texturas"
>  
> -#: t_options.h:153
> -msgid ""
> -"Enable S3TC texture compression even if software support is not available"
> -msgstr ""
> -"Habilitar la compresión de texturas S3TC incluso si el soporte por software 
> "
> -"no está disponible"
> -
>  #: t_options.h:170
>  msgid "Color rounding method"
>  msgstr "Método de redondeo de colores"
> diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
> index 611e9ed46fe..e4a963af62e 100644
> --- a/src/util/xmlpool/fr.po
> +++ b/src/util/xmlpool/fr.po
> @@ -86,12 +86,6 @@ msgstr "Valeur maximale initiale pour le filtrage 
> anisotropique de texture"
>  msgid "Forbid negative texture LOD bias"
>  msgstr "Interdire le LOD bias negatif"
>  
> -#: t_options.h:153
> -msgid ""
> -"Enable S3TC texture compression even if software support is not available"
> -msgstr ""
> -"Activer la compression de texture S3TC même si le support logiciel est 
> absent"
> -
>  #: t_options.h:170
>  msgid "Color rounding method"
>  msgstr "Méthode d'arrondi des couleurs"
> diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
> index 51e7050b2eb..a91ad89ac4a 100644
> --- a/src/util/xmlpool/nl.po
> +++ b/src/util/xmlpool/nl.po
> @@ -86,13 +86,6 @@ msgstr "Initïele maximum waarde voor anisotrophische 
> textuur filtering"
>  msgid "Forbid negative texture LOD bias"
>  msgstr "Verbied negatief niveau detailonderscheid (LOD) van texturen"
>  
> -#: t_options.h:153
> -msgid ""
> -"Enable S3TC texture compression even if software support is not available"
> -msgstr ""
> -"Schakel S3TC textuurcompressie in, zelfs als softwareondersteuning niet "
> -"aanwezig is"
> -
>  #: t_options.h:182
>  msgid "Horizontal error diffusion"
>  msgstr "Horizontale foutdiffusie"
> diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
> index f7430625a24..c2d640b2141 100644
> --- a/src/util/xmlpool/sv.po
> +++ b/src/util/xmlpool/sv.po
> @@ -86,11 +86,6 @@ msgstr "Initialt maximalt värde för anisotropisk 
> texturfiltrering"
>  msgid "Forbid negative texture LOD bias"
>  msgstr "Förbjud negativ LOD-kompensation för texturer"
>  
> -#: t_options.h:153
> -msgid ""
> -"Enable S3TC texture compression even if software support is not available"
> -msgstr "Aktivera S3TC-texturkomprimering även om programvarustöd saknas"
> -
>  #: t_options.h:170
>  msgid "Color rounding method"
>  msgstr "Färgavrundningsmetod"
> 

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Re: [Mesa-dev] [PATCH 09/21] mesa: remove legacy TCL dri config options

[Ian Romanick]

On 08/15/2018 04:09 AM, Timothy Arceri wrote:
> On 15/08/18 20:26, Michel Dänzer wrote:
>> On 2018-08-15 12:13 PM, Timothy Arceri wrote:
>>> Use enviroment var overrides in legacy drivers instead.
>>
>> This could break existing user configurations using the driconf tcl_mode
>> option.
>>
>> Apart from this, I like the idea of this series.
> 
> I assumed this was a debug like option. If you think I should keep the
> dri config entry I can move it to the driver.

I have some vague recollection that at least at one time there were
applications that didn't work with HW TNL on at least R100 cards... or
maybe they just had rubbish performance.  The memories are pretty fuzzy.
 Moving it to the driver and deleting the duplicate envvar seems like
the safest option.

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Re: [Mesa-dev] [PATCH] anv: add VK_EXT_sampler_filter_minmax support

[He, Yunchao]

Thanks for your review, Jason. 
I submitted a new patch set accordingly. PTAL when you have time. 

-Original Message-
From: Jason Ekstrand [mailto:ja...@jlekstrand.net] 
Sent: Monday, August 13, 2018 6:00 PM
To: He, Yunchao ; mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH] anv: add VK_EXT_sampler_filter_minmax support

On August 10, 2018 19:18:53 Yunchao He  wrote:

> This extension can be supported on SKL+. With this patch, all 
> corresponding tests (6K+) in CTS can pass. No test fails.
>
> I verified CTS with the command below:
> deqp-vk --deqp-case=dEQP-VK.pipeline.sampler.view_type.*reduce*
> ---
> src/intel/vulkan/anv_device.c  |  8 
> src/intel/vulkan/anv_extensions.py |  1 +
> src/intel/vulkan/anv_formats.c |  6 ++
> src/intel/vulkan/genX_state.c  | 27 +++
> 4 files changed, 42 insertions(+)
>
> diff --git a/src/intel/vulkan/anv_device.c 
> b/src/intel/vulkan/anv_device.c index 04fd6a829e..e45ba4b3af 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -1116,6 +1116,14 @@ void anv_GetPhysicalDeviceProperties2(
>  break;
>   }
>
> +  case
> VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
> : {
> + VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
> +(VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
> + properties->filterMinmaxImageComponentMapping = 
> + pdevice->info.gen
> >= 9;
> + properties->filterMinmaxSingleComponentFormats = true;
> + break;
> +  }
> +
>   case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
>  VkPhysicalDeviceSubgroupProperties *properties = (void *)ext;
>
> diff --git a/src/intel/vulkan/anv_extensions.py
> b/src/intel/vulkan/anv_extensions.py
> index ea837744b4..e165bd371d 100644
> --- a/src/intel/vulkan/anv_extensions.py
> +++ b/src/intel/vulkan/anv_extensions.py
> @@ -125,6 +125,7 @@ EXTENSIONS = [
> Extension('VK_EXT_shader_stencil_export', 1, 
> 'device->info.gen 
> >= 9'),
> Extension('VK_EXT_vertex_attribute_divisor',  2, True),
> Extension('VK_EXT_post_depth_coverage',   1, 
> 'device->info.gen 
> >= 9'),
> +Extension('VK_EXT_sampler_filter_minmax', 1, 
> 'device->info.gen >= 9'),
> ]
>
> class VkVersion:
> diff --git a/src/intel/vulkan/anv_formats.c 
> b/src/intel/vulkan/anv_formats.c index 815b320a82..b0eb4c6afa 100644
> --- a/src/intel/vulkan/anv_formats.c
> +++ b/src/intel/vulkan/anv_formats.c
> @@ -489,6 +489,9 @@ get_image_format_features(const struct 
> gen_device_info *devinfo,
>   if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT || devinfo->gen >= 8)
>  flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
>
> +  if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT && devinfo->gen >= 9)
> + flags |= 
> + VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
> +
>   flags |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
>VK_FORMAT_FEATURE_BLIT_DST_BIT |
>VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR | @@ -521,6 
> +524,9 @@ get_image_format_features(const struct gen_device_info 
> *devinfo,
>if (isl_format_supports_sampling(devinfo, plane_format.isl_format)) {
>   flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
>
> +  if (devinfo->gen >= 9)
> + flags |= 
> +VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;

Something is indented wrong here

> +
>   if (isl_format_supports_filtering(devinfo, plane_format.isl_format))
>  flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
>}
> diff --git a/src/intel/vulkan/genX_state.c 
> b/src/intel/vulkan/genX_state.c index b1014d9e79..e095cb4cc0 100644
> --- a/src/intel/vulkan/genX_state.c
> +++ b/src/intel/vulkan/genX_state.c
> @@ -245,6 +245,14 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = {
>[VK_COMPARE_OP_ALWAYS]   = PREFILTEROPNEVER,
> };
>
> +#if GEN_GEN >= 9
> +static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
> +   [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
> +   [VK_SAMPLER_REDUCTION_MODE_MIN_EXT]  = MINIMUM,
> +   [VK_SAMPLER_REDUCTION_MODE_MAX_EXT]  = MAXIMUM,
> +};
> +#endif
> +
> VkResult genX(CreateSampler)(
> VkDevice_device,
> const VkSamplerCreateInfo*  pCreateInfo,
> @@ -266,6 +274,10 @@ VkResult genX(CreateSampler)(
>uint32_t border_color_offset = device->border_colors.offset +
>   pCreateInfo->borderColor * 64;
>
> +#if GEN_GEN >= 9
> +   unsigned sampler_reduction_mode = STD_FILTER; #endif
> +
>vk_foreach_struct(ext, pCreateInfo->pNext) {
>   switch (ext->sType) {
>   case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: { @@ 
> -281,6 +293,16 @@ VkResult genX(CreateSampler)(
>  sampler->conversion = conversion;
>  break;
>   }
> 

Re: [Mesa-dev] [PATCH 07/21] mesa: remove dri configs unused software-fallback options

[Ian Romanick]

I could have sworn that the nouveau_viex drivers used this, but I guess
not.  Weird.  This patch is

Reviewed-by: Ian Romanick 

On 08/15/2018 03:13 AM, Timothy Arceri wrote:
> These seems to have only been used by DRI1 drivers which were
> removed with e4344161bde2.
> ---
>  src/util/xmlpool/ca.po   |  8 
>  src/util/xmlpool/de.po   |  8 
>  src/util/xmlpool/es.po   |  8 
>  src/util/xmlpool/fr.po   |  8 
>  src/util/xmlpool/nl.po   |  8 
>  src/util/xmlpool/sv.po   |  8 
>  src/util/xmlpool/t_options.h | 14 --
>  7 files changed, 62 deletions(-)
> 
> diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
> index db74464cafb..36872e2f2ba 100644
> --- a/src/util/xmlpool/ca.po
> +++ b/src/util/xmlpool/ca.po
> @@ -295,14 +295,6 @@ msgstr "Només memòria de targeta (si està disponible)"
>  msgid "Only GART (AGP/PCIE) memory (if available)"
>  msgstr "Només memòria GART (AGP/PCIE) (si està disponible)"
>  
> -#: t_options.h:309
> -msgid "Features that are not hardware-accelerated"
> -msgstr "Característiques no accelerades per maquinari"
> -
> -#: t_options.h:313
> -msgid "Enable extension GL_ARB_vertex_program"
> -msgstr "Habilita l'extensió GL_ARB_vertex_program"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr "Miscel·lània"
> diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
> index fcd0e843869..57fa6fb4619 100644
> --- a/src/util/xmlpool/de.po
> +++ b/src/util/xmlpool/de.po
> @@ -270,14 +270,6 @@ msgstr "Nur Grafikspeicher (falls verfügbar)"
>  msgid "Only GART (AGP/PCIE) memory (if available)"
>  msgstr "Nur GART-Speicher (AGP/PCIE) (falls verfügbar)"
>  
> -#: t_options.h:309
> -msgid "Features that are not hardware-accelerated"
> -msgstr "Funktionalität, die nicht hardwarebeschleunigt ist"
> -
> -#: t_options.h:313
> -msgid "Enable extension GL_ARB_vertex_program"
> -msgstr "Erweiterung GL_ARB_vertex_program aktivieren"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
> index 666762cc4b5..68824b61af2 100644
> --- a/src/util/xmlpool/es.po
> +++ b/src/util/xmlpool/es.po
> @@ -279,14 +279,6 @@ msgstr "Solo memoria de tarjeta (si está disponible)"
>  msgid "Only GART (AGP/PCIE) memory (if available)"
>  msgstr "Solo memoria GART (AGP/PCIE) (si está disponible)"
>  
> -#: t_options.h:309
> -msgid "Features that are not hardware-accelerated"
> -msgstr "Características no aceleradas por hardware"
> -
> -#: t_options.h:313
> -msgid "Enable extension GL_ARB_vertex_program"
> -msgstr "Habilitar la extensión GL_ARB_vertex_program"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr "Misceláneos"
> diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
> index 6a1c23263c3..ea5f6812aeb 100644
> --- a/src/util/xmlpool/fr.po
> +++ b/src/util/xmlpool/fr.po
> @@ -266,14 +266,6 @@ msgstr "Utiliser uniquement la mémoire graphique (si 
> disponible)"
>  msgid "Only GART (AGP/PCIE) memory (if available)"
>  msgstr "Utiliser uniquement la mémoire GART (AGP/PCIE) (si disponible)"
>  
> -#: t_options.h:309
> -msgid "Features that are not hardware-accelerated"
> -msgstr "Fonctionnalités ne bénéficiant pas d'une accélération matérielle"
> -
> -#: t_options.h:313
> -msgid "Enable extension GL_ARB_vertex_program"
> -msgstr "Activer l'extension GL_ARB_vertex_program"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
> index f3576a9cf55..9dc0428ea63 100644
> --- a/src/util/xmlpool/nl.po
> +++ b/src/util/xmlpool/nl.po
> @@ -267,14 +267,6 @@ msgstr "Alleen geheugen op de kaart (als het aanwezig 
> is)"
>  msgid "Only GART (AGP/PCIE) memory (if available)"
>  msgstr "Alleen GART (AGP/PCIE) geheugen (als het aanwezig is)"
>  
> -#: t_options.h:309
> -msgid "Features that are not hardware-accelerated"
> -msgstr "Eigenschappen die niet hardwareversneld zijn"
> -
> -#: t_options.h:313
> -msgid "Enable extension GL_ARB_vertex_program"
> -msgstr "Zet uitbreiding GL_ARB_vertex_program aan"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
> index 05aca5d0a95..d156eba7214 100644
> --- a/src/util/xmlpool/sv.po
> +++ b/src/util/xmlpool/sv.po
> @@ -259,14 +259,6 @@ msgstr "Endast kortminne (om tillgängligt)"
>  msgid "Only GART (AGP/PCIE) memory (if available)"
>  msgstr "Endast GART-minne (AGP/PCIE) (om tillgängligt)"
>  
> -#: t_options.h:309
> -msgid "Features that are not hardware-accelerated"
> -msgstr "Funktioner som inte är hårdvaruaccelererade"
> -
> -#: t_options.h:313
> -msgid "Enable extension GL_ARB_vertex_program"
> -msgstr "Aktivera tillägget GL_ARB_vertex_program"
> -
>  #: t_options.h:323
>  msgid "Miscellaneous"
>  msgstr ""
> diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
> index f0dc78dd595..ee12f104d76 100644
> --- a/src/util/xmlpool/t_options.h
> 

Re: [Mesa-dev] [PATCH 06/21] mesa: remove unused dri config option excess_mipmap

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 08/15/2018 03:13 AM, Timothy Arceri wrote:
> This seems to have only been used by DRI1 drivers which were
> removed with e4344161bde2.
> ---
>  src/util/xmlpool/t_options.h | 5 -
>  1 file changed, 5 deletions(-)
> 
> diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
> index 3e5993caf78..f0dc78dd595 100644
> --- a/src/util/xmlpool/t_options.h
> +++ b/src/util/xmlpool/t_options.h
> @@ -142,11 +142,6 @@ DRI_CONF_OPT_END
>  DRI_CONF_SECTION_BEGIN \
>   DRI_CONF_DESC(en,gettext("Image Quality"))
>  
> -#define DRI_CONF_EXCESS_MIPMAP(def) \
> -DRI_CONF_OPT_BEGIN_B(excess_mipmap, def) \
> - DRI_CONF_DESC(en,"Enable extra mipmap level") \
> -DRI_CONF_OPT_END
> -
>  #define DRI_CONF_TEXTURE_DEPTH_FB   0
>  #define DRI_CONF_TEXTURE_DEPTH_32   1
>  #define DRI_CONF_TEXTURE_DEPTH_16   2
> 

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[Mesa-dev] [PATCH v2] anv: add VK_EXT_sampler_filter_minmax support

[Yunchao He]

This extension can be supported on SKL+. With this patch,
all corresponding tests (6K+) in CTS can pass. No test fails.

I verified CTS with the command below:
deqp-vk --deqp-case=dEQP-VK.pipeline.sampler.view_type.*reduce*

v2: 1) support all depth formats, not depth-only formats, 2) fix
a wrong indention (Jason).
---
 src/intel/vulkan/anv_device.c  |  8 
 src/intel/vulkan/anv_extensions.py |  1 +
 src/intel/vulkan/anv_formats.c |  6 ++
 src/intel/vulkan/genX_state.c  | 27 +++
 4 files changed, 42 insertions(+)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 04fd6a829e..e45ba4b3af 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1116,6 +1116,14 @@ void anv_GetPhysicalDeviceProperties2(
  break;
   }
 
+  case 
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
+ VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
+(VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
+ properties->filterMinmaxImageComponentMapping = pdevice->info.gen >= 
9;
+ properties->filterMinmaxSingleComponentFormats = true;
+ break;
+  }
+
   case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
  VkPhysicalDeviceSubgroupProperties *properties = (void *)ext;
 
diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index ea837744b4..e165bd371d 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -125,6 +125,7 @@ EXTENSIONS = [
 Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen 
>= 9'),
 Extension('VK_EXT_vertex_attribute_divisor',  2, True),
 Extension('VK_EXT_post_depth_coverage',   1, 'device->info.gen 
>= 9'),
+Extension('VK_EXT_sampler_filter_minmax', 1, 'device->info.gen 
>= 9'),
 ]
 
 class VkVersion:
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 815b320a82..33faf7cc37 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -489,6 +489,9 @@ get_image_format_features(const struct gen_device_info 
*devinfo,
   if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT || devinfo->gen >= 8)
  flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
 
+  if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
   flags |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
VK_FORMAT_FEATURE_BLIT_DST_BIT |
VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
@@ -521,6 +524,9 @@ get_image_format_features(const struct gen_device_info 
*devinfo,
if (isl_format_supports_sampling(devinfo, plane_format.isl_format)) {
   flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
 
+  if (devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
   if (isl_format_supports_filtering(devinfo, plane_format.isl_format))
  flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
}
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index b1014d9e79..e095cb4cc0 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -245,6 +245,14 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = {
[VK_COMPARE_OP_ALWAYS]   = PREFILTEROPNEVER,
 };
 
+#if GEN_GEN >= 9
+static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
+   [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
+   [VK_SAMPLER_REDUCTION_MODE_MIN_EXT]  = MINIMUM,
+   [VK_SAMPLER_REDUCTION_MODE_MAX_EXT]  = MAXIMUM,
+};
+#endif
+
 VkResult genX(CreateSampler)(
 VkDevice_device,
 const VkSamplerCreateInfo*  pCreateInfo,
@@ -266,6 +274,10 @@ VkResult genX(CreateSampler)(
uint32_t border_color_offset = device->border_colors.offset +
   pCreateInfo->borderColor * 64;
 
+#if GEN_GEN >= 9
+   unsigned sampler_reduction_mode = STD_FILTER;
+#endif
+
vk_foreach_struct(ext, pCreateInfo->pNext) {
   switch (ext->sType) {
   case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
@@ -281,6 +293,16 @@ VkResult genX(CreateSampler)(
  sampler->conversion = conversion;
  break;
   }
+#if GEN_GEN >= 9
+  case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
+struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
+   (struct VkSamplerReductionModeCreateInfoEXT *) ext;
+ if (sampler_reduction)
+sampler_reduction_mode =
+   
vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode];
+ break;
+  }
+#endif
   default:
  anv_debug_ignored_stype(ext->sType);
  break;
@@ -348,6 +370,11 @@ VkResult 

Re: [Mesa-dev] [PATCH 04/21] mesa: remove unused dri config option performance_boxes

[Ian Romanick]

This patch is

Reviewed-by: Ian Romanick 

On 08/15/2018 03:13 AM, Timothy Arceri wrote:
> This seems to have only been used by DRI1 drivers which were
> removed with e4344161bde2.
> ---
>  src/util/xmlpool/ca.po   | 4 
>  src/util/xmlpool/de.po   | 4 
>  src/util/xmlpool/es.po   | 4 
>  src/util/xmlpool/fr.po   | 4 
>  src/util/xmlpool/nl.po   | 4 
>  src/util/xmlpool/sv.po   | 4 
>  src/util/xmlpool/t_options.h | 5 -
>  7 files changed, 29 deletions(-)
> 
> diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
> index 568be939eb8..a1e42d43977 100644
> --- a/src/util/xmlpool/ca.po
> +++ b/src/util/xmlpool/ca.po
> @@ -39,10 +39,6 @@ msgstr ""
>  msgid "Debugging"
>  msgstr "Depuració"
>  
> -#: t_options.h:65
> -msgid "Show performance boxes"
> -msgstr "Mostra les caixes de rendiment"
> -
>  #: t_options.h:70
>  msgid "Enable flushing batchbuffer after each draw call"
>  msgstr "Habilita el buidatge del batchbuffer després de cada trucada de 
> dibuix"
> diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
> index 9aa9c11e075..fc915447919 100644
> --- a/src/util/xmlpool/de.po
> +++ b/src/util/xmlpool/de.po
> @@ -21,10 +21,6 @@ msgstr ""
>  msgid "Debugging"
>  msgstr "Fehlersuche"
>  
> -#: t_options.h:65
> -msgid "Show performance boxes"
> -msgstr "Zeige Performanceboxen"
> -
>  #: t_options.h:70
>  msgid "Enable flushing batchbuffer after each draw call"
>  msgstr "Aktiviere sofortige Leerung des Stapelpuffers nach jedem 
> Zeichenaufruf"
> diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
> index 581a30c3595..8ccf14876fe 100644
> --- a/src/util/xmlpool/es.po
> +++ b/src/util/xmlpool/es.po
> @@ -24,10 +24,6 @@ msgstr ""
>  msgid "Debugging"
>  msgstr "Depuración"
>  
> -#: t_options.h:65
> -msgid "Show performance boxes"
> -msgstr "Mostrar cajas de rendimiento"
> -
>  #: t_options.h:70
>  msgid "Enable flushing batchbuffer after each draw call"
>  msgstr "Habilitar vaciado del batchbuffer después de cada llamada de dibujo"
> diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
> index 27a2a4f5e47..c3c7895a68f 100644
> --- a/src/util/xmlpool/fr.po
> +++ b/src/util/xmlpool/fr.po
> @@ -21,10 +21,6 @@ msgstr ""
>  msgid "Debugging"
>  msgstr "Debogage"
>  
> -#: t_options.h:65
> -msgid "Show performance boxes"
> -msgstr "Afficher les boîtes de performance"
> -
>  #: t_options.h:70
>  msgid "Enable flushing batchbuffer after each draw call"
>  msgstr ""
> diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
> index dc8a73098eb..1d4ecd14049 100644
> --- a/src/util/xmlpool/nl.po
> +++ b/src/util/xmlpool/nl.po
> @@ -21,10 +21,6 @@ msgstr ""
>  msgid "Debugging"
>  msgstr "Debuggen"
>  
> -#: t_options.h:65
> -msgid "Show performance boxes"
> -msgstr "Laat prestatie boxjes zien"
> -
>  #: t_options.h:70
>  msgid "Enable flushing batchbuffer after each draw call"
>  msgstr ""
> diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
> index 33f389d6075..764c66c367c 100644
> --- a/src/util/xmlpool/sv.po
> +++ b/src/util/xmlpool/sv.po
> @@ -21,10 +21,6 @@ msgstr ""
>  msgid "Debugging"
>  msgstr "Felsökning"
>  
> -#: t_options.h:65
> -msgid "Show performance boxes"
> -msgstr "Visa prestandarutor"
> -
>  #: t_options.h:70
>  msgid "Enable flushing batchbuffer after each draw call"
>  msgstr ""
> diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
> index 4c143009efe..bd4304a155d 100644
> --- a/src/util/xmlpool/t_options.h
> +++ b/src/util/xmlpool/t_options.h
> @@ -55,11 +55,6 @@
>  DRI_CONF_SECTION_BEGIN \
>   DRI_CONF_DESC(en,gettext("Debugging"))
>  
> -#define DRI_CONF_PERFORMANCE_BOXES(def) \
> -DRI_CONF_OPT_BEGIN_B(performance_boxes, def) \
> -DRI_CONF_DESC(en,gettext("Show performance boxes")) \
> -DRI_CONF_OPT_END
> -
>  #define DRI_CONF_ALWAYS_FLUSH_BATCH(def) \
>  DRI_CONF_OPT_BEGIN_B(always_flush_batch, def) \
>  DRI_CONF_DESC(en,gettext("Enable flushing batchbuffer after each 
> draw call")) \
> 

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Re: [Mesa-dev] [PATCH 2/8] mesa: expose AMD_gpu_shader_int64

[Ian Romanick]

On 08/08/2018 07:12 PM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> because the closed driver exposes it.
> 
> It's equivalent to ARB_gpu_shader_int64.
> In this patch, I did everything the same as we do for ARB_gpu_shader_int64.

The closed driver only exposes this on core profile?  That's unexpected.

Either way, this patch is

Reviewed-by: Ian Romanick 

> ---
>  docs/relnotes/18.3.0.html   |   1 +
>  src/compiler/glsl/builtin_functions.cpp |   3 +-
>  src/compiler/glsl/builtin_types.cpp |   3 +-
>  src/compiler/glsl/glsl_lexer.ll |  18 +-
>  src/compiler/glsl/glsl_parser_extras.cpp|   1 +
>  src/compiler/glsl/glsl_parser_extras.h  |   5 +-
>  src/mapi/glapi/gen/AMD_gpu_shader_int64.xml | 239 
>  src/mapi/glapi/gen/gl_API.xml   |   2 +
>  src/mesa/main/extensions_table.h|   1 +
>  9 files changed, 261 insertions(+), 12 deletions(-)
>  create mode 100644 src/mapi/glapi/gen/AMD_gpu_shader_int64.xml
> 
> diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
> index ac2cc1e893b..840a336d41a 100644
> --- a/docs/relnotes/18.3.0.html
> +++ b/docs/relnotes/18.3.0.html
> @@ -45,20 +45,21 @@ TBD.
>  
>  
>  New features
>  
>  
>  Note: some of the new features are only available with certain drivers.
>  
>  
>  
>  GL_AMD_framebuffer_multisample_advanced on radeonsi.
> +GL_AMD_gpu_shader_int64 on i965, nvc0, radeonsi.
>  GL_EXT_window_rectangles on radeonsi.
>  
>  
>  Bug fixes
>  
>  
>  TBD
>  
>  
>  Changes
> diff --git a/src/compiler/glsl/builtin_functions.cpp 
> b/src/compiler/glsl/builtin_functions.cpp
> index 7119903795f..e37d96c4636 100644
> --- a/src/compiler/glsl/builtin_functions.cpp
> +++ b/src/compiler/glsl/builtin_functions.cpp
> @@ -522,21 +522,22 @@ supports_arb_fragment_shader_interlock(const 
> _mesa_glsl_parse_state *state)
>  static bool
>  shader_clock(const _mesa_glsl_parse_state *state)
>  {
> return state->ARB_shader_clock_enable;
>  }
>  
>  static bool
>  shader_clock_int64(const _mesa_glsl_parse_state *state)
>  {
> return state->ARB_shader_clock_enable &&
> -  state->ARB_gpu_shader_int64_enable;
> +  (state->ARB_gpu_shader_int64_enable ||
> +   state->AMD_gpu_shader_int64_enable);
>  }
>  
>  static bool
>  shader_storage_buffer_object(const _mesa_glsl_parse_state *state)
>  {
> return state->has_shader_storage_buffer_objects();
>  }
>  
>  static bool
>  shader_trinary_minmax(const _mesa_glsl_parse_state *state)
> diff --git a/src/compiler/glsl/builtin_types.cpp 
> b/src/compiler/glsl/builtin_types.cpp
> index 7a01cb48bc8..d2bcdd68138 100644
> --- a/src/compiler/glsl/builtin_types.cpp
> +++ b/src/compiler/glsl/builtin_types.cpp
> @@ -404,21 +404,22 @@ _mesa_glsl_initialize_types(struct 
> _mesa_glsl_parse_state *state)
>add_type(symbols, glsl_type::dmat3_type);
>add_type(symbols, glsl_type::dmat4_type);
>add_type(symbols, glsl_type::dmat2x3_type);
>add_type(symbols, glsl_type::dmat2x4_type);
>add_type(symbols, glsl_type::dmat3x2_type);
>add_type(symbols, glsl_type::dmat3x4_type);
>add_type(symbols, glsl_type::dmat4x2_type);
>add_type(symbols, glsl_type::dmat4x3_type);
> }
>  
> -   if (state->ARB_gpu_shader_int64_enable) {
> +   if (state->ARB_gpu_shader_int64_enable ||
> +   state->AMD_gpu_shader_int64_enable) {
>add_type(symbols, glsl_type::int64_t_type);
>add_type(symbols, glsl_type::i64vec2_type);
>add_type(symbols, glsl_type::i64vec3_type);
>add_type(symbols, glsl_type::i64vec4_type);
>  
>add_type(symbols, glsl_type::uint64_t_type);
>add_type(symbols, glsl_type::u64vec2_type);
>add_type(symbols, glsl_type::u64vec3_type);
>add_type(symbols, glsl_type::u64vec4_type);
> }
> diff --git a/src/compiler/glsl/glsl_lexer.ll b/src/compiler/glsl/glsl_lexer.ll
> index 87b64e09c16..74d4acca61f 100644
> --- a/src/compiler/glsl/glsl_lexer.ll
> +++ b/src/compiler/glsl/glsl_lexer.ll
> @@ -656,29 +656,29 @@ isampler2DRect  TYPE(140, 300, 140, 0, 
> glsl_type::isampler2DRect_type);
>  usampler2DRect   TYPE(140, 300, 140, 0, glsl_type::usampler2DRect_type);
>  isamplerBuffer   TYPE_WITH_ALT(140, 300, 140, 320, 
> yyextra->EXT_texture_buffer_enable || yyextra->OES_texture_buffer_enable, 
> glsl_type::isamplerBuffer_type);
>  usamplerBuffer   TYPE_WITH_ALT(140, 300, 140, 320, 
> yyextra->EXT_texture_buffer_enable || yyextra->OES_texture_buffer_enable, 
> glsl_type::usamplerBuffer_type);
>  
>  /* Additional reserved words in GLSL ES 3.00 */
>  resource KEYWORD(420, 300, 0, 0, RESOURCE);
>  sample   KEYWORD_WITH_ALT(400, 300, 400, 320, 
> yyextra->ARB_gpu_shader5_enable || 
> yyextra->OES_shader_multisample_interpolation_enable, SAMPLE);
>  subroutine   KEYWORD_WITH_ALT(400, 300, 400, 0, 
> yyextra->ARB_shader_subroutine_enable, SUBROUTINE);
>  
>  /* Additional words for 

Re: [Mesa-dev] [PATCH 1/8] mesa: expose ARB_post_depth_coverage in the Compatibility profile

[Ian Romanick]

On 08/08/2018 07:12 PM, Marek Olšák wrote:
> From: Marek Olšák 
> 
> It only contains GLSL changes.

This will probably need some other changes.  This extension requires the
use of the layout keyword, and we only enable that in early GLSL
versions when certain extensions are enabled.

> ---
>  src/mesa/main/extensions_table.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/main/extensions_table.h 
> b/src/mesa/main/extensions_table.h
> index bdba49d5380..b4c1b203c57 100644
> --- a/src/mesa/main/extensions_table.h
> +++ b/src/mesa/main/extensions_table.h
> @@ -92,21 +92,21 @@ EXT(ARB_multi_bind  , dummy_true
>  EXT(ARB_multi_draw_indirect , ARB_draw_indirect  
> , GLL, GLC,  x ,  x , 2012)
>  EXT(ARB_multisample , dummy_true 
> , GLL,  x ,  x ,  x , 1994)
>  EXT(ARB_multitexture, dummy_true 
> , GLL,  x ,  x ,  x , 1998)
>  EXT(ARB_occlusion_query , ARB_occlusion_query
> , GLL,  x ,  x ,  x , 2001)
>  EXT(ARB_occlusion_query2, ARB_occlusion_query2   
> , GLL, GLC,  x ,  x , 2003)
>  EXT(ARB_pipeline_statistics_query   , ARB_pipeline_statistics_query  
> , GLL, GLC,  x ,  x , 2014)
>  EXT(ARB_pixel_buffer_object , EXT_pixel_buffer_object
> , GLL, GLC,  x ,  x , 2004)
>  EXT(ARB_point_parameters, EXT_point_parameters   
> , GLL,  x ,  x ,  x , 1997)
>  EXT(ARB_point_sprite, ARB_point_sprite   
> , GLL, GLC,  x ,  x , 2003)
>  EXT(ARB_polygon_offset_clamp, ARB_polygon_offset_clamp   
> , GLL, GLC,  x ,  x , 2017)
> -EXT(ARB_post_depth_coverage , ARB_post_depth_coverage
> ,  x , GLC,  x ,  x,  2015)
> +EXT(ARB_post_depth_coverage , ARB_post_depth_coverage
> , GLL, GLC,  x ,  x,  2015)
>  EXT(ARB_program_interface_query , dummy_true 
> , GLL, GLC,  x ,  x , 2012)
>  EXT(ARB_provoking_vertex, EXT_provoking_vertex   
> , GLL, GLC,  x ,  x , 2009)
>  EXT(ARB_query_buffer_object , ARB_query_buffer_object
> , GLL, GLC,  x ,  x , 2013)
>  EXT(ARB_robust_buffer_access_behavior   , 
> ARB_robust_buffer_access_behavior  , GLL, GLC,  x ,  x , 2012)
>  EXT(ARB_robustness  , dummy_true 
> , GLL, GLC,  x ,  x , 2010)
>  EXT(ARB_sample_locations, ARB_sample_locations   
> , GLL, GLC,  x ,  x , 2015)
>  EXT(ARB_sample_shading  , ARB_sample_shading 
> , GLL, GLC,  x ,  x , 2009)
>  EXT(ARB_sampler_objects , dummy_true 
> , GLL, GLC,  x ,  x , 2009)
>  EXT(ARB_seamless_cube_map   , ARB_seamless_cube_map  
> , GLL, GLC,  x ,  x , 2009)
>  EXT(ARB_seamless_cubemap_per_texture, 
> AMD_seamless_cubemap_per_texture   , GLL, GLC,  x ,  x , 2013)
> 

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Re: [Mesa-dev] [PATCH v4 13/15] mesa/st/glsl_to_tgsi: Expose array live range tracking and merging

[Gert Wollny]

Am Mittwoch, den 15.08.2018, 12:58 +1000 schrieb Dave Airlie:
> On Wed, 6 Jun 2018 at 06:30, Gert Wollny 
> wrote:
> > 
> > This patch ties in the array split, merge, and interleave code.
> > 
> > shader-db changes in the TGSI code are:
> 
> This regresses
> tests/spec/glsl-1.50/execution/variable-indexing/gs-input-array-vec4-
> index-rd.shader_test
> 
> on virgl for me here.
I've send a patch that should fix this (tested on virgl + intel host
via vtest): https://patchwork.freedesktop.org/series/48275/

Best, 
Gert

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[Mesa-dev] [PATCH] mesa/st: fix array indices off-by-one error in remapping

[Gert Wollny]

When moving the array sizes from the old list to the new one it was
not taken into account that the array indices start with one, but the
array_size array started at index zero, which resulted in incorrect array
sizes when arrays were merged. Correct this by copying the array_size
values of the retained arrays with an offset of -1.

Also fix whitespaces for the replaced lines.

Fixes: d8c2119f9b0b257a23ceb398f6d0d78da916417e
  mesa/st/glsl_to_tgsi: Expose array live range tracking and merging
Signed-off-by: Gert Wollny 
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp |  2 +-
 src/mesa/state_tracker/st_glsl_to_tgsi_array_merge.cpp | 10 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 2b9183abbb..bbb28b0d7b 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -5601,7 +5601,7 @@ glsl_to_tgsi_visitor::merge_registers(void)
if (this->next_array > 0) {
   arr_live_ranges = new array_live_range[this->next_array];
   for (unsigned i = 0; i < this->next_array; ++i)
-arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i+1]);
+ arr_live_ranges[i] = array_live_range(i+1, this->array_sizes[i]);
}
 
 
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi_array_merge.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi_array_merge.cpp
index f95b1fac7b..1431824369 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi_array_merge.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi_array_merge.cpp
@@ -587,10 +587,10 @@ int remap_arrays(int narrays, unsigned *array_sizes,
/* re-calculate arrays */
 #if __cplusplus < 201402L
int *idx_map = new int[narrays + 1];
-   unsigned *old_sizes = new unsigned[narrays + 1];
+   unsigned *old_sizes = new unsigned[narrays];
 #else
unique_ptr idx_map = make_unique(narrays + 1);
-   unique_ptr old_sizes = make_unique(narrays + 1);
+   unique_ptr old_sizes = make_unique(narrays);
 #endif
 
memcpy(_sizes[0], _sizes[0], sizeof(unsigned) * narrays);
@@ -599,9 +599,9 @@ int remap_arrays(int narrays, unsigned *array_sizes,
int new_narrays = 0;
for (int i = 1; i <= narrays; ++i) {
   if (!map[i].is_valid()) {
-++new_narrays;
-idx_map[i] = new_narrays;
-array_sizes[new_narrays] = old_sizes[i];
+ ++new_narrays;
+ array_sizes[new_narrays-1] = old_sizes[i-1];
+ idx_map[i] = new_narrays;
   }
}
 
-- 
2.16.4

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Re: [Mesa-dev] [PATCH 2/2] virgl: report actual max-texture sizes

[Jakob Bornecrantz]

Reviewed-by: Jakob Bornecrantz 

On Tue, Aug 14, 2018 at 2:02 PM, Erik Faye-Lund
 wrote:
> Instead of doing conservative guesses, we should report the max levels
> based on the max sizes we get from GL on the host.
>
> Signed-off-by: Erik Faye-Lund 
> ---
>  src/gallium/drivers/virgl/virgl_hw.h | 3 +++
>  src/gallium/drivers/virgl/virgl_screen.c | 7 +++
>  2 files changed, 10 insertions(+)
>
> diff --git a/src/gallium/drivers/virgl/virgl_hw.h 
> b/src/gallium/drivers/virgl/virgl_hw.h
> index b56f554b00..787452d328 100644
> --- a/src/gallium/drivers/virgl/virgl_hw.h
> +++ b/src/gallium/drivers/virgl/virgl_hw.h
> @@ -347,6 +347,9 @@ struct virgl_caps_v2 {
>  uint32_t max_compute_shared_memory_size;
>  uint32_t max_compute_grid_size[3];
>  uint32_t max_compute_block_size[3];
> +uint32_t max_texture_2d_size;
> +uint32_t max_texture_3d_size;
> +uint32_t max_texture_cube_size;
>  };
>
>  union virgl_caps {
> diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
> b/src/gallium/drivers/virgl/virgl_screen.c
> index 0ac976acbd..86063c66aa 100644
> --- a/src/gallium/drivers/virgl/virgl_screen.c
> +++ b/src/gallium/drivers/virgl/virgl_screen.c
> @@ -24,6 +24,7 @@
>  #include "util/u_format.h"
>  #include "util/u_format_s3tc.h"
>  #include "util/u_video.h"
> +#include "util/u_math.h"
>  #include "util/os_time.h"
>  #include "pipe/p_defines.h"
>  #include "pipe/p_screen.h"
> @@ -72,10 +73,16 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
> param)
> case PIPE_CAP_TEXTURE_SWIZZLE:
>return 1;
> case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
> +  if (vscreen->caps.caps.v2.max_texture_2d_size)
> + return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_2d_size);
>return 15; /* 16K x 16K */
> case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
> +  if (vscreen->caps.caps.v2.max_texture_3d_size)
> + return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
>return 9; /* 256 x 256 x 256 */
> case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
> +  if (vscreen->caps.caps.v2.max_texture_cube_size)
> + return 1 + 
> util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
>return 13; /* 4K x 4K */
> case PIPE_CAP_BLEND_EQUATION_SEPARATE:
>return 1;
> --
> 2.17.1
>
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[Mesa-dev] [Bug 105371] r600_shader_from_tgsi - GPR limit exceeded - shader requires 360 registers

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105371

--- Comment #11 from MWATTT  ---
Hello,

Many thanks for this series. It fix a lot of bugs. Animated leaders in Civ5 and
Civ6 now works fine. It also solves a lot of Minecraft shaderpack's issues.
Dolphin-emu's ubershader still however cause problems (160 registers). I will
create a bug report with an apitrace for that.

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Re: [Mesa-dev] [PATCH 1/2] virgl: do not use SP_MAX_TEXTURE_*_LEVELS defines

[Jakob Bornecrantz]

Reviewed-by: Jakob Bornecrantz 

On Tue, Aug 14, 2018 at 2:02 PM, Erik Faye-Lund
 wrote:
> These macro-names are also used for softpipe, so let's avoid confusion
> by avoiding them. Besides, they are just used in one place in virgl, so
> let's just inline them into the place they are used instead.
>
> While we're at it, fixup an error in the comment for the 3D version.
> Mesa subtracts computes max-size by doing by 2^(n-1), which means this
> should be 256 cubed, not 512 cubed. The other comments are correct.
>
> Signed-off-by: Erik Faye-Lund 
> ---
>  src/gallium/drivers/virgl/virgl_screen.c | 10 +++---
>  1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
> b/src/gallium/drivers/virgl/virgl_screen.c
> index 87ce3b7355..0ac976acbd 100644
> --- a/src/gallium/drivers/virgl/virgl_screen.c
> +++ b/src/gallium/drivers/virgl/virgl_screen.c
> @@ -35,10 +35,6 @@
>  #include "virgl_public.h"
>  #include "virgl_context.h"
>
> -#define SP_MAX_TEXTURE_2D_LEVELS 15  /* 16K x 16K */
> -#define SP_MAX_TEXTURE_3D_LEVELS 9   /* 512 x 512 x 512 */
> -#define SP_MAX_TEXTURE_CUBE_LEVELS 13  /* 4K x 4K */
> -
>  static const char *
>  virgl_get_vendor(struct pipe_screen *screen)
>  {
> @@ -76,11 +72,11 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
> param)
> case PIPE_CAP_TEXTURE_SWIZZLE:
>return 1;
> case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
> -  return SP_MAX_TEXTURE_2D_LEVELS;
> +  return 15; /* 16K x 16K */
> case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
> -  return SP_MAX_TEXTURE_3D_LEVELS;
> +  return 9; /* 256 x 256 x 256 */
> case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
> -  return SP_MAX_TEXTURE_CUBE_LEVELS;
> +  return 13; /* 4K x 4K */
> case PIPE_CAP_BLEND_EQUATION_SEPARATE:
>return 1;
> case PIPE_CAP_INDEP_BLEND_ENABLE:
> --
> 2.17.1
>
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Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: Fix missing Android platform define.

[Dylan Baker]

Quoting Bas Nieuwenhuizen (2018-08-15 09:34:41)
> On Wed, Aug 15, 2018 at 6:08 PM, Dylan Baker  wrote:
> > Quoting Bas Nieuwenhuizen (2018-08-09 17:27:46)
> >> CC: 
> >> ---
> >>  src/amd/vulkan/Android.mk  | 2 ++
> >>  src/amd/vulkan/Makefile.am | 2 +-
> >>  2 files changed, 3 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/src/amd/vulkan/Android.mk b/src/amd/vulkan/Android.mk
> >> index cee3744f40b..51b03561fa7 100644
> >> --- a/src/amd/vulkan/Android.mk
> >> +++ b/src/amd/vulkan/Android.mk
> >> @@ -62,6 +62,7 @@ LOCAL_SRC_FILES := \
> >> $(VULKAN_FILES)
> >>
> >>  LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU   # instructs LLVM to declare 
> >> LLVMInitializeAMDGPU* functions
> >> +LOCAL_CFLAGS += -DVK_USE_PLATFORM_ANDROID_KHR
> >>
> >>  $(call mesa-build-with-llvm)
> >>
> >> @@ -140,6 +141,7 @@ LOCAL_SRC_FILES := \
> >> $(VULKAN_ANDROID_FILES)
> >>
> >>  LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU   # instructs LLVM to declare 
> >> LLVMInitializeAMDGPU* functions
> >> +LOCAL_CFLAGS += -DVK_USE_PLATFORM_ANDROID_KHR
> >>
> >>  $(call mesa-build-with-llvm)
> >>
> >> diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
> >> index e7ccc58a28e..e28f032cbee 100644
> >> --- a/src/amd/vulkan/Makefile.am
> >> +++ b/src/amd/vulkan/Makefile.am
> >> @@ -124,7 +124,7 @@ VULKAN_LIB_DEPS += \
> >>  endif
> >>
> >>  if HAVE_PLATFORM_ANDROID
> >> -AM_CPPFLAGS += $(ANDROID_CPPFLAGS)
> >> +AM_CPPFLAGS += $(ANDROID_CPPFLAGS) -DVK_USE_PLATFORM_ANDROID_KHR
> >>  AM_CFLAGS += $(ANDROID_CFLAGS)
> >>  VULKAN_LIB_DEPS += $(ANDROID_LIBS)
> >>  VULKAN_SOURCES += $(VULKAN_ANDROID_FILES)
> >> --
> >> 2.18.0
> >>
> >
> > Hi Bas,
> >
> > I went ahead and pulled this into the staging/18.1 branch, we don't have
> > android.mk support for radv in 18.1, so I only pulled in the autotools part.
> > Please let me know if you're happy with that or not.
> 
> That works for me, thanks!
> 
> >
> > Dylan

Cool, thanks!


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Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: Fix missing Android platform define.

[Bas Nieuwenhuizen]

On Wed, Aug 15, 2018 at 6:08 PM, Dylan Baker  wrote:
> Quoting Bas Nieuwenhuizen (2018-08-09 17:27:46)
>> CC: 
>> ---
>>  src/amd/vulkan/Android.mk  | 2 ++
>>  src/amd/vulkan/Makefile.am | 2 +-
>>  2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/amd/vulkan/Android.mk b/src/amd/vulkan/Android.mk
>> index cee3744f40b..51b03561fa7 100644
>> --- a/src/amd/vulkan/Android.mk
>> +++ b/src/amd/vulkan/Android.mk
>> @@ -62,6 +62,7 @@ LOCAL_SRC_FILES := \
>> $(VULKAN_FILES)
>>
>>  LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU   # instructs LLVM to declare 
>> LLVMInitializeAMDGPU* functions
>> +LOCAL_CFLAGS += -DVK_USE_PLATFORM_ANDROID_KHR
>>
>>  $(call mesa-build-with-llvm)
>>
>> @@ -140,6 +141,7 @@ LOCAL_SRC_FILES := \
>> $(VULKAN_ANDROID_FILES)
>>
>>  LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU   # instructs LLVM to declare 
>> LLVMInitializeAMDGPU* functions
>> +LOCAL_CFLAGS += -DVK_USE_PLATFORM_ANDROID_KHR
>>
>>  $(call mesa-build-with-llvm)
>>
>> diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
>> index e7ccc58a28e..e28f032cbee 100644
>> --- a/src/amd/vulkan/Makefile.am
>> +++ b/src/amd/vulkan/Makefile.am
>> @@ -124,7 +124,7 @@ VULKAN_LIB_DEPS += \
>>  endif
>>
>>  if HAVE_PLATFORM_ANDROID
>> -AM_CPPFLAGS += $(ANDROID_CPPFLAGS)
>> +AM_CPPFLAGS += $(ANDROID_CPPFLAGS) -DVK_USE_PLATFORM_ANDROID_KHR
>>  AM_CFLAGS += $(ANDROID_CFLAGS)
>>  VULKAN_LIB_DEPS += $(ANDROID_LIBS)
>>  VULKAN_SOURCES += $(VULKAN_ANDROID_FILES)
>> --
>> 2.18.0
>>
>
> Hi Bas,
>
> I went ahead and pulled this into the staging/18.1 branch, we don't have
> android.mk support for radv in 18.1, so I only pulled in the autotools part.
> Please let me know if you're happy with that or not.

That works for me, thanks!

>
> Dylan
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[Mesa-dev] [PATCH v2 2/5] meson: use python3 module to find python3

[Dylan Baker]

This handy helper is nice for OSes that are not linux or BSD like (mac
and windows) as it knows how to find python3 in odd places.
---
 meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 5dc9b45eb42..c8bac35659f 100644
--- a/meson.build
+++ b/meson.build
@@ -697,7 +697,7 @@ if with_platform_haiku
   pre_args += '-DHAVE_HAIKU_PLATFORM'
 endif
 
-prog_python = find_program('python3')
+prog_python = import('python3').find_python()
 has_mako = run_command(prog_python, '-c', 'import mako; assert 
mako.__version__ >= "0.8.0"')
 if has_mako.returncode() != 0
   error('Python (3.x) mako module >= 0.8.0 required to build mesa.')
-- 
2.18.0

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[Mesa-dev] [PATCH v2 1/5] meson: Ensure that mako is >= 0.8.0

[Dylan Baker]

It's what autotools has required for a long time.
---
 meson.build | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/meson.build b/meson.build
index 7436164946b..5dc9b45eb42 100644
--- a/meson.build
+++ b/meson.build
@@ -698,9 +698,9 @@ if with_platform_haiku
 endif
 
 prog_python = find_program('python3')
-has_mako = run_command(prog_python, '-c', 'import mako')
+has_mako = run_command(prog_python, '-c', 'import mako; assert 
mako.__version__ >= "0.8.0"')
 if has_mako.returncode() != 0
-  error('Python (3.x) mako module required to build mesa.')
+  error('Python (3.x) mako module >= 0.8.0 required to build mesa.')
 endif
 
 if cc.get_id() == 'gcc' and cc.version().version_compare('< 4.4.6')
-- 
2.18.0

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[Mesa-dev] [PATCH v2 5/5] scons: Check for mako 0.8.0

[Dylan Baker]

v2: - Use distutils to do the version checking

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107565
---
 scons/gallium.py | 13 +
 1 file changed, 13 insertions(+)

diff --git a/scons/gallium.py b/scons/gallium.py
index 659da72c1c3..aa7201a9715 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -29,6 +29,7 @@ Frontend-tool for Gallium3D architecture.
 # SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #
 
+from __future__ import print_function
 
 import distutils.version
 import os
@@ -677,6 +678,18 @@ def generate(env):
 env.PkgCheckModules('XF86VIDMODE', ['xxf86vm'])
 env.PkgCheckModules('DRM', ['libdrm >= 2.4.75'])
 
+if not os.path.exists("src/util/format_srgb.c"):
+print("Checking for Python Mako module (>= 0.8.0)... ", end='')
+try:
+import mako
+except ImportError:
+print("no")
+exit(1)
+if distutils.version.StrictVersion(mako.__version__) < 
distutils.version.StrictVersion('0.8.0'):
+print("no")
+exit(1)
+print("yes")
+
 if env['x11']:
 env.Append(CPPPATH = env['X11_CPPPATH'])
 
-- 
2.18.0

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[Mesa-dev] [PATCH v2 3/5] configure: Enforce python 2.7.x

[Dylan Baker]

We don't want to support older versions of python 2 anymore, and we
don't support python 3.x in autotools currently.
---
 configure.ac | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/configure.ac b/configure.ac
index c2155a541b0..78672734d06 100644
--- a/configure.ac
+++ b/configure.ac
@@ -162,6 +162,13 @@ if test -z "$PYTHON2"; then
 AC_MSG_ERROR([Python not found - unable to generate sources])
 fi
 else
+PYTHON_VERSION=`$PYTHON2 --version |& awk '{print $2}'`  dnl Yes, python2 
prints it's version to stderr
+PYTHON_MAJOR=`echo $PYTHON_VERSION | cut -d . -f 1`
+PYTHON_MINOR=`echo $PYTHON_VERSION | cut -d . -f 2`
+if test $PYTHON_MAJOR -ne 2 -o $PYTHON_MINOR -ne 7; then
+AC_MSG_ERROR([Python version 2.7.x not found - unable to generate 
sources])
+fi
+
 if test "x$acv_mako_found" = xno; then
 if test ! -f "$srcdir/src/mesa/main/format_unpack.c"; then
 AC_MSG_ERROR([Python mako module v$PYTHON_MAKO_REQUIRED or higher 
not found])
-- 
2.18.0

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[Mesa-dev] [PATCH v2 4/5] scons: Require python 2.7

[Dylan Baker]

less than 2.7 is not supported.

v2: - Remove check for python >= 2.0, since we've already enforced 2.7
---
 SConstruct   | 1 +
 scons/gallium.py | 4 
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/SConstruct b/SConstruct
index 6e034fb968f..51dc301a9a8 100644
--- a/SConstruct
+++ b/SConstruct
@@ -31,6 +31,7 @@ import common
 # Minimal scons version
 
 EnsureSConsVersion(2, 4)
+EnsurePythonVersion(2, 7)
 
 
 ###
diff --git a/scons/gallium.py b/scons/gallium.py
index 92a762a0c1e..659da72c1c3 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -221,10 +221,6 @@ def generate(env):
 env['suncc'] = env['platform'] == 'sunos' and os.path.basename(env['CC']) 
== 'cc'
 env['icc'] = 'icc' == os.path.basename(env['CC'])
 
-if env['msvc'] and env['toolchain'] == 'default' and env['machine'] == 
'x86_64':
-# MSVC x64 support is broken in earlier versions of scons
-env.EnsurePythonVersion(2, 0)
-
 # shortcuts
 machine = env['machine']
 platform = env['platform']
-- 
2.18.0

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[Mesa-dev] [PATCH 1/3] freedreno: Fix warnings

[Kristian H. Kristensen]

From: "Kristian H. Kristensen" 

Signed-off-by: Kristian H. Kristensen 
---
 src/gallium/drivers/freedreno/a5xx/fd5_compute.c   | 2 +-
 src/gallium/drivers/freedreno/freedreno_resource.c | 8 
 src/gallium/drivers/freedreno/ir3/ir3.h| 8 ++--
 src/gallium/drivers/freedreno/ir3/ir3_cmdline.c| 2 +-
 src/gallium/drivers/freedreno/ir3/ir3_shader.h | 4 +---
 5 files changed, 9 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c 
b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
index 8e2c228e90..66ed7a4af5 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
@@ -181,7 +181,7 @@ static void
 fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
 {
struct fd5_compute_stateobj *so = ctx->compute;
-   struct ir3_shader_key key = {0};
+   struct ir3_shader_key key = {};
struct ir3_shader_variant *v;
struct fd_ringbuffer *ring = ctx->batch->draw;
unsigned i, nglobal = 0;
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c 
b/src/gallium/drivers/freedreno/freedreno_resource.c
index 3fbf50003e..f882cf5a8b 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -211,7 +211,7 @@ fd_try_shadow_resource(struct fd_context *ctx, struct 
fd_resource *rsc,
 
mtx_unlock(>screen->lock);
 
-   struct pipe_blit_info blit = {0};
+   struct pipe_blit_info blit = {};
blit.dst.resource = prsc;
blit.dst.format   = prsc->format;
blit.src.resource = pshadow;
@@ -305,7 +305,7 @@ static void
 fd_blit_from_staging(struct fd_context *ctx, struct fd_transfer *trans)
 {
struct pipe_resource *dst = trans->base.resource;
-   struct pipe_blit_info blit = {0};
+   struct pipe_blit_info blit = {};
 
blit.dst.resource = dst;
blit.dst.format   = dst->format;
@@ -325,7 +325,7 @@ static void
 fd_blit_to_staging(struct fd_context *ctx, struct fd_transfer *trans)
 {
struct pipe_resource *src = trans->base.resource;
-   struct pipe_blit_info blit = {0};
+   struct pipe_blit_info blit = {};
 
blit.src.resource = src;
blit.src.format   = src->format;
@@ -372,7 +372,7 @@ flush_resource(struct fd_context *ctx, struct fd_resource 
*rsc, unsigned usage)
fd_batch_reference(_batch, rsc->write_batch);
 
if (usage & PIPE_TRANSFER_WRITE) {
-   struct fd_batch *batch, *batches[32] = {0};
+   struct fd_batch *batch, *batches[32] = {};
uint32_t batch_mask;
 
/* This is a bit awkward, probably a fd_batch_flush_locked()
diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h 
b/src/gallium/drivers/freedreno/ir3/ir3.h
index 8bac91660b..63215cefc9 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3.h
@@ -445,14 +445,12 @@ struct ir3 {
 #endif
 };
 
-typedef struct nir_register nir_register;
-
 struct ir3_array {
struct list_head node;
unsigned length;
unsigned id;
 
-   nir_register *r;
+   struct nir_register *r;
 
/* To avoid array write's from getting DCE'd, keep track of the
 * most recent write.  Any array access depends on the most
@@ -470,13 +468,11 @@ struct ir3_array {
 
 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
 
-typedef struct nir_block nir_block;
-
 struct ir3_block {
struct list_head node;
struct ir3 *shader;
 
-   const nir_block *nblock;
+   const struct nir_block *nblock;
 
struct list_head instr_list;  /* list of ir3_instruction */
 
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c 
b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index 23d5006352..b41c32d375 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -379,7 +379,7 @@ int main(int argc, char **argv)
 
while (n < argc) {
char *filename = argv[n];
-   char *ext = rindex(filename, '.');
+   char *ext = strrchr(filename, '.');
 
if (strcmp(ext, ".tgsi") == 0) {
if (num_files != 0)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h 
b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index 507e89c473..288e9fa4e7 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -345,8 +345,6 @@ struct ir3_shader_variant {
struct ir3_shader *shader;
 };
 
-typedef struct nir_shader nir_shader;
-
 struct ir3_shader {
enum shader_t type;
 
@@ -359,7 +357,7 @@ struct ir3_shader {
 
struct ir3_compiler *compiler;
 
-   nir_shader *nir;
+   struct nir_shader *nir;
struct pipe_stream_output_info stream_output;
 
struct ir3_shader_variant *variants;
-- 

Re: [Mesa-dev] [PATCH] Revert "intel/nir: Call nir_lower_io_to_scalar_early"

[Jason Ekstrand]

On Tue, Aug 14, 2018 at 7:25 PM Timothy Arceri 
wrote:

> On 09/08/18 05:05, Jason Ekstrand wrote:
> > Commit 4434591bf56a6b0 caused substantially more URB messages in
> > geometry and tessellation shaders.  Before we can really enable this
> > sort of optimization,  We either need some way of combining them back
> > together into vectors or we need to do cross-stage vector element
> > elimination without splitting everything into scalars.
>
> You should be calling:
>
> nir_compact_varyings() after remove_unused_varyings this should do most
> of what you want.
>

Does that turn things back into vectors?  The problem we're hitting is not
that things aren't compacted, it's that we want to read/write whole vectors
at a time as much as possible.  Just reverting the patch isn't quite the
proper solution because we want to be able to compact things and it would
be nice if we could load two variables at a time if they're packed
side-by-side in one vec4.  However, it does solve the perf regression for
now.

--Jason
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Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: Fix missing Android platform define.

[Dylan Baker]

Quoting Bas Nieuwenhuizen (2018-08-09 17:27:46)
> CC: 
> ---
>  src/amd/vulkan/Android.mk  | 2 ++
>  src/amd/vulkan/Makefile.am | 2 +-
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/src/amd/vulkan/Android.mk b/src/amd/vulkan/Android.mk
> index cee3744f40b..51b03561fa7 100644
> --- a/src/amd/vulkan/Android.mk
> +++ b/src/amd/vulkan/Android.mk
> @@ -62,6 +62,7 @@ LOCAL_SRC_FILES := \
> $(VULKAN_FILES)
>  
>  LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU   # instructs LLVM to declare 
> LLVMInitializeAMDGPU* functions
> +LOCAL_CFLAGS += -DVK_USE_PLATFORM_ANDROID_KHR
>  
>  $(call mesa-build-with-llvm)
>  
> @@ -140,6 +141,7 @@ LOCAL_SRC_FILES := \
> $(VULKAN_ANDROID_FILES)
>  
>  LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU   # instructs LLVM to declare 
> LLVMInitializeAMDGPU* functions
> +LOCAL_CFLAGS += -DVK_USE_PLATFORM_ANDROID_KHR
>  
>  $(call mesa-build-with-llvm)
>  
> diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
> index e7ccc58a28e..e28f032cbee 100644
> --- a/src/amd/vulkan/Makefile.am
> +++ b/src/amd/vulkan/Makefile.am
> @@ -124,7 +124,7 @@ VULKAN_LIB_DEPS += \
>  endif
>  
>  if HAVE_PLATFORM_ANDROID
> -AM_CPPFLAGS += $(ANDROID_CPPFLAGS)
> +AM_CPPFLAGS += $(ANDROID_CPPFLAGS) -DVK_USE_PLATFORM_ANDROID_KHR
>  AM_CFLAGS += $(ANDROID_CFLAGS)
>  VULKAN_LIB_DEPS += $(ANDROID_LIBS)
>  VULKAN_SOURCES += $(VULKAN_ANDROID_FILES)
> -- 
> 2.18.0
> 

Hi Bas,

I went ahead and pulled this into the staging/18.1 branch, we don't have
android.mk support for radv in 18.1, so I only pulled in the autotools part.
Please let me know if you're happy with that or not.

Dylan


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Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

[andrey simiklit]

Hi all,

This workaround just helps me to avoid the graphical corruption on SNB but
I not sure is it good idea.

Regards,
Andrii.

On Wed, Aug 15, 2018 at 6:20 PM,  wrote:

> From: Andrii Simiklit 
>
> When the SVBI Payload Enable is false I guess the register R1.4
> which contains the Maximum Streamed Vertex Buffer Index is filled by zero
> and GS stops to write transform feedback when the transform feedback
> is not active.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107579
> Signed-off-by: Andrii Simiklit 
> ---
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
> b/src/mesa/drivers/dri/i965/genX_state_upload.c
> index ea5ad55..0f82500 100644
> --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> @@ -2806,7 +2806,7 @@ genX(upload_gs_state)(struct brw_context *brw)
>  #if GEN_GEN < 7
>   gs.SOStatisticsEnable = true;
>   if (gs_prog->info.has_transform_feedback_varyings)
> -gs.SVBIPayloadEnable = true;
> +gs.SVBIPayloadEnable = _mesa_is_xfb_active_and_unpaused(ctx);
>
>   /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled
> as it
>* was previously done for gen6.
> --
> 2.7.4
>
>
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[Mesa-dev] [Bug 107509] corrupted Box in top Right corner in some games

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107509

Michel Dänzer  changed:

   What|Removed |Added

   Assignee|mesa-dev@lists.freedesktop. |dri-devel@lists.freedesktop
   |org |.org
 QA Contact|mesa-dev@lists.freedesktop. |dri-devel@lists.freedesktop
   |org |.org
  Component|Other   |Drivers/Gallium/radeonsi

--- Comment #4 from Michel Dänzer  ---
Is it the same using the amdgpu kernel driver instead of radeon?

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[Mesa-dev] [Bug 107509] corrupted Box in top Right corner in some games

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107509

Michel Dänzer  changed:

   What|Removed |Added

 Attachment #140998|text/x-log  |text/plain
  mime type||

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[Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

[asimiklit . work]

From: Andrii Simiklit 

When the SVBI Payload Enable is false I guess the register R1.4
which contains the Maximum Streamed Vertex Buffer Index is filled by zero
and GS stops to write transform feedback when the transform feedback 
is not active.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107579
Signed-off-by: Andrii Simiklit 
---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index ea5ad55..0f82500 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2806,7 +2806,7 @@ genX(upload_gs_state)(struct brw_context *brw)
 #if GEN_GEN < 7
  gs.SOStatisticsEnable = true;
  if (gs_prog->info.has_transform_feedback_varyings)
-gs.SVBIPayloadEnable = true;
+gs.SVBIPayloadEnable = _mesa_is_xfb_active_and_unpaused(ctx);
 
  /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
   * was previously done for gen6.
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.

[Jason Ekstrand]

On August 15, 2018 09:28:36 Bas Nieuwenhuizen  wrote:


On Wed, Aug 15, 2018 at 11:49 AM, Jason Ekstrand  wrote:

On Tue, Aug 14, 2018 at 7:20 AM Samuel Pitoiset 
wrote:


Reviewed-by: Samuel Pitoiset 

On 7/23/18 4:24 PM, Bas Nieuwenhuizen wrote:

Behavior wrt firstInstance got changed, and a divisor of 0 has been
disallowed.

The new version of the ext got published in specification 1.1.81.
---
src/amd/vulkan/radv_extensions.py | 2 +-
src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_extensions.py
b/src/amd/vulkan/radv_extensions.py
index a5fbffac33b..d02042e5647 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -104,7 +104,7 @@ EXTENSIONS = [
Extension('VK_EXT_sampler_filter_minmax', 1,
'device->rad_info.chip_class >= CIK'),
Extension('VK_EXT_shader_viewport_index_layer',   1, True),
Extension('VK_EXT_shader_stencil_export', 1, True),
-Extension('VK_EXT_vertex_attribute_divisor',  1, True),
+Extension('VK_EXT_vertex_attribute_divisor',  2, True),
Extension('VK_AMD_draw_indirect_count',   1, True),
Extension('VK_AMD_gcn_shader',1, True),
Extension('VK_AMD_rasterization_order',   1,
'device->has_out_of_order_rast'),
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index c7d772fa652..d12ef09c9f3 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1984,8 +1984,7 @@ handle_vs_input_decl(struct radv_shader_context
*ctx,
uint32_t divisor =
ctx->options->key.vs.instance_rate_divisors[attrib_index];

if (divisor) {
- buffer_index =
LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
-
ctx->abi.start_instance, "");
+ buffer_index = ctx->abi.instance_id;

if (divisor != 1) {
buffer_index =
LLVMBuildUDiv(ctx->ac.builder, buffer_index,
@@ -2000,8 +1999,10 @@ handle_vs_input_decl(struct radv_shader_context
*ctx,
MAX2(1,
ctx->shader_info->vs.vgpr_comp_cnt);
}
} else {
- buffer_index = ctx->ac.i32_0;
+ unreachable("Invalid vertex attribute
divisor of 0.");



You'll want to leave this alone.  zero is coming back...  Yeah, I know it's
annoying but I'm really trying to get this settled out as quickly as
possible.  In the mean time, reports are that zero is useful for some DXVK
apps so it's best to just silently support it rather than breaking stuff.


Is the behavior of zero going to be the same as it was in version 1?


Almost. There base instance will be added in but instance is never 
incremented beyond that. Look at Khronos MR 2771.









}
+
+ buffer_index = LLVMBuildAdd(ctx->ac.builder,
ctx->abi.start_instance, buffer_index, "");
} else
buffer_index = LLVMBuildAdd(ctx->ac.builder,
ctx->abi.vertex_id,
ctx->abi.base_vertex,
"");

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[Mesa-dev] [PATCH v4 2/4] gm107/ir: add support for OP_XMAD on GM107+

[Rhys Perry]

v4: make the immediate field 16 bits

Signed-off-by: Rhys Perry 
---
 .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 65 ++
 .../nouveau/codegen/nv50_ir_target_gm107.cpp   |  6 +-
 .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  1 +
 3 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 5e8c22cd54..9138a2717d 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -156,6 +156,7 @@ private:
void emitIMUL();
void emitIMAD();
void emitISCADD();
+   void emitXMAD();
void emitIMNMX();
void emitICMP();
void emitISET();
@@ -1893,6 +1894,67 @@ CodeEmitterGM107::emitISCADD()
emitGPR (0x00, insn->def(0));
 }
 
+void
+CodeEmitterGM107::emitXMAD()
+{
+   assert(insn->src(0).getFile() == FILE_GPR);
+
+   bool constbuf = false;
+   bool psl_mrg = true;
+   bool immediate = false;
+   if (insn->src(2).getFile() == FILE_MEMORY_CONST) {
+  assert(insn->src(1).getFile() == FILE_GPR);
+  constbuf = true;
+  psl_mrg = false;
+  emitInsn(0x5100);
+  emitGPR(0x27, insn->src(1));
+  emitCBUF(0x22, -1, 0x14, 16, 2, insn->src(2));
+   } else if (insn->src(1).getFile() == FILE_MEMORY_CONST) {
+  assert(insn->src(2).getFile() == FILE_GPR);
+  constbuf = true;
+  emitInsn(0x4e00);
+  emitCBUF(0x22, -1, 0x14, 16, 2, insn->src(1));
+  emitGPR(0x27, insn->src(2));
+   } else if (insn->src(1).getFile() == FILE_IMMEDIATE) {
+  assert(insn->src(2).getFile() == FILE_GPR);
+  assert(!(insn->subOp & NV50_IR_SUBOP_XMAD_H1(1)));
+  immediate = false;
+  emitInsn(0x3600);
+  emitIMMD(0x14, 16, insn->src(1));
+  emitGPR(0x27, insn->src(2));
+   } else {
+  assert(insn->src(1).getFile() == FILE_GPR);
+  assert(insn->src(2).getFile() == FILE_GPR);
+  emitInsn(0x5b00);
+  emitGPR(0x14, insn->src(1));
+  emitGPR(0x27, insn->src(2));
+   }
+
+   if (psl_mrg)
+  emitField(constbuf ? 0x37 : 0x24, 2, insn->subOp & 0x3);
+
+   unsigned cmode = (insn->subOp & NV50_IR_SUBOP_XMAD_CMODE_MASK);
+   cmode >>= NV50_IR_SUBOP_XMAD_CMODE_SHIFT;
+   emitField(0x32, constbuf ? 2 : 3, cmode);
+
+   emitX(constbuf ? 0x36 : 0x26);
+   emitCC(0x2f);
+
+   emitGPR(0x0, insn->def(0));
+   emitGPR(0x8, insn->src(0));
+
+   // source flags
+   if (isSignedType(insn->sType)) {
+  uint16_t h1s = insn->subOp & NV50_IR_SUBOP_XMAD_H1_MASK;
+  emitField(0x30, 2, h1s >> NV50_IR_SUBOP_XMAD_H1_SHIFT);
+   }
+   emitField(0x35, 1, insn->subOp & NV50_IR_SUBOP_XMAD_H1(0) ? 1 : 0);
+   if (!immediate) {
+  bool h1 = insn->subOp & NV50_IR_SUBOP_XMAD_H1(1);
+  emitField(constbuf ? 0x34 : 0x23, 1, h1);
+   }
+}
+
 void
 CodeEmitterGM107::emitIMNMX()
 {
@@ -3267,6 +3329,9 @@ CodeEmitterGM107::emitInstruction(Instruction *i)
case OP_SHLADD:
   emitISCADD();
   break;
+   case OP_XMAD:
+  emitXMAD();
+  break;
case OP_MIN:
case OP_MAX:
   if (isFloatType(insn->dType)) {
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
index 2dd12322a8..de07ad1de8 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
@@ -59,12 +59,15 @@ TargetGM107::isOpSupported(operation op, DataType ty) const
case OP_POW:
case OP_DIV:
case OP_MOD:
-   case OP_XMAD:
   return false;
case OP_SQRT:
   if (ty == TYPE_F64)
  return false;
   return chipset >= NVISA_GM200_CHIPSET;
+   case OP_XMAD:
+  if (isFloatType(ty))
+ return false;
+  break;
default:
   break;
}
@@ -235,6 +238,7 @@ TargetGM107::getLatency(const Instruction *insn) const
case OP_SUB:
case OP_VOTE:
case OP_XOR:
+   case OP_XMAD:
   if (insn->dType != TYPE_F64)
  return 6;
   break;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 8e04069536..60134b445d 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -162,6 +162,7 @@ static const struct opProperties _initPropsGM107[] = {
{ OP_SUSTP,   0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
{ OP_SUREDB,  0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
{ OP_SUREDP,  0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
+   { OP_XMAD,0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
 };
 
 void TargetNVC0::initProps(const struct opProperties *props, int size)
-- 
2.14.4

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[Mesa-dev] [PATCH v4 0/4] nv50/ir: Improve Performance of Integer Multiplication

[Rhys Perry]

Changes in v4:
- remove uint16_t(...) in nv50_ir.h
- change XMAD immediate size from signed 20 bit to unsigned 16 bit
- rework the 4th patch
Changes in v3:
- stylistic changes
- simplify createMulMethod2()
- update shader-db statistics
- use util_bitcount64 and util_next_power_of_two64 instead of
  reimplementing them
Changes in v2:
- rebase
- bring back constant folding for multiplication by power-of-twos for nv50
- remove TODO in nv50_ir_target_gm107.cpp
- document XMAD's flags
- change how XMAD's per-operand flags are represented
- move util/bitscan.h stuff into a new patch
- stylistic changes

This series improve the performance of integer multiplication by removing
much usage of the very slow IMAD and IMUL on Maxwell+ and improving
multiplication by immediates on Fermi+.

The first and second patch add support for the XMAD instruction in codegen

The third patch replaces most IMADs and IMULs with a sequence of XMADs on
Maxwell+. This is far faster but increases the total instructions in the
shader-db by 0.90%, gpr count by 0.10% and local memory by 0.46%.

The next patch significantly lowers this number. It replaces many
multiplications by immediates with instructions that should be as fast or
faster than the generic approach. They are also typically smaller and less
register heavy, so they decrease the total instruction count by -0.56% and
bring the gpr count and local memory back to normal.

This series gives about a ~50% speedup in fragment-heavy scenaries with
Dolphin 5.0 on my GTX 1060. All timings were made with interesting looking
fifos from Dolphin's bugtracker:
 Wind Waker: 18 FPS -> 26 FPS at 3x internal resolution
 Wind Waker:  8 FPS -> 11 FPS at 5x internal resolution
   Paper Mario?: 26 FPS -> 42 FPS at 5x internal resolution
SpongeBob Movie: 19 FPS -> 30 FPS at 5x internal resolution

Unigine Heaven and Unigine Valley seems to run the same at low quality with
no anti-aliasing and no tessellation. SuperTuxKart and 0 A.D. also show no
change.

It's possible these patches may break something. Piglit shows no functionality
regressions though they should probably be tested for improvements or breakage
with actual applications.

These patches can also be found on my github:
https://github.com/pendingchaos/mesa/tree/nv-xmad-v4

The final changes in shader-db are as follows:

total instructions in shared programs : 5768871 -> 5788434 (0.34%)
total gprs used in shared programs: 669919 -> 669996 (0.01%)
total shared used in shared programs  : 548832 -> 548832 (0.00%)
total local used in shared programs   : 21068 -> 21068 (0.00%)

local sharedgpr   inst  bytes 
helped   0   0 220 901 901 
  hurt   0   0 23420252025 

Rhys Perry (4):
  nv50/ir: add preliminary support for OP_XMAD
  gm107/ir: add support for OP_XMAD on GM107+
  nv50/ir: optimize imul/imad to xmads
  nv50/ir: further optimize multiplication by immediates

 src/gallium/drivers/nouveau/codegen/nv50_ir.h  |  26 
 .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp |  65 +
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   | 155 ++---
 .../drivers/nouveau/codegen/nv50_ir_print.cpp  |  19 +++
 .../drivers/nouveau/codegen/nv50_ir_target.cpp |   7 +-
 .../nouveau/codegen/nv50_ir_target_gm107.cpp   |   6 +-
 .../nouveau/codegen/nv50_ir_target_nv50.cpp|   1 +
 .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  19 +++
 8 files changed, 277 insertions(+), 21 deletions(-)

-- 
2.14.4

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[Mesa-dev] [PATCH v4 1/4] nv50/ir: add preliminary support for OP_XMAD

[Rhys Perry]

v4: remove uint16_t(...)
v4: don't allow immediates outside [0,65535] in insnCanLoad()

Signed-off-by: Rhys Perry 
Reviewed-by: Karol Herbst 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir.h  | 26 ++
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   | 18 +--
 .../drivers/nouveau/codegen/nv50_ir_print.cpp  | 19 
 .../drivers/nouveau/codegen/nv50_ir_target.cpp |  7 +++---
 .../nouveau/codegen/nv50_ir_target_gm107.cpp   |  1 +
 .../nouveau/codegen/nv50_ir_target_nv50.cpp|  1 +
 .../nouveau/codegen/nv50_ir_target_nvc0.cpp| 18 +++
 7 files changed, 85 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 0b220cc48d..d5c9570a56 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -58,6 +58,9 @@ enum operation
OP_FMA,
OP_SAD, // abs(src0 - src1) + src2
OP_SHLADD,
+   // extended multiply-add (GM107+), does a lot of things.
+   // see envytools for detailed documentation
+   OP_XMAD,
OP_ABS,
OP_NEG,
OP_NOT,
@@ -256,6 +259,29 @@ enum operation
 #define NV50_IR_SUBOP_MINMAX_MED  2
 #define NV50_IR_SUBOP_MINMAX_HIGH 3
 
+// xmad(src0, src1, 0) << 16 + src2
+#define NV50_IR_SUBOP_XMAD_PSL (1 << 0)
+// (xmad(src0, src1, src2) & 0x) | (src1 << 16)
+#define NV50_IR_SUBOP_XMAD_MRG (1 << 1)
+// xmad(src0, src1, src2.lo)
+#define NV50_IR_SUBOP_XMAD_CLO (1 << 2)
+// xmad(src0, src1, src2.hi)
+#define NV50_IR_SUBOP_XMAD_CHI (2 << 2)
+// if both operands to the multiplication are non-zero, subtract 65536 for each
+// negative operand
+#define NV50_IR_SUBOP_XMAD_CSFU (3 << 2)
+// xmad(src0, src1, src2) + src1 << 16
+#define NV50_IR_SUBOP_XMAD_CBCC (4 << 2)
+#define NV50_IR_SUBOP_XMAD_CMODE_SHIFT 2
+#define NV50_IR_SUBOP_XMAD_CMODE_MASK (0x7 << NV50_IR_SUBOP_XMAD_CMODE_SHIFT)
+
+// use the high 16 bits instead of the low 16 bits for the multiplication.
+// if the instruction's sType is signed, sign extend the operand from 16 bits
+// to 32 before multiplication.
+#define NV50_IR_SUBOP_XMAD_H1_SHIFT 5
+#define NV50_IR_SUBOP_XMAD_H1(i) (1 << (NV50_IR_SUBOP_XMAD_H1_SHIFT + (i)))
+#define NV50_IR_SUBOP_XMAD_H1_MASK (0x3 << NV50_IR_SUBOP_XMAD_H1_SHIFT)
+
 enum DataType
 {
TYPE_NONE,
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 2f7cc206b8..5b4a98d25c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -191,9 +191,17 @@ void
 LoadPropagation::checkSwapSrc01(Instruction *insn)
 {
const Target *targ = prog->getTarget();
-   if (!targ->getOpInfo(insn).commutative)
-  if (insn->op != OP_SET && insn->op != OP_SLCT && insn->op != OP_SUB)
+   if (!targ->getOpInfo(insn).commutative) {
+  if (insn->op != OP_SET && insn->op != OP_SLCT &&
+  insn->op != OP_SUB && insn->op != OP_XMAD)
  return;
+  // XMAD is only commutative if both the CBCC and MRG flags are not set.
+  if (insn->op == OP_XMAD &&
+  (insn->subOp & NV50_IR_SUBOP_XMAD_CMODE_MASK) == 
NV50_IR_SUBOP_XMAD_CBCC)
+ return;
+  if (insn->op == OP_XMAD && (insn->subOp & NV50_IR_SUBOP_XMAD_MRG))
+ return;
+   }
if (insn->src(1).getFile() != FILE_GPR)
   return;
// This is the special OP_SET used for alphatesting, we can't reverse its
@@ -236,6 +244,12 @@ LoadPropagation::checkSwapSrc01(Instruction *insn)
if (insn->op == OP_SUB) {
   insn->src(0).mod = insn->src(0).mod ^ Modifier(NV50_IR_MOD_NEG);
   insn->src(1).mod = insn->src(1).mod ^ Modifier(NV50_IR_MOD_NEG);
+   } else
+   if (insn->op == OP_XMAD) {
+  // swap h1 flags
+  uint16_t h1 = (insn->subOp >> 1 & NV50_IR_SUBOP_XMAD_H1(0)) |
+(insn->subOp << 1 & NV50_IR_SUBOP_XMAD_H1(1));
+  insn->subOp = (insn->subOp & ~NV50_IR_SUBOP_XMAD_H1_MASK) | h1;
}
 }
 
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index ee3506fbae..7eab8b8d70 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
@@ -86,6 +86,7 @@ const char *operationStr[OP_LAST + 1] =
"fma",
"sad",
"shladd",
+   "xmad",
"abs",
"neg",
"not",
@@ -240,6 +241,11 @@ static const char *barOpStr[] =
"sync", "arrive", "red and", "red or", "red popc"
 };
 
+static const char *xmadOpCModeStr[] =
+{
+   "clo", "chi", "csfu", "cbcc"
+};
+
 static const char *DataTypeStr[] =
 {
"-",
@@ -625,6 +631,19 @@ void Instruction::print() const
  if (subOp < ARRAY_SIZE(barOpStr))
 PRINT("%s ", barOpStr[subOp]);
  break;
+  case OP_XMAD: {
+ if (subOp & NV50_IR_SUBOP_XMAD_PSL)
+PRINT("psl ");
+ if 

[Mesa-dev] [PATCH v4 3/4] nv50/ir: optimize imul/imad to xmads

[Rhys Perry]

This hits the shader-db numbers a good bit, though a few xmads is way
faster than an imul or imad and the cost is mitigated by the next commit,
which optimizes many multiplications by immediates into shorter and less
register heavy instructions than the xmads.

total instructions in shared programs : 5768871 -> 5820882 (0.90%)
total gprs used in shared programs: 669919 -> 670595 (0.10%)
total shared used in shared programs  : 548832 -> 548832 (0.00%)
total local used in shared programs   : 21068 -> 21164 (0.46%)

local sharedgpr   inst  bytes
helped   0   0  38   0   0
  hurt   1   0 36530763076

Signed-off-by: Rhys Perry 
Reviewed-by: Karol Herbst 
---
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   | 56 ++
 .../nouveau/codegen/nv50_ir_target_gm107.cpp   |  1 -
 2 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 5b4a98d25c..dc7bf24ba2 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -2301,13 +2301,18 @@ AlgebraicOpt::visit(BasicBlock *bb)
 // 
=
 
 // ADD(SHL(a, b), c) -> SHLADD(a, b, c)
+// MUL(a, b) -> a few XMADs
+// MAD/FMA(a, b, c) -> a few XMADs
 class LateAlgebraicOpt : public Pass
 {
 private:
virtual bool visit(Instruction *);
 
void handleADD(Instruction *);
+   void handleMULMAD(Instruction *);
bool tryADDToSHLADD(Instruction *);
+
+   BuildUtil bld;
 };
 
 void
@@ -2368,6 +2373,52 @@ LateAlgebraicOpt::tryADDToSHLADD(Instruction *add)
return true;
 }
 
+// MUL(a, b) -> a few XMADs
+// MAD/FMA(a, b, c) -> a few XMADs
+void
+LateAlgebraicOpt::handleMULMAD(Instruction *i)
+{
+   // TODO: handle NV50_IR_SUBOP_MUL_HIGH
+   if (!prog->getTarget()->isOpSupported(OP_XMAD, TYPE_U32))
+  return;
+   if (isFloatType(i->dType) || typeSizeof(i->dType) != 4)
+  return;
+   if (i->subOp || i->usesFlags() || i->flagsDef >= 0)
+  return;
+
+   assert(!i->src(0).mod);
+   assert(!i->src(1).mod);
+   assert(i->op == OP_MUL ? 1 : !i->src(2).mod);
+
+   bld.setPosition(i, false);
+
+   Value *a = i->getSrc(0);
+   Value *b = i->getSrc(1);
+   Value *c = i->op == OP_MUL ? bld.mkImm(0) : i->getSrc(2);
+
+   Value *tmp0 = bld.getSSA();
+   Value *tmp1 = bld.getSSA();
+
+   Instruction *insn = bld.mkOp3(OP_XMAD, TYPE_U32, tmp0, b, a, c);
+   insn->setPredicate(i->cc, i->getPredicate());
+
+   insn = bld.mkOp3(OP_XMAD, TYPE_U32, tmp1, b, a, bld.mkImm(0));
+   insn->setPredicate(i->cc, i->getPredicate());
+   insn->subOp = NV50_IR_SUBOP_XMAD_MRG | NV50_IR_SUBOP_XMAD_H1(1);
+
+   Value *pred = i->getPredicate();
+   i->setPredicate(i->cc, NULL);
+
+   i->op = OP_XMAD;
+   i->setSrc(0, b);
+   i->setSrc(1, tmp1);
+   i->setSrc(2, tmp0);
+   i->subOp = NV50_IR_SUBOP_XMAD_PSL | NV50_IR_SUBOP_XMAD_CBCC;
+   i->subOp |= NV50_IR_SUBOP_XMAD_H1(0) | NV50_IR_SUBOP_XMAD_H1(1);
+
+   i->setPredicate(i->cc, pred);
+}
+
 bool
 LateAlgebraicOpt::visit(Instruction *i)
 {
@@ -2375,6 +2426,11 @@ LateAlgebraicOpt::visit(Instruction *i)
case OP_ADD:
   handleADD(i);
   break;
+   case OP_MUL:
+   case OP_MAD:
+   case OP_FMA:
+  handleMULMAD(i);
+  break;
default:
   break;
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
index de07ad1de8..2e2e40770e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
@@ -170,7 +170,6 @@ TargetGM107::isBarrierRequired(const Instruction *insn) 
const
   }
   break;
case OPCLASS_ARITH:
-  // TODO: IMUL/IMAD require barriers too, use of XMAD instead!
   if ((insn->op == OP_MUL || insn->op == OP_MAD) &&
   !isFloatType(insn->dType))
  return true;
-- 
2.14.4

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[Mesa-dev] [PATCH v4 4/4] nv50/ir: further optimize multiplication by immediates

[Rhys Perry]

Strongly mitigates the harm from the previous commit, which made many
integer multiplications much more heavy on the register and instruction
count.

total instructions in shared programs : 5820882 -> 5788434 (-0.56%)
total gprs used in shared programs: 670595 -> 669996 (-0.09%)
total shared used in shared programs  : 548832 -> 548832 (0.00%)
total local used in shared programs   : 21164 -> 21068 (-0.45%)

local sharedgpr   inst  bytes
helped   1   0 38825002500
  hurt   0   0  94  11  11

v4: rework createMul() (has a side-effect that mad/fma is optimized to
shl+add on nv50)

Signed-off-by: Rhys Perry 
---
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   | 81 ++
 1 file changed, 66 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index dc7bf24ba2..d7eb6b503e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -379,6 +379,8 @@ private:
 
CmpInstruction *findOriginForTestWithZero(Value *);
 
+   bool createMul(Value *def, Value *a, int32_t b, Value *c);
+
unsigned int foldCount;
 
BuildUtil bld;
@@ -953,10 +955,65 @@ ConstantFolding::opnd3(Instruction *i, ImmediateValue 
)
}
 }
 
+bool
+ConstantFolding::createMul(Value *def, Value *a, int32_t b, Value *c)
+{
+   const Target *target = prog->getTarget();
+   int64_t absB = llabs(b);
+
+   //a * (2^shl) -> a << shl
+   if (b >= 0 && util_is_power_of_two_or_zero64(b)) {
+  int shl = util_logbase2_64(b);
+
+  if (c && target->isOpSupported(OP_SHLADD, TYPE_U32))
+ return bld.mkOp3(OP_SHLADD, TYPE_U32, def, a, bld.mkImm(shl), c);
+
+  Value *res = c ? bld.getSSA() : def;
+  bld.mkOp2(OP_SHL, TYPE_U32, res, a, bld.mkImm(shl));
+  if (c)
+ bld.mkOp2(OP_ADD, TYPE_U32, def, res, c);
+
+  return true;
+   }
+
+   //a * (2^shl + 1) -> a << shl + a
+   //a * -(2^shl + 1) -> -a << shl + a
+   //a * (2^shl - 1) -> a << shl - a
+   //a * -(2^shl - 1) -> -a << shl - a
+   if ((util_is_power_of_two_or_zero64(absB - 1) ||
+util_is_power_of_two_or_zero64(absB + 1)) &&
+   target->isOpSupported(OP_SHLADD, TYPE_U32)) {
+  bool subA = util_is_power_of_two_or_zero64(absB + 1);
+  int shl = subA ? util_logbase2_64(absB + 1) : util_logbase2_64(absB - 1);
+
+  Value *res = c ? bld.getSSA() : def;
+  Instruction *insn = bld.mkOp3(OP_SHLADD, TYPE_U32, res, a, 
bld.mkImm(shl), a);
+  if (b < 0)
+ insn->src(0).mod = Modifier(NV50_IR_MOD_NEG);
+  if (subA)
+ insn->src(2).mod = Modifier(NV50_IR_MOD_NEG);
+
+  if (c)
+ bld.mkOp2(OP_ADD, TYPE_U32, def, res, c);
+
+  return true;
+   }
+
+   if (b >= 0 && b <= 0x && target->isOpSupported(OP_XMAD, TYPE_U32)) {
+  Value *tmp = bld.mkOp3v(OP_XMAD, TYPE_U32, bld.getSSA(),
+  a, bld.mkImm(b), c ? c : bld.mkImm(0));
+  bld.mkOp3(OP_XMAD, TYPE_U32, def, a, bld.mkImm(b), tmp)->subOp =
+ NV50_IR_SUBOP_XMAD_PSL | NV50_IR_SUBOP_XMAD_H1(0);
+
+  return true;
+   }
+
+   return false;
+}
+
 void
 ConstantFolding::opnd(Instruction *i, ImmediateValue , int s)
 {
-   const Target *target = prog->getTarget();
const int t = !s;
const operation op = i->op;
Instruction *newi = i;
@@ -1040,13 +1097,10 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue 
, int s)
  i->setSrc(s, i->getSrc(t));
  i->src(s).mod = i->src(t).mod;
   } else
-  if (!isFloatType(i->sType) && !imm0.isNegative() && imm0.isPow2()) {
- i->op = OP_SHL;
- imm0.applyLog2();
- i->setSrc(0, i->getSrc(t));
- i->src(0).mod = i->src(t).mod;
- i->setSrc(1, new_ImmediateValue(prog, imm0.reg.data.u32));
- i->src(1).mod = 0;
+  if (!isFloatType(i->dType) && !i->src(t).mod) {
+ bld.setPosition(i, false);
+ if (createMul(i->getDef(0), i->getSrc(t), imm0.reg.data.s32, NULL))
+delete_Instruction(prog, i);
   } else
   if (i->postFactor && i->sType == TYPE_F32) {
  /* Can't emit a postfactor with an immediate, have to fold it in */
@@ -1079,13 +1133,10 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue 
, int s)
  i->setSrc(2, NULL);
  i->op = OP_ADD;
   } else
-  if (s == 1 && !imm0.isNegative() && imm0.isPow2() &&
-  !isFloatType(i->dType) &&
-  target->isOpSupported(OP_SHLADD, i->dType) &&
-  !i->subOp) {
- i->op = OP_SHLADD;
- imm0.applyLog2();
- i->setSrc(1, new_ImmediateValue(prog, imm0.reg.data.u32));
+  if (!isFloatType(i->dType) && !i->subOp && !i->src(t).mod && 
!i->src(2).mod) {
+ bld.setPosition(i, false);
+ if (createMul(i->getDef(0), i->getSrc(t), 

Re: [Mesa-dev] [PATCH v5 1/2] intel/ppgtt: memory address alignment

[Lionel Landwerlin]

On 15/08/18 12:23, Sergii Romantsov wrote:

Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).

-v2: added marking that also fixes initial commit 01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris Wilson).
-v4: changes related to PAGE_SIZE moved to separate commit
-v5: restored alignment to page-size for 0-size.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.)
Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to 
brw_bufmgr.)
Signed-off-by: Sergii Romantsov 


CI seems happy this time :

Reviewed-by: Lionel Landwerlin 


---
  src/mesa/drivers/dri/i965/brw_bufmgr.c | 7 +++
  1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 09d45e3..19e2d14 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -496,7 +496,6 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
uint32_t stride)
  {
 struct brw_bo *bo;
-   unsigned int page_size = getpagesize();
 int ret;
 struct bo_cache_bucket *bucket;
 bool alloc_from_cache;
@@ -522,12 +521,12 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
  * allocation up.
  */
 if (bucket == NULL) {
-  bo_size = size;
-  if (bo_size < page_size)
- bo_size = page_size;
+  unsigned int page_size = getpagesize();
+  bo_size = size == 0 ? page_size : ALIGN(size, page_size);
 } else {
bo_size = bucket->size;
 }
+   assert(bo_size);
  
 mtx_lock(>lock);

 /* Get a buffer out of the cache if available */



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Re: [Mesa-dev] [PATCH] radv: Revert divisor = 0 case for vertex attribute extension.

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 8/15/18 4:30 PM, Bas Nieuwenhuizen wrote:

Seems like DXVK depends on that and it might get reverted
upstream. Since apps are not supposed to use 0 in v2 anyway,
we should be safe implementing the old behavior there.

Fixes: 66e12451ac4 "radv: Update to new VK_EXT_vertex_attribute_divisor to version 
2."
CC: 18.2 
---
  src/amd/vulkan/radv_nir_to_llvm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index bfd8b562e5c..8bf3ae0f150 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2006,7 +2006,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
MAX2(1, 
ctx->shader_info->vs.vgpr_comp_cnt);
}
} else {
-   unreachable("Invalid vertex attribute divisor of 
0.");
+   buffer_index = ctx->ac.i32_0;
}
  
  			buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");



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[Mesa-dev] [PATCH] radv: Revert divisor = 0 case for vertex attribute extension.

[Bas Nieuwenhuizen]

Seems like DXVK depends on that and it might get reverted
upstream. Since apps are not supposed to use 0 in v2 anyway,
we should be safe implementing the old behavior there.

Fixes: 66e12451ac4 "radv: Update to new VK_EXT_vertex_attribute_divisor to 
version 2."
CC: 18.2 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index bfd8b562e5c..8bf3ae0f150 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2006,7 +2006,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
MAX2(1, 
ctx->shader_info->vs.vgpr_comp_cnt);
}
} else {
-   unreachable("Invalid vertex attribute divisor 
of 0.");
+   buffer_index = ctx->ac.i32_0;
}
 
buffer_index = LLVMBuildAdd(ctx->ac.builder, 
ctx->abi.start_instance, buffer_index, "");
-- 
2.18.0

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Re: [Mesa-dev] [PATCH] radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.

[Bas Nieuwenhuizen]

On Wed, Aug 15, 2018 at 11:49 AM, Jason Ekstrand  wrote:
> On Tue, Aug 14, 2018 at 7:20 AM Samuel Pitoiset 
> wrote:
>>
>> Reviewed-by: Samuel Pitoiset 
>>
>> On 7/23/18 4:24 PM, Bas Nieuwenhuizen wrote:
>> > Behavior wrt firstInstance got changed, and a divisor of 0 has been
>> > disallowed.
>> >
>> > The new version of the ext got published in specification 1.1.81.
>> > ---
>> >   src/amd/vulkan/radv_extensions.py | 2 +-
>> >   src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
>> >   2 files changed, 5 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/src/amd/vulkan/radv_extensions.py
>> > b/src/amd/vulkan/radv_extensions.py
>> > index a5fbffac33b..d02042e5647 100644
>> > --- a/src/amd/vulkan/radv_extensions.py
>> > +++ b/src/amd/vulkan/radv_extensions.py
>> > @@ -104,7 +104,7 @@ EXTENSIONS = [
>> >   Extension('VK_EXT_sampler_filter_minmax', 1,
>> > 'device->rad_info.chip_class >= CIK'),
>> >   Extension('VK_EXT_shader_viewport_index_layer',   1, True),
>> >   Extension('VK_EXT_shader_stencil_export', 1, True),
>> > -Extension('VK_EXT_vertex_attribute_divisor',  1, True),
>> > +Extension('VK_EXT_vertex_attribute_divisor',  2, True),
>> >   Extension('VK_AMD_draw_indirect_count',   1, True),
>> >   Extension('VK_AMD_gcn_shader',1, True),
>> >   Extension('VK_AMD_rasterization_order',   1,
>> > 'device->has_out_of_order_rast'),
>> > diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
>> > b/src/amd/vulkan/radv_nir_to_llvm.c
>> > index c7d772fa652..d12ef09c9f3 100644
>> > --- a/src/amd/vulkan/radv_nir_to_llvm.c
>> > +++ b/src/amd/vulkan/radv_nir_to_llvm.c
>> > @@ -1984,8 +1984,7 @@ handle_vs_input_decl(struct radv_shader_context
>> > *ctx,
>> >   uint32_t divisor =
>> > ctx->options->key.vs.instance_rate_divisors[attrib_index];
>> >
>> >   if (divisor) {
>> > - buffer_index =
>> > LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
>> > -
>> > ctx->abi.start_instance, "");
>> > + buffer_index = ctx->abi.instance_id;
>> >
>> >   if (divisor != 1) {
>> >   buffer_index =
>> > LLVMBuildUDiv(ctx->ac.builder, buffer_index,
>> > @@ -2000,8 +1999,10 @@ handle_vs_input_decl(struct radv_shader_context
>> > *ctx,
>> >   MAX2(1,
>> > ctx->shader_info->vs.vgpr_comp_cnt);
>> >   }
>> >   } else {
>> > - buffer_index = ctx->ac.i32_0;
>> > + unreachable("Invalid vertex attribute
>> > divisor of 0.");
>
>
> You'll want to leave this alone.  zero is coming back...  Yeah, I know it's
> annoying but I'm really trying to get this settled out as quickly as
> possible.  In the mean time, reports are that zero is useful for some DXVK
> apps so it's best to just silently support it rather than breaking stuff.

Is the behavior of zero going to be the same as it was in version 1?

>
>>
>> >   }
>> > +
>> > + buffer_index = LLVMBuildAdd(ctx->ac.builder,
>> > ctx->abi.start_instance, buffer_index, "");
>> >   } else
>> >   buffer_index = LLVMBuildAdd(ctx->ac.builder,
>> > ctx->abi.vertex_id,
>> >   ctx->abi.base_vertex,
>> > "");
>> >
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[Mesa-dev] [PATCH] radv: Possible demand compilation fix.

[Bas Nieuwenhuizen]

Seems that in a single case we use the renderpass before checking
the pipeline, so check the renderpass before we use it.

Fixes: fbcd1673144 "radv: Add on-demand compilation of built-in shaders."
---
 src/amd/vulkan/radv_meta_resolve_fs.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c 
b/src/amd/vulkan/radv_meta_resolve_fs.c
index 21a5922f5df..af4a6fe7a66 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -463,6 +463,14 @@ void radv_meta_resolve_fragment_image(struct 
radv_cmd_buffer *cmd_buffer,
radv_decompress_resolve_src(cmd_buffer, src_image, src_image_layout,
region_count, regions);
 
+   if 
(!device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout])
 {
+   VkResult ret = create_resolve_pipeline(device, samples_log2, 
radv_fs_key_format_exemplars[fs_key]);
+   if (ret != VK_SUCCESS) {
+   cmd_buffer->record_result = ret;
+   return;
+   }
+   }
+
rp = 
device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout];
 
radv_meta_save(_state, cmd_buffer,
-- 
2.18.0

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[Mesa-dev] [Bug 107460] radv: OpControlBarrier does not always work correctly (bisected)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107460

Samuel Pitoiset  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #4 from Samuel Pitoiset  ---
Should be fixed with
https://cgit.freedesktop.org/mesa/mesa/commit/?id=71d5b2fbf83061a1319141d26942771e8c75ff2b

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Re: [Mesa-dev] [PATCH v1] i965: Emitting 3DSTATE_SO_BUFFER of 0-size.

[Sergii Romantsov]

Hello,
that patch is according to remark:
>
> "Additionally, we probably ought to fix the callers to stop allocating 0
> size BOs.
> It looks like most of them come from the 3DSTATE_SO_BUFFER code,
> where one stream has valid transform feedback info, and the other
> 3 are empty. "


 And seems additional one: https://patchwork.freedesktop.org/patch/244674/


On Wed, Aug 15, 2018 at 3:21 PM, Sergii Romantsov <
sergii.romant...@gmail.com> wrote:

> Avoided filling of whole structure and bo-allocation if
> size of surface is 0.
>
> Signed-off-by: Sergii Romantsov 
> ---
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
> b/src/mesa/drivers/dri/i965/genX_state_upload.c
> index ea5ad55..c051848 100644
> --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> @@ -3787,19 +3787,20 @@ genX(upload_3dstate_so_buffers)(struct
> brw_context *brw)
> for (int i = 0; i < 4; i++) {
>struct intel_buffer_object *bufferobj =
>   intel_buffer_object(xfb_obj->Buffers[i]);
> +  uint32_t start = xfb_obj->Offset[i];
> +  uint32_t end = ALIGN(start + xfb_obj->Size[i], 4);
> +  uint32_t const size = end - start;
>
> -  if (!bufferobj) {
> +  if (!bufferobj || !size) {
>   brw_batch_emit(brw, GENX(3DSTATE_SO_BUFFER), sob) {
>  sob.SOBufferIndex = i;
>   }
>   continue;
>}
>
> -  uint32_t start = xfb_obj->Offset[i];
>assert(start % 4 == 0);
> -  uint32_t end = ALIGN(start + xfb_obj->Size[i], 4);
>struct brw_bo *bo =
> - intel_bufferobj_buffer(brw, bufferobj, start, end - start, true);
> + intel_bufferobj_buffer(brw, bufferobj, start, size, true);
>assert(end <= bo->size);
>
>brw_batch_emit(brw, GENX(3DSTATE_SO_BUFFER), sob) {
> --
> 2.7.4
>
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[Mesa-dev] [PATCH v1] i965/bo/perf: 0-sized-bo allocation log

[Sergii Romantsov]

Added debug-log in case of bo-allocation with 0 size.
Potentially we may not need to allocate such buffers and each
case could be analyzed to improve behaviour.

Signed-off-by: Sergii Romantsov 
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 09d45e3..726b266 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -514,6 +514,9 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
 * be idle before we can memset.  Just disallow that combination.
 */
assert(!(busy && zeroed));
+   if (!size && unlikely(INTEL_DEBUG & DEBUG_PERF))
+  dbg_printf("performance: allocation of 0-sized BO: %s\n", name);
+
 
/* Round the allocated size up to a power of two number of pages. */
bucket = bucket_for_size(bufmgr, size);
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] radv: fix memory leaks in radv_load_meta_pipeline()

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Wed, Aug 15, 2018 at 3:28 PM, Samuel Pitoiset
 wrote:
> Reported by Coverity.
>
> Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_meta.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
> index ccdcb9ceb0..b8d0a7cfc7 100644
> --- a/src/amd/vulkan/radv_meta.c
> +++ b/src/amd/vulkan/radv_meta.c
> @@ -263,6 +263,7 @@ radv_load_meta_pipeline(struct radv_device *device)
> char path[PATH_MAX + 1];
> struct stat st;
> void *data = NULL;
> +   bool ret = false;
>
> if (!radv_builtin_cache_path(path))
> return false;
> @@ -278,11 +279,11 @@ radv_load_meta_pipeline(struct radv_device *device)
> if(read(fd, data, st.st_size) == -1)
> goto fail;
>
> -   return radv_pipeline_cache_load(>meta_state.cache, data, 
> st.st_size);
> +   ret = radv_pipeline_cache_load(>meta_state.cache, data, 
> st.st_size);
>  fail:
> free(data);
> close(fd);
> -   return false;
> +   return ret;
>  }
>
>  static void
> --
> 2.18.0
>
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Re: [Mesa-dev] [PATCH] radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITS

[Samuel Pitoiset]

On 8/15/18 3:34 PM, Bas Nieuwenhuizen wrote:

On Wed, Aug 15, 2018 at 2:13 PM, Samuel Pitoiset
 wrote:



On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote:


On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset
 wrote:


The last parameter of radeon_set_sh_reg_seq() is the number of
dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but
it was initialized to 0.

COMPUTE_RESOURCE_LIMITS is correctly set when generating
compute pipelines, so we don't need to initialize it.



Note that there we don't set WAVES_PER_SH. Is that intended?



Yeah, I don't think that matters and it wasn't set before anyway.



Reviewed-by: Bas Nieuwenhuizen 

Also a radeonsi patch?



Why?


The same wrong patch was applied to radeonsi initialization, no?


No, RadeonSI looks good.










Signed-off-by: Samuel Pitoiset 
---
   src/amd/vulkan/si_cmd_buffer.c | 4 +---
   1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c
b/src/amd/vulkan/si_cmd_buffer.c
index 2337036c67..2cfa7f4c2c 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -88,9 +88,7 @@ si_emit_compute(struct radv_physical_device
*physical_device,
  radeon_emit(cs, 0);
  radeon_emit(cs, 0);

-   radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
- S_00B854_WAVES_PER_SH(0x3));
-   radeon_emit(cs, 0);
+   radeon_set_sh_reg_seq(cs,
R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
  /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
  radeon_emit(cs, S_00B858_SH0_CU_EN(0x) |
S_00B858_SH1_CU_EN(0x));
  radeon_emit(cs, S_00B85C_SH0_CU_EN(0x) |
S_00B85C_SH1_CU_EN(0x));
--
2.18.0

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Re: [Mesa-dev] [PATCH] radv: disable the auto-waitcnt-before-barrier LLVM option

[Samuel Pitoiset]

On 8/15/18 3:33 PM, Bas Nieuwenhuizen wrote:

Reviewed-by: Bas Nieuwenhuizen 

On Wed, Aug 15, 2018 at 3:09 PM, Samuel Pitoiset
 wrote:

This option allows us to remove additional s_waitcnt instructions
because s_barrier internally does s_waitcnt 0.

Though, apparently there is a problem with LDS accesses that
causes rendering issues with FFXV and DXVK. Disable this
optimization for now (RadeonSI still uses it).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460
CC: 18.2 
Signed-off-by: Samuel Pitoiset 
---
  src/amd/common/ac_llvm_util.c  | 3 ++-
  src/amd/common/ac_llvm_util.h  | 1 +
  src/gallium/drivers/radeonsi/si_pipe.c | 1 +
  3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index 10e1ca99d4..008a2cfa4e 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -149,7 +149,8 @@ static LLVMTargetMachineRef ac_create_target_machine(enum 
radeon_family family,
 char features[256];
 const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" 
: "amdgcn--";
 LLVMTargetRef target = ac_get_llvm_target(triple);
-   bool barrier_does_waitcnt = family != CHIP_VEGA20;
+   bool barrier_does_waitcnt = tm_options & AC_TM_AUTO_WAITCNT_BEFORE_BARRIER 
&&


Can you please do parentheses around the and? I know they're not
strictly necessary but I'd like not to have to
think about precedence too much.


Will do before pushing.




+   family != CHIP_VEGA20;

 snprintf(features, sizeof(features),
  
"+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
index eaf5f21876..e252bed3bb 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -65,6 +65,7 @@ enum ac_target_machine_options {
 AC_TM_CHECK_IR = (1 << 5),
 AC_TM_ENABLE_GLOBAL_ISEL = (1 << 6),
 AC_TM_CREATE_LOW_OPT = (1 << 7),
+   AC_TM_AUTO_WAITCNT_BEFORE_BARRIER = (1 << 8),
  };

  enum ac_float_mode {
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 13fcf1f3ae..4327a3f749 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -115,6 +115,7 @@ static void si_init_compiler(struct si_screen *sscreen,
sscreen->info.chip_class <= VI;

 enum ac_target_machine_options tm_options =
+   AC_TM_AUTO_WAITCNT_BEFORE_BARRIER |
 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL 
: 0) |
 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 
0) |
--
2.18.0

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Re: [Mesa-dev] [PATCH] radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITS

[Bas Nieuwenhuizen]

On Wed, Aug 15, 2018 at 2:13 PM, Samuel Pitoiset
 wrote:
>
>
> On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote:
>>
>> On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset
>>  wrote:
>>>
>>> The last parameter of radeon_set_sh_reg_seq() is the number of
>>> dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but
>>> it was initialized to 0.
>>>
>>> COMPUTE_RESOURCE_LIMITS is correctly set when generating
>>> compute pipelines, so we don't need to initialize it.
>>
>>
>> Note that there we don't set WAVES_PER_SH. Is that intended?
>
>
> Yeah, I don't think that matters and it wasn't set before anyway.
>
>>
>> Reviewed-by: Bas Nieuwenhuizen 
>>
>> Also a radeonsi patch?
>
>
> Why?

The same wrong patch was applied to radeonsi initialization, no?

>
>
>>
>>>
>>> Signed-off-by: Samuel Pitoiset 
>>> ---
>>>   src/amd/vulkan/si_cmd_buffer.c | 4 +---
>>>   1 file changed, 1 insertion(+), 3 deletions(-)
>>>
>>> diff --git a/src/amd/vulkan/si_cmd_buffer.c
>>> b/src/amd/vulkan/si_cmd_buffer.c
>>> index 2337036c67..2cfa7f4c2c 100644
>>> --- a/src/amd/vulkan/si_cmd_buffer.c
>>> +++ b/src/amd/vulkan/si_cmd_buffer.c
>>> @@ -88,9 +88,7 @@ si_emit_compute(struct radv_physical_device
>>> *physical_device,
>>>  radeon_emit(cs, 0);
>>>  radeon_emit(cs, 0);
>>>
>>> -   radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
>>> - S_00B854_WAVES_PER_SH(0x3));
>>> -   radeon_emit(cs, 0);
>>> +   radeon_set_sh_reg_seq(cs,
>>> R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
>>>  /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
>>>  radeon_emit(cs, S_00B858_SH0_CU_EN(0x) |
>>> S_00B858_SH1_CU_EN(0x));
>>>  radeon_emit(cs, S_00B85C_SH0_CU_EN(0x) |
>>> S_00B85C_SH1_CU_EN(0x));
>>> --
>>> 2.18.0
>>>
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Re: [Mesa-dev] [PATCH] radv: disable the auto-waitcnt-before-barrier LLVM option

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Wed, Aug 15, 2018 at 3:09 PM, Samuel Pitoiset
 wrote:
> This option allows us to remove additional s_waitcnt instructions
> because s_barrier internally does s_waitcnt 0.
>
> Though, apparently there is a problem with LDS accesses that
> causes rendering issues with FFXV and DXVK. Disable this
> optimization for now (RadeonSI still uses it).
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460
> CC: 18.2 
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/common/ac_llvm_util.c  | 3 ++-
>  src/amd/common/ac_llvm_util.h  | 1 +
>  src/gallium/drivers/radeonsi/si_pipe.c | 1 +
>  3 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
> index 10e1ca99d4..008a2cfa4e 100644
> --- a/src/amd/common/ac_llvm_util.c
> +++ b/src/amd/common/ac_llvm_util.c
> @@ -149,7 +149,8 @@ static LLVMTargetMachineRef ac_create_target_machine(enum 
> radeon_family family,
> char features[256];
> const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? 
> "amdgcn-mesa-mesa3d" : "amdgcn--";
> LLVMTargetRef target = ac_get_llvm_target(triple);
> -   bool barrier_does_waitcnt = family != CHIP_VEGA20;
> +   bool barrier_does_waitcnt = tm_options & 
> AC_TM_AUTO_WAITCNT_BEFORE_BARRIER &&

Can you please do parentheses around the and? I know they're not
strictly necessary but I'd like not to have to
think about precedence too much.

> +   family != CHIP_VEGA20;
>
> snprintf(features, sizeof(features),
>  
> "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
> diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
> index eaf5f21876..e252bed3bb 100644
> --- a/src/amd/common/ac_llvm_util.h
> +++ b/src/amd/common/ac_llvm_util.h
> @@ -65,6 +65,7 @@ enum ac_target_machine_options {
> AC_TM_CHECK_IR = (1 << 5),
> AC_TM_ENABLE_GLOBAL_ISEL = (1 << 6),
> AC_TM_CREATE_LOW_OPT = (1 << 7),
> +   AC_TM_AUTO_WAITCNT_BEFORE_BARRIER = (1 << 8),
>  };
>
>  enum ac_float_mode {
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 13fcf1f3ae..4327a3f749 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -115,6 +115,7 @@ static void si_init_compiler(struct si_screen *sscreen,
>sscreen->info.chip_class <= VI;
>
> enum ac_target_machine_options tm_options =
> +   AC_TM_AUTO_WAITCNT_BEFORE_BARRIER |
> (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
> (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL 
> : 0) |
> (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK 
> : 0) |
> --
> 2.18.0
>
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Re: [Mesa-dev] [PATCH v3 0/6] support config for third-party DRI driver load

[Yu, Qiang]

> Pardon for the delay, Qiang Yu  Series looks good and is
> Reviewed-by: Emil Velikov 
>
> The series has been on the list for a while, Michel seems happy with
> it, so I'm inclined to merge this late today/early tomorrow.
> Please keep an eye open for any bug reports - just a gut feeling.

Thanks Emil, I will. Hope it's OK.

Regards,
Qiang
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[Mesa-dev] [PATCH] radv: fix memory leaks in radv_load_meta_pipeline()

[Samuel Pitoiset]

Reported by Coverity.

Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index ccdcb9ceb0..b8d0a7cfc7 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -263,6 +263,7 @@ radv_load_meta_pipeline(struct radv_device *device)
char path[PATH_MAX + 1];
struct stat st;
void *data = NULL;
+   bool ret = false;
 
if (!radv_builtin_cache_path(path))
return false;
@@ -278,11 +279,11 @@ radv_load_meta_pipeline(struct radv_device *device)
if(read(fd, data, st.st_size) == -1)
goto fail;
 
-   return radv_pipeline_cache_load(>meta_state.cache, data, 
st.st_size);
+   ret = radv_pipeline_cache_load(>meta_state.cache, data, 
st.st_size);
 fail:
free(data);
close(fd);
-   return false;
+   return ret;
 }
 
 static void
-- 
2.18.0

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