Re: [Mesa-dev] [PATCH] radv: Use build ID if available for cache UUID.
On Mon, Sep 17, 2018 at 2:10 AM Timothy Arceri wrote:
>
> On 16/9/18 10:58 am, Bas Nieuwenhuizen wrote:
> > To get an useful UUID for systems that have a non-useful mtime
> > for the binaries.
> >
> > I started using using SHA1 to ensure we get reasonable mixing
>
> using using - > using
Fixed locally.
>
> So did this return a build id for LLVM on your distro?
Yes, got one for each
>
> Reviewed-by: Timothy Arceri
Thanks!
>
> > in the various possibilities and the various build id lengths.
> >
> > CC:
> > ---
> > src/amd/vulkan/radv_device.c | 43 +---
> > 1 file changed, 35 insertions(+), 8 deletions(-)
> >
> > diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> > index 8989ec3553f..a2a73089f27 100644
> > --- a/src/amd/vulkan/radv_device.c
> > +++ b/src/amd/vulkan/radv_device.c
> > @@ -45,22 +45,49 @@
> > #include "sid.h"
> > #include "gfx9d.h"
> > #include "addrlib/gfx9/chip/gfx9_enum.h"
> > +#include "util/build_id.h"
> > #include "util/debug.h"
> > +#include "util/mesa-sha1.h"
> > +
> > +static bool
> > +radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
> > +{
> > + uint32_t timestamp;
> > +
> > +#ifdef HAVE_DL_ITERATE_PHDR
> > + const struct build_id_note *note = NULL;
> > + if ((note = build_id_find_nhdr_for_addr(ptr))) {
> > + _mesa_sha1_update(ctx, build_id_data(note),
> > build_id_length(note));
> > + } else
> > +#endif
> > + if (disk_cache_get_function_timestamp(ptr, )) {
> > + if (!timestamp) {
> > + fprintf(stderr, "radv: The provided filesystem
> > timestamp for the cache is bogus!\n");
> > + }
> > +
> > + _mesa_sha1_update(ctx, , sizeof(timestamp));
> > + } else
> > + return false;
> > + return true;
> > +}
> >
> > static int
> > radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
> > {
> > - uint32_t mesa_timestamp, llvm_timestamp;
> > - uint16_t f = family;
> > + struct mesa_sha1 ctx;
> > + unsigned char sha1[20];
> > + unsigned ptr_size = sizeof(void*);
> > memset(uuid, 0, VK_UUID_SIZE);
> > - if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid,
> > _timestamp) ||
> > -
> > !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
> > _timestamp))
> > +
> > + if (!radv_get_build_id(radv_device_get_cache_uuid, ) ||
> > + !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, ))
> > return -1;
> >
> > - memcpy(uuid, _timestamp, 4);
> > - memcpy((char*)uuid + 4, _timestamp, 4);
> > - memcpy((char*)uuid + 8, , 2);
> > - snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv%zd", sizeof(void
> > *));
> > + _mesa_sha1_update(, , sizeof(family));
> > + _mesa_sha1_update(, _size, sizeof(ptr_size));
> > + _mesa_sha1_final(, sha1);
> > +
> > + memcpy(uuid, sha1, VK_UUID_SIZE);
> > return 0;
> > }
> >
> >
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[Mesa-dev] [Bug 107765] [regression] Batman Arkham City crashes with DXVK under wine
https://bugs.freedesktop.org/show_bug.cgi?id=107765
Timothy Arceri changed:
What|Removed |Added
Status|NEEDINFO|NEW
--- Comment #3 from Timothy Arceri ---
Ok I now see the crash when replaying a renderdoc capture on a 64-bit version
of RADV (its possible I messed up my 32 RADV build or forgot to enable a debug
build).
I've uploaded the capture to google driver [1]. The capture was taken from the
benchmark where there are some rendering issues. Anyway the trace should be
enough for others to reproduce this issue without access to the game (note
rendedoc build from git required).
Seems we get to:
uint32_t radv_translate_colorformat(VkFormat format)
...
case 3:
if (HAS_SIZE(5,6,5,0)) {
return V_028C70_COLOR_5_6_5;
} else if (HAS_SIZE(32,8,24,0)) {
return V_028C70_COLOR_X24_8_32_FLOAT;
}
break;
And fall through to:
return V_028C70_COLOR_INVALID;
[1]
https://drive.google.com/file/d/1OvISgWIHv4_Y7MkWX8U-c6b0DAojbo4Y/view?usp=sharing
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Re: [Mesa-dev] [PATCH] radv: Use build ID if available for cache UUID.
On 16/9/18 10:58 am, Bas Nieuwenhuizen wrote:
To get an useful UUID for systems that have a non-useful mtime
for the binaries.
I started using using SHA1 to ensure we get reasonable mixing
using using - > using
So did this return a build id for LLVM on your distro?
Reviewed-by: Timothy Arceri
in the various possibilities and the various build id lengths.
CC:
---
src/amd/vulkan/radv_device.c | 43 +---
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 8989ec3553f..a2a73089f27 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -45,22 +45,49 @@
#include "sid.h"
#include "gfx9d.h"
#include "addrlib/gfx9/chip/gfx9_enum.h"
+#include "util/build_id.h"
#include "util/debug.h"
+#include "util/mesa-sha1.h"
+
+static bool
+radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
+{
+ uint32_t timestamp;
+
+#ifdef HAVE_DL_ITERATE_PHDR
+ const struct build_id_note *note = NULL;
+ if ((note = build_id_find_nhdr_for_addr(ptr))) {
+ _mesa_sha1_update(ctx, build_id_data(note),
build_id_length(note));
+ } else
+#endif
+ if (disk_cache_get_function_timestamp(ptr, )) {
+ if (!timestamp) {
+ fprintf(stderr, "radv: The provided filesystem timestamp for
the cache is bogus!\n");
+ }
+
+ _mesa_sha1_update(ctx, , sizeof(timestamp));
+ } else
+ return false;
+ return true;
+}
static int
radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
{
- uint32_t mesa_timestamp, llvm_timestamp;
- uint16_t f = family;
+ struct mesa_sha1 ctx;
+ unsigned char sha1[20];
+ unsigned ptr_size = sizeof(void*);
memset(uuid, 0, VK_UUID_SIZE);
- if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid,
_timestamp) ||
- !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
_timestamp))
+
+ if (!radv_get_build_id(radv_device_get_cache_uuid, ) ||
+ !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, ))
return -1;
- memcpy(uuid, _timestamp, 4);
- memcpy((char*)uuid + 4, _timestamp, 4);
- memcpy((char*)uuid + 8, , 2);
- snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv%zd", sizeof(void
*));
+ _mesa_sha1_update(, , sizeof(family));
+ _mesa_sha1_update(, _size, sizeof(ptr_size));
+ _mesa_sha1_final(, sha1);
+
+ memcpy(uuid, sha1, VK_UUID_SIZE);
return 0;
}
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Re: [Mesa-dev] [PATCH 2/2] anv: add support for VK_EXT_inline_uniform_block
On 16/09/2018 21:57, Bas Nieuwenhuizen wrote:
On Tue, Sep 11, 2018 at 10:23 PM Lionel Landwerlin
wrote:
This new extension adds an implicitly allocated block of uniforms into
the descriptors sets through a new descriptor type.
We implement this by having a single BO in the descriptor set pool
from which we source uniforms.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_cmd_buffer.c | 3 +
src/intel/vulkan/anv_descriptor_set.c | 238 +-
src/intel/vulkan/anv_device.c | 22 ++
src/intel/vulkan/anv_extensions.py| 1 +
.../vulkan/anv_nir_apply_pipeline_layout.c| 52
src/intel/vulkan/anv_private.h| 33 +++
src/intel/vulkan/genX_cmd_buffer.c| 32 ++-
7 files changed, 367 insertions(+), 14 deletions(-)
diff --git a/src/intel/vulkan/anv_cmd_buffer.c
b/src/intel/vulkan/anv_cmd_buffer.c
index 8ef71b0ed9c..b14be94f470 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -651,6 +651,7 @@ anv_isl_format_for_descriptor_type(VkDescriptorType type)
switch (type) {
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
+ case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
return ISL_FORMAT_R32G32B32A32_FLOAT;
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
@@ -1039,6 +1040,8 @@ void anv_CmdPushDescriptorSetKHR(
}
break;
+ case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
+ unreachable("Invalid descriptor type for push descriptors");
default:
break;
}
diff --git a/src/intel/vulkan/anv_descriptor_set.c
b/src/intel/vulkan/anv_descriptor_set.c
index 3439f828900..2e5f2a1f288 100644
--- a/src/intel/vulkan/anv_descriptor_set.c
+++ b/src/intel/vulkan/anv_descriptor_set.c
@@ -26,8 +26,10 @@
#include
#include
#include
+#include
#include "util/mesa-sha1.h"
+#include "vk_util.h"
#include "anv_private.h"
@@ -40,7 +42,8 @@ void anv_GetDescriptorSetLayoutSupport(
const VkDescriptorSetLayoutCreateInfo* pCreateInfo,
VkDescriptorSetLayoutSupport* pSupport)
{
- uint32_t surface_count[MESA_SHADER_STAGES] = { 0, };
+ int16_t surface_count[MESA_SHADER_STAGES] = { 0, };
+ int16_t inline_surface_indexes[MESA_SHADER_STAGES] = { -1, };
for (uint32_t b = 0; b < pCreateInfo->bindingCount; b++) {
const VkDescriptorSetLayoutBinding *binding =
>pBindings[b];
@@ -50,6 +53,15 @@ void anv_GetDescriptorSetLayoutSupport(
/* There is no real limit on samplers */
break;
+ case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
+ anv_foreach_stage(s, binding->stageFlags) {
+if (inline_surface_indexes[s] < 0) {
+ inline_surface_indexes[s] = surface_count[s];
+ surface_count[s] += 1;
+}
+ }
+ break;
+
case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
if (binding->pImmutableSamplers) {
for (uint32_t i = 0; i < binding->descriptorCount; i++) {
@@ -118,6 +130,9 @@ VkResult anv_CreateDescriptorSetLayout(
memset(set_layout, 0, sizeof(*set_layout));
set_layout->ref_cnt = 1;
set_layout->binding_count = max_binding + 1;
+ set_layout->inline_blocks_descriptor_index = -1;
+ memset(set_layout->inline_blocks_surface_indexes,
+ -1, sizeof(set_layout->inline_blocks_surface_indexes));
for (uint32_t b = 0; b <= max_binding; b++) {
/* Initialize all binding_layout entries to -1 */
@@ -159,9 +174,24 @@ VkResult anv_CreateDescriptorSetLayout(
#ifndef NDEBUG
set_layout->binding[b].type = binding->descriptorType;
#endif
- set_layout->binding[b].array_size = binding->descriptorCount;
- set_layout->binding[b].descriptor_index = set_layout->size;
- set_layout->size += binding->descriptorCount;
+
+ if (binding->descriptorType ==
VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
+ /* We only a single descriptor entry for all the inline uniforms. */
+ set_layout->binding[b].array_size = 1;
+ if (set_layout->inline_blocks_descriptor_index < 0) {
+set_layout->binding[b].descriptor_index =
+ set_layout->inline_blocks_descriptor_index =
+ set_layout->size;
+set_layout->size += 1;
+ } else {
+set_layout->binding[b].descriptor_index =
+ set_layout->inline_blocks_descriptor_index;
+ }
+ } else {
+ set_layout->binding[b].array_size = binding->descriptorCount;
+ set_layout->binding[b].descriptor_index = set_layout->size;
+ set_layout->size += binding->descriptorCount;
+ }
switch (binding->descriptorType) {
case VK_DESCRIPTOR_TYPE_SAMPLER:
@@ -176,6 +206,24 @@ VkResult anv_CreateDescriptorSetLayout(
}
switch (binding->descriptorType) {
+ case
[Mesa-dev] [Bug 107777] No 3D in "Vampire: The Masquerade - Bloodlines" when d3d-nine enabled
https://bugs.freedesktop.org/show_bug.cgi?id=10 --- Comment #8 from Axel Davy --- I have implemented a missing feature to resize when rendering area and window size are of different size, which may fix your 'crop' behaviour. The patch is currently on our current work-in-progress git: https://github.com/iXit/Mesa-3D Related to the misrendering menu, could you make a trace under nine ? On the other bug report I mentionned, the user had made a trace under wine, and it replays well on both wine and nine. To compare, it may help to have a trace made under nine. For that, download apitrace latest binaries: https://people.freedesktop.org/~jrfonseca/apitrace/ and under the apitrace/x86/lib/ dir copy d3d9.dll and d3d9.pdb to your game exe directory. Finally in winecfg, add a redirection for d3d9.dll: native then integrated. This will automatically create a trace file in the exe directory. To uninstall, remove the files and the redirection. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] anv: add support for VK_EXT_inline_uniform_block
On Tue, Sep 11, 2018 at 10:23 PM Lionel Landwerlin
wrote:
>
> This new extension adds an implicitly allocated block of uniforms into
> the descriptors sets through a new descriptor type.
>
> We implement this by having a single BO in the descriptor set pool
> from which we source uniforms.
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/vulkan/anv_cmd_buffer.c | 3 +
> src/intel/vulkan/anv_descriptor_set.c | 238 +-
> src/intel/vulkan/anv_device.c | 22 ++
> src/intel/vulkan/anv_extensions.py| 1 +
> .../vulkan/anv_nir_apply_pipeline_layout.c| 52
> src/intel/vulkan/anv_private.h| 33 +++
> src/intel/vulkan/genX_cmd_buffer.c| 32 ++-
> 7 files changed, 367 insertions(+), 14 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_cmd_buffer.c
> b/src/intel/vulkan/anv_cmd_buffer.c
> index 8ef71b0ed9c..b14be94f470 100644
> --- a/src/intel/vulkan/anv_cmd_buffer.c
> +++ b/src/intel/vulkan/anv_cmd_buffer.c
> @@ -651,6 +651,7 @@ anv_isl_format_for_descriptor_type(VkDescriptorType type)
> switch (type) {
> case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
> case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
> + case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
>return ISL_FORMAT_R32G32B32A32_FLOAT;
>
> case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
> @@ -1039,6 +1040,8 @@ void anv_CmdPushDescriptorSetKHR(
> }
> break;
>
> + case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
> + unreachable("Invalid descriptor type for push descriptors");
>default:
> break;
>}
> diff --git a/src/intel/vulkan/anv_descriptor_set.c
> b/src/intel/vulkan/anv_descriptor_set.c
> index 3439f828900..2e5f2a1f288 100644
> --- a/src/intel/vulkan/anv_descriptor_set.c
> +++ b/src/intel/vulkan/anv_descriptor_set.c
> @@ -26,8 +26,10 @@
> #include
> #include
> #include
> +#include
>
> #include "util/mesa-sha1.h"
> +#include "vk_util.h"
>
> #include "anv_private.h"
>
> @@ -40,7 +42,8 @@ void anv_GetDescriptorSetLayoutSupport(
> const VkDescriptorSetLayoutCreateInfo* pCreateInfo,
> VkDescriptorSetLayoutSupport* pSupport)
> {
> - uint32_t surface_count[MESA_SHADER_STAGES] = { 0, };
> + int16_t surface_count[MESA_SHADER_STAGES] = { 0, };
> + int16_t inline_surface_indexes[MESA_SHADER_STAGES] = { -1, };
>
> for (uint32_t b = 0; b < pCreateInfo->bindingCount; b++) {
>const VkDescriptorSetLayoutBinding *binding =
> >pBindings[b];
> @@ -50,6 +53,15 @@ void anv_GetDescriptorSetLayoutSupport(
> /* There is no real limit on samplers */
> break;
>
> + case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
> + anv_foreach_stage(s, binding->stageFlags) {
> +if (inline_surface_indexes[s] < 0) {
> + inline_surface_indexes[s] = surface_count[s];
> + surface_count[s] += 1;
> +}
> + }
> + break;
> +
>case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
> if (binding->pImmutableSamplers) {
> for (uint32_t i = 0; i < binding->descriptorCount; i++) {
> @@ -118,6 +130,9 @@ VkResult anv_CreateDescriptorSetLayout(
> memset(set_layout, 0, sizeof(*set_layout));
> set_layout->ref_cnt = 1;
> set_layout->binding_count = max_binding + 1;
> + set_layout->inline_blocks_descriptor_index = -1;
> + memset(set_layout->inline_blocks_surface_indexes,
> + -1, sizeof(set_layout->inline_blocks_surface_indexes));
>
> for (uint32_t b = 0; b <= max_binding; b++) {
>/* Initialize all binding_layout entries to -1 */
> @@ -159,9 +174,24 @@ VkResult anv_CreateDescriptorSetLayout(
> #ifndef NDEBUG
>set_layout->binding[b].type = binding->descriptorType;
> #endif
> - set_layout->binding[b].array_size = binding->descriptorCount;
> - set_layout->binding[b].descriptor_index = set_layout->size;
> - set_layout->size += binding->descriptorCount;
> +
> + if (binding->descriptorType ==
> VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
> + /* We only a single descriptor entry for all the inline uniforms. */
> + set_layout->binding[b].array_size = 1;
> + if (set_layout->inline_blocks_descriptor_index < 0) {
> +set_layout->binding[b].descriptor_index =
> + set_layout->inline_blocks_descriptor_index =
> + set_layout->size;
> +set_layout->size += 1;
> + } else {
> +set_layout->binding[b].descriptor_index =
> + set_layout->inline_blocks_descriptor_index;
> + }
> + } else {
> + set_layout->binding[b].array_size = binding->descriptorCount;
> + set_layout->binding[b].descriptor_index = set_layout->size;
> + set_layout->size += binding->descriptorCount;
> + }
>
>switch (binding->descriptorType) {
>case VK_DESCRIPTOR_TYPE_SAMPLER:
>
Re: [Mesa-dev] [PATCH 1/5] anv/query: Increment an index while writing results
This series looks great to me. Thanks for the helpers everywhere :)
Reviewed-by: Lionel Landwerlin
On 15/09/2018 04:14, Jason Ekstrand wrote:
Instead of computing an index at the end which we hope maps to the
number of things written, just count the number of things as we go.
---
src/intel/vulkan/genX_query.c | 67 ---
1 file changed, 31 insertions(+), 36 deletions(-)
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 011db549c08..1b26401c9ff 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -249,18 +249,19 @@ VkResult genX(GetQueryPoolResults)(
*/
bool write_results = available || (flags & VK_QUERY_RESULT_PARTIAL_BIT);
- if (write_results) {
- switch (pool->type) {
- case VK_QUERY_TYPE_OCCLUSION: {
-cpu_write_query_result(pData, flags, 0, slot[2] - slot[1]);
-break;
- }
+ uint32_t idx = 0;
+ switch (pool->type) {
+ case VK_QUERY_TYPE_OCCLUSION:
+ if (write_results)
+cpu_write_query_result(pData, flags, idx, slot[2] - slot[1]);
+ idx++;
+ break;
- case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
-uint32_t statistics = pool->pipeline_statistics;
-uint32_t idx = 0;
-while (statistics) {
- uint32_t stat = u_bit_scan();
+ case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
+ uint32_t statistics = pool->pipeline_statistics;
+ while (statistics) {
+uint32_t stat = u_bit_scan();
+if (write_results) {
uint64_t result = slot[idx * 2 + 2] - slot[idx * 2 + 1];
/* WaDividePSInvocationCountBy4:HSW,BDW */
@@ -269,29 +270,28 @@ VkResult genX(GetQueryPoolResults)(
result >>= 2;
cpu_write_query_result(pData, flags, idx, result);
-
- idx++;
}
-assert(idx == util_bitcount(pool->pipeline_statistics));
-break;
+idx++;
}
+ assert(idx == util_bitcount(pool->pipeline_statistics));
+ break;
+ }
- case VK_QUERY_TYPE_TIMESTAMP: {
-cpu_write_query_result(pData, flags, 0, slot[1]);
-break;
- }
- default:
-unreachable("invalid pool type");
- }
- } else {
- status = VK_NOT_READY;
+ case VK_QUERY_TYPE_TIMESTAMP:
+ if (write_results)
+cpu_write_query_result(pData, flags, idx, slot[1]);
+ idx++;
+ break;
+
+ default:
+ unreachable("invalid pool type");
}
- if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
- uint32_t idx = (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) ?
-util_bitcount(pool->pipeline_statistics) : 1;
+ if (!write_results)
+ status = VK_NOT_READY;
+
+ if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)
cpu_write_query_result(pData, flags, idx, available);
- }
pData += stride;
if (pData >= data_end)
@@ -749,17 +749,17 @@ void genX(CmdCopyQueryPoolResults)(
for (uint32_t i = 0; i < queryCount; i++) {
slot_offset = (firstQuery + i) * pool->stride;
+ uint32_t idx = 0;
switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION:
compute_query_result(_buffer->batch, MI_ALU_REG2,
>bo, slot_offset + 8);
gpu_write_query_result(_buffer->batch, buffer, destOffset,
-flags, 0, CS_GPR(2));
+flags, idx++, CS_GPR(2));
break;
case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
uint32_t statistics = pool->pipeline_statistics;
- uint32_t idx = 0;
while (statistics) {
uint32_t stat = u_bit_scan();
@@ -774,9 +774,7 @@ void genX(CmdCopyQueryPoolResults)(
}
gpu_write_query_result(_buffer->batch, buffer, destOffset,
- flags, idx, CS_GPR(0));
-
-idx++;
+ flags, idx++, CS_GPR(0));
}
assert(idx == util_bitcount(pool->pipeline_statistics));
break;
@@ -794,9 +792,6 @@ void genX(CmdCopyQueryPoolResults)(
}
if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
- uint32_t idx = (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) ?
-util_bitcount(pool->pipeline_statistics) : 1;
-
emit_load_alu_reg_u64(_buffer->batch, CS_GPR(0),
>bo, slot_offset);
gpu_write_query_result(_buffer->batch, buffer, destOffset,
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Re: [Mesa-dev] [PATCH 2/5] anv/query: Write both dwords in emit_zero_queries
I did wonder about using a PIPE_CONTROL with WriteImmediate, but there
is a workaround in gpgpu mode so not really worth it...
On 15/09/2018 04:14, Jason Ekstrand wrote:
Each query slot is a uint64_t and we were only zeroing half of it.
Fixes: 7ec6e4e68980 "anv/query: implement multiview interactions"
---
src/intel/vulkan/genX_query.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 1b26401c9ff..817a3a3c4e2 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -347,6 +347,11 @@ emit_zero_queries(struct anv_cmd_buffer *cmd_buffer,
sdi.Address.offset = slot_offset + j * sizeof(uint64_t);
sdi.ImmediateData = 0ull;
}
+ anv_batch_emit(_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
+sdi.Address.bo = >bo;
+sdi.Address.offset = slot_offset + j * sizeof(uint64_t) + 4;
+sdi.ImmediateData = 0ull;
+ }
}
emit_query_availability(cmd_buffer, >bo, slot_offset);
}
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Re: [Mesa-dev] [PATCH 2/2] anv: add support for VK_EXT_inline_uniform_block
Hey Tapani,
Descriptors were kind of tricky to get my head around so thanks a lot
for looking into this.
Regarding this max values, there isn't really a limit with our hardware.
I just picked the minimum required by the spec.
I think the assert are somewhat unnecessary but I don't really object to
them.
Thanks again for your time on this!
-
Lionel
On 14/09/2018 11:32, Tapani Pälli wrote:
I can't say I know enough of all these parts but I went through the
API functions and tried to check that you have proper checks in place.
Will try to still review :)
I did not see any check against MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS
when creating pipeline layout. I'm not sure if such is necessary
(since it's implicit rule), do you think there should there be
check/assert?
one minor possible addition below ..
On 11.09.2018 23:22, Lionel Landwerlin wrote:
This new extension adds an implicitly allocated block of uniforms into
the descriptors sets through a new descriptor type. > We implement
this by having a single BO in the descriptor set pool
from which we source uniforms.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_cmd_buffer.c | 3 +
src/intel/vulkan/anv_descriptor_set.c | 238 +-
src/intel/vulkan/anv_device.c | 22 ++
src/intel/vulkan/anv_extensions.py | 1 +
.../vulkan/anv_nir_apply_pipeline_layout.c | 52
src/intel/vulkan/anv_private.h | 33 +++
src/intel/vulkan/genX_cmd_buffer.c | 32 ++-
7 files changed, 367 insertions(+), 14 deletions(-)
diff --git a/src/intel/vulkan/anv_cmd_buffer.c
b/src/intel/vulkan/anv_cmd_buffer.c
index 8ef71b0ed9c..b14be94f470 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -651,6 +651,7 @@
anv_isl_format_for_descriptor_type(VkDescriptorType type)
switch (type) {
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
+ case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
return ISL_FORMAT_R32G32B32A32_FLOAT;
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
@@ -1039,6 +1040,8 @@ void anv_CmdPushDescriptorSetKHR(
}
break;
+ case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
+ unreachable("Invalid descriptor type for push descriptors");
default:
break;
}
diff --git a/src/intel/vulkan/anv_descriptor_set.c
b/src/intel/vulkan/anv_descriptor_set.c
index 3439f828900..2e5f2a1f288 100644
--- a/src/intel/vulkan/anv_descriptor_set.c
+++ b/src/intel/vulkan/anv_descriptor_set.c
@@ -26,8 +26,10 @@
#include
#include
#include
+#include
#include "util/mesa-sha1.h"
+#include "vk_util.h"
#include "anv_private.h"
@@ -40,7 +42,8 @@ void anv_GetDescriptorSetLayoutSupport(
const VkDescriptorSetLayoutCreateInfo* pCreateInfo,
VkDescriptorSetLayoutSupport* pSupport)
{
- uint32_t surface_count[MESA_SHADER_STAGES] = { 0, };
+ int16_t surface_count[MESA_SHADER_STAGES] = { 0, };
+ int16_t inline_surface_indexes[MESA_SHADER_STAGES] = { -1, };
for (uint32_t b = 0; b < pCreateInfo->bindingCount; b++) {
const VkDescriptorSetLayoutBinding *binding =
>pBindings[b];
@@ -50,6 +53,15 @@ void anv_GetDescriptorSetLayoutSupport(
/* There is no real limit on samplers */
break;
+ case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
+ anv_foreach_stage(s, binding->stageFlags) {
+ if (inline_surface_indexes[s] < 0) {
+ inline_surface_indexes[s] = surface_count[s];
+ surface_count[s] += 1;
+ }
+ }
+ break;
+
case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
if (binding->pImmutableSamplers) {
for (uint32_t i = 0; i < binding->descriptorCount; i++) {
@@ -118,6 +130,9 @@ VkResult anv_CreateDescriptorSetLayout(
memset(set_layout, 0, sizeof(*set_layout));
set_layout->ref_cnt = 1;
set_layout->binding_count = max_binding + 1;
+ set_layout->inline_blocks_descriptor_index = -1;
+ memset(set_layout->inline_blocks_surface_indexes,
+ -1, sizeof(set_layout->inline_blocks_surface_indexes));
for (uint32_t b = 0; b <= max_binding; b++) {
/* Initialize all binding_layout entries to -1 */
@@ -159,9 +174,24 @@ VkResult anv_CreateDescriptorSetLayout(
#ifndef NDEBUG
set_layout->binding[b].type = binding->descriptorType;
#endif
- set_layout->binding[b].array_size = binding->descriptorCount;
- set_layout->binding[b].descriptor_index = set_layout->size;
- set_layout->size += binding->descriptorCount;
+
+ if (binding->descriptorType ==
VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
Maybe add here
assert(binding->descriptorCount % 4 == 0 &&
binding->descriptorCount <= MAX_INLINE_UNIFORM_BLOCK_SIZE);
Sure, added locally.
?
+ /* We only a single
[Mesa-dev] [Bug 107954] radv_shader_compile_to_nir doesn't check for bad entry point
https://bugs.freedesktop.org/show_bug.cgi?id=107954 Bug ID: 107954 Summary: radv_shader_compile_to_nir doesn't check for bad entry point Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/Vulkan/radeon Assignee: mesa-dev@lists.freedesktop.org Reporter: freedesk...@treblig.org QA Contact: mesa-dev@lists.freedesktop.org I screwed up my vulkan calling and ended up getting radv_shader_compile_to_nir to seg because it has: 251 entry_point = spirv_to_nir(spirv, module->size / 4, spec_entries, num_spec_entries, stage, entrypoint_name, _options, _options); 252 nir = entry_point->shader; assert(nir->info.stage == stage); it's dereferencing 'entry_point' on 252, but if the caller screws up entry_point can be NULL from spirv_to_nir; Could this failure be made cleaner? (Nothing else printed anything first before the seg by default; spirv_to_nir took a bit of an odd route; it checks b->entry_point = NULL then call vrn_fail that jumps back to it's setjmp handler and cleans up - so it's not obvious to me why it also has a ralloc_free(b), return NULL if the vtn_fail is going to take the setjmp). My screwup incidentally was a cut-and-paste where I'd copied the code for my vertex shader for my fragment shader and so I was trying to find the fragment shader entrypoint in my vertex shader. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] radv: Only allow 16 user SGPRs for compute on GFX9+.
Apparently for compute there are only 16 instead of the 32 for the graphics path. Fixes dEQP-VK.binding_model.descriptorset_random.sets16.noarray.ubolimitlow.sbolimitlow.imglimitlow.noiub.comp.0 CC: --- src/amd/vulkan/radv_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 968d96fc056..32d347ebd0f 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -689,7 +689,7 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx, if (ctx->shader_info->info.loads_push_constants) user_sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2; - uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16; + uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16; uint32_t remaining_sgprs = available_sgprs - user_sgpr_count; uint32_t num_desc_set = util_bitcount(ctx->shader_info->info.desc_set_used_mask); -- 2.19.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106187] Vulkan apps run on secondary GPU on multi-GPU system
https://bugs.freedesktop.org/show_bug.cgi?id=106187 --- Comment #13 from gloriouseggr...@gmail.com --- Hi, I've run into this issue with DOOM 2016 recently: so I have a ryzen 2400g and an rx 580 in this system both vulkan capable for whatever reason, doom renders on my vega in my 2400g and outputs to whatever display i have hooked up which is why i was only getting 20-30 fps on like medium settings with my RX 580 set as my primary gpu in bios. the only way I was able to get around this was to go in my bios and completely disable the integrated graphics Once I disabled the 2400g's igpu, my framerates returned to normal with my RX 580 Tested on both llvm-svn and mesa-git as well as llvm 6 + mesa 18.2 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] radv: Set the user SGPR MSB for Vega.
Otherwise using 32 user SGPRs would be broken. CC: --- src/amd/vulkan/radv_shader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index e05961339ca..51e0b7d65fc 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -408,6 +408,7 @@ radv_fill_shader_variant(struct radv_device *device, variant->code_size = radv_get_shader_binary_size(binary); variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | +S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) | S_00B12C_SCRATCH_EN(scratch_enabled); variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | -- 2.19.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: Optimize rebinding the same descriptor set.
On 9/16/18 2:21 AM, Bas Nieuwenhuizen wrote:
Thsi makes it cheaper to just change the dynamic offsets with
typo: This
Sounds reasonable.
Reviewed-by: Samuel Pitoiset
the same descriptor sets.
Suggested-by: Philip Rebohle
---
src/amd/vulkan/radv_cmd_buffer.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d492456d6b8..2f168321197 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2464,7 +2464,13 @@ void radv_CmdBindDescriptorSets(
for (unsigned i = 0; i < descriptorSetCount; ++i) {
unsigned idx = i + firstSet;
RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
- radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set,
idx);
+
+ /* If the set is already bound we only need to update the
+* (potentially changed) dynamic offsets. */
+ if (descriptors_state->sets[idx] != set ||
+ !(descriptors_state->valid & (1u << idx))) {
+ radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
set, idx);
+ }
for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
unsigned idx = j + layout->set[i +
firstSet].dynamic_offset_start;
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[Mesa-dev] [PATCH] radv: Use build ID if available for cache UUID.
To get an useful UUID for systems that have a non-useful mtime
for the binaries.
I started using using SHA1 to ensure we get reasonable mixing
in the various possibilities and the various build id lengths.
CC:
---
src/amd/vulkan/radv_device.c | 43 +---
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 8989ec3553f..a2a73089f27 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -45,22 +45,49 @@
#include "sid.h"
#include "gfx9d.h"
#include "addrlib/gfx9/chip/gfx9_enum.h"
+#include "util/build_id.h"
#include "util/debug.h"
+#include "util/mesa-sha1.h"
+
+static bool
+radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
+{
+ uint32_t timestamp;
+
+#ifdef HAVE_DL_ITERATE_PHDR
+ const struct build_id_note *note = NULL;
+ if ((note = build_id_find_nhdr_for_addr(ptr))) {
+ _mesa_sha1_update(ctx, build_id_data(note),
build_id_length(note));
+ } else
+#endif
+ if (disk_cache_get_function_timestamp(ptr, )) {
+ if (!timestamp) {
+ fprintf(stderr, "radv: The provided filesystem
timestamp for the cache is bogus!\n");
+ }
+
+ _mesa_sha1_update(ctx, , sizeof(timestamp));
+ } else
+ return false;
+ return true;
+}
static int
radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
{
- uint32_t mesa_timestamp, llvm_timestamp;
- uint16_t f = family;
+ struct mesa_sha1 ctx;
+ unsigned char sha1[20];
+ unsigned ptr_size = sizeof(void*);
memset(uuid, 0, VK_UUID_SIZE);
- if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid,
_timestamp) ||
- !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo,
_timestamp))
+
+ if (!radv_get_build_id(radv_device_get_cache_uuid, ) ||
+ !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, ))
return -1;
- memcpy(uuid, _timestamp, 4);
- memcpy((char*)uuid + 4, _timestamp, 4);
- memcpy((char*)uuid + 8, , 2);
- snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv%zd", sizeof(void
*));
+ _mesa_sha1_update(, , sizeof(family));
+ _mesa_sha1_update(, _size, sizeof(ptr_size));
+ _mesa_sha1_final(, sha1);
+
+ memcpy(uuid, sha1, VK_UUID_SIZE);
return 0;
}
--
2.19.0
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