date:20181025


Pushed. Thanks again!

Ccing stable in case the Fixes tag isnt enough for this to get picked up 
(since the previous cache fix this fixes was also backported)


On 24/10/18 11:51 am, David McFarland wrote:

After discussion with Timothy Arceri. disk_cache_get_function_identifier
was using only the first byte of the sha1 build-id.  Replace
disk_cache_get_function_identifier with implementation from
radv_get_build_id.  Instead of writing a uint32_t it now writes to a
mesa_sha1.  All drivers using disk_cache_get_function_identifier are
updated accordingly.

Reviewed-by: Timothy Arceri 
Fixes: 83ea8dd99bb1 ("util: add disk_cache_get_function_identifier()")
---
  src/amd/vulkan/radv_device.c | 22 +--
  src/gallium/drivers/nouveau/nouveau_screen.c | 29 -
  src/gallium/drivers/r600/r600_pipe_common.c  | 43 ++---
  src/gallium/drivers/radeonsi/si_pipe.c   | 64 ++--
  src/util/disk_cache.h| 16 +++--
  5 files changed, 81 insertions(+), 93 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index cf1132098d..81b558b91c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -49,24 +49,6 @@
  #include "util/debug.h"
  #include "util/mesa-sha1.h"
  
-static bool

-radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
-{
-   uint32_t timestamp;
-
-#ifdef HAVE_DL_ITERATE_PHDR
-   const struct build_id_note *note = NULL;
-   if ((note = build_id_find_nhdr_for_addr(ptr))) {
-   _mesa_sha1_update(ctx, build_id_data(note), 
build_id_length(note));
-   } else
-#endif
-   if (disk_cache_get_function_timestamp(ptr, )) {
-   _mesa_sha1_update(ctx, , sizeof(timestamp));
-   } else
-   return false;
-   return true;
-}
-
  static int
  radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
  {
@@ -77,8 +59,8 @@ radv_device_get_cache_uuid(enum radeon_family family, void 
*uuid)
memset(uuid, 0, VK_UUID_SIZE);
_mesa_sha1_init();
  
-	if (!radv_get_build_id(radv_device_get_cache_uuid, ) ||

-   !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, ))
+   if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, 
) ||
+   !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, 
))
return -1;
  
  	_mesa_sha1_update(, , sizeof(family));

diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c 
b/src/gallium/drivers/nouveau/nouveau_screen.c
index eb184d3559..d7898ed58f 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.c
+++ b/src/gallium/drivers/nouveau/nouveau_screen.c
@@ -148,20 +148,21 @@ nouveau_screen_bo_get_handle(struct pipe_screen *pscreen,
  static void
  nouveau_disk_cache_create(struct nouveau_screen *screen)
  {
-   uint32_t mesa_id;
-   char *mesa_id_str;
-   int res;
-
-   if (disk_cache_get_function_identifier(nouveau_disk_cache_create,
-  _id)) {
-  res = asprintf(_id_str, "%u", mesa_id);
-  if (res != -1) {
- screen->disk_shader_cache =
-disk_cache_create(nouveau_screen_get_name(>base),
-  mesa_id_str, 0);
- free(mesa_id_str);
-  }
-   }
+   struct mesa_sha1 ctx;
+   unsigned char sha1[20];
+   char cache_id[20 * 2 + 1];
+
+   _mesa_sha1_init();
+   if (!disk_cache_get_function_identifier(nouveau_disk_cache_create,
+   ))
+  return;
+
+   _mesa_sha1_final(, sha1);
+   disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
+
+   screen->disk_shader_cache =
+  disk_cache_create(nouveau_screen_get_name(>base),
+cache_id, 0);
  }
  
  int

diff --git a/src/gallium/drivers/r600/r600_pipe_common.c 
b/src/gallium/drivers/r600/r600_pipe_common.c
index 6b581242a1..e7c645611d 100644
--- a/src/gallium/drivers/r600/r600_pipe_common.c
+++ b/src/gallium/drivers/r600/r600_pipe_common.c
@@ -854,27 +854,28 @@ static void r600_disk_cache_create(struct 
r600_common_screen *rscreen)
if (rscreen->debug_flags & DBG_ALL_SHADERS)
return;
  
-	uint32_t mesa_id;

-   if (disk_cache_get_function_identifier(r600_disk_cache_create,
-  _id)) {
-   char *mesa_id_str;
-   int res = -1;
-
-   res = asprintf(_id_str, "%u", mesa_id);
-   if (res != -1) {
-   /* These flags affect shader compilation. */
-   uint64_t shader_debug_flags =
-   rscreen->debug_flags &
-   (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
-DBG_UNSAFE_MATH);
-
-   rscreen->disk_shader_cache =
-   disk_cache_create(r600_get_family_name(rscreen),
- mesa_id_str,
-

Re: [Mesa-dev] [Mesa-stable] [PATCH] radeonsi: add a workaround for bitfield_extract when count is 0




On 26/10/18 10:21 am, Tom Stellard wrote:

On 09/27/2018 10:01 PM, Timothy Arceri wrote:

On 28/9/18 2:53 am, Tom Stellard wrote:

On 09/24/2018 11:51 PM, Samuel Pitoiset wrote:



On 9/25/18 6:46 AM, Timothy Arceri wrote:

On 25/9/18 10:35 am, Marek Olšák wrote:

Do you know what's broken in LLVM? Or is it a problem with the ISA?


I haven't actually dug any further. Adding Samuel to see if he remembers more.

However according to the original bug report this is a regression when going 
from LLVM 6 to LLVM 7. I see the issue on both polaris and vega.


I didn't investigate either, it was just simpler to add a workaround in mesa 
than fixing LLVM.


If you have a test case, I can take a look.  There is still a lot of time
before 7.0.1 is released.


Hi Tom,

There is a renderdoc capture [1] attached to a RADV bug and an apitrace [2] 
attached to a seemingly unrelated radeonsi (VEGA) bug.

In the apitrace from Civ VI there is incorrect rendering behind the chinese 
emperor on the loading screen.

I've bisected the problem, reverting the following llvm commit fixes the issue.



Here is a proposed fix for LLVM: https://reviews.llvm.org/D53739
Would someone be able to test this?


Yes the issue is gone with that patch. Thanks!

If you let me know which LLVM versions this lands in I'll write some 
patches to disable the workaround in radeonsi and radv.




-Tom


commit ae2a6132b3b998b91943e4ef74fda37313f3145b
Author: Roman Lebedev 
Date:   Fri Jun 15 09:56:52 2018 +

 [InstCombine] Recommit: Fold  (x << y) >> y  ->  x & (-1 >> y)

 Summary:
 We already do it for splat constants, but not just values.
 Also, undef cases are mostly non-functional.

 The original commit was reverted because
 it broke tests for amdgpu backend, which i didn't check.
 Now, the backed was updated to recognize these new
 patterns, so we are good.

 https://bugs.llvm.org/show_bug.cgi?id=37603
 https://rise4fun.com/Alive/cplX

 Reviewers: spatel, craig.topper, mareko, bogner, rampitec, nhaehnle, arsenm

 Reviewed By: spatel, rampitec, nhaehnle

 Subscribers: wdng, nhaehnle, llvm-commits

 Differential Revision: https://reviews.llvm.org/D47980

 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334818 
91177308-0d34-0410-b5e6-96231b3b80d8

[1] https://bugs.freedesktop.org/show_bug.cgi?id=107276
[2] https://bugs.freedesktop.org/show_bug.cgi?id=104602



-Tom







Marek

On Fri, Sep 21, 2018 at 10:38 PM, Timothy Arceri  wrote:

This ports the fix from 3d41757788ac. Both LLVM 7 & 8 continue
to have this problem.

It fixes rendering issues in some menu and loading screens of
Civ VI which can be seen in the trace from bug 104602.

Note: This does not fix the black triangles on Vega for bug
104602.

Cc: mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107276
---
.../drivers/radeonsi/si_shader_tgsi_alu.c | 41 ++-
1 file changed, 30 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c 
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index f54d025aec0..814362bc963 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -494,18 +494,37 @@ static void emit_bfe(const struct lp_build_tgsi_action 
*action,
struct lp_build_emit_data *emit_data)
{
   struct si_shader_context *ctx = si_shader_context(bld_base);
-   LLVMValueRef bfe_sm5;
-   LLVMValueRef cond;
-
-   bfe_sm5 = ac_build_bfe(>ac, emit_data->args[0],
-  emit_data->args[1], emit_data->args[2],
-  emit_data->info->opcode == TGSI_OPCODE_IBFE);

-   /* Correct for GLSL semantics. */
-   cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntUGE, emit_data->args[2],
-LLVMConstInt(ctx->i32, 32, 0), "");
-   emit_data->output[emit_data->chan] =
-   LLVMBuildSelect(ctx->ac.builder, cond, emit_data->args[0], bfe_sm5, 
"");
+   if (HAVE_LLVM < 0x0700) {
+   LLVMValueRef bfe_sm5 =
+   ac_build_bfe(>ac, emit_data->args[0],
+emit_data->args[1], emit_data->args[2],
+emit_data->info->opcode == 
TGSI_OPCODE_IBFE);
+
+   /* Correct for GLSL semantics. */
+   LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntUGE, 
emit_data->args[2],
+ LLVMConstInt(ctx->i32, 32, 0), 
"");
+   emit_data->output[emit_data->chan] =
+   LLVMBuildSelect(ctx->ac.builder, cond, emit_data->args[0], 
bfe_sm5, "");
+   } else {
+   /* FIXME: LLVM 7 returns incorrect result when count is 0.
+*

Re: [Mesa-dev] [RFC] Allow fd.o to join forces with X.Org

2018-10-25 Thread Peter Hutterer

On Wed, Oct 17, 2018 at 02:37:25PM +0200, Daniel Vetter wrote:
> On Wed, Oct 17, 2018 at 2:05 PM Daniel Stone  wrote:
> >
> > On Tue, 16 Oct 2018 at 08:17, Peter Hutterer  
> > wrote:
> > > On Mon, Oct 15, 2018 at 10:49:24AM -0400, Harry Wentland wrote:
> > > > + \item Support free and open source projects through the 
> > > > freedesktop.org
> > > > + infrastructure. For projects outside the scope of item (\ref{1}) 
> > > > support
> > > > + extends to project hosting only.
> > > > +
> > >
> > > Yes to the idea but given that the remaining 11 pages cover all the 
> > > legalese
> > > for xorg I think we need to add at least a section of what "project 
> > > hosting"
> > > means. Even if it's just a "includes but is not limited to blah".  And 
> > > some
> > > addition to 4.1 Powers is needed to spell out what the BoD can do in 
> > > regards
> > > to fdo.
> >
> > Yeah, I think it makes sense. Some things we do:
> >   - provide hosted network services for collaborative development,
> > testing, and discussion, of open-source projects
> >   - administer, improve, and extend this suite of services as necessary
> >   - assist open-source projects in their use of these services
> >   - purchase, lease, or subscribe to, computing and networking
> > infrastructure allowing these services to be run
> 
> I fully agree that we should document all this. I don't think the
> bylaws are the right place though, much better to put that into
> policies that the board approves and which can be adapted as needed.
> Imo bylaws should cover the high-level mission and procedural details,
> as our "constitution", with the really high acceptance criteria of
> 2/3rd of all members approving any changes. Some of the early
> discussions tried to spell out a lot of the fd.o policies in bylaw
> changes, but then we realized it's all there already. All the details
> are much better served in policies enacted by the board, like we do
> with everything else.
> 
> As an example, let's look at XDC. Definitely one of the biggest things
> the foundation does, with handling finances, travel sponsoring grants,
> papers committee, and acquiring lots of sponsors. None of this is
> spelled out in the bylaws, it's all in policies that the board
> deliberates and approves. I think this same approach will also work
> well for fd.o.
> 
> And if members are unhappy with what the board does, they can fix in
> the next election by throwing out the unwanted directors.

yeah, fair call. though IMO in that case we can just reduce to

   \item Support free and open source projects through the freedesktop.org
   infrastructure.

because my gripe is less with the fdo bit but more with defining what
"project hosting" means, given that we use that term to exclude fdo projects
from getting anything else. I think just dropping that bit is sufficient.

Cheers,
   Peter
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Re: [Mesa-dev] [PATCH 07/31] nir/opt_if: Rework condition propagation


Looks ok to me.

Reviewed-by: Timothy Arceri 

On 23/10/18 9:13 am, Jason Ekstrand wrote:

Instead of doing our own constant folding, we just emit instructions and
let constant folding happen.  This is substantially simpler and lets us
use the nir_imm_bool helper instead of dealing with the const_value's
ourselves.
---
  src/compiler/nir/nir_opt_if.c | 91 ---
  1 file changed, 30 insertions(+), 61 deletions(-)

diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index 0c94aa170b5..60368a0259e 100644
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -377,31 +377,15 @@ opt_if_loop_terminator(nir_if *nif)
 return true;
  }
  
-static void

-replace_if_condition_use_with_const(nir_builder *b, nir_src *use,
-nir_const_value nir_boolean,
-bool if_condition)
-{
-   /* Create const */
-   nir_ssa_def *const_def = nir_build_imm(b, 1, 32, nir_boolean);
-
-   /* Rewrite use to use const */
-   nir_src new_src = nir_src_for_ssa(const_def);
-   if (if_condition)
-  nir_if_rewrite_condition(use->parent_if, new_src);
-   else
-  nir_instr_rewrite_src(use->parent_instr, use, new_src);
-}
-
  static bool
-evaluate_if_condition(nir_if *nif, nir_cursor cursor, uint32_t *value)
+evaluate_if_condition(nir_if *nif, nir_cursor cursor, bool *value)
  {
 nir_block *use_block = nir_cursor_current_block(cursor);
 if (nir_block_dominates(nir_if_first_then_block(nif), use_block)) {
-  *value = NIR_TRUE;
+  *value = true;
return true;
 } else if (nir_block_dominates(nir_if_first_else_block(nif), use_block)) {
-  *value = NIR_FALSE;
+  *value = false;
return true;
 } else {
return false;
@@ -460,52 +444,31 @@ propagate_condition_eval(nir_builder *b, nir_if *nif, 
nir_src *use_src,
   nir_src *alu_use, nir_alu_instr *alu,
   bool is_if_condition)
  {
-   bool progress = false;
+   bool bool_value;
+   if (!evaluate_if_condition(nif, b->cursor, _value))
+  return false;
  
-   nir_const_value bool_value;

 b->cursor = nir_before_src(alu_use, is_if_condition);
-   if (nir_op_infos[alu->op].num_inputs == 1) {
-  assert(alu->op == nir_op_inot || alu->op == nir_op_b2i);
-
-  if (evaluate_if_condition(nif, b->cursor, _value.u32[0])) {
- assert(nir_src_bit_size(alu->src[0].src) == 32);
-
- nir_const_value result =
-nir_eval_const_opcode(alu->op, 1, 32, _value);
  
- replace_if_condition_use_with_const(b, alu_use, result,

- is_if_condition);
- progress = true;
+   nir_ssa_def *def[2] = { };
+   for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
+  if (alu->src[i].src.ssa == use_src->ssa) {
+ def[i] = nir_imm_bool(b, bool_value);
+  } else {
+ def[i] = alu->src[i].src.ssa;
}
-   } else {
-  assert(alu->op == nir_op_ior || alu->op == nir_op_iand);
-
-  if (evaluate_if_condition(nif, b->cursor, _value.u32[0])) {
- nir_ssa_def *def[2];
- for (unsigned i = 0; i < 2; i++) {
-if (alu->src[i].src.ssa == use_src->ssa) {
-   def[i] = nir_build_imm(b, 1, 32, bool_value);
-} else {
-   def[i] = alu->src[i].src.ssa;
-}
- }
-
- nir_ssa_def *nalu =
-nir_build_alu(b, alu->op, def[0], def[1], NULL, NULL);
-
- /* Rewrite use to use new alu instruction */
- nir_src new_src = nir_src_for_ssa(nalu);
+   }
+   nir_ssa_def *nalu = nir_build_alu(b, alu->op, def[0], def[1], NULL, NULL);
  
- if (is_if_condition)

-nir_if_rewrite_condition(alu_use->parent_if, new_src);
- else
-nir_instr_rewrite_src(alu_use->parent_instr, alu_use, new_src);
+   /* Rewrite use to use new alu instruction */
+   nir_src new_src = nir_src_for_ssa(nalu);
  
- progress = true;

-  }
-   }
+   if (is_if_condition)
+  nir_if_rewrite_condition(alu_use->parent_if, new_src);
+   else
+  nir_instr_rewrite_src(alu_use->parent_instr, alu_use, new_src);
  
-   return progress;

+   return true;
  }
  
  static bool

@@ -527,11 +490,17 @@ evaluate_condition_use(nir_builder *b, nir_if *nif, 
nir_src *use_src,
  {
 bool progress = false;
  
-   nir_const_value value;

 b->cursor = nir_before_src(use_src, is_if_condition);
  
-   if (evaluate_if_condition(nif, b->cursor, [0])) {

-  replace_if_condition_use_with_const(b, use_src, value, is_if_condition);
+   bool bool_value;
+   if (evaluate_if_condition(nif, b->cursor, _value)) {
+  /* Rewrite use to use const */
+  nir_src imm_src = nir_src_for_ssa(nir_imm_bool(b, bool_value));
+  if (is_if_condition)
+ nir_if_rewrite_condition(use_src->parent_if, imm_src);
+  else
+ nir_instr_rewrite_src(use_src->parent_instr,

[Mesa-dev] [PATCH] intel/blorp: Define the clear value bounds for HiZ clears

2018-10-25 Thread nanleychery

From: Nanley Chery 

Follow the restriction of making sure the clear value is between the min
and max values defined in CC_VIEWPORT. Avoids a simulator warning for
some piglit tests, one of them being:

./bin/depthstencil-render-miplevels 146 d=z32f_s8

Jason found this to make a GPU hang go away on SKL.

Fixes: 09948151ab1d5184b4dd9052bb1f710fa1e00a7b
   ("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP")
---
 src/intel/blorp/blorp_genX_exec.h | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 50341ab0ecf..7a8c45dbee5 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1628,6 +1628,20 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
 */
blorp_emit_3dstate_multisample(batch, params);
 
+   /* From the BDW PRM Volume 7, Depth Buffer Clear:
+*
+*The clear value must be between the min and max depth values
+*(inclusive) defined in the CC_VIEWPORT. If the depth buffer format is
+*D32_FLOAT, then +/-DENORM values are also allowed.
+*
+* Set the bounds to match our hardware limits, [0.0, 1.0].
+*/
+   if (params->depth.enabled && params->hiz_op == ISL_AUX_OP_FAST_CLEAR) {
+  assert(params->depth.clear_color.f32[0] >= 0.0f);
+  assert(params->depth.clear_color.f32[0] <= 1.0f);
+  blorp_emit_cc_viewport(batch);
+   }
+
/* If we can't alter the depth stencil config and multiple layers are
 * involved, the HiZ op will fail. This is because the op requires that a
 * new config is emitted for each additional layer.
-- 
2.19.0

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Re: [Mesa-dev] [PATCH] st/mesa: Don't record garbage streamout information in the non-SSO case.


This is much nicer.

Reviewed-by: Timothy Arceri 

On 25/10/18 8:16 pm, Kenneth Graunke wrote:

In the non-SSO case, where multiple shader stages are linked together,
we were recording garbage pipe_stream_output_info structures for all
but the last enabled geometry-processing stage.

Specifically, we were using the gl_transform_feedback_info from
shader_program->last_vert_prog (the stage whose outputs will be
recorded)...but were pairing it with the output varying mappings
from the current shader stage.  For example, a program with a VS and
GS, the VS's pipe_shader_state would have a pipe_stream_output_info
based on the GS transform feedback info, but the VS output mapping.

This generally worked out okay because only the pipe_stream_output_info
for the last stage really matters - the others can be ignored.  However,
we'd like to avoid confusing the pipe driver.  In particular, my new
driver translates the stream out information to hardware packets at
bind_{vs,tes,gs}_state() time...and was hitting asserts about garbage
varyings that didn't exist.

This patch changes st/mesa to record a blank pipe_stream_output_info
with num_outputs = 0 for all stages prior to last_vert_prog.  The last
one is captured as normal.

(In the fully-SSO case, nothing should change - each program contains
a single shader stage, so last_vert_prog *is* the current shader.)

Tested with llvmpipe (piglit's gpu profile), and freedreno (a3xx,
gpu profile with -t transform.feedback).  Fixes several hundred CTS
tests on my new driver.
---
  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 20 ++--
  src/mesa/state_tracker/st_glsl_to_tgsi.h   |  7 +--
  src/mesa/state_tracker/st_program.c| 19 ---
  3 files changed, 15 insertions(+), 31 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index dea91c7a189..19bd46d6097 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -7467,25 +7467,17 @@ st_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
  }
  
  void

-st_translate_stream_output_info(glsl_to_tgsi_visitor *glsl_to_tgsi,
-const ubyte outputMapping[],
-struct pipe_stream_output_info *so)
-{
-   if (!glsl_to_tgsi->shader_program->last_vert_prog)
-  return;
-
-   struct gl_transform_feedback_info *info =
-  glsl_to_tgsi->shader_program->last_vert_prog->sh.LinkedTransformFeedback;
-   st_translate_stream_output_info2(info, outputMapping, so);
-}
-
-void
-st_translate_stream_output_info2(struct gl_transform_feedback_info *info,
+st_translate_stream_output_info(struct gl_transform_feedback_info *info,
  const ubyte outputMapping[],
  struct pipe_stream_output_info *so)
  {
 unsigned i;
  
+   if (!info) {

+  so->num_outputs = 0;
+  return;
+   }
+
 for (i = 0; i < info->NumOutputs; i++) {
so->output[i].register_index =
   outputMapping[info->Outputs[i].OutputRegister];
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.h 
b/src/mesa/state_tracker/st_glsl_to_tgsi.h
index 8ccfff9bd37..fa6c0e02712 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.h
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.h
@@ -58,12 +58,7 @@ void free_glsl_to_tgsi_visitor(struct glsl_to_tgsi_visitor 
*v);
  GLboolean st_link_shader(struct gl_context *ctx, struct gl_shader_program 
*prog);
  
  void

-st_translate_stream_output_info(struct glsl_to_tgsi_visitor *glsl_to_tgsi,
-const ubyte outputMapping[],
-struct pipe_stream_output_info *so);
-
-void
-st_translate_stream_output_info2(struct gl_transform_feedback_info *info,
+st_translate_stream_output_info(struct gl_transform_feedback_info *info,
  const ubyte outputMapping[],
  struct pipe_stream_output_info *so);
  
diff --git a/src/mesa/state_tracker/st_program.c b/src/mesa/state_tracker/st_program.c

index af86c47b945..3bc7b0649c4 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -458,12 +458,9 @@ st_translate_vertex_program(struct st_context *st,
 }
  
 if (stvp->shader_program) {

-  struct gl_program *prog = stvp->shader_program->last_vert_prog;
-  if (prog) {
- st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
-  stvp->result_to_output,
-  >tgsi.stream_output);
-  }
+  st_translate_stream_output_info(stvp->Base.sh.LinkedTransformFeedback,
+  stvp->result_to_output,
+  >tgsi.stream_output);
  
st_store_ir_in_disk_cache(st, >Base, true);

return true;
@@ -505,7 +502,7 @@

Re: [Mesa-dev] [Mesa-stable] [PATCH] radeonsi: add a workaround for bitfield_extract when count is 0

2018-10-25 Thread Tom Stellard

On 09/27/2018 10:01 PM, Timothy Arceri wrote:
> On 28/9/18 2:53 am, Tom Stellard wrote:
>> On 09/24/2018 11:51 PM, Samuel Pitoiset wrote:
>>>
>>>
>>> On 9/25/18 6:46 AM, Timothy Arceri wrote:
 On 25/9/18 10:35 am, Marek Olšák wrote:
> Do you know what's broken in LLVM? Or is it a problem with the ISA?

 I haven't actually dug any further. Adding Samuel to see if he remembers 
 more.

 However according to the original bug report this is a regression when 
 going from LLVM 6 to LLVM 7. I see the issue on both polaris and vega.
>>>
>>> I didn't investigate either, it was just simpler to add a workaround in 
>>> mesa than fixing LLVM.
>>
>> If you have a test case, I can take a look.  There is still a lot of time
>> before 7.0.1 is released.
> 
> Hi Tom,
> 
> There is a renderdoc capture [1] attached to a RADV bug and an apitrace [2] 
> attached to a seemingly unrelated radeonsi (VEGA) bug.
> 
> In the apitrace from Civ VI there is incorrect rendering behind the chinese 
> emperor on the loading screen.
> 
> I've bisected the problem, reverting the following llvm commit fixes the 
> issue.
> 

Here is a proposed fix for LLVM: https://reviews.llvm.org/D53739
Would someone be able to test this?

-Tom

> commit ae2a6132b3b998b91943e4ef74fda37313f3145b
> Author: Roman Lebedev 
> Date:   Fri Jun 15 09:56:52 2018 +
> 
> [InstCombine] Recommit: Fold  (x << y) >> y  ->  x & (-1 >> y)
> 
> Summary:
> We already do it for splat constants, but not just values.
> Also, undef cases are mostly non-functional.
> 
> The original commit was reverted because
> it broke tests for amdgpu backend, which i didn't check.
> Now, the backed was updated to recognize these new
> patterns, so we are good.
> 
> https://bugs.llvm.org/show_bug.cgi?id=37603
> https://rise4fun.com/Alive/cplX
> 
> Reviewers: spatel, craig.topper, mareko, bogner, rampitec, nhaehnle, 
> arsenm
> 
> Reviewed By: spatel, rampitec, nhaehnle
> 
> Subscribers: wdng, nhaehnle, llvm-commits
> 
> Differential Revision: https://reviews.llvm.org/D47980
> 
> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334818 
> 91177308-0d34-0410-b5e6-96231b3b80d8
> 
> [1] https://bugs.freedesktop.org/show_bug.cgi?id=107276
> [2] https://bugs.freedesktop.org/show_bug.cgi?id=104602
> 
>>
>> -Tom
>>
>>>

>
> Marek
>
> On Fri, Sep 21, 2018 at 10:38 PM, Timothy Arceri  
> wrote:
>> This ports the fix from 3d41757788ac. Both LLVM 7 & 8 continue
>> to have this problem.
>>
>> It fixes rendering issues in some menu and loading screens of
>> Civ VI which can be seen in the trace from bug 104602.
>>
>> Note: This does not fix the black triangles on Vega for bug
>> 104602.
>>
>> Cc: mesa-sta...@lists.freedesktop.org
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107276
>> ---
>>.../drivers/radeonsi/si_shader_tgsi_alu.c | 41 ++-
>>1 file changed, 30 insertions(+), 11 deletions(-)
>>
>> diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c 
>> b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
>> index f54d025aec0..814362bc963 100644
>> --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
>> +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
>> @@ -494,18 +494,37 @@ static void emit_bfe(const struct 
>> lp_build_tgsi_action *action,
>>struct lp_build_emit_data *emit_data)
>>{
>>   struct si_shader_context *ctx = si_shader_context(bld_base);
>> -   LLVMValueRef bfe_sm5;
>> -   LLVMValueRef cond;
>> -
>> -   bfe_sm5 = ac_build_bfe(>ac, emit_data->args[0],
>> -  emit_data->args[1], emit_data->args[2],
>> -  emit_data->info->opcode == 
>> TGSI_OPCODE_IBFE);
>>
>> -   /* Correct for GLSL semantics. */
>> -   cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntUGE, 
>> emit_data->args[2],
>> -LLVMConstInt(ctx->i32, 32, 0), "");
>> -   emit_data->output[emit_data->chan] =
>> -   LLVMBuildSelect(ctx->ac.builder, cond, 
>> emit_data->args[0], bfe_sm5, "");
>> +   if (HAVE_LLVM < 0x0700) {
>> +   LLVMValueRef bfe_sm5 =
>> +   ac_build_bfe(>ac, emit_data->args[0],
>> +emit_data->args[1], 
>> emit_data->args[2],
>> +emit_data->info->opcode == 
>> TGSI_OPCODE_IBFE);
>> +
>> +   /* Correct for GLSL semantics. */
>> +   LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, 
>> LLVMIntUGE, emit_data->args[2],
>> + LLVMConstInt(ctx->i32,

Re: [Mesa-dev] [PATCH mesa] util: remove unnecessary random whitespaces

2018-10-25 Thread Eric Anholt

Ian Romanick  writes:

> On 10/25/2018 05:13 AM, Eric Engestrom wrote:
>> On Thursday, 2018-10-25 17:54:16 +1100, Timothy Arceri wrote:
>>> On 25/10/18 7:42 am, Ian Romanick wrote:
 On 10/23/2018 04:15 AM, Eric Engestrom wrote:
> Suggested-by: Timothy Arceri 
>>>
>>> Um no :P I suggested you fix the formatting in your patch to match the Mesa
>>> style.
>> 
>> Right, sorry, you suggested fixing the formatting, but not the fix
>> I went with, so I should've dropped this tag.
>> 
>>>
> Signed-off-by: Eric Engestrom 
> ---
> Timothy, I opted to remove them all instead of adding even more, as it
> would break again next time something changes (the set_foreach() one was
> already broken before my patch for instance) and result in lots of
> unnecessary churn for seemingly no gain, and I don't like hiding the
> backslash away (it hinders readability).

 NAK... we use this formatting everywhere in Mesa.  The point is to move
 the \ characters out of the way.  When you're trying to read a
 multi-line macro, they are distracting, so it is nice to move them over.
>> 
>> I don't have the same opinion, but respecting mesa style is the point
>> here, so I added those whitespace chars, squashed them in the previous
>> patches, and pushed them.
>> 
>> Sorry for this patch :)
>
> It's always worth a try. :)  Everyone has aspects of the Mesa style that
> they don't like.  Sending out a patch like this is a good way to test
> the waters about changing the style.  It does happen from time to time.
> It's better to do it like this than to try to sneak it in a big patch
> series.

I would love to see this style change.  emacs in my experience does
horrible things to these weird (inconsistently-)aligned \s, so I have to
manually align them and fail.


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[Mesa-dev] [PATCH] gallium: rework PIPE_HANDLE_USAGE_* flags

2018-10-25 Thread Marek Olšák

From: Marek Olšák 

Only radeonsi uses them, so adjust them to match its needs.
---
 src/gallium/auxiliary/renderonly/renderonly.c  |  2 +-
 src/gallium/auxiliary/vl/vl_winsys_dri.c   |  2 +-
 src/gallium/auxiliary/vl/vl_winsys_dri3.c  |  4 ++--
 src/gallium/drivers/etnaviv/etnaviv_resource.c |  2 +-
 src/gallium/drivers/r600/r600_texture.c|  2 +-
 src/gallium/drivers/radeonsi/si_texture.c  |  7 ---
 src/gallium/drivers/tegra/tegra_screen.c   |  3 +--
 src/gallium/include/pipe/p_defines.h   |  8 +++-
 src/gallium/state_trackers/dri/dri2.c  | 18 --
 src/gallium/state_trackers/dri/drisw.c |  2 +-
 src/gallium/state_trackers/nine/swapchain9.c   |  5 ++---
 src/gallium/state_trackers/va/buffer.c |  2 +-
 src/gallium/state_trackers/va/surface.c|  6 ++
 src/gallium/state_trackers/vdpau/output.c  |  2 +-
 src/gallium/state_trackers/vdpau/surface.c |  2 +-
 src/gallium/state_trackers/xa/xa_tracker.c |  4 ++--
 .../winsys/sw/wrapper/wrapper_sw_winsys.c  |  4 ++--
 src/mesa/state_tracker/st_vdpau.c  |  2 +-
 18 files changed, 35 insertions(+), 42 deletions(-)

diff --git a/src/gallium/auxiliary/renderonly/renderonly.c 
b/src/gallium/auxiliary/renderonly/renderonly.c
index f83910a9404..d6a34400937 100644
--- a/src/gallium/auxiliary/renderonly/renderonly.c
+++ b/src/gallium/auxiliary/renderonly/renderonly.c
@@ -131,21 +131,21 @@ renderonly_create_gpu_import_for_resource(struct 
pipe_resource *rsc,
int fd, err;
struct winsys_handle handle = {
   .type = WINSYS_HANDLE_TYPE_FD
};
 
scanout = CALLOC_STRUCT(renderonly_scanout);
if (!scanout)
   return NULL;
 
status = screen->resource_get_handle(screen, NULL, rsc, ,
- PIPE_HANDLE_USAGE_READ_WRITE);
+ PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE);
if (!status)
   goto free_scanout;
 
scanout->stride = handle.stride;
fd = handle.handle;
 
err = drmPrimeFDToHandle(ro->kms_fd, fd, >handle);
close(fd);
 
if (err < 0) {
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri.c 
b/src/gallium/auxiliary/vl/vl_winsys_dri.c
index 137885d9475..1905516a761 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri.c
@@ -242,21 +242,21 @@ vl_dri2_screen_texture_from_drawable(struct vl_screen 
*vscreen, void *drawable)
templ.width0 = reply->width;
templ.height0 = reply->height;
templ.depth0 = 1;
templ.array_size = 1;
templ.usage = PIPE_USAGE_DEFAULT;
templ.bind = PIPE_BIND_RENDER_TARGET;
templ.flags = 0;
 
tex = scrn->base.pscreen->resource_from_handle(scrn->base.pscreen, ,
   _handle,
-  
PIPE_HANDLE_USAGE_READ_WRITE);
+  
PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE);
free(reply);
 
return tex;
 }
 
 static struct u_rect *
 vl_dri2_screen_get_dirty_area(struct vl_screen *vscreen)
 {
struct vl_dri_screen *scrn = (struct vl_dri_screen *)vscreen;
assert(scrn);
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c 
b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
index d6a1ec0bfdd..152d28e59fc 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
@@ -265,21 +265,21 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn)
} else {
   templ.bind |= PIPE_BIND_SCANOUT | PIPE_BIND_SHARED;
   buffer->texture = (scrn->output_texture) ? scrn->output_texture :
 
scrn->base.pscreen->resource_create(scrn->base.pscreen, );
   if (!buffer->texture)
  goto unmap_shm;
   pixmap_buffer_texture = buffer->texture;
}
memset(, 0, sizeof(whandle));
whandle.type= WINSYS_HANDLE_TYPE_FD;
-   usage = PIPE_HANDLE_USAGE_EXPLICIT_FLUSH | PIPE_HANDLE_USAGE_READ;
+   usage = PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
scrn->base.pscreen->resource_get_handle(scrn->base.pscreen, NULL,
pixmap_buffer_texture, ,
usage);
buffer_fd = whandle.handle;
buffer->pitch = whandle.stride;
buffer->width = templ.width0;
buffer->height = templ.height0;
 
xcb_dri3_pixmap_from_buffer(scrn->conn,
(pixmap = xcb_generate_id(scrn->conn)),
@@ -500,21 +500,21 @@ dri3_get_front_buffer(struct vl_dri3_screen *scrn)
templ.format = vl_dri2_format_for_depth(>base, bp_reply->depth);
templ.target = PIPE_TEXTURE_2D;
templ.last_level = 0;
templ.width0 = bp_reply->width;
templ.height0 = bp_reply->height;
templ.depth0 = 1;
templ.array_size = 1;
scrn->front_buffer->texture =
   scrn->base.pscreen->resource_from_handle(scrn->base.pscreen,
, ,
-   PIPE_HANDLE_USAGE_READ_WRITE);
+

Re: [Mesa-dev] [PATCH] anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREG


Reviewed-by: Lionel Landwerlin 

On 25/10/2018 18:14, Anuj Phogat wrote:

The default setting of this bit is not the desirable behavior.
WA_1406697149

Signed-off-by: Anuj Phogat 
---
  src/intel/genxml/gen11.xml | 1 +
  src/intel/vulkan/genX_cmd_buffer.c | 7 +++
  2 files changed, 8 insertions(+)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index c69d7dc89c2..454ef8f4103 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3546,6 +3546,7 @@

  
  
+
  
  
  
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 43a02f22567..ed88157170d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1617,6 +1617,13 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer 
*cmd_buffer,
 uint32_t l3cr;
 anv_pack_struct(, GENX(L3CNTLREG),
 .SLMEnable = has_slm,
+#if GEN_GEN == 11
+   /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
+* in L3CNTLREG register. The default setting of the bit is not the
+* desirable behavior.
+   */
+   .ErrorDetectionBehaviorControl = true,
+#endif
 .URBAllocation = cfg->n[GEN_L3P_URB],
 .ROAllocation = cfg->n[GEN_L3P_RO],
 .DCAllocation = cfg->n[GEN_L3P_DC],



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Re: [Mesa-dev] [PATCH] i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREG


Reviewed-by: Lionel Landwerlin 

On 25/10/2018 18:13, Anuj Phogat wrote:

The default setting of this bit is not the desirable behavior.
WA_1406697149

Signed-off-by: Anuj Phogat 
---
  src/mesa/drivers/dri/i965/brw_defines.h  | 1 +
  src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++
  2 files changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 97a787a2ab3..897c91aa31e 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1646,6 +1646,7 @@ enum brw_pixel_shader_coverage_mask_mode {
  # define GEN8_L3CNTLREG_DC_ALLOC_MASK  INTEL_MASK(24, 18)
  # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT25
  # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
+# define GEN8_L3CNTLREG_EDBC_NO_HANG   (1 << 9)
  
  #define GEN10_CACHE_MODE_SS0x0e420

  #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 7f20579fb87..60b72bf4ab3 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -79,6 +79,13 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
brw_load_register_imm32(brw, HALF_SLICE_CHICKEN7,
TEXEL_OFFSET_FIX_MASK |
TEXEL_OFFSET_FIX_ENABLE);
+
+  /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
+   * in L3CNTLREG register. The default setting of the bit is not the
+   * desirable behavior.
+   */
+  brw_load_register_imm32(brw, GEN8_L3CNTLREG,
+  GEN8_L3CNTLREG_EDBC_NO_HANG);
 }
  
 if (devinfo->gen == 10 || devinfo->gen == 11) {



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[Mesa-dev] [PATCH 01/14] util/gen_xmlpool: use argparse for argument handling

2018-10-25 Thread Dylan Baker

This is a little cleaner than just looking at sys.argv, but it's also
going to allow us to handle the differences in the way meson and
autotools handle translations more cleanly.
---
 src/util/xmlpool/gen_xmlpool.py | 20 +---
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/src/util/xmlpool/gen_xmlpool.py b/src/util/xmlpool/gen_xmlpool.py
index 56a67bcab55..b40f295738e 100644
--- a/src/util/xmlpool/gen_xmlpool.py
+++ b/src/util/xmlpool/gen_xmlpool.py
@@ -9,25 +9,23 @@
 
 from __future__ import print_function
 
+import argparse
 import io
 import sys
 import gettext
 import re
 
+parser = argparse.ArgumentParser()
+parser.add_argument('template')
+parser.add_argument('localedir')
+parser.add_argument('languages', nargs='*')
+args = parser.parse_args()
 
 if sys.version_info < (3, 0):
 gettext_method = 'ugettext'
 else:
 gettext_method = 'gettext'
 
-# Path to t_options.h
-template_header_path = sys.argv[1]
-
-localedir = sys.argv[2]
-
-# List of supported languages
-languages = sys.argv[3:]
-
 # Escape special characters in C strings
 def escapeCString (s):
 escapeSeqs = {'\a' : '\\a', '\b' : '\\b', '\f' : '\\f', '\n' : '\\n',
@@ -166,9 +164,9 @@ def expandMatches (matches, translations, end=None):
 # Compile a list of translation classes to all supported languages.
 # The first translation is always a NullTranslations.
 translations = [("en", gettext.NullTranslations())]
-for lang in languages:
+for lang in args.languages:
 try:
-trans = gettext.translation ("options", localedir, [lang])
+trans = gettext.translation ("options", args.localedir, [lang])
 except IOError:
 sys.stderr.write ("Warning: language '%s' not found.\n" % lang)
 continue
@@ -188,7 +186,7 @@ 
print("/***\
 
 # Process the options template and generate options.h with all
 # translations.
-template = io.open (template_header_path, mode="rt", encoding='utf-8')
+template = io.open (args.template, mode="rt", encoding='utf-8')
 descMatches = []
 for line in template:
 if len(descMatches) > 0:
-- 
2.19.1

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Re: [Mesa-dev] [PATCH] nir: Divergence Analysis

I'm going to try to review this more thoroughly for content later.  For
now, I'm going to send a bunch of notes about formatting / Mesa coding
conventions.


On 10/08/2018 04:04 AM, Daniel Schürmann wrote:
> ---
>  src/compiler/nir/meson.build   |   1 +
>  src/compiler/nir/nir.h |   2 +
>  src/compiler/nir/nir_divergence_analysis.c | 333 +
>  3 files changed, 336 insertions(+)
>  create mode 100644 src/compiler/nir/nir_divergence_analysis.c
> 
> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> index 090aa7a628..aabfeee02c 100644
> --- a/src/compiler/nir/meson.build
> +++ b/src/compiler/nir/meson.build
> @@ -96,6 +96,7 @@ files_libnir = files(
>'nir_control_flow_private.h',
>'nir_deref.c',
>'nir_deref.h',
> +  'nir_divergence_analysis.c',
>'nir_dominance.c',
>'nir_format_convert.h',
>'nir_from_ssa.c',
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index e0df95c391..374280a1cc 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -3010,6 +3010,8 @@ void nir_convert_loop_to_lcssa(nir_loop *loop);
>   */
>  bool nir_convert_from_ssa(nir_shader *shader, bool phi_webs_only);
>  
> +bool* nir_divergence_analysis(nir_shader *shader);
> +

bool *nir_divergence_analysis(nir_shader *shader);

>  bool nir_lower_phis_to_regs_block(nir_block *block);
>  bool nir_lower_ssa_defs_to_regs_block(nir_block *block);
>  bool nir_rematerialize_derefs_in_use_blocks_impl(nir_function_impl *impl);
> diff --git a/src/compiler/nir/nir_divergence_analysis.c 
> b/src/compiler/nir/nir_divergence_analysis.c
> new file mode 100644
> index 00..d91f4e55e6
> --- /dev/null
> +++ b/src/compiler/nir/nir_divergence_analysis.c
> @@ -0,0 +1,333 @@
> +/*
> + * Copyright © 2018 Valve Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + *Daniel Schürmann (daniel.schuerm...@campus.tu-berlin.de)
> + *

We stopped including "Authors" in the header comment years ago.  GIT
tracks this for us. :)

> + */
> +
> +#include "nir.h"
> +#include "nir_worklist.h"
> +
> +/* This pass computes for each ssa definition if it is uniform.
> + * That is, the variable has the same value for all invocations
> + * of the group.
> + *
> + * This algorithm implements "The Simple Divergence Analysis" from
> + * Diogo Sampaio, Rafael De Souza, Sylvain Collange, Fernando Magno Quintão 
> Pereira.
> + * Divergence Analysis.  ACM Transactions on Programming Languages and 
> Systems (TOPLAS),
> + * ACM, 2013, 35 (4), pp.13:1-13:36. <10.1145/2523815>. 
> + */
> +
> +
> +static bool alu_src_is_divergent(bool *divergent, nir_alu_src src, unsigned 
> num_input_components)

static bool
alu_src_is_divergent(bool *divergent, nir_alu_src src, unsigned 
num_input_components)

Mesa uses this style so that you can find a function definition by doing

   grep -r ^function_name src/'

> +{
> +   /* If the alu src is swizzled and defined by a vec-instruction,
> +* we can check if the originating value is non-divergent. */
> +   if (num_input_components == 1 &&
> +   src.src.ssa->num_components != 1 &&
> +   src.src.parent_instr->type == nir_instr_type_alu) {
> +  nir_alu_instr *parent = nir_instr_as_alu(src.src.parent_instr);

Blank line here.

> +  switch(parent->op) {
> + case nir_op_vec2:

case should be indented to the same level a switch.

> + case nir_op_vec3:
> + case nir_op_vec4: {
> +if (divergent[parent->src[src.swizzle[0]].src.ssa->index])
> +   return true;
> +return false;
> + }

Blank line here.

> + default:
> +break;
> +  }
> +   }

Blank line here.

> +   return divergent[src.src.ssa->index];
> +}
> +
> +static bool visit_alu(bool *divergent, nir_alu_instr *instr)
> +{
> +   if

[Mesa-dev] [PATCH] spirv: Emit NIR deref instructions on-the-fly

This simplifies our deref handling by emitting the actual NIR deref
instructions on-the-fly instead of of building up a deref chain and then
emitting them at the last moment.  In order for this to work with the
parts of the compiler that assume they can chase deref chains, we have
to run nir_rematerialize_derefs_in_use_blocks_impl to put the derefs
back in the right places in cases like loops where dominance may not
quite work out the way SPIR-V thinks it does.
---
 src/compiler/spirv/vtn_cfg.c   |  2 +
 src/compiler/spirv/vtn_private.h   | 13 +
 src/compiler/spirv/vtn_variables.c | 90 ++
 3 files changed, 34 insertions(+), 71 deletions(-)

diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index 87149905ed1..57a9b0ea6e3 100644
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -951,6 +951,8 @@ vtn_function_emit(struct vtn_builder *b, struct 
vtn_function *func,
vtn_foreach_instruction(b, func->start_block->label, func->end,
vtn_handle_phi_second_pass);
 
+   nir_rematerialize_derefs_in_use_blocks_impl(func->impl);
+
/* Continue blocks for loops get inserted before the body of the loop
 * but instructions in the continue may use SSA defs in the loop body.
 * Therefore, we need to repair SSA to insert the needed phi nodes.
diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index da7a04ce59f..defcbb8e69d 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -443,20 +443,9 @@ struct vtn_pointer {
 */
struct vtn_variable *var;
 
-   /** The deref at the base of the chain
-*
-* This field may be NULL if the pointer uses a (block_index, offset) pair
-* instead of an access chain or if the access chain starts at a variable.
-*/
+   /** The NIR deref corresponding to this pointer */
nir_deref_instr *deref;
 
-   /** An access chain describing how to get from var to the referenced data
-*
-* This field may be NULL if the pointer references the entire variable or
-* if a (block_index, offset) pair is used instead of an access chain.
-*/
-   struct vtn_access_chain *chain;
-
/** A (block_index, offset) pair representing a UBO or SSBO position. */
struct nir_ssa_def *block_index;
struct nir_ssa_def *offset;
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index c5cf345d02a..6d6040a1e1f 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -43,21 +43,6 @@ vtn_access_chain_create(struct vtn_builder *b, unsigned 
length)
return chain;
 }
 
-static struct vtn_access_chain *
-vtn_access_chain_extend(struct vtn_builder *b, struct vtn_access_chain *old,
-unsigned new_ids)
-{
-   struct vtn_access_chain *chain;
-
-   unsigned old_len = old ? old->length : 0;
-   chain = vtn_access_chain_create(b, old_len + new_ids);
-
-   for (unsigned i = 0; i < old_len; i++)
-  chain->link[i] = old->link[i];
-
-   return chain;
-}
-
 static bool
 vtn_pointer_uses_ssa_offset(struct vtn_builder *b,
 struct vtn_pointer *ptr)
@@ -82,29 +67,42 @@ vtn_pointer_is_external_block(struct vtn_builder *b,
 
 /* Dereference the given base pointer by the access chain */
 static struct vtn_pointer *
-vtn_access_chain_pointer_dereference(struct vtn_builder *b,
- struct vtn_pointer *base,
- struct vtn_access_chain *deref_chain)
+vtn_nir_deref_pointer_dereference(struct vtn_builder *b,
+  struct vtn_pointer *base,
+  struct vtn_access_chain *deref_chain)
 {
-   struct vtn_access_chain *chain =
-  vtn_access_chain_extend(b, base->chain, deref_chain->length);
struct vtn_type *type = base->type;
enum gl_access_qualifier access = base->access;
 
+   nir_deref_instr *tail;
+   if (base->deref) {
+  tail = base->deref;
+   } else {
+  assert(base->var && base->var->var);
+  tail = nir_build_deref_var(>nb, base->var->var);
+   }
+
/* OpPtrAccessChain is only allowed on things which support variable
 * pointers.  For everything else, the client is expected to just pass us
 * the right access chain.
 */
vtn_assert(!deref_chain->ptr_as_array);
 
-   unsigned start = base->chain ? base->chain->length : 0;
for (unsigned i = 0; i < deref_chain->length; i++) {
-  chain->link[start + i] = deref_chain->link[i];
-
   if (glsl_type_is_struct(type->type)) {
  vtn_assert(deref_chain->link[i].mode == vtn_access_mode_literal);
- type = type->members[deref_chain->link[i].id];
+ unsigned idx = deref_chain->link[i].id;
+ tail = nir_build_deref_struct(>nb, tail, idx);
+ type = type->members[idx];
   } else {
+ nir_ssa_def *index;
+ if (deref_chain->link[i].mode ==

Re: [Mesa-dev] [PATCH mesa] util: remove unnecessary random whitespaces

On 10/25/2018 05:13 AM, Eric Engestrom wrote:
> On Thursday, 2018-10-25 17:54:16 +1100, Timothy Arceri wrote:
>> On 25/10/18 7:42 am, Ian Romanick wrote:
>>> On 10/23/2018 04:15 AM, Eric Engestrom wrote:
 Suggested-by: Timothy Arceri 
>>
>> Um no :P I suggested you fix the formatting in your patch to match the Mesa
>> style.
> 
> Right, sorry, you suggested fixing the formatting, but not the fix
> I went with, so I should've dropped this tag.
> 
>>
 Signed-off-by: Eric Engestrom 
 ---
 Timothy, I opted to remove them all instead of adding even more, as it
 would break again next time something changes (the set_foreach() one was
 already broken before my patch for instance) and result in lots of
 unnecessary churn for seemingly no gain, and I don't like hiding the
 backslash away (it hinders readability).
>>>
>>> NAK... we use this formatting everywhere in Mesa.  The point is to move
>>> the \ characters out of the way.  When you're trying to read a
>>> multi-line macro, they are distracting, so it is nice to move them over.
> 
> I don't have the same opinion, but respecting mesa style is the point
> here, so I added those whitespace chars, squashed them in the previous
> patches, and pushed them.
> 
> Sorry for this patch :)

It's always worth a try. :)  Everyone has aspects of the Mesa style that
they don't like.  Sending out a patch like this is a good way to test
the waters about changing the style.  It does happen from time to time.
It's better to do it like this than to try to sneak it in a big patch
series.
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Re: [Mesa-dev] [PATCH 2/4] gen: Add AMD_gpu_shader_int64.xml to tarball

This patch is

Reviewed-by: Ian Romanick 

On 10/23/2018 03:56 PM, Dylan Baker wrote:
> CC: Ian Romanick 
> CC: Marek Olšák 
> Fixes: b3c17330e631695b5e5dc209ba9ea1a528618c97
>("mesa: expose AMD_gpu_shader_int64")
> ---
>  src/mapi/glapi/gen/Makefile.am | 1 +
>  src/mapi/glapi/gen/meson.build | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
> index e59e6cc90a3..187928e377a 100644
> --- a/src/mapi/glapi/gen/Makefile.am
> +++ b/src/mapi/glapi/gen/Makefile.am
> @@ -190,6 +190,7 @@ API_XML = \
>   ARB_viewport_array.xml \
>   AMD_depth_clamp_separate.xml \
>   AMD_draw_buffers_blend.xml \
> + AMD_gpu_shader_int64.xml \
>   AMD_performance_monitor.xml \
>   ARB_vertex_type_2_10_10_10_rev.xml \
>   APPLE_object_purgeable.xml \
> diff --git a/src/mapi/glapi/gen/meson.build b/src/mapi/glapi/gen/meson.build
> index 1cf3339e30e..f494e9707b6 100644
> --- a/src/mapi/glapi/gen/meson.build
> +++ b/src/mapi/glapi/gen/meson.build
> @@ -97,6 +97,7 @@ api_xml_files = files(
>'ARB_viewport_array.xml',
>'AMD_depth_clamp_separate.xml',
>'AMD_draw_buffers_blend.xml',
> +  'AMD_gpu_shader_int64.xml',
>'AMD_performance_monitor.xml',
>'ARB_vertex_type_2_10_10_10_rev.xml',
>'APPLE_object_purgeable.xml',
> 

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Re: [Mesa-dev] [PATCH 1/4] gen: Add EXT_vertex_attrib_64bit.xml to dependency lists

This patch is

Reviewed-by: Ian Romanick 

On 10/23/2018 03:56 PM, Dylan Baker wrote:
> Which is also required to put it in the tarball, a requirement for
> building with meson from the tarball.
> 
> CC: Ian Romanick 
> CC: Marek Olšák 
> Fixes: 263c962cfdee6b43578ee5f28601309ea77d1434
>("mesa: expose EXT_vertex_attrib_64bit")
> ---
>  src/mapi/glapi/gen/Makefile.am | 1 +
>  src/mapi/glapi/gen/meson.build | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am
> index ab369a0d333..e59e6cc90a3 100644
> --- a/src/mapi/glapi/gen/Makefile.am
> +++ b/src/mapi/glapi/gen/Makefile.am
> @@ -205,6 +205,7 @@ API_XML = \
>   EXT_texture_array.xml \
>   EXT_texture_integer.xml \
>   EXT_transform_feedback.xml \
> + EXT_vertex_attrib_64bit.xml \
>   EXT_window_rectangles.xml \
>   GREMEDY_string_marker.xml \
>   INTEL_performance_query.xml \
> diff --git a/src/mapi/glapi/gen/meson.build b/src/mapi/glapi/gen/meson.build
> index c638b1ece60..1cf3339e30e 100644
> --- a/src/mapi/glapi/gen/meson.build
> +++ b/src/mapi/glapi/gen/meson.build
> @@ -112,6 +112,7 @@ api_xml_files = files(
>'EXT_texture_array.xml',
>'EXT_texture_integer.xml',
>'EXT_transform_feedback.xml',
> +  'EXT_vertex_attrib_64bit.xml',
>'EXT_window_rectangles.xml',
>'GREMEDY_string_marker.xml',
>'INTEL_performance_query.xml',
> 

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Re: [Mesa-dev] [PATCH mesa] radv: remove duplicate brackets in version string



On October 25, 2018 5:12:30 PM UTC, Bas Nieuwenhuizen 
 wrote:
> How did you notice that?

Just saw the commit and knew the behaviour of the macro because
I was the one who changed it a couple months ago ^^

> Anyway, can confirm,
> 
> Reviewed-by: Bas Nieuwenhuizen 

Cheers; I'll probably push it tomorrow.

> On Thu, Oct 25, 2018 at 6:40 PM Eric Engestrom
>  wrote:
> >
> > MESA_GIT_SHA1 resolves to either an empty "" string if not build
> from git,
> > or " (git-DEADBEEF)" if it is. No need to wrap it in additional
> "()".
> >
> > Fixes: 9d40ec2cf6ec6d3d9d78 "radv: Add support for
> VK_KHR_driver_properties."
> > Signed-off-by: Eric Engestrom 
> > ---
> >  src/amd/vulkan/radv_device.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/src/amd/vulkan/radv_device.c
> b/src/amd/vulkan/radv_device.c
> > index 8e43a3aab58620dfc756..73d0f9fe02db6bc74643 100644
> > --- a/src/amd/vulkan/radv_device.c
> > +++ b/src/amd/vulkan/radv_device.c
> > @@ -1218,7 +1218,7 @@ void radv_GetPhysicalDeviceProperties2(
> >
> > memset(driver_props->driverInfo, 0,
> VK_MAX_DRIVER_INFO_SIZE_KHR);
> > snprintf(driver_props->driverInfo,
> VK_MAX_DRIVER_INFO_SIZE_KHR,
> > -   "Mesa " PACKAGE_VERSION " ("
> MESA_GIT_SHA1 ")"
> > +   "Mesa " PACKAGE_VERSION
> MESA_GIT_SHA1
> > " (LLVM %d.%d.%d)",
> >  (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM
> & 0xff,
> >  MESA_LLVM_VERSION_PATCH);
> > --
> > Cheers,
> >   Eric
> >
> ___
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> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [Bug 108508] Graphic glitches with stream output support on OLAND AMD GPU GCN 1.0

https://bugs.freedesktop.org/show_bug.cgi?id=108508

Ahmed Elsayed  changed:

   What|Removed |Added

Summary|Graphic glitches with   |Graphic glitches with
   |stream output support on|stream output support on
   |OLAND AMD GPU GCN   |OLAND AMD GPU GCN 1.0

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Re: [Mesa-dev] [PATCH 2/3] anv: Add helpers for setting/checking device lost

I would put the vk_errorf within the anv_device_set_lost and make it 
return VkResult so that you can cull a bunch of lines, but that can be 
done in another commit.


Reviewed-by: Lionel Landwerlin 

On 25/10/2018 17:46, Jason Ekstrand wrote:

---
  src/intel/vulkan/anv_device.c  | 28 +---
  src/intel/vulkan/anv_private.h | 11 ++-
  src/intel/vulkan/anv_queue.c   | 14 +++---
  src/intel/vulkan/genX_query.c  |  4 ++--
  4 files changed, 36 insertions(+), 21 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 8e4436ec960..79d3f052113 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1712,7 +1712,7 @@ VkResult anv_CreateDevice(
 device->instance = physical_device->instance;
 device->chipset_id = physical_device->chipset_id;
 device->no_hw = physical_device->no_hw;
-   device->lost = false;
+   device->_lost = false;
  
 if (pAllocator)

device->alloc = *pAllocator;
@@ -2049,6 +2049,12 @@ void anv_GetDeviceQueue2(
*pQueue = NULL;
  }
  
+void

+anv_device_set_lost(struct anv_device *device, const char *msg, ...)
+{
+   device->_lost = true;
+}
+
  VkResult
  anv_device_query_status(struct anv_device *device)
  {
@@ -2056,24 +2062,24 @@ anv_device_query_status(struct anv_device *device)
  * for it.  However, it doesn't hurt to check and it potentially lets us
  * avoid an ioctl.
  */
-   if (unlikely(device->lost))
+   if (anv_device_is_lost(device))
return VK_ERROR_DEVICE_LOST;
  
 uint32_t active, pending;

 int ret = anv_gem_gpu_get_reset_stats(device, , );
 if (ret == -1) {
/* We don't know the real error. */
-  device->lost = true;
+  anv_device_set_lost(device, "get_reset_stats failed: %m");
return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
 "get_reset_stats failed: %m");
 }
  
 if (active) {

-  device->lost = true;
+  anv_device_set_lost(device, "GPU hung on one of our command buffers");
return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
 "GPU hung on one of our command buffers");
 } else if (pending) {
-  device->lost = true;
+  anv_device_set_lost(device, "GPU hung with commands in-flight");
return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
 "GPU hung with commands in-flight");
 }
@@ -2093,7 +2099,7 @@ anv_device_bo_busy(struct anv_device *device, struct 
anv_bo *bo)
return VK_NOT_READY;
 } else if (ret == -1) {
/* We don't know the real error. */
-  device->lost = true;
+  anv_device_set_lost(device, "gem wait failed: %m");
return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
 "gem wait failed: %m");
 }
@@ -2116,7 +2122,7 @@ anv_device_wait(struct anv_device *device, struct anv_bo 
*bo,
return VK_TIMEOUT;
 } else if (ret == -1) {
/* We don't know the real error. */
-  device->lost = true;
+  anv_device_set_lost(device, "gem wait failed: %m");
return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
 "gem wait failed: %m");
 }
@@ -2133,7 +2139,7 @@ VkResult anv_DeviceWaitIdle(
  VkDevice_device)
  {
 ANV_FROM_HANDLE(anv_device, device, _device);
-   if (unlikely(device->lost))
+   if (anv_device_is_lost(device))
return VK_ERROR_DEVICE_LOST;
  
 struct anv_batch batch;

@@ -2807,7 +2813,7 @@ VkResult anv_QueueBindSparse(
  VkFence fence)
  {
 ANV_FROM_HANDLE(anv_queue, queue, _queue);
-   if (unlikely(queue->device->lost))
+   if (anv_device_is_lost(queue->device))
return VK_ERROR_DEVICE_LOST;
  
 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);

@@ -2865,7 +2871,7 @@ VkResult anv_GetEventStatus(
 ANV_FROM_HANDLE(anv_device, device, _device);
 ANV_FROM_HANDLE(anv_event, event, _event);
  
-   if (unlikely(device->lost))

+   if (anv_device_is_lost(device))
return VK_ERROR_DEVICE_LOST;
  
 if (!device->info.has_llc) {

@@ -3095,7 +3101,7 @@ VkResult anv_GetCalibratedTimestampsEXT(
  [d]);
  
   if (ret != 0) {

-device->lost = TRUE;
+anv_device_set_lost(device, "Failed to get a timestamp");
  return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
   "Failed to read the TIMESTAMP register: %m");
   }
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 0f957fae69b..a9fada56dd3 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1028,7 +1028,7 @@ struct anv_device {
  
  pthread_mutex_t mutex;

  pthread_cond_t  queue_submit;

[Mesa-dev] [PATCH] anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREG

2018-10-25 Thread Anuj Phogat

The default setting of this bit is not the desirable behavior.
WA_1406697149

Signed-off-by: Anuj Phogat 
---
 src/intel/genxml/gen11.xml | 1 +
 src/intel/vulkan/genX_cmd_buffer.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index c69d7dc89c2..454ef8f4103 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3546,6 +3546,7 @@
   
 
 
+
 
 
 
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 43a02f22567..ed88157170d 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1617,6 +1617,13 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer 
*cmd_buffer,
uint32_t l3cr;
anv_pack_struct(, GENX(L3CNTLREG),
.SLMEnable = has_slm,
+#if GEN_GEN == 11
+   /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
+* in L3CNTLREG register. The default setting of the bit is not the
+* desirable behavior.
+   */
+   .ErrorDetectionBehaviorControl = true,
+#endif
.URBAllocation = cfg->n[GEN_L3P_URB],
.ROAllocation = cfg->n[GEN_L3P_RO],
.DCAllocation = cfg->n[GEN_L3P_DC],
-- 
2.17.1

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[Mesa-dev] [PATCH] i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREG

2018-10-25 Thread Anuj Phogat

The default setting of this bit is not the desirable behavior.
WA_1406697149

Signed-off-by: Anuj Phogat 
---
 src/mesa/drivers/dri/i965/brw_defines.h  | 1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c | 7 +++
 2 files changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 97a787a2ab3..897c91aa31e 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1646,6 +1646,7 @@ enum brw_pixel_shader_coverage_mask_mode {
 # define GEN8_L3CNTLREG_DC_ALLOC_MASK  INTEL_MASK(24, 18)
 # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT25
 # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
+# define GEN8_L3CNTLREG_EDBC_NO_HANG   (1 << 9)
 
 #define GEN10_CACHE_MODE_SS0x0e420
 #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 7f20579fb87..60b72bf4ab3 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -79,6 +79,13 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
   brw_load_register_imm32(brw, HALF_SLICE_CHICKEN7,
   TEXEL_OFFSET_FIX_MASK |
   TEXEL_OFFSET_FIX_ENABLE);
+
+  /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
+   * in L3CNTLREG register. The default setting of the bit is not the
+   * desirable behavior.
+   */
+  brw_load_register_imm32(brw, GEN8_L3CNTLREG,
+  GEN8_L3CNTLREG_EDBC_NO_HANG);
}
 
if (devinfo->gen == 10 || devinfo->gen == 11) {
-- 
2.17.1

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Re: [Mesa-dev] [PATCH 3/3] anv: Handle the device loss abort in anv_device_set_lost


Reviewed-by: Lionel Landwerlin 

On 25/10/2018 17:46, Jason Ekstrand wrote:

---
  src/intel/vulkan/anv_device.c | 11 +++
  src/intel/vulkan/anv_util.c   |  4 
  2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 79d3f052113..d62bdde078c 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2053,6 +2053,17 @@ void
  anv_device_set_lost(struct anv_device *device, const char *msg, ...)
  {
 device->_lost = true;
+
+   if (env_var_as_boolean("ANV_ABORT_ON_DEVICE_LOSS", false)) {
+  intel_loge("Device lost!");
+
+  va_list ap;
+  va_start(ap, msg);
+  intel_loge_v(msg, ap);
+  va_end(ap);
+
+  abort();
+   }
  }
  
  VkResult

diff --git a/src/intel/vulkan/anv_util.c b/src/intel/vulkan/anv_util.c
index 9082707624c..9963a15ace3 100644
--- a/src/intel/vulkan/anv_util.c
+++ b/src/intel/vulkan/anv_util.c
@@ -112,9 +112,5 @@ __vk_errorf(struct anv_instance *instance, const void 
*object,
  
 intel_loge("%s", report);
  
-   if (error == VK_ERROR_DEVICE_LOST &&

-   env_var_as_boolean("ANV_ABORT_ON_DEVICE_LOSS", false))
-  abort();
-
 return error;
  }



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Re: [Mesa-dev] [PATCH 1/3] anv: Provide a error message with a DEVICE_LOST


Reviewed-by: Lionel Landwerlin 

On 25/10/2018 17:46, Jason Ekstrand wrote:

---
  src/intel/vulkan/anv_device.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index c009176dcc6..8e4436ec960 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -3096,7 +3096,8 @@ VkResult anv_GetCalibratedTimestampsEXT(
  
   if (ret != 0) {

  device->lost = TRUE;
-return VK_ERROR_DEVICE_LOST;
+return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
+ "Failed to read the TIMESTAMP register: %m");
   }
   uint64_t device_period = DIV_ROUND_UP(10, 
timestamp_frequency);
   max_clock_period = MAX2(max_clock_period, device_period);



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Re: [Mesa-dev] [PATCH] radv: Add support for VK_KHR_driver_properties.

2018-10-25 Thread Bas Nieuwenhuizen

On Wed, Oct 17, 2018 at 1:29 PM Alex Smith  wrote:
>
> This patch never landed in git, is that intentional?

It turned out the CTS version we did our conformance submission in was
rejected for some reason in the CTS test for this ext so had to make
some adjustments. It is upstream now.
>
> On Mon, 1 Oct 2018 at 17:46, Jason Ekstrand  wrote:
>>
>> On Sun, Sep 30, 2018 at 1:04 PM Bas Nieuwenhuizen  
>> wrote:
>>>
>>> ---
>>>  src/amd/vulkan/radv_device.c  | 27 +++
>>>  src/amd/vulkan/radv_extensions.py |  1 +
>>>  2 files changed, 28 insertions(+)
>>>
>>> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
>>> index f7752eac83b..fe7e7f7f6ac 100644
>>> --- a/src/amd/vulkan/radv_device.c
>>> +++ b/src/amd/vulkan/radv_device.c
>>> @@ -1196,6 +1196,33 @@ void radv_GetPhysicalDeviceProperties2(
>>> 
>>> properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
>>> break;
>>> }
>>> +   case 
>>> VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
>>> +   VkPhysicalDeviceDriverPropertiesKHR *driver_props =
>>> +   (VkPhysicalDeviceDriverPropertiesKHR *) ext;
>>> +
>>> +   driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
>>> +   memset(driver_props->driverName, 0, 
>>> VK_MAX_DRIVER_NAME_SIZE_KHR);
>>> +   strcpy(driver_props->driverName, "radv");
>>> +
>>> +   memset(driver_props->driverInfo, 0, 
>>> VK_MAX_DRIVER_INFO_SIZE_KHR);
>>> +   snprintf(driver_props->driverInfo, 
>>> VK_MAX_DRIVER_INFO_SIZE_KHR,
>>> +   "Mesa " PACKAGE_VERSION
>>> +#ifdef MESA_GIT_SHA1
>>> +   " ("MESA_GIT_SHA1")"
>>> +#endif
>>> +   " (LLVM %i.%i.%i)",
>>
>>
>> I think %d is more customary, but I don't care.  Assuming you actually pass 
>> 1.1.0.2,
>>
>> Reviewed-by: Jason Ekstrand 
>>
>>>
>>> +(HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
>>> +MESA_LLVM_VERSION_PATCH);
>>> +
>>> +   driver_props->conformanceVersion = 
>>> (VkConformanceVersionKHR) {
>>> +   .major = 1,
>>> +   .minor = 1,
>>> +   .subminor = 0,
>>> +   .patch = 2,
>>> +   };
>>> +   break;
>>> +   }
>>> +
>>> default:
>>> break;
>>> }
>>> diff --git a/src/amd/vulkan/radv_extensions.py 
>>> b/src/amd/vulkan/radv_extensions.py
>>> index 584926df390..8df5da76ed5 100644
>>> --- a/src/amd/vulkan/radv_extensions.py
>>> +++ b/src/amd/vulkan/radv_extensions.py
>>> @@ -59,6 +59,7 @@ EXTENSIONS = [
>>>  Extension('VK_KHR_device_group',  1, True),
>>>  Extension('VK_KHR_device_group_creation', 1, True),
>>>  Extension('VK_KHR_draw_indirect_count',   1, True),
>>> +Extension('VK_KHR_driver_properties', 1, True),
>>>  Extension('VK_KHR_external_fence',1, 
>>> 'device->rad_info.has_syncobj_wait_for_submit'),
>>>  Extension('VK_KHR_external_fence_capabilities',   1, True),
>>>  Extension('VK_KHR_external_fence_fd', 1, 
>>> 'device->rad_info.has_syncobj_wait_for_submit'),
>>> --
>>> 2.19.0
>>>
>>> ___
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>>> mesa-dev@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>>
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[Mesa-dev] [Bug 108508] Graphic glitches with stream output support on OLAND AMD GPU GCN

https://bugs.freedesktop.org/show_bug.cgi?id=108508

Ahmed Elsayed  changed:

   What|Removed |Added

Summary|Graphic glitches with   |Graphic glitches with
   |stream output support on|stream output support on
   |OLAND AMD GPU   |OLAND AMD GPU GCN

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[Mesa-dev] [Bug 108508] Graphic glitches with stream output support on OLAND AMD GPU

https://bugs.freedesktop.org/show_bug.cgi?id=108508

Ahmed Elsayed  changed:

   What|Removed |Added

Summary|Graphic glitches with   |Graphic glitches with
   |stream output support on|stream output support on
   |OLAND AMD GPU GCN 1.0   |OLAND AMD GPU

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Re: [Mesa-dev] [PATCH mesa] radv: remove duplicate brackets in version string

2018-10-25 Thread Bas Nieuwenhuizen

How did you notice that? Anyway, can confirm,

Reviewed-by: Bas Nieuwenhuizen 
On Thu, Oct 25, 2018 at 6:40 PM Eric Engestrom  wrote:
>
> MESA_GIT_SHA1 resolves to either an empty "" string if not build from git,
> or " (git-DEADBEEF)" if it is. No need to wrap it in additional "()".
>
> Fixes: 9d40ec2cf6ec6d3d9d78 "radv: Add support for VK_KHR_driver_properties."
> Signed-off-by: Eric Engestrom 
> ---
>  src/amd/vulkan/radv_device.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 8e43a3aab58620dfc756..73d0f9fe02db6bc74643 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -1218,7 +1218,7 @@ void radv_GetPhysicalDeviceProperties2(
>
> memset(driver_props->driverInfo, 0, 
> VK_MAX_DRIVER_INFO_SIZE_KHR);
> snprintf(driver_props->driverInfo, 
> VK_MAX_DRIVER_INFO_SIZE_KHR,
> -   "Mesa " PACKAGE_VERSION " (" MESA_GIT_SHA1 ")"
> +   "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
> " (LLVM %d.%d.%d)",
>  (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
>  MESA_LLVM_VERSION_PATCH);
> --
> Cheers,
>   Eric
>
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[Mesa-dev] Q: Intel/i965: how to add a new texture format (GL_SRGB_R8)

2018-10-25 Thread Gert Wollny

Dear all, 

I'm currently working on getting EXT_texture_sRGB_R8 into mesa. I'm at
the point where it is working for r600, i.e.

 dEQP-GLES31.functional.texture.filtering.cube_array.formats.sr8*

all pass, so I assume that the mesa/core, Gallium, and r600 patches are
more or less correct. However, with the Intel driver I'm hitting a
wall. The dEQP test 
  
GLES31.functional.texture.filtering.cube_array.formats.sr8_nearest

runs without error messages, the log with INTEL_DEBUG=tex indicates
that the GL_SR8_EXT interbal format is used, but the test fails - only
a black texture is drawn. 

The patch related to the changes I did to the driver is here: 

https://gitlab.freedesktop.org/gerddie/mesa/commit/e7bdc0385d4ef02a6aaa
82f1ee06da7c9f42313d

(There is some unrelated white space change, from a dri radeon driver,
sorry for that) and the whole series for implementing this (very much
WIP for various reasons) can be found here: 

https://gitlab.freedesktop.org/gerddie/mesa/commits/add-EXT_texture_sRG
B_R8

Any pointer what might be missing would be great, 
thanks a lot, 
Gert 
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Re: [Mesa-dev] [PATCH] anv: Fix sanitization of stencil state when the depth test is disabled

Maybe we should just roll the depthTestEnable check in with the ds_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT check right below it.  In either case,

Reviewed-by: Jason Ekstrand 

On Thu, Oct 25, 2018 at 5:25 AM Alex Smith 
wrote:

> When depth testing is disabled, we shouldn't pay attention to the
> specified depthCompareOp, and just treat it as always passing. Before,
> if the depth test is disabled, but depthCompareOp is VK_COMPARE_OP_NEVER
> (e.g. from the app having zero-initialized the structure), then
> sanitize_stencil_face() would have incorrectly changed passOp to
> VK_STENCIL_OP_KEEP.
>
> Signed-off-by: Alex Smith 
> ---
>  src/intel/vulkan/genX_pipeline.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/vulkan/genX_pipeline.c
> b/src/intel/vulkan/genX_pipeline.c
> index 33f1f7832a..877a9fb850 100644
> --- a/src/intel/vulkan/genX_pipeline.c
> +++ b/src/intel/vulkan/genX_pipeline.c
> @@ -755,9 +755,13 @@
> sanitize_ds_state(VkPipelineDepthStencilStateCreateInfo *state,
>  {
> *stencilWriteEnable = state->stencilTestEnable;
>
> -   /* If the depth test is disabled, we won't be writing anything. */
> -   if (!state->depthTestEnable)
> +   /* If the depth test is disabled, we won't be writing anything. Make
> sure
> +* we treat it as always passing later on as well.
> +*/
> +   if (!state->depthTestEnable) {
>state->depthWriteEnable = false;
> +  state->depthCompareOp = VK_COMPARE_OP_ALWAYS;
> +   }
>
> /* The Vulkan spec requires that if either depth or stencil is not
> present,
>  * the pipeline is to act as if the test silently passes.
> --
> 2.14.4
>
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[Mesa-dev] [PATCH 1/3] anv: Provide a error message with a DEVICE_LOST

---
 src/intel/vulkan/anv_device.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index c009176dcc6..8e4436ec960 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -3096,7 +3096,8 @@ VkResult anv_GetCalibratedTimestampsEXT(
 
  if (ret != 0) {
 device->lost = TRUE;
-return VK_ERROR_DEVICE_LOST;
+return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
+ "Failed to read the TIMESTAMP register: %m");
  }
  uint64_t device_period = DIV_ROUND_UP(10, 
timestamp_frequency);
  max_clock_period = MAX2(max_clock_period, device_period);
-- 
2.19.1

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Re: [Mesa-dev] [PATCH] intel/compiler: Print message descriptor as immediate source

2018-10-25 Thread Sagar Ghuge



On 10/25/18 12:55 AM, Samuel Iglesias Gonsálvez wrote:
> On Thursday, 25 October 2018 1:25:53 (CEST) Sagar Ghuge wrote:
>> While disassembling send(c) instruction print message descriptor as
>> immediate source operand along with message descriptor. This allows
>> assembler to read immediate source operand and set bits accordingly.
>>
>> Signed-off-by: Sagar Ghuge 
>> ---
>>  src/intel/compiler/brw_disasm.c | 9 +++--
>>  1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/intel/compiler/brw_disasm.c
>> b/src/intel/compiler/brw_disasm.c index 6a7e988641..9c6df9e645 100644
>> --- a/src/intel/compiler/brw_disasm.c
>> +++ b/src/intel/compiler/brw_disasm.c
>> @@ -1606,7 +1606,12 @@ brw_disassemble_inst(FILE *file, const struct
>> gen_device_info *devinfo, /* show the indirect descriptor source */
>>   pad(file, 48);
>>   err |= src1(file, devinfo, inst);
>> -  }
>> + pad(file, 64);
>> +  } else
>> + pad(file, 48);
>> +
> 
> IIRC, we have a coding style rules that is: when the if's body has several 
> statements like here, then the else body should be between braces even when 
> it 
> is one line. That thing increases readability.
> 
Thanks for pointing out. 
> I have not found it written in the coding style guidelines [0], but I have 
> seen it in a lot of places of the code.
> 
> I can do this change for you before pushing it tomorrow. Sounds good?
> 
Yep, sounds great. Thank you. 

> With that fixed,
> 
> Reviewed-by: Samuel Iglesias Gonsálvez 
> 
> Sam
> 
> [0] https://www.mesa3d.org/codingstyle.html
> 
>> +  /* Print message descriptor as immediate source */
>> +  fprintf(file, "0x%08"PRIx64, inst->data[1] >> 32);
>>
>>newline(file);
>>pad(file, 16);
>> @@ -1615,7 +1620,7 @@ brw_disassemble_inst(FILE *file, const struct
>> gen_device_info *devinfo, fprintf(file, "");
>>err |= control(file, "SFID", devinfo->gen >= 6 ? gen6_sfid :
>> gen4_sfid, sfid, );
>> -
>> +  string(file, " MsgDesc:");
>>
>>if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
>>   format(file, " indirect");
> 
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[Mesa-dev] [PATCH 2/3] anv: Add helpers for setting/checking device lost

---
 src/intel/vulkan/anv_device.c  | 28 +---
 src/intel/vulkan/anv_private.h | 11 ++-
 src/intel/vulkan/anv_queue.c   | 14 +++---
 src/intel/vulkan/genX_query.c  |  4 ++--
 4 files changed, 36 insertions(+), 21 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 8e4436ec960..79d3f052113 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1712,7 +1712,7 @@ VkResult anv_CreateDevice(
device->instance = physical_device->instance;
device->chipset_id = physical_device->chipset_id;
device->no_hw = physical_device->no_hw;
-   device->lost = false;
+   device->_lost = false;
 
if (pAllocator)
   device->alloc = *pAllocator;
@@ -2049,6 +2049,12 @@ void anv_GetDeviceQueue2(
   *pQueue = NULL;
 }
 
+void
+anv_device_set_lost(struct anv_device *device, const char *msg, ...)
+{
+   device->_lost = true;
+}
+
 VkResult
 anv_device_query_status(struct anv_device *device)
 {
@@ -2056,24 +2062,24 @@ anv_device_query_status(struct anv_device *device)
 * for it.  However, it doesn't hurt to check and it potentially lets us
 * avoid an ioctl.
 */
-   if (unlikely(device->lost))
+   if (anv_device_is_lost(device))
   return VK_ERROR_DEVICE_LOST;
 
uint32_t active, pending;
int ret = anv_gem_gpu_get_reset_stats(device, , );
if (ret == -1) {
   /* We don't know the real error. */
-  device->lost = true;
+  anv_device_set_lost(device, "get_reset_stats failed: %m");
   return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
"get_reset_stats failed: %m");
}
 
if (active) {
-  device->lost = true;
+  anv_device_set_lost(device, "GPU hung on one of our command buffers");
   return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
"GPU hung on one of our command buffers");
} else if (pending) {
-  device->lost = true;
+  anv_device_set_lost(device, "GPU hung with commands in-flight");
   return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
"GPU hung with commands in-flight");
}
@@ -2093,7 +2099,7 @@ anv_device_bo_busy(struct anv_device *device, struct 
anv_bo *bo)
   return VK_NOT_READY;
} else if (ret == -1) {
   /* We don't know the real error. */
-  device->lost = true;
+  anv_device_set_lost(device, "gem wait failed: %m");
   return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
"gem wait failed: %m");
}
@@ -2116,7 +2122,7 @@ anv_device_wait(struct anv_device *device, struct anv_bo 
*bo,
   return VK_TIMEOUT;
} else if (ret == -1) {
   /* We don't know the real error. */
-  device->lost = true;
+  anv_device_set_lost(device, "gem wait failed: %m");
   return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
"gem wait failed: %m");
}
@@ -2133,7 +2139,7 @@ VkResult anv_DeviceWaitIdle(
 VkDevice_device)
 {
ANV_FROM_HANDLE(anv_device, device, _device);
-   if (unlikely(device->lost))
+   if (anv_device_is_lost(device))
   return VK_ERROR_DEVICE_LOST;
 
struct anv_batch batch;
@@ -2807,7 +2813,7 @@ VkResult anv_QueueBindSparse(
 VkFence fence)
 {
ANV_FROM_HANDLE(anv_queue, queue, _queue);
-   if (unlikely(queue->device->lost))
+   if (anv_device_is_lost(queue->device))
   return VK_ERROR_DEVICE_LOST;
 
return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
@@ -2865,7 +2871,7 @@ VkResult anv_GetEventStatus(
ANV_FROM_HANDLE(anv_device, device, _device);
ANV_FROM_HANDLE(anv_event, event, _event);
 
-   if (unlikely(device->lost))
+   if (anv_device_is_lost(device))
   return VK_ERROR_DEVICE_LOST;
 
if (!device->info.has_llc) {
@@ -3095,7 +3101,7 @@ VkResult anv_GetCalibratedTimestampsEXT(
 [d]);
 
  if (ret != 0) {
-device->lost = TRUE;
+anv_device_set_lost(device, "Failed to get a timestamp");
 return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
  "Failed to read the TIMESTAMP register: %m");
  }
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 0f957fae69b..a9fada56dd3 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1028,7 +1028,7 @@ struct anv_device {
 
 pthread_mutex_t mutex;
 pthread_cond_t  queue_submit;
-boollost;
+bool_lost;
 };
 
 static inline struct anv_state_pool *
@@ -1075,6 +1075,15 @@ anv_state_flush(struct anv_device *device, struct 
anv_state state)
 void anv_device_init_blorp(struct anv_device *device);
 void

[Mesa-dev] [PATCH 3/3] anv: Handle the device loss abort in anv_device_set_lost

---
 src/intel/vulkan/anv_device.c | 11 +++
 src/intel/vulkan/anv_util.c   |  4 
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 79d3f052113..d62bdde078c 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -2053,6 +2053,17 @@ void
 anv_device_set_lost(struct anv_device *device, const char *msg, ...)
 {
device->_lost = true;
+
+   if (env_var_as_boolean("ANV_ABORT_ON_DEVICE_LOSS", false)) {
+  intel_loge("Device lost!");
+
+  va_list ap;
+  va_start(ap, msg);
+  intel_loge_v(msg, ap);
+  va_end(ap);
+
+  abort();
+   }
 }
 
 VkResult
diff --git a/src/intel/vulkan/anv_util.c b/src/intel/vulkan/anv_util.c
index 9082707624c..9963a15ace3 100644
--- a/src/intel/vulkan/anv_util.c
+++ b/src/intel/vulkan/anv_util.c
@@ -112,9 +112,5 @@ __vk_errorf(struct anv_instance *instance, const void 
*object,
 
intel_loge("%s", report);
 
-   if (error == VK_ERROR_DEVICE_LOST &&
-   env_var_as_boolean("ANV_ABORT_ON_DEVICE_LOSS", false))
-  abort();
-
return error;
 }
-- 
2.19.1

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Re: [Mesa-dev] [PATCH] intel/compiler: Print hex representation along with floating point value

2018-10-25 Thread Sagar Ghuge

Thank you for reviewing the patch. 

On 10/25/18 12:40 AM, Samuel Iglesias Gonsálvez wrote:
> Reviewed-by: Samuel Iglesias Gonsálvez 
> 
> Do you need somebody to push it to the repo? I can do it tomorrow.
> 
Yes, I don't have commit access. I really appreciate it.  
> Sam
> 
> On Wednesday, 24 October 2018 22:27:27 (CEST) Sagar Ghuge wrote:
>> While encoding the immediate floating point values in instruction we use
>> values upto precision 9, but while disassembling, we print precision to
>> 6 places, which round up the value and gives wrong interpretation for
>> encoded immediate constant.
>>
>> To avoid misinterpretation of encoded immediate values in instruction
>> and disassembled output, print hex representation along with floating
>> point value which can be used by assembler in future.
>>
>> Signed-off-by: Sagar Ghuge 
>> ---
>>  src/intel/compiler/brw_disasm.c | 12 +---
>>  1 file changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/intel/compiler/brw_disasm.c
>> b/src/intel/compiler/brw_disasm.c index 322f4544df..6a7e988641 100644
>> --- a/src/intel/compiler/brw_disasm.c
>> +++ b/src/intel/compiler/brw_disasm.c
>> @@ -1283,7 +1283,9 @@ imm(FILE *file, const struct gen_device_info *devinfo,
>> enum brw_reg_type type, format(file, "0x%08xUV", brw_inst_imm_ud(devinfo,
>> inst));
>>break;
>> case BRW_REGISTER_TYPE_VF:
>> -  format(file, "[%-gF, %-gF, %-gF, %-gF]VF",
>> +  format(file, "0x%"PRIx64"VF", brw_inst_bits(inst, 127, 96));
>> +  pad(file, 48);
>> +  format(file, "/* [%-gF, %-gF, %-gF, %-gF]VF */",
>>   brw_vf_to_float(brw_inst_imm_ud(devinfo, inst)),
>>   brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 8),
>>   brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16),
>> @@ -1293,10 +1295,14 @@ imm(FILE *file, const struct gen_device_info
>> *devinfo, enum brw_reg_type type, format(file, "0x%08xV",
>> brw_inst_imm_ud(devinfo, inst));
>>break;
>> case BRW_REGISTER_TYPE_F:
>> -  format(file, "%-gF", brw_inst_imm_f(devinfo, inst));
>> +  format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96));
>> +  pad(file, 48);
>> +  format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst));
>>break;
>> case BRW_REGISTER_TYPE_DF:
>> -  format(file, "%-gDF", brw_inst_imm_df(devinfo, inst));
>> +  format(file, "0x%016"PRIx64"DF", brw_inst_bits(inst, 127, 64));
>> +  pad(file, 48);
>> +  format(file, "/* %-gDF */", brw_inst_imm_df(devinfo, inst));
>>break;
>> case BRW_REGISTER_TYPE_HF:
>>string(file, "Half Float IMM");
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Re: [Mesa-dev] [PATCH mesa 1/4] meson: turn git_sha1.h target into a proper dependency

On Tuesday, 2018-10-02 13:44:07 -0700, Dylan Baker wrote:
> Quoting Eric Engestrom (2018-10-02 07:09:03)
> > Cc: mesa-sta...@lists.freedesktop.org
> > Signed-off-by: Eric Engestrom 
> > ---
> >  src/mesa/meson.build |  3 +--
> >  src/meson.build  | 13 -
> >  2 files changed, 9 insertions(+), 7 deletions(-)
> > 
> > diff --git a/src/mesa/meson.build b/src/mesa/meson.build
> > index ea884977db8052d86fcb..861b0311048eff422b9f 100644
> > --- a/src/mesa/meson.build
> > +++ b/src/mesa/meson.build
> > @@ -705,7 +705,6 @@ files_libmesa_common += [
> >ir_expression_operation_h,
> >main_remap_helper_h,
> >matypes_h,
> > -  sha1_h,
> >  ]
> >  
> >  if with_sse41
> > @@ -726,7 +725,7 @@ libmesa_classic = static_library(
> >cpp_args : [cpp_vis_args, cpp_msvc_compat_args],
> >include_directories : [inc_common, inc_libmesa_asm, 
> > include_directories('main')],
> >link_with : [libglsl, libmesa_sse41],
> > -  dependencies : idep_nir_headers,
> > +  dependencies : [idep_nir_headers, idep_git_sha1],
> >build_by_default : false,
> >  )
> >  
> > diff --git a/src/meson.build b/src/meson.build
> > index af881cff70bf752a6474..89ffaddf47b7286e4fe0 100644
> > --- a/src/meson.build
> > +++ b/src/meson.build
> > @@ -39,11 +39,14 @@ libglsl_util = static_library(
> >build_by_default : false,
> >  )
> >  
> > -sha1_h = custom_target(
> > -  'git_sha1.h',
> > -  output : 'git_sha1.h',
> > -  command : [prog_python, git_sha1_gen_py, '--output', '@OUTPUT@'],
> > -  build_always : true, # commit sha1 can change without having touched 
> > these files
> > +idep_git_sha1 = declare_dependency(
> > +  sources : custom_target(
> > +'git_sha1.h',
> > +output : 'git_sha1.h',
> > +command : [prog_python, git_sha1_gen_py, '--output', '@OUTPUT@'],
> > +build_always : true, # commit sha1 can change without having touched 
> > these files
> > +  ),
> > +  include_directories : inc_src,
> 
> What does this get us over including it in the source list, since it's a .h
> meson should generate the proper include paths already, right?

Are you sure it does? I'll respin if that's really guaranteed and not
just a coincidence :)
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[Mesa-dev] [PATCH mesa] radv: remove duplicate brackets in version string

MESA_GIT_SHA1 resolves to either an empty "" string if not build from git,
or " (git-DEADBEEF)" if it is. No need to wrap it in additional "()".

Fixes: 9d40ec2cf6ec6d3d9d78 "radv: Add support for VK_KHR_driver_properties."
Signed-off-by: Eric Engestrom 
---
 src/amd/vulkan/radv_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 8e43a3aab58620dfc756..73d0f9fe02db6bc74643 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1218,7 +1218,7 @@ void radv_GetPhysicalDeviceProperties2(
 
memset(driver_props->driverInfo, 0, 
VK_MAX_DRIVER_INFO_SIZE_KHR);
snprintf(driver_props->driverInfo, 
VK_MAX_DRIVER_INFO_SIZE_KHR,
-   "Mesa " PACKAGE_VERSION " (" MESA_GIT_SHA1 ")"
+   "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
" (LLVM %d.%d.%d)",
 (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
 MESA_LLVM_VERSION_PATCH);
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH 2/2] kmsro: Extend to include hx8357d.

2018-10-25 Thread Eric Anholt

This allows vc4 to initialize on the Adafruit PiTFT 3.5" touchscreen with
the new tinydrm driver I just submitted.  If this series extending the
pl111/kmsro driver is accepted, then I'll extend kmsro with the other
tinydrm drivers as well.
---
 src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c | 5 +
 src/gallium/drivers/kmsro/Android.mk| 1 +
 src/gallium/drivers/kmsro/Automake.inc  | 1 +
 src/gallium/targets/dri/meson.build | 1 +
 src/gallium/targets/dri/target.c| 1 +
 5 files changed, 9 insertions(+)

diff --git a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c 
b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
index 230bafe5e159..73ddab0cbf02 100644
--- a/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
+++ b/src/gallium/auxiliary/pipe-loader/pipe_loader_drm.c
@@ -111,6 +111,11 @@ static const struct drm_driver_descriptor 
driver_descriptors[] = {
 .create_screen = pipe_kmsro_create_screen,
 .configuration = pipe_default_configuration_query,
 },
+{
+   .driver_name = "hx8357d",
+.create_screen = pipe_kmsro_create_screen,
+.configuration = pipe_default_configuration_query,
+},
 {
 .driver_name = "virtio_gpu",
 .create_screen = pipe_virgl_create_screen,
diff --git a/src/gallium/drivers/kmsro/Android.mk 
b/src/gallium/drivers/kmsro/Android.mk
index 8a851024dc88..f6a444e8865b 100644
--- a/src/gallium/drivers/kmsro/Android.mk
+++ b/src/gallium/drivers/kmsro/Android.mk
@@ -35,5 +35,6 @@ include $(BUILD_STATIC_LIBRARY)
 
 ifneq ($(HAVE_GALLIUM_KMSRO),)
 GALLIUM_TARGET_DRIVERS += pl111
+GALLIUM_TARGET_DRIVERS += hx8357d
 $(eval GALLIUM_LIBS += $(LOCAL_MODULE) libmesa_winsys_kmsro)
 endif
diff --git a/src/gallium/drivers/kmsro/Automake.inc 
b/src/gallium/drivers/kmsro/Automake.inc
index 66d125cb440a..d5961c907653 100644
--- a/src/gallium/drivers/kmsro/Automake.inc
+++ b/src/gallium/drivers/kmsro/Automake.inc
@@ -1,6 +1,7 @@
 if HAVE_GALLIUM_KMSRO
 
 TARGET_DRIVERS += pl111
+TARGET_DRIVERS += hx8357d
 TARGET_CPPFLAGS += -DGALLIUM_KMSRO
 TARGET_LIB_DEPS += \
 $(top_builddir)/src/gallium/winsys/kmsro/drm/libkmsrodrm.la \
diff --git a/src/gallium/targets/dri/meson.build 
b/src/gallium/targets/dri/meson.build
index c1cb616b4dad..bc63702498ba 100644
--- a/src/gallium/targets/dri/meson.build
+++ b/src/gallium/targets/dri/meson.build
@@ -63,6 +63,7 @@ libgallium_dri = shared_library(
 )
 
 foreach d : [[with_gallium_kmsro, 'pl111_dri.so'],
+ [with_gallium_kmsro, 'hx8357d_dri.so'],
  [with_gallium_radeonsi, 'radeonsi_dri.so'],
  [with_gallium_nouveau, 'nouveau_dri.so'],
  [with_gallium_freedreno, ['msm_dri.so', 'kgsl_dri.so']],
diff --git a/src/gallium/targets/dri/target.c b/src/gallium/targets/dri/target.c
index 2821cef197ea..6b0ea785c405 100644
--- a/src/gallium/targets/dri/target.c
+++ b/src/gallium/targets/dri/target.c
@@ -78,6 +78,7 @@ DEFINE_LOADER_DRM_ENTRYPOINT(v3d)
 #if defined(GALLIUM_VC4)
 DEFINE_LOADER_DRM_ENTRYPOINT(vc4)
 #if defined(GALLIUM_KMSRO)
+DEFINE_LOADER_DRM_ENTRYPOINT(hx8357d)
 DEFINE_LOADER_DRM_ENTRYPOINT(pl111)
 #endif
 #endif
-- 
2.19.1

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[Mesa-dev] [PATCH 1/2] pl111: Rename the pl111 driver to "kmsro".

2018-10-25 Thread Eric Anholt

The vc4 driver can do prime sharing to many different KMS-only devices,
such as the various tinydrm drivers for SPI-attached displays.  Rename the
driver away from "pl111" to represent what it will actually support:
various sorts of KMS displays with the renderonly layer used to attach a
GPU.
---
 .travis.yml  |  2 +-
 Android.mk   |  4 ++--
 Makefile.am  |  2 +-
 configure.ac | 16 
 meson.build  |  8 
 meson_options.txt|  2 +-
 src/gallium/Android.mk   |  2 +-
 src/gallium/Makefile.am  |  4 ++--
 .../auxiliary/pipe-loader/pipe_loader_drm.c  |  2 +-
 .../auxiliary/target-helpers/drm_helper.h| 12 ++--
 .../auxiliary/target-helpers/drm_helper_public.h |  2 +-
 src/gallium/drivers/{pl111 => kmsro}/Android.mk  |  6 +++---
 src/gallium/drivers/kmsro/Automake.inc   |  9 +
 src/gallium/drivers/{pl111 => kmsro}/Makefile.am |  4 ++--
 .../drivers/{pl111 => kmsro}/Makefile.sources|  0
 src/gallium/drivers/pl111/Automake.inc   |  9 -
 src/gallium/meson.build  |  6 +++---
 src/gallium/targets/dri/Makefile.am  |  2 +-
 src/gallium/targets/dri/meson.build  |  4 ++--
 src/gallium/targets/dri/target.c |  2 +-
 .../winsys/{pl111 => kmsro}/drm/Android.mk   |  2 +-
 .../winsys/{pl111 => kmsro}/drm/Makefile.am  |  4 ++--
 src/gallium/winsys/kmsro/drm/Makefile.sources|  3 +++
 .../drm/kmsro_drm_public.h}  |  8 
 .../drm/kmsro_drm_winsys.c}  |  6 +++---
 .../winsys/{pl111 => kmsro}/drm/meson.build  | 12 ++--
 src/gallium/winsys/pl111/drm/Makefile.sources|  3 ---
 27 files changed, 68 insertions(+), 68 deletions(-)
 rename src/gallium/drivers/{pl111 => kmsro}/Android.mk (91%)
 create mode 100644 src/gallium/drivers/kmsro/Automake.inc
 rename src/gallium/drivers/{pl111 => kmsro}/Makefile.am (55%)
 rename src/gallium/drivers/{pl111 => kmsro}/Makefile.sources (100%)
 delete mode 100644 src/gallium/drivers/pl111/Automake.inc
 rename src/gallium/winsys/{pl111 => kmsro}/drm/Android.mk (97%)
 rename src/gallium/winsys/{pl111 => kmsro}/drm/Makefile.am (94%)
 create mode 100644 src/gallium/winsys/kmsro/drm/Makefile.sources
 rename src/gallium/winsys/{pl111/drm/pl111_drm_public.h => 
kmsro/drm/kmsro_drm_public.h} (89%)
 rename src/gallium/winsys/{pl111/drm/pl111_drm_winsys.c => 
kmsro/drm/kmsro_drm_winsys.c} (92%)
 rename src/gallium/winsys/{pl111 => kmsro}/drm/meson.build (87%)
 delete mode 100644 src/gallium/winsys/pl111/drm/Makefile.sources

diff --git a/.travis.yml b/.travis.yml
index 78e6d251ae4b..8bcd77143569 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -165,7 +165,7 @@ matrix:
 - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
 - DRI_DRIVERS=""
 - GALLIUM_ST="--enable-dri --disable-opencl --disable-xa 
--disable-nine --disable-xvmc --disable-vdpau --disable-va 
--disable-omx-bellagio --disable-gallium-osmesa"
-- 
GALLIUM_DRIVERS="i915,nouveau,pl111,r300,r600,freedreno,svga,swrast,v3d,vc4,virgl,etnaviv,imx"
+- 
GALLIUM_DRIVERS="i915,nouveau,kmsro,r300,r600,freedreno,svga,swrast,v3d,vc4,virgl,etnaviv,imx"
 - VULKAN_DRIVERS=""
 - LIBUNWIND_FLAGS="--enable-libunwind"
   addons:
diff --git a/Android.mk b/Android.mk
index 914854c27d63..1a0bdd1736cf 100644
--- a/Android.mk
+++ b/Android.mk
@@ -24,7 +24,7 @@
 # BOARD_GPU_DRIVERS should be defined.  The valid values are
 #
 #   classic drivers: i915 i965
-#   gallium drivers: swrast freedreno i915g nouveau pl111 r300g r600g radeonsi 
vc4 virgl vmwgfx etnaviv imx
+#   gallium drivers: swrast freedreno i915g nouveau kmsro r300g r600g radeonsi 
vc4 virgl vmwgfx etnaviv imx
 #
 # The main target is libGLES_mesa.  For each classic driver enabled, a DRI
 # module will also be built.  DRI modules will be loaded by libGLES_mesa.
@@ -52,7 +52,7 @@ gallium_drivers := \
freedreno.HAVE_GALLIUM_FREEDRENO \
i915g.HAVE_GALLIUM_I915 \
nouveau.HAVE_GALLIUM_NOUVEAU \
-   pl111.HAVE_GALLIUM_PL111 \
+   kmsro.HAVE_GALLIUM_KMSRO \
r300g.HAVE_GALLIUM_R300 \
r600g.HAVE_GALLIUM_R600 \
radeonsi.HAVE_GALLIUM_RADEONSI \
diff --git a/Makefile.am b/Makefile.am
index 9e27db046e52..62c755aeca7f 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -45,7 +45,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \
--enable-libunwind \
--with-platforms=x11,wayland,drm,surfaceless \
--with-dri-drivers=i915,i965,nouveau,radeon,r200,swrast \
-   
--with-gallium-drivers=i915,nouveau,r300,pl111,r600,radeonsi,freedreno,svga,swrast,vc4,tegra,virgl,swr,etnaviv,imx
 \
+

Re: [Mesa-dev] [PATCH] wayland/egl: Resize EGL surface on update buffer for swrast

2018-10-25 Thread Juan A. Suarez Romero

On Thu, 2018-10-25 at 14:48 +0200, Olivier Fourdan wrote:
> After commit a9fb331ea ("wayland/egl: update surface size on window
> resize"), the surface size is updated as soon as the resize is done, and
> `update_buffers()` would resize only if the surface size differs from
> the attached size.
> 
> However, in the case of swrast, there is no resize callback and the
> attached size is updated in `dri2_wl_swrast_commit_backbuffer()` prior
> to the `swrast_update_buffers()` so the attached size is always up to
> date when it reaches `swrast_update_buffers()` and the surface is never
> resized.
> 
> This can be observed with "totem" using the GDK backend on Wayland (the
> default) when running on software rendering:
> 
>   $ LIBGL_ALWAYS_SOFTWARE=true CLUTTER_BACKEND=gdk totem
> 
> Resizing the window would leave the EGL surface size unchanged.
> 
> To avoid the issue, partially revert the part of commit a9fb331ea for
> `swrast_update_buffers()` and resize on the win size and not the
> attached size.
> 
> Fixes: a9fb331ea - wayland/egl: update surface size on window resize
> Signed-off-by: Olivier Fourdan 
> CC: Daniel Stone 
> CC: Juan A. Suarez Romero 
> CC: mesa-sta...@lists.freedesktop.org
> ---

I've been checking why this happened. Turns out that in the original patch, we
update the size in the resize_callback(), so we need to do the changes in
update_buffers() accordingly.

But turns out that with swrast we are not invoking resize_callback(), so we need
to keep the old code in swrast_update_buffers().

Thanks for finding this.

Reviewed-by: Juan A. Suarez 


>  Resending because I got the "mesa-dev" address wrong! And a reply to the
>  previous email won't fly with patchwork... Sorry! 
> 
>  src/egl/drivers/dri2/platform_wayland.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/src/egl/drivers/dri2/platform_wayland.c 
> b/src/egl/drivers/dri2/platform_wayland.c
> index 03a3e0993b..69a51e64fd 100644
> --- a/src/egl/drivers/dri2/platform_wayland.c
> +++ b/src/egl/drivers/dri2/platform_wayland.c
> @@ -1652,8 +1652,8 @@ swrast_update_buffers(struct dri2_egl_surface 
> *dri2_surf)
> if (dri2_surf->back)
>return 0;
>  
> -   if (dri2_surf->base.Width != dri2_surf->wl_win->attached_width ||
> -   dri2_surf->base.Height != dri2_surf->wl_win->attached_height) {
> +   if (dri2_surf->base.Width != dri2_surf->wl_win->width ||
> +   dri2_surf->base.Height != dri2_surf->wl_win->height) {
>  
>dri2_wl_release_buffers(dri2_surf);
>  

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Re: [Mesa-dev] [PATCH mesa] vulkan: drop always-true param

Reviewed-by: Jason Ekstrand 

On Thu, Oct 25, 2018 at 5:17 AM Eric Engestrom 
wrote:

> Signed-off-by: Eric Engestrom 
> ---
>  src/amd/vulkan/radv_wsi_x11.c   | 2 --
>  src/intel/vulkan/anv_wsi_x11.c  | 2 --
>  src/vulkan/wsi/wsi_common_x11.c | 5 -
>  src/vulkan/wsi/wsi_common_x11.h | 1 -
>  4 files changed, 10 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_wsi_x11.c b/src/amd/vulkan/radv_wsi_x11.c
> index f3ebc791e2dc8a8fe8d8..acad74d3cf2a4d48d3ce 100644
> --- a/src/amd/vulkan/radv_wsi_x11.c
> +++ b/src/amd/vulkan/radv_wsi_x11.c
> @@ -45,7 +45,6 @@ VkBool32 radv_GetPhysicalDeviceXcbPresentationSupportKHR(
> return wsi_get_physical_device_xcb_presentation_support(
>>wsi_device,
>queueFamilyIndex,
> -  true,
>connection, visual_id);
>  }
>
> @@ -60,7 +59,6 @@ VkBool32
> radv_GetPhysicalDeviceXlibPresentationSupportKHR(
> return wsi_get_physical_device_xcb_presentation_support(
>>wsi_device,
>queueFamilyIndex,
> -  true,
>XGetXCBConnection(dpy), visualID);
>  }
>
> diff --git a/src/intel/vulkan/anv_wsi_x11.c
> b/src/intel/vulkan/anv_wsi_x11.c
> index 7a27ceab64fecbfe199b..9a50b17f99937b48fc93 100644
> --- a/src/intel/vulkan/anv_wsi_x11.c
> +++ b/src/intel/vulkan/anv_wsi_x11.c
> @@ -41,7 +41,6 @@ VkBool32 anv_GetPhysicalDeviceXcbPresentationSupportKHR(
> return wsi_get_physical_device_xcb_presentation_support(
>>wsi_device,
>queueFamilyIndex,
> -  true,
>connection, visual_id);
>  }
>
> @@ -56,7 +55,6 @@ VkBool32 anv_GetPhysicalDeviceXlibPresentationSupportKHR(
> return wsi_get_physical_device_xcb_presentation_support(
>>wsi_device,
>queueFamilyIndex,
> -  true,
>XGetXCBConnection(dpy), visualID);
>  }
>
> diff --git a/src/vulkan/wsi/wsi_common_x11.c
> b/src/vulkan/wsi/wsi_common_x11.c
> index 6eb72827eda5a6ce67c7..c740726fe54746f8bfc3 100644
> --- a/src/vulkan/wsi/wsi_common_x11.c
> +++ b/src/vulkan/wsi/wsi_common_x11.c
> @@ -375,7 +375,6 @@ visual_has_alpha(xcb_visualtype_t *visual, unsigned
> depth)
>  VkBool32 wsi_get_physical_device_xcb_presentation_support(
>  struct wsi_device *wsi_device,
>  uint32_tqueueFamilyIndex,
> -bool can_handle_different_gpu,
>  xcb_connection_t*   connection,
>  xcb_visualid_t  visual_id)
>  {
> @@ -388,10 +387,6 @@ VkBool32
> wsi_get_physical_device_xcb_presentation_support(
> if (!wsi_x11_check_for_dri3(wsi_conn))
>return false;
>
> -   if (!can_handle_different_gpu)
> -  if (!wsi_x11_check_dri3_compatible(wsi_device, connection))
> - return false;
> -
> unsigned visual_depth;
> if (!connection_get_visualtype(connection, visual_id, _depth))
>return false;
> diff --git a/src/vulkan/wsi/wsi_common_x11.h
> b/src/vulkan/wsi/wsi_common_x11.h
> index 99b1bcdc6fd73487b3df..e4b1e94a8c8c9d4bbed6 100644
> --- a/src/vulkan/wsi/wsi_common_x11.h
> +++ b/src/vulkan/wsi/wsi_common_x11.h
> @@ -28,7 +28,6 @@
>  VkBool32 wsi_get_physical_device_xcb_presentation_support(
>  struct wsi_device *wsi_device,
>  uint32_tqueueFamilyIndex,
> -bool can_handle_different_gpu,
>  xcb_connection_t*   connection,
>  xcb_visualid_t  visual_id);
>
> --
> Cheers,
>   Eric
>
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Re: [Mesa-dev] [PATCH] mesa: expose EXT_texture_compression_s3tc on GLES

2018-10-25 Thread Ilia Mirkin

Please confirm that this passes the piglit tests you sent to the list
when run with ES2 forced, i.e. not ES3.
(MESA_GLES_VERSION_OVERRIDE=2.0 iirc.) I'm concerned that the extra
logic was only added to _mesa_es3_error_check_bla and not the es2
paths.
On Thu, Oct 25, 2018 at 6:59 AM Erik Faye-Lund
 wrote:
>
> From: Marek Olšák 
>
> The spec was modified to support GLES.
>
> Tested-by: Erik Faye-Lund 
> ---
> This replaces this patch:
> https://patchwork.freedesktop.org/patch/257423/
>
>  docs/relnotes/18.3.0.html|  1 +
>  src/mesa/main/extensions_table.h |  2 +-
>  src/mesa/main/glformats.c| 11 +++
>  3 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
> index 5874d3fa330..e0061872de4 100644
> --- a/docs/relnotes/18.3.0.html
> +++ b/docs/relnotes/18.3.0.html
> @@ -57,6 +57,7 @@ Note: some of the new features are only available with 
> certain drivers.
>  GL_AMD_multi_draw_indirect on all GL 4.x drivers.
>  GL_AMD_query_buffer_object on i965, nvc0, r600, radeonsi.
>  GL_EXT_disjoint_timer_query on radeonsi and most other Gallium drivers 
> (ES extension)
> +GL_EXT_texture_compression_s3tc on all drivers (ES extension)
>  GL_EXT_vertex_attrib_64bit on i965, nvc0, radeonsi.
>  GL_EXT_window_rectangles on radeonsi.
>  GL_KHR_texture_compression_astc_sliced_3d on radeonsi.
> diff --git a/src/mesa/main/extensions_table.h 
> b/src/mesa/main/extensions_table.h
> index 09bf923bd0e..47db1583135 100644
> --- a/src/mesa/main/extensions_table.h
> +++ b/src/mesa/main/extensions_table.h
> @@ -278,7 +278,7 @@ EXT(EXT_texture_buffer  , 
> OES_texture_buffer
>  EXT(EXT_texture_compression_dxt1, ANGLE_texture_compression_dxt  
> , GLL, GLC, ES1, ES2, 2004)
>  EXT(EXT_texture_compression_latc, EXT_texture_compression_latc   
> , GLL,  x ,  x ,  x , 2006)
>  EXT(EXT_texture_compression_rgtc, ARB_texture_compression_rgtc   
> , GLL, GLC,  x ,  x , 2004)
> -EXT(EXT_texture_compression_s3tc, EXT_texture_compression_s3tc   
> , GLL, GLC,  x ,  x , 2000)
> +EXT(EXT_texture_compression_s3tc, EXT_texture_compression_s3tc   
> , GLL, GLC,  x , ES2, 2000)
>  EXT(EXT_texture_cube_map, ARB_texture_cube_map   
> , GLL,  x ,  x ,  x , 2001)
>  EXT(EXT_texture_cube_map_array  , OES_texture_cube_map_array 
> ,  x ,  x ,  x ,  31, 2014)
>  EXT(EXT_texture_edge_clamp  , dummy_true 
> , GLL,  x ,  x ,  x , 1997)
> diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
> index 6cb3435dea2..f8fc36e9311 100644
> --- a/src/mesa/main/glformats.c
> +++ b/src/mesa/main/glformats.c
> @@ -2803,6 +2803,17 @@ _mesa_es3_error_check_format_and_type(const struct 
> gl_context *ctx,
>internalFormat = effectiveInternalFormat;
> }
>
> +   /* The GLES variant of EXT_texture_compression_s3tc is very vague and
> +* doesn't list valid types. Just do exactly what the spec says.
> +*/
> +   if (ctx->Extensions.EXT_texture_compression_s3tc &&
> +   (internalFormat == GL_COMPRESSED_RGB_S3TC_DXT1_EXT ||
> +internalFormat == GL_COMPRESSED_RGBA_S3TC_DXT1_EXT ||
> +internalFormat == GL_COMPRESSED_RGBA_S3TC_DXT3_EXT ||
> +internalFormat == GL_COMPRESSED_RGBA_S3TC_DXT5_EXT))
> +  return format == GL_RGB || format == GL_RGBA ? GL_NO_ERROR :
> + GL_INVALID_OPERATION;
> +
> switch (format) {
> case GL_BGRA_EXT:
>if (type != GL_UNSIGNED_BYTE || internalFormat != GL_BGRA)
> --
> 2.17.2
>
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[Mesa-dev] [Bug 108524] [RADV] GPU lockup on event synchronization

https://bugs.freedesktop.org/show_bug.cgi?id=108524

Bas Nieuwenhuizen  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #2 from Bas Nieuwenhuizen  ---
Fixed with

commit d41c3cc01314fd2586ad2392a05647197d04c28d
Author: Bas Nieuwenhuizen 
Date:   Tue Oct 23 10:54:24 2018 +0200

radv: Emit enqueued pipeline barriers on event write.

Since the CPU can read them we need to execute any GPU->CPU
flushes before the event is written.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108524
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Samuel Pitoiset 

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Re: [Mesa-dev] [PATCH 2/2] st/nir: Drop unused parameter from st_nir_assign_uniform_locations().

2018-10-25 Thread Rob Clark

On Thu, Oct 25, 2018 at 5:22 AM Kenneth Graunke  wrote:
>
> ARB programs won't have one of these, and we don't use it anyway.

Reviewed-by: Rob Clark 

> ---
>  src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
> b/src/mesa/state_tracker/st_glsl_to_nir.cpp
> index c15bd7e511b..dcde95cd609 100644
> --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
> @@ -240,7 +240,6 @@ st_nir_lookup_parameter_index(const struct 
> gl_program_parameter_list *params,
>  static void
>  st_nir_assign_uniform_locations(struct gl_context *ctx,
>  struct gl_program *prog,
> -struct gl_shader_program *shader_program,
>  struct exec_list *uniform_list, unsigned 
> *size)
>  {
> int max = 0;
> @@ -849,7 +848,7 @@ st_finalize_nir(struct st_context *st, struct gl_program 
> *prog,
> NIR_PASS_V(nir, nir_lower_atomics_to_ssbo,
>   st->ctx->Const.Program[nir->info.stage].MaxAtomicBuffers);
>
> -   st_nir_assign_uniform_locations(st->ctx, prog, shader_program,
> +   st_nir_assign_uniform_locations(st->ctx, prog,
> >uniforms, >num_uniforms);
>
> if (st->ctx->Const.PackedDriverUniformStorage) {
> --
> 2.19.0
>
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Re: [Mesa-dev] [PATCH 1/2] st/mesa: Pull nir_lower_wpos_ytransform work into a helper function.

2018-10-25 Thread Rob Clark

On Thu, Oct 25, 2018 at 5:22 AM Kenneth Graunke  wrote:
>
> This will let me use it in the ARB program code as well.

lgtm,

Reviewed-by: Rob Clark 

> ---
>  src/mesa/state_tracker/st_glsl_to_nir.cpp | 66 +--
>  src/mesa/state_tracker/st_nir.h   |  4 ++
>  2 files changed, 41 insertions(+), 29 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
> b/src/mesa/state_tracker/st_glsl_to_nir.cpp
> index 911284401e0..c15bd7e511b 100644
> --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
> @@ -619,6 +619,41 @@ st_nir_link_shaders(nir_shader **producer, nir_shader 
> **consumer, bool scalar)
>
>  extern "C" {
>
> +void
> +st_nir_lower_wpos_ytransform(struct nir_shader *nir,
> + struct gl_program *prog,
> + struct pipe_screen *pscreen)
> +{
> +   if (nir->info.stage != MESA_SHADER_FRAGMENT)
> +  return;
> +
> +   static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
> +  STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
> +   };
> +   nir_lower_wpos_ytransform_options wpos_options = { { 0 } };
> +
> +   memcpy(wpos_options.state_tokens, wposTransformState,
> +  sizeof(wpos_options.state_tokens));
> +   wpos_options.fs_coord_origin_upper_left =
> +  pscreen->get_param(pscreen,
> + PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT);
> +   wpos_options.fs_coord_origin_lower_left =
> +  pscreen->get_param(pscreen,
> + PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
> +   wpos_options.fs_coord_pixel_center_integer =
> +  pscreen->get_param(pscreen,
> + PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
> +   wpos_options.fs_coord_pixel_center_half_integer =
> +  pscreen->get_param(pscreen,
> + PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER);
> +
> +   if (nir_lower_wpos_ytransform(nir, _options)) {
> +  nir_validate_shader(nir);
> +  _mesa_add_state_reference(prog->Parameters,
> +wposTransformState);
> +   }
> +}
> +
>  bool
>  st_link_nir(struct gl_context *ctx,
>  struct gl_shader_program *shader_program)
> @@ -697,35 +732,8 @@ st_link_nir(struct gl_context *ctx,
>
>nir_shader *nir = shader->Program->nir;
>
> -  /* fragment shaders may need : */
> -  if (nir->info.stage == MESA_SHADER_FRAGMENT) {
> - static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
> -STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
> - };
> - nir_lower_wpos_ytransform_options wpos_options = { { 0 } };
> - struct pipe_screen *pscreen = st->pipe->screen;
> -
> - memcpy(wpos_options.state_tokens, wposTransformState,
> -sizeof(wpos_options.state_tokens));
> - wpos_options.fs_coord_origin_upper_left =
> -pscreen->get_param(pscreen,
> -   PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT);
> - wpos_options.fs_coord_origin_lower_left =
> -pscreen->get_param(pscreen,
> -   PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
> - wpos_options.fs_coord_pixel_center_integer =
> -pscreen->get_param(pscreen,
> -   PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
> - wpos_options.fs_coord_pixel_center_half_integer =
> -pscreen->get_param(pscreen,
> -   
> PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER);
> -
> - if (nir_lower_wpos_ytransform(nir, _options)) {
> -nir_validate_shader(nir);
> -_mesa_add_state_reference(shader->Program->Parameters,
> -  wposTransformState);
> - }
> -  }
> +  NIR_PASS_V(nir, st_nir_lower_wpos_ytransform, shader->Program,
> + st->pipe->screen);
>
>NIR_PASS_V(nir, nir_lower_system_values);
>
> diff --git a/src/mesa/state_tracker/st_nir.h b/src/mesa/state_tracker/st_nir.h
> index aa6e32758e8..10f23c03ef6 100644
> --- a/src/mesa/state_tracker/st_nir.h
> +++ b/src/mesa/state_tracker/st_nir.h
> @@ -38,6 +38,10 @@ void st_nir_lower_tex_src_plane(struct nir_shader *shader, 
> unsigned free_slots,
>  unsigned lower_2plane, unsigned 
> lower_3plane);
>  bool st_nir_lower_uniforms_to_ubo(struct nir_shader *shader);
>
> +void st_nir_lower_wpos_ytransform(struct nir_shader *nir,
> +  struct gl_program *prog,
> +  struct pipe_screen *pscreen);
> +
>  void st_finalize_nir(struct st_context *st, struct gl_program *prog,
>   struct gl_shader_program *shader_program,
>   struct nir_shader *nir);
> --
> 2.19.0
>
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Re: [Mesa-dev] [PATCH 5/5] radv: implement image to image operations for R32G32B32

2018-10-25 Thread Bas Nieuwenhuizen

Reviewed-by: Bas Nieuwenhuizen 

for the series.
On Wed, Oct 24, 2018 at 8:48 AM Samuel Pitoiset
 wrote:
>
> This should address the remaining failures in Batman Arkhman City.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107765
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_meta_bufimage.c | 320 
>  src/amd/vulkan/radv_meta_copy.c |   8 +-
>  src/amd/vulkan/radv_private.h   |   5 +
>  3 files changed, 331 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta_bufimage.c 
> b/src/amd/vulkan/radv_meta_bufimage.c
> index 56f1620db5..6f074a70b4 100644
> --- a/src/amd/vulkan/radv_meta_bufimage.c
> +++ b/src/amd/vulkan/radv_meta_bufimage.c
> @@ -909,6 +909,216 @@ radv_device_finish_meta_itoi_state(struct radv_device 
> *device)
>  state->itoi.pipeline_3d, >alloc);
>  }
>
> +static nir_shader *
> +build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev)
> +{
> +   nir_builder b;
> +   const struct glsl_type *type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF,
> +false,
> +false,
> +GLSL_TYPE_FLOAT);
> +   nir_builder_init_simple_shader(, NULL, MESA_SHADER_COMPUTE, NULL);
> +   b.shader->info.name = ralloc_strdup(b.shader, 
> "meta_itoi_r32g32b32_cs");
> +   b.shader->info.cs.local_size[0] = 16;
> +   b.shader->info.cs.local_size[1] = 16;
> +   b.shader->info.cs.local_size[2] = 1;
> +   nir_variable *input_img = nir_variable_create(b.shader, 
> nir_var_uniform,
> + type, "input_img");
> +   input_img->data.descriptor_set = 0;
> +   input_img->data.binding = 0;
> +
> +   nir_variable *output_img = nir_variable_create(b.shader, 
> nir_var_uniform,
> + type, "output_img");
> +   output_img->data.descriptor_set = 0;
> +   output_img->data.binding = 1;
> +
> +   nir_ssa_def *invoc_id = nir_load_system_value(, 
> nir_intrinsic_load_local_invocation_id, 0);
> +   nir_ssa_def *wg_id = nir_load_system_value(, 
> nir_intrinsic_load_work_group_id, 0);
> +   nir_ssa_def *block_size = nir_imm_ivec4(,
> +   
> b.shader->info.cs.local_size[0],
> +   
> b.shader->info.cs.local_size[1],
> +   
> b.shader->info.cs.local_size[2], 0);
> +
> +   nir_ssa_def *global_id = nir_iadd(, nir_imul(, wg_id, 
> block_size), invoc_id);
> +
> +   nir_intrinsic_instr *src_offset = 
> nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +   nir_intrinsic_set_base(src_offset, 0);
> +   nir_intrinsic_set_range(src_offset, 24);
> +   src_offset->src[0] = nir_src_for_ssa(nir_imm_int(, 0));
> +   src_offset->num_components = 3;
> +   nir_ssa_dest_init(_offset->instr, _offset->dest, 3, 32, 
> "src_offset");
> +   nir_builder_instr_insert(, _offset->instr);
> +
> +   nir_ssa_def *src_stride = nir_channel(, _offset->dest.ssa, 2);
> +
> +   nir_intrinsic_instr *dst_offset = 
> nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
> +   nir_intrinsic_set_base(dst_offset, 0);
> +   nir_intrinsic_set_range(dst_offset, 24);
> +   dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(, 12));
> +   dst_offset->num_components = 3;
> +   nir_ssa_dest_init(_offset->instr, _offset->dest, 3, 32, 
> "dst_offset");
> +   nir_builder_instr_insert(, _offset->instr);
> +
> +   nir_ssa_def *dst_stride = nir_channel(, _offset->dest.ssa, 2);
> +
> +   nir_ssa_def *src_img_coord = nir_iadd(, global_id, 
> _offset->dest.ssa);
> +   nir_ssa_def *dst_img_coord = nir_iadd(, global_id, 
> _offset->dest.ssa);
> +
> +   nir_ssa_def *src_global_pos =
> +   nir_iadd(,
> +nir_imul(, nir_channel(, src_img_coord, 1), 
> src_stride),
> +nir_imul(, nir_channel(, src_img_coord, 0), 
> nir_imm_int(, 3)));
> +
> +   nir_ssa_def *dst_global_pos =
> +   nir_iadd(,
> +nir_imul(, nir_channel(, dst_img_coord, 1), 
> dst_stride),
> +nir_imul(, nir_channel(, dst_img_coord, 0), 
> nir_imm_int(, 3)));
> +
> +   for (int chan = 0; chan < 3; chan++) {
> +   /* src */
> +   nir_ssa_def *src_local_pos =
> +   nir_iadd(, src_global_pos, nir_imm_int(, chan));
> +
> +   nir_ssa_def *src_coord =
> +   nir_vec4(, src_local_pos, src_local_pos,
> +src_local_pos, src_local_pos);
> +
> +   nir_ssa_def *input_img_deref = _build_deref_var(, 
> input_img)->dest.ssa;
> +
> +

[Mesa-dev] [PATCH] wayland/egl: Resize EGL surface on update buffer for swrast

After commit a9fb331ea ("wayland/egl: update surface size on window
resize"), the surface size is updated as soon as the resize is done, and
`update_buffers()` would resize only if the surface size differs from
the attached size.

However, in the case of swrast, there is no resize callback and the
attached size is updated in `dri2_wl_swrast_commit_backbuffer()` prior
to the `swrast_update_buffers()` so the attached size is always up to
date when it reaches `swrast_update_buffers()` and the surface is never
resized.

This can be observed with "totem" using the GDK backend on Wayland (the
default) when running on software rendering:

  $ LIBGL_ALWAYS_SOFTWARE=true CLUTTER_BACKEND=gdk totem

Resizing the window would leave the EGL surface size unchanged.

To avoid the issue, partially revert the part of commit a9fb331ea for
`swrast_update_buffers()` and resize on the win size and not the
attached size.

Fixes: a9fb331ea - wayland/egl: update surface size on window resize
Signed-off-by: Olivier Fourdan 
CC: Daniel Stone 
CC: Juan A. Suarez Romero 
CC: mesa-sta...@lists.freedesktop.org
---
 Resending because I got the "mesa-dev" address wrong! And a reply to the
 previous email won't fly with patchwork... Sorry! 

 src/egl/drivers/dri2/platform_wayland.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 03a3e0993b..69a51e64fd 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -1652,8 +1652,8 @@ swrast_update_buffers(struct dri2_egl_surface *dri2_surf)
if (dri2_surf->back)
   return 0;
 
-   if (dri2_surf->base.Width != dri2_surf->wl_win->attached_width ||
-   dri2_surf->base.Height != dri2_surf->wl_win->attached_height) {
+   if (dri2_surf->base.Width != dri2_surf->wl_win->width ||
+   dri2_surf->base.Height != dri2_surf->wl_win->height) {
 
   dri2_wl_release_buffers(dri2_surf);
 
-- 
2.19.1

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Re: [Mesa-dev] [PATCH] wayland/egl: Resize EGL surface on update buffer for swrast

Oops got the mesa-dev address wrong...

On Thu, Oct 25, 2018 at 2:40 PM Olivier Fourdan  wrote:
>
> After commit a9fb331ea ("wayland/egl: update surface size on window
> resize"), the surface size is updated as soon as the resize is done, and
> `update_buffers()` would resize only if the surface size differs from
> the attached size.
>
> However, in the case of swrast, there is no resize callback and the
> attached size is updated in `dri2_wl_swrast_commit_backbuffer()` prior
> to the `swrast_update_buffers()` so the attached size is always up to
> date when it reaches `swrast_update_buffers()` and the surface is never
> resized.
>
> This can be observed with "totem" using the GDK backend on Wayland (the
> default) when running on software rendering:
>
>   $ LIBGL_ALWAYS_SOFTWARE=true CLUTTER_BACKEND=gdk totem
>
> Resizing the window would leave the EGL surface size unchanged.
>
> To avoid the issue, partially revert the part of commit a9fb331ea for
> `swrast_update_buffers()` and resize on the win size and not the
> attached size.
>
> Fixes: a9fb331ea - wayland/egl: update surface size on window resize
> Signed-off-by: Olivier Fourdan 
> CC: Daniel Stone 
> CC: Juan A. Suarez Romero 
> CC: mesa-sta...@lists.freedesktop.org
> ---
>  src/egl/drivers/dri2/platform_wayland.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/platform_wayland.c 
> b/src/egl/drivers/dri2/platform_wayland.c
> index 03a3e0993b..69a51e64fd 100644
> --- a/src/egl/drivers/dri2/platform_wayland.c
> +++ b/src/egl/drivers/dri2/platform_wayland.c
> @@ -1652,8 +1652,8 @@ swrast_update_buffers(struct dri2_egl_surface 
> *dri2_surf)
> if (dri2_surf->back)
>return 0;
>
> -   if (dri2_surf->base.Width != dri2_surf->wl_win->attached_width ||
> -   dri2_surf->base.Height != dri2_surf->wl_win->attached_height) {
> +   if (dri2_surf->base.Width != dri2_surf->wl_win->width ||
> +   dri2_surf->base.Height != dri2_surf->wl_win->height) {
>
>dri2_wl_release_buffers(dri2_surf);
>
> --
> 2.19.1
>
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Re: [Mesa-dev] [PATCH mesa] util: remove unnecessary random whitespaces

On Thursday, 2018-10-25 17:54:16 +1100, Timothy Arceri wrote:
> On 25/10/18 7:42 am, Ian Romanick wrote:
> > On 10/23/2018 04:15 AM, Eric Engestrom wrote:
> > > Suggested-by: Timothy Arceri 
> 
> Um no :P I suggested you fix the formatting in your patch to match the Mesa
> style.

Right, sorry, you suggested fixing the formatting, but not the fix
I went with, so I should've dropped this tag.

> 
> > > Signed-off-by: Eric Engestrom 
> > > ---
> > > Timothy, I opted to remove them all instead of adding even more, as it
> > > would break again next time something changes (the set_foreach() one was
> > > already broken before my patch for instance) and result in lots of
> > > unnecessary churn for seemingly no gain, and I don't like hiding the
> > > backslash away (it hinders readability).
> > 
> > NAK... we use this formatting everywhere in Mesa.  The point is to move
> > the \ characters out of the way.  When you're trying to read a
> > multi-line macro, they are distracting, so it is nice to move them over.

I don't have the same opinion, but respecting mesa style is the point
here, so I added those whitespace chars, squashed them in the previous
patches, and pushed them.

Sorry for this patch :)

> > 
> > > ---
> > >   src/util/hash_table.h | 6 +++---
> > >   src/util/set.h| 6 +++---
> > >   2 files changed, 6 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/src/util/hash_table.h b/src/util/hash_table.h
> > > index b96cd6146960a6a6f8a1..b9c9dfa01aeaa5e9cac1 100644
> > > --- a/src/util/hash_table.h
> > > +++ b/src/util/hash_table.h
> > > @@ -139,9 +139,9 @@ _mesa_fnv32_1a_accumulate_block(uint32_t hash, const 
> > > void *data, size_t size)
> > >* an entry's data with the deleted marker), but not against insertion
> > >* (which may rehash the table, making entry a dangling pointer).
> > >*/
> > > -#define hash_table_foreach(ht, entry)   \
> > > -   for (struct hash_entry *entry = _mesa_hash_table_next_entry(ht, 
> > > NULL);  \
> > > -entry != NULL;  \
> > > +#define hash_table_foreach(ht, entry) \
> > > +   for (struct hash_entry *entry = _mesa_hash_table_next_entry(ht, 
> > > NULL); \
> > > +entry != NULL; \
> > >   entry = _mesa_hash_table_next_entry(ht, entry))
> > >   static inline void
> > > diff --git a/src/util/set.h b/src/util/set.h
> > > index 3c9abfe77128292557ec..4307f4732fd4fde132a0 100644
> > > --- a/src/util/set.h
> > > +++ b/src/util/set.h
> > > @@ -96,9 +96,9 @@ _mesa_set_random_entry(struct set *set,
> > >* insertion (which may rehash the set, making entry a dangling
> > >* pointer).
> > >*/
> > > -#define set_foreach(set, entry)  \
> > > -   for (struct set_entry *entry = _mesa_set_next_entry(set, NULL);  \
> > > -entry != NULL;   \
> > > +#define set_foreach(set, entry) \
> > > +   for (struct set_entry *entry = _mesa_set_next_entry(set, NULL); \
> > > +entry != NULL; \
> > >   entry = _mesa_set_next_entry(set, entry))
> > >   #ifdef __cplusplus
> > > 
> > 
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Re: [Mesa-dev] [PATCH] m4: add Werror when checking for compiler flags

On Wednesday, 2018-10-24 11:26:56 -0700, Dylan Baker wrote:
> Quoting Emil Velikov (2018-10-24 10:57:00)
> > Seemingly that at some point clang started accepting _any_ flags,
> > whereas previously it would error out.
> > 
> > These days, you can give it -Whamsandwich and it will succeed, while
> > at the same time throwing an annoying warning.
> > 
> > Add -Werror so that everything gets flagged and set accordingly.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108082
> > Cc: Eric Engestrom 
> > Cc: Dylan Baker 
> > Cc: Vinson Lee 
> > Repored-by: Vinson Lee 
> > Signed-off-by: Emil Velikov 
> > ---
> >  m4/ax_check_compile_flag.m4 | 7 ++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> > 
> > diff --git a/m4/ax_check_compile_flag.m4 b/m4/ax_check_compile_flag.m4
> > index 51df0c09a7a..0fdca907e8b 100644
> > --- a/m4/ax_check_compile_flag.m4
> > +++ b/m4/ax_check_compile_flag.m4
> > @@ -55,6 +55,11 @@
> >  #   modified version of the Autoconf Macro, you may extend this special
> >  #   exception to the GPL to apply to your modified version as well.
> >  
> > +# Emil:
> > +# Toggle Werror since at some point clang started treating unknown -W
> > +# flags as warnings, succeeding with the build, yet issuing an annoying
> > +# warning.
> > +
> >  #serial 3
> >  
> >  AC_DEFUN([AX_CHECK_COMPILE_FLAG],
> > @@ -62,7 +67,7 @@ AC_DEFUN([AX_CHECK_COMPILE_FLAG],
> >  AS_VAR_PUSHDEF([CACHEVAR],[ax_cv_check_[]_AC_LANG_ABBREV[]flags_$4_$1])dnl
> >  AC_CACHE_CHECK([whether _AC_LANG compiler accepts $1], CACHEVAR, [
> >ax_check_save_flags=$[]_AC_LANG_PREFIX[]FLAGS
> > -  _AC_LANG_PREFIX[]FLAGS="$[]_AC_LANG_PREFIX[]FLAGS $4 $1"
> > +  _AC_LANG_PREFIX[]FLAGS="$[]_AC_LANG_PREFIX[]FLAGS $4 $1 -Werror"
> >AC_COMPILE_IFELSE([m4_default([$5],[AC_LANG_PROGRAM()])],
> >  [AS_VAR_SET(CACHEVAR,[yes])],
> >  [AS_VAR_SET(CACHEVAR,[no])])
> > -- 
> > 2.19.1
> > 
> 
> This seems like the most straightforward way to solve the issue, since 
> otherwise
> you need to track which compiler you have.

Agreed; thanks for tracking it down!

> 
> Reviewed-by: Dylan Baker 

Reviewed-by: Eric Engestrom 
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Re: [Mesa-dev] Meson windows v5 (10/19/2018) review

2018-10-25 Thread Jose Fonseca

On 21/10/18 20:54, Liviu Prodea wrote:
1. When using Meson 0.48.x both -Dc_args -Dcpp_args and -Db_vscrt
methods of selecting the CRT are ineffective on changing the CRT from MD
to MT resulting in build failure if LLVM is built with MT CRT. This
issue persists from last time I tested this WIP branch. However if MT
built LLVM is indeed unsupported unlike Scons I am OK with it as long as
it is documented.

2. Assuming no 1 has been worked around (we have LLVM built with MD CRT
available), LLVM JIT-ed drivers like llvmpipe and swr cannot be selected
despite resulted opengl32.dll being around 20MB and swr DLLs being built
as well only when expected. Tested with GPU Caps Viewer (a 32-bit only
software), it reports the driver as softpipe OpenGL 3.1 with 248
extensions. Since it's 32-bit app I did not attempt to build swr for
this test as it's unsupported for 32-bit apps. It appears this is a
really persistent issue as I had it right from the first time I tested
this branch. Maybe I need to change the recipe I use to build LLVM so
that I use Meson instead of CMake. That would be really unpleasant if it
turns out to be the root of this problem. I have this marked as optional
and it is on least priority on my TODO list:

https://github.com/pal1000/mesa-dist-win/issues/7

3. More filename parity with Scons similar to

https://gitlab.freedesktop.org/dbaker/mesa/commit/f31d0802da6a20b3878a789bb38c9733c4b0ff24#bda6b0f93966e610f473867639a87adfc5437011

- swrAVX-0.dll should be swrAVX.dll

- swrAVX2-0.dll should be swrAVX2.dll

- libOsmesa.dll should be osmesa.dll

4. opengl32.dll built with Meson depends on shared library z.dll. I have
absolutely no problem with this but Jose Fonseca may not like this
considering one of his replies from the Scons gles option conversations.

Yep, we really don't want opengl32.dll (or any Mesa based OpenGL ICD) to
depend on any DLL whatsoever besides Windows standard DLLs (this
excludes even MSVC runtime, hence the need of /MT /MTd.) This is
because these drivers will be loaded onto arbitrary process are normally
installed into C:\Windows\system32, hence any dependencies will need to
be installed there, so depending on a z.dll could clash with z.dll
shipped by applications

Regarding MT vs MTd, I've often considered just always use /MT and side
step the runtime mismatch issue completely, because I honestly don't
remember the debug C runtime ever helping debugging anything. In fact,
we often use cross compiled MinGW binaries for day-to-day development
anyway.

Jose
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[Mesa-dev] [PATCH] mesa: expose EXT_texture_compression_s3tc on GLES

2018-10-25 Thread Erik Faye-Lund

From: Marek Olšák 

The spec was modified to support GLES.

Tested-by: Erik Faye-Lund 
---
This replaces this patch:
https://patchwork.freedesktop.org/patch/257423/

 docs/relnotes/18.3.0.html|  1 +
 src/mesa/main/extensions_table.h |  2 +-
 src/mesa/main/glformats.c| 11 +++
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
index 5874d3fa330..e0061872de4 100644
--- a/docs/relnotes/18.3.0.html
+++ b/docs/relnotes/18.3.0.html
@@ -57,6 +57,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_AMD_multi_draw_indirect on all GL 4.x drivers.
 GL_AMD_query_buffer_object on i965, nvc0, r600, radeonsi.
 GL_EXT_disjoint_timer_query on radeonsi and most other Gallium drivers (ES 
extension)
+GL_EXT_texture_compression_s3tc on all drivers (ES extension)
 GL_EXT_vertex_attrib_64bit on i965, nvc0, radeonsi.
 GL_EXT_window_rectangles on radeonsi.
 GL_KHR_texture_compression_astc_sliced_3d on radeonsi.
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 09bf923bd0e..47db1583135 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -278,7 +278,7 @@ EXT(EXT_texture_buffer  , 
OES_texture_buffer
 EXT(EXT_texture_compression_dxt1, ANGLE_texture_compression_dxt
  , GLL, GLC, ES1, ES2, 2004)
 EXT(EXT_texture_compression_latc, EXT_texture_compression_latc 
  , GLL,  x ,  x ,  x , 2006)
 EXT(EXT_texture_compression_rgtc, ARB_texture_compression_rgtc 
  , GLL, GLC,  x ,  x , 2004)
-EXT(EXT_texture_compression_s3tc, EXT_texture_compression_s3tc 
  , GLL, GLC,  x ,  x , 2000)
+EXT(EXT_texture_compression_s3tc, EXT_texture_compression_s3tc 
  , GLL, GLC,  x , ES2, 2000)
 EXT(EXT_texture_cube_map, ARB_texture_cube_map 
  , GLL,  x ,  x ,  x , 2001)
 EXT(EXT_texture_cube_map_array  , OES_texture_cube_map_array   
  ,  x ,  x ,  x ,  31, 2014)
 EXT(EXT_texture_edge_clamp  , dummy_true   
  , GLL,  x ,  x ,  x , 1997)
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 6cb3435dea2..f8fc36e9311 100644
--- a/src/mesa/main/glformats.c
+++ b/src/mesa/main/glformats.c
@@ -2803,6 +2803,17 @@ _mesa_es3_error_check_format_and_type(const struct 
gl_context *ctx,
   internalFormat = effectiveInternalFormat;
}
 
+   /* The GLES variant of EXT_texture_compression_s3tc is very vague and
+* doesn't list valid types. Just do exactly what the spec says.
+*/
+   if (ctx->Extensions.EXT_texture_compression_s3tc &&
+   (internalFormat == GL_COMPRESSED_RGB_S3TC_DXT1_EXT ||
+internalFormat == GL_COMPRESSED_RGBA_S3TC_DXT1_EXT ||
+internalFormat == GL_COMPRESSED_RGBA_S3TC_DXT3_EXT ||
+internalFormat == GL_COMPRESSED_RGBA_S3TC_DXT5_EXT))
+  return format == GL_RGB || format == GL_RGBA ? GL_NO_ERROR :
+ GL_INVALID_OPERATION;
+
switch (format) {
case GL_BGRA_EXT:
   if (type != GL_UNSIGNED_BYTE || internalFormat != GL_BGRA)
-- 
2.17.2

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[Mesa-dev] [PATCH] anv: Fix sanitization of stencil state when the depth test is disabled

2018-10-25 Thread Alex Smith

When depth testing is disabled, we shouldn't pay attention to the
specified depthCompareOp, and just treat it as always passing. Before,
if the depth test is disabled, but depthCompareOp is VK_COMPARE_OP_NEVER
(e.g. from the app having zero-initialized the structure), then
sanitize_stencil_face() would have incorrectly changed passOp to
VK_STENCIL_OP_KEEP.

Signed-off-by: Alex Smith 
---
 src/intel/vulkan/genX_pipeline.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 33f1f7832a..877a9fb850 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -755,9 +755,13 @@ sanitize_ds_state(VkPipelineDepthStencilStateCreateInfo 
*state,
 {
*stencilWriteEnable = state->stencilTestEnable;
 
-   /* If the depth test is disabled, we won't be writing anything. */
-   if (!state->depthTestEnable)
+   /* If the depth test is disabled, we won't be writing anything. Make sure
+* we treat it as always passing later on as well.
+*/
+   if (!state->depthTestEnable) {
   state->depthWriteEnable = false;
+  state->depthCompareOp = VK_COMPARE_OP_ALWAYS;
+   }
 
/* The Vulkan spec requires that if either depth or stencil is not present,
 * the pipeline is to act as if the test silently passes.
-- 
2.14.4

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Re: [Mesa-dev] [PATCH v4 1/2] wayland/egl: initialize window surface size to window size

On Thu, Oct 25, 2018 at 12:05 PM Olivier Fourdan  wrote:
>
> Hi,
>
> On Tue, Aug 7, 2018 at 5:50 PM Juan A. Suarez Romero
>  wrote:
> >
> > When creating a windows surface with eglCreateWindowSurface(), the
> > width and height returned by eglQuerySurface(EGL_{WIDTH,HEIGHT}) is
> > invalid until buffers are updated (like calling glClear()).
> >
> > But according to EGL 1.5 spec, section 3.5.6 ("Surface Attributes"):
> >
> >   "Querying EGL_WIDTH and EGL_HEIGHT returns respectively the width and
> >height, in pixels, of the surface. For a window or pixmap surface,
> >these values are initially equal to the width and height of the
> >native window or pixmap with respect to which the surface was
> >created"
> >
> > This fixes dEQP-EGL.functional.color_clears.* CTS tests
> >
> > v2:
> > - Do not modify attached_{width,height} (Daniel)
> > - Do not update size on resizing window (Brendan)
> >
> > CC: Daniel Stone 
> > CC: Brendan King 
> > CC: mesa-sta...@lists.freedesktop.org
> > Tested-by: Eric Engestrom 
> > ---
> >  src/egl/drivers/dri2/platform_wayland.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/src/egl/drivers/dri2/platform_wayland.c 
> > b/src/egl/drivers/dri2/platform_wayland.c
> > index dca099500a8..a5d43094cf3 100644
> > --- a/src/egl/drivers/dri2/platform_wayland.c
> > +++ b/src/egl/drivers/dri2/platform_wayland.c
> > @@ -258,6 +258,9 @@ dri2_wl_create_window_surface(_EGLDriver *drv, 
> > _EGLDisplay *disp,
> >goto cleanup_surf;
> > }
> >
> > +   dri2_surf->base.Width = window->width;
> > +   dri2_surf->base.Height = window->height;
> > +
> > visual_idx = dri2_wl_visual_idx_from_config(dri2_dpy, config);
> > assert(visual_idx != -1);
> >
> > --
> > 2.17.1
>
> Just a quick heads up, this patch is causing a regression with
> "swrast" which does not have DRI2flushExtension.
>
> Easiest way to demonstrate the issue is to use totem with "swrast" on
> mesa-18.2.x (e.g. Fedora 29) under Wayland:
>
>   $ LIBGL_ALWAYS_SOFTWARE=true CLUTTER_BACKEND=gdk totem
>
> Play a video and resize the totem toplevel window, the size of the EGL
> surface remains unchanged...
>
> Reverting that patch fixes the issue, as using a DRI driver which
> supports DRI2flushExtension. Nevertheless, that's a regression.

Sorry, wrong patch, the culprit is:

https://cgit.freedesktop.org/mesa/mesa/commit/src/egl/drivers/dri2/platform_wayland.c?id=a9fb331ea
(or 
https://cgit.freedesktop.org/mesa/mesa/commit/src/egl/drivers/dri2/platform_wayland.c?id=7af6be886
cherry-picked in 18.2)

And actually reverting just that part from the patch:

@@ -1635,8 +1646,8 @@ swrast_update_buffers(struct dri2_egl_surface *dri2_surf)
if (dri2_surf->back)
return 0;
- if (dri2_surf->base.Width != dri2_surf->wl_win->width ||
- dri2_surf->base.Height != dri2_surf->wl_win->height) {
+ if (dri2_surf->base.Width != dri2_surf->wl_win->attached_width ||
+ dri2_surf->base.Height != dri2_surf->wl_win->attached_height) {
dri2_wl_release_buffers(dri2_surf);

Fixes the issue.

Cheers,
Olivier
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[Mesa-dev] [PATCH mesa] vulkan: drop always-true param

Signed-off-by: Eric Engestrom 
---
 src/amd/vulkan/radv_wsi_x11.c   | 2 --
 src/intel/vulkan/anv_wsi_x11.c  | 2 --
 src/vulkan/wsi/wsi_common_x11.c | 5 -
 src/vulkan/wsi/wsi_common_x11.h | 1 -
 4 files changed, 10 deletions(-)

diff --git a/src/amd/vulkan/radv_wsi_x11.c b/src/amd/vulkan/radv_wsi_x11.c
index f3ebc791e2dc8a8fe8d8..acad74d3cf2a4d48d3ce 100644
--- a/src/amd/vulkan/radv_wsi_x11.c
+++ b/src/amd/vulkan/radv_wsi_x11.c
@@ -45,7 +45,6 @@ VkBool32 radv_GetPhysicalDeviceXcbPresentationSupportKHR(
return wsi_get_physical_device_xcb_presentation_support(
   >wsi_device,
   queueFamilyIndex,
-  true,
   connection, visual_id);
 }
 
@@ -60,7 +59,6 @@ VkBool32 radv_GetPhysicalDeviceXlibPresentationSupportKHR(
return wsi_get_physical_device_xcb_presentation_support(
   >wsi_device,
   queueFamilyIndex,
-  true,
   XGetXCBConnection(dpy), visualID);
 }
 
diff --git a/src/intel/vulkan/anv_wsi_x11.c b/src/intel/vulkan/anv_wsi_x11.c
index 7a27ceab64fecbfe199b..9a50b17f99937b48fc93 100644
--- a/src/intel/vulkan/anv_wsi_x11.c
+++ b/src/intel/vulkan/anv_wsi_x11.c
@@ -41,7 +41,6 @@ VkBool32 anv_GetPhysicalDeviceXcbPresentationSupportKHR(
return wsi_get_physical_device_xcb_presentation_support(
   >wsi_device,
   queueFamilyIndex,
-  true,
   connection, visual_id);
 }
 
@@ -56,7 +55,6 @@ VkBool32 anv_GetPhysicalDeviceXlibPresentationSupportKHR(
return wsi_get_physical_device_xcb_presentation_support(
   >wsi_device,
   queueFamilyIndex,
-  true,
   XGetXCBConnection(dpy), visualID);
 }
 
diff --git a/src/vulkan/wsi/wsi_common_x11.c b/src/vulkan/wsi/wsi_common_x11.c
index 6eb72827eda5a6ce67c7..c740726fe54746f8bfc3 100644
--- a/src/vulkan/wsi/wsi_common_x11.c
+++ b/src/vulkan/wsi/wsi_common_x11.c
@@ -375,7 +375,6 @@ visual_has_alpha(xcb_visualtype_t *visual, unsigned depth)
 VkBool32 wsi_get_physical_device_xcb_presentation_support(
 struct wsi_device *wsi_device,
 uint32_tqueueFamilyIndex,
-bool can_handle_different_gpu,
 xcb_connection_t*   connection,
 xcb_visualid_t  visual_id)
 {
@@ -388,10 +387,6 @@ VkBool32 wsi_get_physical_device_xcb_presentation_support(
if (!wsi_x11_check_for_dri3(wsi_conn))
   return false;
 
-   if (!can_handle_different_gpu)
-  if (!wsi_x11_check_dri3_compatible(wsi_device, connection))
- return false;
-
unsigned visual_depth;
if (!connection_get_visualtype(connection, visual_id, _depth))
   return false;
diff --git a/src/vulkan/wsi/wsi_common_x11.h b/src/vulkan/wsi/wsi_common_x11.h
index 99b1bcdc6fd73487b3df..e4b1e94a8c8c9d4bbed6 100644
--- a/src/vulkan/wsi/wsi_common_x11.h
+++ b/src/vulkan/wsi/wsi_common_x11.h
@@ -28,7 +28,6 @@
 VkBool32 wsi_get_physical_device_xcb_presentation_support(
 struct wsi_device *wsi_device,
 uint32_tqueueFamilyIndex,
-bool can_handle_different_gpu,
 xcb_connection_t*   connection,
 xcb_visualid_t  visual_id);
 
-- 
Cheers,
  Eric

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Re: [Mesa-dev] [PATCH v4 1/2] wayland/egl: initialize window surface size to window size

Hi,

On Tue, Aug 7, 2018 at 5:50 PM Juan A. Suarez Romero
 wrote:
>
> When creating a windows surface with eglCreateWindowSurface(), the
> width and height returned by eglQuerySurface(EGL_{WIDTH,HEIGHT}) is
> invalid until buffers are updated (like calling glClear()).
>
> But according to EGL 1.5 spec, section 3.5.6 ("Surface Attributes"):
>
>   "Querying EGL_WIDTH and EGL_HEIGHT returns respectively the width and
>height, in pixels, of the surface. For a window or pixmap surface,
>these values are initially equal to the width and height of the
>native window or pixmap with respect to which the surface was
>created"
>
> This fixes dEQP-EGL.functional.color_clears.* CTS tests
>
> v2:
> - Do not modify attached_{width,height} (Daniel)
> - Do not update size on resizing window (Brendan)
>
> CC: Daniel Stone 
> CC: Brendan King 
> CC: mesa-sta...@lists.freedesktop.org
> Tested-by: Eric Engestrom 
> ---
>  src/egl/drivers/dri2/platform_wayland.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/egl/drivers/dri2/platform_wayland.c 
> b/src/egl/drivers/dri2/platform_wayland.c
> index dca099500a8..a5d43094cf3 100644
> --- a/src/egl/drivers/dri2/platform_wayland.c
> +++ b/src/egl/drivers/dri2/platform_wayland.c
> @@ -258,6 +258,9 @@ dri2_wl_create_window_surface(_EGLDriver *drv, 
> _EGLDisplay *disp,
>goto cleanup_surf;
> }
>
> +   dri2_surf->base.Width = window->width;
> +   dri2_surf->base.Height = window->height;
> +
> visual_idx = dri2_wl_visual_idx_from_config(dri2_dpy, config);
> assert(visual_idx != -1);
>
> --
> 2.17.1

Just a quick heads up, this patch is causing a regression with
"swrast" which does not have DRI2flushExtension.

Easiest way to demonstrate the issue is to use totem with "swrast" on
mesa-18.2.x (e.g. Fedora 29) under Wayland:

  $ LIBGL_ALWAYS_SOFTWARE=true CLUTTER_BACKEND=gdk totem

Play a video and resize the totem toplevel window, the size of the EGL
surface remains unchanged...

Reverting that patch fixes the issue, as using a DRI driver which
supports DRI2flushExtension. Nevertheless, that's a regression.

Cheers,
Olivier
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Re: [Mesa-dev] [RFC] freedreno: import libdrm_freedreno + redesign submit

On Tuesday, 2018-10-23 10:49:26 -0400, mesa-dev-boun...@lists.freedesktop.org 
wrote:
> In the pursuit of lowering driver overhead, it became clear that some
> amount of redesign of how libdrm_freedreno constructs the submit ioctl
> would be needed.  In particular, as the gallium driver is starting to
> make heavier use of CP_SET_DRAW_STATE state groups/objects, the over-
> head of tracking cmd buffers and relocs becomes too much.  And for
> "streaming" state, which isn't ever reused (like uniform uploads) the
> overhead of allocating/freeing ringbuffer[1] objects is too high.
> 
> This redesign makes two main changes:
> 
>  1) Introduces a fd_submit object for tracking bos and cmds table
> for the submit ioctl, making ringbuffer objects more light-
> weight.  This was previously done in the ringbuffer.  But we
> have many ringbuffer instances involved in a submit (gmem +
> draw + potentially 1000's of state-group rbs), and only need
> a single bos and cmds table.  (Reloc table is still per-rb)
> 
> The submit is also a convenient place for a slab allocator for
> ringbuffer objects.  Other options would have required locking
> because, while we can guarantee allocations will only happen on
> a single thread, free's could happen either on the application
> thread or the flush_queue thread.  With the slab allocator in
> the submit object, any frees that happen on the flush_queue
> thread happen after we know that the application thread is done
> with the submit.
> 
>  2) Introduce a new "softpin" msm_ringbuffer_sp implementation that
> does not use relocs and only has cmds table entries for IB1 (ie.
> the cmdstream buffers that kernel needs to CP_INDIRECT_BUFFER
> to from the RB).  To do this properly will require some updates
> on the kernel side, so whether you get the softpin or legacy
> submit/ringbuffer implementation at runtime depends on your
> kernel version.
> 
> To make all these changes in libdrm would basically require adding a
> libdrm_freedreno2, so this is a good point to just pull the libdrm code
> into mesa.  Plus it allows for using mesa's hashtable, slab allocator,
> etc.  And it lets us have asserts enabled for debug mesa buids but
> omitted for release builds.  And it makes life easier if further API
> changes become necessary.
> 
> At this point I haven't tried to pull in the kgsl backend.  Although
> I left the level of vfunc indirection which would make it possible
> to have other backends.  (And this was convenient to keep to allow
> for the "softpin" ringbuffer to coexist.)
> 
> NOTE: if bisecting a build error takes you hear, try a clean build.
> There are a bunch of ways things can go wrong if you still have
> libdrm_freedreno cflags.

Good note!
(and s/hear/here/)

> 
> [1] "ringbuffer" is probably a bad name, the only level of cmdstream
> buffer that is actually a ring is RB managed by kernel.  User-
> space cmdstream is all IB1/IB2 and state-groups.
> 
> Signed-off-by: Rob Clark 
> ---
> Note one "benchmark" that I was at while working on this is webgl
> aquarium.  It isn't a terribly clever gl app, doing one draw per
> fish, uploading uniforms (and usually not making any other state
> changes) between each draw.  The "softpin" implementation drops
> CPU utilization by about 20%, and once you get CPU limited, it is
> worth ~50% fps boost.
> 
> Also note, android build probably needs some attention (mostly
> replacing libdrm_freedreno dependency with libdrm + valgrind).

Might be best to do that in the same commit, to avoid breaking bisects.

> 
>  configure.ac  |   2 -
>  meson.build   |   2 -
>  src/gallium/drivers/freedreno/Makefile.am |   7 +-
>  .../drivers/freedreno/Makefile.sources|  17 +
>  .../drivers/freedreno/a3xx/fd3_context.h  |   2 -
>  .../drivers/freedreno/a4xx/fd4_context.h  |   2 -
>  .../drivers/freedreno/a5xx/fd5_context.h  |   2 -
>  src/gallium/drivers/freedreno/a5xx/fd5_draw.c |   3 +-
>  .../drivers/freedreno/a6xx/fd6_context.h  |   2 -
>  src/gallium/drivers/freedreno/a6xx/fd6_draw.c |   3 +-
>  src/gallium/drivers/freedreno/a6xx/fd6_emit.c |  26 +-
>  .../drivers/freedreno/drm/freedreno_bo.c  | 361 +
>  .../freedreno/drm/freedreno_bo_cache.c| 218 ++
>  .../drivers/freedreno/drm/freedreno_device.c  | 156 
>  .../drivers/freedreno/drm/freedreno_drmif.h   | 126 +++
>  .../drivers/freedreno/drm/freedreno_pipe.c| 100 +++
>  .../drivers/freedreno/drm/freedreno_priv.h| 258 +++
>  .../freedreno/drm/freedreno_ringbuffer.c  | 114 +++
>  .../freedreno/drm/freedreno_ringbuffer.h  | 159 
>  src/gallium/drivers/freedreno/drm/msm_bo.c| 170 +
>  .../drivers/freedreno/drm/msm_device.c|  61 ++
>  src/gallium/drivers/freedreno/drm/msm_drm.h   | 308 
>  src/gallium/drivers/freedreno/drm/msm_pipe.c  | 223 ++
>

[Mesa-dev] [PATCH 2/2] st/nir: Drop unused parameter from st_nir_assign_uniform_locations().

2018-10-25 Thread Kenneth Graunke

ARB programs won't have one of these, and we don't use it anyway.
---
 src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index c15bd7e511b..dcde95cd609 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -240,7 +240,6 @@ st_nir_lookup_parameter_index(const struct 
gl_program_parameter_list *params,
 static void
 st_nir_assign_uniform_locations(struct gl_context *ctx,
 struct gl_program *prog,
-struct gl_shader_program *shader_program,
 struct exec_list *uniform_list, unsigned *size)
 {
int max = 0;
@@ -849,7 +848,7 @@ st_finalize_nir(struct st_context *st, struct gl_program 
*prog,
NIR_PASS_V(nir, nir_lower_atomics_to_ssbo,
  st->ctx->Const.Program[nir->info.stage].MaxAtomicBuffers);
 
-   st_nir_assign_uniform_locations(st->ctx, prog, shader_program,
+   st_nir_assign_uniform_locations(st->ctx, prog,
>uniforms, >num_uniforms);
 
if (st->ctx->Const.PackedDriverUniformStorage) {
-- 
2.19.0

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[Mesa-dev] [PATCH 1/2] st/mesa: Pull nir_lower_wpos_ytransform work into a helper function.

2018-10-25 Thread Kenneth Graunke

This will let me use it in the ARB program code as well.
---
 src/mesa/state_tracker/st_glsl_to_nir.cpp | 66 +--
 src/mesa/state_tracker/st_nir.h   |  4 ++
 2 files changed, 41 insertions(+), 29 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 911284401e0..c15bd7e511b 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -619,6 +619,41 @@ st_nir_link_shaders(nir_shader **producer, nir_shader 
**consumer, bool scalar)
 
 extern "C" {
 
+void
+st_nir_lower_wpos_ytransform(struct nir_shader *nir,
+ struct gl_program *prog,
+ struct pipe_screen *pscreen)
+{
+   if (nir->info.stage != MESA_SHADER_FRAGMENT)
+  return;
+
+   static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
+  STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
+   };
+   nir_lower_wpos_ytransform_options wpos_options = { { 0 } };
+
+   memcpy(wpos_options.state_tokens, wposTransformState,
+  sizeof(wpos_options.state_tokens));
+   wpos_options.fs_coord_origin_upper_left =
+  pscreen->get_param(pscreen,
+ PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT);
+   wpos_options.fs_coord_origin_lower_left =
+  pscreen->get_param(pscreen,
+ PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
+   wpos_options.fs_coord_pixel_center_integer =
+  pscreen->get_param(pscreen,
+ PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
+   wpos_options.fs_coord_pixel_center_half_integer =
+  pscreen->get_param(pscreen,
+ PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER);
+
+   if (nir_lower_wpos_ytransform(nir, _options)) {
+  nir_validate_shader(nir);
+  _mesa_add_state_reference(prog->Parameters,
+wposTransformState);
+   }
+}
+
 bool
 st_link_nir(struct gl_context *ctx,
 struct gl_shader_program *shader_program)
@@ -697,35 +732,8 @@ st_link_nir(struct gl_context *ctx,
 
   nir_shader *nir = shader->Program->nir;
 
-  /* fragment shaders may need : */
-  if (nir->info.stage == MESA_SHADER_FRAGMENT) {
- static const gl_state_index16 wposTransformState[STATE_LENGTH] = {
-STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
- };
- nir_lower_wpos_ytransform_options wpos_options = { { 0 } };
- struct pipe_screen *pscreen = st->pipe->screen;
-
- memcpy(wpos_options.state_tokens, wposTransformState,
-sizeof(wpos_options.state_tokens));
- wpos_options.fs_coord_origin_upper_left =
-pscreen->get_param(pscreen,
-   PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT);
- wpos_options.fs_coord_origin_lower_left =
-pscreen->get_param(pscreen,
-   PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT);
- wpos_options.fs_coord_pixel_center_integer =
-pscreen->get_param(pscreen,
-   PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
- wpos_options.fs_coord_pixel_center_half_integer =
-pscreen->get_param(pscreen,
-   
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER);
-
- if (nir_lower_wpos_ytransform(nir, _options)) {
-nir_validate_shader(nir);
-_mesa_add_state_reference(shader->Program->Parameters,
-  wposTransformState);
- }
-  }
+  NIR_PASS_V(nir, st_nir_lower_wpos_ytransform, shader->Program,
+ st->pipe->screen);
 
   NIR_PASS_V(nir, nir_lower_system_values);
 
diff --git a/src/mesa/state_tracker/st_nir.h b/src/mesa/state_tracker/st_nir.h
index aa6e32758e8..10f23c03ef6 100644
--- a/src/mesa/state_tracker/st_nir.h
+++ b/src/mesa/state_tracker/st_nir.h
@@ -38,6 +38,10 @@ void st_nir_lower_tex_src_plane(struct nir_shader *shader, 
unsigned free_slots,
 unsigned lower_2plane, unsigned lower_3plane);
 bool st_nir_lower_uniforms_to_ubo(struct nir_shader *shader);
 
+void st_nir_lower_wpos_ytransform(struct nir_shader *nir,
+  struct gl_program *prog,
+  struct pipe_screen *pscreen);
+
 void st_finalize_nir(struct st_context *st, struct gl_program *prog,
  struct gl_shader_program *shader_program,
  struct nir_shader *nir);
-- 
2.19.0

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[Mesa-dev] [PATCH] st/mesa: Don't record garbage streamout information in the non-SSO case.

2018-10-25 Thread Kenneth Graunke

In the non-SSO case, where multiple shader stages are linked together,
we were recording garbage pipe_stream_output_info structures for all
but the last enabled geometry-processing stage.

Specifically, we were using the gl_transform_feedback_info from
shader_program->last_vert_prog (the stage whose outputs will be
recorded)...but were pairing it with the output varying mappings
from the current shader stage.  For example, a program with a VS and
GS, the VS's pipe_shader_state would have a pipe_stream_output_info
based on the GS transform feedback info, but the VS output mapping.

This generally worked out okay because only the pipe_stream_output_info
for the last stage really matters - the others can be ignored.  However,
we'd like to avoid confusing the pipe driver.  In particular, my new
driver translates the stream out information to hardware packets at
bind_{vs,tes,gs}_state() time...and was hitting asserts about garbage
varyings that didn't exist.

This patch changes st/mesa to record a blank pipe_stream_output_info
with num_outputs = 0 for all stages prior to last_vert_prog.  The last
one is captured as normal.

(In the fully-SSO case, nothing should change - each program contains
a single shader stage, so last_vert_prog *is* the current shader.)

Tested with llvmpipe (piglit's gpu profile), and freedreno (a3xx,
gpu profile with -t transform.feedback).  Fixes several hundred CTS
tests on my new driver.
---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 20 ++--
 src/mesa/state_tracker/st_glsl_to_tgsi.h   |  7 +--
 src/mesa/state_tracker/st_program.c| 19 ---
 3 files changed, 15 insertions(+), 31 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index dea91c7a189..19bd46d6097 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -7467,25 +7467,17 @@ st_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
 }
 
 void
-st_translate_stream_output_info(glsl_to_tgsi_visitor *glsl_to_tgsi,
-const ubyte outputMapping[],
-struct pipe_stream_output_info *so)
-{
-   if (!glsl_to_tgsi->shader_program->last_vert_prog)
-  return;
-
-   struct gl_transform_feedback_info *info =
-  glsl_to_tgsi->shader_program->last_vert_prog->sh.LinkedTransformFeedback;
-   st_translate_stream_output_info2(info, outputMapping, so);
-}
-
-void
-st_translate_stream_output_info2(struct gl_transform_feedback_info *info,
+st_translate_stream_output_info(struct gl_transform_feedback_info *info,
 const ubyte outputMapping[],
 struct pipe_stream_output_info *so)
 {
unsigned i;
 
+   if (!info) {
+  so->num_outputs = 0;
+  return;
+   }
+
for (i = 0; i < info->NumOutputs; i++) {
   so->output[i].register_index =
  outputMapping[info->Outputs[i].OutputRegister];
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.h 
b/src/mesa/state_tracker/st_glsl_to_tgsi.h
index 8ccfff9bd37..fa6c0e02712 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.h
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.h
@@ -58,12 +58,7 @@ void free_glsl_to_tgsi_visitor(struct glsl_to_tgsi_visitor 
*v);
 GLboolean st_link_shader(struct gl_context *ctx, struct gl_shader_program 
*prog);
 
 void
-st_translate_stream_output_info(struct glsl_to_tgsi_visitor *glsl_to_tgsi,
-const ubyte outputMapping[],
-struct pipe_stream_output_info *so);
-
-void
-st_translate_stream_output_info2(struct gl_transform_feedback_info *info,
+st_translate_stream_output_info(struct gl_transform_feedback_info *info,
 const ubyte outputMapping[],
 struct pipe_stream_output_info *so);
 
diff --git a/src/mesa/state_tracker/st_program.c 
b/src/mesa/state_tracker/st_program.c
index af86c47b945..3bc7b0649c4 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -458,12 +458,9 @@ st_translate_vertex_program(struct st_context *st,
}
 
if (stvp->shader_program) {
-  struct gl_program *prog = stvp->shader_program->last_vert_prog;
-  if (prog) {
- st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
-  stvp->result_to_output,
-  >tgsi.stream_output);
-  }
+  st_translate_stream_output_info(stvp->Base.sh.LinkedTransformFeedback,
+  stvp->result_to_output,
+  >tgsi.stream_output);
 
   st_store_ir_in_disk_cache(st, >Base, true);
   return true;
@@ -505,7 +502,7 @@ st_translate_vertex_program(struct st_context *st,
output_semantic_name,

[Mesa-dev] [PATCH 2/2] freedreno: take reg->num out of union in ir3_register

2018-10-25 Thread Hyunjun Ko

To avoid wrong result when identifying the type of register.
Ie. If the reg is an array, it might be identified as address or
predicate register.
---
 src/gallium/drivers/freedreno/ir3/ir3.h | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h 
b/src/gallium/drivers/freedreno/ir3/ir3.h
index 3055c10f1d..1f47cef7e0 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3.h
@@ -95,12 +95,13 @@ struct ir3_register {
IR3_REG_ARRAY  = 0x8000,
 
} flags;
+
+   /* normal registers:
+* the component is in the low two bits of the reg #, so
+* rN.x becomes: (N << 2) | x
+*/
+   int   num;
union {
-   /* normal registers:
-* the component is in the low two bits of the reg #, so
-* rN.x becomes: (N << 2) | x
-*/
-   int   num;
/* immediate: */
int32_t  iim_val;
uint32_t uim_val;
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] intel/compiler: Print message descriptor as immediate source

2018-10-25 Thread Samuel Iglesias Gonsálvez

On Thursday, 25 October 2018 1:25:53 (CEST) Sagar Ghuge wrote:
> While disassembling send(c) instruction print message descriptor as
> immediate source operand along with message descriptor. This allows
> assembler to read immediate source operand and set bits accordingly.
> 
> Signed-off-by: Sagar Ghuge 
> ---
>  src/intel/compiler/brw_disasm.c | 9 +++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/src/intel/compiler/brw_disasm.c
> b/src/intel/compiler/brw_disasm.c index 6a7e988641..9c6df9e645 100644
> --- a/src/intel/compiler/brw_disasm.c
> +++ b/src/intel/compiler/brw_disasm.c
> @@ -1606,7 +1606,12 @@ brw_disassemble_inst(FILE *file, const struct
> gen_device_info *devinfo, /* show the indirect descriptor source */
>   pad(file, 48);
>   err |= src1(file, devinfo, inst);
> -  }
> + pad(file, 64);
> +  } else
> + pad(file, 48);
> +

IIRC, we have a coding style rules that is: when the if's body has several 
statements like here, then the else body should be between braces even when it 
is one line. That thing increases readability.

I have not found it written in the coding style guidelines [0], but I have 
seen it in a lot of places of the code.

I can do this change for you before pushing it tomorrow. Sounds good?

With that fixed,

Reviewed-by: Samuel Iglesias Gonsálvez 

Sam

[0] https://www.mesa3d.org/codingstyle.html

> +  /* Print message descriptor as immediate source */
> +  fprintf(file, "0x%08"PRIx64, inst->data[1] >> 32);
> 
>newline(file);
>pad(file, 16);
> @@ -1615,7 +1620,7 @@ brw_disassemble_inst(FILE *file, const struct
> gen_device_info *devinfo, fprintf(file, "");
>err |= control(file, "SFID", devinfo->gen >= 6 ? gen6_sfid :
> gen4_sfid, sfid, );
> -
> +  string(file, " MsgDesc:");
> 
>if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
>   format(file, " indirect");



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Re: [Mesa-dev] [PATCH] intel/compiler: Print hex representation along with floating point value

2018-10-25 Thread Samuel Iglesias Gonsálvez

Reviewed-by: Samuel Iglesias Gonsálvez 

Do you need somebody to push it to the repo? I can do it tomorrow.

Sam

On Wednesday, 24 October 2018 22:27:27 (CEST) Sagar Ghuge wrote:
> While encoding the immediate floating point values in instruction we use
> values upto precision 9, but while disassembling, we print precision to
> 6 places, which round up the value and gives wrong interpretation for
> encoded immediate constant.
> 
> To avoid misinterpretation of encoded immediate values in instruction
> and disassembled output, print hex representation along with floating
> point value which can be used by assembler in future.
> 
> Signed-off-by: Sagar Ghuge 
> ---
>  src/intel/compiler/brw_disasm.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/src/intel/compiler/brw_disasm.c
> b/src/intel/compiler/brw_disasm.c index 322f4544df..6a7e988641 100644
> --- a/src/intel/compiler/brw_disasm.c
> +++ b/src/intel/compiler/brw_disasm.c
> @@ -1283,7 +1283,9 @@ imm(FILE *file, const struct gen_device_info *devinfo,
> enum brw_reg_type type, format(file, "0x%08xUV", brw_inst_imm_ud(devinfo,
> inst));
>break;
> case BRW_REGISTER_TYPE_VF:
> -  format(file, "[%-gF, %-gF, %-gF, %-gF]VF",
> +  format(file, "0x%"PRIx64"VF", brw_inst_bits(inst, 127, 96));
> +  pad(file, 48);
> +  format(file, "/* [%-gF, %-gF, %-gF, %-gF]VF */",
>   brw_vf_to_float(brw_inst_imm_ud(devinfo, inst)),
>   brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 8),
>   brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16),
> @@ -1293,10 +1295,14 @@ imm(FILE *file, const struct gen_device_info
> *devinfo, enum brw_reg_type type, format(file, "0x%08xV",
> brw_inst_imm_ud(devinfo, inst));
>break;
> case BRW_REGISTER_TYPE_F:
> -  format(file, "%-gF", brw_inst_imm_f(devinfo, inst));
> +  format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96));
> +  pad(file, 48);
> +  format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst));
>break;
> case BRW_REGISTER_TYPE_DF:
> -  format(file, "%-gDF", brw_inst_imm_df(devinfo, inst));
> +  format(file, "0x%016"PRIx64"DF", brw_inst_bits(inst, 127, 64));
> +  pad(file, 48);
> +  format(file, "/* %-gDF */", brw_inst_imm_df(devinfo, inst));
>break;
> case BRW_REGISTER_TYPE_HF:
>string(file, "Half Float IMM");


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Re: [Mesa-dev] 18.3 release plan

2018-10-25 Thread Juan A. Suarez Romero

On Tue, 2018-10-23 at 09:19 -0700, Dylan Baker wrote:
> Hi List,
> 
> It's that time again, release time! We're a little late getting started, but
> here's the plan:
> 
> Branch point/RC1: 10/31
> RC2: 11/7
> RC3: 11/14
> RC4/final release: 11/21
> 
> With point releases following the normal two week period, this would also
> require adding two additional 18.2 releases:
> 
> 18.2.6: 11/21
> 18.2.7: 12/05
> 
> I have gone ahead and created the 18.3 tracker bug, so please start adding any
> block bugs to that issue. I'll be sending out a patch to update the calendar
> accordingly shortly.

For reference, the tracking issue is 
https://bugs.freedesktop.org/show_bug.cgi?id=108530


J.A.

> 
> You may note that this means you now have 8 days until the branch point to get
> last minute fixes into 18.3. I'd really like to do the branch point/RC1 on the
> 31st, as this will allow the stable releases to nicely leapfrog the US
> thanksgiving holiday and the Christmas holiday weeks.
> 
> Dylan
> ___
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> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev

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[Mesa-dev] [Bug 107455] [TRACKER] Mesa 18.3 feature tracker

https://bugs.freedesktop.org/show_bug.cgi?id=107455

Juan A. Suarez  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from Juan A. Suarez  ---
Superseded by bug #108530

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Re: [Mesa-dev] [PATCH] docs/calendar: Add 18.3 plan and expand 18.2

2018-10-25 Thread Juan A. Suarez Romero

On Wed, 2018-10-24 at 18:32 +0100, Emil Velikov wrote:
> From: Dylan Baker 
> 
> Emil will be helping out with 18.3, while Juan finalises 18.2
> 
> v2: add Emil for 18.3, fix typos


Reviewed-by: Juan A. Suarez 

J.A.

> 
> CC: Emil Velikov 
> CC: Juan A. Romero Suarez 
> Cc: Dylan Baker 
> ---
>  docs/release-calendar.html | 38 +-
>  1 file changed, 37 insertions(+), 1 deletion(-)
> 
> diff --git a/docs/release-calendar.html b/docs/release-calendar.html
> index 566b11623b7..1e071a97947 100644
> --- a/docs/release-calendar.html
> +++ b/docs/release-calendar.html
> @@ -39,7 +39,7 @@ if you'd like to nominate a patch in the next stable 
> release.
>  Notes
>  
>  
> -18.2
> +18.2
>  2018-10-31
>  18.2.4
>  Juan A. Suarez
> @@ -49,8 +49,44 @@ if you'd like to nominate a patch in the next stable 
> release.
>  2018-11-14
>  18.2.5
>  Juan A. Suarez
> +
> +
> +
> +2018-11-28
> +18.2.6
> +Juan A. Suarez
> +
> +
> +
> +2018-12-12
> +18.2.7
> +Juan A. Suarez
>  Last planned 18.2.x release
>  
> +18.3
> +2018-10-31
> +18.3.0-rc1
> +Emil Velikov
> +
> +
> +
> +2018-11-07
> +18.3.0-rc2
> +Emil Velikov
> +
> +
> +
> +2018-11-14
> +18.3.0-rc3
> +Emil Velikov
> +
> +
> +
> +2018-11-21
> +18.3.0-rc4
> +Emil Velikov
> +Last planned RC/final release
> +
>  
>  
>  

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Re: [Mesa-dev] [PATCH 2/2] freedreno: ir3: fix wrong return if reg is an array

2018-10-25 Thread Hyunjun Ko



On 10/24/18 11:05 PM, Rob Clark wrote:

On Tue, Oct 23, 2018 at 9:57 PM Hyunjun Ko  wrote:

Since ir3_register struct has union, it could return true even
if it's an array register accidentally when checking whether it
is address/predicate register.

Fixes: dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6
---
  src/gallium/drivers/freedreno/ir3/ir3.h | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h 
b/src/gallium/drivers/freedreno/ir3/ir3.h
index 3055c10f1d..db94603558 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3.h
@@ -739,7 +739,7 @@ static inline bool writes_addr(struct ir3_instruction 
*instr)
  {
 if (instr->regs_count > 0) {
 struct ir3_register *dst = instr->regs[0];
-   return reg_num(dst) == REG_A0;
+   return (reg_num(dst) == REG_A0) && !(dst->flags & 
IR3_REG_ARRAY);

hmm, good catch.. although I wonder if writes_gpr() in ir3_ra.c has
the same issue.  Or anywhere else?  (Otoh, I guess checking for CONST
and IMMED in writes_gpr() is a bit silly)

 From a quick look at the IR3_REG_* flags, I think IR3_REG_ARRAY is the
only problematic case.. but this is a bit more fragile than it should
be.  Maybe we should just move 'int num' out of the union?  Maybe that
was too much premature optimization?

BR,
-R


Didn't figure out writes_gpr() might have same issue.
I think taking num out of union should avoid other similar issues if we 
don't think

that would increase memory footprint that much.

Working on this.





 }
 return false;
  }
@@ -748,7 +748,7 @@ static inline bool writes_pred(struct ir3_instruction 
*instr)
  {
 if (instr->regs_count > 0) {
 struct ir3_register *dst = instr->regs[0];
-   return reg_num(dst) == REG_P0;
+   return (reg_num(dst) == REG_P0) && !(dst->flags & 
IR3_REG_ARRAY);
 }
 return false;
  }
--
2.17.1


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Re: [Mesa-dev] [PATCH mesa] util: remove unnecessary random whitespaces