Re: [Mesa-dev] How to build mesa to run vulkan application on Intel HD graphics?

2019-07-23 Thread Xu, Xing 
This works! Thanks dave!

Regards,
Xing

-Original Message-
From: Dave Airlie [mailto:airl...@gmail.com] 
Sent: Wednesday, July 24, 2019 10:53 AM
To: Xu, Xing 
Cc: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] How to build mesa to run vulkan application on Intel HD 
graphics?

On Wed, 24 Jul 2019 at 11:55, Xu, Xing  wrote:
>
> Hi, I tried to add some logs as below in file 
> ./src/vulkan/wsi/wsi_common_x11.c (x11_queue_present):
>
> printf("%s,%d\n",__FUNCTION__,__LINE__);
>
> assert(0);
>
> but got nothing(no logs and assert didn’t happen) when I run my application.
>
>
>
> Here is how I build run my applications:
>
> 1), Build install
>
> meson configure builddir -Dvulkan-drivers=intel
>
> ninja -C builddir/
>
> meson configure builddir -Dprefix=/tmp/install
>
> sudo ninja -C builddir/ install
>
>
>
> 2), Run
>
> export 
> LD_LIBRARY_PATH=/tmp/install/lib/x86_64-linux-gnu/:$LD_LIBRARY_PATH
>
> export LIBGL_DRIVERS_PATH=/tmp/install/lib/x86_64-linux-gnu/dri
>
> ./angle_end2end_tests

For vulkan you have to set VK_ICD_FILENAMES and point at the 
/tmp/install/share/vulkan/icd.d/intel_icd.x86_64.json

use vulkaninfo to debug.
Dave.
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Re: [Mesa-dev] How to build mesa to run vulkan application on Intel HD graphics?

2019-07-23 Thread Dave Airlie 
On Wed, 24 Jul 2019 at 11:55, Xu, Xing  wrote:
>
> Hi, I tried to add some logs as below in file 
> ./src/vulkan/wsi/wsi_common_x11.c (x11_queue_present):
>
> printf("%s,%d\n",__FUNCTION__,__LINE__);
>
> assert(0);
>
> but got nothing(no logs and assert didn’t happen) when I run my application.
>
>
>
> Here is how I build run my applications:
>
> 1), Build install
>
> meson configure builddir -Dvulkan-drivers=intel
>
> ninja -C builddir/
>
> meson configure builddir -Dprefix=/tmp/install
>
> sudo ninja -C builddir/ install
>
>
>
> 2), Run
>
> export LD_LIBRARY_PATH=/tmp/install/lib/x86_64-linux-gnu/:$LD_LIBRARY_PATH
>
> export LIBGL_DRIVERS_PATH=/tmp/install/lib/x86_64-linux-gnu/dri
>
> ./angle_end2end_tests

For vulkan you have to set VK_ICD_FILENAMES and point at the
/tmp/install/share/vulkan/icd.d/intel_icd.x86_64.json

use vulkaninfo to debug.
Dave.
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[Mesa-dev] How to build mesa to run vulkan application on Intel HD graphics?

2019-07-23 Thread Xu, Xing 
Hi, I tried to add some logs as below in file ./src/vulkan/wsi/wsi_common_x11.c 
(x11_queue_present):

printf("%s,%d\n",__FUNCTION__,__LINE__);

assert(0);

but got nothing(no logs and assert didn't happen) when I run my application.



Here is how I build run my applications:

1), Build install

meson configure builddir -Dvulkan-drivers=intel

ninja -C builddir/

meson configure builddir -Dprefix=/tmp/install

sudo ninja -C builddir/ install



2), Run

export LD_LIBRARY_PATH=/tmp/install/lib/x86_64-linux-gnu/:$LD_LIBRARY_PATH

export LIBGL_DRIVERS_PATH=/tmp/install/lib/x86_64-linux-gnu/dri

./angle_end2end_tests





Do you have any hints how to see the add logs or make the assert happen?









Also I notice' d that there are soft links between libvulkan.so under /usr/lib:

ls -l /usr/lib/x86_64-linux-gnu/libvulkan*

/usr/lib/x86_64-linux-gnu/libvulkan_intel.so

/usr/lib/x86_64-linux-gnu/libvulkan_radeon.so

/usr/lib/x86_64-linux-gnu/libvulkan.so -> libvulkan.so.1

/usr/lib/x86_64-linux-gnu/libvulkan.so.1 -> libvulkan.so.1.1.70

/usr/lib/x86_64-linux-gnu/libvulkan.so.1.1.70



but no libvulkan.so under /tmp/install. Here are the detail structure for 
/tmp/install:

ls /tmp/install/lib/x86_64-linux-gnu/ -l

dri

libEGL.so -> libEGL.so.1

libEGL.so.1 -> libEGL.so.1.0.0

libEGL.so.1.0.0

libgbm.so -> libgbm.so.1

libgbm.so.1 -> libgbm.so.1.0.0

libgbm.so.1.0.0

libglapi.so -> libglapi.so.0

libglapi.so.0 -> libglapi.so.0.0.0

libglapi.so.0.0.0

libGLESv1_CM.so -> libGLESv1_CM.so.1

libGLESv1_CM.so.1 -> libGLESv1_CM.so.1.1.0

libGLESv1_CM.so.1.1.0

libGLESv2.so -> libGLESv2.so.2

libGLESv2.so.2 -> libGLESv2.so.2.0.0

libGLESv2.so.2.0.0

libGL.so -> libGL.so.1

libGL.so.1 -> libGL.so.1.2.0

libGL.so.1.2.0

libvulkan_intel.so

libxatracker.so -> libxatracker.so.2

libxatracker.so.2 -> libxatracker.so.2.5.0

libxatracker.so.2.5.0

pkgconfig

vdpau

Regards,
Xing

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[Mesa-dev] [PATCH] intel/ir: Fix CFG corruption in opt_predicated_break().

2019-07-23 Thread Francisco Jerez 
Specifically the optimization of a conditional BREAK + WHILE sequence
into a conditional WHILE seems pretty broken.  The list of successors
of "earlier_block" (where the conditional BREAK was found) is emptied
and then re-created with the same edges for no apparent reason.  On
top of that the list of predecessors of the block immediately after
the WHILE loop is emptied, but only one of the original edges will be
added back, which means that potentially several blocks that still
have it on their list of successors won't be on its list of
predecessors anymore, causing all sorts of hilarity due to the
inconsistency in the control flow graph.

The solution is to remove the code that's removing valid edges from
the CFG.  cfg_t::remove_block() will already clean up after itself.
The assert in bblock_t::combine_with() also needs to be removed since
we will be merging a block with multiple children into the first one
of them.

Found the issue on a hardware enabling branch originally, but
apparently somebody reproduced the same problem independently on
master in the meantime.

Fixes: d13bcdb3a9f ("i965/fs: Extend predicated break pass to predicate WHILE.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111009
Cc: jiradet...@gmail.com
Cc: Sergii Romantsov 
Cc: Matt Turner 
Cc: mesa-sta...@lists.freedesktop.org
---
 src/intel/compiler/brw_cfg.cpp  | 3 ---
 src/intel/compiler/brw_predicated_break.cpp | 6 --
 2 files changed, 9 deletions(-)

diff --git a/src/intel/compiler/brw_cfg.cpp b/src/intel/compiler/brw_cfg.cpp
index 600b428a492..6c40889088d 100644
--- a/src/intel/compiler/brw_cfg.cpp
+++ b/src/intel/compiler/brw_cfg.cpp
@@ -128,9 +128,6 @@ void
 bblock_t::combine_with(bblock_t *that)
 {
assert(this->can_combine_with(that));
-   foreach_list_typed (bblock_link, link, link, >children) {
-  assert(link->block == that);
-   }
foreach_list_typed (bblock_link, link, link, >parents) {
   assert(link->block == this);
}
diff --git a/src/intel/compiler/brw_predicated_break.cpp 
b/src/intel/compiler/brw_predicated_break.cpp
index 607715dace4..e60052f3608 100644
--- a/src/intel/compiler/brw_predicated_break.cpp
+++ b/src/intel/compiler/brw_predicated_break.cpp
@@ -128,14 +128,8 @@ opt_predicated_break(backend_shader *s)
  while_inst->predicate = jump_inst->predicate;
  while_inst->predicate_inverse = !jump_inst->predicate_inverse;
 
- earlier_block->children.make_empty();
- earlier_block->add_successor(s->cfg->mem_ctx, while_block);
-
  assert(earlier_block->can_combine_with(while_block));
  earlier_block->combine_with(while_block);
-
- earlier_block->next()->parents.make_empty();
- earlier_block->add_successor(s->cfg->mem_ctx, earlier_block->next());
   }
 
   progress = true;
-- 
2.22.0

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[Mesa-dev] [PATCH 2/4] panfrost: Use nir_gather_info information about discards

2019-07-23 Thread Alyssa Rosenzweig 
No need to track this ourselves!

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_assemble.c | 2 +-
 src/panfrost/midgard/compiler.h | 3 ---
 src/panfrost/midgard/midgard_compile.c  | 4 
 src/panfrost/midgard/midgard_compile.h  | 1 -
 4 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_assemble.c 
b/src/gallium/drivers/panfrost/pan_assemble.c
index 334ea83305a..75158089c88 100644
--- a/src/gallium/drivers/panfrost/pan_assemble.c
+++ b/src/gallium/drivers/panfrost/pan_assemble.c
@@ -91,7 +91,7 @@ panfrost_shader_compile(struct panfrost_context *ctx, struct 
mali_shader_meta *m
 meta->varying_count = program.varying_count;
 meta->midgard1.work_count = program.work_register_count;
 
-state->can_discard = program.can_discard;
+state->can_discard = s->info.fs.uses_discard;
 state->writes_point_size = program.writes_point_size;
 state->reads_point_coord = false;
 state->helper_invocations = s->info.fs.needs_helper_invocations;
diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h
index a3e174cb30c..2d5f07451a5 100644
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -244,9 +244,6 @@ typedef struct compiler_context {
 /* Mapping of texture register -> SSA index for unaliasing */
 int texture_index[2];
 
-/* If any path hits a discard instruction */
-bool can_discard;
-
 /* The number of uniforms allowable for the fast path */
 int uniform_cutoff;
 
diff --git a/src/panfrost/midgard/midgard_compile.c 
b/src/panfrost/midgard/midgard_compile.c
index 5e5356ff72b..251eaed44e0 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -1248,8 +1248,6 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr 
*instr)
 struct midgard_instruction discard = v_branch(conditional, 
false);
 discard.branch.target_type = TARGET_DISCARD;
 emit_mir_instruction(ctx, discard);
-
-ctx->can_discard = true;
 break;
 }
 
@@ -2702,8 +2700,6 @@ midgard_compile_shader_nir(struct midgard_screen *screen, 
nir_shader *nir, midga
 
 /* Deal with off-by-one related to the fencepost problem */
 program->work_register_count = ctx->work_registers + 1;
-
-program->can_discard = ctx->can_discard;
 program->uniform_cutoff = ctx->uniform_cutoff;
 
 program->blend_patch_offset = ctx->blend_constant_offset;
diff --git a/src/panfrost/midgard/midgard_compile.h 
b/src/panfrost/midgard/midgard_compile.h
index 2c86ccbca7b..f76715e7a53 100644
--- a/src/panfrost/midgard/midgard_compile.h
+++ b/src/panfrost/midgard/midgard_compile.h
@@ -89,7 +89,6 @@ typedef struct {
 unsigned varyings[32];
 
 /* Boolean properties of the program */
-bool can_discard;
 bool writes_point_size;
 
 int first_tag;
-- 
2.20.1

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[Mesa-dev] [PATCH 3/4] panfrost: Don't DIY point size/coord fields

2019-07-23 Thread Alyssa Rosenzweig 
Again, it's in shader_info for us!

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_assemble.c | 8 ++--
 src/panfrost/midgard/midgard_compile.h  | 3 ---
 2 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_assemble.c 
b/src/gallium/drivers/panfrost/pan_assemble.c
index 75158089c88..8ccf9125a43 100644
--- a/src/gallium/drivers/panfrost/pan_assemble.c
+++ b/src/gallium/drivers/panfrost/pan_assemble.c
@@ -92,8 +92,8 @@ panfrost_shader_compile(struct panfrost_context *ctx, struct 
mali_shader_meta *m
 meta->midgard1.work_count = program.work_register_count;
 
 state->can_discard = s->info.fs.uses_discard;
-state->writes_point_size = program.writes_point_size;
-state->reads_point_coord = false;
+state->writes_point_size = s->info.outputs_written & VARYING_SLOT_PSIZ;
+state->reads_point_coord = s->info.inputs_read & VARYING_SLOT_PNTC;
 state->helper_invocations = s->info.fs.needs_helper_invocations;
 
 /* Separate as primary uniform count is truncated */
@@ -125,14 +125,10 @@ panfrost_shader_compile(struct panfrost_context *ctx, 
struct mali_shader_meta *m
 v.index = 2;
 v.format = MALI_R16F;
 v.swizzle = default_vec1_swizzle;
-
-state->writes_point_size = true;
 } else if (location == VARYING_SLOT_PNTC) {
 v.index = 3;
 v.format = MALI_RG16F;
 v.swizzle = default_vec2_swizzle;
-
-state->reads_point_coord = true;
 } else {
 v.index = 0;
 }
diff --git a/src/panfrost/midgard/midgard_compile.h 
b/src/panfrost/midgard/midgard_compile.h
index f76715e7a53..3b16cbd2bb5 100644
--- a/src/panfrost/midgard/midgard_compile.h
+++ b/src/panfrost/midgard/midgard_compile.h
@@ -88,9 +88,6 @@ typedef struct {
 
 unsigned varyings[32];
 
-/* Boolean properties of the program */
-bool writes_point_size;
-
 int first_tag;
 
 struct util_dynarray compiled;
-- 
2.20.1

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[Mesa-dev] [PATCH 0/4] panfrost: Use shader_info more

2019-07-23 Thread Alyssa Rosenzweig 
We already have all this information available to us, so let's use it
rather than duplicating code left and right. This is obviously a
maintainability win (and means there are less places for things to
wrong). But almost more important is simplifying the compiler backend
specific ABI, which will be a win when wiring in Bifrost support.

Alyssa Rosenzweig (4):
  panfrost: Use NIR helper invocations info
  panfrost: Use nir_gather_info information about discards
  panfrost: Don't DIY point size/coord fields
  panfrost: Compute I/O counts from shader_info

 src/gallium/drivers/panfrost/pan_assemble.c | 28 +
 src/gallium/drivers/panfrost/pan_context.c  |  2 +-
 src/gallium/drivers/panfrost/pan_context.h  |  3 +++
 src/panfrost/midgard/compiler.h |  3 ---
 src/panfrost/midgard/midgard_compile.c  |  7 --
 src/panfrost/midgard/midgard_compile.h  |  7 --
 6 files changed, 22 insertions(+), 28 deletions(-)

-- 
2.20.1

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[Mesa-dev] [PATCH 4/4] panfrost: Compute I/O counts from shader_info

2019-07-23 Thread Alyssa Rosenzweig 
...rather than exposing it in the vendored compiler region.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_assemble.c | 17 ++---
 src/panfrost/midgard/midgard_compile.c  |  3 ---
 src/panfrost/midgard/midgard_compile.h  |  3 ---
 3 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_assemble.c 
b/src/gallium/drivers/panfrost/pan_assemble.c
index 8ccf9125a43..c724489da3c 100644
--- a/src/gallium/drivers/panfrost/pan_assemble.c
+++ b/src/gallium/drivers/panfrost/pan_assemble.c
@@ -87,10 +87,21 @@ panfrost_shader_compile(struct panfrost_context *ctx, 
struct mali_shader_meta *m
 memcpy(state->sysval, program.sysvals, sizeof(state->sysval[0]) * 
state->sysval_count);
 
 meta->midgard1.uniform_count = MIN2(program.uniform_count, 
program.uniform_cutoff);
-meta->attribute_count = program.attribute_count;
-meta->varying_count = program.varying_count;
 meta->midgard1.work_count = program.work_register_count;
 
+switch (s->info.stage) {
+case MESA_SHADER_VERTEX:
+meta->attribute_count = util_bitcount64(s->info.inputs_read);
+meta->varying_count = util_bitcount64(s->info.outputs_written);
+break;
+case MESA_SHADER_FRAGMENT:
+meta->attribute_count = 0;
+meta->varying_count = util_bitcount64(s->info.inputs_read);
+break;
+default:
+unreachable("Unknown shader state");
+}
+
 state->can_discard = s->info.fs.uses_discard;
 state->writes_point_size = s->info.outputs_written & VARYING_SLOT_PSIZ;
 state->reads_point_coord = s->info.inputs_read & VARYING_SLOT_PNTC;
@@ -106,7 +117,7 @@ panfrost_shader_compile(struct panfrost_context *ctx, 
struct mali_shader_meta *m
 unsigned default_vec4_swizzle = panfrost_get_default_swizzle(4);
 
 /* Iterate the varyings and emit the corresponding descriptor */
-for (unsigned i = 0; i < program.varying_count; ++i) {
+for (unsigned i = 0; i < meta->varying_count; ++i) {
 unsigned location = program.varyings[i];
 
 /* Default to a vec4 varying */
diff --git a/src/panfrost/midgard/midgard_compile.c 
b/src/panfrost/midgard/midgard_compile.c
index 251eaed44e0..86d97e37095 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -2477,9 +2477,6 @@ midgard_compile_shader_nir(struct midgard_screen *screen, 
nir_shader *nir, midga
 program->sysval_count = ctx->sysval_count;
 memcpy(program->sysvals, ctx->sysvals, sizeof(ctx->sysvals[0]) * 
ctx->sysval_count);
 
-program->attribute_count = (ctx->stage == MESA_SHADER_VERTEX) ? 
nir->num_inputs : 0;
-program->varying_count = max_varying + 1; /* Fencepost off-by-one */
-
 nir_foreach_function(func, nir) {
 if (!func->impl)
 continue;
diff --git a/src/panfrost/midgard/midgard_compile.h 
b/src/panfrost/midgard/midgard_compile.h
index 3b16cbd2bb5..9f8064873f7 100644
--- a/src/panfrost/midgard/midgard_compile.h
+++ b/src/panfrost/midgard/midgard_compile.h
@@ -77,9 +77,6 @@ typedef struct {
 int uniform_count;
 int uniform_cutoff;
 
-int attribute_count;
-int varying_count;
-
 /* Prepended before uniforms, mapping to SYSVAL_ names for the
  * sysval */
 
-- 
2.20.1

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[Mesa-dev] [PATCH 1/4] panfrost: Use NIR helper invocations info

2019-07-23 Thread Alyssa Rosenzweig 
We don't need to guesstimate this ourselves. This will help when we
bringup derivatives.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_assemble.c | 1 +
 src/gallium/drivers/panfrost/pan_context.c  | 2 +-
 src/gallium/drivers/panfrost/pan_context.h  | 3 +++
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/panfrost/pan_assemble.c 
b/src/gallium/drivers/panfrost/pan_assemble.c
index 5e6f9448668..334ea83305a 100644
--- a/src/gallium/drivers/panfrost/pan_assemble.c
+++ b/src/gallium/drivers/panfrost/pan_assemble.c
@@ -94,6 +94,7 @@ panfrost_shader_compile(struct panfrost_context *ctx, struct 
mali_shader_meta *m
 state->can_discard = program.can_discard;
 state->writes_point_size = program.writes_point_size;
 state->reads_point_coord = false;
+state->helper_invocations = s->info.fs.needs_helper_invocations;
 
 /* Separate as primary uniform count is truncated */
 state->uniform_count = program.uniform_count;
diff --git a/src/gallium/drivers/panfrost/pan_context.c 
b/src/gallium/drivers/panfrost/pan_context.c
index 2f19113e703..9aeb1ba9055 100644
--- a/src/gallium/drivers/panfrost/pan_context.c
+++ b/src/gallium/drivers/panfrost/pan_context.c
@@ -1128,7 +1128,7 @@ panfrost_emit_for_draw(struct panfrost_context *ctx, bool 
with_vertex_data)
 /* Any time texturing is used, derivatives are implicitly
  * calculated, so we need to enable helper invocations */
 
-if (ctx->sampler_view_count[PIPE_SHADER_FRAGMENT])
+if (variant->helper_invocations)
 flags |= MALI_HELPER_INVOCATIONS;
 
 ctx->fragment_shader_core.midgard1.flags = flags;
diff --git a/src/gallium/drivers/panfrost/pan_context.h 
b/src/gallium/drivers/panfrost/pan_context.h
index 5584003b2dd..a398691f0ba 100644
--- a/src/gallium/drivers/panfrost/pan_context.h
+++ b/src/gallium/drivers/panfrost/pan_context.h
@@ -234,6 +234,9 @@ struct panfrost_shader_state {
 
 uint16_t point_sprite_mask;
 unsigned point_sprite_upper_left : 1;
+
+/* Should we enable helper invocations */
+bool helper_invocations;
 };
 
 /* A collection of varyings (the CSO) */
-- 
2.20.1

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[Mesa-dev] [ANNOUNCE] glu 9.0.1

2019-07-23 Thread Matt Turner 

Amarnath Valluri (1):
 libutils/mipmap.c: Fixed possible memory leak

John Hein (1):
 pkgconfig: Include -I path for glu itself

Krzysztof Kosiński (1):
 Remove all uses of the register keyword.

Matt Turner (4):
 Add -D(N)DEBUG to CFLAGS dependent on --enable-debug
 libutil: Include stddef.h for NULL
 Switch from bz2 to xz
 glu 9.0.1

Mike Gorchak (1):
 glu: initialize PriorityQ::order field to NULL in pqNewPriorityQ()

git tag: glu-9.0.1

https://mesa.freedesktop.org/archive/glu/glu-9.0.1.tar.gz
MD5:  5599a0e0a97335e10239d9165aced60d  glu-9.0.1.tar.gz
SHA1: 2d1388106d2556a3847ae7404d7d9dba6531755b  glu-9.0.1.tar.gz
SHA256: f6f484cfcd51e489afe88031afdea1e173aa652697e4c19ddbcb8260579a10f7  
glu-9.0.1.tar.gz
SHA512: 
31d5ae196a42df61a6b161f6107049dbcb59c1517d18dd106324297543b90cff5f0a0720328364f9befaeb7f36d8425ec37b05dfa33f1b750cbcda423888f71e
  glu-9.0.1.tar.gz
PGP:  https://mesa.freedesktop.org/archive/glu/glu-9.0.1.tar.gz.sig

https://mesa.freedesktop.org/archive/glu/glu-9.0.1.tar.xz
MD5:  151aef599b8259efe9acd599c96ea2a3  glu-9.0.1.tar.xz
SHA1: b6ffef562ba55d3f80146d4238589cb9b1de66f5  glu-9.0.1.tar.xz
SHA256: fb5a4c2dd6ba6d1c21ab7c05129b0769544e1d68e1e3b0ffecb18e73c93055bc  
glu-9.0.1.tar.xz
SHA512: 
8a6dae5b4bd63efb96d15f23ccda4ad9c2ffaa964897e5fa63d1e58360d8d4e6732c5efd2109dba04155d5fc457ab1718a65cf9b544ce0d452679ba988d04018
  glu-9.0.1.tar.xz
PGP:  https://mesa.freedesktop.org/archive/glu/glu-9.0.1.tar.xz.sig



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[Mesa-dev] [AppVeyor] mesa master #12016 failed

2019-07-23 Thread AppVeyor 



Build mesa 12016 failed


Commit 2631fd3b0b by Dave Airlie on 7/22/2019 2:04 AM:

gallivm: rework lp_build_tgsi_soa to take a struct\n\nThe parameters were getting messy and I have to add a few more\nfor compute shaders, so clean it up before proceeding.\n\nReviewed-by: Roland Scheidegger 


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[Mesa-dev] [Bug 111150] [BRW] WRC 5 asserts with gallium nine and iris.

2019-07-23 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=50

--- Comment #7 from Nanley Chery  ---
(In reply to Matías Zúñiga from comment #6)
> (In reply to Nanley Chery from comment #3)
> > *** Bug 62 has been marked as a duplicate of this bug. ***
> 
> Sorry, i didn't find this bug before posting.
> 
> The merge request also fixes the problem for me

No problem. I just updated the MR to fix the issue in iris. Please let me know
if it still helps. 

I'm not sure what issues are remaining in gallium nine (if any).

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Re: [Mesa-dev] [PATCH 5/5] radv/gfx10: enable VK_EXT_transform_feedback

2019-07-23 Thread Bas Nieuwenhuizen 
r-b for the series if you resolve my comment on patch  4.

On Tue, Jul 23, 2019 at 3:21 PM Samuel Pitoiset
 wrote:
>
> When a pipeline uses transform feedback, the driver fallbacks to
> the legacy path because NGG support for streamout is a non-trivial
> amount of work.
>
> AMDVLK also uses the legacy path for streamout, while RadeonSI
> uses the new NGG path.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_extensions.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_extensions.py 
> b/src/amd/vulkan/radv_extensions.py
> index e9addad0035..8e1d61dfaaf 100644
> --- a/src/amd/vulkan/radv_extensions.py
> +++ b/src/amd/vulkan/radv_extensions.py
> @@ -129,7 +129,7 @@ EXTENSIONS = [
>  Extension('VK_EXT_shader_stencil_export', 1, True),
>  Extension('VK_EXT_shader_subgroup_ballot',1, True),
>  Extension('VK_EXT_shader_subgroup_vote',  1, True),
> -Extension('VK_EXT_transform_feedback',1, 
> 'device->rad_info.chip_class < GFX10'),
> +Extension('VK_EXT_transform_feedback',1, True),
>  Extension('VK_EXT_vertex_attribute_divisor',  3, True),
>  Extension('VK_EXT_ycbcr_image_arrays',1, True),
>  Extension('VK_AMD_buffer_marker', 1, True),
> --
> 2.22.0
>
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Re: [Mesa-dev] [PATCH 4/5] radv/gfx10: do not enable NGG if a pipeline uses XFB

2019-07-23 Thread Bas Nieuwenhuizen 
On Tue, Jul 23, 2019 at 3:21 PM Samuel Pitoiset
 wrote:
>
> NGG GS for streamout requires a bunch of work, so enable it with
> the legacy path only for now.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_pipeline.c | 28 
>  1 file changed, 28 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index a7ff0e2d139..0903e5abf37 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -33,6 +33,7 @@
>  #include "radv_shader.h"
>  #include "nir/nir.h"
>  #include "nir/nir_builder.h"
> +#include "nir/nir_xfb_info.h"
>  #include "spirv/nir_spirv.h"
>  #include "vk_util.h"
>
> @@ -2269,6 +2270,16 @@ radv_generate_graphics_pipeline_key(struct 
> radv_pipeline *pipeline,
> return key;
>  }
>
> +static bool
> +radv_nir_stage_uses_xfb(const nir_shader *nir)
> +{
> +   nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
> +   bool uses_xfb = !!xfb;
> +
> +   ralloc_free(xfb);
> +   return uses_xfb;
> +}
> +
>  static void
>  radv_fill_shader_keys(struct radv_device *device,
>   struct radv_shader_variant_key *keys,
> @@ -2321,6 +2332,23 @@ radv_fill_shader_keys(struct radv_device *device,
>  */
> keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = 
> false;
> }
> +
> +   /* TODO: Implement streamout support for NGG. */
> +   bool uses_xfb = false;
> +   if ((nir[MESA_SHADER_VERTEX] &&
> +radv_nir_stage_uses_xfb(nir[MESA_SHADER_VERTEX])) ||
> +   (nir[MESA_SHADER_TESS_EVAL] &&
> +radv_nir_stage_uses_xfb(nir[MESA_SHADER_TESS_EVAL])) ||
> +   (nir[MESA_SHADER_GEOMETRY] &&
> +radv_nir_stage_uses_xfb(nir[MESA_SHADER_GEOMETRY])))
> +   uses_xfb = true;

transform feedback can only happen on the last stage before PS right?
Can we first determine what the last shader is and only then check for
xfb? That way we don't have to scan 3 shaders.
> +
> +   if (uses_xfb) {
> +   if (nir[MESA_SHADER_TESS_CTRL])
> +   
> keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
> +   else
> +   keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg 
> = false;
> +   }
> }
>
> for(int i = 0; i < MESA_SHADER_STAGES; ++i)
> --
> 2.22.0
>
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Re: [Mesa-dev] [PATCH v3] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Bas Nieuwenhuizen 
r-b

On Tue, Jul 23, 2019 at 2:44 PM Samuel Pitoiset
 wrote:
>
> For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1.
>
> v3: fix instanceID input VGPR for geometry
> v2: fix instanceID
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_nir_to_llvm.c | 12 +---
>  src/amd/vulkan/radv_shader.c  |  8 ++--
>  2 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index 336bae28614..cf73cdc692b 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -852,9 +852,15 @@ declare_vs_input_vgprs(struct radv_shader_context *ctx, 
> struct arg_info *args)
> }
> } else {
> if (ctx->ac.chip_class >= GFX10) {
> -   add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); 
> /* user vgpr */
> -   add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); 
> /* user vgpr */
> -   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >abi.instance_id);
> +   if (ctx->options->key.vs_common_out.as_ngg) {
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> NULL); /* user vgpr */
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> NULL); /* user vgpr */
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >abi.instance_id);
> +   } else {
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> NULL); /* unused */
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >vs_prim_id);
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >abi.instance_id);
> +   }
> } else {
> add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >abi.instance_id);
> add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >vs_prim_id);
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 3adaf52e152..06122664a13 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -765,7 +765,7 @@ static void radv_postprocess_config(const struct 
> radv_physical_device *pdevice,
> if (info->vs.export_prim_id) {
> vgpr_comp_cnt = 2;
> } else if (info->info.vs.needs_instance_id) {
> -   vgpr_comp_cnt = 1;
> +   vgpr_comp_cnt = pdevice->rad_info.chip_class 
> >= GFX10 ? 3 : 1;
> } else {
> vgpr_comp_cnt = 0;
> }
> @@ -837,7 +837,11 @@ static void radv_postprocess_config(const struct 
> radv_physical_device *pdevice,
>
> if (es_type == MESA_SHADER_VERTEX) {
> /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
> -   es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 
> 1 : 0;
> +   if (info->info.vs.needs_instance_id) {
> +   es_vgpr_comp_cnt = 
> pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
> +   } else {
> +   es_vgpr_comp_cnt = 0;
> +   }
> } else if (es_type == MESA_SHADER_TESS_EVAL) {
> es_vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
> } else {
> --
> 2.22.0
>
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[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization

2019-07-23 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=41

--- Comment #16 from Steven Newbury  ---
Replaying the trace with a recent Mesa causes my GPU to crash in such a way it
requires reboot.  Is that expected to work?

I've rebuit mesa + llvm + xorg-server git master using gcc-9.1 and
C(XX)FLAGS=-O2 and I still get the same output.  Previously, I was building
llvm with clang.  Proton/DXVK is built using "-O2 -march=native", also with
gcc-9.1.

Is it a bug in my GPU?

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Re: [Mesa-dev] [PATCH] nv50/ir: Add mul and mod constant optimizations

2019-07-23 Thread Karol Herbst 
yeah.. I am not quite sure myself about it. But skipping on the div
emulation seems like a good idea in general. But it's also not common
enough to actually care all that much about it.

On Tue, Jul 23, 2019 at 5:18 PM Ilia Mirkin  wrote:
>
> On Tue, Jul 23, 2019 at 11:15 AM Karol Herbst  wrote:
> >
> > On Tue, Jul 23, 2019 at 4:50 PM Ilia Mirkin  wrote:
> > >
> > > You handle 1/n but not 1%n? TBH, the 1/n code isn't 100% obvious to
> > > me... 1/n = |n|-1 > 0 ?  i forget how SLCT works, but I can't
> > > think of a way to finish that expression in terms of |n|-1 and n. And
> > > what about n == 0. I'd just as soon drop that case.
> > >
> >
> > is 1/0 actually defined in glsl? I thought that the result is
> > undefined and we can basically do whatever, no? At least intel seems
> > to return INT_MAX for 1/0
>
> If you guys really like it, just add more comments that cover my questions.
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Re: [Mesa-dev] [PATCH] nv50/ir: Add mul and mod constant optimizations

2019-07-23 Thread Ilia Mirkin 
On Tue, Jul 23, 2019 at 11:15 AM Karol Herbst  wrote:
>
> On Tue, Jul 23, 2019 at 4:50 PM Ilia Mirkin  wrote:
> >
> > You handle 1/n but not 1%n? TBH, the 1/n code isn't 100% obvious to
> > me... 1/n = |n|-1 > 0 ?  i forget how SLCT works, but I can't
> > think of a way to finish that expression in terms of |n|-1 and n. And
> > what about n == 0. I'd just as soon drop that case.
> >
>
> is 1/0 actually defined in glsl? I thought that the result is
> undefined and we can basically do whatever, no? At least intel seems
> to return INT_MAX for 1/0

If you guys really like it, just add more comments that cover my questions.
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Re: [Mesa-dev] [PATCH] nv50/ir: Add mul and mod constant optimizations

2019-07-23 Thread Karol Herbst 
On Tue, Jul 23, 2019 at 4:50 PM Ilia Mirkin  wrote:
>
> You handle 1/n but not 1%n? TBH, the 1/n code isn't 100% obvious to
> me... 1/n = |n|-1 > 0 ?  i forget how SLCT works, but I can't
> think of a way to finish that expression in terms of |n|-1 and n. And
> what about n == 0. I'd just as soon drop that case.
>

is 1/0 actually defined in glsl? I thought that the result is
undefined and we can basically do whatever, no? At least intel seems
to return INT_MAX for 1/0

> On Tue, Jul 23, 2019 at 10:20 AM Mark Menzynski  wrote:
> >
> > Optimizations for 0/n, 1/n and 0%n.
> > No changes in shader db tests, because it is never used here, but it
> > should become handy.
> >
> > Signed-off-by: Mark Menzynski 
> > ---
> >  .../nouveau/codegen/nv50_ir_peephole.cpp  | 30 +--
> >  1 file changed, 28 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
> > b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> > index 0b3220903b9..12069e19808 100644
> > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> > @@ -1177,10 +1177,28 @@ ConstantFolding::opnd(Instruction *i, 
> > ImmediateValue , int s)
> >break;
> >
> > case OP_DIV:
> > -  if (s != 1 || (i->dType != TYPE_S32 && i->dType != TYPE_U32))
> > +  if (i->dType != TYPE_S32 && i->dType != TYPE_U32)
> >   break;
> > +
> >bld.setPosition(i, false);
> > -  if (imm0.reg.data.u32 == 0) {
> > +  if (s == 0) {
> > + if (imm0.reg.data.u32 == 0) {
> > +i->op = OP_MOV;
> > +i->setSrc(1, NULL);
> > + }
> > + else if (imm0.reg.data.u32 == 1) {
> > +Value *tA, *tB;
> > +Instruction *slct;
> > +
> > +tA = bld.mkOp1v(OP_ABS, TYPE_U32, bld.getSSA(), i->getSrc(1));
> > +tB = bld.mkOp2v(OP_ADD, TYPE_S32, bld.getSSA(), tA, 
> > bld.loadImm(NULL, -1));
> > +slct = bld.mkCmp(OP_SLCT, CC_GT, i->dType, bld.getSSA(), 
> > TYPE_U32, bld.loadImm(NULL, 0), i->getSrc(1), tB);
> > +i->def(0).replace(slct->getDef(0), false);
> > + }
> > + break;
> > +  }
> > +
> > +  if (s != 1 || imm0.reg.data.u32 == 0) {
> >   break;
> >} else
> >if (imm0.reg.data.u32 == 1) {
> > @@ -1259,6 +1277,14 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue 
> > , int s)
> >break;
> >
> > case OP_MOD:
> > +  if (s == 0) {
> > + if (imm0.reg.data.u32 == 0) {
> > +i->op = OP_MOV;
> > +i->setSrc(1, NULL);
> > + }
> > + break;
> > +  }
> > +
> >if (s == 1 && imm0.isPow2()) {
> >   bld.setPosition(i, false);
> >   if (i->sType == TYPE_U32) {
> > --
> > 2.21.0
> >
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Re: [Mesa-dev] [PATCH] nv50/ir: Add mul and mod constant optimizations

2019-07-23 Thread Ilia Mirkin 
You handle 1/n but not 1%n? TBH, the 1/n code isn't 100% obvious to
me... 1/n = |n|-1 > 0 ?  i forget how SLCT works, but I can't
think of a way to finish that expression in terms of |n|-1 and n. And
what about n == 0. I'd just as soon drop that case.

On Tue, Jul 23, 2019 at 10:20 AM Mark Menzynski  wrote:
>
> Optimizations for 0/n, 1/n and 0%n.
> No changes in shader db tests, because it is never used here, but it
> should become handy.
>
> Signed-off-by: Mark Menzynski 
> ---
>  .../nouveau/codegen/nv50_ir_peephole.cpp  | 30 +--
>  1 file changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> index 0b3220903b9..12069e19808 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> @@ -1177,10 +1177,28 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue 
> , int s)
>break;
>
> case OP_DIV:
> -  if (s != 1 || (i->dType != TYPE_S32 && i->dType != TYPE_U32))
> +  if (i->dType != TYPE_S32 && i->dType != TYPE_U32)
>   break;
> +
>bld.setPosition(i, false);
> -  if (imm0.reg.data.u32 == 0) {
> +  if (s == 0) {
> + if (imm0.reg.data.u32 == 0) {
> +i->op = OP_MOV;
> +i->setSrc(1, NULL);
> + }
> + else if (imm0.reg.data.u32 == 1) {
> +Value *tA, *tB;
> +Instruction *slct;
> +
> +tA = bld.mkOp1v(OP_ABS, TYPE_U32, bld.getSSA(), i->getSrc(1));
> +tB = bld.mkOp2v(OP_ADD, TYPE_S32, bld.getSSA(), tA, 
> bld.loadImm(NULL, -1));
> +slct = bld.mkCmp(OP_SLCT, CC_GT, i->dType, bld.getSSA(), 
> TYPE_U32, bld.loadImm(NULL, 0), i->getSrc(1), tB);
> +i->def(0).replace(slct->getDef(0), false);
> + }
> + break;
> +  }
> +
> +  if (s != 1 || imm0.reg.data.u32 == 0) {
>   break;
>} else
>if (imm0.reg.data.u32 == 1) {
> @@ -1259,6 +1277,14 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue 
> , int s)
>break;
>
> case OP_MOD:
> +  if (s == 0) {
> + if (imm0.reg.data.u32 == 0) {
> +i->op = OP_MOV;
> +i->setSrc(1, NULL);
> + }
> + break;
> +  }
> +
>if (s == 1 && imm0.isPow2()) {
>   bld.setPosition(i, false);
>   if (i->sType == TYPE_U32) {
> --
> 2.21.0
>
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[Mesa-dev] [PATCH] nv50/ir: Add mul and mod constant optimizations

2019-07-23 Thread Mark Menzynski 
Optimizations for 0/n, 1/n and 0%n.
No changes in shader db tests, because it is never used here, but it
should become handy.

Signed-off-by: Mark Menzynski 
---
 .../nouveau/codegen/nv50_ir_peephole.cpp  | 30 +--
 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 0b3220903b9..12069e19808 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1177,10 +1177,28 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue 
, int s)
   break;
 
case OP_DIV:
-  if (s != 1 || (i->dType != TYPE_S32 && i->dType != TYPE_U32))
+  if (i->dType != TYPE_S32 && i->dType != TYPE_U32)
  break;
+
   bld.setPosition(i, false);
-  if (imm0.reg.data.u32 == 0) {
+  if (s == 0) {
+ if (imm0.reg.data.u32 == 0) {
+i->op = OP_MOV;
+i->setSrc(1, NULL);
+ }
+ else if (imm0.reg.data.u32 == 1) {
+Value *tA, *tB;
+Instruction *slct;
+
+tA = bld.mkOp1v(OP_ABS, TYPE_U32, bld.getSSA(), i->getSrc(1));
+tB = bld.mkOp2v(OP_ADD, TYPE_S32, bld.getSSA(), tA, 
bld.loadImm(NULL, -1));
+slct = bld.mkCmp(OP_SLCT, CC_GT, i->dType, bld.getSSA(), TYPE_U32, 
bld.loadImm(NULL, 0), i->getSrc(1), tB);
+i->def(0).replace(slct->getDef(0), false);
+ }
+ break;
+  }
+
+  if (s != 1 || imm0.reg.data.u32 == 0) {
  break;
   } else
   if (imm0.reg.data.u32 == 1) {
@@ -1259,6 +1277,14 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue 
, int s)
   break;
 
case OP_MOD:
+  if (s == 0) {
+ if (imm0.reg.data.u32 == 0) {
+i->op = OP_MOV;
+i->setSrc(1, NULL);
+ }
+ break;
+  }
+
   if (s == 1 && imm0.isPow2()) {
  bld.setPosition(i, false);
  if (i->sType == TYPE_U32) {
-- 
2.21.0

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[Mesa-dev] [PATCH v2] gm107/ir: Add stg, ldg instructions and function for checking offset length

2019-07-23 Thread Mark Menzynski 
Nvidia actively uses these instructions, maybe they are better in
something.
Long offset checking function was made because these functions only have 24 bit
address offsets.

v2: removed long offset funnction

Signed-off-by: Mark Menzynski 
---
 .../nouveau/codegen/nv50_ir_emit_gm107.cpp| 24 +++
 1 file changed, 24 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 6eefe8f0025..8da5adb94ce 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -174,9 +174,11 @@ private:
void emitLDC();
void emitLDL();
void emitLDS();
+   void emitLDG();
void emitLD();
void emitSTL();
void emitSTS();
+   void emitSTG();
void emitST();
void emitALD();
void emitAST();
@@ -2414,6 +2416,17 @@ CodeEmitterGM107::emitLDS()
emitGPR  (0x00, insn->def(0));
 }
 
+void
+CodeEmitterGM107::emitLDG()
+{
+   emitInsn (0xeed0);
+   emitLDSTs(0x30, insn->dType);
+   emitLDSTc(0x2e);
+   emitField(0x2d, 1, insn->src(0).getIndirect(0)->getSize() == 8);
+   emitADDR (0x08, 0x14, 24, 0, insn->src(0));
+   emitGPR  (0x00, insn->def(0));
+}
+
 void
 CodeEmitterGM107::emitLD()
 {
@@ -2445,6 +2458,17 @@ CodeEmitterGM107::emitSTS()
emitGPR  (0x00, insn->src(1));
 }
 
+void
+CodeEmitterGM107::emitSTG()
+{
+   emitInsn (0xeed8);
+   emitLDSTs(0x30, insn->dType);
+   emitLDSTc(0x2e);
+   emitField(0x2d, 1, insn->src(0).getIndirect(0)->getSize() == 8);
+   emitADDR (0x08, 0x14, 24, 0, insn->src(0));
+   emitGPR  (0x00, insn->src(1));
+}
+
 void
 CodeEmitterGM107::emitST()
 {
-- 
2.21.0

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Re: [Mesa-dev] [PATCH] gm107/ir: Add stg, ldg instructions and function for checking offset length

2019-07-23 Thread Mark Menzynski 
> > @@ -2414,6 +2428,17 @@ CodeEmitterGM107::emitLDS()
> > emitGPR  (0x00, insn->def(0));
> >  }
> >
> > +void
> > +CodeEmitterGM107::emitLDG()
> > +{
> > +   emitInsn (0xeed0);
> > +   emitLDSTs(0x30, insn->dType);
> > +   emitLDSTc(0x2e);
> > +   emitField(0x2d, 1, insn->src(0).getIndirect(0)->getSize() == 8);
>
> I didn't look, but we don't do something a bit more subtle on the
> other ones, like checking if there's an indirect access in the first
> place? With g[], it almost exclusively will be, but still...

It's done same in the original store and load functions.

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[Mesa-dev] [PATCH 1/5] radv/gfx10: update streamout descriptors

2019-07-23 Thread Samuel Pitoiset 
Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_cmd_buffer.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 84d627340e9..c2e3f3b5fd0 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2419,8 +2419,15 @@ radv_flush_streamout_descriptors(struct radv_cmd_buffer 
*cmd_buffer)
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
- S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
- 
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
+
+   if 
(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+   desc[3] |= 
S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+  S_008F0C_OOB_SELECT(3) |
+  S_008F0C_RESOURCE_LEVEL(1);
+   } else {
+   desc[3] |= 
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+   }
}
 
va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
-- 
2.22.0

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[Mesa-dev] [PATCH 3/5] radv/gfx10: emit streamout shader config

2019-07-23 Thread Samuel Pitoiset 
Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_shader.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 5fd1022b05a..56f421026b7 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -690,7 +690,12 @@ static void radv_postprocess_config(const struct 
radv_physical_device *pdevice,
config_out->float_mode |= V_00B028_FP_64_DENORMS;
 
config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
-   S_00B12C_SCRATCH_EN(scratch_enabled);
+   S_00B12C_SCRATCH_EN(scratch_enabled) |
+   S_00B12C_SO_BASE0_EN(!!info->info.so.strides[0]) |
+   S_00B12C_SO_BASE1_EN(!!info->info.so.strides[1]) |
+   S_00B12C_SO_BASE2_EN(!!info->info.so.strides[2]) |
+   S_00B12C_SO_BASE3_EN(!!info->info.so.strides[3]) |
+   S_00B12C_SO_EN(!!info->info.so.num_outputs);
 
config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / 4) |
S_00B848_DX10_CLAMP(1) |
@@ -700,12 +705,7 @@ static void radv_postprocess_config(const struct 
radv_physical_device *pdevice,
config_out->rsrc2 |= 
S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
} else {
config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
-   config_out->rsrc2 |= 
S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5)  |
-
S_00B12C_SO_BASE0_EN(!!info->info.so.strides[0]) |
-
S_00B12C_SO_BASE1_EN(!!info->info.so.strides[1]) |
-
S_00B12C_SO_BASE2_EN(!!info->info.so.strides[2]) |
-
S_00B12C_SO_BASE3_EN(!!info->info.so.strides[3]) |
-
S_00B12C_SO_EN(!!info->info.so.num_outputs);
+   config_out->rsrc2 |= 
S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
}
 
switch (stage) {
-- 
2.22.0

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[Mesa-dev] [PATCH 4/5] radv/gfx10: do not enable NGG if a pipeline uses XFB

2019-07-23 Thread Samuel Pitoiset 
NGG GS for streamout requires a bunch of work, so enable it with
the legacy path only for now.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_pipeline.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a7ff0e2d139..0903e5abf37 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -33,6 +33,7 @@
 #include "radv_shader.h"
 #include "nir/nir.h"
 #include "nir/nir_builder.h"
+#include "nir/nir_xfb_info.h"
 #include "spirv/nir_spirv.h"
 #include "vk_util.h"
 
@@ -2269,6 +2270,16 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline 
*pipeline,
return key;
 }
 
+static bool
+radv_nir_stage_uses_xfb(const nir_shader *nir)
+{
+   nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
+   bool uses_xfb = !!xfb;
+
+   ralloc_free(xfb);
+   return uses_xfb;
+}
+
 static void
 radv_fill_shader_keys(struct radv_device *device,
  struct radv_shader_variant_key *keys,
@@ -2321,6 +2332,23 @@ radv_fill_shader_keys(struct radv_device *device,
 */
keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = 
false;
}
+
+   /* TODO: Implement streamout support for NGG. */
+   bool uses_xfb = false;
+   if ((nir[MESA_SHADER_VERTEX] &&
+radv_nir_stage_uses_xfb(nir[MESA_SHADER_VERTEX])) ||
+   (nir[MESA_SHADER_TESS_EVAL] &&
+radv_nir_stage_uses_xfb(nir[MESA_SHADER_TESS_EVAL])) ||
+   (nir[MESA_SHADER_GEOMETRY] &&
+radv_nir_stage_uses_xfb(nir[MESA_SHADER_GEOMETRY])))
+   uses_xfb = true;
+
+   if (uses_xfb) {
+   if (nir[MESA_SHADER_TESS_CTRL])
+   
keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
+   else
+   keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = 
false;
+   }
}
 
for(int i = 0; i < MESA_SHADER_STAGES; ++i)
-- 
2.22.0

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[Mesa-dev] [PATCH 5/5] radv/gfx10: enable VK_EXT_transform_feedback

2019-07-23 Thread Samuel Pitoiset 
When a pipeline uses transform feedback, the driver fallbacks to
the legacy path because NGG support for streamout is a non-trivial
amount of work.

AMDVLK also uses the legacy path for streamout, while RadeonSI
uses the new NGG path.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_extensions.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index e9addad0035..8e1d61dfaaf 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -129,7 +129,7 @@ EXTENSIONS = [
 Extension('VK_EXT_shader_stencil_export', 1, True),
 Extension('VK_EXT_shader_subgroup_ballot',1, True),
 Extension('VK_EXT_shader_subgroup_vote',  1, True),
-Extension('VK_EXT_transform_feedback',1, 
'device->rad_info.chip_class < GFX10'),
+Extension('VK_EXT_transform_feedback',1, True),
 Extension('VK_EXT_vertex_attribute_divisor',  3, True),
 Extension('VK_EXT_ycbcr_image_arrays',1, True),
 Extension('VK_AMD_buffer_marker', 1, True),
-- 
2.22.0

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[Mesa-dev] [PATCH 2/5] radv/gfx10: declare streamout user SGPRs

2019-07-23 Thread Samuel Pitoiset 
Required for legacy streamout.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index cf73cdc692b..020c6d17771 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -876,9 +876,6 @@ declare_streamout_sgprs(struct radv_shader_context *ctx, 
gl_shader_stage stage,
 {
int i;
 
-   if (ctx->ac.chip_class >= GFX10)
-   return;
-
/* Streamout SGPRs. */
if (ctx->shader_info->info.so.num_outputs) {
assert(stage == MESA_SHADER_VERTEX ||
-- 
2.22.0

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[Mesa-dev] [PATCH v3] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Samuel Pitoiset 
For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1.

v3: fix instanceID input VGPR for geometry
v2: fix instanceID

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 12 +---
 src/amd/vulkan/radv_shader.c  |  8 ++--
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 336bae28614..cf73cdc692b 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -852,9 +852,15 @@ declare_vs_input_vgprs(struct radv_shader_context *ctx, 
struct arg_info *args)
}
} else {
if (ctx->ac.chip_class >= GFX10) {
-   add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* 
user vgpr */
-   add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* 
user vgpr */
-   add_arg(args, ARG_VGPR, ctx->ac.i32, 
>abi.instance_id);
+   if (ctx->options->key.vs_common_out.as_ngg) {
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
NULL); /* user vgpr */
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
NULL); /* user vgpr */
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
>abi.instance_id);
+   } else {
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
NULL); /* unused */
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
>vs_prim_id);
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
>abi.instance_id);
+   }
} else {
add_arg(args, ARG_VGPR, ctx->ac.i32, 
>abi.instance_id);
add_arg(args, ARG_VGPR, ctx->ac.i32, 
>vs_prim_id);
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 3adaf52e152..06122664a13 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -765,7 +765,7 @@ static void radv_postprocess_config(const struct 
radv_physical_device *pdevice,
if (info->vs.export_prim_id) {
vgpr_comp_cnt = 2;
} else if (info->info.vs.needs_instance_id) {
-   vgpr_comp_cnt = 1;
+   vgpr_comp_cnt = pdevice->rad_info.chip_class >= 
GFX10 ? 3 : 1;
} else {
vgpr_comp_cnt = 0;
}
@@ -837,7 +837,11 @@ static void radv_postprocess_config(const struct 
radv_physical_device *pdevice,
 
if (es_type == MESA_SHADER_VERTEX) {
/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
-   es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 
: 0;
+   if (info->info.vs.needs_instance_id) {
+   es_vgpr_comp_cnt = pdevice->rad_info.chip_class 
>= GFX10 ? 3 : 1;
+   } else {
+   es_vgpr_comp_cnt = 0;
+   }
} else if (es_type == MESA_SHADER_TESS_EVAL) {
es_vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
} else {
-- 
2.22.0

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Re: [Mesa-dev] [PATCH v2] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Bas Nieuwenhuizen 
r-b

On Tue, Jul 23, 2019 at 2:10 PM Samuel Pitoiset
 wrote:
>
> For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1.
>
> v2: fix instanceID
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_nir_to_llvm.c | 12 +---
>  src/amd/vulkan/radv_shader.c  |  2 +-
>  2 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index 336bae28614..cf73cdc692b 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -852,9 +852,15 @@ declare_vs_input_vgprs(struct radv_shader_context *ctx, 
> struct arg_info *args)
> }
> } else {
> if (ctx->ac.chip_class >= GFX10) {
> -   add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); 
> /* user vgpr */
> -   add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); 
> /* user vgpr */
> -   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >abi.instance_id);
> +   if (ctx->options->key.vs_common_out.as_ngg) {
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> NULL); /* user vgpr */
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> NULL); /* user vgpr */
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >abi.instance_id);
> +   } else {
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> NULL); /* unused */
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >vs_prim_id);
> +   add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >abi.instance_id);
> +   }
> } else {
> add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >abi.instance_id);
> add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >vs_prim_id);
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 3adaf52e152..3d1b56e7f60 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -765,7 +765,7 @@ static void radv_postprocess_config(const struct 
> radv_physical_device *pdevice,
> if (info->vs.export_prim_id) {
> vgpr_comp_cnt = 2;
> } else if (info->info.vs.needs_instance_id) {
> -   vgpr_comp_cnt = 1;
> +   vgpr_comp_cnt = pdevice->rad_info.chip_class 
> >= GFX10 ? 3 : 1;
> } else {
> vgpr_comp_cnt = 0;
> }
> --
> 2.22.0
>
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[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization

2019-07-23 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=41

--- Comment #15 from Steven Newbury  ---
I've tried recent versions, and compiled with just "-O2", every version since
the commit behaves that way for me.  I'm going to try to rebuild llvm with -O2,
perhaps llvm is getting subtly miscompiled.  It's strange that everything else
I've tried has worked fine thougth!

Are there any other dependencies which might affect shader
compilation/rendering that I might try to rebuild?

(I'm on Gentoo so trying different versions or complier flags isn't an issue)

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[Mesa-dev] [PATCH v2] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Samuel Pitoiset 
For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1.

v2: fix instanceID

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 12 +---
 src/amd/vulkan/radv_shader.c  |  2 +-
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 336bae28614..cf73cdc692b 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -852,9 +852,15 @@ declare_vs_input_vgprs(struct radv_shader_context *ctx, 
struct arg_info *args)
}
} else {
if (ctx->ac.chip_class >= GFX10) {
-   add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* 
user vgpr */
-   add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* 
user vgpr */
-   add_arg(args, ARG_VGPR, ctx->ac.i32, 
>abi.instance_id);
+   if (ctx->options->key.vs_common_out.as_ngg) {
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
NULL); /* user vgpr */
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
NULL); /* user vgpr */
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
>abi.instance_id);
+   } else {
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
NULL); /* unused */
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
>vs_prim_id);
+   add_arg(args, ARG_VGPR, ctx->ac.i32, 
>abi.instance_id);
+   }
} else {
add_arg(args, ARG_VGPR, ctx->ac.i32, 
>abi.instance_id);
add_arg(args, ARG_VGPR, ctx->ac.i32, 
>vs_prim_id);
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 3adaf52e152..3d1b56e7f60 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -765,7 +765,7 @@ static void radv_postprocess_config(const struct 
radv_physical_device *pdevice,
if (info->vs.export_prim_id) {
vgpr_comp_cnt = 2;
} else if (info->info.vs.needs_instance_id) {
-   vgpr_comp_cnt = 1;
+   vgpr_comp_cnt = pdevice->rad_info.chip_class >= 
GFX10 ? 3 : 1;
} else {
vgpr_comp_cnt = 0;
}
-- 
2.22.0

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Re: [Mesa-dev] [PATCH] radv: fix crash in vkCmdClearAttachments with unused attachment

2019-07-23 Thread Juan A. Suarez Romero 
On Mon, 2019-07-22 at 10:12 +0200, Samuel Pitoiset wrote:
> depth_stencil_attachment and/or ds_resolve attachment can be NULL.
> 
> This fixes crashes with
> dEQP-VK.renderpass.suballocation.unused_clear_attachments.*
> 
> Cc: 19.1 
> Signed-off-by: Samuel Pitoiset 
> ---


This does not apply cleanly, so I've resolved it as 
https://gitlab.freedesktop.org/mesa/mesa/commit/e1800b20f44670829ce4d3ec9c0df2f9f2d87976


J.A.

>  src/amd/vulkan/radv_meta_clear.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/amd/vulkan/radv_meta_clear.c 
> b/src/amd/vulkan/radv_meta_clear.c
> index dd2ba402f40..b93ba3e0b29 100644
> --- a/src/amd/vulkan/radv_meta_clear.c
> +++ b/src/amd/vulkan/radv_meta_clear.c
> @@ -1688,7 +1688,7 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer,
>   if (ds_resolve_clear)
>   ds_att = subpass->ds_resolve_attachment;
>  
> - if (ds_att->attachment == VK_ATTACHMENT_UNUSED)
> + if (!ds_att || ds_att->attachment == VK_ATTACHMENT_UNUSED)
>   return;
>  
>   VkImageLayout image_layout = ds_att->layout;

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Re: [Mesa-dev] [PATCH] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Samuel Pitoiset 


On 7/23/19 1:37 PM, Bas Nieuwenhuizen wrote:

So does this work with tests that use multiple instances?

Apparently no.


If so, r-b.

On Tue, Jul 23, 2019 at 1:29 PM Samuel Pitoiset
 wrote:

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_nir_to_llvm.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 336bae28614..9cea92e8a69 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -851,7 +851,8 @@ declare_vs_input_vgprs(struct radv_shader_context *ctx, 
struct arg_info *args)
 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* 
unused */
 }
 } else {
-   if (ctx->ac.chip_class >= GFX10) {
+   if (ctx->ac.chip_class >= GFX10 &&
+   ctx->options->key.vs_common_out.as_ngg) {
 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* 
user vgpr */
 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* 
user vgpr */
 add_arg(args, ARG_VGPR, ctx->ac.i32, 
>abi.instance_id);
--
2.22.0

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Re: [Mesa-dev] [PATCH] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Bas Nieuwenhuizen 
So does this work with tests that use multiple instances?

If so, r-b.

On Tue, Jul 23, 2019 at 1:29 PM Samuel Pitoiset
 wrote:
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_nir_to_llvm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index 336bae28614..9cea92e8a69 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -851,7 +851,8 @@ declare_vs_input_vgprs(struct radv_shader_context *ctx, 
> struct arg_info *args)
> add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); 
> /* unused */
> }
> } else {
> -   if (ctx->ac.chip_class >= GFX10) {
> +   if (ctx->ac.chip_class >= GFX10 &&
> +   ctx->options->key.vs_common_out.as_ngg) {
> add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); 
> /* user vgpr */
> add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); 
> /* user vgpr */
> add_arg(args, ARG_VGPR, ctx->ac.i32, 
> >abi.instance_id);
> --
> 2.22.0
>
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[Mesa-dev] [PATCH] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Samuel Pitoiset 
Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 336bae28614..9cea92e8a69 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -851,7 +851,8 @@ declare_vs_input_vgprs(struct radv_shader_context *ctx, 
struct arg_info *args)
add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* 
unused */
}
} else {
-   if (ctx->ac.chip_class >= GFX10) {
+   if (ctx->ac.chip_class >= GFX10 &&
+   ctx->options->key.vs_common_out.as_ngg) {
add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* 
user vgpr */
add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* 
user vgpr */
add_arg(args, ARG_VGPR, ctx->ac.i32, 
>abi.instance_id);
-- 
2.22.0

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[Mesa-dev] [Bug 111200] Xorg Graphical Corruption when using anything Vulkan on Navi10

2019-07-23 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=111200

Bas Nieuwenhuizen  changed:

   What|Removed |Added

 Status|NEW |NEEDINFO

--- Comment #1 from Bas Nieuwenhuizen  ---
Do 

https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1425/commits

+

https://patchwork.freedesktop.org/patch/319206/?series=64045=1

Fix this issue. (I suspect it is a state leak)

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[Mesa-dev] [ANNOUNCE] Mesa 19.1.3

2019-07-23 Thread Juan A. Suarez Romero 
Mesa 19.1.3 is now available.

In this release we have:

Mostly in fixes for ANV and RADV drivers, as well as NIR backend fixes.

Several of those patches fixe actually crashes with the drivers,
and a couple of them fix memory leaks.


Bas Nieuwenhuizen (3):
  radv: Handle cmask being disallowed by addrlib.
  anv: Add android dependencies on android.
  radv: Only save the descriptor set if we have one.

Caio Marcelo de Oliveira Filho (2):
  anv: Fix pool allocator when first alloc needs to grow
  spirv: Fix stride calculation when lowering Workgroup to offsets

Chia-I Wu (2):
  anv: fix VkExternalBufferProperties for unsupported handles
  anv: fix VkExternalBufferProperties for host allocation

Connor Abbott (1):
  nir: Add a helper to determine if an intrinsic can be reordered

Dave Airlie (1):
  radv: fix crash in shader tracing.

Eric Anholt (1):
  freedreno: Fix assertion failures in context setup in shader-db mode.

Gert Wollny (1):
  softpipe: Remove unused static function

Ian Romanick (4):
  intel/vec4: Reswizzle VF immediates too
  nir: Add unit tests for nir_opt_comparison_pre
  nir: Use nir_src_bit_size instead of alu1->dest.dest.ssa.bit_size
  mesa: Set minimum possible GLSL version

Jason Ekstrand (13):
  nir/instr_set: Expose nir_instrs_equal()
  nir/loop_analyze: Fix phi-of-identical-alu detection
  nir: Add more helpers for working with const values
  nir/loop_analyze: Handle bit sizes correctly in calculate_iterations
  nir/loop_analyze: Bail if we encounter swizzles
  anv: Set Stateless Data Port Access MOCS
  nir/opt_if: Clean up single-src phis in opt_if_loop_terminator
  nir,intel: Add support for lowering 64-bit nir_opt_extract_*
  anv: Account for dynamic stencil write disables in the PMA fix
  nir/regs_to_ssa: Handle regs in phi sources properly
  nir/loop_analyze: Refactor detection of limit vars
  nir: Add some helpers for chasing SSA values properly
  nir/loop_analyze: Properly handle swizzles in loop conditions

Juan A. Suarez Romero (3):
  docs: add sha256 checksums for 19.1.2
  Update version to 19.1.3
  docs: add release notes for 19.1.3

Lepton Wu (1):
  virgl: Set meta data for textures from handle.

Lionel Landwerlin (6):
  vulkan/overlay: fix command buffer stats
  vulkan/overlay: fix crash on freeing NULL command buffer
  anv: fix crash in vkCmdClearAttachments with unused attachment
  vulkan/wsi: update swapchain status on vkQueuePresent
  anv: report timestampComputeAndGraphics true
  anv: fix format mapping for depth/stencil formats

Marek Olšák (1):
  radeonsi: don't set READ_ONLY for const_uploader to fix bindless texture 
hangs

Samuel Iglesias Gonsálvez (1):
  anv: fix alphaToCoverage when there is no color attachment

Samuel Pitoiset (1):
  radv: fix VGT_GS_MODE if VS uses the primitive ID

Sergii Romantsov (1):
  meta: memory leak of CopyPixels usage

Timothy Arceri (1):
  mesa: save/restore SSO flag when using ARB_get_program_binary

Vinson Lee (1):
  meson: Add dep_thread dependency.

Yevhenii Kolesnikov (1):
  meta: leaking of BO with DrawPixels

git tag: mesa-19.1.3

https://mesa.freedesktop.org/archive/mesa-19.1.3.tar.xz
MD5:  9772ebf9ac40289a62a02c046904c8af  mesa-19.1.3.tar.xz
SHA1: ee3b1b4f9dac391d17b5f5325e41c1d3fcd1e730  mesa-19.1.3.tar.xz
SHA256: 845460b2225d15c15d4a9743dec798ff0b7396b533011d43e774e67f7825b7e0  
mesa-19.1.3.tar.xz
SHA512: 
787310c43089142209ff7db298489b0815b630577680d5ce1bc3f796eed3772ba41f03e5e773b77ae084c191ed4e365eac1753166ce60f12b8f5974d55762eeb
  mesa-19.1.3.tar.xz
PGP:  https://mesa.freedesktop.org/archive/mesa-19.1.3.tar.xz.sig



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[Mesa-dev] [Bug 111200] Xorg Graphical Corruption when using anything Vulkan on Navi10

2019-07-23 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=111200

Bug ID: 111200
   Summary: Xorg Graphical Corruption when using anything Vulkan
on Navi10
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: m.mcn...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

Created attachment 144852
  --> https://bugs.freedesktop.org/attachment.cgi?id=144852=edit
example of font corruption

Fedora 30, with Kernel 5.1rc1
Mesa 19.2.0-0.25.git915abbe
LLVM 10.0.0-0.1.r366635
GPU RX 5700XT (navi 10)

Usual desktop usage with the above packages is fine, but as soon as user loads
anything that makes use of RADV (Steam Client, anything in DXVK) xorg starts
visually corrupting, black boxes around things like firefox windows, fonts turn
into boxes. Corruption is not resolved until a reboot

Does not happen with mesa-vulkan-drivers packages are removed and replaced with
amdvlk equivalent

Multiple users on Arch Forums and Reddit report similar experience

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Re: [Mesa-dev] [PATCH] radv/gfx10: enable CLEAR_state

2019-07-23 Thread Bas Nieuwenhuizen 
r-b

On Tue, Jul 23, 2019 at 8:37 AM Samuel Pitoiset
 wrote:
>
> It actually works.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_device.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 992e12840f7..93b03afda22 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -354,8 +354,7 @@ radv_physical_device_init(struct radv_physical_device 
> *device,
> /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
>  * on GFX6.
>  */
> -   device->has_clear_state = device->rad_info.chip_class >= GFX7 &&
> - device->rad_info.chip_class <= GFX9;
> +   device->has_clear_state = device->rad_info.chip_class >= GFX7;
>
> device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= 
> GFX8;
>
> --
> 2.22.0
>
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[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization

2019-07-23 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=41

--- Comment #14 from Connor Abbott  ---
I tried this on my polaris10 card (Rx 580) and I couldn't see the corruption
with either the commit you mentioned + LLVM 8.0, or a recent mesa master + LLVM
master. The before trace wouldn't render with an "Error   - Unrecognised
section type 'c0'", but the after trace didn't have the corruption (btw, you
don't need to record two separate traces -- the trace only has the game's
rendering commands, and not the final output, so if there's a bug in the driver
it'll be recreated when replaying the trace with the buggy driver). Does the
corruption still occur for you when you replay your trace under renderdoc with
a recent mesa?

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[Mesa-dev] [AppVeyor] mesa master #11986 completed

2019-07-23 Thread AppVeyor 


Build mesa 11986 completed



Commit b1c35fa6d6 by Eric Engestrom on 7/19/2019 9:13 PM:

st/nir: use asprintf() wrapper to fix MSVC issues\n\nFixes: 856e84083eee9b22408a ("mesa/st: add sampler uniforms")\nSigned-off-by: Eric Engestrom \nReviewed-by: Eric Anholt 


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Re: [Mesa-dev] [PATCH] radv: fix dumping disassembly with RADV_DEBUG=shaders

2019-07-23 Thread Bas Nieuwenhuizen 
r-b

On Tue, Jul 23, 2019 at 9:51 AM Samuel Pitoiset
 wrote:
>
> Fixes: a20a9d0c5e7 ("radv: dont store disasm string unless keep_shader_info 
> flag set")
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_shader.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 3adaf52e152..736388c555c 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -1013,7 +1013,8 @@ radv_shader_variant_create(struct radv_device *device,
> return NULL;
> }
>
> -   if (device->keep_shader_info) {
> +   if (device->keep_shader_info ||
> +   (device->instance->debug_flags & 
> RADV_DEBUG_DUMP_SHADERS)) {
> const char *disasm_data;
> size_t disasm_size;
> if (!ac_rtld_get_section_by_name(_binary, 
> ".AMDGPU.disasm", _data, _size)) {
> --
> 2.22.0
>
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[Mesa-dev] [PATCH] radv: fix dumping disassembly with RADV_DEBUG=shaders

2019-07-23 Thread Samuel Pitoiset 
Fixes: a20a9d0c5e7 ("radv: dont store disasm string unless keep_shader_info 
flag set")
Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_shader.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 3adaf52e152..736388c555c 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1013,7 +1013,8 @@ radv_shader_variant_create(struct radv_device *device,
return NULL;
}
 
-   if (device->keep_shader_info) {
+   if (device->keep_shader_info ||
+   (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
const char *disasm_data;
size_t disasm_size;
if (!ac_rtld_get_section_by_name(_binary, 
".AMDGPU.disasm", _data, _size)) {
-- 
2.22.0

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[Mesa-dev] [PATCH] radv/gfx10: enable CLEAR_state

2019-07-23 Thread Samuel Pitoiset 
It actually works.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_device.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 992e12840f7..93b03afda22 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -354,8 +354,7 @@ radv_physical_device_init(struct radv_physical_device 
*device,
/* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
 * on GFX6.
 */
-   device->has_clear_state = device->rad_info.chip_class >= GFX7 &&
- device->rad_info.chip_class <= GFX9;
+   device->has_clear_state = device->rad_info.chip_class >= GFX7;
 
device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= 
GFX8;
 
-- 
2.22.0

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