[Mesa-dev] [AppVeyor] mesa-webhook master #15068 failed
Build mesa-webhook 15068 failed Commit e609737526 by Marek Olšák on 3/20/2020 9:34 PM: radeonsi/gfx10: fix descriptors and compute registers for compute-based culling\n\nAcked-by: Pierre-Eric Pelloux-Prayer \nTested-by: Marge Bot \nPart-of: Configure your notification preferences ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [AppVeyor] mesa-webhook master #15063 completed
Build mesa-webhook 15063 completed Commit 6cfe074b86 by Jesse Natalie on 3/17/2020 5:53 PM: wgl: use gldrv.h instead of stw_icd.h\n\nNow that we have the official header, let's use that instead of\nstw_icd.h.\n\nReviewed-by: Jose Fonseca \nTested-by: Marge Bot \nPart-of: Configure your notification preferences ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [AppVeyor] mesa-webhook master #15062 failed
Build mesa-webhook 15062 failed Commit c9091f1f24 by Karol Herbst on 9/20/2019 6:27 PM: nv50, nvc0: fix must_check warning of util_dynarray_resize_bytes\n\nSigned-off-by: Karol Herbst \nReviewed-by: Erik Faye-Lund \nTested-by: Marge Bot \nPart-of: Configure your notification preferences ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Drop scons for 20.1?
From: Michel Dänzer Sent: Friday, March 27, 2020 15:56 To: Jose Fonseca ; Marek Olšák Cc: Neha Bhende ; Kristian Høgsberg ; Dylan Baker ; mesa-dev Subject: Re: [Mesa-dev] Drop scons for 20.1? On 2020-03-27 2:29 p.m., Jose Fonseca wrote: > > If SCons is such a time sink, then the best we can do is suggest to > take it off Marge-bot. That would be something like https://nam04.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fmesa%2Fmesa%2F-%2Fmerge_requests%2F4352data=02%7C01%7Cjfonseca%40vmware.com%7C786cd1eeae684a45dd3a08d7d26766aa%7Cb39138ca3cee4b4aa4d6cd83d9dd62f0%7C0%7C0%7C637209213877300351sdata=c9OoEsfgpIGhwoewerL%2Fb7ZShTr9CVCtLJdcMPLoUVk%3Dreserved=0 then. Not quite what I had in mind (I suggested take it off Marge-bot, as opposed to take it off completely.) But lets continue the conversion in the MR. For the record I also did make a https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4348 for reducing the targets as suggested by Marek, which I'd like to get in first. > The onus of fixing SCons will go back to us, as it always did > throughout these the past twelve years. Not for the last year or so, when it's been part of the pre-merge CI pipeline? True. And while I don't recall asking SCons to be added to pre-merge CI (I certainly did not), I do appreciate the effort and grief this might have caused. Lets take it out. As tiring fixing SCons by ourselves might be, is still better than being constantly painted as the bad guys and constantly have to fend off requests to yank off SCons. Jose ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] Drop scons for 20.1?
On 2020-03-27 2:29 p.m., Jose Fonseca wrote: > > If SCons is such a time sink, then the best we can do is suggest to > take it off Marge-bot. That would be something like https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4352 then. > The onus of fixing SCons will go back to us, as it always did > throughout these the past twelve years. Not for the last year or so, when it's been part of the pre-merge CI pipeline? -- Earthling Michel Dänzer | https://redhat.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v3 3/8] nv50/ir: Add nv50_ir_prog_info_out serialize and deserialize
Adds functions for serializing and deserializing
nv50_ir_prog_info_out structure, which are needed for shader caching.
Signed-off-by: Mark Menzynski
---
.../drivers/nouveau/codegen/nv50_ir_driver.h | 44 +
.../nouveau/codegen/nv50_ir_emit_gk110.cpp| 14 +-
.../nouveau/codegen/nv50_ir_emit_gm107.cpp| 14 +-
.../nouveau/codegen/nv50_ir_emit_nv50.cpp | 6 +-
.../nouveau/codegen/nv50_ir_emit_nvc0.cpp | 14 +-
.../nouveau/codegen/nv50_ir_serialize.cpp | 185 ++
src/gallium/drivers/nouveau/meson.build | 1 +
7 files changed, 254 insertions(+), 24 deletions(-)
create mode 100644 src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index dab1ce030cb..591aa8f57e8 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -25,6 +25,7 @@
#include "pipe/p_shader_tokens.h"
+#include "util/blob.h"
#include "tgsi/tgsi_util.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_scan.h"
@@ -242,6 +243,49 @@ nv50_ir_apply_fixups(void *fixupData, uint32_t *code,
extern void nv50_ir_get_target_library(uint32_t chipset,
const uint32_t **code, uint32_t *size);
+
+#ifdef __cplusplus
+namespace nv50_ir
+{
+ class FixupEntry;
+ class FixupData;
+
+ void
+ gk110_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code,
+ const nv50_ir::FixupData& data);
+ void
+ gm107_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code,
+ const nv50_ir::FixupData& data);
+ void
+ nv50_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code,
+const nv50_ir::FixupData& data);
+ void
+ nvc0_interpApply(const nv50_ir::FixupEntry *entry, uint32_t *code,
+const nv50_ir::FixupData& data);
+ void
+ gk110_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code,
+ const nv50_ir::FixupData& data);
+ void
+ gm107_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code,
+ const nv50_ir::FixupData& data);
+ void
+ nvc0_selpFlip(const nv50_ir::FixupEntry *entry, uint32_t *code,
+ const nv50_ir::FixupData& data);
+
+}
+#endif
+
+/* Serialize a nv50_ir_prog_info_out structure and save it into blob */
+extern bool MUST_CHECK
+nv50_ir_prog_info_out_serialize(struct blob *, struct nv50_ir_prog_info_out *);
+
+/* Deserialize from data and save into a nv50_ir_prog_info_out structure
+ * using a pointer. Size is a total size of the serialized data.
+ * Offset points to where info_out in data is located. */
+extern bool MUST_CHECK
+nv50_ir_prog_info_out_deserialize(void *data, size_t size, size_t offset,
+ struct nv50_ir_prog_info_out *);
+
#ifdef __cplusplus
}
#endif
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index 2118c3153f7..e651d7fdcb0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -1209,8 +1209,8 @@ CodeEmitterGK110::emitSLCT(const CmpInstruction *i)
}
}
-static void
-selpFlip(const FixupEntry *entry, uint32_t *code, const FixupData& data)
+void
+gk110_selpFlip(const FixupEntry *entry, uint32_t *code, const FixupData& data)
{
int loc = entry->loc;
if (data.force_persample_interp)
@@ -1227,7 +1227,7 @@ void CodeEmitterGK110::emitSELP(const Instruction *i)
code[1] |= 1 << 13;
if (i->subOp == 1) {
- addInterp(0, 0, selpFlip);
+ addInterp(0, 0, gk110_selpFlip);
}
}
@@ -2042,8 +2042,8 @@ CodeEmitterGK110::emitInterpMode(const Instruction *i)
code[1] |= (i->ipa & 0xc) << (19 - 2);
}
-static void
-interpApply(const FixupEntry *entry, uint32_t *code, const FixupData& data)
+void
+gk110_interpApply(const struct FixupEntry *entry, uint32_t *code, const
FixupData& data)
{
int ipa = entry->ipa;
int reg = entry->reg;
@@ -2078,10 +2078,10 @@ CodeEmitterGK110::emitINTERP(const Instruction *i)
if (i->op == OP_PINTERP) {
srcId(i->src(1), 23);
- addInterp(i->ipa, SDATA(i->src(1)).id, interpApply);
+ addInterp(i->ipa, SDATA(i->src(1)).id, gk110_interpApply);
} else {
code[0] |= 0xff << 23;
- addInterp(i->ipa, 0xff, interpApply);
+ addInterp(i->ipa, 0xff, gk110_interpApply);
}
srcId(i->src(0).getIndirect(0), 10);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index e244bd0d610..4970f14cb33 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -947,8 +947,8 @@ CodeEmitterGM107::emitI2I()
emitGPR (0x00,
[Mesa-dev] [PATCH v3 8/8] nv50: Add shader disk caching
Adds shader disk caching for nv50 to reduce the need to every time compile
shaders. Shaders are saved into disk_shader_cache from nv50_screen structure.
It serializes the input nv50_ir_prog_info to compute the hash key and
also to do a byte compare between the original nv50_ir_prog_info and the one
saved in the cache. If keys match and also the byte compare returns they
are equal, shaders are same, and the compiled nv50_ir_prog_info_out from the
cache can be used instead of compiling input info.
Signed-off-by: Mark Menzynski
---
.../drivers/nouveau/nv50/nv50_program.c | 283 +++---
.../drivers/nouveau/nv50/nv50_program.h | 2 +
.../drivers/nouveau/nv50/nv50_shader_state.c | 4 +-
src/gallium/drivers/nouveau/nv50/nv50_state.c | 1 +
4 files changed, 54 insertions(+), 236 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index f4f2e951fd5..a03d5b9f6d0 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -37,108 +37,6 @@ bitcount4(const uint32_t val)
return cnt[val & 0xf];
}
-static int
-nv50_vertprog_assign_slots(struct nv50_ir_prog_info_out *info)
-{
- struct nv50_program *prog = (struct nv50_program *)info->driverPriv;
- unsigned i, n, c;
-
- n = 0;
- for (i = 0; i < info->numInputs; ++i) {
- prog->in[i].id = i;
- prog->in[i].sn = info->in[i].sn;
- prog->in[i].si = info->in[i].si;
- prog->in[i].hw = n;
- prog->in[i].mask = info->in[i].mask;
-
- prog->vp.attrs[(4 * i) / 32] |= info->in[i].mask << ((4 * i) % 32);
-
- for (c = 0; c < 4; ++c)
- if (info->in[i].mask & (1 << c))
-info->in[i].slot[c] = n++;
-
- if (info->in[i].sn == TGSI_SEMANTIC_PRIMID)
- prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_PRIMITIVE_ID;
- }
- prog->in_nr = info->numInputs;
-
- for (i = 0; i < info->numSysVals; ++i) {
- switch (info->sv[i].sn) {
- case TGSI_SEMANTIC_INSTANCEID:
- prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_INSTANCE_ID;
- continue;
- case TGSI_SEMANTIC_VERTEXID:
- prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID;
- prog->vp.attrs[2] |=
NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID_DRAW_ARRAYS_ADD_START;
- continue;
- default:
- break;
- }
- }
-
- /*
-* Corner case: VP has no inputs, but we will still need to submit data to
-* draw it. HW will shout at us and won't draw anything if we don't enable
-* any input, so let's just pretend it's the first one.
-*/
- if (prog->vp.attrs[0] == 0 &&
- prog->vp.attrs[1] == 0 &&
- prog->vp.attrs[2] == 0)
- prog->vp.attrs[0] |= 0xf;
-
- /* VertexID before InstanceID */
- if (info->io.vertexId < info->numSysVals)
- info->sv[info->io.vertexId].slot[0] = n++;
- if (info->io.instanceId < info->numSysVals)
- info->sv[info->io.instanceId].slot[0] = n++;
-
- n = 0;
- for (i = 0; i < info->numOutputs; ++i) {
- switch (info->out[i].sn) {
- case TGSI_SEMANTIC_PSIZE:
- prog->vp.psiz = i;
- break;
- case TGSI_SEMANTIC_CLIPDIST:
- prog->vp.clpd[info->out[i].si] = n;
- break;
- case TGSI_SEMANTIC_EDGEFLAG:
- prog->vp.edgeflag = i;
- break;
- case TGSI_SEMANTIC_BCOLOR:
- prog->vp.bfc[info->out[i].si] = i;
- break;
- case TGSI_SEMANTIC_LAYER:
- prog->gp.has_layer = true;
- prog->gp.layerid = n;
- break;
- case TGSI_SEMANTIC_VIEWPORT_INDEX:
- prog->gp.has_viewport = true;
- prog->gp.viewportid = n;
- break;
- default:
- break;
- }
- prog->out[i].id = i;
- prog->out[i].sn = info->out[i].sn;
- prog->out[i].si = info->out[i].si;
- prog->out[i].hw = n;
- prog->out[i].mask = info->out[i].mask;
-
- for (c = 0; c < 4; ++c)
- if (info->out[i].mask & (1 << c))
-info->out[i].slot[c] = n++;
- }
- prog->out_nr = info->numOutputs;
- prog->max_out = n;
- if (!prog->max_out)
- prog->max_out = 1;
-
- if (prog->vp.psiz < info->numOutputs)
- prog->vp.psiz = prog->out[prog->vp.psiz].hw;
-
- return 0;
-}
-
static int
nv50_vertprog_assign_slots_info(struct nv50_ir_prog_info_out *info)
{
@@ -263,115 +161,6 @@ nv50_vertprog_assign_slots_prog(struct
nv50_ir_prog_info_out *info)
return 0;
}
-static int
-nv50_fragprog_assign_slots(struct nv50_ir_prog_info_out *info)
-{
- struct nv50_program *prog = (struct nv50_program *)info->driverPriv;
- unsigned i, n, m, c;
- unsigned nvary;
- unsigned nflat;
- unsigned nintp = 0;
-
- /* count recorded non-flat inputs */
- for (m = 0, i = 0; i < info->numInputs; ++i) {
- switch (info->in[i].sn) {
- case TGSI_SEMANTIC_POSITION:
- continue;
- default:
- m += info->in[i].flat ? 0 : 1;
-
[Mesa-dev] [PATCH v3 7/8] nv50: Add separate functions for varying bits
This separation will be needed for shader disk caching. The reason for it
is that when loading shaders from cache, data in info structure already gets
loaded. That means varying bits for info is needed only when compiling
shaders and not needed when loading from cache. Varying bits for prog are
needed in both cases.
Unfortunately, I don't know how most of the code works, I have separated
this manually, only by looking at the original code. That means that this
patch is experimental. Together with following commit it works
(there seem to be no regressions at all in VK-GL-CTS
[openglcts/data/mustpass/gl/khronos_mustpass/4.6.1.x/gl33-master.txt]
and all benchmarks behaved normally). Unfortunately, I cannot test in
Piglit because of technical problems, so there might be still some
work needed.
I am mainly asking to help with the function names,
look for bugs and pointing out useless code. I will be glad for every
review.
Signed-off-by: Mark Menzynski
---
.../drivers/nouveau/nv50/nv50_program.c | 344 ++
1 file changed, 344 insertions(+)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index e36b8a0f8cc..f4f2e951fd5 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -139,6 +139,130 @@ nv50_vertprog_assign_slots(struct nv50_ir_prog_info_out
*info)
return 0;
}
+static int
+nv50_vertprog_assign_slots_info(struct nv50_ir_prog_info_out *info)
+{
+ unsigned i, n, c;
+
+ n = 0;
+ for (i = 0; i < info->numInputs; ++i) {
+ for (c = 0; c < 4; ++c)
+ if (info->in[i].mask & (1 << c))
+info->in[i].slot[c] = n++;
+ }
+
+ /* VertexID before InstanceID */
+ if (info->io.vertexId < info->numSysVals)
+ info->sv[info->io.vertexId].slot[0] = n++;
+ if (info->io.instanceId < info->numSysVals)
+ info->sv[info->io.instanceId].slot[0] = n++;
+
+ n = 0;
+ for (i = 0; i < info->numOutputs; ++i) {
+ for (c = 0; c < 4; ++c)
+ if (info->out[i].mask & (1 << c))
+info->out[i].slot[c] = n++;
+ }
+
+ return 0;
+}
+
+static int
+nv50_vertprog_assign_slots_prog(struct nv50_ir_prog_info_out *info)
+{
+ struct nv50_program *prog = (struct nv50_program *)info->driverPriv;
+ unsigned i, n, c;
+
+ n = 0;
+ for (i = 0; i < info->numInputs; ++i) {
+ prog->in[i].id = i;
+ prog->in[i].sn = info->in[i].sn;
+ prog->in[i].si = info->in[i].si;
+ prog->in[i].hw = n;
+ prog->in[i].mask = info->in[i].mask;
+
+ prog->vp.attrs[(4 * i) / 32] |= info->in[i].mask << ((4 * i) % 32);
+
+ for (c = 0; c < 4; ++c)
+ if (info->in[i].mask & (1 << c))
+n++;
+
+ if (info->in[i].sn == TGSI_SEMANTIC_PRIMID)
+ prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_PRIMITIVE_ID;
+ }
+ prog->in_nr = info->numInputs;
+
+ for (i = 0; i < info->numSysVals; ++i) {
+ switch (info->sv[i].sn) {
+ case TGSI_SEMANTIC_INSTANCEID:
+ prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_INSTANCE_ID;
+ continue;
+ case TGSI_SEMANTIC_VERTEXID:
+ prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID;
+ prog->vp.attrs[2] |=
NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID_DRAW_ARRAYS_ADD_START;
+ continue;
+ default:
+ break;
+ }
+ }
+
+ /*
+* Corner case: VP has no inputs, but we will still need to submit data to
+* draw it. HW will shout at us and won't draw anything if we don't enable
+* any input, so let's just pretend it's the first one.
+*/
+ if (prog->vp.attrs[0] == 0 &&
+ prog->vp.attrs[1] == 0 &&
+ prog->vp.attrs[2] == 0)
+ prog->vp.attrs[0] |= 0xf;
+
+ n = 0;
+ for (i = 0; i < info->numOutputs; ++i) {
+ switch (info->out[i].sn) {
+ case TGSI_SEMANTIC_PSIZE:
+ prog->vp.psiz = i;
+ break;
+ case TGSI_SEMANTIC_CLIPDIST:
+ prog->vp.clpd[info->out[i].si] = n;
+ break;
+ case TGSI_SEMANTIC_EDGEFLAG:
+ prog->vp.edgeflag = i;
+ break;
+ case TGSI_SEMANTIC_BCOLOR:
+ prog->vp.bfc[info->out[i].si] = i;
+ break;
+ case TGSI_SEMANTIC_LAYER:
+ prog->gp.has_layer = true;
+ prog->gp.layerid = n;
+ break;
+ case TGSI_SEMANTIC_VIEWPORT_INDEX:
+ prog->gp.has_viewport = true;
+ prog->gp.viewportid = n;
+ break;
+ default:
+ break;
+ }
+ prog->out[i].id = i;
+ prog->out[i].sn = info->out[i].sn;
+ prog->out[i].si = info->out[i].si;
+ prog->out[i].hw = n;
+ prog->out[i].mask = info->out[i].mask;
+
+ for (c = 0; c < 4; ++c)
+ if (info->out[i].mask & (1 << c))
+n++;
+ }
+ prog->out_nr = info->numOutputs;
+ prog->max_out = n;
+ if (!prog->max_out)
+ prog->max_out = 1;
+
+ if (prog->vp.psiz < info->numOutputs)
+ prog->vp.psiz =
[Mesa-dev] [PATCH v3 2/8] nv50/ir: add nv50_ir_prog_info_out
From: Karol Herbst
Split out the output relevant fields from the nv50_ir_prog_info struct
in order to have a cleaner separation between the input and output of
the compilation.
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir.cpp | 49 ++--
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 9 +-
.../drivers/nouveau/codegen/nv50_ir_driver.h | 117 +---
.../nouveau/codegen/nv50_ir_from_common.cpp | 14 +-
.../nouveau/codegen/nv50_ir_from_common.h | 3 +-
.../nouveau/codegen/nv50_ir_from_nir.cpp | 204 +++---
.../nouveau/codegen/nv50_ir_from_tgsi.cpp | 256 +-
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 6 +-
.../nouveau/codegen/nv50_ir_target.cpp| 2 +-
.../drivers/nouveau/codegen/nv50_ir_target.h | 5 +-
.../nouveau/codegen/nv50_ir_target_nv50.cpp | 17 +-
.../nouveau/codegen/nv50_ir_target_nv50.h | 3 +-
.../drivers/nouveau/nouveau_compiler.c| 9 +-
.../drivers/nouveau/nv50/nv50_program.c | 61 +++--
.../drivers/nouveau/nvc0/nvc0_program.c | 87 +++---
15 files changed, 448 insertions(+), 394 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
index c65853578f6..c2c5956874a 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
@@ -1241,15 +1241,18 @@ void Program::releaseValue(Value *value)
extern "C" {
static void
-nv50_ir_init_prog_info(struct nv50_ir_prog_info *info)
+nv50_ir_init_prog_info(struct nv50_ir_prog_info *info,
+ struct nv50_ir_prog_info_out *info_out)
{
+ info_out->target = info->target;
+ info_out->type = info->type;
if (info->type == PIPE_SHADER_TESS_CTRL || info->type ==
PIPE_SHADER_TESS_EVAL) {
- info->prop.tp.domain = PIPE_PRIM_MAX;
- info->prop.tp.outputPrim = PIPE_PRIM_MAX;
+ info_out->prop.tp.domain = PIPE_PRIM_MAX;
+ info_out->prop.tp.outputPrim = PIPE_PRIM_MAX;
}
if (info->type == PIPE_SHADER_GEOMETRY) {
- info->prop.gp.instanceCount = 1;
- info->prop.gp.maxVertices = 1;
+ info_out->prop.gp.instanceCount = 1;
+ info_out->prop.gp.maxVertices = 1;
}
if (info->type == PIPE_SHADER_COMPUTE) {
info->prop.cp.numThreads[0] =
@@ -1257,23 +1260,26 @@ nv50_ir_init_prog_info(struct nv50_ir_prog_info *info)
info->prop.cp.numThreads[2] = 1;
}
info->io.pointSize = 0xff;
- info->io.instanceId = 0xff;
- info->io.vertexId = 0xff;
- info->io.edgeFlagIn = 0xff;
- info->io.edgeFlagOut = 0xff;
- info->io.fragDepth = 0xff;
- info->io.sampleMask = 0xff;
+ info_out->bin.smemSize = info->bin.smemSize;
+ info_out->io.genUserClip = info->io.genUserClip;
+ info_out->io.instanceId = 0xff;
+ info_out->io.vertexId = 0xff;
+ info_out->io.edgeFlagIn = 0xff;
+ info_out->io.edgeFlagOut = 0xff;
+ info_out->io.fragDepth = 0xff;
+ info_out->io.sampleMask = 0xff;
info->io.backFaceColor[0] = info->io.backFaceColor[1] = 0xff;
}
int
-nv50_ir_generate_code(struct nv50_ir_prog_info *info)
+nv50_ir_generate_code(struct nv50_ir_prog_info *info,
+ struct nv50_ir_prog_info_out *info_out)
{
int ret = 0;
nv50_ir::Program::Type type;
- nv50_ir_init_prog_info(info);
+ nv50_ir_init_prog_info(info, info_out);
#define PROG_TYPE_CASE(a, b) \
case PIPE_SHADER_##a: type = nv50_ir::Program::TYPE_##b; break
@@ -1301,15 +1307,16 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info)
return -1;
}
prog->driver = info;
+ prog->driver_out = info_out;
prog->dbgFlags = info->dbgFlags;
prog->optLevel = info->optLevel;
switch (info->bin.sourceRep) {
case PIPE_SHADER_IR_NIR:
- ret = prog->makeFromNIR(info) ? 0 : -2;
+ ret = prog->makeFromNIR(info, info_out) ? 0 : -2;
break;
case PIPE_SHADER_IR_TGSI:
- ret = prog->makeFromTGSI(info) ? 0 : -2;
+ ret = prog->makeFromTGSI(info, info_out) ? 0 : -2;
break;
default:
ret = -1;
@@ -1320,7 +1327,7 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info)
if (prog->dbgFlags & NV50_IR_DEBUG_VERBOSE)
prog->print();
- targ->parseDriverInfo(info);
+ targ->parseDriverInfo(info, info_out);
prog->getTarget()->runLegalizePass(prog, nv50_ir::CG_STAGE_PRE_SSA);
prog->convertToSSA();
@@ -1342,7 +1349,7 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info)
prog->optimizePostRA(info->optLevel);
- if (!prog->emitBinary(info)) {
+ if (!prog->emitBinary(info_out)) {
ret = -5;
goto out;
}
@@ -1350,10 +1357,10 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info)
out:
INFO_DBG(prog->dbgFlags, VERBOSE, "nv50_ir_generate_code: ret = %i\n", ret);
- info->bin.maxGPR = prog->maxGPR;
- info->bin.code = prog->code;
- info->bin.codeSize = prog->binSize;
- info->bin.tlsSpace =
[Mesa-dev] [PATCH v3 5/8] nv50/ir: Add nv50_ir_prog_info serialize
Adds a function for serializing a nv50_ir_prog_info structure, which is
needed for shader caching.
Signed-off-by: Mark Menzynski
---
.../drivers/nouveau/codegen/nv50_ir_driver.h | 4 ++
.../nouveau/codegen/nv50_ir_serialize.cpp | 42 +++
2 files changed, 46 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 1bfaa8483ca..d33c6b6b83c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -278,6 +278,10 @@ namespace nv50_ir
extern void
nv50_ir_prog_info_out_print(struct nv50_ir_prog_info_out *);
+/* Serialize a nv50_ir_prog_info structure and save it into blob */
+extern bool
+nv50_ir_prog_info_serialize(struct blob *, struct nv50_ir_prog_info *);
+
/* Serialize a nv50_ir_prog_info_out structure and save it into blob */
extern bool MUST_CHECK
nv50_ir_prog_info_out_serialize(struct blob *, struct nv50_ir_prog_info_out *);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp
index 52ceb66947f..e9d1d0b3215 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_serialize.cpp
@@ -16,6 +16,48 @@ enum FixupApplyFunc {
FLIP_GM107
};
+extern bool
+nv50_ir_prog_info_serialize(struct blob *blob, struct nv50_ir_prog_info *info)
+{
+ blob_write_uint16(blob, info->target);
+ blob_write_uint8(blob, info->type);
+ blob_write_uint8(blob, info->optLevel);
+ blob_write_uint8(blob, info->dbgFlags);
+ blob_write_uint8(blob, info->omitLineNum);
+ blob_write_uint32(blob, info->bin.smemSize);
+ blob_write_uint16(blob, info->bin.maxOutput);
+ blob_write_uint8(blob, info->bin.sourceRep);
+
+ switch(info->bin.sourceRep) {
+ case PIPE_SHADER_IR_TGSI: {
+ struct tgsi_token *tokens = (struct tgsi_token *)info->bin.source;
+ unsigned int num_tokens = tgsi_num_tokens(tokens);
+
+ blob_write_uint32(blob, num_tokens);
+ blob_write_bytes(blob, tokens, num_tokens * sizeof(struct
tgsi_token));
+ break;
+ }
+ case PIPE_SHADER_IR_NIR: {
+ struct nir_shader *nir = (struct nir_shader *)info->bin.source;
+ nir_serialize(blob, nir, false);
+ break;
+ }
+ default:
+ assert(!"unhandled info->bin.sourceRep switch case");
+ return false;
+ }
+
+ blob_write_uint16(blob, info->immd.bufSize);
+ blob_write_bytes(blob, info->immd.buf, info->immd.bufSize *
sizeof(*info->immd.buf));
+ blob_write_uint16(blob, info->immd.count);
+ blob_write_bytes(blob, info->immd.data, info->immd.count *
sizeof(*info->immd.data));
+ blob_write_bytes(blob, info->immd.type, info->immd.count * 16); // for each
vec4 (128 bit)
+ blob_write_bytes(blob, >prop, sizeof(info->prop));
+ blob_write_bytes(blob, >io, sizeof(info->io));
+
+ return true;
+}
+
extern bool
nv50_ir_prog_info_out_serialize(struct blob *blob,
struct nv50_ir_prog_info_out *info_out)
--
2.24.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v3 6/8] nvc0: Add shader disk caching
Adds shader disk caching for nvc0 to reduce the need to every time compile
shaders. Shaders are saved into disk_shader_cache from nvc0_screen structure.
It serializes the input nv50_ir_prog_info to compute the hash key and
also to do a byte compare between the original nv50_ir_prog_info and the one
saved in the cache. If keys match and also the byte compare returns they
are equal, shaders are same, and the compiled nv50_ir_prog_info_out from the
cache can be used instead of compiling input info.
Seems to be significantly improving loading times, these are the results
from running bunch of shaders:
cache off
real2m58.574s
user21m34.018s
sys 0m8.055s
cache on, first run
real3m32.617s
user24m52.701s
sys 0m20.400s
cache on, second run
real0m23.745s
user2m43.566s
sys 0m4.532s
Signed-off-by: Mark Menzynski
---
.../drivers/nouveau/nvc0/nvc0_context.h | 1 +
.../drivers/nouveau/nvc0/nvc0_program.c | 51 +--
.../drivers/nouveau/nvc0/nvc0_shader_state.c | 3 +-
src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 2 +
4 files changed, 51 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index 8a2a8f2797e..4b83d1afeb4 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -321,6 +321,7 @@ extern struct draw_stage *nvc0_draw_render_stage(struct
nvc0_context *);
/* nvc0_program.c */
bool nvc0_program_translate(struct nvc0_program *, uint16_t chipset,
+struct disk_cache *,
struct pipe_debug_callback *);
bool nvc0_program_upload(struct nvc0_context *, struct nvc0_program *);
void nvc0_program_destroy(struct nvc0_context *, struct nvc0_program *);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 7f32dc941d6..50430931194 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -24,6 +24,7 @@
#include "compiler/nir/nir.h"
#include "tgsi/tgsi_ureg.h"
+#include "util/blob.h"
#include "nvc0/nvc0_context.h"
@@ -568,11 +569,18 @@ nvc0_program_dump(struct nvc0_program *prog)
bool
nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
+ struct disk_cache *disk_shader_cache,
struct pipe_debug_callback *debug)
{
+ struct blob blob;
struct nv50_ir_prog_info *info;
struct nv50_ir_prog_info_out info_out = {};
- int ret;
+
+
+
+ int ret = 0;
+ cache_key key;
+ bool shader_found = false;
info = CALLOC_STRUCT(nv50_ir_prog_info);
if (!info)
@@ -632,11 +640,44 @@ nvc0_program_translate(struct nvc0_program *prog,
uint16_t chipset,
info->bin.smemSize = prog->cp.smem_size;
info->io.genUserClip = prog->vp.num_ucps;
- ret = nv50_ir_generate_code(info, _out);
- if (ret) {
- NOUVEAU_ERR("shader translation failed: %i\n", ret);
- goto out;
+ blob_init();
+
+ if (disk_shader_cache) {
+ void *cached_data = NULL;
+ size_t cached_size;
+
+ nv50_ir_prog_info_serialize(, info);
+ disk_cache_compute_key(disk_shader_cache, blob.data, blob.size, key);
+ cached_data = disk_cache_get(disk_shader_cache, key, _size);
+
+ if (cached_data && cached_size >= blob.size) { // blob.size is the size
of serialized "info"
+ if (memcmp(cached_data, blob.data, blob.size) == 0) {
+shader_found = true;
+/* Blob contains only "info". In disk cache, "info_out" comes
right after it */
+size_t offset = blob.size;
+if (!nv50_ir_prog_info_out_deserialize(cached_data, cached_size,
offset, _out)) {
+ NOUVEAU_ERR("shader deserialization failed:\n");
+ goto out;
+}
+ }
+ }
+ free(cached_data);
+ }
+ if (!shader_found) {
+ ret = nv50_ir_generate_code(info, _out);
+ if (ret) {
+ NOUVEAU_ERR("shader translation failed: %i\n", ret);
+ goto out;
+ }
+ if (disk_shader_cache) {
+ if (!nv50_ir_prog_info_out_serialize(, _out)) {
+NOUVEAU_ERR("shader serialization failed:\n");
+goto out;
+ }
+ disk_cache_put(disk_shader_cache, key, blob.data, blob.size, NULL);
+ }
}
+ blob_finish();
prog->code = info_out.bin.code;
prog->code_size = info_out.bin.codeSize;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
index 774c5648113..4327a89454b 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
@@ -54,7 +54,8 @@ nvc0_program_validate(struct nvc0_context *nvc0, struct
nvc0_program *prog)
if (!prog->translated) {
prog->translated = nvc0_program_translate(
-
[Mesa-dev] [PATCH v3 4/8] nv50/ir: Add prog_info_out print
Adds a function for printing nv50_ir_prog_info_out structure
in JSON-like format, which could be used in debugging.
Signed-off-by: Mark Menzynski
---
.../drivers/nouveau/codegen/nv50_ir_driver.h | 3 +
.../drivers/nouveau/codegen/nv50_ir_print.cpp | 154 ++
2 files changed, 157 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 591aa8f57e8..1bfaa8483ca 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -275,6 +275,9 @@ namespace nv50_ir
}
#endif
+extern void
+nv50_ir_prog_info_out_print(struct nv50_ir_prog_info_out *);
+
/* Serialize a nv50_ir_prog_info_out structure and save it into blob */
extern bool MUST_CHECK
nv50_ir_prog_info_out_serialize(struct blob *, struct nv50_ir_prog_info_out *);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index 5dcbf3c3e0c..2c13bef5e1a 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
@@ -22,6 +22,7 @@
#include "codegen/nv50_ir.h"
#include "codegen/nv50_ir_target.h"
+#include "codegen/nv50_ir_driver.h"
#include
@@ -852,3 +853,156 @@ Function::printLiveIntervals() const
}
} // namespace nv50_ir
+
+extern void
+nv50_ir_prog_info_out_print(struct nv50_ir_prog_info_out *info_out)
+{
+ int i;
+
+ INFO("{\n");
+ INFO(" \"target\":\"%d\",\n", info_out->target);
+ INFO(" \"type\":\"%d\",\n", info_out->type);
+
+ // Bin
+ INFO(" \"bin\":{\n");
+ INFO(" \"maxGPR\":\"%d\",\n", info_out->bin.maxGPR);
+ INFO(" \"tlsSpace\":\"%d\",\n", info_out->bin.tlsSpace);
+ INFO(" \"smemSize\":\"%d\",\n", info_out->bin.smemSize);
+ INFO(" \"codeSize\":\"%d\",\n", info_out->bin.codeSize);
+ INFO(" \"instructions\":\"%d\",\n", info_out->bin.instructions);
+
+ // RelocInfo
+ INFO(" \"RelocInfo\":");
+ if (!info_out->bin.relocData) {
+ INFO("\"NULL\",\n");
+ } else {
+ nv50_ir::RelocInfo *reloc = (nv50_ir::RelocInfo
*)info_out->bin.relocData;
+ INFO("{\n");
+ INFO(" \"codePos\":\"%d\",\n", reloc->codePos);
+ INFO(" \"libPos\":\"%d\",\n", reloc->libPos);
+ INFO(" \"dataPos\":\"%d\",\n", reloc->dataPos);
+ INFO(" \"count\":\"%d\",\n", reloc->count);
+ INFO(" \"RelocEntry\":[\n");
+ for (unsigned int i = 0; i < reloc->count; i++) {
+ INFO("
{\"data\":\"%d\",\t\"mask\":\"%d\",\t\"offset\":\"%d\",\t\"bitPos\":\"%d\",\t\"type\":\"%d\"}",
+ reloc->entry[i].data, reloc->entry[i].mask,
reloc->entry[i].offset, reloc->entry[i].bitPos, reloc->entry[i].type
+ );
+ }
+ INFO("\n");
+ INFO(" ]\n");
+ INFO(" },\n");
+ }
+
+ // FixupInfo
+ INFO(" \"FixupInfo\":");
+ if (!info_out->bin.fixupData) {
+ INFO("\"NULL\"\n");
+ } else {
+ nv50_ir::FixupInfo *fixup = (nv50_ir::FixupInfo
*)info_out->bin.fixupData;
+ INFO("{\n");
+ INFO(" \"count\":\"%d\"\n", fixup->count);
+ INFO(" \"FixupEntry\":[\n");
+ for (unsigned int i = 0; i < fixup->count; i++) {
+ INFO("
{\"apply\":\"%p\",\t\"ipa\":\"%d\",\t\"reg\":\"%d\",\t\"loc\":\"%d\"}\n",
+ fixup->entry[i].apply, fixup->entry[i].ipa,
fixup->entry[i].reg, fixup->entry[i].loc);
+ }
+ INFO("\n");
+ INFO(" ]\n");
+ INFO(" }\n");
+
+ INFO(" },\n");
+ }
+
+ if (info_out->numSysVals) {
+ INFO(" \"sv\":[\n");
+ for (i = 0; i < info_out->numSysVals; i++) {
+ if (&(info_out->sv[i])) {
+INFO(" {\"id\":\"%d\", \"sn\":\"%d\", \"si\":\"%d\"}\n",
+ info_out->sv[i].id, info_out->sv[i].sn, info_out->sv[i].si);
+ }
+ }
+ INFO("\n ],\n");
+ }
+ if (info_out->numInputs) {
+ INFO(" \"in\":[\n");
+ for (i = 0; i < info_out->numInputs; i++) {
+ if (&(info_out->in[i])) {
+INFO(" {\"id\":\"%d\",\t\"sn\":\"%d\",\t\"si\":\"%d\"}\n",
+info_out->in[i].id, info_out->in[i].sn, info_out->in[i].si);
+ }
+ }
+ INFO("\n ],\n");
+ }
+ if (info_out->numOutputs) {
+ INFO(" \"out\":[\n");
+ for (i = 0; i < info_out->numOutputs; i++) {
+ if (&(info_out->out[i])) {
+INFO(" {\"id\":\"%d\",\t\"sn\":\"%d\",\t\"si\":\"%d\"}\n",
+ info_out->out[i].id, info_out->out[i].sn,
info_out->out[i].si);
+ }
+ }
+ INFO("\n ],\n");
+ }
+
+ INFO(" \"numInputs\":\"%d\",\n", info_out->numInputs);
+ INFO(" \"numOutputs\":\"%d\",\n", info_out->numOutputs);
+ INFO(" \"numPatchConstants\":\"%d\",\n", info_out->numPatchConstants);
+ INFO("
[Mesa-dev] [PATCH v3 1/8] nv50/ir: remove symbol table support for compute shaders
From: Karol Herbst
The initial plan was to use this for OpenCL kernels, but back then the
plan was to convert from LLVM to TGSI. As it turns out, we didn't went
that way.
Right now for OpenCL we don't reqiure supporting multiple entry points
inside the same binary and if we want to support it later, we can add
this back.
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 2 --
.../drivers/nouveau/codegen/nv50_ir_driver.h | 2 --
.../nouveau/codegen/nv50_ir_target.cpp| 23 ---
.../drivers/nouveau/nv50/nv50_compute.c | 17 +-
.../drivers/nouveau/nv50/nv50_program.c | 10
.../drivers/nouveau/nv50/nv50_program.h | 2 --
.../drivers/nouveau/nvc0/nvc0_compute.c | 2 +-
.../drivers/nouveau/nvc0/nvc0_context.h | 2 --
.../drivers/nouveau/nvc0/nvc0_program.c | 21 -
.../drivers/nouveau/nvc0/nvc0_program.h | 2 --
.../drivers/nouveau/nvc0/nve4_compute.c | 4 ++--
11 files changed, 4 insertions(+), 83 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 296b79f5d49..d2200fc4ea9 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -1297,8 +1297,6 @@ public:
const Target *getTarget() const { return target; }
private:
- void emitSymbolTable(struct nv50_ir_prog_info *);
-
Type progType;
Target *target;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 322bdd02557..55cc4c609f0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -97,8 +97,6 @@ struct nv50_ir_prog_info
const void *source;
void *relocData;
void *fixupData;
- struct nv50_ir_prog_symbol *syms;
- uint16_t numSyms;
} bin;
struct nv50_ir_varying sv[PIPE_MAX_SHADER_INPUTS];
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
index 5c6d0570ae2..0af79e9d50a 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
@@ -343,27 +343,6 @@ CodeEmitter::prepareEmission(BasicBlock *bb)
func->binSize += bb->binSize;
}
-void
-Program::emitSymbolTable(struct nv50_ir_prog_info *info)
-{
- unsigned int n = 0, nMax = allFuncs.getSize();
-
- info->bin.syms =
- (struct nv50_ir_prog_symbol *)MALLOC(nMax * sizeof(*info->bin.syms));
-
- for (ArrayList::Iterator fi = allFuncs.iterator();
-!fi.end();
-fi.next(), ++n) {
- Function *f = (Function *)fi.get();
- assert(n < nMax);
-
- info->bin.syms[n].label = f->getLabel();
- info->bin.syms[n].offset = f->binPos;
- }
-
- info->bin.numSyms = n;
-}
-
bool
Program::emitBinary(struct nv50_ir_prog_info *info)
{
@@ -403,8 +382,6 @@ Program::emitBinary(struct nv50_ir_prog_info *info)
info->bin.relocData = emit->getRelocInfo();
info->bin.fixupData = emit->getFixupInfo();
- emitSymbolTable(info);
-
// the nvc0 driver will print the binary iself together with the header
if ((dbgFlags & NV50_IR_DEBUG_BASIC) && getTarget()->getChipset() < 0xc0)
emit->printBinary();
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_compute.c
b/src/gallium/drivers/nouveau/nv50/nv50_compute.c
index d781f6fd7d4..1a78a371405 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_compute.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_compute.c
@@ -225,21 +225,6 @@ nv50_compute_upload_input(struct nv50_context *nv50, const
uint32_t *input)
}
}
-static uint32_t
-nv50_compute_find_symbol(struct nv50_context *nv50, uint32_t label)
-{
- struct nv50_program *prog = nv50->compprog;
- const struct nv50_ir_prog_symbol *syms =
- (const struct nv50_ir_prog_symbol *)prog->cp.syms;
- unsigned i;
-
- for (i = 0; i < prog->cp.num_syms; ++i) {
- if (syms[i].label == label)
- return prog->code_base + syms[i].offset;
- }
- return prog->code_base; /* no symbols or symbol not found */
-}
-
void
nv50_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
{
@@ -258,7 +243,7 @@ nv50_launch_grid(struct pipe_context *pipe, const struct
pipe_grid_info *info)
nv50_compute_upload_input(nv50, info->input);
BEGIN_NV04(push, NV50_CP(CP_START_ID), 1);
- PUSH_DATA (push, nv50_compute_find_symbol(nv50, info->pc));
+ PUSH_DATA (push, cp->code_base);
BEGIN_NV04(push, NV50_CP(SHARED_SIZE), 1);
PUSH_DATA (push, align(cp->cp.smem_size + cp->parm_size + 0x10, 0x40));
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index c9d01e8cee7..58c0463f1a2 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++
Re: [Mesa-dev] Drop scons for 20.1?
In the long term we should reduce the complexity of the project. scons is a
maintenance burden.
We all agree here. And we are making progress. Even a couple of weeks ago I
had to debug and fix weird Meson behaviour --
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4186
Every time I break the scons build and the CI reports it, can I politely ask
you to fix my MR instead of me doing it? Then at least the real maintenance
cost would be known to scons supporters, instead of the cost being invisible to
most.
Sure. But first I want all the time back I spent fixing scons and msvc builds
when the cost was invisible to most. Even after setting up Appveyor people
ignored the successive build failures. Even when fix was plain trivial and
easily avoidable (like replacing non-standard `= {}` initializers for `= { 0
}`). Even when I politely asked to fix it, people ignored. Not you perhaps,
but several did.
Honestly, why do you blame me/us? Mesa had multiple build systems for all its
life -- all with different state of brokenness. What really changed these
days is not actually the Meson-holy-grail, but this new Marge-bot overlord.
Personally I find it this new process a tad too draconian.
If SCons is such a time sink, then the best we can do is suggest to take it off
Marge-bot. The onus of fixing SCons will go back to us, as it always did
throughout these the past twelve years.
BTW, the grief you and others might be experiencing now, is probably 1/100th of
what we systematically had throughout these years. I particularly recall all
the pain and grief to replicate all the autoconf build logic for code
generation every time there was a major addition / refactoring in Mesa -- in
particular all those Python scripts that generated C code are very difficult to
match, because unlike Autoconf, SCons had fined grained dependencies, so
missing one dependency meant incremental builds would use stale source code.
Some times there were more broken builds that good ones. Even git-bisecting
was extremely had as result. Though to be fair, I do recall I also moaned and
bitch about it too.
In the mean time, I think we can remove all parts of scons that VMWare does NOT
care about. Do you need haiku-softpipe? Do you need graw-null? Do you need swr?
glx? There is bunch you don't really need on Windows.
Now that is a more serious proposal. An excellent one in fact.
The only scons targets we need are libgl-gdi (and its dependencies, including
llvmpipe) and svga.
Everything else can go as far as we are concerned. graw was useful at one
point, but I don't think it's that useful anymore. Regarding haiku-softpipe
and swr targets, they were not added to SCons by VMware. I suppose if the
stakeholders didn't speak up so far, one can assume they don't care.
Jose
From: Marek Olšák
Sent: Friday, March 27, 2020 00:56
To: Jose Fonseca
Cc: Jason Ekstrand ; Rob Clark ;
Kristian Høgsberg ; mesa-dev
; Dylan Baker
Subject: Re: [Mesa-dev] Drop scons for 20.1?
In the long term we should reduce the complexity of the project. scons is a
maintenance burden. Every time I break the scons build and the CI reports it,
can I politely ask you to fix my MR instead of me doing it? Then at least the
real maintenance cost would be known to scons supporters, instead of the cost
being invisible to most.
In the mean time, I think we can remove all parts of scons that VMWare does NOT
care about. Do you need haiku-softpipe? Do you need graw-null? Do you need swr?
glx? There is bunch you don't really need on Windows.
Marek
On Wed, Feb 26, 2020 at 3:44 PM Jose Fonseca
mailto:jfons...@vmware.com>> wrote:
We already solved some pieces (e.g, how to consume and use Meson, while
following our internal legal process required for adding new 3rd party
dependencies), and figured a way to consume Meson build without having to
migrate lots of internal build logic from Scons to Meson. But other stuff just
keeps getting higher priority, and we haven't fully migrated.
Please do understand, SCons just works for us. We are making progress with
Meson. It's just not the highest priority, when time is short, it gets
deferred.
I don't understand the rush. If it was trivial and easy we'd obviously would
have done it.
Jose
From: Jason Ekstrand mailto:ja...@jlekstrand.net>>
Sent: Wednesday, February 26, 2020 04:15
To: Rob Clark mailto:robdcl...@gmail.com>>; Kristian
Høgsberg mailto:hoegsb...@gmail.com>>
Cc: mesa-dev
mailto:mesa-dev@lists.freedesktop.org>>; Dylan
Baker mailto:baker.dyla...@gmail.com>>; Jose Fonseca
mailto:jfons...@vmware.com>>; Brian Paul
mailto:bri...@vmware.com>>
Subject: Re: [Mesa-dev] Drop scons for 20.1?
+Jose & Brian
I'm not personally opposed but I also can't remember the last time I had to
fix the scons build. I think it's been years. Maybe that's because I don't
work on GL anymore? In any case, I don't
