[Mesa-dev] [ANNOUNCE] mesa 20.0.3
Hi all, I'd like to announce the release of Mesa 20.0.3. Quite a busy cycle again, with fixes all over the tree, but nothing extraordinary; mostly AMD (radv, aco), NIR and Intel (isl, anv), as expected. Cheers, Eric --- Git shortlog Caio Marcelo de Oliveira Filho (1): mesa/main: Fix overflow in validation of DispatchComputeGroupSizeARB Dylan Baker (6): docs/relnotes: Add sha256 sums for 20.0.2 .pick_status.json: Update to cf62c2b2ac69637785f55b790fdd601c17e7e9d5 .pick_status.json: Mark 672d10619980687acec329742f055f7f3796c1b8 as backported .pick_status.json: Mark c923de68dd0ab10a5a5fb3196f539707d046d897 as backported .pick_status.json: Mark 56de6f698e3f164d97f132203e8159ef0b8e9bb8 as denominated .pick_status.json: Update to aee004a7c8900938d1c17f0ac299d40001b383b0 Eric Engestrom (8): .pick_status.json: Update to 3252041a7872c49e53bb02ffe8b079b5fc43f15e .pick_status.json: Update to 12711939320e4fcd3a0d86af22da1042ad92035f .pick_status.json: Update to 05069e1f0794aadd40ce9269f858e50c64254388 .pick_status.json: Update to 8970b7839aebefa7207c9535ac34ab4e8cc0ae25 .pick_status.json: Update to 5f4d9b419a1c931ad468b8b22b8a95b1216891e4 .pick_status.json: Update to 70ac7f5b0c46370075a35067c9f7dfe78e84b16d docs: add release notes for 20.0.3 VERSION: bump to 20.0.3 Erik Faye-Lund (3): rbug: do not return void-value pipebuffer: clean up cast-warnings vtn/opencl: fully enable OpenCLstd_Clz Francisco Jerez (1): intel/fs/gen12: Fix interaction of SWSB dependency combination with EU fusion workaround. Greg V (1): amd/addrlib: fix build on non-x86 platforms Ian Romanick (2): soft-fp64/fsat: Correctly handle NaN soft-fp64: Split a block that was missing a cast on a comparison Jason Ekstrand (5): intel/blorp: Add support for swizzling fast-clear colors anv: Swizzle fast-clear values nir/lower_int64: Lower 8 and 16-bit downcasts with nir_lower_mov64 anv: Account for the header in anv_state_stream_alloc spirv: Implement OpCopyObject and OpCopyLogical as blind copies John Stultz (2): gallium: hud_context: Fix scalar initializer warning. vc4_bufmgr: Remove duplicative VC definition Jordan Justen (2): intel: Update TGL PCI strings intel: Add TGL PCI ID Lionel Landwerlin (5): isl: implement linear tiling row pitch requirement for display isl: properly filter supported display modifiers on Gen9+ isl: only apply main surface ccs pitch constraint with CCS isl: drop min row pitch alignment when set by the driver intel: add new TGL pci ids Marek Olšák (3): nir: fix clip/cull_distance_array_size in nir_lower_clip_cull_distance_arrays ac: fix fast division st/mesa: fix use of uninitialized memory due to st_nir_lower_builtin Marek Vasut (1): etnaviv: Emit PE.ALPHA_COLOR_EXT* on GPUs with half-float support Neil Armstrong (1): Revert "ci: Remove T820 from CI temporarily" Pierre-Eric Pelloux-Prayer (1): st/mesa: disallow deferred flush if there are multiple contexts Rhys Perry (11): nir/gather_info: handle emit_vertex_with_counter aco: set has_divergent_branch for discards in loops aco: handle missing second predecessors at merge block phis aco: skip NIR in unreachable merge blocks aco: improve check for unreachable loop continue blocks aco: emit IR in IF's merge block instead if the other side ends in a jump aco: fix boolean undef regclass nir/gather_info: fix per-vertex handling in try_mask_partial_io aco: implement 64-bit VGPR constant copies in handle_operands() glsl: fix race in instance getters util/u_queue: fix race in total_jobs_size access Rob Clark (2): freedreno/ir3/ra: fix array liveranges util: fix u_fifo_pop() Samuel Pitoiset (7): radv/gfx10: fix required subgroup size with VK_EXT_subgroup_size_control radv/gfx10: fix required ballot size with VK_EXT_subgroup_size_control radv: fix optional pSizes parameter when binding streamout buffers radv: enable VK_KHR_8bit_storage on GFX6-GFX7 ac/nir: use llvm.amdgcn.rcp for nir_op_frcp ac/nir: use llvm.amdgcn.rsq for nir_op_frsq ac/nir: use llvm.amdgcn.rcp in ac_build_fdiv() Tapani Pälli (1): glsl: set error_emitted true if type not ok for assignment Thomas Hellstrom (1): svga, winsys/svga: Fix persistent memory discard maps Timothy Arceri (3): glsl: fix varying packing for 64bit integers nir: fix packing of TCS varyings not read by the TES nir: fix crash in varying packing on interface mismatch Timur Kristóf (1): radv/llvm: fix subgroup shuffle for chips without bpermute git tag: mesa-20.0.3 https://mesa.freedesktop.org/archive/mesa-20.0.3.tar.xz SHA256: d63aaf2c27143eded2f4f376f18f7a766ad997f8eeb96c357e8ade84e8a237af mesa-20.0.3.tar.xz
Re: [Mesa-dev] nir: find_msb vs clz
On Wed, Apr 1, 2020 at 1:52 PM Eric Anholt wrote: > > On Wed, Apr 1, 2020 at 11:39 AM Erik Faye-Lund > wrote: > > > > While working on the NIR to DXIL conversion code for D3D12, I've > > noticed that we're not exactly doing the best we could here. > > > > First some background: > > > > NIR currently has a few instructions that does kinda the same: > > > > 1. nir_op_ufind_msb: Finds the index of the most significant bit, > > counting from the least significant bit. It returns -1 on zero-input. > > > > 2. nir_op_ifind_msb: A signed version of ufind_msb; looks for the first > > non sign-bit. It's not terribly interesting in this context, as it can > > be trivially lowered if missing, and it doesn't seem like any hardware > > supports this natively. I'm just mentioning it for completeness. > > > > 3. nir_op_uclz: Counts the amount of leading zeroes, counding from the > > most significant bit. It returns 32 on zero-input, and only exist in an > > unsigned 32-bit variation. > > > > ufind_msb is kinda the O.G here, uclz was recently added, and is as far > > as I can see only used in an intel-specific SPIR-V instruction. > > > > Additionally, there's the OpenCLstd_Clz SPIR-V instruction, which we > > lower to ufind_msb using nir_clz_u(), regardless if the backend > > supports nir_op_uclz or not. > > > > It seems only the nouveau's NV50 backend actually wants ufind_msb, > > everything else seems to convert ufind_msb to some clz-variant while > > emitting code. Some have to special-case on zero-input, and some > > not... > > > > All of this is not really awesome in my eyes. > > > > So, while adding support for DXIL, I need to figure out how to map > > these (well, ufind_msb at least) onto the DXIL intrinsics. DXIL doesn't > > have a ufind_msb, but it has a firstbit_hi that is identical to > > nir_op_uclz... except that it returns -1 on zero-input :( > > > > For now, I'm lowering ufind_msb to something ufind_msb while emitting > > code, like everyone else. But this feels a bit dirty, *especially* > > since we have a clz-instruction that *almost* fits. And since we're > > targetting OpenCL, which use clz as it's primitive, we end up doing 32 > > - (32 - x), and since that inner isub happens while emitting, we can't > > easily optimize it away without introducing an optimizing backend... > > > > The solution seems obvious; use nir_op_uclz instead. > > > > But that's also a bit annoying, for a few reasons: > > > > 1. Only *one* backend actually implements support for it. So this > > either means a lot of work, or making it an opt-in feature somehow. That's likely fairly easily fixed. That said, making it an optional feature is also easy. Add lowering in nir_opt_algebraic.py hidden behind a lower_ufind_msb_to_clz flag. If setting that flag on Intel doesn't hurt shader-db (I think our back-end lowering may be slightly more efficient), we'll set it and delete a pile of code. > > 2. We would probably have to support lowering in either direction to > > support what all hardware prefers. I suspect that virtually everyone who has an instruction for this in hardware has one that supports returning the bit-width for 0. There's an interesting wikipedia page on this: https://en.wikipedia.org/wiki/Find_first_set According to the table there, virtually all CPUs that implement this return the bit-width for 0 except for the old way to do it on Intel. Since this is also what's defined for OpenCL, that's what we're likely to see on mobile. Intel has instructions for both and I would guess AMD and Nvidia do as well since they care a lot about D3D. > > 3. That zero-case still needs special treatment in several backends, it > > seems. We could alternatively declare that nir_op_uclz is undefined for > > zero-input, and handle this when lowering...? > > > > 4. It seems some (Intel?) hardware only supports 32-bit clz, so we > > would have to lower to something else for other bit-sizes. That's not > > too hard, though. On Intel, we have two instructions for this: FBH which returns -1 for 0 and LZD which returns 32 for 0. Both count leading zeros from the MSB side. We don't have native hardware support for computing from the LSB side. And, yeah, we can only do it on 32-bit types so that sucks a bit. > > So yeah... > > > > I guess the first step would be to add a switch to use nir_uclz() > > instead of nir_clz_u() when handling OpenCLstd_Clz in vtn. I would say just implement clz in nouveau and then make it always emit the clz instruction. Not that many consumers for OpenCL NIR right now. > > Next, I guess I would add a lower_ufind_msb flag to > > nir_shader_compiler_options, and make nir_opt_algebraic.py lower > > ufind_msb to uclz. I would add the lowering first, set the flag for nouveau (those are the people hacking on OpenCL NIR stuff right now), and then make OpenCL use the new nir_op_uclz instruction. > > Finally, we can start implementing support for this in more drivers, > > and flip on some switches. > > > > I'm s
Re: [Mesa-dev] nir: find_msb vs clz
On Wed, Apr 1, 2020 at 11:39 AM Erik Faye-Lund wrote: > > While working on the NIR to DXIL conversion code for D3D12, I've > noticed that we're not exactly doing the best we could here. > > First some background: > > NIR currently has a few instructions that does kinda the same: > > 1. nir_op_ufind_msb: Finds the index of the most significant bit, > counting from the least significant bit. It returns -1 on zero-input. > > 2. nir_op_ifind_msb: A signed version of ufind_msb; looks for the first > non sign-bit. It's not terribly interesting in this context, as it can > be trivially lowered if missing, and it doesn't seem like any hardware > supports this natively. I'm just mentioning it for completeness. > > 3. nir_op_uclz: Counts the amount of leading zeroes, counding from the > most significant bit. It returns 32 on zero-input, and only exist in an > unsigned 32-bit variation. > > ufind_msb is kinda the O.G here, uclz was recently added, and is as far > as I can see only used in an intel-specific SPIR-V instruction. > > Additionally, there's the OpenCLstd_Clz SPIR-V instruction, which we > lower to ufind_msb using nir_clz_u(), regardless if the backend > supports nir_op_uclz or not. > > It seems only the nouveau's NV50 backend actually wants ufind_msb, > everything else seems to convert ufind_msb to some clz-variant while > emitting code. Some have to special-case on zero-input, and some > not... > > All of this is not really awesome in my eyes. > > So, while adding support for DXIL, I need to figure out how to map > these (well, ufind_msb at least) onto the DXIL intrinsics. DXIL doesn't > have a ufind_msb, but it has a firstbit_hi that is identical to > nir_op_uclz... except that it returns -1 on zero-input :( > > For now, I'm lowering ufind_msb to something ufind_msb while emitting > code, like everyone else. But this feels a bit dirty, *especially* > since we have a clz-instruction that *almost* fits. And since we're > targetting OpenCL, which use clz as it's primitive, we end up doing 32 > - (32 - x), and since that inner isub happens while emitting, we can't > easily optimize it away without introducing an optimizing backend... > > The solution seems obvious; use nir_op_uclz instead. > > But that's also a bit annoying, for a few reasons: > > 1. Only *one* backend actually implements support for it. So this > either means a lot of work, or making it an opt-in feature somehow. > > 2. We would probably have to support lowering in either direction to > support what all hardware prefers. > > 3. That zero-case still needs special treatment in several backends, it > seems. We could alternatively declare that nir_op_uclz is undefined for > zero-input, and handle this when lowering...? > > 4. It seems some (Intel?) hardware only supports 32-bit clz, so we > would have to lower to something else for other bit-sizes. That's not > too hard, though. > > So yeah... > > I guess the first step would be to add a switch to use nir_uclz() > instead of nir_clz_u() when handling OpenCLstd_Clz in vtn. > > Next, I guess I would add a lower_ufind_msb flag to > nir_shader_compiler_options, and make nir_opt_algebraic.py lower > ufind_msb to uclz. > > Finally, we can start implementing support for this in more drivers, > and flip on some switches. > > I'm still not really sold on what to do about the special-case for > zero... By making it undefined, I think we're just punishing all > backends, just in the name of making the compiler backends a bit > simpler, so that doesn't seem too good of an idea either. > > Does anyone have a better idea? I would kinda love to optimize away the > zero-case if it's obvious that it's impossible, e.g cases like "clz(x | > 1)"... FWIW, as a datapoint: broadcom's v3d has a clz that returns 32 for clz(0). I would generally be of the opinion that we should have NIR opcodes that match any common hardware instructions, and lowering in algebraic to help turn input patterns into clean sequences of hardware instructions. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] nir: find_msb vs clz
On Wed, Apr 1, 2020 at 2:39 PM Erik Faye-Lund wrote: > > While working on the NIR to DXIL conversion code for D3D12, I've > noticed that we're not exactly doing the best we could here. > > First some background: > > NIR currently has a few instructions that does kinda the same: > > 1. nir_op_ufind_msb: Finds the index of the most significant bit, > counting from the least significant bit. It returns -1 on zero-input. > > 2. nir_op_ifind_msb: A signed version of ufind_msb; looks for the first > non sign-bit. It's not terribly interesting in this context, as it can > be trivially lowered if missing, and it doesn't seem like any hardware > supports this natively. I'm just mentioning it for completeness. While I can't speak to the current state of the nouveau NIR backend, the hardware definitely has both of these. (And a cursory look indicates that both are properly supported without any unnecessary lowering.) It's known as "FLO" in the NVIDIA intrinsic names, and it's the "BFIND" instruction in nv50_ir-speak. It's present on all Fermi+ GPUs. https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp#n2346 https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp#n946 Note that it has a separate bit for whether it's the signed variant or not. There's also a "SAMT" variant of it, but I honestly don't remember what that does exactly. We use it when finding the LSB after reversing the bits. I think makes the op return 32-x or something. Cheers, -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] nir: find_msb vs clz
While working on the NIR to DXIL conversion code for D3D12, I've noticed that we're not exactly doing the best we could here. First some background: NIR currently has a few instructions that does kinda the same: 1. nir_op_ufind_msb: Finds the index of the most significant bit, counting from the least significant bit. It returns -1 on zero-input. 2. nir_op_ifind_msb: A signed version of ufind_msb; looks for the first non sign-bit. It's not terribly interesting in this context, as it can be trivially lowered if missing, and it doesn't seem like any hardware supports this natively. I'm just mentioning it for completeness. 3. nir_op_uclz: Counts the amount of leading zeroes, counding from the most significant bit. It returns 32 on zero-input, and only exist in an unsigned 32-bit variation. ufind_msb is kinda the O.G here, uclz was recently added, and is as far as I can see only used in an intel-specific SPIR-V instruction. Additionally, there's the OpenCLstd_Clz SPIR-V instruction, which we lower to ufind_msb using nir_clz_u(), regardless if the backend supports nir_op_uclz or not. It seems only the nouveau's NV50 backend actually wants ufind_msb, everything else seems to convert ufind_msb to some clz-variant while emitting code. Some have to special-case on zero-input, and some not... All of this is not really awesome in my eyes. So, while adding support for DXIL, I need to figure out how to map these (well, ufind_msb at least) onto the DXIL intrinsics. DXIL doesn't have a ufind_msb, but it has a firstbit_hi that is identical to nir_op_uclz... except that it returns -1 on zero-input :( For now, I'm lowering ufind_msb to something ufind_msb while emitting code, like everyone else. But this feels a bit dirty, *especially* since we have a clz-instruction that *almost* fits. And since we're targetting OpenCL, which use clz as it's primitive, we end up doing 32 - (32 - x), and since that inner isub happens while emitting, we can't easily optimize it away without introducing an optimizing backend... The solution seems obvious; use nir_op_uclz instead. But that's also a bit annoying, for a few reasons: 1. Only *one* backend actually implements support for it. So this either means a lot of work, or making it an opt-in feature somehow. 2. We would probably have to support lowering in either direction to support what all hardware prefers. 3. That zero-case still needs special treatment in several backends, it seems. We could alternatively declare that nir_op_uclz is undefined for zero-input, and handle this when lowering...? 4. It seems some (Intel?) hardware only supports 32-bit clz, so we would have to lower to something else for other bit-sizes. That's not too hard, though. So yeah... I guess the first step would be to add a switch to use nir_uclz() instead of nir_clz_u() when handling OpenCLstd_Clz in vtn. Next, I guess I would add a lower_ufind_msb flag to nir_shader_compiler_options, and make nir_opt_algebraic.py lower ufind_msb to uclz. Finally, we can start implementing support for this in more drivers, and flip on some switches. I'm still not really sold on what to do about the special-case for zero... By making it undefined, I think we're just punishing all backends, just in the name of making the compiler backends a bit simpler, so that doesn't seem too good of an idea either. Does anyone have a better idea? I would kinda love to optimize away the zero-case if it's obvious that it's impossible, e.g cases like "clz(x | 1)"... ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
