[ANNOUNCE] mesa 21.3.7

2022-02-23 Thread Eric Engestrom
Hello everyone,

The seventh bugfix release, 21.3.7, is now available.

Please report any issue here:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/new

The next bugfix release is due in two weeks, on March 9th.

Cheers,
  Eric

---

Alyssa Rosenzweig (4):
  pan/bi: Avoid *FADD.v2f16 hazard in optimizer
  pan/bi: Avoid *FADD.v2f16 hazard in scheduler
  pan/bi: Lower swizzles on CSEL.i32/MUX.i32
  panvk: Use more reliable assert for UBO pushing

Bas Nieuwenhuizen (1):
  radv: Fix preamble argument order.

Connor Abbott (1):
  ir3/spill: Fix simplify_phi_nodes with multiple loop nesting

Dave Airlie (3):
  lavapipe: fix sampler + sampler view leaks.
  lavapipe: reference gallium fences correctly.
  crocus: fix leak on gen4/5 stencil fallback blit path.

Emma Anholt (1):
  i915g: Initialize the rest of the "from_nir" temporary VS struct.

Eric Engestrom (4):
  .pick_status.json: Update to dabba7d7263be6ffb6f3676465e92c65952fa824
  .pick_status.json: Mark b07372312d7053f2ef5c858ceb1fbf9ade5e7c52 as 
denominated
  docs: add release notes for 21.3.7
  VERSION: bump for 21.3.7

Ian Romanick (9):
  gallivm/nir: Call nir_lower_bool_to_int32 after nir_opt_algebraic_late
  nir: All set-on-comparison opcodes can take all float types
  intel/fs: Don't optimize out 1.0*x and -1.0*x
  spriv: Produce correct result for GLSLstd450Step with NaN
  spirv: Produce correct result for GLSLstd450Modf with Inf
  spirv: Produce correct result for GLSLstd450Tanh with NaN
  nir: Properly handle various exceptional values in frexp
  nir: Produce correct results for atan with NaN
  nir: Add missing dependency on nir_opcodes.py

Jason Ekstrand (1):
  anv: Call vk_command_buffer_finish if create fails

Jonathan Gray (1):
  dri: avoid NULL deref of DrawBuffer on flush

Lionel Landwerlin (2):
  nir: fix lower_memcpy
  anv/genxml/intel/fs: fix binding shader record entry

Marcin Ślusarz (1):
  anv: don't set color state when input state was requested

Marek Olšák (1):
  ac/surface: add more elements to meta equations because HTILE can use them

Mike Blumenkrantz (4):
  lavapipe: use util_pack_color_union() for generating clear colors
  aux/draw: fix llvm tcs lane vec generation
  zink: always set VkPipelineMultisampleStateCreateInfo::pSampleMask
  zink: always invalidate streamout counter buffer if not resuming

Nanley Chery (1):
  iris: Don't fast clear with the view format

Pavel Ondračka (1):
  r300: fix transformation of abs modifiers with negate

Qiang Yu (3):
  radeonsi: workaround Specviewperf13 Catia hang on GFX9
  radeonsi: fix depth stencil multi sample texture blit
  glx: fix pbuffer refcount init

Samuel Pitoiset (1):
  radv/winsys: fix initializing debug/perftest options if multiple instances

Tapani Pälli (5):
  intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
  anv: invalidate L3 read only cache when VF cache is invalidated
  iris: invalidate L3 read only cache when VF cache is invalidated
  iris: fix a leak on surface states
  mesa/st: always use DXT5 when transcoding ASTC format

Thierry Reding (2):
  tegra: Use private reference count for sampler views
  tegra: Use private reference count for resources

Timur Kristóf (1):
  radv: Disable IB2 on compute queues.

Yiwei Zhang (1):
  venus: properly destroy deferred ahb image before real image creation

git tag: mesa-21.3.7

https://mesa.freedesktop.org/archive/mesa-21.3.7.tar.xz
SHA256: b4fa9db7aa61bf209ef0b40bef83080999d86ad98df8b8b4fada7c128a1efc3d  
mesa-21.3.7.tar.xz
SHA512: 
0991543e9435457fa4d077517408b3f197be32ed61a6c7ca34ddb3906eed208791f1a57227f74115f99df18e612efab1d2c6809b7cf426d273633b53d4aefc88
  mesa-21.3.7.tar.xz
PGP:  https://mesa.freedesktop.org/archive/mesa-21.3.7.tar.xz.sig



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Re: [PATCH 2/2] drm/doc: add rfc section for small BAR uapi

2022-02-23 Thread Thomas Hellström



On 2/18/22 12:22, Matthew Auld wrote:

Add an entry for the new uapi needed for small BAR on DG2+.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Jon Bloomfield 
Cc: Daniel Vetter 
Cc: Jordan Justen 
Cc: Kenneth Graunke 
Cc: mesa-dev@lists.freedesktop.org
---
  Documentation/gpu/rfc/i915_small_bar.h   | 153 +++
  Documentation/gpu/rfc/i915_small_bar.rst |  40 ++
  Documentation/gpu/rfc/index.rst  |   4 +
  3 files changed, 197 insertions(+)
  create mode 100644 Documentation/gpu/rfc/i915_small_bar.h
  create mode 100644 Documentation/gpu/rfc/i915_small_bar.rst

diff --git a/Documentation/gpu/rfc/i915_small_bar.h 
b/Documentation/gpu/rfc/i915_small_bar.h
new file mode 100644
index ..fa65835fd608
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_small_bar.h
@@ -0,0 +1,153 @@
+/**
+ * struct __drm_i915_gem_create_ext - Existing gem_create behaviour, with added
+ * extension support using struct i915_user_extension.
+ *
+ * Note that in the future we want to have our buffer flags here,


Does this sentence need updating, with the flags member?



  at least for
+ * the stuff that is immutable. Previously we would have two ioctls, one to
+ * create the object with gem_create, and another to apply various parameters,
+ * however this creates some ambiguity for the params which are considered
+ * immutable. Also in general we're phasing out the various SET/GET ioctls.
+ */
+struct __drm_i915_gem_create_ext {
+   /**
+* @size: Requested size for the object.
+*
+* The (page-aligned) allocated size for the object will be returned.
+*
+* Note that for some devices we have might have further minimum
+* page-size restrictions(larger than 4K), like for device local-memory.
+* However in general the final size here should always reflect any
+* rounding up, if for example using the 
I915_GEM_CREATE_EXT_MEMORY_REGIONS
+* extension to place the object in device local-memory.
+*/
+   __u64 size;
+   /**
+* @handle: Returned handle for the object.
+*
+* Object handles are nonzero.
+*/
+   __u32 handle;
+   /**
+* @flags: Optional flags.
+*
+* Supported values:
+*
+* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that
+* the object will need to be accessed via the CPU.
+*
+* Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and
+* only strictly required on platforms where only some of the device
+* memory is directly visible or mappable through the CPU, like on DG2+.
+*
+* One of the placements MUST also be I915_MEMORY_CLASS_SYSTEM, to
+* ensure we can always spill the allocation to system memory, if we
+* can't place the object in the mappable part of
+* I915_MEMORY_CLASS_DEVICE.
+*
+* Note that buffers that need to be captured with EXEC_OBJECT_CAPTURE,
+* will need to enable this hint, if the object can also be placed in
+* I915_MEMORY_CLASS_DEVICE, starting from DG2+. The execbuf call will
+* throw an error otherwise. This also means that such objects will need
+* I915_MEMORY_CLASS_SYSTEM set as a possible placement.
+*
+* Without this hint, the kernel will assume that non-mappable
+* I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the
+* kernel can still migrate the object to the mappable part, as a last
+* resort, if userspace ever CPU faults this object, but this might be
+* expensive, and so ideally should be avoided.
+*/
+#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)
+   __u32 flags;
+   /**
+* @extensions: The chain of extensions to apply to this object.
+*
+* This will be useful in the future when we need to support several
+* different extensions, and we need to apply more than one when
+* creating the object. See struct i915_user_extension.
+*
+* If we don't supply any extensions then we get the same old gem_create
+* behaviour.
+*
+* For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
+* struct drm_i915_gem_create_ext_memory_regions.
+*
+* For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
+* struct drm_i915_gem_create_ext_protected_content.
+*/
+#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
+#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
+   __u64 extensions;
+};
+
+#define DRM_I915_QUERY_VMA_INFO5
+
+/**
+ * struct __drm_i915_query_vma_info
+ *
+ * Given a vm and GTT address, lookup the corresponding vma, returning its set
+ * of attributes.
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_query_vma_info info = {};
+ * struct drm_i915_query_item item = {
+ * .data_ptr = (uintptr_t)&info,
+ *