[Mesa-dev] [PATCH] RV730 support for Big Endian platforms

2011-04-19 Thread Cédric Cano

Hi

Few days ago, I posted a couple of patches on dri-devel but it doesn't 
seem to be the correct place. Here you are 2 patches that adds support 
for RV730 in r600c and r600g.


More details are available here :
http://lists.freedesktop.org/archives/dri-devel/2011-April/010056.html
http://lists.freedesktop.org/archives/dri-devel/2011-April/010281.html

Regards,
Cedric
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev


Re: [Mesa-dev] [PATCH] RV730 support for Big Endian platforms

2011-04-19 Thread Cédric Cano

Signed-off-by: Cedric Canoccano at interfaceconcept.com
---
diff -Naur Mesa-7.10/src/mesa/drivers/dri/r600/defaultendian.h 
Mesa-7.10/src/mesa/drivers/dri/r600/defaultendian.h
--- Mesa-7.10/src/mesa/drivers/dri/r600/defaultendian.h 2010-02-05 
01:10:40.0 +0100
+++ Mesa-7.10/src/mesa/drivers/dri/r600/defaultendian.h 2011-04-07 
16:19:50.0 +0200
@@ -29,8 +29,8 @@
 #define _DEFINEENDIAN_H_

 //We have to choose a reg bits orientation if there is no compile flag for it.
-#if defined(LITTLEENDIAN_CPU)
-#elif defined(BIGENDIAN_CPU)
+#ifdef MESA_BIG_ENDIAN
+#define BIGENDIAN_CPU
 #else
 #define LITTLEENDIAN_CPU
 #endif
diff -Naur Mesa-7.10/src/mesa/drivers/dri/r600/r600_blit.c 
Mesa-7.10/src/mesa/drivers/dri/r600/r600_blit.c
--- Mesa-7.10/src/mesa/drivers/dri/r600/r600_blit.c 2010-12-14 
22:43:15.0 +0100
+++ Mesa-7.10/src/mesa/drivers/dri/r600/r600_blit.c 2011-04-11 
16:43:40.0 +0200
@@ -94,17 +94,17 @@
 {
 uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, 
cb_color0_view = 0;
 int id = 0;
-uint32_t comp_swap, format;
+uint32_t endian, comp_swap, format;
 BATCH_LOCALS(context-radeon);

 cb_color0_base = dst_offset / 256;
+   endian = ENDIAN_NONE;

 SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
  PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
 SETfield(cb_color0_size, ((nPitchInPixel * h) / 64) - 1,
  SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);

-SETfield(cb_color0_info, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
 SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
  CB_COLOR0_INFO__ARRAY_MODE_shift, 
CB_COLOR0_INFO__ARRAY_MODE_mask);

@@ -112,24 +112,36 @@

 switch(mesa_format) {
 case MESA_FORMAT_RGBA:
+#ifdef MESA_BIG_ENDIAN
+   endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, 
NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_SIGNED_RGBA:
+#ifdef MESA_BIG_ENDIAN
+   endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, 
NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_RGBA_REV:
+#ifdef MESA_BIG_ENDIAN
+   endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_STD;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, 
NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_SIGNED_RGBA_REV:
+#ifdef MESA_BIG_ENDIAN
+   endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_STD;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -137,6 +149,9 @@
 break;
 case MESA_FORMAT_ARGB:
 case MESA_FORMAT_XRGB:
+#ifdef MESA_BIG_ENDIAN
+   endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_ALT;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -144,54 +159,81 @@
 break;
 case MESA_FORMAT_ARGB_REV:
 case MESA_FORMAT_XRGB_REV:
+#ifdef MESA_BIG_ENDIAN
+   endian = ENDIAN_8IN32;
+#endif
 format = COLOR_8_8_8_8;
 comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, 
NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_RGB565:
+#ifdef MESA_BIG_ENDIAN
+   endian = ENDIAN_8IN16;
+#endif
+   comp_swap = SWAP_STD_REV;   
 format = COLOR_5_6_5;
-comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, 
NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_RGB565_REV:
-format = COLOR_5_6_5;
+#ifdef MESA_BIG_ENDIAN
+   endian = ENDIAN_8IN16;
+#endif
 comp_swap = SWAP_STD;
+format = COLOR_5_6_5;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, 
NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_ARGB:
+#ifdef MESA_BIG_ENDIAN
+   endian = ENDIAN_8IN16;
+#endif
 format = COLOR_4_4_4_4;
 comp_swap = SWAP_ALT;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, 
NUMBER_TYPE_mask);
 break;
 case MESA_FORMAT_ARGB_REV:
+#ifdef MESA_BIG_ENDIAN
+

Re: [Mesa-dev] [PATCH] RV730 support for Big Endian platforms

2011-04-19 Thread Cédric Cano

Signed-off-by: Cedric Canoccano at interfaceconcept.com
---
diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c

index c22bd8e..7e854b1 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -22,6 +22,7 @@
  */
 #include stdio.h
 #include errno.h
+#include byteswap.h
 #include util/u_format.h
 #include util/u_memory.h
 #include pipe/p_shader_tokens.h
@@ -32,6 +33,12 @@
 #include r600_formats.h
 #include r600d.h

+#ifdef PIPE_ARCH_BIG_ENDIAN
+#define CPU_TO_LE32(x)bswap_32(x)
+#else
+#define CPU_TO_LE32(x)(x)
+#endif
+
 #define NUM_OF_CYCLES 3
 #define NUM_OF_COMPONENTS 4

@@ -1383,6 +1390,7 @@ static int r600_bc_vtx_build(struct r600_bc *bc, 
struct r600_bc_vtx *vtx, unsign

 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx-srf_mode_all) |
 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx-dst_gpr);
 bc-bytecode[id++] = S_SQ_VTX_WORD2_OFFSET(vtx-offset) |
+   S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx-endian) |
 S_SQ_VTX_WORD2_MEGA_FETCH(1);
 bc-bytecode[id++] = 0;
 return 0;
@@ -1917,6 +1925,7 @@ void r600_bc_dump(struct r600_bc *bc)
 fprintf(stderr, MODE:%d)\n, vtx-srf_mode_all);
 id++;
 fprintf(stderr, %04d %08X   , id, bc-bytecode[id]);
+fprintf(stderr, ENDIAN:%d , vtx-endian);
 fprintf(stderr, OFFSET:%d\n, vtx-offset);
 //TODO
 id++;
@@ -1929,7 +1938,7 @@ void r600_bc_dump(struct r600_bc *bc)
 }

 static void r600_vertex_data_type(enum pipe_format pformat, unsigned 
*format,

-unsigned *num_format, unsigned *format_comp)
+unsigned *num_format, unsigned *format_comp, unsigned 
*endian)

 {
 const struct util_format_description *desc;
 unsigned i;
@@ -1937,6 +1946,7 @@ static void r600_vertex_data_type(enum pipe_format 
pformat, unsigned *format,

 *format = 0;
 *num_format = 0;
 *format_comp = 0;
+*endian = ENDIAN_NONE;

 desc = util_format_description(pformat);
 if (desc-layout != UTIL_FORMAT_LAYOUT_PLAIN) {
@@ -1967,6 +1977,9 @@ static void r600_vertex_data_type(enum pipe_format 
pformat, unsigned *format,

 *format = FMT_16_16_16_16_FLOAT;
 break;
 }
+#ifdef PIPE_ARCH_BIG_ENDIAN
+*endian = ENDIAN_8IN16;
+#endif
 break;
 case 32:
 switch (desc-nr_channels) {
@@ -1983,6 +1996,9 @@ static void r600_vertex_data_type(enum pipe_format 
pformat, unsigned *format,

 *format = FMT_32_32_32_32_FLOAT;
 break;
 }
+#ifdef PIPE_ARCH_BIG_ENDIAN
+*endian = ENDIAN_8IN32;
+#endif
 break;
 default:
 goto out_unknown;
@@ -2020,6 +2036,9 @@ static void r600_vertex_data_type(enum pipe_format 
pformat, unsigned *format,

 *format = FMT_16_16_16_16;
 break;
 }
+#ifdef PIPE_ARCH_BIG_ENDIAN
+*endian = ENDIAN_8IN16;
+#endif
 break;
 case 32:
 switch (desc-nr_channels) {
@@ -2036,6 +2055,9 @@ static void r600_vertex_data_type(enum pipe_format 
pformat, unsigned *format,

 *format = FMT_32_32_32_32;
 break;
 }
+#ifdef PIPE_ARCH_BIG_ENDIAN
+*endian = ENDIAN_8IN32;
+#endif
 break;
 default:
 goto out_unknown;
@@ -2067,7 +2089,7 @@ int r600_vertex_elements_build_fetch_shader(struct 
r600_pipe_context *rctx, stru

 struct pipe_vertex_element *elements = ve-elements;
 const struct util_format_description *desc;
 unsigned fetch_resource_start = rctx-family = CHIP_CEDAR ? 0 : 160;
-unsigned format, num_format, format_comp;
+unsigned format, num_format, format_comp, endian;
 u32 *bytecode;
 int i, r;

@@ -2114,7 +2136,7 @@ int r600_vertex_elements_build_fetch_shader(struct 
r600_pipe_context *rctx, stru


 for (i = 0; i  ve-count; i++) {
 unsigned vbuffer_index;
-r600_vertex_data_type(ve-elements[i].src_format, format, 
num_format, format_comp);
+r600_vertex_data_type(ve-elements[i].src_format, format, 
num_format, format_comp, endian);

 desc = util_format_description(ve-elements[i].src_format);
 if (desc == NULL) {
 r600_bc_clear(bc);
@@ -2140,6 +2162,7 @@ int r600_vertex_elements_build_fetch_shader(struct 
r600_pipe_context *rctx, stru

 vtx.format_comp_all = format_comp;
 vtx.srf_mode_all = 1;
 vtx.offset = elements[i].src_offset;
+vtx.endian = endian;

 if ((r = r600_bc_add_vtx(bc, vtx))) {
 r600_bc_clear(bc);
@@ -2179,7 +2202,9 @@ int r600_vertex_elements_build_fetch_shader(struct 
r600_pipe_context *rctx, stru

 return -ENOMEM;
 }

-memcpy(bytecode, bc.bytecode, ve-fs_size);
+for(i = 0; i  ve-fs_size / 4; i++) {
+*(bytecode + i) = CPU_TO_LE32(*(bc.bytecode + i));
+