Re: [Mesa-dev] [PATCH v03 14/38] i965: Move MOCS macros to brw_context.h.

[Rafael Antognolli]

On Wed, May 03, 2017 at 11:36:29PM -0700, Kenneth Graunke wrote:
> On Wednesday, May 3, 2017 7:52:01 PM PDT Pohjolainen, Topi wrote:
> > On Wed, May 03, 2017 at 05:11:45PM -0700, Rafael Antognolli wrote:
> > > On Wed, May 03, 2017 at 08:28:24PM +0300, Pohjolainen, Topi wrote:
> > > > On Mon, May 01, 2017 at 06:43:02PM -0700, Rafael Antognolli wrote:
> > > > > These macros are defined in brw_defines.h, which contains a lot of
> > > > > macros that conflict with autogenerated code from genxml. But we need 
> > > > > to
> > > > > use them (the MOCS macros) in some of that same genxml code.
> > > > > 
> > > > > Moving them to brw_context.h solves that problem and we don't have to
> > > > > include brw_defines.h.
> > > > 
> > > > I've been hoping to remove things from brw_context.h - it starts to
> > > > resemble a dump yard for all sort of things. I think in this case we
> > > > could put these into brw_state.h instead? Or did you already try that?
> > > 
> > > I just tried this and it works fine too. I'm OK with either place to put
> > > these macros.
> > 
> > That would get my:
> > 
> > Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> 
> I do like that better.  Since I already landed this patch...Rafael,
> would you mind sending a patch to move them from brw_context.h to
> brw_state.h, and applying Topi's R-b?  I can push it.

Just sent it. I added them to the end of the header, as I couldn't
figure out a place that would make more sense. But feel free to move
them around if you prefer.
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[Mesa-dev] [PATCH] i965: Move MOCS macros to brw_state.h.

[Rafael Antognolli]

brw_state.h is a better place to keep them, instead of brw_context.h.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.h | 42 -
 src/mesa/drivers/dri/i965/brw_state.h   | 42 +
 2 files changed, 42 insertions(+), 42 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index df7b6eb..723c5d6 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -397,48 +397,6 @@ struct brw_cache {
bool bo_used_by_gpu;
 };
 
-/* Memory Object Control State:
- * Specifying zero for L3 means "uncached in L3", at least on Haswell
- * and Baytrail, since there are no PTE flags for setting L3 cacheability.
- * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
- * may still respect that.
- */
-#define GEN7_MOCS_L31
-
-/* Ivybridge only: cache in LLC.
- * Specifying zero here means to use the PTE values set by the kernel;
- * non-zero overrides the PTE values.
- */
-#define IVB_MOCS_LLC(1 << 1)
-
-/* Baytrail only: snoop in CPU cache */
-#define BYT_MOCS_SNOOP  (1 << 1)
-
-/* Haswell only: LLC/eLLC controls (write-back or uncached).
- * Specifying zero here means to use the PTE values set by the kernel,
- * which is useful since it offers additional control (write-through
- * cacheing and age).  Non-zero overrides the PTE values.
- */
-#define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
-#define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
-#define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
-
-/* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
- * and let you force write-back (WB) or write-through (WT) caching, or leave
- * it up to the page table entry (PTE) specified by the kernel.
- */
-#define BDW_MOCS_WB  0x78
-#define BDW_MOCS_WT  0x58
-#define BDW_MOCS_PTE 0x18
-
-/* Skylake: MOCS is now an index into an array of 62 different caching
- * configurations programmed by the kernel.
- */
-/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
-#define SKL_MOCS_WB  (2 << 1)
-/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
-#define SKL_MOCS_PTE (1 << 1)
-
 /* Considered adding a member to this struct to document which flags
  * an update might raise so that ordering of the state atoms can be
  * checked or derived at runtime.  Dropped the idea in favor of having
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index d2d3d7c..5b51dc0 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -368,6 +368,48 @@ void gen9_init_atoms(struct brw_context *brw);
 
 void upload_gs_state_for_tf(struct brw_context *brw);
 
+/* Memory Object Control State:
+ * Specifying zero for L3 means "uncached in L3", at least on Haswell
+ * and Baytrail, since there are no PTE flags for setting L3 cacheability.
+ * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
+ * may still respect that.
+ */
+#define GEN7_MOCS_L31
+
+/* Ivybridge only: cache in LLC.
+ * Specifying zero here means to use the PTE values set by the kernel;
+ * non-zero overrides the PTE values.
+ */
+#define IVB_MOCS_LLC(1 << 1)
+
+/* Baytrail only: snoop in CPU cache */
+#define BYT_MOCS_SNOOP  (1 << 1)
+
+/* Haswell only: LLC/eLLC controls (write-back or uncached).
+ * Specifying zero here means to use the PTE values set by the kernel,
+ * which is useful since it offers additional control (write-through
+ * cacheing and age).  Non-zero overrides the PTE values.
+ */
+#define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
+#define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
+#define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
+
+/* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
+ * and let you force write-back (WB) or write-through (WT) caching, or leave
+ * it up to the page table entry (PTE) specified by the kernel.
+ */
+#define BDW_MOCS_WB  0x78
+#define BDW_MOCS_WT  0x58
+#define BDW_MOCS_PTE 0x18
+
+/* Skylake: MOCS is now an index into an array of 62 different caching
+ * configurations programmed by the kernel.
+ */
+/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
+#define SKL_MOCS_WB  (2 << 1)
+/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
+#define SKL_MOCS_PTE (1 << 1)
+
 #ifdef __cplusplus
 }
 #endif
-- 
2.9.3

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Re: [Mesa-dev] [PATCH 1/3] mesa: Simplify _mesa_primitive_restart_index().

[Rafael Antognolli]

Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>

On Thu, May 04, 2017 at 08:13:05AM -0700, Kenneth Graunke wrote:
> We can use a simple shift equation rather than a switch statement.
> ---
>  src/mesa/main/varray.c | 12 ++--
>  1 file changed, 2 insertions(+), 10 deletions(-)
> 
> diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
> index eda86ec6a82..9497090e88a 100644
> --- a/src/mesa/main/varray.c
> +++ b/src/mesa/main/varray.c
> @@ -1959,16 +1959,8 @@ _mesa_primitive_restart_index(const struct gl_context 
> *ctx,
>  *  is used."
>  */
> if (ctx->Array.PrimitiveRestartFixedIndex) {
> -  switch (index_size) {
> -  case 1:
> - return 0xff;
> -  case 2:
> - return 0x;
> -  case 4:
> - return 0x;
> -  default:
> - assert(!"_mesa_primitive_restart_index: Invalid index size.");
> -  }
> +  /* 1 -> 0xff, 2 -> 0x, 4 -> 0x */
> +  return 0xu >> 8 * (4 - index_size);
> }
>  
> return ctx->Array.RestartIndex;
> -- 
> 2.12.2
> 
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[Mesa-dev] [PATCH] genxml: Fix 3DSTATE_DEPTH_BUFFER length on gen5.

[Rafael Antognolli]

The hardware docs are wrong, but the length used in the xml is also
wrong.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/genxml/gen5.xml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index 0b84650..447499c 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -649,14 +649,14 @@
 
   
 
-  
-
+  
+
 
 
 
 
 
-
+
 
 
   
-- 
2.9.3

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Re: [Mesa-dev] [PATCH v03 14/38] i965: Move MOCS macros to brw_context.h.

[Rafael Antognolli]

On Wed, May 03, 2017 at 08:28:24PM +0300, Pohjolainen, Topi wrote:
> On Mon, May 01, 2017 at 06:43:02PM -0700, Rafael Antognolli wrote:
> > These macros are defined in brw_defines.h, which contains a lot of
> > macros that conflict with autogenerated code from genxml. But we need to
> > use them (the MOCS macros) in some of that same genxml code.
> > 
> > Moving them to brw_context.h solves that problem and we don't have to
> > include brw_defines.h.
> 
> I've been hoping to remove things from brw_context.h - it starts to
> resemble a dump yard for all sort of things. I think in this case we
> could put these into brw_state.h instead? Or did you already try that?

I just tried this and it works fine too. I'm OK with either place to put
these macros.

> > 
> > Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
> > ---
> >  src/mesa/drivers/dri/i965/brw_context.h | 41 +-
> >  src/mesa/drivers/dri/i965/brw_defines.h | 42 +--
> >  2 files changed, 41 insertions(+), 42 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
> > b/src/mesa/drivers/dri/i965/brw_context.h
> > index c7d6e49..5e627ae 100644
> > --- a/src/mesa/drivers/dri/i965/brw_context.h
> > +++ b/src/mesa/drivers/dri/i965/brw_context.h
> > @@ -397,6 +397,47 @@ struct brw_cache {
> > bool bo_used_by_gpu;
> >  };
> >  
> > +/* Memory Object Control State:
> > + * Specifying zero for L3 means "uncached in L3", at least on Haswell
> > + * and Baytrail, since there are no PTE flags for setting L3 cacheability.
> > + * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
> > + * may still respect that.
> > + */
> > +#define GEN7_MOCS_L31
> > +
> > +/* Ivybridge only: cache in LLC.
> > + * Specifying zero here means to use the PTE values set by the kernel;
> > + * non-zero overrides the PTE values.
> > + */
> > +#define IVB_MOCS_LLC(1 << 1)
> > +
> > +/* Baytrail only: snoop in CPU cache */
> > +#define BYT_MOCS_SNOOP  (1 << 1)
> > +
> > +/* Haswell only: LLC/eLLC controls (write-back or uncached).
> > + * Specifying zero here means to use the PTE values set by the kernel,
> > + * which is useful since it offers additional control (write-through
> > + * cacheing and age).  Non-zero overrides the PTE values.
> > + */
> > +#define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
> > +#define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
> > +#define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
> > +
> > +/* Broadwell: these defines always use all available caches (L3, LLC, 
> > eLLC),
> > + * and let you force write-back (WB) or write-through (WT) caching, or 
> > leave
> > + * it up to the page table entry (PTE) specified by the kernel.
> > + */
> > +#define BDW_MOCS_WB  0x78
> > +#define BDW_MOCS_WT  0x58
> > +#define BDW_MOCS_PTE 0x18
> > +
> > +/* Skylake: MOCS is now an index into an array of 62 different caching
> > + * configurations programmed by the kernel.
> > + */
> > +/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
> > +#define SKL_MOCS_WB  (2 << 1)
> > +/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
> > +#define SKL_MOCS_PTE (1 << 1)
> >  
> >  /* Considered adding a member to this struct to document which flags
> >   * an update might raise so that ordering of the state atoms can be
> > diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
> > b/src/mesa/drivers/dri/i965/brw_defines.h
> > index 08106c0..130a1ed 100644
> > --- a/src/mesa/drivers/dri/i965/brw_defines.h
> > +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> > @@ -1365,48 +1365,6 @@ enum brw_pixel_shader_coverage_mask_mode {
> >   */
> >  #define BRW_MAX_NUM_BUFFER_ENTRIES (1 << 27)
> >  
> > -/* Memory Object Control State:
> > - * Specifying zero for L3 means "uncached in L3", at least on Haswell
> > - * and Baytrail, since there are no PTE flags for setting L3 cacheability.
> > - * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
> > - * may still respect that.
> > - */
> > -#define GEN7_MOCS_L31
> > -
> > -/* Ivybridge only: cache in LLC.
> > - * Specifying zero here means to use the PTE values set by the kernel;
> > - * non-zero overrides the PTE values.
> > - */
> > -#define IVB_MOCS_LLC(1 << 1)
> > -
> > -/* Baytrail only: snoop in CPU cache

Re: [Mesa-dev] [PATCH v03 17/38] genxml: Add rules to build gen4, gen45 and ge5.

[Rafael Antognolli]

On Wed, May 03, 2017 at 09:10:10PM +0300, Pohjolainen, Topi wrote:
> 
> In the subject: s/ge5/gen5/
> 
> But don't we need to squash this into the previous patch? Alone that patch
> won't even link, right?

Yes, you are right, it should be squashed.

> On Mon, May 01, 2017 at 06:43:05PM -0700, Rafael Antognolli wrote:
> > Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
> > ---
> >  src/mesa/drivers/dri/i965/Makefile.am  | 12 
> >  src/mesa/drivers/dri/i965/Makefile.sources |  9 +
> >  src/mesa/drivers/dri/i965/brw_state.h  |  1 +
> >  3 files changed, 22 insertions(+)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/Makefile.am 
> > b/src/mesa/drivers/dri/i965/Makefile.am
> > index 4e9b062..762aefc 100644
> > --- a/src/mesa/drivers/dri/i965/Makefile.am
> > +++ b/src/mesa/drivers/dri/i965/Makefile.am
> > @@ -46,12 +46,24 @@ AM_CFLAGS = \
> >  AM_CXXFLAGS = $(AM_CFLAGS)
> >  
> >  I965_PERGEN_LIBS = \
> > +   libi965_gen4.la \
> > +   libi965_gen45.la \
> > +   libi965_gen5.la \
> > libi965_gen6.la \
> > libi965_gen7.la \
> > libi965_gen75.la \
> > libi965_gen8.la \
> > libi965_gen9.la
> >  
> > +libi965_gen4_la_SOURCES = $(i965_gen4_FILES)
> > +libi965_gen4_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=40
> > +
> > +libi965_gen45_la_SOURCES = $(i965_gen45_FILES)
> > +libi965_gen45_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=45
> > +
> > +libi965_gen5_la_SOURCES = $(i965_gen5_FILES)
> > +libi965_gen5_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=50
> > +
> >  libi965_gen6_la_SOURCES = $(i965_gen6_FILES)
> >  libi965_gen6_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=60
> >  
> > diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
> > b/src/mesa/drivers/dri/i965/Makefile.sources
> > index db55a3f..41f4d83 100644
> > --- a/src/mesa/drivers/dri/i965/Makefile.sources
> > +++ b/src/mesa/drivers/dri/i965/Makefile.sources
> > @@ -160,6 +160,15 @@ i965_FILES = \
> > intel_upload.c \
> > libdrm_macros.h
> >  
> > +i965_gen4_FILES = \
> > +   genX_state_upload.c
> > +
> > +i965_gen45_FILES = \
> > +   genX_state_upload.c
> > +
> > +i965_gen5_FILES = \
> > +   genX_state_upload.c
> > +
> >  i965_gen6_FILES = \
> > genX_blorp_exec.c \
> > genX_state_upload.c
> > diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
> > b/src/mesa/drivers/dri/i965/brw_state.h
> > index 008326a..6403570 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state.h
> > +++ b/src/mesa/drivers/dri/i965/brw_state.h
> > @@ -446,6 +446,7 @@ void brw_copy_pipeline_atoms(struct brw_context *brw,
> >   const struct brw_tracked_state **atoms,
> >   int num_atoms);
> >  void gen4_init_atoms(struct brw_context *brw);
> > +void gen45_init_atoms(struct brw_context *brw);
> >  void gen5_init_atoms(struct brw_context *brw);
> >  void gen6_init_atoms(struct brw_context *brw);
> >  void gen7_init_atoms(struct brw_context *brw);
> > -- 
> > git-series 0.9.1
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Re: [Mesa-dev] i965: Use isl for hiz and stencil

[Rafael Antognolli]

On Wed, May 03, 2017 at 12:22:13PM +0300, Topi Pohjolainen wrote:
> Patches 1-17 are revision that
> 
>   - rework hiz on gen6 to use on-demand offset calculator allowing
> one to drop dependency to miptree structure and 
>   - rework all auxiliary surfaces to be created against isl directly.
> 
> Patches 18 and 19 introduce new surface layout in ISL. This is called
> back-to-back and similar to layout ALL_SLICES_AT_EACH_LOD found in
> i965 for gen6 hiz and stencil. This layout stacks slices for each level
> after one and other, or back to back. All slices ate each lod is almost
> the same except that it places levels one and two side-by-side trying
> to preserve space. Back-to-back wastes a little more memory but aligns
> each level on page boundary simplifying driver logic.
> 
> Patch 20 switches gen6 hiz to use back-to-back.
> 
> Patches 22-37 prepare i965 driver to work with miptrees based on isl.
> Patches 38 and 39 start to use isl for stencil surfaces and effectively
> switches to back-to-back stencil layout on gen6.
> Patch 25 is mostly unneeded but it doesn't hurt and it provides me the
> tiling converter I need in patch 36.
> 
> There are two uglies, patches 21 and 37. Perhaps Nanley, Jason or Chad
> can help me with 21...
> 
> Jason: You have reviewed most of 1-17, and I don't think they have
>changed that much.
> 
> Rafael: I have conflicting patches with your series addressing depth
> and stencil state emission. We should try to land your patches
> first and then I'll rebase this on top.

Hey Topi, thanks for letting me know. Yeah, I saw the conflicts you
mention, and there are also conflicts with depth buffer state, which I'm
also converting to genxml. But from what I looked, it doesn't seem like
it's going to be too hard to rebase/solve the conflicts.

> If we agree on the approach here, I'll continue with gen4/5 depth
> surface alignment workaround aiming to base depth surfaces also on
> isl. That should allow me to start using isl state emitter for
> depth-hiz-stencil.
> 
> CC: Jason Ekstrand <ja...@jlekstrand.net>
> CC: Nanley Chery <nanley.g.ch...@intel.com>
> CC: Chad Versace <chadvers...@chromium.org>
> CC: Rafael Antognolli <rafael.antogno...@intel.com>
> 
> Topi Pohjolainen (39):
>   i965/dbg: Add means for forcing stencil sampling using y-tiled copy
>   i965/gen6: Remove dead code in hiz surface setup
>   i965/blorp/gen6: Drop unnecessary stencil/hiz surf dimension adjust
>   i965/gen6: Calculate stencil offset on demand
>   i965/gen6: Calculate hiz offset on demand
>   i965/blorp/gen6: Use on-demand stencil/hiz offset resolvers
>   i965/gen6: Drop miptrees in depth/stencil offset resolvers
>   i965/blorp/gen6: Set aux pitch directly
>   i965/gen6/hiz: Add direct buffer size resolver
>   i965/gen6: Allocate hiz directly without miptree
>   i965/miptree: Refactor aux surface allocation
>   i965/miptree: Refactor ISL aux usage resolver
>   i965/miptree: Use ISL for MCS layouts
>   i965/miptree: Drop MIPTREE_LAYOUT_ACCELERATED_UPLOAD in mcs init
>   i965/miptree/gen7+: Use ISL for HIZ layouts
>   i965/blorp: Use hiz surface instead of creating copy
>   i965: Use stored hiz surface instead of creating copy
>   intel/isl/gen6: Add offsetting support for back-to-back layouts
>   intel/isl/gen6: Add size calculator for back-to-back layouts
>   i965/hiz/gen6: Use isl back-to-back layout
>   intel/isl/gen6/hack: Use hiz vertical alignment of 16 instead of 8
>   i965/miptree: Add support for resolving offsets using isl
>   i965/blorp: Add support for isl based miptrees
>   i965: Prepare up/downsampling for isl based miptrees
>   i965: Prepare blit engine for isl based miptrees
>   i965: Prepare image validation for isl based miptrees
>   i965: Refactor miptree to isl converter and adjustment
>   i965: Prepare tex, img and rt state emission for isl based miptrees
>   i965: Prepare slice validator for isl based miptrees
>   i965: Prepare framebuffer validator for isl based miptrees
>   i965/tex: Prepare image update for isl based miptrees
>   i965: Prepare texture validator for isl based miptrees
>   i965: Prepare slice copy for isl based miptrees
>   i965/gen7: Prepare depth state emission for isl based miptrees
>   i965/gen8+: Prepare depth state emission for isl based miptrees
>   i965: Add isl based miptree creator
>   intel/isl/gen7/hack: Use stencil vertical alignment of 8 instead of 4
>   i965/miptree: Represent w-tiled stencil surfaces with isl
>   i965/miptree: Represent y-tiled stencil copies with isl
> 
>  src/intel/blorp/blorp.c  |   4 +-
>  src/intel/blorp/blorp_blit.c |  11 +-
>  src/intel/common/gen_debug.c 

Re: [Mesa-dev] [PATCH] i965: Drop "Destination Element Offset" from Ironlake SGVs.

[Rafael Antognolli]

Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>

On Fri, Apr 28, 2017 at 05:04:05PM -0700, Kenneth Graunke wrote:
> The Ironlake documentation is terrible, so it's unclear whether or not
> this field exists there.  It definitely doesn't exist on Sandybridge
> and later.  It definitely does exist on G45.
> 
> We haven't been setting it for our normal vertex attributes - just
> the SGVs (VertexID, InstanceID, BaseVertex, BaseInstance, DrawID).
> We should be consistent.  My guess is that it isn't necessary and
> doesn't exist - this patch drops it from the SGVs elements, making
> them follow the behavior of most attributes.
> ---
>  src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c 
> b/src/mesa/drivers/dri/i965/brw_draw_upload.c
> index 7846293cb1b..002e863a649 100644
> --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
> @@ -1096,7 +1096,8 @@ brw_emit_vertices(struct brw_context *brw)
>   dw0 |= BRW_VE0_VALID |
>  brw->vb.nr_buffers << BRW_VE0_INDEX_SHIFT |
>  ISL_FORMAT_R32G32_UINT << BRW_VE0_FORMAT_SHIFT;
> -  dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
> + if (brw->gen == 4)
> +dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
>}
>  
>/* Note that for gl_VertexID, gl_InstanceID, and gl_PrimitiveID values,
> @@ -1124,7 +1125,8 @@ brw_emit_vertices(struct brw_context *brw)
>  ((brw->vb.nr_buffers + 1) << BRW_VE0_INDEX_SHIFT) |
>  (ISL_FORMAT_R32_UINT << BRW_VE0_FORMAT_SHIFT);
>  
> -  dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
> + if (brw->gen == 4)
> +dw1 |= (i * 4) << BRW_VE1_DST_OFFSET_SHIFT;
>}
>  
>OUT_BATCH(dw0);
> -- 
> 2.12.2
> 
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Re: [Mesa-dev] [PATCH 08/11] intel/decoder: Fix indentation

[Rafael Antognolli]

Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>

On Mon, May 01, 2017 at 01:54:52PM -0700, Matt Turner wrote:
> ---
>  src/intel/common/gen_decoder.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
> index 15bba32..049d1be 100644
> --- a/src/intel/common/gen_decoder.c
> +++ b/src/intel/common/gen_decoder.c
> @@ -433,8 +433,8 @@ end_element(void *data, const char *name)
> struct gen_spec *spec = ctx->spec;
>  
> if (strcmp(name, "instruction") == 0 ||
> -  strcmp(name, "struct") == 0 ||
> -  strcmp(name, "register") == 0) {
> +   strcmp(name, "struct") == 0 ||
> +   strcmp(name, "register") == 0) {
>size_t size = ctx->nfields * sizeof(ctx->fields[0]);
>struct gen_group *group = ctx->group;
>  
> @@ -446,8 +446,8 @@ end_element(void *data, const char *name)
>  
>for (int i = 0; i < group->nfields; i++) {
>   if (group->fields[i]->start >= 16 &&
> -group->fields[i]->end <= 31 &&
> -group->fields[i]->has_default) {
> + group->fields[i]->end <= 31 &&
> + group->fields[i]->has_default) {
>  group->opcode_mask |=
> mask(group->fields[i]->start % 32, group->fields[i]->end % 
> 32);
>  group->opcode |=
> -- 
> 2.10.2
> 
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Re: [Mesa-dev] [PATCH 05/11] genxml: Remove brackets from kernel start pointer names

[Rafael Antognolli]

Patch is
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>

On Mon, May 01, 2017 at 01:54:49PM -0700, Matt Turner wrote:
> Newer Gens' names don't have the brackets. Having common names will make
> some later patches simpler.
> ---
>  src/intel/genxml/gen4.xml  | 2 +-
>  src/intel/genxml/gen45.xml | 2 +-
>  src/intel/genxml/gen6.xml  | 6 +++---
>  3 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
> index 5ea15e7..22755bf 100644
> --- a/src/intel/genxml/gen4.xml
> +++ b/src/intel/genxml/gen4.xml
> @@ -474,7 +474,7 @@
>  
>
>  
> -
> +
>  
>  
>  
> diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
> index 4582beb..9c43aef 100644
> --- a/src/intel/genxml/gen45.xml
> +++ b/src/intel/genxml/gen45.xml
> @@ -466,7 +466,7 @@
>  
>
>  
> -
> +
>  
>  
>  
> diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
> index 3059bfc..a5e39d3 100644
> --- a/src/intel/genxml/gen6.xml
> +++ b/src/intel/genxml/gen6.xml
> @@ -1392,7 +1392,7 @@
>   default="0"/>
>   default="20"/>
>  
> -
> +
>  
>  
>  
> @@ -1475,8 +1475,8 @@
>
>
>  
> - type="offset"/>
> - type="offset"/>
> + type="offset"/>
> + type="offset"/>
>
>  
>
> -- 
> 2.10.2
> 
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[Mesa-dev] [PATCH] i965: Make the field computed_depth_mode an enum.

[Rafael Antognolli]

Since the enum is in the same header now, we can use it as the type of
the field.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---

PS: We can merge this with the previous patch too if that's better.

 src/intel/compiler/brw_compiler.h | 2 +-
 src/intel/compiler/brw_fs.cpp | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_compiler.h 
b/src/intel/compiler/brw_compiler.h
index b5b1ee9..92fd4a2 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -504,7 +504,7 @@ struct brw_wm_prog_data {
   /** @} */
} binding_table;
 
-   uint8_t computed_depth_mode;
+   enum brw_pixel_shader_computed_depth_mode computed_depth_mode;
bool computed_stencil;
 
bool early_fragment_tests;
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 4dcdc1b..a0c62a2 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -6281,7 +6281,7 @@ brw_compute_flat_inputs(struct brw_wm_prog_data 
*prog_data,
}
 }
 
-static uint8_t
+static enum brw_pixel_shader_computed_depth_mode
 computed_depth_mode(const nir_shader *shader)
 {
if (shader->info->outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
-- 
2.9.3

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[Mesa-dev] [PATCH] i965: Move enums to brw_compiler.h.

[Rafael Antognolli]

These enums live inside struct brw_wm_prog_data, so it makes sense to
keep them in the same header. It also allows to use them without
including brw_eu_defines.h.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/compiler/brw_compiler.h   | 21 +
 src/intel/compiler/brw_eu_defines.h | 21 -
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/src/intel/compiler/brw_compiler.h 
b/src/intel/compiler/brw_compiler.h
index 9228413..b5b1ee9 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -458,6 +458,27 @@ brw_mark_surface_used(struct brw_stage_prog_data 
*prog_data,
   MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 }
 
+enum brw_barycentric_mode {
+   BRW_BARYCENTRIC_PERSPECTIVE_PIXEL   = 0,
+   BRW_BARYCENTRIC_PERSPECTIVE_CENTROID= 1,
+   BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE  = 2,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL= 3,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
+   BRW_BARYCENTRIC_MODE_COUNT  = 6
+};
+#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
+   ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
+(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
+(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
+
+enum brw_pixel_shader_computed_depth_mode {
+   BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
+   BRW_PSCDEPTH_ON= 1, /* PS computes depth; no guarantee about value */
+   BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
+   BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
+};
+
 /* Data about a particular attempt to compile a program.  Note that
  * there can be many of these, each in a different GL state
  * corresponding to a different brw_wm_prog_key struct, with different
diff --git a/src/intel/compiler/brw_eu_defines.h 
b/src/intel/compiler/brw_eu_defines.h
index 13a70f6..ccc838d 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -72,27 +72,6 @@
 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x16
 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
 
-enum brw_barycentric_mode {
-   BRW_BARYCENTRIC_PERSPECTIVE_PIXEL   = 0,
-   BRW_BARYCENTRIC_PERSPECTIVE_CENTROID= 1,
-   BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE  = 2,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL= 3,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
-   BRW_BARYCENTRIC_MODE_COUNT  = 6
-};
-#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
-   ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
-(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
-(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
-
-enum brw_pixel_shader_computed_depth_mode {
-   BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
-   BRW_PSCDEPTH_ON= 1, /* PS computes depth; no guarantee about value */
-   BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
-   BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
-};
-
 /* Bitfields for the URB_WRITE message, DW2 of message header: */
 #define URB_WRITE_PRIM_END 0x1
 #define URB_WRITE_PRIM_START   0x2
-- 
2.9.3

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Re: [Mesa-dev] [PATCH v03 12/38] i965: Split out enum from brw_eu_defines.h

[Rafael Antognolli]

On Tue, May 02, 2017 at 08:44:05AM -0700, Jason Ekstrand wrote:
> On Tue, May 2, 2017 at 8:28 AM, Rafael Antognolli 
> <rafael.antogno...@intel.com>
> wrote:
> 
> On Tue, May 02, 2017 at 07:26:53AM -0700, Jason Ekstrand wrote:
> > On Mon, May 1, 2017 at 6:43 PM, Rafael Antognolli <
> rafael.antogno...@intel.com>
> > wrote:
> >
> > We need to use some enums inside genX_state_upload.c, but including
> the
> > whole header will cause several conflicts between things defined in
> this
> > header and the genxml auto-generated headers.
> >
> > So create a separate header that is included both by 
> brw_eu_defines.h
> > and genX_state_upload.c.
> >
> > Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
> > Acked-by: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
> > ---
> >  src/intel/Makefile.sources  |  1 +-
> >  src/intel/compiler/brw_defines_common.h | 46
> ++-
> >  src/intel/compiler/brw_eu_defines.h | 22 +
> >  3 files changed, 48 insertions(+), 21 deletions(-)
> >  create mode 100644 src/intel/compiler/brw_defines_common.h
> >
> > diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
> > index e9a39a6..652f376 100644
> > --- a/src/intel/Makefile.sources
> > +++ b/src/intel/Makefile.sources
> > @@ -27,6 +27,7 @@ COMPILER_FILES = \
> > compiler/brw_compiler.h \
> > compiler/brw_dead_control_flow.cpp \
> > compiler/brw_dead_control_flow.h \
> > +   compiler/brw_defines_common.h \
> > compiler/brw_disasm.c \
> > compiler/brw_eu.c \
> > compiler/brw_eu_compact.c \
> > diff --git a/src/intel/compiler/brw_defines_common.h b/src/intel/
> compiler/
> > brw_defines_common.h
> > new file mode 100644
> > index 000..fdae125
> > --- /dev/null
> > +++ b/src/intel/compiler/brw_defines_common.h
> > @@ -0,0 +1,46 @@
> > +/*
> > + * Copyright © 2017 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> obtaining a
> > + * copy of this software and associated documentation files (the
> > "Software"),
> > + * to deal in the Software without restriction, including without
> > limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > sublicense,
> > + * and/or sell copies of the Software, and to permit persons to 
> whom
> the
> > + * Software is furnished to do so, subject to the following
> conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> the
> > next
> > + * paragraph) shall be included in all copies or substantial
> portions of
> > the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS
> > OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT
> > SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, 
> DAMAGES
> OR
> > OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> > DEALINGS
> > + * IN THE SOFTWARE.
> > + */
> > +
> > +#ifndef BRW_DEFINES_COMMON_H
> > +#endif // BRW_DEFINES_COMMON_H
> > +
> > +enum brw_pixel_shader_computed_depth_mode {
> > +   BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
> > +   BRW_PSCDEPTH_ON= 1, /* PS computes depth; no guarantee about
> value
> > */
> > +   BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source
> depth *
> > /
> > +   BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source
> depth *
> > /
&

Re: [Mesa-dev] [PATCH v03 12/38] i965: Split out enum from brw_eu_defines.h

[Rafael Antognolli]

On Tue, May 02, 2017 at 07:26:53AM -0700, Jason Ekstrand wrote:
> On Mon, May 1, 2017 at 6:43 PM, Rafael Antognolli 
> <rafael.antogno...@intel.com>
> wrote:
> 
> We need to use some enums inside genX_state_upload.c, but including the
> whole header will cause several conflicts between things defined in this
> header and the genxml auto-generated headers.
> 
> So create a separate header that is included both by brw_eu_defines.h
> and genX_state_upload.c.
> 
> Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
> Acked-by: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
> ---
>  src/intel/Makefile.sources  |  1 +-
>  src/intel/compiler/brw_defines_common.h | 46 ++-
>  src/intel/compiler/brw_eu_defines.h | 22 +
>  3 files changed, 48 insertions(+), 21 deletions(-)
>  create mode 100644 src/intel/compiler/brw_defines_common.h
> 
> diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
> index e9a39a6..652f376 100644
> --- a/src/intel/Makefile.sources
> +++ b/src/intel/Makefile.sources
> @@ -27,6 +27,7 @@ COMPILER_FILES = \
> compiler/brw_compiler.h \
> compiler/brw_dead_control_flow.cpp \
> compiler/brw_dead_control_flow.h \
> +   compiler/brw_defines_common.h \
> compiler/brw_disasm.c \
> compiler/brw_eu.c \
> compiler/brw_eu_compact.c \
> diff --git a/src/intel/compiler/brw_defines_common.h b/src/intel/compiler/
> brw_defines_common.h
> new file mode 100644
> index 000..fdae125
> --- /dev/null
> +++ b/src/intel/compiler/brw_defines_common.h
> @@ -0,0 +1,46 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining 
> a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> next
> + * paragraph) shall be included in all copies or substantial portions of
> the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
> EXPRESS
> OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT
> SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 
> ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#ifndef BRW_DEFINES_COMMON_H
> +#endif // BRW_DEFINES_COMMON_H
> +
> +enum brw_pixel_shader_computed_depth_mode {
> +   BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
> +   BRW_PSCDEPTH_ON= 1, /* PS computes depth; no guarantee about value
> */
> +   BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth 
> *
> /
> +   BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth 
> *
> /
> 
> 
> These are provided by the pack header at least on gen8.  If they're not
> available elsewhere, we should just add them.

Hmm... good point. They are values to "Pixel Shader Computed Depth Mode"
in 3DSTATE_PS_EXTRA, which is only available in gen7+, so where would be
a good place for gen6?

> +};
> +
> +enum brw_barycentric_mode {
> +   BRW_BARYCENTRIC_PERSPECTIVE_PIXEL   = 0,
> +   BRW_BARYCENTRIC_PERSPECTIVE_CENTROID= 1,
> +   BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE  = 2,
> +   BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL= 3,
> +   BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
> +   BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
> 
> 
> These are also in the pack header.

OK.

> 
> +   BRW_BARYCENTRIC_MODE_COUNT  = 6
> +};
> +#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
> +   ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
> +(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
> + 

Re: [Mesa-dev] [PATCH v03 12/38] i965: Split out enum from brw_eu_defines.h

[Rafael Antognolli]

On Tue, May 02, 2017 at 09:38:53AM +0100, Emil Velikov wrote:
> On 2 May 2017 at 09:32, Emil Velikov <emil.l.veli...@gmail.com> wrote:
> > Hi Rafael,
> >
> > On 2 May 2017 at 02:43, Rafael Antognolli <rafael.antogno...@intel.com> 
> > wrote:
> >> We need to use some enums inside genX_state_upload.c, but including the
> >> whole header will cause several conflicts between things defined in this
> >> header and the genxml auto-generated headers.
> >>
> >> So create a separate header that is included both by brw_eu_defines.h
> >> and genX_state_upload.c.
> >>
> >> Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
> >> Acked-by: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
> >> ---
> >>  src/intel/Makefile.sources  |  1 +-
> >>  src/intel/compiler/brw_defines_common.h | 46 ++-
> >>  src/intel/compiler/brw_eu_defines.h | 22 +
> >>  3 files changed, 48 insertions(+), 21 deletions(-)
> >>  create mode 100644 src/intel/compiler/brw_defines_common.h
> >>
> >> diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
> >> index e9a39a6..652f376 100644
> >> --- a/src/intel/Makefile.sources
> >> +++ b/src/intel/Makefile.sources
> >> @@ -27,6 +27,7 @@ COMPILER_FILES = \
> >> compiler/brw_compiler.h \
> >> compiler/brw_dead_control_flow.cpp \
> >> compiler/brw_dead_control_flow.h \
> >> +   compiler/brw_defines_common.h \
> > Amazing, thank you!
> >
> >> compiler/brw_disasm.c \
> >> compiler/brw_eu.c \
> >> compiler/brw_eu_compact.c \
> >> diff --git a/src/intel/compiler/brw_defines_common.h 
> >> b/src/intel/compiler/brw_defines_common.h
> >> new file mode 100644
> >> index 000..fdae125
> >> --- /dev/null
> >> +++ b/src/intel/compiler/brw_defines_common.h
> >
> >> +
> >> +#ifndef BRW_DEFINES_COMMON_H
> > You want a "#define BRW_DEFINES_COMMON_H" here
> >
> >> +#endif // BRW_DEFINES_COMMON_H
> >> +
> > And this line should be at the end of the file.
> >
> Forgot to mention: the above is trivial, so I don't bother resending
> the series just for that.

Ugh, my bad. Thank you.

Rafael
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[Mesa-dev] [PATCH v03 37/38] i965: Port gen6+ 3DSTATE_CC_STATE_POINTERS state to genxml.

[Rafael Antognolli]

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|  1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  1 +-
 src/mesa/drivers/dri/i965/gen6_cc.c   | 90 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 53 +++-
 4 files changed, 50 insertions(+), 95 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_cc.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 34162bd..8ae2e87 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -76,7 +76,6 @@ i965_FILES = \
brw_wm.h \
brw_wm_state.c \
brw_wm_surface_state.c \
-   gen6_cc.c \
gen6_clip_state.c \
gen6_constant_state.c \
gen6_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 2b5b1c4..29e83cb 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -107,7 +107,6 @@ extern const struct brw_tracked_state brw_index_buffer;
 extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
-extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c 
b/src/mesa/drivers/dri/i965/gen6_cc.c
deleted file mode 100644
index 688362f..000
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt <e...@anholt.net>
- *
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "intel_batchbuffer.h"
-#include "main/macros.h"
-#include "main/enums.h"
-#include "main/glformats.h"
-#include "main/stencil.h"
-
-static void
-gen6_upload_color_calc_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   struct gen6_color_calc_state *cc;
-
-   cc = brw_state_batch(brw, sizeof(*cc), 64, >cc.state_offset);
-   memset(cc, 0, sizeof(*cc));
-
-   /* _NEW_COLOR */
-   cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
-   UNCLAMPED_FLOAT_TO_UBYTE(cc->cc1.alpha_ref_fi.ui, ctx->Color.AlphaRef);
-
-   if (brw->gen < 9) {
-  /* _NEW_STENCIL */
-  cc->cc0.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
-  cc->cc0.bf_stencil_ref =
- _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
-   }
-
-   /* _NEW_COLOR */
-   cc->constant_r = ctx->Color.BlendColorUnclamped[0];
-   cc->constant_g = ctx->Color.BlendColorUnclamped[1];
-   cc->constant_b = ctx->Color.BlendColorUnclamped[2];
-   cc->constant_a = ctx->Color.BlendColorUnclamped[3];
-
-   /* Point the GPU at the new indirect state. */
-   if (brw->gen == 6) {
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(brw->cc.state_offset | 1);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(2);
-  OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
-  OUT_BATCH(brw->cc.state_offset | 1);
-  ADVANCE_BATCH();
-   }
-}
-
-const struct brw_tracked_state gen6_color_calc_state = {
-   .dirty = {
-  .mesa = _NEW_COLOR |
-  _NEW_STENCIL,
-  .brw = BRW_NEW_BATCH |
- BRW_NEW_BLORP |
- BRW_

[Mesa-dev] [PATCH v03 33/38] i965: Port gen6+ 3DSTATE_SCISSOR_STATE_POINTERS to use genxml.

[Rafael Antognolli]

Emit 3DSTATE_SCISSOR_STATE_POINTERS using brw_batch_emit, and pack the
scissor states using GENX(SCISSOR_RECT_pack), generated from genxml.

v3:
   - Remove old code (Ken)
   - Style fixes (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/Makefile.sources |   1 +-
 src/mesa/drivers/dri/i965/brw_state.h  |   1 +-
 src/mesa/drivers/dri/i965/gen6_scissor_state.c | 111 +--
 src/mesa/drivers/dri/i965/genX_state_upload.c  |  90 ++-
 4 files changed, 87 insertions(+), 116 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_scissor_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 0123913..a63d576 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -84,7 +84,6 @@ i965_FILES = \
gen6_multisample_state.c \
gen6_queryobj.c \
gen6_sampler_state.c \
-   gen6_scissor_state.c \
gen6_sol.c \
gen6_urb.c \
gen6_viewport_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 322d767..6adcf46 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -114,7 +114,6 @@ extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_multisample_state;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
-extern const struct brw_tracked_state gen6_scissor_state;
 extern const struct brw_tracked_state gen6_sol_surface;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c 
b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
deleted file mode 100644
index 3407f6a..000
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt <e...@anholt.net>
- *
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "intel_batchbuffer.h"
-#include "main/fbobject.h"
-#include "main/framebuffer.h"
-
-static void
-gen6_upload_scissor_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
-   struct gen6_scissor_rect *scissor;
-   uint32_t scissor_state_offset;
-   const unsigned int fb_width= _mesa_geometric_width(ctx->DrawBuffer);
-   const unsigned int fb_height = _mesa_geometric_height(ctx->DrawBuffer);
-
-   /* BRW_NEW_VIEWPORT_COUNT */
-   const unsigned viewport_count = brw->clip.viewport_count;
-
-   scissor = brw_state_batch(brw, sizeof(*scissor) * viewport_count, 32,
- _state_offset);
-
-   /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
-
-   /* The scissor only needs to handle the intersection of drawable and
-* scissor rect.  Clipping to the boundaries of static shared buffers
-* for front/back/depth is covered by looping over cliprects in brw_draw.c.
-*
-* Note that the hardware's coordinates are inclusive, while Mesa's min is
-* inclusive but max is exclusive.
-*/
-   for (unsigned i = 0; i < viewport_count; i++) {
-  int bbox[4];
-
-  bbox[0] = MAX2(ctx->ViewportArray[i].X, 0);
-  bbox[1] = MIN2(bbox[0] + ctx->ViewportArray[i].Width, fb_width);
-  bbox[2] = MAX2(ctx->ViewportArray[i].Y, 0);
-  bbox[3] = MIN2(bbox[2] + ctx->ViewportArray[i].Height, fb_height);
-  _mesa_in

[Mesa-dev] [PATCH v03 14/38] i965: Move MOCS macros to brw_context.h.

[Rafael Antognolli]

These macros are defined in brw_defines.h, which contains a lot of
macros that conflict with autogenerated code from genxml. But we need to
use them (the MOCS macros) in some of that same genxml code.

Moving them to brw_context.h solves that problem and we don't have to
include brw_defines.h.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.h | 41 +-
 src/mesa/drivers/dri/i965/brw_defines.h | 42 +--
 2 files changed, 41 insertions(+), 42 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index c7d6e49..5e627ae 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -397,6 +397,47 @@ struct brw_cache {
bool bo_used_by_gpu;
 };
 
+/* Memory Object Control State:
+ * Specifying zero for L3 means "uncached in L3", at least on Haswell
+ * and Baytrail, since there are no PTE flags for setting L3 cacheability.
+ * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
+ * may still respect that.
+ */
+#define GEN7_MOCS_L31
+
+/* Ivybridge only: cache in LLC.
+ * Specifying zero here means to use the PTE values set by the kernel;
+ * non-zero overrides the PTE values.
+ */
+#define IVB_MOCS_LLC(1 << 1)
+
+/* Baytrail only: snoop in CPU cache */
+#define BYT_MOCS_SNOOP  (1 << 1)
+
+/* Haswell only: LLC/eLLC controls (write-back or uncached).
+ * Specifying zero here means to use the PTE values set by the kernel,
+ * which is useful since it offers additional control (write-through
+ * cacheing and age).  Non-zero overrides the PTE values.
+ */
+#define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
+#define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
+#define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
+
+/* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
+ * and let you force write-back (WB) or write-through (WT) caching, or leave
+ * it up to the page table entry (PTE) specified by the kernel.
+ */
+#define BDW_MOCS_WB  0x78
+#define BDW_MOCS_WT  0x58
+#define BDW_MOCS_PTE 0x18
+
+/* Skylake: MOCS is now an index into an array of 62 different caching
+ * configurations programmed by the kernel.
+ */
+/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
+#define SKL_MOCS_WB  (2 << 1)
+/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
+#define SKL_MOCS_PTE (1 << 1)
 
 /* Considered adding a member to this struct to document which flags
  * an update might raise so that ordering of the state atoms can be
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 08106c0..130a1ed 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1365,48 +1365,6 @@ enum brw_pixel_shader_coverage_mask_mode {
  */
 #define BRW_MAX_NUM_BUFFER_ENTRIES (1 << 27)
 
-/* Memory Object Control State:
- * Specifying zero for L3 means "uncached in L3", at least on Haswell
- * and Baytrail, since there are no PTE flags for setting L3 cacheability.
- * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
- * may still respect that.
- */
-#define GEN7_MOCS_L31
-
-/* Ivybridge only: cache in LLC.
- * Specifying zero here means to use the PTE values set by the kernel;
- * non-zero overrides the PTE values.
- */
-#define IVB_MOCS_LLC(1 << 1)
-
-/* Baytrail only: snoop in CPU cache */
-#define BYT_MOCS_SNOOP  (1 << 1)
-
-/* Haswell only: LLC/eLLC controls (write-back or uncached).
- * Specifying zero here means to use the PTE values set by the kernel,
- * which is useful since it offers additional control (write-through
- * cacheing and age).  Non-zero overrides the PTE values.
- */
-#define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
-#define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
-#define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
-
-/* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
- * and let you force write-back (WB) or write-through (WT) caching, or leave
- * it up to the page table entry (PTE) specified by the kernel.
- */
-#define BDW_MOCS_WB  0x78
-#define BDW_MOCS_WT  0x58
-#define BDW_MOCS_PTE 0x18
-
-/* Skylake: MOCS is now an index into an array of 62 different caching
- * configurations programmed by the kernel.
- */
-/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
-#define SKL_MOCS_WB  (2 << 1)
-/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
-#define SKL_MOCS_PTE (1 << 1)
-
 #define MEDIA_VFE_STATE 0x7000
 /* GEN7 DW2, GEN8+ DW3 */
 # define MEDIA_VFE_STATE_MAX_THREADS_SHIFT  16
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v03 13/38] anv: Use BRW_BARYCENTRIC_NONPERSPECTIVE_BITS from common header.

[Rafael Antognolli]

In a previous patch some enums were split out from brw_eu_defines.h, so
they could be used by genxml based code. anv can also benefit from this.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/vulkan/genX_pipeline.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 43e6ab5..198a353 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -28,6 +28,7 @@
 
 #include "common/gen_l3_config.h"
 #include "common/gen_sample_positions.h"
+#include "compiler/brw_defines_common.h"
 #include "vk_format_info.h"
 
 static uint32_t
@@ -1059,7 +1060,8 @@ emit_3dstate_clip(struct anv_pipeline *pipeline,
   }
 #else
   clip.NonPerspectiveBarycentricEnable = wm_prog_data ?
- (wm_prog_data->barycentric_interp_modes & 0x38) != 0 : 0;
+ (wm_prog_data->barycentric_interp_modes &
+  BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) != 0 : 0;
 #endif
}
 }
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v03 38/38] i965: Port gen4+ state emitting code to genxml.

[Rafael Antognolli]

On this patch, we port:
   - brw_polygon_stipple
   - brw_polygon_stipple_offset
   - brw_line_stipple
   - brw_drawing_rect

v2:
   - Also emit states for gen4-5 with this code.
v3:
   - Style fixes and remove excessive checks (Ken).

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources  |   1 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c  | 147 +-
 src/mesa/drivers/dri/i965/brw_state.h   |   5 +-
 src/mesa/drivers/dri/i965/gen6_viewport_state.c |  60 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c   | 191 +++--
 5 files changed, 174 insertions(+), 230 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_viewport_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 8ae2e87..9e567cb 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -85,7 +85,6 @@ i965_FILES = \
gen6_sampler_state.c \
gen6_sol.c \
gen6_urb.c \
-   gen6_viewport_state.c \
gen7_cs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 83c1810..afa7e08 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -44,32 +44,6 @@
 #include "main/fbobject.h"
 #include "main/glformats.h"
 
-/* Constant single cliprect for framebuffer object or DRI2 drawing */
-static void
-upload_drawing_rect(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   const struct gl_framebuffer *fb = ctx->DrawBuffer;
-   const unsigned int fb_width = _mesa_geometric_width(fb);
-   const unsigned int fb_height = _mesa_geometric_height(fb);
-
-   BEGIN_BATCH(4);
-   OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
-   OUT_BATCH(0); /* xmin, ymin */
-   OUT_BATCH(((fb_width - 1) & 0x) | ((fb_height - 1) << 16));
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state brw_drawing_rect = {
-   .dirty = {
-  .mesa = _NEW_BUFFERS,
-  .brw = BRW_NEW_BLORP |
- BRW_NEW_CONTEXT,
-   },
-   .emit = upload_drawing_rect
-};
-
 /**
  * Upload pointers to the per-stage state.
  *
@@ -696,127 +670,6 @@ const struct brw_tracked_state brw_depthbuffer = {
.emit = brw_emit_depthbuffer,
 };
 
-/**
- * Polygon stipple packet
- */
-static void
-upload_polygon_stipple(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   GLuint i;
-
-   /* _NEW_POLYGON */
-   if (!ctx->Polygon.StippleFlag)
-  return;
-
-   BEGIN_BATCH(33);
-   OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
-
-   /* Polygon stipple is provided in OpenGL order, i.e. bottom
-* row first.  If we're rendering to a window (i.e. the
-* default frame buffer object, 0), then we need to invert
-* it to match our pixel layout.  But if we're rendering
-* to a FBO (i.e. any named frame buffer object), we *don't*
-* need to invert - we already match the layout.
-*/
-   if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
-  for (i = 0; i < 32; i++)
- OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */
-   } else {
-  for (i = 0; i < 32; i++)
-OUT_BATCH(ctx->PolygonStipple[i]);
-   }
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state brw_polygon_stipple = {
-   .dirty = {
-  .mesa = _NEW_POLYGON |
-  _NEW_POLYGONSTIPPLE,
-  .brw = BRW_NEW_CONTEXT,
-   },
-   .emit = upload_polygon_stipple
-};
-
-/**
- * Polygon stipple offset packet
- */
-static void
-upload_polygon_stipple_offset(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-
-   /* _NEW_POLYGON */
-   if (!ctx->Polygon.StippleFlag)
-  return;
-
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));
-
-   /* _NEW_BUFFERS
-*
-* If we're drawing to a system window we have to invert the Y axis
-* in order to match the OpenGL pixel coordinate system, and our
-* offset must be matched to the window position.  If we're drawing
-* to a user-created FBO then our native pixel coordinate system
-* works just fine, and there's no window system to worry about.
-*/
-   if (_mesa_is_winsys_fbo(ctx->DrawBuffer))
-  OUT_BATCH((32 - (_mesa_geometric_height(ctx->DrawBuffer) & 31)) & 31);
-   else
-  OUT_BATCH(0);
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state brw_polygon_stipple_offset = {
-   .dirty = {
-  .mesa = _NEW_BUFFERS |
-  _NEW_POLYGON,
-  .brw = BRW_NEW_CONTEXT,
-   },
-   .emit = upload_polygon_stipple_offset
-};
-
-/**
- * Line stipple packet
- */
-static void
-upload_line_stipple(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   GLfloat tmp;
-   GLint tmpi;
-
-   if (!ctx-&

[Mesa-dev] [PATCH v03 07/38] genxml: 3DSTATE_VS rename Function Enable to Enable.

[Rafael Antognolli]

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/blorp/blorp_genX_exec.h | 2 +-
 src/intel/genxml/gen6.xml | 2 +-
 src/intel/genxml/gen7.xml | 2 +-
 src/intel/genxml/gen75.xml| 2 +-
 src/intel/genxml/gen8.xml | 2 +-
 src/intel/genxml/gen9.xml | 2 +-
 src/intel/vulkan/genX_pipeline.c  | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 0bde2d2..bc829d0 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -432,7 +432,7 @@ blorp_emit_vs_config(struct blorp_batch *batch,
 
blorp_emit(batch, GENX(3DSTATE_VS), vs) {
   if (vs_prog_data) {
- vs.FunctionEnable = true;
+ vs.Enable = true;
 
  vs.KernelStartPointer = params->vs_prog_kernel;
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 14d643c..a12e22c 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1391,7 +1391,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index e6b61b7..2ac096e 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1864,7 +1864,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index e63979c..6d2bfaa 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2192,7 +2192,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 3b44406..05e228c 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2352,7 +2352,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index d78a321..191c74c 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2585,7 +2585,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 2631ed0..74d6f9a 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1132,7 +1132,7 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
 
anv_batch_emit(>batch, GENX(3DSTATE_VS), vs) {
-  vs.FunctionEnable   = true;
+  vs.Enable   = true;
   vs.StatisticsEnable = true;
   vs.KernelStartPointer   = vs_bin->kernel.offset;
 #if GEN_GEN >= 8
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v03 11/38] genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.

[Rafael Antognolli]

- "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid"
   - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer"
   - "BackFace" -> "Backface"

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/blorp/blorp_genX_exec.h  | 4 ++--
 src/intel/genxml/gen6.xml  | 4 ++--
 src/intel/genxml/gen8.xml  | 2 +-
 src/intel/vulkan/gen8_cmd_buffer.c | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index be22be0..9e61f69 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1365,10 +1365,10 @@ blorp_exec(struct blorp_batch *batch, const struct 
blorp_params *params)
 */
blorp_emit(batch, GENX(3DSTATE_CC_STATE_POINTERS), cc) {
   cc.BLEND_STATEChange = true;
-  cc.COLOR_CALC_STATEChange = true;
+  cc.ColorCalcStatePointerValid = true;
   cc.DEPTH_STENCIL_STATEChange = true;
   cc.PointertoBLEND_STATE = blend_state_offset;
-  cc.PointertoCOLOR_CALC_STATE = color_calc_state_offset;
+  cc.ColorCalcStatePointer = color_calc_state_offset;
   cc.PointertoDEPTH_STENCIL_STATE = depth_stencil_state_offset;
}
 #else
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index a8ce7e0..cdcead3 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -773,8 +773,8 @@
 
 
 
-
-
+
+
   
 
   
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 7f60ea4..c57ddb4 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -568,7 +568,7 @@
 
   
 
-
+
 
 
   
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c 
b/src/intel/vulkan/gen8_cmd_buffer.c
index c891a76..0e26dda 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -467,7 +467,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer 
*cmd_buffer)
  .BlendConstantColorBlue = 
cmd_buffer->state.dynamic.blend_constants[2],
  .BlendConstantColorAlpha = 
cmd_buffer->state.dynamic.blend_constants[3],
  .StencilReferenceValue = d->stencil_reference.front & 0xff,
- .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
+ .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
   };
   GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, );
 
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v03 19/38] i965: Port Gen6+ 3DSTATE_CLIP state to genxml.

[Rafael Antognolli]

Emit clip state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.

v3:
   - Lots style fixes (Ken)
   - Do not set CullTestEnableBitMask on Gen8+ (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_state.h |   1 +-
 src/mesa/drivers/dri/i965/gen6_clip_state.c   | 139 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 140 ++-
 3 files changed, 137 insertions(+), 143 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 7b6d718..c26be41 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,7 +109,6 @@ extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_blend_state;
-extern const struct brw_tracked_state gen6_clip_state;
 extern const struct brw_tracked_state gen6_sf_and_clip_viewports;
 extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_state;
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c 
b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index 23d969b..2fffb67 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -88,142 +88,3 @@ brw_is_drawing_lines(const struct brw_context *brw)
return false;
 }
 
-static void
-upload_clip_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_META_IN_PROGRESS */
-   uint32_t dw1 = brw->meta_in_progress ? 0 : GEN6_CLIP_STATISTICS_ENABLE;
-   uint32_t dw2 = 0;
-
-   /* _NEW_BUFFERS */
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-
-   /* BRW_NEW_FS_PROG_DATA */
-   if (brw_wm_prog_data(brw->wm.base.prog_data)->barycentric_interp_modes &
-   BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) {
-  dw2 |= GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE;
-   }
-
-   /* BRW_NEW_VS_PROG_DATA */
-   dw1 |= brw_vue_prog_data(brw->vs.base.prog_data)->cull_distance_mask;
-
-   if (brw->gen >= 7)
-  dw1 |= GEN7_CLIP_EARLY_CULL;
-
-   if (brw->gen == 7) {
-  /* _NEW_POLYGON */
-  if (ctx->Polygon._FrontBit == _mesa_is_user_fbo(fb))
- dw1 |= GEN7_CLIP_WINDING_CCW;
-
-  if (ctx->Polygon.CullFlag) {
- switch (ctx->Polygon.CullFaceMode) {
- case GL_FRONT:
-dw1 |= GEN7_CLIP_CULLMODE_FRONT;
-break;
- case GL_BACK:
-dw1 |= GEN7_CLIP_CULLMODE_BACK;
-break;
- case GL_FRONT_AND_BACK:
-dw1 |= GEN7_CLIP_CULLMODE_BOTH;
-break;
- default:
-unreachable("Should not get here: invalid CullFlag");
- }
-  } else {
- dw1 |= GEN7_CLIP_CULLMODE_NONE;
-  }
-   }
-
-   if (brw->gen < 8 && !ctx->Transform.DepthClamp)
-  dw2 |= GEN6_CLIP_Z_TEST;
-
-   /* _NEW_LIGHT */
-   if (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
-  dw2 |=
-(0 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
-(1 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
-(0 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
-   } else {
-  dw2 |=
-(2 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
-(2 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
-(1 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
-   }
-
-   /* _NEW_TRANSFORM */
-   dw2 |= (ctx->Transform.ClipPlanesEnabled <<
-   GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT);
-
-   /* Have the hardware use the user clip distance clip test enable bitmask
-* specified here in 3DSTATE_CLIP rather than the one in 3DSTATE_VS/DS/GS.
-* We already listen to _NEW_TRANSFORM here, but the other atoms don't
-* need to other than this.
-*/
-   if (brw->gen >= 8)
-  dw1 |= GEN8_CLIP_FORCE_USER_CLIP_DISTANCE_BITMASK;
-
-   if (ctx->Transform.ClipDepthMode == GL_ZERO_TO_ONE)
-  dw2 |= GEN6_CLIP_API_D3D;
-   else
-  dw2 |= GEN6_CLIP_API_OGL;
-
-   dw2 |= GEN6_CLIP_GB_TEST;
-
-   /* BRW_NEW_VIEWPORT_COUNT */
-   const unsigned viewport_count = brw->clip.viewport_count;
-
-   /* BRW_NEW_RASTERIZER_DISCARD */
-   if (ctx->RasterDiscard) {
-  dw2 |= GEN6_CLIP_MODE_REJECT_ALL;
-  if (brw->gen == 6) {
- perf_debug("Rasterizer discard is currently implemented via the "
-"clipper; having the GS not write primitives would "
-"likely be faster.\n");
-  }
-   }
-
-   uint32_t enable;
-   if (brw->primitive == _3DPRIM_RECTLIST)
-  enable = 0;
-   else
-  enable = GEN6_CLIP_ENABLE;
-
-   /* _NEW_POLYGON,
-* BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
-*/
-   if (!brw_is_drawing_points(brw) && !brw_is_drawing_lines(b

[Mesa-dev] [PATCH v03 31/38] i965: Port gen6+ blend state code to genxml.

[Rafael Antognolli]

Upload blend states using GENX(BLEND_STATE_ENTRY_pack), generated from
genxml.

v3:
   - style fixes (Ken)
   - cleanup to remove excessive #ifdef's (Ken)
   - remove memset (Ken)
   - disable blend.AlphaToCoverageDitherEnable on gen6 (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |   3 +-
 src/mesa/drivers/dri/i965/gen6_cc.c   | 216 +-
 src/mesa/drivers/dri/i965/gen8_blend_state.c  | 298 +--
 src/mesa/drivers/dri/i965/genX_state_upload.c | 316 ++-
 5 files changed, 312 insertions(+), 522 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_blend_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 3f0c66a..0c67170 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -99,7 +99,6 @@ i965_FILES = \
gen7_te_state.c \
gen7_urb.c \
gen7_wm_surface_state.c \
-   gen8_blend_state.c \
gen8_depth_state.c \
gen8_draw_upload.c \
gen8_multisample_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index b6e8abc..cf043a0 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -108,7 +108,6 @@ extern const struct brw_tracked_state brw_index_buffer;
 extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
-extern const struct brw_tracked_state gen6_blend_state;
 extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
@@ -130,11 +129,9 @@ extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
-extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_index_buffer;
 extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
-extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c 
b/src/mesa/drivers/dri/i965/gen6_cc.c
index 0e0d05e..688362f 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -36,222 +36,6 @@
 #include "main/stencil.h"
 
 static void
-gen6_upload_blend_state(struct brw_context *brw)
-{
-   bool is_buffer_zero_integer_format = false;
-   struct gl_context *ctx = >ctx;
-   struct gen6_blend_state *blend;
-   int b;
-   int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers;
-   int size;
-
-   /* We need at least one BLEND_STATE written, because we might do
-* thread dispatch even if _NumColorDrawBuffers is 0 (for example
-* for computed depth or alpha test), which will do an FB write
-* with render target 0, which will reference BLEND_STATE[0] for
-* alpha test enable.
-*/
-   if (nr_draw_buffers == 0)
-  nr_draw_buffers = 1;
-
-   size = sizeof(*blend) * nr_draw_buffers;
-   blend = brw_state_batch(brw, size, 64, >cc.blend_state_offset);
-
-   memset(blend, 0, size);
-
-   for (b = 0; b < nr_draw_buffers; b++) {
-  /* _NEW_BUFFERS */
-  struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[b];
-  GLenum rb_type;
-  bool integer;
-
-  if (rb)
-rb_type = _mesa_get_format_datatype(rb->Format);
-  else
-rb_type = GL_UNSIGNED_NORMALIZED;
-
-  /* Used for implementing the following bit of GL_EXT_texture_integer:
-   * "Per-fragment operations that require floating-point color
-   *  components, including multisample alpha operations, alpha test,
-   *  blending, and dithering, have no effect when the corresponding
-   *  colors are written to an integer color buffer."
-  */
-  integer = (rb_type == GL_INT || rb_type == GL_UNSIGNED_INT);
-
-  if(b == 0 && integer)
- is_buffer_zero_integer_format = true;
-
-  /* _NEW_COLOR */
-  if (ctx->Color.ColorLogicOpEnabled) {
-/* Floating point RTs should have no effect from LogicOp,
- * except for disabling of blending, but other types should.
- *
- * However, from the Sandy Bridge PRM, Vol 2 Par 1, Section 8.1.11,
- * "Logic Ops",
- *

[Mesa-dev] [PATCH v03 21/38] i965: Add brw_get_line_width_float.

[Rafael Antognolli]

That helper function returns the line width as a float, and is then used
by brw_get_line_width to return the fixed point width.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_util.h | 25 ++---
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_util.h 
b/src/mesa/drivers/dri/i965/brw_util.h
index 3e9a6ee..7395d34 100644
--- a/src/mesa/drivers/dri/i965/brw_util.h
+++ b/src/mesa/drivers/dri/i965/brw_util.h
@@ -40,8 +40,8 @@ extern GLuint brw_translate_blend_factor( GLenum factor );
 extern GLuint brw_translate_blend_equation( GLenum mode );
 extern GLenum brw_fix_xRGB_alpha(GLenum function);
 
-static inline uint32_t
-brw_get_line_width(struct brw_context *brw)
+static inline float
+brw_get_line_width_float(struct brw_context *brw)
 {
/* From the OpenGL 4.4 spec:
 *
@@ -52,14 +52,9 @@ brw_get_line_width(struct brw_context *brw)
float line_width =
   CLAMP(!_mesa_is_multisample_enabled(>ctx) && 
!brw->ctx.Line.SmoothFlag
 ? roundf(brw->ctx.Line.Width) : brw->ctx.Line.Width,
-0.0f, brw->ctx.Const.MaxLineWidth);
-   uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
+0.125f, brw->ctx.Const.MaxLineWidth);
 
-   /* Line width of 0 is not allowed when MSAA enabled */
-   if (_mesa_is_multisample_enabled(>ctx)) {
-  if (line_width_u3_7 == 0)
- line_width_u3_7 = 1;
-   } else if (brw->ctx.Line.SmoothFlag && line_width < 1.5f) {
+   if (!_mesa_is_multisample_enabled(>ctx) && brw->ctx.Line.SmoothFlag && 
line_width < 1.5f) {
   /* For 1 pixel line thickness or less, the general
* anti-aliasing algorithm gives up, and a garbage line is
* generated.  Setting a Line Width of 0.0 specifies the
@@ -71,10 +66,18 @@ brw_get_line_width(struct brw_context *brw)
* bspec section 6.3.12.1 Zero-Width (Cosmetic) Line
* Rasterization.
*/
-  line_width_u3_7 = 0;
+  line_width = 0.0f;
}
 
-   return line_width_u3_7;
+   return line_width;
+}
+
+static inline uint32_t
+brw_get_line_width(struct brw_context *brw)
+{
+   float line_width = brw_get_line_width_float(brw);
+
+   return U_FIXED(line_width, 7);
 }
 
 #endif
-- 
git-series 0.9.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v03 25/38] i965: Port gen7+ 3DSTATE_SOL to genxml.

[Rafael Antognolli]

Emit 3DSTATE_SOL on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Add helpers to assign struct brw_address (Kristian)
v3:
   - Rename MOCS -> SOBufferMOCS
   - Do not re-declare MOCS macros (Ken).
   - Style and code reorganization (Ken).

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |   6 +-
 src/mesa/drivers/dri/i965/gen7_sol_state.c| 307 +-
 src/mesa/drivers/dri/i965/gen8_sol_state.c|  95 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 341 ++-
 5 files changed, 338 insertions(+), 412 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_sol_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 47680a7..bfcf57c 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -111,7 +111,6 @@ i965_FILES = \
gen8_hs_state.c \
gen8_multisample_state.c \
gen8_ps_state.c \
-   gen8_sol_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
gen8_vs_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 3df975a..94f758b 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -135,7 +135,6 @@ extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
-extern const struct brw_tracked_state gen7_sol_state;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
@@ -299,11 +298,6 @@ void gen8_upload_ps_state(struct brw_context *brw,
 void gen8_upload_ps_extra(struct brw_context *brw,
   const struct brw_wm_prog_data *prog_data);
 
-/* gen7_sol_state.c */
-void gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
-  const struct brw_vue_map *vue_map);
-void gen8_upload_3dstate_so_buffers(struct brw_context *brw);
-
 /* gen8_surface_state.c */
 
 void gen8_init_vtable_surface_functions(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c 
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index f1bd19c..f54b370 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -35,313 +35,6 @@
 #include "intel_buffer_objects.h"
 #include "main/transformfeedback.h"
 
-static void
-upload_3dstate_so_buffers(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_TRANSFORM_FEEDBACK */
-   struct gl_transform_feedback_object *xfb_obj =
-  ctx->TransformFeedback.CurrentObject;
-   const struct gl_transform_feedback_info *linked_xfb_info =
-  xfb_obj->program->sh.LinkedTransformFeedback;
-   int i;
-
-   /* Set up the up to 4 output buffers.  These are the ranges defined in the
-* gl_transform_feedback_object.
-*/
-   for (i = 0; i < 4; i++) {
-  struct intel_buffer_object *bufferobj =
-intel_buffer_object(xfb_obj->Buffers[i]);
-  struct brw_bo *bo;
-  uint32_t start, end;
-  uint32_t stride;
-
-  if (!xfb_obj->Buffers[i]) {
-/* The pitch of 0 in this command indicates that the buffer is
- * unbound and won't be written to.
- */
-BEGIN_BATCH(4);
-OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
-OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT));
-OUT_BATCH(0);
-OUT_BATCH(0);
-ADVANCE_BATCH();
-
-continue;
-  }
-
-  stride = linked_xfb_info->Buffers[i].Stride * 4;
-
-  start = xfb_obj->Offset[i];
-  assert(start % 4 == 0);
-  end = ALIGN(start + xfb_obj->Size[i], 4);
-  bo = intel_bufferobj_buffer(brw, bufferobj, start, end - start);
-  assert(end <= bo->size);
-
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
-  OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) | stride);
-  OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
-  OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
-  ADVANCE_BATCH();
-   }
-}
-
-/**
- * Outputs the 3DSTATE_SO_DECL_LIST command.
- *
- * The data output is a series of 64-bit entries containing a SO_DECL per
- * stream.  We only have one stream of rendering coming out of the GS unit, so
- * we only emit stream 0 (low 16 bits) SO_DECLs.
- */
-void
-gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
- const struc

[Mesa-dev] [PATCH v03 20/38] i965: Port Gen8+ 3DSTATE_RASTER state to genxml.

[Rafael Antognolli]

Emits 3DSTATE_RASTER from genX_state_upload.c using pack structs from
genxml.

v3:
   - Style fixes (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_state.h |   1 +-
 src/mesa/drivers/dri/i965/gen8_sf_state.c | 125 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 124 ++-
 3 files changed, 123 insertions(+), 127 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index c26be41..3a10a8a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -156,7 +156,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
-extern const struct brw_tracked_state gen8_raster_state;
 extern const struct brw_tracked_state gen8_sbe_state;
 extern const struct brw_tracked_state gen8_sf_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c 
b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 41e94fb..d47adcd 100644
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -224,128 +224,3 @@ const struct brw_tracked_state gen8_sf_state = {
},
.emit = upload_sf,
 };
-
-static void
-upload_raster(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   uint32_t dw1 = 0;
-
-   /* _NEW_BUFFERS */
-   bool render_to_fbo = _mesa_is_user_fbo(brw->ctx.DrawBuffer);
-
-   /* _NEW_POLYGON */
-   if (ctx->Polygon._FrontBit == render_to_fbo)
-  dw1 |= GEN8_RASTER_FRONT_WINDING_CCW;
-
-   if (ctx->Polygon.CullFlag) {
-  switch (ctx->Polygon.CullFaceMode) {
-  case GL_FRONT:
- dw1 |= GEN8_RASTER_CULL_FRONT;
- break;
-  case GL_BACK:
- dw1 |= GEN8_RASTER_CULL_BACK;
- break;
-  case GL_FRONT_AND_BACK:
- dw1 |= GEN8_RASTER_CULL_BOTH;
- break;
-  default:
- unreachable("not reached");
-  }
-   } else {
-  dw1 |= GEN8_RASTER_CULL_NONE;
-   }
-
-   /* _NEW_POINT */
-   if (ctx->Point.SmoothFlag)
-  dw1 |= GEN8_RASTER_SMOOTH_POINT_ENABLE;
-
-   if (_mesa_is_multisample_enabled(ctx))
-  dw1 |= GEN8_RASTER_API_MULTISAMPLE_ENABLE;
-
-   if (ctx->Polygon.OffsetFill)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
-
-   if (ctx->Polygon.OffsetLine)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
-
-   if (ctx->Polygon.OffsetPoint)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
-
-   switch (ctx->Polygon.FrontMode) {
-   case GL_FILL:
-  dw1 |= GEN6_SF_FRONT_SOLID;
-  break;
-   case GL_LINE:
-  dw1 |= GEN6_SF_FRONT_WIREFRAME;
-  break;
-   case GL_POINT:
-  dw1 |= GEN6_SF_FRONT_POINT;
-  break;
-
-   default:
-  unreachable("not reached");
-   }
-
-   switch (ctx->Polygon.BackMode) {
-   case GL_FILL:
-  dw1 |= GEN6_SF_BACK_SOLID;
-  break;
-   case GL_LINE:
-  dw1 |= GEN6_SF_BACK_WIREFRAME;
-  break;
-   case GL_POINT:
-  dw1 |= GEN6_SF_BACK_POINT;
-  break;
-   default:
-  unreachable("not reached");
-   }
-
-   /* _NEW_LINE */
-   if (ctx->Line.SmoothFlag)
-  dw1 |= GEN8_RASTER_LINE_AA_ENABLE;
-
-   /* _NEW_SCISSOR */
-   if (ctx->Scissor.EnableFlags)
-  dw1 |= GEN8_RASTER_SCISSOR_ENABLE;
-
-   /* _NEW_TRANSFORM */
-   if (!ctx->Transform.DepthClamp) {
-  if (brw->gen >= 9) {
- dw1 |= GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE |
-GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE;
-  } else {
- dw1 |= GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE;
-  }
-   }
-
-   /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
-   if (ctx->IntelConservativeRasterization) {
-  if (brw->gen >= 9)
- dw1 |= GEN9_RASTER_CONSERVATIVE_RASTERIZATION_ENABLE;
-   }
-
-   BEGIN_BATCH(5);
-   OUT_BATCH(_3DSTATE_RASTER << 16 | (5 - 2));
-   OUT_BATCH(dw1);
-   OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
-   OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
-   OUT_BATCH_F(ctx->Polygon.OffsetClamp); /* global depth offset clamp */
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen8_raster_state = {
-   .dirty = {
-  .mesa  = _NEW_BUFFERS |
-   _NEW_LINE |
-   _NEW_MULTISAMPLE |
-   _NEW_POINT |
-   _NEW_POLYGON |
-   _NEW_SCISSOR |
-   _NEW_TRANSFORM,
-  .brw   = BRW_NEW_BLORP |
-   BRW_NEW_CONTEXT |
-   BRW_NEW_CONSERVATIVE_RASTERIZATION,
-   },
-   .emit = upload_raster,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c

[Mesa-dev] [PATCH v03 36/38] i965: Port gen6+ multisample state emitting code to genxml.

[Rafael Antognolli]

Emit 3DSTATE_MULTISAMPLE using brw_batch_emit.

v3:
   - Remove dead code (Ken)
   - Simplify #if/#endif (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_context.h|   9 +-
 src/mesa/drivers/dri/i965/brw_state.h  |   2 +-
 src/mesa/drivers/dri/i965/gen6_multisample_state.c | 103 +--
 src/mesa/drivers/dri/i965/gen8_multisample_state.c |  18 +--
 src/mesa/drivers/dri/i965/genX_state_upload.c  | 100 +-
 5 files changed, 96 insertions(+), 136 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 5e627ae..df7b6eb 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1579,15 +1579,6 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
   int dstX0, int dstY0,
   int width, int height);
 
-/* gen6_multisample_state.c */
-unsigned
-gen6_determine_sample_mask(struct brw_context *brw);
-
-void
-gen6_emit_3dstate_multisample(struct brw_context *brw,
-  unsigned num_samples);
-void
-gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask);
 void
 gen6_get_sample_position(struct gl_context *ctx,
  struct gl_framebuffer *fb,
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index acb7334..2b5b1c4 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,7 +109,6 @@ extern const struct brw_tracked_state 
gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_binding_table;
-extern const struct brw_tracked_state gen6_multisample_state;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
 extern const struct brw_tracked_state gen6_sol_surface;
@@ -122,7 +121,6 @@ extern const struct brw_tracked_state 
gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_index_buffer;
-extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_vf_topology;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c 
b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index a59ffec..bfa84fb 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -118,106 +118,3 @@ gen6_set_sample_maps(struct gl_context *ctx)
memcpy(ctx->Const.SampleMap8x, map_8x, sizeof(map_8x));
memcpy(ctx->Const.SampleMap16x, map_16x, sizeof(map_16x));
 }
-
-/**
- * 3DSTATE_MULTISAMPLE
- */
-void
-gen6_emit_3dstate_multisample(struct brw_context *brw,
-  unsigned num_samples)
-{
-   uint32_t number_of_multisamples = 0;
-   uint32_t sample_positions_3210 = 0;
-   uint32_t sample_positions_7654 = 0;
-
-   assert(brw->gen < 8);
-
-   switch (num_samples) {
-   case 0:
-   case 1:
-  number_of_multisamples = MS_NUMSAMPLES_1;
-  break;
-   case 4:
-  number_of_multisamples = MS_NUMSAMPLES_4;
-  sample_positions_3210 = brw_multisample_positions_4x;
-  break;
-   case 8:
-  number_of_multisamples = MS_NUMSAMPLES_8;
-  sample_positions_3210 = brw_multisample_positions_8x[0];
-  sample_positions_7654 = brw_multisample_positions_8x[1];
-  break;
-   default:
-  unreachable("Unrecognized num_samples in gen6_emit_3dstate_multisample");
-   }
-
-   int len = brw->gen >= 7 ? 4 : 3;
-   BEGIN_BATCH(len);
-   OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
-   OUT_BATCH(MS_PIXEL_LOCATION_CENTER | number_of_multisamples);
-   OUT_BATCH(sample_positions_3210);
-   if (brw->gen >= 7)
-  OUT_BATCH(sample_positions_7654);
-   ADVANCE_BATCH();
-}
-
-unsigned
-gen6_determine_sample_mask(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   float coverage = 1.0f;
-   float coverage_invert = false;
-   unsigned sample_mask = ~0u;
-
-   /* BRW_NEW_NUM_SAMPLES */
-   unsigned num_samples = brw->num_samples;
-
-   if (_mesa_is_multisample_enabled(ctx)) {
-  if (ctx->Multisample.SampleCoverage) {
- coverage = ctx->Multisample.SampleCoverageValue;
- coverage_invert = ctx->Multisample.SampleCoverageInvert;
-  }
-  if (ctx->Multisample.SampleMask) {
- sample_mask = ctx->Multisample.SampleMaskValue;
-  }
-   }
-
-   if (num_samples > 1) {
-  int coverag

[Mesa-dev] [PATCH v03 12/38] i965: Split out enum from brw_eu_defines.h

[Rafael Antognolli]

We need to use some enums inside genX_state_upload.c, but including the
whole header will cause several conflicts between things defined in this
header and the genxml auto-generated headers.

So create a separate header that is included both by brw_eu_defines.h
and genX_state_upload.c.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Acked-by: Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/Makefile.sources  |  1 +-
 src/intel/compiler/brw_defines_common.h | 46 ++-
 src/intel/compiler/brw_eu_defines.h | 22 +
 3 files changed, 48 insertions(+), 21 deletions(-)
 create mode 100644 src/intel/compiler/brw_defines_common.h

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index e9a39a6..652f376 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -27,6 +27,7 @@ COMPILER_FILES = \
compiler/brw_compiler.h \
compiler/brw_dead_control_flow.cpp \
compiler/brw_dead_control_flow.h \
+   compiler/brw_defines_common.h \
compiler/brw_disasm.c \
compiler/brw_eu.c \
compiler/brw_eu_compact.c \
diff --git a/src/intel/compiler/brw_defines_common.h 
b/src/intel/compiler/brw_defines_common.h
new file mode 100644
index 000..fdae125
--- /dev/null
+++ b/src/intel/compiler/brw_defines_common.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef BRW_DEFINES_COMMON_H
+#endif // BRW_DEFINES_COMMON_H
+
+enum brw_pixel_shader_computed_depth_mode {
+   BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
+   BRW_PSCDEPTH_ON= 1, /* PS computes depth; no guarantee about value */
+   BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
+   BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
+};
+
+enum brw_barycentric_mode {
+   BRW_BARYCENTRIC_PERSPECTIVE_PIXEL   = 0,
+   BRW_BARYCENTRIC_PERSPECTIVE_CENTROID= 1,
+   BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE  = 2,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL= 3,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
+   BRW_BARYCENTRIC_MODE_COUNT  = 6
+};
+#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
+   ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
+(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
+(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
diff --git a/src/intel/compiler/brw_eu_defines.h 
b/src/intel/compiler/brw_eu_defines.h
index 13a70f6..51f9cbc 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -33,6 +33,7 @@
 #define BRW_EU_DEFINES_H
 
 #include "util/macros.h"
+#include "brw_defines_common.h"
 
 /* The following hunk, up-to "Execution Unit" is used by both the
  * intel/compiler and i965 codebase. */
@@ -72,27 +73,6 @@
 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x16
 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
 
-enum brw_barycentric_mode {
-   BRW_BARYCENTRIC_PERSPECTIVE_PIXEL   = 0,
-   BRW_BARYCENTRIC_PERSPECTIVE_CENTROID= 1,
-   BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE  = 2,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL= 3,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
-   BRW_BARYCENTRIC_MODE_COUNT  = 6
-};
-#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
-   ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
-(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
-(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
-
-enum brw_pixel_shader_computed_depth_mode {
-   BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
-   BRW_PSCDEPTH_ON= 1, /* PS computes depth; no guarantee about v

[Mesa-dev] [PATCH v03 17/38] genxml: Add rules to build gen4, gen45 and ge5.

[Rafael Antognolli]

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.am  | 12 
 src/mesa/drivers/dri/i965/Makefile.sources |  9 +
 src/mesa/drivers/dri/i965/brw_state.h  |  1 +
 3 files changed, 22 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/Makefile.am 
b/src/mesa/drivers/dri/i965/Makefile.am
index 4e9b062..762aefc 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -46,12 +46,24 @@ AM_CFLAGS = \
 AM_CXXFLAGS = $(AM_CFLAGS)
 
 I965_PERGEN_LIBS = \
+   libi965_gen4.la \
+   libi965_gen45.la \
+   libi965_gen5.la \
libi965_gen6.la \
libi965_gen7.la \
libi965_gen75.la \
libi965_gen8.la \
libi965_gen9.la
 
+libi965_gen4_la_SOURCES = $(i965_gen4_FILES)
+libi965_gen4_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=40
+
+libi965_gen45_la_SOURCES = $(i965_gen45_FILES)
+libi965_gen45_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=45
+
+libi965_gen5_la_SOURCES = $(i965_gen5_FILES)
+libi965_gen5_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=50
+
 libi965_gen6_la_SOURCES = $(i965_gen6_FILES)
 libi965_gen6_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=60
 
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index db55a3f..41f4d83 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -160,6 +160,15 @@ i965_FILES = \
intel_upload.c \
libdrm_macros.h
 
+i965_gen4_FILES = \
+   genX_state_upload.c
+
+i965_gen45_FILES = \
+   genX_state_upload.c
+
+i965_gen5_FILES = \
+   genX_state_upload.c
+
 i965_gen6_FILES = \
genX_blorp_exec.c \
genX_state_upload.c
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 008326a..6403570 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -446,6 +446,7 @@ void brw_copy_pipeline_atoms(struct brw_context *brw,
  const struct brw_tracked_state **atoms,
  int num_atoms);
 void gen4_init_atoms(struct brw_context *brw);
+void gen45_init_atoms(struct brw_context *brw);
 void gen5_init_atoms(struct brw_context *brw);
 void gen6_init_atoms(struct brw_context *brw);
 void gen7_init_atoms(struct brw_context *brw);
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v03 09/38] genxml: Rename "Function Enable" to "Enable".

[Rafael Antognolli]

Rename that field name on genxml for:
   - 3DSTATE_GS - gen6+
   - 3DSTATE_DS - gen7+
   - 3DSTATE_HS - gen7+

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/genxml/gen6.xml| 2 +-
 src/intel/genxml/gen7.xml| 6 +++---
 src/intel/genxml/gen75.xml   | 6 +++---
 src/intel/genxml/gen8.xml| 6 +++---
 src/intel/genxml/gen9.xml| 6 +++---
 src/intel/vulkan/genX_pipeline.c | 6 +++---
 6 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 2173dbf..2cb9419 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1014,7 +1014,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 2ac096e..75954fe 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1101,7 +1101,7 @@
 
 
 
-
+
   
 
   
@@ -1162,7 +1162,7 @@
   
 
 
-
+
 
   
 
@@ -1199,7 +1199,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 6d2bfaa..1e64fef 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -1292,7 +1292,7 @@
 
 
 
-
+
   
 
   
@@ -1440,7 +1440,7 @@
   
 
 
-
+
 
   
   
@@ -1484,7 +1484,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 05e228c..7f60ea4 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -1350,7 +1350,7 @@
 
 
 
-
+
 
 
 
@@ -1506,7 +1506,7 @@
   
 
 
-
+
 
   
   
@@ -1555,7 +1555,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 191c74c..445a366 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -1412,7 +1412,7 @@
 
 
 
-
+
 
 
 
@@ -1611,7 +1611,7 @@
   
 
 
-
+
 
   
   
@@ -1661,7 +1661,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 74d6f9a..954273b 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1192,7 +1192,7 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
 
anv_batch_emit(>batch, GENX(3DSTATE_HS), hs) {
-  hs.FunctionEnable = true;
+  hs.Enable = true;
   hs.StatisticsEnable = true;
   hs.KernelStartPointer = tcs_bin->kernel.offset;
 
@@ -1222,7 +1222,7 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
}
 
anv_batch_emit(>batch, GENX(3DSTATE_DS), ds) {
-  ds.FunctionEnable = true;
+  ds.Enable = true;
   ds.StatisticsEnable = true;
   ds.KernelStartPointer = tes_bin->kernel.offset;
 
@@ -1275,7 +1275,7 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 
anv_batch_emit(>batch, GENX(3DSTATE_GS), gs) {
-  gs.FunctionEnable  = true;
+  gs.Enable  = true;
   gs.StatisticsEnable= true;
   gs.KernelStartPointer  = gs_bin->kernel.offset;
   gs.DispatchMode= gs_prog_data->base.dispatch_mode;
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v03 28/38] i965: Port gen8+ 3DSTATE_PS_EXTRA to genxml.

[Rafael Antognolli]

Emit 3DSTATE_PS_EXTRA on Gen8+ using brw_batch_emit helper, that uses
pack structs from genxml.

v3:
   - Style fixes and moving code around to be cleaner (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  10 +-
 src/mesa/drivers/dri/i965/gen8_ps_state.c | 138 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c |  89 +++-
 4 files changed, 88 insertions(+), 150 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_ps_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index da09df8..7f25ae1 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -109,7 +109,6 @@ i965_FILES = \
gen8_gs_state.c \
gen8_hs_state.c \
gen8_multisample_state.c \
-   gen8_ps_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
gen8_vs_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 5010237..a87bf3a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -146,7 +146,6 @@ extern const struct brw_tracked_state gen8_index_buffer;
 extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
-extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
@@ -284,15 +283,6 @@ void brw_update_renderbuffer_surfaces(struct brw_context 
*brw,
 void gen7_check_surface_setup(uint32_t *surf, bool is_render_target);
 void gen7_init_vtable_surface_functions(struct brw_context *brw);
 
-/* gen8_ps_state.c */
-void gen8_upload_ps_state(struct brw_context *brw,
-  const struct brw_stage_state *stage_state,
-  const struct brw_wm_prog_data *prog_data,
-  uint32_t fast_clear_op);
-
-void gen8_upload_ps_extra(struct brw_context *brw,
-  const struct brw_wm_prog_data *prog_data);
-
 /* gen8_surface_state.c */
 
 void gen8_init_vtable_surface_functions(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c 
b/src/mesa/drivers/dri/i965/gen8_ps_state.c
deleted file mode 100644
index 1a4a680..000
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Copyright © 2012 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include 
-#include "program/program.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_wm.h"
-#include "intel_batchbuffer.h"
-
-void
-gen8_upload_ps_extra(struct brw_context *brw,
- const struct brw_wm_prog_data *prog_data)
-{
-   struct gl_context *ctx = >ctx;
-   uint32_t dw1 = 0;
-
-   dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
-   dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
-
-   if (prog_data->uses_kill)
-  dw1 |= GEN8_PSX_KILL_ENABLE;
-
-   if (prog_data->num_varying_inputs != 0)
-  dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
-
-   if (prog_data->uses_src_depth)
-  dw1 |= GEN8_PSX_USES_SOURCE_DEPTH;
-
-   if (prog_data->uses_src_w)
-  dw1 |= GEN8_PSX_USES_SOURCE_W;
-
-   if (prog_data->persample_dispatch)
-  dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
-
-   /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
-   if (prog_data->uses_sample_mask) 

[Mesa-dev] [PATCH v03 18/38] i965: Port Gen6+ DEPTH_STENCIL state to genxml.

[Rafael Antognolli]

From: Kenneth Graunke <kenn...@whitecape.org>

This emits 3DSTATE_WM_DEPTH_STENCIL on Gen8+ or DEPTH_STENCIL_STATE
(and the relevant pointer packets) on Gen6-7.5 from a single function.

v3:
   - Watch for BRW_NEW_BATCH too on gen8+ (Ken)

Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/brw_state.h |   2 +-
 src/mesa/drivers/dri/i965/gen6_depthstencil.c | 114 +--
 src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c | 118 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 103 -
 5 files changed, 101 insertions(+), 238 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_depthstencil.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 41f4d83..b085251 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -80,7 +80,6 @@ i965_FILES = \
gen6_clip_state.c \
gen6_constant_state.c \
gen6_depth_state.c \
-   gen6_depthstencil.c \
gen6_gs_state.c \
gen6_multisample_state.c \
gen6_queryobj.c \
@@ -119,7 +118,6 @@ i965_FILES = \
gen8_surface_state.c \
gen8_viewport_state.c \
gen8_vs_state.c \
-   gen8_wm_depth_stencil.c \
hsw_queryobj.c \
hsw_sol.c \
intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 6403570..7b6d718 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -112,7 +112,6 @@ extern const struct brw_tracked_state gen6_blend_state;
 extern const struct brw_tracked_state gen6_clip_state;
 extern const struct brw_tracked_state gen6_sf_and_clip_viewports;
 extern const struct brw_tracked_state gen6_color_calc_state;
-extern const struct brw_tracked_state gen6_depth_stencil_state;
 extern const struct brw_tracked_state gen6_gs_state;
 extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
@@ -157,7 +156,6 @@ extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
-extern const struct brw_tracked_state gen8_wm_depth_stencil;
 extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_raster_state;
 extern const struct brw_tracked_state gen8_sbe_state;
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c 
b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
deleted file mode 100644
index 0f9626c..000
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt <e...@anholt.net>
- *
- */
-
-#include "intel_batchbuffer.h"
-#include "intel_fbo.h"
-#include "brw_context.h"
-#include "brw_defines.h"
-#include "brw_state.h"
-
-static void
-gen6_upload_depth_stencil_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   struct gen6_depth_stencil_state *ds;
-   struct intel_renderbuffer *depth_irb;
-
-   /* _NEW_BUFFERS */
-   depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
-
-   ds = brw_state_batch(brw, sizeof(*ds), 64,
-   >cc.depth_stencil_state_offset);
-   memset(ds, 0, sizeof(*ds));
-
-   /* _NEW_STENCIL 

[Mesa-dev] [PATCH v03 26/38] i965: Port gen7+ 3DSTATE_PS to genxml.

[Rafael Antognolli]

Emit 3DSTATE_PS on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)
v3:
   - Style fixes and code cleanup (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/brw_state.h |   2 +-
 src/mesa/drivers/dri/i965/gen7_wm_state.c | 137 +---
 src/mesa/drivers/dri/i965/gen8_ps_state.c | 114 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 136 ++-
 4 files changed, 134 insertions(+), 255 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 94f758b..c55c175 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -132,7 +132,6 @@ extern const struct brw_tracked_state gen7_gs_state;
 extern const struct brw_tracked_state gen7_tcs_push_constants;
 extern const struct brw_tracked_state gen7_hs_state;
 extern const struct brw_tracked_state gen7_l3_state;
-extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
@@ -150,7 +149,6 @@ extern const struct brw_tracked_state 
gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
-extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c 
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 5efe55a..3173035 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -145,140 +145,3 @@ const struct brw_tracked_state gen7_wm_state = {
},
.emit = upload_wm_state,
 };
-
-static void
-gen7_upload_ps_state(struct brw_context *brw,
- const struct brw_stage_state *stage_state,
- const struct brw_wm_prog_data *prog_data,
- bool enable_dual_src_blend, unsigned sample_mask,
- unsigned fast_clear_op)
-{
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   uint32_t dw2, dw4, dw5, ksp0, ksp2;
-   const int max_threads_shift = brw->is_haswell ?
-  HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
-
-   dw2 = dw4 = dw5 = ksp2 = 0;
-
-   const unsigned sampler_count =
-  DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
-   dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
-
-   dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
-   GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
-
-   if (prog_data->base.use_alt_mode)
-  dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
-
-   /* Haswell requires the sample mask to be set in this packet as well as
-* in 3DSTATE_SAMPLE_MASK; the values should match. */
-   /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
-   if (brw->is_haswell)
-  dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
-
-   dw4 |= (devinfo->max_wm_threads - 1) << max_threads_shift;
-
-   if (prog_data->base.nr_params > 0)
-  dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
-
-   /* From the IVB PRM, volume 2 part 1, page 287:
-* "This bit is inserted in the PS payload header and made available to
-* the DataPort (either via the message header or via header bypass) to
-* indicate that oMask data (one or two phases) is included in Render
-* Target Write messages. If present, the oMask data is used to mask off
-* samples."
-*/
-   if (prog_data->uses_omask)
-  dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
-
-   /* From the IVB PRM, volume 2 part 1, page 287:
-* "If the PS kernel does not need the Position XY Offsets to
-* compute a Position Value, then this field should be programmed
-* to POSOFFSET_NONE."
-* "SW Recommendation: If the PS kernel needs the Position Offsets
-* to compute a Position XY value, this field should match Position
-* ZW Interpolation Mode to ensure a consistent position.xyzw
-* computation."
-* We only require XY sample offsets. So, this recommendation doesn't
-* look useful at the moment. We might need this in future.
-*/
-   if (prog_data->uses_pos_offset)
-  dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
-   else
-  dw4 |= GEN7_PS_POSOFFSET_NONE;
-
-   /* The hardware wedges if you have this bit set but don't turn on any dual
-* source blend factors.
-*/
-   if (enable_dual_src_blend)
-  dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
-
-   /* BRW_NEW_FS_PROG_DATA */
-   if (prog_data-&g

[Mesa-dev] [PATCH v03 23/38] i965: Port Gen7+ 3DSTATE_SBE state to genxml.

[Rafael Antognolli]

Emit 3DSTATE_SBE on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use ACTIVE_COMPONENT_XYZW from gen9.xml.
v3:
   - Style fixes (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/brw_state.h |   2 +-
 src/mesa/drivers/dri/i965/gen7_sf_state.c | 109 +--
 src/mesa/drivers/dri/i965/gen8_sf_state.c | 153 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 126 ++--
 5 files changed, 118 insertions(+), 274 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_sf_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_sf_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index b085251..81759ed 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -97,7 +97,6 @@ i965_FILES = \
gen7_hs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
-   gen7_sf_state.c \
gen7_sol_state.c \
gen7_te_state.c \
gen7_urb.c \
@@ -113,7 +112,6 @@ i965_FILES = \
gen8_hs_state.c \
gen8_multisample_state.c \
gen8_ps_state.c \
-   gen8_sf_state.c \
gen8_sol_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 594757c..bc68c2c 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -134,7 +134,6 @@ extern const struct brw_tracked_state gen7_hs_state;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_sbe_state;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_sol_state;
 extern const struct brw_tracked_state gen7_te_state;
@@ -154,7 +153,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
-extern const struct brw_tracked_state gen8_sbe_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c 
b/src/mesa/drivers/dri/i965/gen7_sf_state.c
deleted file mode 100644
index 7ab8a99..000
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "main/macros.h"
-#include "main/fbobject.h"
-#include "main/framebuffer.h"
-#include "intel_batchbuffer.h"
-
-static void
-upload_sbe_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_FS_PROG_DATA */
-   const struct brw_wm_prog_data *wm_prog_data =
-  brw_wm_prog_data(brw->wm.base.prog_data);
-   uint32_t num_outputs = wm_prog_data->num_varying_inputs;
-   uint32_t dw1;
-   uint32_t point_sprite_enables;
-   int i;
-   uint16_t attr_overrides[16];
-   /* _NEW_BUFFERS */
-   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
-   uint32_t point_sprite_origin;
-
-   /* FINISHME: Attribute Swizzle Control Mode? */
-   dw1 = GEN7_SBE_SWIZZLE_ENABLE | num_outputs << GEN7_SBE_NUM_OUTPU

[Mesa-dev] [PATCH v03 22/38] i965: Port gen6+ 3DSTATE_SF to genxml.

[Rafael Antognolli]

Emit sf state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.

v3:
   - Reorganize code and reduce #if/#endif's (Ken)
   - Style fixes (Ken)
   - Always set AALINEDISTANCE_TRUE (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_state.h |   3 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c | 189 +-
 src/mesa/drivers/dri/i965/gen7_sf_state.c | 156 +---
 src/mesa/drivers/dri/i965/gen8_sf_state.c |  73 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 420 ++-
 5 files changed, 417 insertions(+), 424 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 3a10a8a..594757c 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -119,7 +119,6 @@ extern const struct brw_tracked_state 
gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
 extern const struct brw_tracked_state gen6_scissor_state;
 extern const struct brw_tracked_state gen6_sol_surface;
-extern const struct brw_tracked_state gen6_sf_state;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
@@ -137,7 +136,6 @@ extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sbe_state;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
-extern const struct brw_tracked_state gen7_sf_state;
 extern const struct brw_tracked_state gen7_sol_state;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
@@ -157,7 +155,6 @@ extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_sbe_state;
-extern const struct brw_tracked_state gen8_sf_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 0f118b6..45b5769 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -263,192 +263,3 @@ calculate_attr_overrides(const struct brw_context *brw,
 */
*urb_entry_read_length = ALIGN(max_source_attr + 1, 2) / 2;
 }
-
-
-static void
-upload_sf_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_FS_PROG_DATA */
-   const struct brw_wm_prog_data *wm_prog_data =
-  brw_wm_prog_data(brw->wm.base.prog_data);
-   uint32_t num_outputs = wm_prog_data->num_varying_inputs;
-   uint32_t dw1, dw2, dw3, dw4;
-   uint32_t point_sprite_enables;
-   int i;
-   /* _NEW_BUFFER */
-   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
-   const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
-
-   float point_size;
-   uint16_t attr_overrides[16];
-   uint32_t point_sprite_origin;
-
-   dw1 = GEN6_SF_SWIZZLE_ENABLE | num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT;
-   dw2 = GEN6_SF_STATISTICS_ENABLE;
-   dw3 = GEN6_SF_SCISSOR_ENABLE | GEN6_SF_LINE_AA_MODE_TRUE;
-   dw4 = 0;
-
-   if (brw->sf.viewport_transform_enable)
-   dw2 |= GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
-
-   /* _NEW_POLYGON */
-   if (ctx->Polygon._FrontBit == render_to_fbo)
-  dw2 |= GEN6_SF_WINDING_CCW;
-
-   if (ctx->Polygon.OffsetFill)
-   dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
-
-   if (ctx->Polygon.OffsetLine)
-   dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
-
-   if (ctx->Polygon.OffsetPoint)
-   dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
-
-   switch (ctx->Polygon.FrontMode) {
-   case GL_FILL:
-   dw2 |= GEN6_SF_FRONT_SOLID;
-   break;
-
-   case GL_LINE:
-   dw2 |= GEN6_SF_FRONT_WIREFRAME;
-   break;
-
-   case GL_POINT:
-   dw2 |= GEN6_SF_FRONT_POINT;
-   break;
-
-   default:
-   unreachable("not reached");
-   }
-
-   switch (ctx->Polygon.BackMode) {
-   case GL_FILL:
-   dw2 |= GEN6_SF_BACK_SOLID;
-   break;
-
-   case GL_LINE:
-   dw2 |= GEN6_SF_BACK_WIREFRAME;
-   break;
-
-   case GL_POINT:
-   dw2 |= GEN6_SF_BACK_POINT;
-   break;
-
-   default:
-   unreachable("not reached");
-   }
-
-   /* _NEW_POLYGON */
-   if (ctx->Polygon.CullFlag) {
-  switch (ctx->Polygon.CullFaceMode) {
-  case GL_FRONT:
-dw3 |= GEN6_SF_CULL_FRONT;
-break;
-  case GL_BACK:
-dw3 |= GEN6_SF_CULL_BACK;
-break;
-  case GL_FRONT_AND_BACK:
-dw3 |= GEN6_SF_CULL_BOTH;
-break;
-  default:
-unre

[Mesa-dev] [PATCH v03 24/38] i965: Remove calculate_attr_overrides.

[Rafael Antognolli]

This function now lives inside genX_state_upload.c.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/Makefile.sources |   1 +-
 src/mesa/drivers/dri/i965/brw_state.h  |   8 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c  | 265 +--
 3 files changed, 274 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_sf_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 81759ed..47680a7 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -85,7 +85,6 @@ i965_FILES = \
gen6_queryobj.c \
gen6_sampler_state.c \
gen6_scissor_state.c \
-   gen6_sf_state.c \
gen6_sol.c \
gen6_urb.c \
gen6_viewport_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index bc68c2c..3df975a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -339,14 +339,6 @@ gen6_upload_wm_state(struct brw_context *brw,
  bool line_stipple_enable, bool polygon_stipple_enable,
  bool statistic_enable);
 
-/* gen6_sf_state.c */
-void
-calculate_attr_overrides(const struct brw_context *brw,
- uint16_t *attr_overrides,
- uint32_t *point_sprite_enables,
- uint32_t *urb_entry_read_length,
- uint32_t *urb_entry_read_offset);
-
 /* gen6_surface_state.c */
 void gen6_init_vtable_surface_functions(struct brw_context *brw);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
deleted file mode 100644
index 45b5769..000
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt <e...@anholt.net>
- *
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "compiler/nir/nir.h"
-#include "main/macros.h"
-#include "main/fbobject.h"
-#include "main/framebuffer.h"
-#include "intel_batchbuffer.h"
-
-/**
- * Determine the appropriate attribute override value to store into the
- * 3DSTATE_SF structure for a given fragment shader attribute.  The attribute
- * override value contains two pieces of information: the location of the
- * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
- * flag indicating whether to "swizzle" the attribute based on the direction
- * the triangle is facing.
- *
- * If an attribute is "swizzled", then the given VUE location is used for
- * front-facing triangles, and the VUE location that immediately follows is
- * used for back-facing triangles.  We use this to implement the mapping from
- * gl_FrontColor/gl_BackColor to gl_Color.
- *
- * urb_entry_read_offset is the offset into the VUE at which the SF unit is
- * being instructed to begin reading attribute data.  It can be set to a
- * nonzero value to prevent the SF unit from wasting time reading elements of
- * the VUE that are not needed by the fragment shader.  It is measured in
- * 256-bit increments.
- */
-static uint32_t
-get_attr_override(const struct brw_vue_map *vue_map, int urb_entry_read_offset,
-  int fs_attr, bool two_side_color, uint32_t *max_source_attr)
-{
-   /* Find the VUE slot for this attribute. */
-   int slot = vue_map->varying_to_slot[fs_attr];
-
-   /* Viewport and Layer are stored in the VUE header.  We need to override
-   

[Mesa-dev] [PATCH v03 29/38] i965: Port gen6+ 3DSTATE_VS to genxml.

[Rafael Antognolli]

Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)
v3:
   - Bring back some comments for gen6 and remove _NEW_TRANSFORM blocks
   from gen7+.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/brw_state.h |   3 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c | 113 +-
 src/mesa/drivers/dri/i965/gen7_vs_state.c |  87 +-
 src/mesa/drivers/dri/i965/gen8_vs_state.c |  96 +--
 src/mesa/drivers/dri/i965/genX_state_upload.c | 127 ++-
 6 files changed, 124 insertions(+), 304 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_vs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 7f25ae1..95d29ac 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -100,7 +100,6 @@ i965_FILES = \
gen7_te_state.c \
gen7_urb.c \
gen7_viewport_state.c \
-   gen7_vs_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
gen8_depth_state.c \
@@ -111,7 +110,6 @@ i965_FILES = \
gen8_multisample_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
-   gen8_vs_state.c \
hsw_queryobj.c \
hsw_sol.c \
intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index a87bf3a..72d63f6 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -123,7 +123,6 @@ extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
-extern const struct brw_tracked_state gen6_vs_state;
 extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_ds_state;
@@ -136,7 +135,6 @@ extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
-extern const struct brw_tracked_state gen7_vs_state;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_ds_state;
@@ -149,7 +147,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
-extern const struct brw_tracked_state gen8_vs_state;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
 
 static inline bool
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 17b8118..b2d2306 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -68,116 +68,3 @@ const struct brw_tracked_state gen6_vs_push_constants = {
},
.emit = gen6_upload_vs_push_constants,
 };
-
-static void
-upload_vs_state(struct brw_context *brw)
-{
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   const struct brw_stage_state *stage_state = >vs.base;
-   const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
-   const struct brw_vue_prog_data *vue_prog_data =
-  brw_vue_prog_data(stage_state->prog_data);
-   uint32_t floating_point_mode = 0;
-
-   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
-* 3DSTATE_VS, Dword 5.0 "VS Function Enable":
-*
-*   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
-*   command that causes the VS Function Enable to toggle. Pipeline
-*   flush can be executed by sending a PIPE_CONTROL command with CS
-*   stall bit set and a post sync operation.
-*
-* We've already done such a flush at the start of state upload, so we
-* don't need to do another one here.
-*/
-
-   if (stage_state->push_const_size == 0) {
-  /* Disable the push constant buffers. */
-  BEGIN_BATCH(5);
-  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(5);
-  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
-   GEN6_CONSTANT_BUFFER_0_ENABLE |
-   (5 - 2));
-  /* Pointer to the VS const

[Mesa-dev] [PATCH v03 16/38] i965: Get real per-gen atom lists

[Rafael Antognolli]

From: Kenneth Graunke 

Make atoms initalization compile conditionally based on the target
platform.
---
 src/mesa/drivers/dri/i965/brw_state.h |  12 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c  | 385 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 340 +-
 3 files changed, 369 insertions(+), 368 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index ec79a4e..008326a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -441,6 +441,18 @@ void brw_calculate_guardband_size(const struct 
gen_device_info *devinfo,
   float *xmin, float *xmax,
   float *ymin, float *ymax);
 
+void brw_copy_pipeline_atoms(struct brw_context *brw,
+ enum brw_pipeline pipeline,
+ const struct brw_tracked_state **atoms,
+ int num_atoms);
+void gen4_init_atoms(struct brw_context *brw);
+void gen5_init_atoms(struct brw_context *brw);
+void gen6_init_atoms(struct brw_context *brw);
+void gen7_init_atoms(struct brw_context *brw);
+void gen75_init_atoms(struct brw_context *brw);
+void gen8_init_atoms(struct brw_context *brw);
+void gen9_init_atoms(struct brw_context *brw);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 9c0b82c..6c9c748 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -45,341 +45,6 @@
 #include "brw_cs.h"
 #include "main/framebuffer.h"
 
-static const struct brw_tracked_state *gen4_atoms[] =
-{
-   /* Once all the programs are done, we know how large urb entry
-* sizes need to be and can decide if we need to change the urb
-* layout.
-*/
-   _curbe_offsets,
-   _recalculate_urb_fence,
-
-   _cc_vp,
-   _cc_unit,
-
-   /* Surface state setup.  Must come before the VS/WM unit.  The binding
-* table upload must be last.
-*/
-   _vs_pull_constants,
-   _wm_pull_constants,
-   _renderbuffer_surfaces,
-   _renderbuffer_read_surfaces,
-   _texture_surfaces,
-   _vs_binding_table,
-   _wm_binding_table,
-
-   _fs_samplers,
-   _vs_samplers,
-
-   /* These set up state for brw_psp_urb_cbs */
-   _wm_unit,
-   _sf_vp,
-   _sf_unit,
-   _vs_unit,   /* always required, enabled or not */
-   _clip_unit,
-   _gs_unit,
-
-   /* Command packets:
-*/
-   _invariant_state,
-
-   _binding_table_pointers,
-   _blend_constant_color,
-
-   _depthbuffer,
-
-   _polygon_stipple,
-   _polygon_stipple_offset,
-
-   _line_stipple,
-
-   _psp_urb_cbs,
-
-   _drawing_rect,
-   _indices, /* must come before brw_vertices */
-   _index_buffer,
-   _vertices,
-
-   _constant_buffer
-};
-
-static const struct brw_tracked_state *gen6_atoms[] =
-{
-   _sf_and_clip_viewports,
-
-   /* Command packets: */
-
-   _cc_vp,
-   _viewport_state,   /* must do after *_vp stages */
-
-   _urb,
-   _blend_state,  /* must do before cc unit */
-   _color_calc_state, /* must do before cc unit */
-   _depth_stencil_state,  /* must do before cc unit */
-
-   _vs_push_constants, /* Before vs_state */
-   _gs_push_constants, /* Before gs_state */
-   _wm_push_constants, /* Before wm_state */
-
-   /* Surface state setup.  Must come before the VS/WM unit.  The binding
-* table upload must be last.
-*/
-   _vs_pull_constants,
-   _vs_ubo_surfaces,
-   _gs_pull_constants,
-   _gs_ubo_surfaces,
-   _wm_pull_constants,
-   _wm_ubo_surfaces,
-   _renderbuffer_surfaces,
-   _renderbuffer_read_surfaces,
-   _texture_surfaces,
-   _sol_surface,
-   _vs_binding_table,
-   _gs_binding_table,
-   _wm_binding_table,
-
-   _fs_samplers,
-   _vs_samplers,
-   _gs_samplers,
-   _sampler_state,
-   _multisample_state,
-
-   _vs_state,
-   _gs_state,
-   _clip_state,
-   _sf_state,
-   _wm_state,
-
-   _scissor_state,
-
-   _binding_table_pointers,
-
-   _depthbuffer,
-
-   _polygon_stipple,
-   _polygon_stipple_offset,
-
-   _line_stipple,
-
-   _drawing_rect,
-
-   _indices, /* must come before brw_vertices */
-   _index_buffer,
-   _vertices,
-};
-
-static const struct brw_tracked_state *gen7_render_atoms[] =
-{
-   /* Command packets: */
-
-   _cc_vp,
-   _sf_clip_viewport,
-
-   _l3_state,
-   _push_constant_space,
-   _urb,
-   _blend_state,  /* must do before cc unit */
-   _color_calc_state, /* must do before cc unit */
-   _depth_stencil_state,  /* must do before cc unit */
-
-   _vs_image_surfaces, /* Before vs push/pull constants and binding table 
*/
-   _tcs_image_surfaces, /* Before tcs push/pull constants and binding 
table */
-   _tes_image_surfaces, /* Before tes push/pull constants and binding 
table */
-   _gs_image_surfaces, /* Before gs push/pull constants and binding table 
*/
-   _wm_image_surfaces, /* Before wm push/pull 

[Mesa-dev] [PATCH v03 35/38] i965: Port gen4+ emit vertices code to genxml.

[Rafael Antognolli]

Some code that was placed in brw_draw_upload.c and exported to be used
by gen8+ was also moved to genX_state_upload, and the respective symbols
are not exported anymore.

v2:
   - Remove code from brw_draw_upload too
   - Emit vertices for gen4-5 too.
   - Use helper to setup brw_address (Kristian)
   - Use macros for MOCS values.
   - Do not use #ifndef NDEBUG on code that is actually used (Ken)
v3:
   - Style and code clenup (Ken)
   - Keep some of the common code inside brw_draw_upload.c (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_draw_upload.c   | 454 +---
 src/mesa/drivers/dri/i965/brw_state.h |   2 +-
 src/mesa/drivers/dri/i965/gen8_draw_upload.c  | 330 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 560 ++-
 4 files changed, 556 insertions(+), 790 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c 
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 7846293..8b30151 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -242,86 +242,6 @@ double_types(struct brw_context *brw,
: double_types_float[size]);
 }
 
-static bool
-is_passthru_format(uint32_t format)
-{
-   switch (format) {
-   case ISL_FORMAT_R64_PASSTHRU:
-   case ISL_FORMAT_R64G64_PASSTHRU:
-   case ISL_FORMAT_R64G64B64_PASSTHRU:
-   case ISL_FORMAT_R64G64B64A64_PASSTHRU:
-  return true;
-   default:
-  return false;
-   }
-}
-
-static int
-uploads_needed(uint32_t format)
-{
-   if (!is_passthru_format(format))
-  return 1;
-
-   switch (format) {
-   case ISL_FORMAT_R64_PASSTHRU:
-   case ISL_FORMAT_R64G64_PASSTHRU:
-  return 1;
-   case ISL_FORMAT_R64G64B64_PASSTHRU:
-   case ISL_FORMAT_R64G64B64A64_PASSTHRU:
-  return 2;
-   default:
-  unreachable("not reached");
-   }
-}
-
-/*
- * Returns the number of componentes associated with a format that is used on
- * a 64 to 32 format split. See downsize_format()
- */
-static int
-upload_format_size(uint32_t upload_format)
-{
-   switch (upload_format) {
-   case ISL_FORMAT_R32G32_FLOAT:
-  return 2;
-   case ISL_FORMAT_R32G32B32A32_FLOAT:
-  return 4;
-   default:
-  unreachable("not reached");
-   }
-}
-
-/*
- * Returns the format that we are finally going to use when upload a vertex
- * element. It will only change if we are using *64*PASSTHRU formats, as for
- * gen < 8 they need to be splitted on two *32*FLOAT formats.
- *
- * @upload points in which upload we are. Valid values are [0,1]
- */
-static uint32_t
-downsize_format_if_needed(uint32_t format,
-  int upload)
-{
-   assert(upload == 0 || upload == 1);
-
-   if (!is_passthru_format(format))
-  return format;
-
-   switch (format) {
-   case ISL_FORMAT_R64_PASSTHRU:
-  return ISL_FORMAT_R32G32_FLOAT;
-   case ISL_FORMAT_R64G64_PASSTHRU:
-  return ISL_FORMAT_R32G32B32A32_FLOAT;
-   case ISL_FORMAT_R64G64B64_PASSTHRU:
-  return !upload ? ISL_FORMAT_R32G32B32A32_FLOAT
- : ISL_FORMAT_R32G32_FLOAT;
-   case ISL_FORMAT_R64G64B64A64_PASSTHRU:
-  return ISL_FORMAT_R32G32B32A32_FLOAT;
-   default:
-  unreachable("not reached");
-   }
-}
-
 /**
  * Given vertex array type/size/format/normalized info, return
  * the appopriate hardware surface type.
@@ -786,380 +706,6 @@ brw_prepare_shader_draw_parameters(struct brw_context 
*brw)
}
 }
 
-/**
- * Emit a VERTEX_BUFFER_STATE entry (part of 3DSTATE_VERTEX_BUFFERS).
- */
-uint32_t *
-brw_emit_vertex_buffer_state(struct brw_context *brw,
- unsigned buffer_nr,
- struct brw_bo *bo,
- unsigned start_offset,
- unsigned end_offset,
- unsigned stride,
- unsigned step_rate,
- uint32_t *__map)
-{
-   struct gl_context *ctx = >ctx;
-   uint32_t dw0;
-
-   if (brw->gen >= 8) {
-  dw0 = buffer_nr << GEN6_VB0_INDEX_SHIFT;
-   } else if (brw->gen >= 6) {
-  dw0 = (buffer_nr << GEN6_VB0_INDEX_SHIFT) |
-(step_rate ? GEN6_VB0_ACCESS_INSTANCEDATA
-   : GEN6_VB0_ACCESS_VERTEXDATA);
-   } else {
-  dw0 = (buffer_nr << BRW_VB0_INDEX_SHIFT) |
-(step_rate ? BRW_VB0_ACCESS_INSTANCEDATA
-   : BRW_VB0_ACCESS_VERTEXDATA);
-   }
-
-   if (brw->gen >= 7)
-  dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
-
-   switch (brw->gen) {
-   case 7:
-  dw0 |= GEN7_MOCS_L3 << 16;
-  break;
-   case 8:
-  dw0 |= BDW_MOCS_WB << 16;
-  break;
-   case 9:
-  dw0 |= SKL_MOCS_WB << 16;
-  break;
-   }
-
-   WARN_ONCE(stride >= (brw->gen >= 5 ? 2048 : 2047),
- "VBO stride %d too large, bad rendering may occur\n",
-

[Mesa-dev] [PATCH v03 34/38] i965: Port push constant code to genxml.

[Rafael Antognolli]

The following states are ported on this patch:
   - gen6_gs_push_constants
   - gen6_vs_push_constants
   - gen6_wm_push_constants
   - gen7_tes_push_constants

v2:
   - Use helper to setup brw_address (Kristian)
v3:
   - Do not use macro for upload_constant_state (Ken)
   - Do not re-declare MOCS macro (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   4 +-
 src/mesa/drivers/dri/i965/brw_state.h |   5 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c |  33 +---
 src/mesa/drivers/dri/i965/gen6_vs_state.c |  70 +--
 src/mesa/drivers/dri/i965/gen6_wm_state.c |  70 +--
 src/mesa/drivers/dri/i965/gen7_ds_state.c |  57 +-
 src/mesa/drivers/dri/i965/gen7_hs_state.c |  60 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 240 +--
 8 files changed, 227 insertions(+), 312 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_vs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_wm_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_ds_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_hs_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index a63d576..34162bd 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -87,11 +87,7 @@ i965_FILES = \
gen6_sol.c \
gen6_urb.c \
gen6_viewport_state.c \
-   gen6_vs_state.c \
-   gen6_wm_state.c \
gen7_cs_state.c \
-   gen7_ds_state.c \
-   gen7_hs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
gen7_sol_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 6adcf46..084f97f 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,7 +109,6 @@ extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_color_calc_state;
-extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_multisample_state;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
@@ -118,13 +117,9 @@ extern const struct brw_tracked_state gen6_sol_surface;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
-extern const struct brw_tracked_state gen6_vs_push_constants;
-extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
-extern const struct brw_tracked_state gen7_tcs_push_constants;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_index_buffer;
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c 
b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 6a9e951..6450c76 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -31,39 +31,6 @@
 #include "intel_batchbuffer.h"
 #include "main/shaderapi.h"
 
-static void
-gen6_upload_gs_push_constants(struct brw_context *brw)
-{
-   struct brw_stage_state *stage_state = >gs.base;
-
-   /* BRW_NEW_GEOMETRY_PROGRAM */
-   const struct brw_program *gp = brw_program_const(brw->geometry_program);
-
-   if (gp) {
-  /* BRW_NEW_GS_PROG_DATA */
-  struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
-
-  _mesa_shader_write_subroutine_indices(>ctx, MESA_SHADER_GEOMETRY);
-  gen6_upload_push_constants(brw, >program, prog_data, stage_state);
-   }
-
-   if (brw->gen >= 7)
-  gen7_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);
-}
-
-const struct brw_tracked_state gen6_gs_push_constants = {
-   .dirty = {
-  .mesa  = _NEW_PROGRAM_CONSTANTS |
-   _NEW_TRANSFORM,
-  .brw   = BRW_NEW_BATCH |
-   BRW_NEW_BLORP |
-   BRW_NEW_GEOMETRY_PROGRAM |
-   BRW_NEW_GS_PROG_DATA |
-   BRW_NEW_PUSH_CONSTANT_ALLOCATION,
-   },
-   .emit = gen6_upload_gs_push_constants,
-};
-
 void
 upload_gs_state_for_tf(struct brw_context *brw)
 {
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
deleted file mode 100644
index b2d2306..000
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permi

[Mesa-dev] [PATCH v03 03/38] genxml: Update xml for 3DSTATE_SF.

[Rafael Antognolli]

- Normalize "Anti-Aliasing Enable"
 - Add "Multisample Rasterization Mode" constants
 - Rename "Use Point Width on Vertex" to "Vertex"
 - Rename "Use Point Width from State" to "State"

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/genxml/gen6.xml | 15 ++-
 src/intel/genxml/gen7.xml |  7 ++-
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 094887a..8ead41f 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1215,7 +1215,7 @@
   
   
 
-
+
 
   
   
@@ -1230,7 +1230,12 @@
   
 
 
-
+
+  
+  
+  
+  
+
 
 
   
@@ -1253,9 +1258,9 @@
   
   
 
-
-  
-  
+
+  
+  
 
 
 
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 867a1d4..440258a 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1602,7 +1602,12 @@
   
 
 
-
+
+  
+  
+  
+  
+   
 
 
   
-- 
git-series 0.9.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v03 30/38] i965: Port gen6+ state emitting code to genxml.

[Rafael Antognolli]

Ported in this patch:
   - 3DSTATE_DS
   - 3DSTATE_GS
   - 3DSTATE_HS
   - 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL

v3:
   - Remove NEW_TRANSFORM blocks (Ken)
   - Bring back some comments and workaround for Ivybridge (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources  |   6 +-
 src/mesa/drivers/dri/i965/brw_state.h   |  18 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c   | 129 +-
 src/mesa/drivers/dri/i965/gen6_viewport_state.c | 147 +-
 src/mesa/drivers/dri/i965/gen7_ds_state.c   |  68 +--
 src/mesa/drivers/dri/i965/gen7_gs_state.c   | 167 +--
 src/mesa/drivers/dri/i965/gen7_hs_state.c   |  63 +--
 src/mesa/drivers/dri/i965/gen7_viewport_state.c | 100 +
 src/mesa/drivers/dri/i965/gen8_ds_state.c   | 116 +
 src/mesa/drivers/dri/i965/gen8_gs_state.c   | 146 +-
 src/mesa/drivers/dri/i965/gen8_hs_state.c   |  93 +---
 src/mesa/drivers/dri/i965/gen8_viewport_state.c | 120 +
 src/mesa/drivers/dri/i965/genX_state_upload.c   | 478 -
 13 files changed, 471 insertions(+), 1180 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_gs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_viewport_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_ds_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_gs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_hs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_viewport_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 95d29ac..3f0c66a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -92,24 +92,18 @@ i965_FILES = \
gen6_wm_state.c \
gen7_cs_state.c \
gen7_ds_state.c \
-   gen7_gs_state.c \
gen7_hs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
gen7_sol_state.c \
gen7_te_state.c \
gen7_urb.c \
-   gen7_viewport_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
gen8_depth_state.c \
gen8_draw_upload.c \
-   gen8_ds_state.c \
-   gen8_gs_state.c \
-   gen8_hs_state.c \
gen8_multisample_state.c \
gen8_surface_state.c \
-   gen8_viewport_state.c \
hsw_queryobj.c \
hsw_sol.c \
intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 72d63f6..b6e8abc 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,9 +109,7 @@ extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_blend_state;
-extern const struct brw_tracked_state gen6_sf_and_clip_viewports;
 extern const struct brw_tracked_state gen6_color_calc_state;
-extern const struct brw_tracked_state gen6_gs_state;
 extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_multisample_state;
@@ -125,26 +123,18 @@ extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
 extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
-extern const struct brw_tracked_state gen7_ds_state;
-extern const struct brw_tracked_state gen7_gs_state;
 extern const struct brw_tracked_state gen7_tcs_push_constants;
-extern const struct brw_tracked_state gen7_hs_state;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
-extern const struct brw_tracked_state gen8_ds_state;
-extern const struct brw_tracked_state gen8_gs_state;
-extern const struct brw_tracked_state gen8_hs_state;
 extern const struct brw_tracked_state gen8_index_buffer;
 extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
-extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
@@ -383,12 +373,6 @@ use_state_point_size(const struct brw_context *brw)
 

[Mesa-dev] [PATCH v03 27/38] i965: Port gen6+ 3DSTATE_WM to genxml.

[Rafael Antognolli]

Emit 3DSTATE_WM on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)
   - Remove TODO and use BRW_PSCDEPTH_OFF.
v3:
   - A couple of style fixes (Ken)
   - Enable RASTRULE_UPPER_RIGHT on gen6+ instead of gen8+ (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  14 +-
 src/mesa/drivers/dri/i965/gen6_wm_state.c | 221 +---
 src/mesa/drivers/dri/i965/gen7_wm_state.c | 147 +-
 src/mesa/drivers/dri/i965/gen8_ps_state.c |  49 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 188 +++-
 6 files changed, 185 insertions(+), 435 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_wm_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index bfcf57c..da09df8 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -101,7 +101,6 @@ i965_FILES = \
gen7_urb.c \
gen7_viewport_state.c \
gen7_vs_state.c \
-   gen7_wm_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
gen8_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index c55c175..5010237 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -125,7 +125,6 @@ extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
 extern const struct brw_tracked_state gen6_vs_state;
 extern const struct brw_tracked_state gen6_wm_push_constants;
-extern const struct brw_tracked_state gen6_wm_state;
 extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_ds_state;
 extern const struct brw_tracked_state gen7_gs_state;
@@ -138,7 +137,6 @@ extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state gen7_vs_state;
-extern const struct brw_tracked_state gen7_wm_state;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_ds_state;
@@ -149,7 +147,6 @@ extern const struct brw_tracked_state 
gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
-extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
@@ -320,17 +317,6 @@ void brw_emit_sampler_state(struct brw_context *brw,
 bool non_normalized_coordinates,
 uint32_t border_color_offset);
 
-/* gen6_wm_state.c */
-void
-gen6_upload_wm_state(struct brw_context *brw,
- const struct brw_wm_prog_data *prog_data,
- const struct brw_stage_state *stage_state,
- bool multisampled_fbo,
- bool dual_source_blend_enable, bool kill_enable,
- bool color_buffer_write_enable, bool msaa_enabled,
- bool line_stipple_enable, bool polygon_stipple_enable,
- bool statistic_enable);
-
 /* gen6_surface_state.c */
 void gen6_init_vtable_surface_functions(struct brw_context *brw);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c 
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 2fb2a33..9da1bdd 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -68,224 +68,3 @@ const struct brw_tracked_state gen6_wm_push_constants = {
},
.emit = gen6_upload_wm_push_constants,
 };
-
-void
-gen6_upload_wm_state(struct brw_context *brw,
- const struct brw_wm_prog_data *prog_data,
- const struct brw_stage_state *stage_state,
- bool multisampled_fbo,
- bool dual_source_blend_enable, bool kill_enable,
- bool color_buffer_write_enable, bool msaa_enabled,
- bool line_stipple_enable, bool polygon_stipple_enable,
- bool statistic_enable)
-{
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
-
-   /* We can't fold this into gen6_upload_wm_push_constants(), because
-* according to the SNB PRM, vol 2 part 1 section 7.2.2
-* (3DSTATE_CONSTANT_PS [DevSNB]):
-*
-* &quo

[Mesa-dev] [PATCH v03 05/38] genxml: Add alias for MOCS.

[Rafael Antognolli]

Use an alias, so we can set the same value as the #define's.

v3:
   - Call it "SO Buffer MOCS" to follow the most common naming scheme.
   - Add alias for gen7 and gen75 too (Ken).

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/genxml/gen7.xml  | 1 +
 src/intel/genxml/gen75.xml | 1 +
 src/intel/genxml/gen8.xml  | 1 +
 src/intel/genxml/gen9.xml  | 1 +
 4 files changed, 4 insertions(+)

diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 440258a..b63add0 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1642,6 +1642,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 9f0486c..e63979c 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -1957,6 +1957,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 408d241..3b44406 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2064,6 +2064,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 59daa31..d78a321 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2246,6 +2246,7 @@
 
 
 
+
 
 
 
-- 
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[Mesa-dev] [PATCH v03 15/38] i965: Add genxml related plumbing in a new genX_state_upload.c file.

[Rafael Antognolli]

From: Kenneth Graunke 

v3:
   - Drop aub parameter (Ken)

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/Makefile.sources|  15 ++-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 109 +++-
 2 files changed, 119 insertions(+), 5 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/genX_state_upload.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index aef1a7a..db55a3f 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -161,19 +161,24 @@ i965_FILES = \
libdrm_macros.h
 
 i965_gen6_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen7_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen75_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen8_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen9_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_oa_GENERATED_FILES = \
brw_oa_hsw.h \
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
new file mode 100644
index 000..ec571d5
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+
+#include "common/gen_device_info.h"
+#include "genxml/gen_macros.h"
+
+#include "brw_context.h"
+#include "brw_state.h"
+
+#include "intel_batchbuffer.h"
+
+UNUSED static void *
+emit_dwords(struct brw_context *brw, unsigned n)
+{
+   intel_batchbuffer_begin(brw, n, RENDER_RING);
+   uint32_t *map = brw->batch.map_next;
+   brw->batch.map_next += n;
+   intel_batchbuffer_advance(brw);
+   return map;
+}
+
+struct brw_address {
+   struct brw_bo *bo;
+   uint32_t read_domains;
+   uint32_t write_domain;
+   uint32_t offset;
+};
+
+static uint64_t
+emit_reloc(struct brw_context *brw,
+   void *location, struct brw_address address, uint32_t delta)
+{
+   uint32_t offset = (char *) location - (char *) brw->batch.map;
+
+   return brw_emit_reloc(>batch, offset, address.bo,
+ address.offset + delta,
+ address.read_domains,
+ address.write_domain);
+}
+
+#define __gen_address_type struct brw_address
+#define __gen_user_data struct brw_context
+
+static uint64_t
+__gen_combine_address(struct brw_context *brw, void *location,
+  struct brw_address address, uint32_t delta)
+{
+   if (address.bo == NULL) {
+  return address.offset + delta;
+   } else {
+  return emit_reloc(brw, location, address, delta);
+   }
+}
+
+#include "genxml/genX_pack.h"
+
+#define _brw_cmd_length(cmd) cmd ## _length
+#define _brw_cmd_length_bias(cmd) cmd ## _length_bias
+#define _brw_cmd_header(cmd) cmd ## _header
+#define _brw_cmd_pack(cmd) cmd ## _pack
+
+#define brw_batch_emit(brw, cmd, name)  \
+   for (struct cmd name = { _brw_cmd_header(cmd) }, \
+*_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
+__builtin_expect(_dst != NULL, 1);  \
+_brw_cmd_pack(cmd)(brw, (void *)_dst, ),   \
+_dst = NULL)
+
+#define brw_batch_emitn(brw, cmd, n) ({\
+  uint32_t *_dw = emit_dwords(brw, n); \
+  struct cmd template = {  \
+ _brw_cmd_header(cmd), \
+ .DWordLength = n - _brw_cmd_length_bias(cmd), \
+  };   \
+  _brw_cmd_pack(cmd)(brw, _dw, ); \
+  _dw + 1; /* Array starts at dw[1] */ 

[Mesa-dev] [PATCH v03 02/38] genxml: Rename clip enable property.

[Rafael Antognolli]

There are two variants:
   - Clip Enable
   - CLIP Enable (on gen6)

Rename everything to Clip Enable.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/genxml/gen4.xml  | 2 +-
 src/intel/genxml/gen45.xml | 2 +-
 src/intel/genxml/gen5.xml  | 2 +-
 src/intel/genxml/gen6.xml  | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index 0ea66e5..d3a2f92 100644
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -968,7 +968,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index bff32f9..547e278 100644
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -935,7 +935,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index fc6f248..0b84650 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -1091,7 +1091,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 3059bfc..094887a 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -806,7 +806,7 @@
 
 
 
-
+
 
   
   
-- 
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[Mesa-dev] [PATCH v03 08/38] genxml: Clip guardbands are float, not int.

[Rafael Antognolli]

This makes genxml create the right struct types, and generate the right
batch commands.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/genxml/gen6.xml | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index a12e22c..2173dbf 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -394,10 +394,10 @@
   
 
   
-
-
-
-
+
+
+
+
   
 
   
-- 
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[Mesa-dev] [PATCH v03 10/38] genxml: Normalize xml for 3DSTATE_MULTISAMPLE.

[Rafael Antognolli]

Name the options to "Pixel Location":
   - PIXLOC_CENTER -> CENTER
   - PIXLOC_UL_CORNER -> UL_CORNER

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/blorp/blorp_genX_exec.h | 4 +---
 src/intel/genxml/gen6.xml | 4 ++--
 src/intel/genxml/gen7.xml | 4 ++--
 src/intel/genxml/gen75.xml| 4 ++--
 src/intel/vulkan/genX_pipeline.c  | 3 +--
 5 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index bc829d0..be22be0 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1188,9 +1188,7 @@ blorp_emit_3dstate_multisample(struct blorp_batch *batch,
*should not have any effect by setting or not setting this bit.
*/
   ms.PixelPositionOffsetEnable  = false;
-  ms.PixelLocation  = CENTER;
 #elif GEN_GEN >= 7
-  ms.PixelLocation  = PIXLOC_CENTER;
 
   switch (params->num_samples) {
   case 1:
@@ -1209,9 +1207,9 @@ blorp_emit_3dstate_multisample(struct blorp_batch *batch,
  break;
   }
 #else
-  ms.PixelLocation  = PIXLOC_CENTER;
   GEN_SAMPLE_POS_4X(ms.Sample);
 #endif
+  ms.PixelLocation  = CENTER;
}
 }
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 2cb9419..a8ce7e0 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1089,8 +1089,8 @@
 
 
 
-  
-  
+  
+  
 
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 75954fe..fd70414 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1262,8 +1262,8 @@
 
 
 
-  
-  
+  
+  
 
 
   
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 1e64fef..ac2dbc3 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -1548,8 +1548,8 @@
 
 
 
-  
-  
+  
+  
 
 
   
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 954273b..43e6ab5 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -549,6 +549,7 @@ emit_ms_state(struct anv_pipeline *pipeline,
anv_batch_emit(>batch, GENX(3DSTATE_MULTISAMPLE), ms) {
   ms.NumberofMultisamples   = log2_samples;
 
+  ms.PixelLocation  = CENTER;
 #if GEN_GEN >= 8
   /* The PRM says that this bit is valid only for DX9:
*
@@ -556,9 +557,7 @@ emit_ms_state(struct anv_pipeline *pipeline,
*should not have any effect by setting or not setting this bit.
*/
   ms.PixelPositionOffsetEnable  = false;
-  ms.PixelLocation  = CENTER;
 #else
-  ms.PixelLocation  = PIXLOC_CENTER;
 
   switch (samples) {
   case 1:
-- 
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[Mesa-dev] [PATCH v03 32/38] i965: Port gen7+ 3DSTATE_TE to genxml.

[Rafael Antognolli]

Emit 3DSTATE_TE on Gen7+ using brw_batch_emit helper.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/mesa/drivers/dri/i965/Makefile.sources|  1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  1 +-
 src/mesa/drivers/dri/i965/gen7_te_state.c | 67 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 40 +++-
 4 files changed, 38 insertions(+), 71 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_te_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 0c67170..0123913 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -96,7 +96,6 @@ i965_FILES = \
gen7_l3_state.c \
gen7_misc_state.c \
gen7_sol_state.c \
-   gen7_te_state.c \
gen7_urb.c \
gen7_wm_surface_state.c \
gen8_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index cf043a0..322d767 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -125,7 +125,6 @@ extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_tcs_push_constants;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
diff --git a/src/mesa/drivers/dri/i965/gen7_te_state.c 
b/src/mesa/drivers/dri/i965/gen7_te_state.c
deleted file mode 100644
index e56fdcf..000
--- a/src/mesa/drivers/dri/i965/gen7_te_state.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright © 2014 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "intel_batchbuffer.h"
-
-static void
-upload_te_state(struct brw_context *brw)
-{
-   /* BRW_NEW_TESS_PROGRAMS */
-   bool active = brw->tess_eval_program;
-
-   const struct brw_tes_prog_data *tes_prog_data =
-  brw_tes_prog_data(brw->tes.base.prog_data);
-
-   if (active) {
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
-  OUT_BATCH((tes_prog_data->partitioning << GEN7_TE_PARTITIONING_SHIFT) |
-(tes_prog_data->output_topology << 
GEN7_TE_OUTPUT_TOPOLOGY_SHIFT) |
-(tes_prog_data->domain << GEN7_TE_DOMAIN_SHIFT) |
-GEN7_TE_ENABLE);
-  OUT_BATCH_F(63.0);
-  OUT_BATCH_F(64.0);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH_F(0);
-  OUT_BATCH_F(0);
-  ADVANCE_BATCH();
-   }
-}
-
-const struct brw_tracked_state gen7_te_state = {
-   .dirty = {
-  .mesa  = 0,
-  .brw   = BRW_NEW_BLORP |
-   BRW_NEW_CONTEXT |
-   BRW_NEW_TES_PROG_DATA |
-   BRW_NEW_TESS_PROGRAMS,
-   },
-   .emit = upload_te_state,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 1e66b4c..5fd4037 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2309,6 +2309,42 @@ static const struct brw_tracked_state genX(ds_state) = {
.emit = genX(upload_ds_state),
 };
 
+/* -- */
+
+static void
+upload_te_state(struct brw_context *brw)
+{
+   /* BRW_NEW_TESS_PROGRAMS */
+   boo

[Mesa-dev] [PATCH v03 06/38] genxml: Make "Reorder Mode" fields consistent.

[Rafael Antognolli]

From: Kenneth Graunke <kenn...@whitecape.org>

Both GS and SOL have these fields.  Some were ReorderEnable = true,
some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.

Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/genxml/gen6.xml| 5 -
 src/intel/genxml/gen7.xml| 5 -
 src/intel/vulkan/genX_pipeline.c | 4 
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 8ead41f..14d643c 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1006,7 +1006,10 @@
 
 
 
-
+
+  
+  
+
 
 
 
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index b63add0..e6b61b7 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1157,7 +1157,10 @@
 
 
 
-
+
+  
+  
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index b00707f..2631ed0 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1300,11 +1300,7 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
   gs.ControlDataFormat   = gs_prog_data->control_data_format;
   gs.ControlDataHeaderSize   = 
gs_prog_data->control_data_header_size_hwords;
   gs.InstanceControl = MAX2(gs_prog_data->invocations, 1) - 1;
-#if GEN_GEN >= 8 || GEN_IS_HASWELL
   gs.ReorderMode = TRAILING;
-#else
-  gs.ReorderEnable   = true;
-#endif
 
 #if GEN_GEN >= 8
   gs.ExpectedVertexCount = gs_prog_data->vertices_in;
-- 
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[Mesa-dev] [PATCH v03 04/38] genxml: Add missing field values to 3DSTATE_SBE.

[Rafael Antognolli]

Fill out "Attribute Active Component Format" possible values.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/genxml/gen9.xml | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index ee7056b..59daa31 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2173,7 +2173,12 @@
 
 
 
-  
+  
+ 
+ 
+ 
+ 
+  
 
   
 
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v03 00/38] Rebased and reviewed series to convert state emitting code to genxml.

[Rafael Antognolli]

The main difference for this one is that it includes the changes based on the
review by Kenneth.

Current version here:
https://github.com/rantogno/mesa/commits/review/genxml-v03

Kenneth Graunke (4):
  genxml: Make "Reorder Mode" fields consistent.
  i965: Add genxml related plumbing in a new genX_state_upload.c file.
  i965: Get real per-gen atom lists
  i965: Port Gen6+ DEPTH_STENCIL state to genxml.

Louis-Francis Ratté-Boulianne (1):
  genxml: Fill out Gen4, Gen45 and Gen5 XML

Rafael Antognolli (33):
  genxml: Rename clip enable property.
  genxml: Update xml for 3DSTATE_SF.
  genxml: Add missing field values to 3DSTATE_SBE.
  genxml: Add alias for MOCS.
  genxml: 3DSTATE_VS rename Function Enable to Enable.
  genxml: Clip guardbands are float, not int.
  genxml: Rename "Function Enable" to "Enable".
  genxml: Normalize xml for 3DSTATE_MULTISAMPLE.
  genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.
  i965: Split out enum from brw_eu_defines.h
  anv: Use BRW_BARYCENTRIC_NONPERSPECTIVE_BITS from common header.
  i965: Move MOCS macros to brw_context.h.
  genxml: Add rules to build gen4, gen45 and ge5.
  i965: Port Gen6+ 3DSTATE_CLIP state to genxml.
  i965: Port Gen8+ 3DSTATE_RASTER state to genxml.
  i965: Add brw_get_line_width_float.
  i965: Port gen6+ 3DSTATE_SF to genxml.
  i965: Port Gen7+ 3DSTATE_SBE state to genxml.
  i965: Remove calculate_attr_overrides.
  i965: Port gen7+ 3DSTATE_SOL to genxml.
  i965: Port gen7+ 3DSTATE_PS to genxml.
  i965: Port gen6+ 3DSTATE_WM to genxml.
  i965: Port gen8+ 3DSTATE_PS_EXTRA to genxml.
  i965: Port gen6+ 3DSTATE_VS to genxml.
  i965: Port gen6+ state emitting code to genxml.
  i965: Port gen6+ blend state code to genxml.
  i965: Port gen7+ 3DSTATE_TE to genxml.
  i965: Port gen6+ 3DSTATE_SCISSOR_STATE_POINTERS to use genxml.
  i965: Port push constant code to genxml.
  i965: Port gen4+ emit vertices code to genxml.
  i965: Port gen6+ multisample state emitting code to genxml.
  i965: Port gen6+ 3DSTATE_CC_STATE_POINTERS state to genxml.
  i965: Port gen4+ state emitting code to genxml.

 src/intel/Makefile.sources |1 +-
 src/intel/blorp/blorp_genX_exec.h  |   10 +-
 src/intel/compiler/brw_defines_common.h|   46 +-
 src/intel/compiler/brw_eu_defines.h|   22 +-
 src/intel/genxml/gen4.xml  | 1121 ++--
 src/intel/genxml/gen45.xml | 1174 ++--
 src/intel/genxml/gen5.xml  | 1287 +++-
 src/intel/genxml/gen6.xml  |   42 +-
 src/intel/genxml/gen7.xml  |   25 +-
 src/intel/genxml/gen75.xml |   13 +-
 src/intel/genxml/gen8.xml  |   11 +-
 src/intel/genxml/gen9.xml  |   16 +-
 src/intel/vulkan/gen8_cmd_buffer.c |2 +-
 src/intel/vulkan/genX_pipeline.c   |   19 +-
 src/mesa/drivers/dri/i965/Makefile.am  |   12 +-
 src/mesa/drivers/dri/i965/Makefile.sources |   49 +-
 src/mesa/drivers/dri/i965/brw_context.h|   50 +-
 src/mesa/drivers/dri/i965/brw_defines.h|   42 +-
 src/mesa/drivers/dri/i965/brw_draw_upload.c|  454 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c |  147 +-
 src/mesa/drivers/dri/i965/brw_state.h  |  101 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c   |  385 +-
 src/mesa/drivers/dri/i965/brw_util.h   |   25 +-
 src/mesa/drivers/dri/i965/gen6_cc.c|  306 +-
 src/mesa/drivers/dri/i965/gen6_clip_state.c|  139 +-
 src/mesa/drivers/dri/i965/gen6_depthstencil.c  |  114 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c  |  162 +-
 src/mesa/drivers/dri/i965/gen6_multisample_state.c |  103 +-
 src/mesa/drivers/dri/i965/gen6_scissor_state.c |  111 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c  |  454 +-
 src/mesa/drivers/dri/i965/gen6_viewport_state.c|  207 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c  |  183 +-
 src/mesa/drivers/dri/i965/gen6_wm_state.c  |  291 +-
 src/mesa/drivers/dri/i965/gen7_ds_state.c  |  125 +-
 src/mesa/drivers/dri/i965/gen7_gs_state.c  |  167 +-
 src/mesa/drivers/dri/i965/gen7_hs_state.c  |  123 +-
 src/mesa/drivers/dri/i965/gen7_sf_state.c  |  265 +-
 src/mesa/drivers/dri/i965/gen7_sol_state.c |  307 +-
 src/mesa/drivers/dri/i965/gen7_te_state.c  |   67 +-
 src/mesa/drivers/dri/i965/gen7_viewport_state.c|  100 +-
 src/mesa/drivers/dri/i965/gen7_vs_state.c  |   87 +-
 src/mesa/drivers/dri/i965/gen7_wm_state.c  |  284 +-
 src/mesa/drivers/dri/i965/gen8_blend_state.c   |  298 +-
 src/mesa/drivers/dri/i965/gen8_draw_upload.c   |  330 +-
 src/mesa/drivers/dri/i965/gen8_ds_state.c  |  116 +-
 src/mesa/drivers/dri/i965/gen8_gs_state.c  |  146 +-
 src/mesa/drivers/dri/i965/g

Re: [Mesa-dev] [PATCH v02 26/37] i965: Port gen6+ 3DSTATE_WM to genxml.

[Rafael Antognolli]

On Wed, Apr 26, 2017 at 11:15:45PM -0700, Kenneth Graunke wrote:
> On Monday, April 24, 2017 3:19:21 PM PDT Rafael Antognolli wrote:
> [snip]
> > diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
> > b/src/mesa/drivers/dri/i965/genX_state_upload.c
> > index 1b9dedf..0f7a222 100644
> > --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> > +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> > @@ -28,6 +28,7 @@
> >  
> >  #include "brw_context.h"
> >  #include "brw_state.h"
> > +#include "brw_wm.h"
> >  #include "brw_util.h"
> >  
> >  #include "intel_batchbuffer.h"
> > @@ -39,6 +40,8 @@
> >  #include "main/stencil.h"
> >  #include "main/transformfeedback.h"
> >  
> > +#include "compiler/brw_defines_common.h"
> > +
> >  UNUSED static void *
> >  emit_dwords(struct brw_context *brw, unsigned n)
> >  {
> > @@ -788,6 +791,189 @@ static const struct brw_tracked_state genX(sf_state) 
> > = {
> > .emit = genX(upload_sf),
> >  };
> >  
> > +/* -- 
> > */
> > +
> > +static void
> > +genX(upload_wm)(struct brw_context *brw)
> > +{
> > +   struct gl_context *ctx = >ctx;
> > +
> > +   /* BRW_NEW_FS_PROG_DATA */
> > +   const struct brw_wm_prog_data *wm_prog_data =
> > +  brw_wm_prog_data(brw->wm.base.prog_data);
> > +#if GEN_GEN < 8
> > +   bool writes_depth = wm_prog_data->computed_depth_mode != 
> > BRW_PSCDEPTH_OFF;
> > +   /* _NEW_BUFFERS */
> > +   const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) 
> > > 1;
> > +#endif
> 
> I think you can declare these in the GEN_GEN < 8 block below and save
> yourself an #if...#endif block.

Hmmm... it looks like I can't do that with writes_depth, because it is
also used in the GEN_GEN < 7 block. Is it fine if I just leave it at the
top with UNUSED?

> > +
> > +#if GEN_GEN < 7
> > +   const struct brw_stage_state *stage_state = >wm.base;
> > +   const bool enable_dual_src_blend = wm_prog_data->dual_src_blend &&
> > +  (ctx->Color.BlendEnabled & 1) &&
> > +  ctx->Color.Blend[0]._UsesDualSrc;
> 
> Let's get rid of enable_dual_src_blend and just put the expression in
> the wm.DualSourceBlendEnable assignment below.  Then this whole block
> is about constant packets, which reads nicely.
> 
> > +   const struct gen_device_info *devinfo = >screen->devinfo;
> > +
> > +   /* We can't fold this into gen6_upload_wm_push_constants(), because
> > +* according to the SNB PRM, vol 2 part 1 section 7.2.2
> > +* (3DSTATE_CONSTANT_PS [DevSNB]):
> > +*
> > +* "[DevSNB]: This packet must be followed by WM_STATE."
> > +*/
> > +   brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_PS), wmcp) {
> > +  if (wm_prog_data->base.nr_params != 0) {
> > + wmcp.Buffer0Valid = true;
> > + /* Pointer to the WM constant buffer.  Covered by the set of
> > +  * state flags from gen6_upload_wm_push_constants.
> > +  */
> > + wmcp.PointertoPSConstantBuffer0 = stage_state->push_const_offset;
> > + wmcp.PSConstantBuffer0ReadLength = stage_state->push_const_size - 
> > 1;
> > +  }
> > +   }
> > +#endif
> > +
> > +   brw_batch_emit(brw, GENX(3DSTATE_WM), wm) {
> > +  wm.StatisticsEnable = true;
> > +  wm.LineAntialiasingRegionWidth = _10pixels;
> > +  wm.LineEndCapAntialiasingRegionWidth = _05pixels;
> > +
> > +#if GEN_GEN < 7
> > +  if (wm_prog_data->base.use_alt_mode)
> > + wm.FloatingPointMode = Alternate;
> > +
> > +  wm.SamplerCount |= ALIGN(stage_state->sampler_count, 4) / 4;
> 
> You want =, not |=.  Also, let's use DIV_ROUND_UP:
> 
>   wm.SamplerCount = DIV_ROUND_UP(stage_state->sampler_count, 4);
> 
> > +  wm.BindingTableEntryCount = 
> > wm_prog_data->base.binding_table.size_bytes / 4;
> > +  wm.MaximumNumberofThreads = devinfo->max_wm_threads - 1;
> > +  wm._8PixelDispatchEnable = !!wm_prog_data->dispatch_8;
> > +  wm._16PixelDispatchEnable = !!wm_prog_data->dispatch_16;
> 
> I don't think you need !! - these are bools, they turn into 0 or 1
> automatically.
> 
> > +  wm.DispatchGRFStartRegisterForConstantSetupData0 =
> > + wm_p

Re: [Mesa-dev] [PATCH] i965: Set point rasterization rule to UPPER_RIGHT on Gen6-7.5.

[Rafael Antognolli]

Makes sense to me.

Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>

On Wed, Apr 26, 2017 at 11:14:47PM -0700, Kenneth Graunke wrote:
> Gen4-5 and Gen8+ already set this, but Gen6-7.5 did not.  We ought to
> be consistent - the answer depends on the API, not the hardware generation.
> 
> The Sandybridge PRM says about RASTRULE_UPPER_RIGHT:
> 
>"To match OpenGL point rasterization rules (round to +infinity, where
> this is the upper right direction wrt OpenGL screen origin of lower
> left).
> 
> So this is likely the one we should use.
> ---
>  src/mesa/drivers/dri/i965/gen6_wm_state.c | 2 ++
>  src/mesa/drivers/dri/i965/gen7_wm_state.c | 1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c 
> b/src/mesa/drivers/dri/i965/gen6_wm_state.c
> index aabae70d10b..2fb2a333853 100644
> --- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
> @@ -199,6 +199,8 @@ gen6_upload_wm_state(struct brw_context *brw,
>dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
> }
>  
> +   dw6 |= GEN6_WM_POINT_RASTRULE_UPPER_RIGHT;
> +
> /* From the SNB PRM, volume 2 part 1, page 281:
>  * "If the PS kernel does not need the Position XY Offsets
>  * to compute a Position XY value, then this field should be
> diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c 
> b/src/mesa/drivers/dri/i965/gen7_wm_state.c
> index 1c33db4d3b5..5efe55a0088 100644
> --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
> +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
> @@ -51,6 +51,7 @@ upload_wm_state(struct brw_context *brw)
> dw1 |= GEN7_WM_STATISTICS_ENABLE;
> dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
> dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
> +   dw1 |= GEN7_WM_POINT_RASTRULE_UPPER_RIGHT;
>  
> /* _NEW_LINE */
> if (ctx->Line.StippleFlag)
> -- 
> 2.12.2
> 
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[Mesa-dev] [PATCH v3 06/37] genxml: Add alias for MOCS.

[Rafael Antognolli]

Use an alias, so we can set the same value as the #define's.

v3:
   - Call it "SO Buffer MOCS" to follow the most common naming scheme.
   - Add alias for gen7 and gen75 too (Ken).

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/genxml/gen7.xml  | 1 +
 src/intel/genxml/gen75.xml | 1 +
 src/intel/genxml/gen8.xml  | 1 +
 src/intel/genxml/gen9.xml  | 1 +
 4 files changed, 4 insertions(+)

diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 440258a..b63add0 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1642,6 +1642,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 9f0486c..e63979c 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -1957,6 +1957,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 408d241..3b44406 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2064,6 +2064,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 59daa31..d78a321 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2246,6 +2246,7 @@
 
 
 
+
 
 
 
-- 
2.9.3

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Re: [Mesa-dev] [PATCH v02 06/37] genxml: Add alias for MOCS.

[Rafael Antognolli]

On Mon, Apr 24, 2017 at 03:59:07PM -0700, Kenneth Graunke wrote:
> On Monday, April 24, 2017 3:19:01 PM PDT Rafael Antognolli wrote:
> > Use an alias, so we can set the same value as the #define's.
> > 
> > Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
> > ---
> >  src/intel/genxml/gen8.xml | 1 +
> >  src/intel/genxml/gen9.xml | 1 +
> >  2 files changed, 2 insertions(+)
> > 
> > diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
> > index 408d241..2908082 100644
> > --- a/src/intel/genxml/gen8.xml
> > +++ b/src/intel/genxml/gen8.xml
> > @@ -2064,6 +2064,7 @@
> >  
> >  
> >   > type="MEMORY_OBJECT_CONTROL_STATE"/>
> > +
> >   > type="bool"/>
> >   > end="52" type="bool"/>
> >   > type="address"/>
> > diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
> > index 59daa31..09b9464 100644
> > --- a/src/intel/genxml/gen9.xml
> > +++ b/src/intel/genxml/gen9.xml
> > @@ -2246,6 +2246,7 @@
> >  
> >  
> >   > type="MEMORY_OBJECT_CONTROL_STATE"/>
> > +
> >   > type="bool"/>
> >   > end="52" type="bool"/>
> >   > type="address"/>
> > 
> 
> This seems a bit strange...we're only changing this in the stream out
> packets, and only on Gen8-9?

I only changed this where we were actually going to use it. I don't know
why, but we don't set MOCS for gen7 on stream out packets (or maybe it
was just 0). I'll double check this, and see what we are supposed to
set.

> I've wondered whether we should just use a uint everywhere.  On Gen9+
> it's just an index into the kernel tables, with no hardware-mandated
> meaning.  On earlier platforms, it changed for every piece of hardware.
> 
> I feel like a macro to construct MOCS values on earlier platforms
> would work as well as genxml.  *shrug*

Either way works for me.
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[Mesa-dev] [PATCH v02 00/37] Updated series to convert part of the state emitting code to genxml.

[Rafael Antognolli]

v2:
   - Included Louis patch that adds gen4, gen4.5 and gen5 xml's
   - Merged code for gen4-5 for emit vertices and some other brw_*
 functions
   - Addressed Ken's comments about updating gen4 and gen5 xml.
   - Included suggestion from Kristian about functions to return struct
 brw_address.
   - Moved xml commits to the beginning of the series.
   - Did a couple code cleanups for "TODO's" that I had left in the
 code.

I'm working on this series in this branch:
https://github.com/rantogno/mesa/tree/wip/brwxml

Kenneth Graunke (4):
  genxml: Make "Reorder Mode" fields consistent.
  i965: Add genxml related plumbing in a new genX_state_upload.c file.
  i965: Get real per-gen atom lists
  i965: Port Gen6+ DEPTH_STENCIL state to genxml.

Louis-Francis Ratté-Boulianne (1):
  genxml: Fill out Gen4, Gen45 and Gen5 XML

Rafael Antognolli (32):
  genxml: Fix gen4-5 xml to make it compile correctly.
  genxml: Rename clip enable property.
  genxml: Update xml for 3DSTATE_SF.
  genxml: Add missing field values to 3DSTATE_SBE.
  genxml: Add alias for MOCS.
  genxml: 3DSTATE_VS rename Function Enable to Enable.
  genxml: Clip guardbands are float, not int.
  genxml: Rename "Function Enable" to "Enable".
  genxml: Normalize xml for 3DSTATE_MULTISAMPLE.
  genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.
  i965: Split out enum from brw_eu_defines.h
  anv: Use BRW_BARYCENTRIC_NONPERSPECTIVE_BITS from common header.
  genxml: Add rules to build gen4, gen45 and ge5.
  i965: Port Gen6+ 3DSTATE_CLIP state to genxml.
  i965: Port Gen8+ 3DSTATE_RASTER state to genxml.
  i965: Port gen6+ 3DSTATE_SF to genxml.
  i965: Port Gen7+ 3DSTATE_SBE state to genxml.
  i965: Remove calculate_attr_overrides.
  i965: Port gen7+ 3DSTATE_SOL to genxml.
  i965: Port gen7+ 3DSTATE_PS to genxml.
  i965: Port gen6+ 3DSTATE_WM to genxml.
  i965: Port gen8+ 3DSTATE_PS_EXTRA to genxml.
  i965: Port gen6+ 3DSTATE_VS to genxml.
  i965: Port gen6+ state emitting code to genxml.
  i965: Port gen6+ blend state code to genxml.
  i965: Port gen7+ 3DSTATE_TE to genxml.
  i965: Port gen6+ 3DSTATE_SCISSOR_STATE_POINTERS to use genxml.
  i965: Port push constant code to genxml.
  i965: Port gen4+ emit vertices code to genxml.
  i965: Port gen6+ multisample state emitting code to genxml.
  i965: Port gen6+ 3DSTATE_CC_STATE_POINTERS state to genxml.
  i965: Port gen4+ state emitting code to genxml.

 src/intel/Makefile.sources |1 +-
 src/intel/blorp/blorp_genX_exec.h  |   10 +-
 src/intel/compiler/brw_defines_common.h|   46 +-
 src/intel/compiler/brw_eu_defines.h|   22 +-
 src/intel/genxml/gen4.xml  | 1121 +--
 src/intel/genxml/gen45.xml | 1174 +--
 src/intel/genxml/gen5.xml  | 1287 ++-
 src/intel/genxml/gen6.xml  |   42 +-
 src/intel/genxml/gen7.xml  |   24 +-
 src/intel/genxml/gen75.xml |   12 +-
 src/intel/genxml/gen8.xml  |   11 +-
 src/intel/genxml/gen9.xml  |   16 +-
 src/intel/vulkan/gen8_cmd_buffer.c |2 +-
 src/intel/vulkan/genX_pipeline.c   |   19 +-
 src/mesa/drivers/dri/i965/Makefile.am  |   12 +-
 src/mesa/drivers/dri/i965/Makefile.sources |   48 +-
 src/mesa/drivers/dri/i965/brw_context.h|   15 +-
 src/mesa/drivers/dri/i965/brw_draw.h   |2 +-
 src/mesa/drivers/dri/i965/brw_draw_upload.c| 1123 +---
 src/mesa/drivers/dri/i965/brw_misc_state.c |  147 +-
 src/mesa/drivers/dri/i965/brw_state.h  |  101 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c   |  385 +-
 src/mesa/drivers/dri/i965/brw_util.h   |   25 +-
 src/mesa/drivers/dri/i965/gen6_cc.c|  306 +-
 src/mesa/drivers/dri/i965/gen6_clip_state.c|  139 +-
 src/mesa/drivers/dri/i965/gen6_depthstencil.c  |  114 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c  |  162 +-
 src/mesa/drivers/dri/i965/gen6_multisample_state.c |6 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c  |  455 +-
 src/mesa/drivers/dri/i965/gen6_viewport_state.c|  207 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c  |  183 +-
 src/mesa/drivers/dri/i965/gen6_wm_state.c  |  289 +-
 src/mesa/drivers/dri/i965/gen7_ds_state.c  |  126 +-
 src/mesa/drivers/dri/i965/gen7_gs_state.c  |  168 +-
 src/mesa/drivers/dri/i965/gen7_hs_state.c  |  123 +-
 src/mesa/drivers/dri/i965/gen7_sf_state.c  |  265 +-
 src/mesa/drivers/dri/i965/gen7_sol_state.c |  307 +-
 src/mesa/drivers/dri/i965/gen7_te_state.c  |   67 +-
 src/mesa/drivers/dri/i965/gen7_viewport_state.c|  100 +-
 src/mesa/drivers/dri/i965/gen7_vs_state.c  |   87 +-
 src/mesa/drivers/dri/i965/gen7_wm_state.c  |  283 +-
 src/

[Mesa-dev] [PATCH v02 18/37] i965: Port Gen6+ DEPTH_STENCIL state to genxml.

[Rafael Antognolli]

From: Kenneth Graunke <kenn...@whitecape.org>

This emits 3DSTATE_WM_DEPTH_STENCIL on Gen8+ or DEPTH_STENCIL_STATE
(and the relevant pointer packets) on Gen6-7.5 from a single function.

Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/brw_state.h |   2 +-
 src/mesa/drivers/dri/i965/gen6_depthstencil.c | 114 +--
 src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c | 118 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 107 +-
 5 files changed, 103 insertions(+), 240 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_depthstencil.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_wm_depth_stencil.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 41f4d83..b085251 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -80,7 +80,6 @@ i965_FILES = \
gen6_clip_state.c \
gen6_constant_state.c \
gen6_depth_state.c \
-   gen6_depthstencil.c \
gen6_gs_state.c \
gen6_multisample_state.c \
gen6_queryobj.c \
@@ -119,7 +118,6 @@ i965_FILES = \
gen8_surface_state.c \
gen8_viewport_state.c \
gen8_vs_state.c \
-   gen8_wm_depth_stencil.c \
hsw_queryobj.c \
hsw_sol.c \
intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 6403570..7b6d718 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -112,7 +112,6 @@ extern const struct brw_tracked_state gen6_blend_state;
 extern const struct brw_tracked_state gen6_clip_state;
 extern const struct brw_tracked_state gen6_sf_and_clip_viewports;
 extern const struct brw_tracked_state gen6_color_calc_state;
-extern const struct brw_tracked_state gen6_depth_stencil_state;
 extern const struct brw_tracked_state gen6_gs_state;
 extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
@@ -157,7 +156,6 @@ extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
-extern const struct brw_tracked_state gen8_wm_depth_stencil;
 extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_raster_state;
 extern const struct brw_tracked_state gen8_sbe_state;
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c 
b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
deleted file mode 100644
index 0f9626c..000
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt <e...@anholt.net>
- *
- */
-
-#include "intel_batchbuffer.h"
-#include "intel_fbo.h"
-#include "brw_context.h"
-#include "brw_defines.h"
-#include "brw_state.h"
-
-static void
-gen6_upload_depth_stencil_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   struct gen6_depth_stencil_state *ds;
-   struct intel_renderbuffer *depth_irb;
-
-   /* _NEW_BUFFERS */
-   depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
-
-   ds = brw_state_batch(brw, sizeof(*ds), 64,
-   >cc.depth_stencil_state_offset);
-   memset(ds, 0, sizeof(*ds));
-
-   /* _NEW_STENCIL | _NEW_BUFFERS */
-   if (ctx->Stencil._Enabled) {
-  int back = ctx->Stencil._BackFace;
-
-  ds->d

[Mesa-dev] [PATCH v02 20/37] i965: Port Gen8+ 3DSTATE_RASTER state to genxml.

[Rafael Antognolli]

Emits 3DSTATE_RASTER from genX_state_upload.c using pack structs from
genxml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_state.h |   1 +-
 src/mesa/drivers/dri/i965/gen8_sf_state.c | 125 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 125 ++-
 3 files changed, 124 insertions(+), 127 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index c26be41..3a10a8a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -156,7 +156,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
-extern const struct brw_tracked_state gen8_raster_state;
 extern const struct brw_tracked_state gen8_sbe_state;
 extern const struct brw_tracked_state gen8_sf_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c 
b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 41e94fb..d47adcd 100644
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -224,128 +224,3 @@ const struct brw_tracked_state gen8_sf_state = {
},
.emit = upload_sf,
 };
-
-static void
-upload_raster(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   uint32_t dw1 = 0;
-
-   /* _NEW_BUFFERS */
-   bool render_to_fbo = _mesa_is_user_fbo(brw->ctx.DrawBuffer);
-
-   /* _NEW_POLYGON */
-   if (ctx->Polygon._FrontBit == render_to_fbo)
-  dw1 |= GEN8_RASTER_FRONT_WINDING_CCW;
-
-   if (ctx->Polygon.CullFlag) {
-  switch (ctx->Polygon.CullFaceMode) {
-  case GL_FRONT:
- dw1 |= GEN8_RASTER_CULL_FRONT;
- break;
-  case GL_BACK:
- dw1 |= GEN8_RASTER_CULL_BACK;
- break;
-  case GL_FRONT_AND_BACK:
- dw1 |= GEN8_RASTER_CULL_BOTH;
- break;
-  default:
- unreachable("not reached");
-  }
-   } else {
-  dw1 |= GEN8_RASTER_CULL_NONE;
-   }
-
-   /* _NEW_POINT */
-   if (ctx->Point.SmoothFlag)
-  dw1 |= GEN8_RASTER_SMOOTH_POINT_ENABLE;
-
-   if (_mesa_is_multisample_enabled(ctx))
-  dw1 |= GEN8_RASTER_API_MULTISAMPLE_ENABLE;
-
-   if (ctx->Polygon.OffsetFill)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
-
-   if (ctx->Polygon.OffsetLine)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
-
-   if (ctx->Polygon.OffsetPoint)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
-
-   switch (ctx->Polygon.FrontMode) {
-   case GL_FILL:
-  dw1 |= GEN6_SF_FRONT_SOLID;
-  break;
-   case GL_LINE:
-  dw1 |= GEN6_SF_FRONT_WIREFRAME;
-  break;
-   case GL_POINT:
-  dw1 |= GEN6_SF_FRONT_POINT;
-  break;
-
-   default:
-  unreachable("not reached");
-   }
-
-   switch (ctx->Polygon.BackMode) {
-   case GL_FILL:
-  dw1 |= GEN6_SF_BACK_SOLID;
-  break;
-   case GL_LINE:
-  dw1 |= GEN6_SF_BACK_WIREFRAME;
-  break;
-   case GL_POINT:
-  dw1 |= GEN6_SF_BACK_POINT;
-  break;
-   default:
-  unreachable("not reached");
-   }
-
-   /* _NEW_LINE */
-   if (ctx->Line.SmoothFlag)
-  dw1 |= GEN8_RASTER_LINE_AA_ENABLE;
-
-   /* _NEW_SCISSOR */
-   if (ctx->Scissor.EnableFlags)
-  dw1 |= GEN8_RASTER_SCISSOR_ENABLE;
-
-   /* _NEW_TRANSFORM */
-   if (!ctx->Transform.DepthClamp) {
-  if (brw->gen >= 9) {
- dw1 |= GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE |
-GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE;
-  } else {
- dw1 |= GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE;
-  }
-   }
-
-   /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
-   if (ctx->IntelConservativeRasterization) {
-  if (brw->gen >= 9)
- dw1 |= GEN9_RASTER_CONSERVATIVE_RASTERIZATION_ENABLE;
-   }
-
-   BEGIN_BATCH(5);
-   OUT_BATCH(_3DSTATE_RASTER << 16 | (5 - 2));
-   OUT_BATCH(dw1);
-   OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
-   OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
-   OUT_BATCH_F(ctx->Polygon.OffsetClamp); /* global depth offset clamp */
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen8_raster_state = {
-   .dirty = {
-  .mesa  = _NEW_BUFFERS |
-   _NEW_LINE |
-   _NEW_MULTISAMPLE |
-   _NEW_POINT |
-   _NEW_POLYGON |
-   _NEW_SCISSOR |
-   _NEW_TRANSFORM,
-  .brw   = BRW_NEW_BLORP |
-   BRW_NEW_CONTEXT |
-   BRW_NEW_CONSERVATIVE_RASTERIZATION,
-   },
-   .emit = upload_raster,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 7532085..948782a 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src

[Mesa-dev] [PATCH v02 02/37] genxml: Fix gen4-5 xml to make it compile correctly.

[Rafael Antognolli]

Set the type of some fields, instead of prefix. Also fix the
SAMPLER_BORDER_COLOR_STATE fields of gen5.xml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/genxml/gen4.xml  | 13 +-
 src/intel/genxml/gen45.xml | 12 -
 src/intel/genxml/gen5.xml  | 52 +++
 3 files changed, 39 insertions(+), 38 deletions(-)

diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index 1cdae22..0ea66e5 100644
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -375,12 +375,12 @@
   
   
 
-
-
-
-
-
-
+
+
+
+
+
+
   
   
   
@@ -708,6 +708,7 @@
 
 
 
+
   
 
   
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index 1bf6840..bff32f9 100644
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -376,12 +376,12 @@
   
   
 
-
-
-
-
-
-
+
+
+
+
+
+
   
   
   
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index db0ae46..fc6f248 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -374,12 +374,12 @@
   
   
 
-
-
-
-
-
-
+
+
+
+
+
+
   
   
   
@@ -497,30 +497,30 @@
 
 
 
-
-
-
-
+
+
+
+
 
-
-
-
-
+
+
+
+
 
-
-
-
-
+
+
+
+
 
-
-
-
-
+
+
+
+
 
-
-
-
-
+
+
+
+
   
 
   
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v02 13/37] i965: Split out enum from brw_eu_defines.h

[Rafael Antognolli]

We need to use some enums inside genX_state_upload.c, but including the
whole header will cause several conflicts between things defined in this
header and the genxml auto-generated headers.

So create a separate header that is included both by brw_eu_defines.h
and genX_state_upload.c.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/Makefile.sources  |  1 +-
 src/intel/compiler/brw_defines_common.h | 46 ++-
 src/intel/compiler/brw_eu_defines.h | 22 +
 3 files changed, 48 insertions(+), 21 deletions(-)
 create mode 100644 src/intel/compiler/brw_defines_common.h

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 0d44661..2af5a7a 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -27,6 +27,7 @@ COMPILER_FILES = \
compiler/brw_compiler.h \
compiler/brw_dead_control_flow.cpp \
compiler/brw_dead_control_flow.h \
+   compiler/brw_defines_common.h \
compiler/brw_disasm.c \
compiler/brw_eu.c \
compiler/brw_eu_compact.c \
diff --git a/src/intel/compiler/brw_defines_common.h 
b/src/intel/compiler/brw_defines_common.h
new file mode 100644
index 000..fdae125
--- /dev/null
+++ b/src/intel/compiler/brw_defines_common.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef BRW_DEFINES_COMMON_H
+#endif // BRW_DEFINES_COMMON_H
+
+enum brw_pixel_shader_computed_depth_mode {
+   BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
+   BRW_PSCDEPTH_ON= 1, /* PS computes depth; no guarantee about value */
+   BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
+   BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
+};
+
+enum brw_barycentric_mode {
+   BRW_BARYCENTRIC_PERSPECTIVE_PIXEL   = 0,
+   BRW_BARYCENTRIC_PERSPECTIVE_CENTROID= 1,
+   BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE  = 2,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL= 3,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
+   BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
+   BRW_BARYCENTRIC_MODE_COUNT  = 6
+};
+#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
+   ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
+(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
+(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
diff --git a/src/intel/compiler/brw_eu_defines.h 
b/src/intel/compiler/brw_eu_defines.h
index 13a70f6..51f9cbc 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -33,6 +33,7 @@
 #define BRW_EU_DEFINES_H
 
 #include "util/macros.h"
+#include "brw_defines_common.h"
 
 /* The following hunk, up-to "Execution Unit" is used by both the
  * intel/compiler and i965 codebase. */
@@ -72,27 +73,6 @@
 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x16
 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
 
-enum brw_barycentric_mode {
-   BRW_BARYCENTRIC_PERSPECTIVE_PIXEL   = 0,
-   BRW_BARYCENTRIC_PERSPECTIVE_CENTROID= 1,
-   BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE  = 2,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL= 3,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID = 4,
-   BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE   = 5,
-   BRW_BARYCENTRIC_MODE_COUNT  = 6
-};
-#define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
-   ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
-(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
-(1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
-
-enum brw_pixel_shader_computed_depth_mode {
-   BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
-   BRW_PSCDEPTH_ON= 1, /* PS computes depth; no guarantee about value */
-   BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >

[Mesa-dev] [PATCH v02 17/37] genxml: Add rules to build gen4, gen45 and ge5.

[Rafael Antognolli]

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.am  | 12 
 src/mesa/drivers/dri/i965/Makefile.sources |  9 +
 src/mesa/drivers/dri/i965/brw_state.h  |  1 +
 3 files changed, 22 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/Makefile.am 
b/src/mesa/drivers/dri/i965/Makefile.am
index 4e9b062..762aefc 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -46,12 +46,24 @@ AM_CFLAGS = \
 AM_CXXFLAGS = $(AM_CFLAGS)
 
 I965_PERGEN_LIBS = \
+   libi965_gen4.la \
+   libi965_gen45.la \
+   libi965_gen5.la \
libi965_gen6.la \
libi965_gen7.la \
libi965_gen75.la \
libi965_gen8.la \
libi965_gen9.la
 
+libi965_gen4_la_SOURCES = $(i965_gen4_FILES)
+libi965_gen4_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=40
+
+libi965_gen45_la_SOURCES = $(i965_gen45_FILES)
+libi965_gen45_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=45
+
+libi965_gen5_la_SOURCES = $(i965_gen5_FILES)
+libi965_gen5_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=50
+
 libi965_gen6_la_SOURCES = $(i965_gen6_FILES)
 libi965_gen6_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=60
 
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index db55a3f..41f4d83 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -160,6 +160,15 @@ i965_FILES = \
intel_upload.c \
libdrm_macros.h
 
+i965_gen4_FILES = \
+   genX_state_upload.c
+
+i965_gen45_FILES = \
+   genX_state_upload.c
+
+i965_gen5_FILES = \
+   genX_state_upload.c
+
 i965_gen6_FILES = \
genX_blorp_exec.c \
genX_state_upload.c
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 008326a..6403570 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -446,6 +446,7 @@ void brw_copy_pipeline_atoms(struct brw_context *brw,
  const struct brw_tracked_state **atoms,
  int num_atoms);
 void gen4_init_atoms(struct brw_context *brw);
+void gen45_init_atoms(struct brw_context *brw);
 void gen5_init_atoms(struct brw_context *brw);
 void gen6_init_atoms(struct brw_context *brw);
 void gen7_init_atoms(struct brw_context *brw);
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v02 27/37] i965: Port gen8+ 3DSTATE_PS_EXTRA to genxml.

[Rafael Antognolli]

Emit 3DSTATE_PS_EXTRA on Gen8+ using brw_batch_emit helper, that uses
pack structs from genxml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  10 +-
 src/mesa/drivers/dri/i965/gen8_ps_state.c | 138 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c |  95 -
 4 files changed, 94 insertions(+), 150 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_ps_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index da09df8..7f25ae1 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -109,7 +109,6 @@ i965_FILES = \
gen8_gs_state.c \
gen8_hs_state.c \
gen8_multisample_state.c \
-   gen8_ps_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
gen8_vs_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 5010237..a87bf3a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -146,7 +146,6 @@ extern const struct brw_tracked_state gen8_index_buffer;
 extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
-extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
@@ -284,15 +283,6 @@ void brw_update_renderbuffer_surfaces(struct brw_context 
*brw,
 void gen7_check_surface_setup(uint32_t *surf, bool is_render_target);
 void gen7_init_vtable_surface_functions(struct brw_context *brw);
 
-/* gen8_ps_state.c */
-void gen8_upload_ps_state(struct brw_context *brw,
-  const struct brw_stage_state *stage_state,
-  const struct brw_wm_prog_data *prog_data,
-  uint32_t fast_clear_op);
-
-void gen8_upload_ps_extra(struct brw_context *brw,
-  const struct brw_wm_prog_data *prog_data);
-
 /* gen8_surface_state.c */
 
 void gen8_init_vtable_surface_functions(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c 
b/src/mesa/drivers/dri/i965/gen8_ps_state.c
deleted file mode 100644
index 1a4a680..000
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Copyright © 2012 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include 
-#include "program/program.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_wm.h"
-#include "intel_batchbuffer.h"
-
-void
-gen8_upload_ps_extra(struct brw_context *brw,
- const struct brw_wm_prog_data *prog_data)
-{
-   struct gl_context *ctx = >ctx;
-   uint32_t dw1 = 0;
-
-   dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
-   dw1 |= prog_data->computed_depth_mode << GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT;
-
-   if (prog_data->uses_kill)
-  dw1 |= GEN8_PSX_KILL_ENABLE;
-
-   if (prog_data->num_varying_inputs != 0)
-  dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
-
-   if (prog_data->uses_src_depth)
-  dw1 |= GEN8_PSX_USES_SOURCE_DEPTH;
-
-   if (prog_data->uses_src_w)
-  dw1 |= GEN8_PSX_USES_SOURCE_W;
-
-   if (prog_data->persample_dispatch)
-  dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
-
-   /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
-   if (prog_data->uses_sample_mask) {
-  if (brw->gen >= 9) {
- if (prog_data->post_depth_coverage)
-dw1 |= BRW_PCICMS_DEPTH << 
GEN9_PS

[Mesa-dev] [PATCH v02 21/37] i965: Port gen6+ 3DSTATE_SF to genxml.

[Rafael Antognolli]

Emit sf state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_state.h |   3 +-
 src/mesa/drivers/dri/i965/brw_util.h  |  25 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c | 190 +
 src/mesa/drivers/dri/i965/gen7_sf_state.c | 156 +---
 src/mesa/drivers/dri/i965/gen8_sf_state.c |  73 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 428 ++-
 6 files changed, 439 insertions(+), 436 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 3a10a8a..594757c 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -119,7 +119,6 @@ extern const struct brw_tracked_state 
gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
 extern const struct brw_tracked_state gen6_scissor_state;
 extern const struct brw_tracked_state gen6_sol_surface;
-extern const struct brw_tracked_state gen6_sf_state;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
@@ -137,7 +136,6 @@ extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sbe_state;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
-extern const struct brw_tracked_state gen7_sf_state;
 extern const struct brw_tracked_state gen7_sol_state;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
@@ -157,7 +155,6 @@ extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_sbe_state;
-extern const struct brw_tracked_state gen8_sf_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
diff --git a/src/mesa/drivers/dri/i965/brw_util.h 
b/src/mesa/drivers/dri/i965/brw_util.h
index 3e9a6ee..7395d34 100644
--- a/src/mesa/drivers/dri/i965/brw_util.h
+++ b/src/mesa/drivers/dri/i965/brw_util.h
@@ -40,8 +40,8 @@ extern GLuint brw_translate_blend_factor( GLenum factor );
 extern GLuint brw_translate_blend_equation( GLenum mode );
 extern GLenum brw_fix_xRGB_alpha(GLenum function);
 
-static inline uint32_t
-brw_get_line_width(struct brw_context *brw)
+static inline float
+brw_get_line_width_float(struct brw_context *brw)
 {
/* From the OpenGL 4.4 spec:
 *
@@ -52,14 +52,9 @@ brw_get_line_width(struct brw_context *brw)
float line_width =
   CLAMP(!_mesa_is_multisample_enabled(>ctx) && 
!brw->ctx.Line.SmoothFlag
 ? roundf(brw->ctx.Line.Width) : brw->ctx.Line.Width,
-0.0f, brw->ctx.Const.MaxLineWidth);
-   uint32_t line_width_u3_7 = U_FIXED(line_width, 7);
+0.125f, brw->ctx.Const.MaxLineWidth);
 
-   /* Line width of 0 is not allowed when MSAA enabled */
-   if (_mesa_is_multisample_enabled(>ctx)) {
-  if (line_width_u3_7 == 0)
- line_width_u3_7 = 1;
-   } else if (brw->ctx.Line.SmoothFlag && line_width < 1.5f) {
+   if (!_mesa_is_multisample_enabled(>ctx) && brw->ctx.Line.SmoothFlag && 
line_width < 1.5f) {
   /* For 1 pixel line thickness or less, the general
* anti-aliasing algorithm gives up, and a garbage line is
* generated.  Setting a Line Width of 0.0 specifies the
@@ -71,10 +66,18 @@ brw_get_line_width(struct brw_context *brw)
* bspec section 6.3.12.1 Zero-Width (Cosmetic) Line
* Rasterization.
*/
-  line_width_u3_7 = 0;
+  line_width = 0.0f;
}
 
-   return line_width_u3_7;
+   return line_width;
+}
+
+static inline uint32_t
+brw_get_line_width(struct brw_context *brw)
+{
+   float line_width = brw_get_line_width_float(brw);
+
+   return U_FIXED(line_width, 7);
 }
 
 #endif
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index dd54779..45b5769 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -263,193 +263,3 @@ calculate_attr_overrides(const struct brw_context *brw,
 */
*urb_entry_read_length = ALIGN(max_source_attr + 1, 2) / 2;
 }
-
-
-static void
-upload_sf_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_FS_PROG_DATA */
-   const struct brw_wm_prog_data *wm_prog_data =
-  brw_wm_prog_data(brw->wm.base.prog_data);
-   uint32_t num_outputs = wm_prog_data->num_varying_inputs;
-   uint32_t dw1, dw2, dw3, dw4;
-   uint32_t point_sprite_enables;
-   int i;
-   /* _NEW_BU

[Mesa-dev] [PATCH v02 34/37] i965: Port gen4+ emit vertices code to genxml.

[Rafael Antognolli]

Some code that was placed in brw_draw_upload.c and exported to be used
by gen8+ was also moved to genX_state_upload, and the respective symbols
are not exported anymore.

v2:
   - Remove code from brw_draw_upload too
   - Emit vertices for gen4-5 too.
   - Use helper to setup brw_address (Kristian)
   - Use macros for MOCS values.
   - Do not use #ifndef NDEBUG on code that is actually used (Ken)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.h   |6 +-
 src/mesa/drivers/dri/i965/brw_draw.h  |2 +-
 src/mesa/drivers/dri/i965/brw_draw_upload.c   | 1123 +
 src/mesa/drivers/dri/i965/brw_state.h |2 +-
 src/mesa/drivers/dri/i965/gen8_draw_upload.c  |  330 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 1241 +-
 6 files changed, 1236 insertions(+), 1468 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index c7d6e49..8bd8863 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1396,10 +1396,6 @@ void brw_upload_cs_urb_state(struct brw_context *brw);
 /* brw_vs.c */
 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
 
-/* brw_draw_upload.c */
-unsigned brw_get_vertex_surface_type(struct brw_context *brw,
- const struct gl_vertex_array *glarray);
-
 static inline unsigned
 brw_get_index_type(unsigned index_size)
 {
@@ -1409,8 +1405,6 @@ brw_get_index_type(unsigned index_size)
return (index_size >> 1) << 8;
 }
 
-void brw_prepare_vertices(struct brw_context *brw);
-
 /* brw_wm_surface_state.c */
 void brw_init_surface_formats(struct brw_context *brw);
 void brw_create_constant_surface(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_draw.h 
b/src/mesa/drivers/dri/i965/brw_draw.h
index 3b99915..7fbe363 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.h
+++ b/src/mesa/drivers/dri/i965/brw_draw.h
@@ -58,8 +58,6 @@ void brw_draw_prims(struct gl_context *ctx,
 void brw_draw_init( struct brw_context *brw );
 void brw_draw_destroy( struct brw_context *brw );
 
-void brw_prepare_shader_draw_parameters(struct brw_context *);
-
 /* brw_primitive_restart.c */
 GLboolean
 brw_handle_primitive_restart(struct gl_context *ctx,
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c 
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 7846293..2fb4d5d 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -37,1129 +37,6 @@
 #include "intel_batchbuffer.h"
 #include "intel_buffer_objects.h"
 
-static const GLuint double_types_float[5] = {
-   0,
-   ISL_FORMAT_R64_FLOAT,
-   ISL_FORMAT_R64G64_FLOAT,
-   ISL_FORMAT_R64G64B64_FLOAT,
-   ISL_FORMAT_R64G64B64A64_FLOAT
-};
-
-static const GLuint double_types_passthru[5] = {
-   0,
-   ISL_FORMAT_R64_PASSTHRU,
-   ISL_FORMAT_R64G64_PASSTHRU,
-   ISL_FORMAT_R64G64B64_PASSTHRU,
-   ISL_FORMAT_R64G64B64A64_PASSTHRU
-};
-
-static const GLuint float_types[5] = {
-   0,
-   ISL_FORMAT_R32_FLOAT,
-   ISL_FORMAT_R32G32_FLOAT,
-   ISL_FORMAT_R32G32B32_FLOAT,
-   ISL_FORMAT_R32G32B32A32_FLOAT
-};
-
-static const GLuint half_float_types[5] = {
-   0,
-   ISL_FORMAT_R16_FLOAT,
-   ISL_FORMAT_R16G16_FLOAT,
-   ISL_FORMAT_R16G16B16_FLOAT,
-   ISL_FORMAT_R16G16B16A16_FLOAT
-};
-
-static const GLuint fixed_point_types[5] = {
-   0,
-   ISL_FORMAT_R32_SFIXED,
-   ISL_FORMAT_R32G32_SFIXED,
-   ISL_FORMAT_R32G32B32_SFIXED,
-   ISL_FORMAT_R32G32B32A32_SFIXED,
-};
-
-static const GLuint uint_types_direct[5] = {
-   0,
-   ISL_FORMAT_R32_UINT,
-   ISL_FORMAT_R32G32_UINT,
-   ISL_FORMAT_R32G32B32_UINT,
-   ISL_FORMAT_R32G32B32A32_UINT
-};
-
-static const GLuint uint_types_norm[5] = {
-   0,
-   ISL_FORMAT_R32_UNORM,
-   ISL_FORMAT_R32G32_UNORM,
-   ISL_FORMAT_R32G32B32_UNORM,
-   ISL_FORMAT_R32G32B32A32_UNORM
-};
-
-static const GLuint uint_types_scale[5] = {
-   0,
-   ISL_FORMAT_R32_USCALED,
-   ISL_FORMAT_R32G32_USCALED,
-   ISL_FORMAT_R32G32B32_USCALED,
-   ISL_FORMAT_R32G32B32A32_USCALED
-};
-
-static const GLuint int_types_direct[5] = {
-   0,
-   ISL_FORMAT_R32_SINT,
-   ISL_FORMAT_R32G32_SINT,
-   ISL_FORMAT_R32G32B32_SINT,
-   ISL_FORMAT_R32G32B32A32_SINT
-};
-
-static const GLuint int_types_norm[5] = {
-   0,
-   ISL_FORMAT_R32_SNORM,
-   ISL_FORMAT_R32G32_SNORM,
-   ISL_FORMAT_R32G32B32_SNORM,
-   ISL_FORMAT_R32G32B32A32_SNORM
-};
-
-static const GLuint int_types_scale[5] = {
-   0,
-   ISL_FORMAT_R32_SSCALED,
-   ISL_FORMAT_R32G32_SSCALED,
-   ISL_FORMAT_R32G32B32_SSCALED,
-   ISL_FORMAT_R32G32B32A32_SSCALED
-};
-
-static const GLuint ushort_types_direct[5] = {
-   0,
-   ISL_FORMAT_R16_UINT,
-   ISL_FORMAT_R16G16_UINT,
-   ISL_FORMAT_R16G16B16_UINT,
-   ISL_FORMAT_R16G16B16A16_UINT
-};
-
-static const GLuint ushort_types_norm[5] = {
-   0,
-   ISL_FORMAT_R16_UNORM,
-   ISL_FORMAT_R16G16

[Mesa-dev] [PATCH v02 19/37] i965: Port Gen6+ 3DSTATE_CLIP state to genxml.

[Rafael Antognolli]

Emit clip state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_state.h |   1 +-
 src/mesa/drivers/dri/i965/gen6_clip_state.c   | 139 +--
 src/mesa/drivers/dri/i965/genX_state_upload.c | 143 ++-
 3 files changed, 140 insertions(+), 143 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 7b6d718..c26be41 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,7 +109,6 @@ extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_blend_state;
-extern const struct brw_tracked_state gen6_clip_state;
 extern const struct brw_tracked_state gen6_sf_and_clip_viewports;
 extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_state;
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c 
b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index 23d969b..2fffb67 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -88,142 +88,3 @@ brw_is_drawing_lines(const struct brw_context *brw)
return false;
 }
 
-static void
-upload_clip_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_META_IN_PROGRESS */
-   uint32_t dw1 = brw->meta_in_progress ? 0 : GEN6_CLIP_STATISTICS_ENABLE;
-   uint32_t dw2 = 0;
-
-   /* _NEW_BUFFERS */
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-
-   /* BRW_NEW_FS_PROG_DATA */
-   if (brw_wm_prog_data(brw->wm.base.prog_data)->barycentric_interp_modes &
-   BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) {
-  dw2 |= GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE;
-   }
-
-   /* BRW_NEW_VS_PROG_DATA */
-   dw1 |= brw_vue_prog_data(brw->vs.base.prog_data)->cull_distance_mask;
-
-   if (brw->gen >= 7)
-  dw1 |= GEN7_CLIP_EARLY_CULL;
-
-   if (brw->gen == 7) {
-  /* _NEW_POLYGON */
-  if (ctx->Polygon._FrontBit == _mesa_is_user_fbo(fb))
- dw1 |= GEN7_CLIP_WINDING_CCW;
-
-  if (ctx->Polygon.CullFlag) {
- switch (ctx->Polygon.CullFaceMode) {
- case GL_FRONT:
-dw1 |= GEN7_CLIP_CULLMODE_FRONT;
-break;
- case GL_BACK:
-dw1 |= GEN7_CLIP_CULLMODE_BACK;
-break;
- case GL_FRONT_AND_BACK:
-dw1 |= GEN7_CLIP_CULLMODE_BOTH;
-break;
- default:
-unreachable("Should not get here: invalid CullFlag");
- }
-  } else {
- dw1 |= GEN7_CLIP_CULLMODE_NONE;
-  }
-   }
-
-   if (brw->gen < 8 && !ctx->Transform.DepthClamp)
-  dw2 |= GEN6_CLIP_Z_TEST;
-
-   /* _NEW_LIGHT */
-   if (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
-  dw2 |=
-(0 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
-(1 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
-(0 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
-   } else {
-  dw2 |=
-(2 << GEN6_CLIP_TRI_PROVOKE_SHIFT) |
-(2 << GEN6_CLIP_TRIFAN_PROVOKE_SHIFT) |
-(1 << GEN6_CLIP_LINE_PROVOKE_SHIFT);
-   }
-
-   /* _NEW_TRANSFORM */
-   dw2 |= (ctx->Transform.ClipPlanesEnabled <<
-   GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT);
-
-   /* Have the hardware use the user clip distance clip test enable bitmask
-* specified here in 3DSTATE_CLIP rather than the one in 3DSTATE_VS/DS/GS.
-* We already listen to _NEW_TRANSFORM here, but the other atoms don't
-* need to other than this.
-*/
-   if (brw->gen >= 8)
-  dw1 |= GEN8_CLIP_FORCE_USER_CLIP_DISTANCE_BITMASK;
-
-   if (ctx->Transform.ClipDepthMode == GL_ZERO_TO_ONE)
-  dw2 |= GEN6_CLIP_API_D3D;
-   else
-  dw2 |= GEN6_CLIP_API_OGL;
-
-   dw2 |= GEN6_CLIP_GB_TEST;
-
-   /* BRW_NEW_VIEWPORT_COUNT */
-   const unsigned viewport_count = brw->clip.viewport_count;
-
-   /* BRW_NEW_RASTERIZER_DISCARD */
-   if (ctx->RasterDiscard) {
-  dw2 |= GEN6_CLIP_MODE_REJECT_ALL;
-  if (brw->gen == 6) {
- perf_debug("Rasterizer discard is currently implemented via the "
-"clipper; having the GS not write primitives would "
-"likely be faster.\n");
-  }
-   }
-
-   uint32_t enable;
-   if (brw->primitive == _3DPRIM_RECTLIST)
-  enable = 0;
-   else
-  enable = GEN6_CLIP_ENABLE;
-
-   /* _NEW_POLYGON,
-* BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
-*/
-   if (!brw_is_drawing_points(brw) && !brw_is_drawing_lines(brw))
-  dw2 |= GEN6_CLIP_XY_TEST;
-
-   BEGIN_BATCH(4);
-   OUT_BATCH(_3DSTATE_CLIP 

[Mesa-dev] [PATCH v02 36/37] i965: Port gen6+ 3DSTATE_CC_STATE_POINTERS state to genxml.

[Rafael Antognolli]

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|  1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  1 +-
 src/mesa/drivers/dri/i965/gen6_cc.c   | 90 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 53 +++-
 4 files changed, 50 insertions(+), 95 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_cc.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index b52b08b..098ceba 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -76,7 +76,6 @@ i965_FILES = \
brw_wm.h \
brw_wm_state.c \
brw_wm_surface_state.c \
-   gen6_cc.c \
gen6_clip_state.c \
gen6_constant_state.c \
gen6_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 2b5b1c4..29e83cb 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -107,7 +107,6 @@ extern const struct brw_tracked_state brw_index_buffer;
 extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
-extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c 
b/src/mesa/drivers/dri/i965/gen6_cc.c
deleted file mode 100644
index 688362f..000
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt <e...@anholt.net>
- *
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "intel_batchbuffer.h"
-#include "main/macros.h"
-#include "main/enums.h"
-#include "main/glformats.h"
-#include "main/stencil.h"
-
-static void
-gen6_upload_color_calc_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   struct gen6_color_calc_state *cc;
-
-   cc = brw_state_batch(brw, sizeof(*cc), 64, >cc.state_offset);
-   memset(cc, 0, sizeof(*cc));
-
-   /* _NEW_COLOR */
-   cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
-   UNCLAMPED_FLOAT_TO_UBYTE(cc->cc1.alpha_ref_fi.ui, ctx->Color.AlphaRef);
-
-   if (brw->gen < 9) {
-  /* _NEW_STENCIL */
-  cc->cc0.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
-  cc->cc0.bf_stencil_ref =
- _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
-   }
-
-   /* _NEW_COLOR */
-   cc->constant_r = ctx->Color.BlendColorUnclamped[0];
-   cc->constant_g = ctx->Color.BlendColorUnclamped[1];
-   cc->constant_b = ctx->Color.BlendColorUnclamped[2];
-   cc->constant_a = ctx->Color.BlendColorUnclamped[3];
-
-   /* Point the GPU at the new indirect state. */
-   if (brw->gen == 6) {
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(brw->cc.state_offset | 1);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(2);
-  OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
-  OUT_BATCH(brw->cc.state_offset | 1);
-  ADVANCE_BATCH();
-   }
-}
-
-const struct brw_tracked_state gen6_color_calc_state = {
-   .dirty = {
-  .mesa = _NEW_COLOR |
-  _NEW_STENCIL,
-  .brw = BRW_NEW_BATCH |
- BRW_NEW_BLORP |
- BRW_

[Mesa-dev] [PATCH v02 03/37] genxml: Rename clip enable property.

[Rafael Antognolli]

There are two variants:
   - Clip Enable
   - CLIP Enable (on gen6)

Rename everything to Clip Enable.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/genxml/gen4.xml  | 2 +-
 src/intel/genxml/gen45.xml | 2 +-
 src/intel/genxml/gen5.xml  | 2 +-
 src/intel/genxml/gen6.xml  | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index 0ea66e5..d3a2f92 100644
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -968,7 +968,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index bff32f9..547e278 100644
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -935,7 +935,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index fc6f248..0b84650 100644
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -1091,7 +1091,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 3059bfc..094887a 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -806,7 +806,7 @@
 
 
 
-
+
 
   
   
-- 
git-series 0.9.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v02 28/37] i965: Port gen6+ 3DSTATE_VS to genxml.

[Rafael Antognolli]

Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/brw_state.h |   3 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c | 113 +---
 src/mesa/drivers/dri/i965/gen7_vs_state.c |  87 +---
 src/mesa/drivers/dri/i965/gen8_vs_state.c |  96 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 106 +-
 6 files changed, 103 insertions(+), 304 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_vs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 7f25ae1..95d29ac 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -100,7 +100,6 @@ i965_FILES = \
gen7_te_state.c \
gen7_urb.c \
gen7_viewport_state.c \
-   gen7_vs_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
gen8_depth_state.c \
@@ -111,7 +110,6 @@ i965_FILES = \
gen8_multisample_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
-   gen8_vs_state.c \
hsw_queryobj.c \
hsw_sol.c \
intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index a87bf3a..72d63f6 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -123,7 +123,6 @@ extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
-extern const struct brw_tracked_state gen6_vs_state;
 extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_ds_state;
@@ -136,7 +135,6 @@ extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
-extern const struct brw_tracked_state gen7_vs_state;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_ds_state;
@@ -149,7 +147,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
-extern const struct brw_tracked_state gen8_vs_state;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
 
 static inline bool
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 17b8118..b2d2306 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -68,116 +68,3 @@ const struct brw_tracked_state gen6_vs_push_constants = {
},
.emit = gen6_upload_vs_push_constants,
 };
-
-static void
-upload_vs_state(struct brw_context *brw)
-{
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   const struct brw_stage_state *stage_state = >vs.base;
-   const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
-   const struct brw_vue_prog_data *vue_prog_data =
-  brw_vue_prog_data(stage_state->prog_data);
-   uint32_t floating_point_mode = 0;
-
-   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
-* 3DSTATE_VS, Dword 5.0 "VS Function Enable":
-*
-*   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
-*   command that causes the VS Function Enable to toggle. Pipeline
-*   flush can be executed by sending a PIPE_CONTROL command with CS
-*   stall bit set and a post sync operation.
-*
-* We've already done such a flush at the start of state upload, so we
-* don't need to do another one here.
-*/
-
-   if (stage_state->push_const_size == 0) {
-  /* Disable the push constant buffers. */
-  BEGIN_BATCH(5);
-  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(5);
-  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
-   GEN6_CONSTANT_BUFFER_0_ENABLE |
-   (5 - 2));
-  /* Pointer to the VS constant buffer.  Covered by the set of
-   * state flags from gen6_upload_vs_constants
-   */
-  OUT_BATCH(stage_state->push_const

[Mesa-dev] [PATCH v02 14/37] anv: Use BRW_BARYCENTRIC_NONPERSPECTIVE_BITS from common header.

[Rafael Antognolli]

In a previous patch some enums were split out from brw_eu_defines.h, so
they could be used by genxml based code. anv can also benefit from this.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/vulkan/genX_pipeline.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index a6b4134..cf444c9 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -28,6 +28,7 @@
 
 #include "common/gen_l3_config.h"
 #include "common/gen_sample_positions.h"
+#include "compiler/brw_defines_common.h"
 #include "vk_format_info.h"
 
 static uint32_t
@@ -1059,7 +1060,8 @@ emit_3dstate_clip(struct anv_pipeline *pipeline,
   }
 #else
   clip.NonPerspectiveBarycentricEnable = wm_prog_data ?
- (wm_prog_data->barycentric_interp_modes & 0x38) != 0 : 0;
+ (wm_prog_data->barycentric_interp_modes &
+  BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) != 0 : 0;
 #endif
}
 }
-- 
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[Mesa-dev] [PATCH v02 15/37] i965: Add genxml related plumbing in a new genX_state_upload.c file.

[Rafael Antognolli]

From: Kenneth Graunke 

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/Makefile.sources|  15 ++-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 109 +++-
 2 files changed, 119 insertions(+), 5 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/genX_state_upload.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index aef1a7a..db55a3f 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -161,19 +161,24 @@ i965_FILES = \
libdrm_macros.h
 
 i965_gen6_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen7_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen75_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen8_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_gen9_FILES = \
-   genX_blorp_exec.c
+   genX_blorp_exec.c \
+   genX_state_upload.c
 
 i965_oa_GENERATED_FILES = \
brw_oa_hsw.h \
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
new file mode 100644
index 000..25bf4b6
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include 
+
+#include "common/gen_device_info.h"
+#include "genxml/gen_macros.h"
+
+#include "brw_context.h"
+#include "brw_state.h"
+
+#include "intel_batchbuffer.h"
+
+UNUSED static void *
+emit_dwords(struct brw_context *brw, unsigned n)
+{
+   intel_batchbuffer_begin(brw, n, RENDER_RING);
+   uint32_t *map = brw->batch.map_next;
+   brw->batch.map_next += n;
+   intel_batchbuffer_advance(brw);
+   return map;
+}
+
+struct brw_address {
+   struct brw_bo *bo;
+   uint32_t read_domains;
+   uint32_t write_domain;
+   uint32_t offset;
+};
+
+static uint64_t
+emit_reloc(struct brw_context *brw,
+   void *location, struct brw_address address, uint32_t delta)
+{
+   uint32_t offset = (char *) location - (char *) brw->batch.map;
+
+   return brw_emit_reloc(>batch, offset, address.bo,
+ address.offset + delta,
+ address.read_domains,
+ address.write_domain);
+}
+
+#define __gen_address_type struct brw_address
+#define __gen_user_data struct brw_context
+
+static uint64_t
+__gen_combine_address(struct brw_context *brw, void *location,
+  struct brw_address address, uint32_t delta)
+{
+   if (address.bo == NULL) {
+  return address.offset + delta;
+   } else {
+  return emit_reloc(brw, location, address, delta);
+   }
+}
+
+#include "genxml/genX_pack.h"
+
+#define _brw_cmd_length(cmd) cmd ## _length
+#define _brw_cmd_length_bias(cmd) cmd ## _length_bias
+#define _brw_cmd_header(cmd) cmd ## _header
+#define _brw_cmd_pack(cmd) cmd ## _pack
+
+#define brw_batch_emit(brw, cmd, name)  \
+   for (struct cmd name = { _brw_cmd_header(cmd) }, \
+*_dst = emit_dwords(brw, _brw_cmd_length(cmd)); \
+__builtin_expect(_dst != NULL, 1);  \
+_brw_cmd_pack(cmd)(brw, (void *)_dst, ),   \
+_dst = NULL)
+
+#define brw_batch_emitn(brw, cmd, n) ({\
+  uint32_t *_dw = emit_dwords(brw, n); \
+  struct cmd template = {  \
+ _brw_cmd_header(cmd), \
+ .DWordLength = n - _brw_cmd_length_bias(cmd), \
+  };   \
+  _brw_cmd_pack(cmd)(brw, _dw, ); \
+  _dw + 1; /* Array starts at dw[1] */ \
+   })
+
+#define 

[Mesa-dev] [PATCH v02 06/37] genxml: Add alias for MOCS.

[Rafael Antognolli]

Use an alias, so we can set the same value as the #define's.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/genxml/gen8.xml | 1 +
 src/intel/genxml/gen9.xml | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 408d241..2908082 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2064,6 +2064,7 @@
 
 
 
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 59daa31..09b9464 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2246,6 +2246,7 @@
 
 
 
+
 
 
 
-- 
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[Mesa-dev] [PATCH v02 25/37] i965: Port gen7+ 3DSTATE_PS to genxml.

[Rafael Antognolli]

Emit 3DSTATE_PS on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_state.h |   2 +-
 src/mesa/drivers/dri/i965/gen7_wm_state.c | 137 +---
 src/mesa/drivers/dri/i965/gen8_ps_state.c | 114 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 133 +-
 4 files changed, 131 insertions(+), 255 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 94f758b..c55c175 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -132,7 +132,6 @@ extern const struct brw_tracked_state gen7_gs_state;
 extern const struct brw_tracked_state gen7_tcs_push_constants;
 extern const struct brw_tracked_state gen7_hs_state;
 extern const struct brw_tracked_state gen7_l3_state;
-extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
@@ -150,7 +149,6 @@ extern const struct brw_tracked_state 
gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
-extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c 
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 1c33db4..c9c36ae 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -144,140 +144,3 @@ const struct brw_tracked_state gen7_wm_state = {
},
.emit = upload_wm_state,
 };
-
-static void
-gen7_upload_ps_state(struct brw_context *brw,
- const struct brw_stage_state *stage_state,
- const struct brw_wm_prog_data *prog_data,
- bool enable_dual_src_blend, unsigned sample_mask,
- unsigned fast_clear_op)
-{
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   uint32_t dw2, dw4, dw5, ksp0, ksp2;
-   const int max_threads_shift = brw->is_haswell ?
-  HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
-
-   dw2 = dw4 = dw5 = ksp2 = 0;
-
-   const unsigned sampler_count =
-  DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
-   dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
-
-   dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
-   GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
-
-   if (prog_data->base.use_alt_mode)
-  dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
-
-   /* Haswell requires the sample mask to be set in this packet as well as
-* in 3DSTATE_SAMPLE_MASK; the values should match. */
-   /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
-   if (brw->is_haswell)
-  dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
-
-   dw4 |= (devinfo->max_wm_threads - 1) << max_threads_shift;
-
-   if (prog_data->base.nr_params > 0)
-  dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
-
-   /* From the IVB PRM, volume 2 part 1, page 287:
-* "This bit is inserted in the PS payload header and made available to
-* the DataPort (either via the message header or via header bypass) to
-* indicate that oMask data (one or two phases) is included in Render
-* Target Write messages. If present, the oMask data is used to mask off
-* samples."
-*/
-   if (prog_data->uses_omask)
-  dw4 |= GEN7_PS_OMASK_TO_RENDER_TARGET;
-
-   /* From the IVB PRM, volume 2 part 1, page 287:
-* "If the PS kernel does not need the Position XY Offsets to
-* compute a Position Value, then this field should be programmed
-* to POSOFFSET_NONE."
-* "SW Recommendation: If the PS kernel needs the Position Offsets
-* to compute a Position XY value, this field should match Position
-* ZW Interpolation Mode to ensure a consistent position.xyzw
-* computation."
-* We only require XY sample offsets. So, this recommendation doesn't
-* look useful at the moment. We might need this in future.
-*/
-   if (prog_data->uses_pos_offset)
-  dw4 |= GEN7_PS_POSOFFSET_SAMPLE;
-   else
-  dw4 |= GEN7_PS_POSOFFSET_NONE;
-
-   /* The hardware wedges if you have this bit set but don't turn on any dual
-* source blend factors.
-*/
-   if (enable_dual_src_blend)
-  dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
-
-   /* BRW_NEW_FS_PROG_DATA */
-   if (prog_data->num_varying_inputs != 0)
-  dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
-
-   dw4 |= fast_clear_op;
-
-   if

[Mesa-dev] [PATCH v02 05/37] genxml: Add missing field values to 3DSTATE_SBE.

[Rafael Antognolli]

Fill out "Attribute Active Component Format" possible values.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/genxml/gen9.xml | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index ee7056b..59daa31 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2173,7 +2173,12 @@
 
 
 
-  
+  
+ 
+ 
+ 
+ 
+  
 
   
 
-- 
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[Mesa-dev] [PATCH v02 22/37] i965: Port Gen7+ 3DSTATE_SBE state to genxml.

[Rafael Antognolli]

Emit 3DSTATE_SBE on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use ACTIVE_COMPONENT_XYZW from gen9.xml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/brw_state.h |   2 +-
 src/mesa/drivers/dri/i965/gen7_sf_state.c | 109 +--
 src/mesa/drivers/dri/i965/gen8_sf_state.c | 153 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 129 +++-
 5 files changed, 121 insertions(+), 274 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_sf_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_sf_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index b085251..81759ed 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -97,7 +97,6 @@ i965_FILES = \
gen7_hs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
-   gen7_sf_state.c \
gen7_sol_state.c \
gen7_te_state.c \
gen7_urb.c \
@@ -113,7 +112,6 @@ i965_FILES = \
gen8_hs_state.c \
gen8_multisample_state.c \
gen8_ps_state.c \
-   gen8_sf_state.c \
gen8_sol_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 594757c..bc68c2c 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -134,7 +134,6 @@ extern const struct brw_tracked_state gen7_hs_state;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_sbe_state;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_sol_state;
 extern const struct brw_tracked_state gen7_te_state;
@@ -154,7 +153,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
-extern const struct brw_tracked_state gen8_sbe_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c 
b/src/mesa/drivers/dri/i965/gen7_sf_state.c
deleted file mode 100644
index 7ab8a99..000
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "main/macros.h"
-#include "main/fbobject.h"
-#include "main/framebuffer.h"
-#include "intel_batchbuffer.h"
-
-static void
-upload_sbe_state(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_FS_PROG_DATA */
-   const struct brw_wm_prog_data *wm_prog_data =
-  brw_wm_prog_data(brw->wm.base.prog_data);
-   uint32_t num_outputs = wm_prog_data->num_varying_inputs;
-   uint32_t dw1;
-   uint32_t point_sprite_enables;
-   int i;
-   uint16_t attr_overrides[16];
-   /* _NEW_BUFFERS */
-   bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
-   uint32_t point_sprite_origin;
-
-   /* FINISHME: Attribute Swizzle Control Mode? */
-   dw1 = GEN7_SBE_SWIZZLE_ENABLE | num_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT;
-
-   /* _NEW_POINT
-*
-* Window coordinates in an FBO are 

[Mesa-dev] [PATCH v02 26/37] i965: Port gen6+ 3DSTATE_WM to genxml.

[Rafael Antognolli]

Emit 3DSTATE_WM on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Use render_bo helper to setup brw_address (Kristian)
   - Remove TODO and use BRW_PSCDEPTH_OFF.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  14 +-
 src/mesa/drivers/dri/i965/gen6_wm_state.c | 219 +---
 src/mesa/drivers/dri/i965/gen7_wm_state.c | 146 +-
 src/mesa/drivers/dri/i965/gen8_ps_state.c |  49 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 192 -
 6 files changed, 189 insertions(+), 432 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_wm_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index bfcf57c..da09df8 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -101,7 +101,6 @@ i965_FILES = \
gen7_urb.c \
gen7_viewport_state.c \
gen7_vs_state.c \
-   gen7_wm_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
gen8_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index c55c175..5010237 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -125,7 +125,6 @@ extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
 extern const struct brw_tracked_state gen6_vs_state;
 extern const struct brw_tracked_state gen6_wm_push_constants;
-extern const struct brw_tracked_state gen6_wm_state;
 extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_ds_state;
 extern const struct brw_tracked_state gen7_gs_state;
@@ -138,7 +137,6 @@ extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state gen7_vs_state;
-extern const struct brw_tracked_state gen7_wm_state;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_ds_state;
@@ -149,7 +147,6 @@ extern const struct brw_tracked_state 
gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
-extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
@@ -320,17 +317,6 @@ void brw_emit_sampler_state(struct brw_context *brw,
 bool non_normalized_coordinates,
 uint32_t border_color_offset);
 
-/* gen6_wm_state.c */
-void
-gen6_upload_wm_state(struct brw_context *brw,
- const struct brw_wm_prog_data *prog_data,
- const struct brw_stage_state *stage_state,
- bool multisampled_fbo,
- bool dual_source_blend_enable, bool kill_enable,
- bool color_buffer_write_enable, bool msaa_enabled,
- bool line_stipple_enable, bool polygon_stipple_enable,
- bool statistic_enable);
-
 /* gen6_surface_state.c */
 void gen6_init_vtable_surface_functions(struct brw_context *brw);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c 
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index aabae70..9da1bdd 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -68,222 +68,3 @@ const struct brw_tracked_state gen6_wm_push_constants = {
},
.emit = gen6_upload_wm_push_constants,
 };
-
-void
-gen6_upload_wm_state(struct brw_context *brw,
- const struct brw_wm_prog_data *prog_data,
- const struct brw_stage_state *stage_state,
- bool multisampled_fbo,
- bool dual_source_blend_enable, bool kill_enable,
- bool color_buffer_write_enable, bool msaa_enabled,
- bool line_stipple_enable, bool polygon_stipple_enable,
- bool statistic_enable)
-{
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2;
-
-   /* We can't fold this into gen6_upload_wm_push_constants(), because
-* according to the SNB PRM, vol 2 part 1 section 7.2.2
-* (3DSTATE_CONSTANT_PS [DevSNB]):
-*
-* "[DevSNB]: This packet must be followed by WM_STATE."
-*/
-   if (prog_data->base.nr_params == 0) {
-  /* Disable the push constant buffers

[Mesa-dev] [PATCH v02 11/37] genxml: Normalize xml for 3DSTATE_MULTISAMPLE.

[Rafael Antognolli]

Name the options to "Pixel Location":
   - PIXLOC_CENTER -> CENTER
   - PIXLOC_UL_CORNER -> UL_CORNER

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/blorp/blorp_genX_exec.h | 4 +---
 src/intel/genxml/gen6.xml | 4 ++--
 src/intel/genxml/gen7.xml | 4 ++--
 src/intel/genxml/gen75.xml| 4 ++--
 src/intel/vulkan/genX_pipeline.c  | 3 +--
 5 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index bc829d0..be22be0 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1188,9 +1188,7 @@ blorp_emit_3dstate_multisample(struct blorp_batch *batch,
*should not have any effect by setting or not setting this bit.
*/
   ms.PixelPositionOffsetEnable  = false;
-  ms.PixelLocation  = CENTER;
 #elif GEN_GEN >= 7
-  ms.PixelLocation  = PIXLOC_CENTER;
 
   switch (params->num_samples) {
   case 1:
@@ -1209,9 +1207,9 @@ blorp_emit_3dstate_multisample(struct blorp_batch *batch,
  break;
   }
 #else
-  ms.PixelLocation  = PIXLOC_CENTER;
   GEN_SAMPLE_POS_4X(ms.Sample);
 #endif
+  ms.PixelLocation  = CENTER;
}
 }
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 2cb9419..a8ce7e0 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1089,8 +1089,8 @@
 
 
 
-  
-  
+  
+  
 
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index b4407d4..8530ed9 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1262,8 +1262,8 @@
 
 
 
-  
-  
+  
+  
 
 
   
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 8c8b776..07eafee 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -1548,8 +1548,8 @@
 
 
 
-  
-  
+  
+  
 
 
   
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 2b38c34..a6b4134 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -549,6 +549,7 @@ emit_ms_state(struct anv_pipeline *pipeline,
anv_batch_emit(>batch, GENX(3DSTATE_MULTISAMPLE), ms) {
   ms.NumberofMultisamples   = log2_samples;
 
+  ms.PixelLocation  = CENTER;
 #if GEN_GEN >= 8
   /* The PRM says that this bit is valid only for DX9:
*
@@ -556,9 +557,7 @@ emit_ms_state(struct anv_pipeline *pipeline,
*should not have any effect by setting or not setting this bit.
*/
   ms.PixelPositionOffsetEnable  = false;
-  ms.PixelLocation  = CENTER;
 #else
-  ms.PixelLocation  = PIXLOC_CENTER;
 
   switch (samples) {
   case 1:
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v02 30/37] i965: Port gen6+ blend state code to genxml.

[Rafael Antognolli]

Upload blend states using GENX(BLEND_STATE_ENTRY_pack), generated from
genxml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |   3 +-
 src/mesa/drivers/dri/i965/gen6_cc.c   | 216 +
 src/mesa/drivers/dri/i965/gen8_blend_state.c  | 298 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 336 ++-
 5 files changed, 332 insertions(+), 522 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_blend_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 3f0c66a..0c67170 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -99,7 +99,6 @@ i965_FILES = \
gen7_te_state.c \
gen7_urb.c \
gen7_wm_surface_state.c \
-   gen8_blend_state.c \
gen8_depth_state.c \
gen8_draw_upload.c \
gen8_multisample_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index b6e8abc..cf043a0 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -108,7 +108,6 @@ extern const struct brw_tracked_state brw_index_buffer;
 extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
-extern const struct brw_tracked_state gen6_blend_state;
 extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
@@ -130,11 +129,9 @@ extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
-extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_index_buffer;
 extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
-extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c 
b/src/mesa/drivers/dri/i965/gen6_cc.c
index 0e0d05e..688362f 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -36,222 +36,6 @@
 #include "main/stencil.h"
 
 static void
-gen6_upload_blend_state(struct brw_context *brw)
-{
-   bool is_buffer_zero_integer_format = false;
-   struct gl_context *ctx = >ctx;
-   struct gen6_blend_state *blend;
-   int b;
-   int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers;
-   int size;
-
-   /* We need at least one BLEND_STATE written, because we might do
-* thread dispatch even if _NumColorDrawBuffers is 0 (for example
-* for computed depth or alpha test), which will do an FB write
-* with render target 0, which will reference BLEND_STATE[0] for
-* alpha test enable.
-*/
-   if (nr_draw_buffers == 0)
-  nr_draw_buffers = 1;
-
-   size = sizeof(*blend) * nr_draw_buffers;
-   blend = brw_state_batch(brw, size, 64, >cc.blend_state_offset);
-
-   memset(blend, 0, size);
-
-   for (b = 0; b < nr_draw_buffers; b++) {
-  /* _NEW_BUFFERS */
-  struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[b];
-  GLenum rb_type;
-  bool integer;
-
-  if (rb)
-rb_type = _mesa_get_format_datatype(rb->Format);
-  else
-rb_type = GL_UNSIGNED_NORMALIZED;
-
-  /* Used for implementing the following bit of GL_EXT_texture_integer:
-   * "Per-fragment operations that require floating-point color
-   *  components, including multisample alpha operations, alpha test,
-   *  blending, and dithering, have no effect when the corresponding
-   *  colors are written to an integer color buffer."
-  */
-  integer = (rb_type == GL_INT || rb_type == GL_UNSIGNED_INT);
-
-  if(b == 0 && integer)
- is_buffer_zero_integer_format = true;
-
-  /* _NEW_COLOR */
-  if (ctx->Color.ColorLogicOpEnabled) {
-/* Floating point RTs should have no effect from LogicOp,
- * except for disabling of blending, but other types should.
- *
- * However, from the Sandy Bridge PRM, Vol 2 Par 1, Section 8.1.11,
- * "Logic Ops",
- *
- * "Logic Ops are only supported on *_UNORM surfaces (excluding
- *  _SRGB variants), otherwise Logic Ops must be DISABLED."
- */
- WARN_ONCE(ctx-&

[Mesa-dev] [PATCH v02 32/37] i965: Port gen6+ 3DSTATE_SCISSOR_STATE_POINTERS to use genxml.

[Rafael Antognolli]

Emit 3DSTATE_SCISSOR_STATE_POINTERS using brw_batch_emit, and pack the
scissor states using GENX(SCISSOR_RECT_pack), generated from genxml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_state.h |  1 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 89 +++-
 2 files changed, 86 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 322d767..6adcf46 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -114,7 +114,6 @@ extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_multisample_state;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
-extern const struct brw_tracked_state gen6_scissor_state;
 extern const struct brw_tracked_state gen6_sol_surface;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 45b02a6..3ad9707 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -1651,6 +1651,89 @@ static const struct brw_tracked_state genX(blend_state) 
= {
.emit = genX(upload_blend_state),
 };
 
+/* -- */
+
+static void
+genX(upload_scissor_state)(struct brw_context *brw)
+{
+   struct gl_context *ctx = >ctx;
+   const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
+   struct GENX(SCISSOR_RECT) scissor;
+   uint32_t scissor_state_offset;
+   const unsigned int fb_width= _mesa_geometric_width(ctx->DrawBuffer);
+   const unsigned int fb_height = _mesa_geometric_height(ctx->DrawBuffer);
+   uint32_t *scissor_map;
+
+   /* BRW_NEW_VIEWPORT_COUNT */
+   const unsigned viewport_count = brw->clip.viewport_count;
+
+   scissor_map = brw_state_batch(
+  brw, GENX(SCISSOR_RECT_length) * sizeof(uint32_t) * viewport_count,
+  32, _state_offset);
+
+   /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
+
+   /* The scissor only needs to handle the intersection of drawable and
+* scissor rect.  Clipping to the boundaries of static shared buffers
+* for front/back/depth is covered by looping over cliprects in brw_draw.c.
+*
+* Note that the hardware's coordinates are inclusive, while Mesa's min is
+* inclusive but max is exclusive.
+*/
+   for (unsigned i = 0; i < viewport_count; i++) {
+  int bbox[4];
+
+  bbox[0] = MAX2(ctx->ViewportArray[i].X, 0);
+  bbox[1] = MIN2(bbox[0] + ctx->ViewportArray[i].Width, fb_width);
+  bbox[2] = MAX2(ctx->ViewportArray[i].Y, 0);
+  bbox[3] = MIN2(bbox[2] + ctx->ViewportArray[i].Height, fb_height);
+  _mesa_intersect_scissor_bounding_box(ctx, i, bbox);
+
+  if (bbox[0] == bbox[1] || bbox[2] == bbox[3]) {
+ /* If the scissor was out of bounds and got clamped to 0 width/height
+  * at the bounds, the subtraction of 1 from maximums could produce a
+  * negative number and thus not clip anything.  Instead, just provide
+  * a min > max scissor inside the bounds, which produces the expected
+  * no rendering.
+  */
+ scissor.ScissorRectangleXMin = 1;
+ scissor.ScissorRectangleXMax = 0;
+ scissor.ScissorRectangleYMin = 1;
+ scissor.ScissorRectangleYMax = 0;
+  } else if (render_to_fbo) {
+ /* texmemory: Y=0=bottom */
+ scissor.ScissorRectangleXMin = bbox[0];
+ scissor.ScissorRectangleXMax = bbox[1] - 1;
+ scissor.ScissorRectangleYMin = bbox[2];
+ scissor.ScissorRectangleYMax = bbox[3] - 1;
+  } else {
+ /* memory: Y=0=top */
+ scissor.ScissorRectangleXMin = bbox[0];
+ scissor.ScissorRectangleXMax = bbox[1] - 1;
+ scissor.ScissorRectangleYMin = fb_height - bbox[3];
+ scissor.ScissorRectangleYMax = fb_height - bbox[2] - 1;
+  }
+
+  GENX(SCISSOR_RECT_pack)(NULL, scissor_map + i * 2, );
+   }
+
+   brw_batch_emit(brw, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
+  ptr.ScissorRectPointer = scissor_state_offset;
+   }
+}
+
+static const struct brw_tracked_state genX(scissor_state) = {
+   .dirty = {
+  .mesa = _NEW_BUFFERS |
+  _NEW_SCISSOR |
+  _NEW_VIEWPORT,
+  .brw = BRW_NEW_BATCH |
+ BRW_NEW_BLORP |
+ BRW_NEW_VIEWPORT_COUNT,
+   },
+   .emit = genX(upload_scissor_state),
+};
+
 #endif
 
 /* -- */
@@ -2771,7 +2854,7 @@ genX(init_atoms)(struct brw_context *brw)
   (sf_state),
   (wm_state),
 
-  _scissor_state,
+  (scissor_state),
 
   _binding_table_pointers,
 
@@ -28

[Mesa-dev] [PATCH v02 04/37] genxml: Update xml for 3DSTATE_SF.

[Rafael Antognolli]

- Normalize "Anti-Aliasing Enable"
 - Add "Multisample Rasterization Mode" constants
 - Rename "Use Point Width on Vertex" to "Vertex"
 - Rename "Use Point Width from State" to "State"

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/genxml/gen6.xml | 15 ++-
 src/intel/genxml/gen7.xml |  7 ++-
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 094887a..8ead41f 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1215,7 +1215,7 @@
   
   
 
-
+
 
   
   
@@ -1230,7 +1230,12 @@
   
 
 
-
+
+  
+  
+  
+  
+
 
 
   
@@ -1253,9 +1258,9 @@
   
   
 
-
-  
-  
+
+  
+  
 
 
 
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 867a1d4..440258a 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1602,7 +1602,12 @@
   
 
 
-
+
+  
+  
+  
+  
+   
 
 
   
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v02 29/37] i965: Port gen6+ state emitting code to genxml.

[Rafael Antognolli]

Ported in this patch:
   - 3DSTATE_DS
   - 3DSTATE_GS
   - 3DSTATE_HS
   - 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources  |   6 +-
 src/mesa/drivers/dri/i965/brw_state.h   |  18 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c   | 129 +-
 src/mesa/drivers/dri/i965/gen6_viewport_state.c | 147 +--
 src/mesa/drivers/dri/i965/gen7_ds_state.c   |  69 +---
 src/mesa/drivers/dri/i965/gen7_gs_state.c   | 168 +--
 src/mesa/drivers/dri/i965/gen7_hs_state.c   |  63 +--
 src/mesa/drivers/dri/i965/gen7_viewport_state.c | 100 +
 src/mesa/drivers/dri/i965/gen8_ds_state.c   | 116 +
 src/mesa/drivers/dri/i965/gen8_gs_state.c   | 146 +-
 src/mesa/drivers/dri/i965/gen8_hs_state.c   |  93 +---
 src/mesa/drivers/dri/i965/gen8_viewport_state.c | 120 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c   | 453 -
 13 files changed, 446 insertions(+), 1182 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_gs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_viewport_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_ds_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_gs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_hs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_viewport_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 95d29ac..3f0c66a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -92,24 +92,18 @@ i965_FILES = \
gen6_wm_state.c \
gen7_cs_state.c \
gen7_ds_state.c \
-   gen7_gs_state.c \
gen7_hs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
gen7_sol_state.c \
gen7_te_state.c \
gen7_urb.c \
-   gen7_viewport_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
gen8_depth_state.c \
gen8_draw_upload.c \
-   gen8_ds_state.c \
-   gen8_gs_state.c \
-   gen8_hs_state.c \
gen8_multisample_state.c \
gen8_surface_state.c \
-   gen8_viewport_state.c \
hsw_queryobj.c \
hsw_sol.c \
intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 72d63f6..b6e8abc 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,9 +109,7 @@ extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_blend_state;
-extern const struct brw_tracked_state gen6_sf_and_clip_viewports;
 extern const struct brw_tracked_state gen6_color_calc_state;
-extern const struct brw_tracked_state gen6_gs_state;
 extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_multisample_state;
@@ -125,26 +123,18 @@ extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
 extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
-extern const struct brw_tracked_state gen7_ds_state;
-extern const struct brw_tracked_state gen7_gs_state;
 extern const struct brw_tracked_state gen7_tcs_push_constants;
-extern const struct brw_tracked_state gen7_hs_state;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
-extern const struct brw_tracked_state gen8_ds_state;
-extern const struct brw_tracked_state gen8_gs_state;
-extern const struct brw_tracked_state gen8_hs_state;
 extern const struct brw_tracked_state gen8_index_buffer;
 extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_ps_blend;
-extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
@@ -383,12 +373,6 @@ use_state_point_size(const struct brw_context *brw)
   (brw->vue_map_geom_out.slots_valid & VARYING_BIT_PSIZ) == 0;
 }
 
-void brw_calculate_guardband_size(const struct gen_device_

[Mesa-dev] [PATCH v02 33/37] i965: Port push constant code to genxml.

[Rafael Antognolli]

The following states are ported on this patch:
   - gen6_gs_push_constants
   - gen6_vs_push_constants
   - gen6_wm_push_constants
   - gen7_tes_push_constants

v2:
   - Use helper to setup brw_address (Kristian)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   4 +-
 src/mesa/drivers/dri/i965/brw_state.h |   5 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c |  33 +---
 src/mesa/drivers/dri/i965/gen6_vs_state.c |  70 +--
 src/mesa/drivers/dri/i965/gen6_wm_state.c |  70 +--
 src/mesa/drivers/dri/i965/gen7_ds_state.c |  57 +-
 src/mesa/drivers/dri/i965/gen7_hs_state.c |  60 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 229 +--
 8 files changed, 216 insertions(+), 312 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_vs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_wm_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_ds_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_hs_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 0123913..b52b08b 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -88,11 +88,7 @@ i965_FILES = \
gen6_sol.c \
gen6_urb.c \
gen6_viewport_state.c \
-   gen6_vs_state.c \
-   gen6_wm_state.c \
gen7_cs_state.c \
-   gen7_ds_state.c \
-   gen7_hs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
gen7_sol_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 6adcf46..084f97f 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,7 +109,6 @@ extern const struct brw_tracked_state brw_cs_state;
 extern const struct brw_tracked_state gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_color_calc_state;
-extern const struct brw_tracked_state gen6_gs_push_constants;
 extern const struct brw_tracked_state gen6_gs_binding_table;
 extern const struct brw_tracked_state gen6_multisample_state;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
@@ -118,13 +117,9 @@ extern const struct brw_tracked_state gen6_sol_surface;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
-extern const struct brw_tracked_state gen6_vs_push_constants;
-extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
-extern const struct brw_tracked_state gen7_tcs_push_constants;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_index_buffer;
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c 
b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 6a9e951..6450c76 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -31,39 +31,6 @@
 #include "intel_batchbuffer.h"
 #include "main/shaderapi.h"
 
-static void
-gen6_upload_gs_push_constants(struct brw_context *brw)
-{
-   struct brw_stage_state *stage_state = >gs.base;
-
-   /* BRW_NEW_GEOMETRY_PROGRAM */
-   const struct brw_program *gp = brw_program_const(brw->geometry_program);
-
-   if (gp) {
-  /* BRW_NEW_GS_PROG_DATA */
-  struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
-
-  _mesa_shader_write_subroutine_indices(>ctx, MESA_SHADER_GEOMETRY);
-  gen6_upload_push_constants(brw, >program, prog_data, stage_state);
-   }
-
-   if (brw->gen >= 7)
-  gen7_upload_constant_state(brw, stage_state, gp, _3DSTATE_CONSTANT_GS);
-}
-
-const struct brw_tracked_state gen6_gs_push_constants = {
-   .dirty = {
-  .mesa  = _NEW_PROGRAM_CONSTANTS |
-   _NEW_TRANSFORM,
-  .brw   = BRW_NEW_BATCH |
-   BRW_NEW_BLORP |
-   BRW_NEW_GEOMETRY_PROGRAM |
-   BRW_NEW_GS_PROG_DATA |
-   BRW_NEW_PUSH_CONSTANT_ALLOCATION,
-   },
-   .emit = gen6_upload_gs_push_constants,
-};
-
 void
 upload_gs_state_for_tf(struct brw_context *brw)
 {
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
deleted file mode 100644
index b2d2306..000
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software an

[Mesa-dev] [PATCH v02 16/37] i965: Get real per-gen atom lists

[Rafael Antognolli]

From: Kenneth Graunke 

Make atoms initalization compile conditionally based on the target
platform.
---
 src/mesa/drivers/dri/i965/brw_state.h |  12 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c  | 385 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 340 +-
 3 files changed, 369 insertions(+), 368 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index ec79a4e..008326a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -441,6 +441,18 @@ void brw_calculate_guardband_size(const struct 
gen_device_info *devinfo,
   float *xmin, float *xmax,
   float *ymin, float *ymax);
 
+void brw_copy_pipeline_atoms(struct brw_context *brw,
+ enum brw_pipeline pipeline,
+ const struct brw_tracked_state **atoms,
+ int num_atoms);
+void gen4_init_atoms(struct brw_context *brw);
+void gen5_init_atoms(struct brw_context *brw);
+void gen6_init_atoms(struct brw_context *brw);
+void gen7_init_atoms(struct brw_context *brw);
+void gen75_init_atoms(struct brw_context *brw);
+void gen8_init_atoms(struct brw_context *brw);
+void gen9_init_atoms(struct brw_context *brw);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 9c0b82c..6c9c748 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -45,341 +45,6 @@
 #include "brw_cs.h"
 #include "main/framebuffer.h"
 
-static const struct brw_tracked_state *gen4_atoms[] =
-{
-   /* Once all the programs are done, we know how large urb entry
-* sizes need to be and can decide if we need to change the urb
-* layout.
-*/
-   _curbe_offsets,
-   _recalculate_urb_fence,
-
-   _cc_vp,
-   _cc_unit,
-
-   /* Surface state setup.  Must come before the VS/WM unit.  The binding
-* table upload must be last.
-*/
-   _vs_pull_constants,
-   _wm_pull_constants,
-   _renderbuffer_surfaces,
-   _renderbuffer_read_surfaces,
-   _texture_surfaces,
-   _vs_binding_table,
-   _wm_binding_table,
-
-   _fs_samplers,
-   _vs_samplers,
-
-   /* These set up state for brw_psp_urb_cbs */
-   _wm_unit,
-   _sf_vp,
-   _sf_unit,
-   _vs_unit,   /* always required, enabled or not */
-   _clip_unit,
-   _gs_unit,
-
-   /* Command packets:
-*/
-   _invariant_state,
-
-   _binding_table_pointers,
-   _blend_constant_color,
-
-   _depthbuffer,
-
-   _polygon_stipple,
-   _polygon_stipple_offset,
-
-   _line_stipple,
-
-   _psp_urb_cbs,
-
-   _drawing_rect,
-   _indices, /* must come before brw_vertices */
-   _index_buffer,
-   _vertices,
-
-   _constant_buffer
-};
-
-static const struct brw_tracked_state *gen6_atoms[] =
-{
-   _sf_and_clip_viewports,
-
-   /* Command packets: */
-
-   _cc_vp,
-   _viewport_state,   /* must do after *_vp stages */
-
-   _urb,
-   _blend_state,  /* must do before cc unit */
-   _color_calc_state, /* must do before cc unit */
-   _depth_stencil_state,  /* must do before cc unit */
-
-   _vs_push_constants, /* Before vs_state */
-   _gs_push_constants, /* Before gs_state */
-   _wm_push_constants, /* Before wm_state */
-
-   /* Surface state setup.  Must come before the VS/WM unit.  The binding
-* table upload must be last.
-*/
-   _vs_pull_constants,
-   _vs_ubo_surfaces,
-   _gs_pull_constants,
-   _gs_ubo_surfaces,
-   _wm_pull_constants,
-   _wm_ubo_surfaces,
-   _renderbuffer_surfaces,
-   _renderbuffer_read_surfaces,
-   _texture_surfaces,
-   _sol_surface,
-   _vs_binding_table,
-   _gs_binding_table,
-   _wm_binding_table,
-
-   _fs_samplers,
-   _vs_samplers,
-   _gs_samplers,
-   _sampler_state,
-   _multisample_state,
-
-   _vs_state,
-   _gs_state,
-   _clip_state,
-   _sf_state,
-   _wm_state,
-
-   _scissor_state,
-
-   _binding_table_pointers,
-
-   _depthbuffer,
-
-   _polygon_stipple,
-   _polygon_stipple_offset,
-
-   _line_stipple,
-
-   _drawing_rect,
-
-   _indices, /* must come before brw_vertices */
-   _index_buffer,
-   _vertices,
-};
-
-static const struct brw_tracked_state *gen7_render_atoms[] =
-{
-   /* Command packets: */
-
-   _cc_vp,
-   _sf_clip_viewport,
-
-   _l3_state,
-   _push_constant_space,
-   _urb,
-   _blend_state,  /* must do before cc unit */
-   _color_calc_state, /* must do before cc unit */
-   _depth_stencil_state,  /* must do before cc unit */
-
-   _vs_image_surfaces, /* Before vs push/pull constants and binding table 
*/
-   _tcs_image_surfaces, /* Before tcs push/pull constants and binding 
table */
-   _tes_image_surfaces, /* Before tes push/pull constants and binding 
table */
-   _gs_image_surfaces, /* Before gs push/pull constants and binding table 
*/
-   _wm_image_surfaces, /* Before wm push/pull 

[Mesa-dev] [PATCH v02 08/37] genxml: 3DSTATE_VS rename Function Enable to Enable.

[Rafael Antognolli]

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/blorp/blorp_genX_exec.h | 2 +-
 src/intel/genxml/gen6.xml | 2 +-
 src/intel/genxml/gen7.xml | 2 +-
 src/intel/genxml/gen75.xml| 2 +-
 src/intel/genxml/gen8.xml | 2 +-
 src/intel/genxml/gen9.xml | 2 +-
 src/intel/vulkan/genX_pipeline.c  | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 0bde2d2..bc829d0 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -432,7 +432,7 @@ blorp_emit_vs_config(struct blorp_batch *batch,
 
blorp_emit(batch, GENX(3DSTATE_VS), vs) {
   if (vs_prog_data) {
- vs.FunctionEnable = true;
+ vs.Enable = true;
 
  vs.KernelStartPointer = params->vs_prog_kernel;
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 14d643c..a12e22c 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1391,7 +1391,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index a351486..6af1cbe 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1863,7 +1863,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 9f0486c..793f733 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2191,7 +2191,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 2908082..a6c6d9d 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2352,7 +2352,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 09b9464..45eb454 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2585,7 +2585,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 2631ed0..74d6f9a 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1132,7 +1132,7 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
 
anv_batch_emit(>batch, GENX(3DSTATE_VS), vs) {
-  vs.FunctionEnable   = true;
+  vs.Enable   = true;
   vs.StatisticsEnable = true;
   vs.KernelStartPointer   = vs_bin->kernel.offset;
 #if GEN_GEN >= 8
-- 
git-series 0.9.1
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH v02 12/37] genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS.

[Rafael Antognolli]

- "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid"
   - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer"
   - "BackFace" -> "Backface"

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/blorp/blorp_genX_exec.h  | 4 ++--
 src/intel/genxml/gen6.xml  | 4 ++--
 src/intel/genxml/gen8.xml  | 2 +-
 src/intel/vulkan/gen8_cmd_buffer.c | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index be22be0..9e61f69 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1365,10 +1365,10 @@ blorp_exec(struct blorp_batch *batch, const struct 
blorp_params *params)
 */
blorp_emit(batch, GENX(3DSTATE_CC_STATE_POINTERS), cc) {
   cc.BLEND_STATEChange = true;
-  cc.COLOR_CALC_STATEChange = true;
+  cc.ColorCalcStatePointerValid = true;
   cc.DEPTH_STENCIL_STATEChange = true;
   cc.PointertoBLEND_STATE = blend_state_offset;
-  cc.PointertoCOLOR_CALC_STATE = color_calc_state_offset;
+  cc.ColorCalcStatePointer = color_calc_state_offset;
   cc.PointertoDEPTH_STENCIL_STATE = depth_stencil_state_offset;
}
 #else
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index a8ce7e0..cdcead3 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -773,8 +773,8 @@
 
 
 
-
-
+
+
   
 
   
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index f49c4a3..21db782 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -568,7 +568,7 @@
 
   
 
-
+
 
 
   
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c 
b/src/intel/vulkan/gen8_cmd_buffer.c
index c891a76..0e26dda 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -467,7 +467,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer 
*cmd_buffer)
  .BlendConstantColorBlue = 
cmd_buffer->state.dynamic.blend_constants[2],
  .BlendConstantColorAlpha = 
cmd_buffer->state.dynamic.blend_constants[3],
  .StencilReferenceValue = d->stencil_reference.front & 0xff,
- .BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
+ .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
   };
   GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, );
 
-- 
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[Mesa-dev] [PATCH v02 10/37] genxml: Rename "Function Enable" to "Enable".

[Rafael Antognolli]

Rename that field name on genxml for:
   - 3DSTATE_GS - gen6+
   - 3DSTATE_DS - gen7+
   - 3DSTATE_HS - gen7+

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/genxml/gen6.xml| 2 +-
 src/intel/genxml/gen7.xml| 6 +++---
 src/intel/genxml/gen75.xml   | 6 +++---
 src/intel/genxml/gen8.xml| 6 +++---
 src/intel/genxml/gen9.xml| 6 +++---
 src/intel/vulkan/genX_pipeline.c | 6 +++---
 6 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 2173dbf..2cb9419 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1014,7 +1014,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 6af1cbe..b4407d4 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1101,7 +1101,7 @@
 
 
 
-
+
   
 
   
@@ -1162,7 +1162,7 @@
   
 
 
-
+
 
   
 
@@ -1199,7 +1199,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 793f733..8c8b776 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -1292,7 +1292,7 @@
 
 
 
-
+
   
 
   
@@ -1440,7 +1440,7 @@
   
 
 
-
+
 
   
   
@@ -1484,7 +1484,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index a6c6d9d..f49c4a3 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -1350,7 +1350,7 @@
 
 
 
-
+
 
 
 
@@ -1506,7 +1506,7 @@
   
 
 
-
+
 
   
   
@@ -1555,7 +1555,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 45eb454..178cf73 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -1412,7 +1412,7 @@
 
 
 
-
+
 
 
 
@@ -1611,7 +1611,7 @@
   
 
 
-
+
 
   
   
@@ -1661,7 +1661,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 74d6f9a..2b38c34 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1192,7 +1192,7 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
 
anv_batch_emit(>batch, GENX(3DSTATE_HS), hs) {
-  hs.FunctionEnable = true;
+  hs.Enable = true;
   hs.StatisticsEnable = true;
   hs.KernelStartPointer = tcs_bin->kernel.offset;
 
@@ -1222,7 +1222,7 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
}
 
anv_batch_emit(>batch, GENX(3DSTATE_DS), ds) {
-  ds.FunctionEnable = true;
+  ds.Enable = true;
   ds.StatisticsEnable = true;
   ds.KernelStartPointer = tes_bin->kernel.offset;
 
@@ -1275,7 +1275,7 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 
anv_batch_emit(>batch, GENX(3DSTATE_GS), gs) {
-  gs.FunctionEnable  = true;
+  gs.Enable  = true;
   gs.StatisticsEnable= true;
   gs.KernelStartPointer  = gs_bin->kernel.offset;
   gs.DispatchMode= gs_prog_data->base.dispatch_mode;
-- 
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[Mesa-dev] [PATCH v02 09/37] genxml: Clip guardbands are float, not int.

[Rafael Antognolli]

This makes genxml create the right struct types, and generate the right
batch commands.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
 src/intel/genxml/gen6.xml | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index a12e22c..2173dbf 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -394,10 +394,10 @@
   
 
   
-
-
-
-
+
+
+
+
   
 
   
-- 
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[Mesa-dev] [PATCH v02 31/37] i965: Port gen7+ 3DSTATE_TE to genxml.

[Rafael Antognolli]

Emit 3DSTATE_TE on Gen7+ using brw_batch_emit helper.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|  1 +-
 src/mesa/drivers/dri/i965/brw_state.h |  1 +-
 src/mesa/drivers/dri/i965/gen7_te_state.c | 67 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 40 +++-
 4 files changed, 38 insertions(+), 71 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_te_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 0c67170..0123913 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -96,7 +96,6 @@ i965_FILES = \
gen7_l3_state.c \
gen7_misc_state.c \
gen7_sol_state.c \
-   gen7_te_state.c \
gen7_urb.c \
gen7_wm_surface_state.c \
gen8_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index cf043a0..322d767 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -125,7 +125,6 @@ extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_tcs_push_constants;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
-extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
diff --git a/src/mesa/drivers/dri/i965/gen7_te_state.c 
b/src/mesa/drivers/dri/i965/gen7_te_state.c
deleted file mode 100644
index e56fdcf..000
--- a/src/mesa/drivers/dri/i965/gen7_te_state.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright © 2014 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "intel_batchbuffer.h"
-
-static void
-upload_te_state(struct brw_context *brw)
-{
-   /* BRW_NEW_TESS_PROGRAMS */
-   bool active = brw->tess_eval_program;
-
-   const struct brw_tes_prog_data *tes_prog_data =
-  brw_tes_prog_data(brw->tes.base.prog_data);
-
-   if (active) {
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
-  OUT_BATCH((tes_prog_data->partitioning << GEN7_TE_PARTITIONING_SHIFT) |
-(tes_prog_data->output_topology << 
GEN7_TE_OUTPUT_TOPOLOGY_SHIFT) |
-(tes_prog_data->domain << GEN7_TE_DOMAIN_SHIFT) |
-GEN7_TE_ENABLE);
-  OUT_BATCH_F(63.0);
-  OUT_BATCH_F(64.0);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH_F(0);
-  OUT_BATCH_F(0);
-  ADVANCE_BATCH();
-   }
-}
-
-const struct brw_tracked_state gen7_te_state = {
-   .dirty = {
-  .mesa  = 0,
-  .brw   = BRW_NEW_BLORP |
-   BRW_NEW_CONTEXT |
-   BRW_NEW_TES_PROG_DATA |
-   BRW_NEW_TESS_PROGRAMS,
-   },
-   .emit = upload_te_state,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 1bdcea5..45b02a6 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2315,6 +2315,42 @@ static const struct brw_tracked_state genX(ds_state) = {
.emit = genX(upload_ds_state),
 };
 
+/* -- */
+
+static void
+upload_te_state(struct brw_context *brw)
+{
+   /* BRW_NEW_TESS_PROGRAMS */
+   bool active = brw->tess_eval_program;
+
+   const struct brw_tes_prog_data

[Mesa-dev] [PATCH v02 35/37] i965: Port gen6+ multisample state emitting code to genxml.

[Rafael Antognolli]

Emit 3DSTATE_MULTISAMPLE using brw_batch_emit.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.h|   9 +-
 src/mesa/drivers/dri/i965/brw_state.h  |   2 +-
 src/mesa/drivers/dri/i965/gen6_multisample_state.c |   6 +-
 src/mesa/drivers/dri/i965/gen8_multisample_state.c |  18 +--
 src/mesa/drivers/dri/i965/genX_state_upload.c  | 102 +-
 5 files changed, 101 insertions(+), 36 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 8bd8863..cef54b8 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1532,15 +1532,6 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
   int dstX0, int dstY0,
   int width, int height);
 
-/* gen6_multisample_state.c */
-unsigned
-gen6_determine_sample_mask(struct brw_context *brw);
-
-void
-gen6_emit_3dstate_multisample(struct brw_context *brw,
-  unsigned num_samples);
-void
-gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask);
 void
 gen6_get_sample_position(struct gl_context *ctx,
  struct gl_framebuffer *fb,
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index acb7334..2b5b1c4 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -109,7 +109,6 @@ extern const struct brw_tracked_state 
gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_binding_table;
-extern const struct brw_tracked_state gen6_multisample_state;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
 extern const struct brw_tracked_state gen6_sol_surface;
@@ -122,7 +121,6 @@ extern const struct brw_tracked_state 
gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_index_buffer;
-extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_vf_topology;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c 
b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index a59ffec..77c5fd6 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -122,7 +122,7 @@ gen6_set_sample_maps(struct gl_context *ctx)
 /**
  * 3DSTATE_MULTISAMPLE
  */
-void
+static void
 gen6_emit_3dstate_multisample(struct brw_context *brw,
   unsigned num_samples)
 {
@@ -160,7 +160,7 @@ gen6_emit_3dstate_multisample(struct brw_context *brw,
ADVANCE_BATCH();
 }
 
-unsigned
+static unsigned
 gen6_determine_sample_mask(struct brw_context *brw)
 {
struct gl_context *ctx = >ctx;
@@ -195,7 +195,7 @@ gen6_determine_sample_mask(struct brw_context *brw)
 /**
  * 3DSTATE_SAMPLE_MASK
  */
-void
+static void
 gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask)
 {
BEGIN_BATCH(2);
diff --git a/src/mesa/drivers/dri/i965/gen8_multisample_state.c 
b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
index e36d037..7a31a5d 100644
--- a/src/mesa/drivers/dri/i965/gen8_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
@@ -69,21 +69,3 @@ gen8_emit_3dstate_sample_pattern(struct brw_context *brw)
OUT_BATCH(brw_multisample_positions_1x_2x);
ADVANCE_BATCH();
 }
-
-
-static void
-upload_multisample_state(struct brw_context *brw)
-{
-   gen8_emit_3dstate_multisample(brw, brw->num_samples);
-   gen6_emit_3dstate_sample_mask(brw, gen6_determine_sample_mask(brw));
-}
-
-const struct brw_tracked_state gen8_multisample_state = {
-   .dirty = {
-  .mesa = _NEW_MULTISAMPLE,
-  .brw = BRW_NEW_BLORP |
- BRW_NEW_CONTEXT |
- BRW_NEW_NUM_SAMPLES,
-   },
-   .emit = upload_multisample_state
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index b7475dc..77c9efc 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -24,6 +24,7 @@
 #include 
 
 #include "common/gen_device_info.h"
+#include "common/gen_sample_positions.h"
 #include "genxml/gen_macros.h"
 
 #include "main/bufferobj.h"
@@ -36,6 +37,7 @@
 #include "brw_defines.h"
 #endif
 #include "brw_draw.h"
+#include "brw_multisample_state.h"
 #include "brw_state.h"
 #include "brw_wm.h"
 #include "brw_

[Mesa-dev] [PATCH v02 07/37] genxml: Make "Reorder Mode" fields consistent.

[Rafael Antognolli]

From: Kenneth Graunke 

Both GS and SOL have these fields.  Some were ReorderEnable = true,
some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.

Signed-off-by: Kenneth Graunke 
---
 src/intel/genxml/gen6.xml| 5 -
 src/intel/genxml/gen7.xml| 5 -
 src/intel/vulkan/genX_pipeline.c | 4 
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 8ead41f..14d643c 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1006,7 +1006,10 @@
 
 
 
-
+
+  
+  
+
 
 
 
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 440258a..a351486 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1157,7 +1157,10 @@
 
 
 
-
+
+  
+  
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index b00707f..2631ed0 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1300,11 +1300,7 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
   gs.ControlDataFormat   = gs_prog_data->control_data_format;
   gs.ControlDataHeaderSize   = 
gs_prog_data->control_data_header_size_hwords;
   gs.InstanceControl = MAX2(gs_prog_data->invocations, 1) - 1;
-#if GEN_GEN >= 8 || GEN_IS_HASWELL
   gs.ReorderMode = TRAILING;
-#else
-  gs.ReorderEnable   = true;
-#endif
 
 #if GEN_GEN >= 8
   gs.ExpectedVertexCount = gs_prog_data->vertices_in;
-- 
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[Mesa-dev] [PATCH v02 23/37] i965: Remove calculate_attr_overrides.

[Rafael Antognolli]

This function now lives inside genX_state_upload.c.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources |   1 +-
 src/mesa/drivers/dri/i965/brw_state.h  |   8 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c  | 265 +--
 3 files changed, 274 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_sf_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 81759ed..47680a7 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -85,7 +85,6 @@ i965_FILES = \
gen6_queryobj.c \
gen6_sampler_state.c \
gen6_scissor_state.c \
-   gen6_sf_state.c \
gen6_sol.c \
gen6_urb.c \
gen6_viewport_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index bc68c2c..3df975a 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -339,14 +339,6 @@ gen6_upload_wm_state(struct brw_context *brw,
  bool line_stipple_enable, bool polygon_stipple_enable,
  bool statistic_enable);
 
-/* gen6_sf_state.c */
-void
-calculate_attr_overrides(const struct brw_context *brw,
- uint16_t *attr_overrides,
- uint32_t *point_sprite_enables,
- uint32_t *urb_entry_read_length,
- uint32_t *urb_entry_read_offset);
-
 /* gen6_surface_state.c */
 void gen6_init_vtable_surface_functions(struct brw_context *brw);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
deleted file mode 100644
index 45b5769..000
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt <e...@anholt.net>
- *
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "brw_util.h"
-#include "compiler/nir/nir.h"
-#include "main/macros.h"
-#include "main/fbobject.h"
-#include "main/framebuffer.h"
-#include "intel_batchbuffer.h"
-
-/**
- * Determine the appropriate attribute override value to store into the
- * 3DSTATE_SF structure for a given fragment shader attribute.  The attribute
- * override value contains two pieces of information: the location of the
- * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
- * flag indicating whether to "swizzle" the attribute based on the direction
- * the triangle is facing.
- *
- * If an attribute is "swizzled", then the given VUE location is used for
- * front-facing triangles, and the VUE location that immediately follows is
- * used for back-facing triangles.  We use this to implement the mapping from
- * gl_FrontColor/gl_BackColor to gl_Color.
- *
- * urb_entry_read_offset is the offset into the VUE at which the SF unit is
- * being instructed to begin reading attribute data.  It can be set to a
- * nonzero value to prevent the SF unit from wasting time reading elements of
- * the VUE that are not needed by the fragment shader.  It is measured in
- * 256-bit increments.
- */
-static uint32_t
-get_attr_override(const struct brw_vue_map *vue_map, int urb_entry_read_offset,
-  int fs_attr, bool two_side_color, uint32_t *max_source_attr)
-{
-   /* Find the VUE slot for this attribute. */
-   int slot = vue_map->varying_to_slot[fs_attr];
-
-   /* Viewport and Layer are stored in the VUE header.  We need to override
-* them to zero if earlier stages didn't write them, as GL requi

[Mesa-dev] [PATCH v02 24/37] i965: Port gen7+ 3DSTATE_SOL to genxml.

[Rafael Antognolli]

Emit 3DSTATE_SOL on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.

v2:
   - Add helpers to assign struct brw_address (Kristian)

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 +-
 src/mesa/drivers/dri/i965/brw_state.h |   6 +-
 src/mesa/drivers/dri/i965/gen7_sol_state.c| 307 +
 src/mesa/drivers/dri/i965/gen8_sol_state.c|  95 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c | 358 ++-
 5 files changed, 355 insertions(+), 412 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_sol_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 47680a7..bfcf57c 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -111,7 +111,6 @@ i965_FILES = \
gen8_hs_state.c \
gen8_multisample_state.c \
gen8_ps_state.c \
-   gen8_sol_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
gen8_vs_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 3df975a..94f758b 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -135,7 +135,6 @@ extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
-extern const struct brw_tracked_state gen7_sol_state;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
@@ -299,11 +298,6 @@ void gen8_upload_ps_state(struct brw_context *brw,
 void gen8_upload_ps_extra(struct brw_context *brw,
   const struct brw_wm_prog_data *prog_data);
 
-/* gen7_sol_state.c */
-void gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
-  const struct brw_vue_map *vue_map);
-void gen8_upload_3dstate_so_buffers(struct brw_context *brw);
-
 /* gen8_surface_state.c */
 
 void gen8_init_vtable_surface_functions(struct brw_context *brw);
diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c 
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index f1bd19c..f54b370 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -35,313 +35,6 @@
 #include "intel_buffer_objects.h"
 #include "main/transformfeedback.h"
 
-static void
-upload_3dstate_so_buffers(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_TRANSFORM_FEEDBACK */
-   struct gl_transform_feedback_object *xfb_obj =
-  ctx->TransformFeedback.CurrentObject;
-   const struct gl_transform_feedback_info *linked_xfb_info =
-  xfb_obj->program->sh.LinkedTransformFeedback;
-   int i;
-
-   /* Set up the up to 4 output buffers.  These are the ranges defined in the
-* gl_transform_feedback_object.
-*/
-   for (i = 0; i < 4; i++) {
-  struct intel_buffer_object *bufferobj =
-intel_buffer_object(xfb_obj->Buffers[i]);
-  struct brw_bo *bo;
-  uint32_t start, end;
-  uint32_t stride;
-
-  if (!xfb_obj->Buffers[i]) {
-/* The pitch of 0 in this command indicates that the buffer is
- * unbound and won't be written to.
- */
-BEGIN_BATCH(4);
-OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
-OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT));
-OUT_BATCH(0);
-OUT_BATCH(0);
-ADVANCE_BATCH();
-
-continue;
-  }
-
-  stride = linked_xfb_info->Buffers[i].Stride * 4;
-
-  start = xfb_obj->Offset[i];
-  assert(start % 4 == 0);
-  end = ALIGN(start + xfb_obj->Size[i], 4);
-  bo = intel_bufferobj_buffer(brw, bufferobj, start, end - start);
-  assert(end <= bo->size);
-
-  BEGIN_BATCH(4);
-  OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
-  OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) | stride);
-  OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start);
-  OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end);
-  ADVANCE_BATCH();
-   }
-}
-
-/**
- * Outputs the 3DSTATE_SO_DECL_LIST command.
- *
- * The data output is a series of 64-bit entries containing a SO_DECL per
- * stream.  We only have one stream of rendering coming out of the GS unit, so
- * we only emit stream 0 (low 16 bits) SO_DECLs.
- */
-void
-gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
- const struct brw_vue_map *vue_map)
-{
-   struct gl_context *ctx = >ctx;
-   /* BRW_NEW_TRANSFORM_FEEDBACK */
-   struct gl_transform_feedback_object *xfb_obj =
-  ctx->TransformFeedback.

Re: [Mesa-dev] [PATCH 20/35] genxml: Make "Reorder Mode" fields consistent.

[Rafael Antognolli]

On Mon, Apr 24, 2017 at 03:03:56PM -0700, Kenneth Graunke wrote:
> On Wednesday, April 19, 2017 4:56:13 PM PDT Rafael Antognolli wrote:
> > From: Kenneth Graunke <kenn...@whitecape.org>
> > 
> > Both GS and SOL have these fields.  Some were ReorderEnable = true,
> > some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.
> > 
> > Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
> > ---
> >  src/intel/genxml/gen6.xml| 5 -
> >  src/intel/genxml/gen7.xml| 5 -
> >  src/intel/vulkan/genX_pipeline.c | 4 
> >  3 files changed, 8 insertions(+), 6 deletions(-)
> 
> I'm a little conflicted about this...I had forgotten that the Gen6-7 GS
> doesn't actually do proper "trailing" reordering.  It just...reorders
> them...differently.  So "Reorder Enable" feels kind of appropriate.
> 
> That said, it feels stupid to have ifdefs to set the same exact bit,
> and we call it REORDER_TRAILING in the existing gen7_gs_state.c code.
> We just have a comment pointing out that it's kinda broken.
> 
> So, I suppose it's fine.  I can't really give an R-b for my own patch
> though :)

Heh, you have mine at least:

Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
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Re: [Mesa-dev] [PATCH 22/35] i965: Port gen6+ 3DSTATE_VS to genxml.

[Rafael Antognolli]

On Thu, Apr 20, 2017 at 09:55:56AM -0700, Kristian H. Kristensen wrote:
> Rafael Antognolli <rafael.antogno...@intel.com> writes:
> 
> > Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
> > structs from genxml.
> >
> > Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
> > ---
> >  src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
> >  src/mesa/drivers/dri/i965/brw_state.h |   3 +-
> >  src/mesa/drivers/dri/i965/gen6_vs_state.c | 113 +---
> >  src/mesa/drivers/dri/i965/gen7_vs_state.c |  87 +---
> >  src/mesa/drivers/dri/i965/gen8_vs_state.c |  96 +
> >  src/mesa/drivers/dri/i965/genX_state_upload.c | 110 +-
> >  6 files changed, 107 insertions(+), 304 deletions(-)
> >  delete mode 100644 src/mesa/drivers/dri/i965/gen7_vs_state.c
> >  delete mode 100644 src/mesa/drivers/dri/i965/gen8_vs_state.c
> >
> > diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
> > b/src/mesa/drivers/dri/i965/Makefile.sources
> > index 0f893d6..eec63f8 100644
> > --- a/src/mesa/drivers/dri/i965/Makefile.sources
> > +++ b/src/mesa/drivers/dri/i965/Makefile.sources
> > @@ -102,7 +102,6 @@ i965_FILES = \
> > gen7_te_state.c \
> > gen7_urb.c \
> > gen7_viewport_state.c \
> > -   gen7_vs_state.c \
> > gen7_wm_surface_state.c \
> > gen8_blend_state.c \
> > gen8_depth_state.c \
> > @@ -113,7 +112,6 @@ i965_FILES = \
> > gen8_multisample_state.c \
> > gen8_surface_state.c \
> > gen8_viewport_state.c \
> > -   gen8_vs_state.c \
> > hsw_queryobj.c \
> > hsw_sol.c \
> > intel_batchbuffer.c \
> > diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
> > b/src/mesa/drivers/dri/i965/brw_state.h
> > index 71ec9fb..306bfc5 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state.h
> > +++ b/src/mesa/drivers/dri/i965/brw_state.h
> > @@ -123,7 +123,6 @@ extern const struct brw_tracked_state gen6_sf_vp;
> >  extern const struct brw_tracked_state gen6_urb;
> >  extern const struct brw_tracked_state gen6_viewport_state;
> >  extern const struct brw_tracked_state gen6_vs_push_constants;
> > -extern const struct brw_tracked_state gen6_vs_state;
> >  extern const struct brw_tracked_state gen6_wm_push_constants;
> >  extern const struct brw_tracked_state gen7_depthbuffer;
> >  extern const struct brw_tracked_state gen7_ds_state;
> > @@ -136,7 +135,6 @@ extern const struct brw_tracked_state 
> > gen7_sf_clip_viewport;
> >  extern const struct brw_tracked_state gen7_te_state;
> >  extern const struct brw_tracked_state gen7_tes_push_constants;
> >  extern const struct brw_tracked_state gen7_urb;
> > -extern const struct brw_tracked_state gen7_vs_state;
> >  extern const struct brw_tracked_state haswell_cut_index;
> >  extern const struct brw_tracked_state gen8_blend_state;
> >  extern const struct brw_tracked_state gen8_ds_state;
> > @@ -149,7 +147,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
> >  extern const struct brw_tracked_state gen8_sf_clip_viewport;
> >  extern const struct brw_tracked_state gen8_vertices;
> >  extern const struct brw_tracked_state gen8_vf_topology;
> > -extern const struct brw_tracked_state gen8_vs_state;
> >  extern const struct brw_tracked_state brw_cs_work_groups_surface;
> >  
> >  static inline bool
> > diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
> > b/src/mesa/drivers/dri/i965/gen6_vs_state.c
> > index 17b8118..b2d2306 100644
> > --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
> > @@ -68,116 +68,3 @@ const struct brw_tracked_state gen6_vs_push_constants = 
> > {
> > },
> > .emit = gen6_upload_vs_push_constants,
> >  };
> > -
> > -static void
> > -upload_vs_state(struct brw_context *brw)
> > -{
> > -   const struct gen_device_info *devinfo = >screen->devinfo;
> > -   const struct brw_stage_state *stage_state = >vs.base;
> > -   const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
> > -   const struct brw_vue_prog_data *vue_prog_data =
> > -  brw_vue_prog_data(stage_state->prog_data);
> > -   uint32_t floating_point_mode = 0;
> > -
> > -   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
> > -* 3DSTATE_VS, Dword 5.0 "VS Function Enable":
> > -*
> > -*   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
> > -*   comm

[Mesa-dev] [PATCH 32/35] i965: Port gen6+ multisample state emitting code to genxml.

[Rafael Antognolli]

Emit 3DSTATE_MULTISAMPLE using brw_batch_emit.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_context.h|   9 +-
 src/mesa/drivers/dri/i965/brw_state.h  |   2 +-
 src/mesa/drivers/dri/i965/gen6_multisample_state.c |   6 +-
 src/mesa/drivers/dri/i965/gen8_multisample_state.c |  18 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c  | 100 +-
 5 files changed, 99 insertions(+), 36 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 7b354c4..192ea21 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1549,15 +1549,6 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
   int dstX0, int dstY0,
   int width, int height);
 
-/* gen6_multisample_state.c */
-unsigned
-gen6_determine_sample_mask(struct brw_context *brw);
-
-void
-gen6_emit_3dstate_multisample(struct brw_context *brw,
-  unsigned num_samples);
-void
-gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask);
 void
 gen6_get_sample_position(struct gl_context *ctx,
  struct gl_framebuffer *fb,
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 0ed4dc1..3968916 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -110,7 +110,6 @@ extern const struct brw_tracked_state 
gen7_cs_push_constants;
 extern const struct brw_tracked_state gen6_binding_table_pointers;
 extern const struct brw_tracked_state gen6_color_calc_state;
 extern const struct brw_tracked_state gen6_gs_binding_table;
-extern const struct brw_tracked_state gen6_multisample_state;
 extern const struct brw_tracked_state gen6_renderbuffer_surfaces;
 extern const struct brw_tracked_state gen6_sampler_state;
 extern const struct brw_tracked_state gen6_sol_surface;
@@ -123,7 +122,6 @@ extern const struct brw_tracked_state 
gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_urb;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_index_buffer;
-extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_pma_fix;
 extern const struct brw_tracked_state gen8_vf_topology;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c 
b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index a59ffec..77c5fd6 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -122,7 +122,7 @@ gen6_set_sample_maps(struct gl_context *ctx)
 /**
  * 3DSTATE_MULTISAMPLE
  */
-void
+static void
 gen6_emit_3dstate_multisample(struct brw_context *brw,
   unsigned num_samples)
 {
@@ -160,7 +160,7 @@ gen6_emit_3dstate_multisample(struct brw_context *brw,
ADVANCE_BATCH();
 }
 
-unsigned
+static unsigned
 gen6_determine_sample_mask(struct brw_context *brw)
 {
struct gl_context *ctx = >ctx;
@@ -195,7 +195,7 @@ gen6_determine_sample_mask(struct brw_context *brw)
 /**
  * 3DSTATE_SAMPLE_MASK
  */
-void
+static void
 gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask)
 {
BEGIN_BATCH(2);
diff --git a/src/mesa/drivers/dri/i965/gen8_multisample_state.c 
b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
index e36d037..7a31a5d 100644
--- a/src/mesa/drivers/dri/i965/gen8_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
@@ -69,21 +69,3 @@ gen8_emit_3dstate_sample_pattern(struct brw_context *brw)
OUT_BATCH(brw_multisample_positions_1x_2x);
ADVANCE_BATCH();
 }
-
-
-static void
-upload_multisample_state(struct brw_context *brw)
-{
-   gen8_emit_3dstate_multisample(brw, brw->num_samples);
-   gen6_emit_3dstate_sample_mask(brw, gen6_determine_sample_mask(brw));
-}
-
-const struct brw_tracked_state gen8_multisample_state = {
-   .dirty = {
-  .mesa = _NEW_MULTISAMPLE,
-  .brw = BRW_NEW_BLORP |
- BRW_NEW_CONTEXT |
- BRW_NEW_NUM_SAMPLES,
-   },
-   .emit = upload_multisample_state
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index d314fdc..be06227 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -24,6 +24,7 @@
 #include 
 
 #include "common/gen_device_info.h"
+#include "common/gen_sample_positions.h"
 #include "genxml/gen_macros.h"
 /* #include "vbo/vbo.h" */
 
@@ -37,6 +38,7 @@
 #include "brw_defines.h"
 #endif
 #include "brw_draw.h"
+#include "brw_multisample_state.h"
 #include "brw_state.h"
 #include "brw_wm.h&qu

[Mesa-dev] [PATCH 35/35] i965: Port gen6+ state emitting code to genxml.

[Rafael Antognolli]

On this patch, we port:
   - brw_polygon_stipple
   - brw_polygon_stipple_offset
   - brw_line_stipple
   - brw_drawing_rect

The original code is still left behind because it is being used by
gen4-5.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/Makefile.sources  |   1 +-
 src/mesa/drivers/dri/i965/brw_state.h   |   1 +-
 src/mesa/drivers/dri/i965/gen6_viewport_state.c |  60 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c   | 187 +++--
 4 files changed, 174 insertions(+), 75 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen6_viewport_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 2323fed..d4b3584 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -88,7 +88,6 @@ i965_FILES = \
gen6_scissor_state.c \
gen6_sol.c \
gen6_urb.c \
-   gen6_viewport_state.c \
gen7_cs_state.c \
gen7_l3_state.c \
gen7_misc_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 8260856..55448b5 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -114,7 +114,6 @@ extern const struct brw_tracked_state gen6_sampler_state;
 extern const struct brw_tracked_state gen6_sol_surface;
 extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
-extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_l3_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c 
b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
deleted file mode 100644
index e3968b1..000
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright © 2009 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *Eric Anholt <e...@anholt.net>
- *
- */
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-#include "intel_batchbuffer.h"
-#include "main/fbobject.h"
-#include "main/framebuffer.h"
-#include "main/viewport.h"
-
-static void upload_viewport_state_pointers(struct brw_context *brw)
-{
-   BEGIN_BATCH(4);
-   OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
-GEN6_CC_VIEWPORT_MODIFY |
-GEN6_SF_VIEWPORT_MODIFY |
-GEN6_CLIP_VIEWPORT_MODIFY);
-   OUT_BATCH(brw->clip.vp_offset);
-   OUT_BATCH(brw->sf.vp_offset);
-   OUT_BATCH(brw->cc.vp_offset);
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen6_viewport_state = {
-   .dirty = {
-  .mesa = 0,
-  .brw = BRW_NEW_BATCH |
- BRW_NEW_BLORP |
- BRW_NEW_CC_VP |
- BRW_NEW_CLIP_VP |
- BRW_NEW_SF_VP |
- BRW_NEW_STATE_BASE_ADDRESS,
-   },
-   .emit = upload_viewport_state_pointers,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index bfe8a7b..47b46a7 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -3624,6 +3624,167 @@ static const struct brw_tracked_state 
genX(color_calc_state) = {
 
 /* -- */
 
+/**
+ * Polygon stipple packet
+ */
+static void
+genX(upload_polygon_stipple)(struct brw_context *brw)
+{
+   struct gl_context *ctx = >ctx;
+   GLuint i;
+
+   /* _NEW_POLYGON */
+   if (!ctx->Polygon.StippleFlag)
+  return;
+
+   brw_batch_emit(brw, GENX(3D

[Mesa-dev] [PATCH 21/35] genxml: 3DSTATE_VS rename Function Enable to Enable.

[Rafael Antognolli]

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/blorp/blorp_genX_exec.h | 2 +-
 src/intel/genxml/gen6.xml | 2 +-
 src/intel/genxml/gen7.xml | 2 +-
 src/intel/genxml/gen75.xml| 2 +-
 src/intel/genxml/gen8.xml | 2 +-
 src/intel/genxml/gen9.xml | 2 +-
 src/intel/vulkan/genX_pipeline.c  | 2 +-
 7 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 0bde2d2..bc829d0 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -432,7 +432,7 @@ blorp_emit_vs_config(struct blorp_batch *batch,
 
blorp_emit(batch, GENX(3DSTATE_VS), vs) {
   if (vs_prog_data) {
- vs.FunctionEnable = true;
+ vs.Enable = true;
 
  vs.KernelStartPointer = params->vs_prog_kernel;
 
diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 14d643c..a12e22c 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1391,7 +1391,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index a351486..6af1cbe 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1863,7 +1863,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 594e539..e2d79b8 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2128,7 +2128,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index f4bde85..84ad3a8 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2289,7 +2289,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 0e98139..ce2008f 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2517,7 +2517,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 2631ed0..74d6f9a 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1132,7 +1132,7 @@ emit_3dstate_vs(struct anv_pipeline *pipeline)
assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
 
anv_batch_emit(>batch, GENX(3DSTATE_VS), vs) {
-  vs.FunctionEnable   = true;
+  vs.Enable   = true;
   vs.StatisticsEnable = true;
   vs.KernelStartPointer   = vs_bin->kernel.offset;
 #if GEN_GEN >= 8
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH 10/35] i965: Port Gen8+ 3DSTATE_RASTER state to genxml.

[Rafael Antognolli]

Emits 3DSTATE_RASTER from genX_state_upload.c using pack structs from
genxml.

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/mesa/drivers/dri/i965/brw_state.h |   1 +-
 src/mesa/drivers/dri/i965/gen8_sf_state.c | 125 +---
 src/mesa/drivers/dri/i965/genX_state_upload.c | 125 ++-
 3 files changed, 124 insertions(+), 127 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 0cfe470..fc4325f 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -156,7 +156,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
 extern const struct brw_tracked_state gen8_wm_state;
-extern const struct brw_tracked_state gen8_raster_state;
 extern const struct brw_tracked_state gen8_sbe_state;
 extern const struct brw_tracked_state gen8_sf_state;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c 
b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index 41e94fb..d47adcd 100644
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -224,128 +224,3 @@ const struct brw_tracked_state gen8_sf_state = {
},
.emit = upload_sf,
 };
-
-static void
-upload_raster(struct brw_context *brw)
-{
-   struct gl_context *ctx = >ctx;
-   uint32_t dw1 = 0;
-
-   /* _NEW_BUFFERS */
-   bool render_to_fbo = _mesa_is_user_fbo(brw->ctx.DrawBuffer);
-
-   /* _NEW_POLYGON */
-   if (ctx->Polygon._FrontBit == render_to_fbo)
-  dw1 |= GEN8_RASTER_FRONT_WINDING_CCW;
-
-   if (ctx->Polygon.CullFlag) {
-  switch (ctx->Polygon.CullFaceMode) {
-  case GL_FRONT:
- dw1 |= GEN8_RASTER_CULL_FRONT;
- break;
-  case GL_BACK:
- dw1 |= GEN8_RASTER_CULL_BACK;
- break;
-  case GL_FRONT_AND_BACK:
- dw1 |= GEN8_RASTER_CULL_BOTH;
- break;
-  default:
- unreachable("not reached");
-  }
-   } else {
-  dw1 |= GEN8_RASTER_CULL_NONE;
-   }
-
-   /* _NEW_POINT */
-   if (ctx->Point.SmoothFlag)
-  dw1 |= GEN8_RASTER_SMOOTH_POINT_ENABLE;
-
-   if (_mesa_is_multisample_enabled(ctx))
-  dw1 |= GEN8_RASTER_API_MULTISAMPLE_ENABLE;
-
-   if (ctx->Polygon.OffsetFill)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
-
-   if (ctx->Polygon.OffsetLine)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
-
-   if (ctx->Polygon.OffsetPoint)
-  dw1 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
-
-   switch (ctx->Polygon.FrontMode) {
-   case GL_FILL:
-  dw1 |= GEN6_SF_FRONT_SOLID;
-  break;
-   case GL_LINE:
-  dw1 |= GEN6_SF_FRONT_WIREFRAME;
-  break;
-   case GL_POINT:
-  dw1 |= GEN6_SF_FRONT_POINT;
-  break;
-
-   default:
-  unreachable("not reached");
-   }
-
-   switch (ctx->Polygon.BackMode) {
-   case GL_FILL:
-  dw1 |= GEN6_SF_BACK_SOLID;
-  break;
-   case GL_LINE:
-  dw1 |= GEN6_SF_BACK_WIREFRAME;
-  break;
-   case GL_POINT:
-  dw1 |= GEN6_SF_BACK_POINT;
-  break;
-   default:
-  unreachable("not reached");
-   }
-
-   /* _NEW_LINE */
-   if (ctx->Line.SmoothFlag)
-  dw1 |= GEN8_RASTER_LINE_AA_ENABLE;
-
-   /* _NEW_SCISSOR */
-   if (ctx->Scissor.EnableFlags)
-  dw1 |= GEN8_RASTER_SCISSOR_ENABLE;
-
-   /* _NEW_TRANSFORM */
-   if (!ctx->Transform.DepthClamp) {
-  if (brw->gen >= 9) {
- dw1 |= GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE |
-GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE;
-  } else {
- dw1 |= GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE;
-  }
-   }
-
-   /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
-   if (ctx->IntelConservativeRasterization) {
-  if (brw->gen >= 9)
- dw1 |= GEN9_RASTER_CONSERVATIVE_RASTERIZATION_ENABLE;
-   }
-
-   BEGIN_BATCH(5);
-   OUT_BATCH(_3DSTATE_RASTER << 16 | (5 - 2));
-   OUT_BATCH(dw1);
-   OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
-   OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
-   OUT_BATCH_F(ctx->Polygon.OffsetClamp); /* global depth offset clamp */
-   ADVANCE_BATCH();
-}
-
-const struct brw_tracked_state gen8_raster_state = {
-   .dirty = {
-  .mesa  = _NEW_BUFFERS |
-   _NEW_LINE |
-   _NEW_MULTISAMPLE |
-   _NEW_POINT |
-   _NEW_POLYGON |
-   _NEW_SCISSOR |
-   _NEW_TRANSFORM,
-  .brw   = BRW_NEW_BLORP |
-   BRW_NEW_CONTEXT |
-   BRW_NEW_CONSERVATIVE_RASTERIZATION,
-   },
-   .emit = upload_raster,
-};
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 72cada6..c10fe71 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/sr

[Mesa-dev] [PATCH 24/35] genxml: Rename "Function Enable" to "Enable".

[Rafael Antognolli]

Rename that field name on genxml for:
   - 3DSTATE_GS - gen6+
   - 3DSTATE_DS - gen7+
   - 3DSTATE_HS - gen7+

Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
 src/intel/genxml/gen6.xml| 2 +-
 src/intel/genxml/gen7.xml| 6 +++---
 src/intel/genxml/gen75.xml   | 6 +++---
 src/intel/genxml/gen8.xml| 6 +++---
 src/intel/genxml/gen9.xml| 6 +++---
 src/intel/vulkan/genX_pipeline.c | 6 +++---
 6 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 2173dbf..2cb9419 100644
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1014,7 +1014,7 @@
 
 
 
-
+
   
 
   
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 6af1cbe..b4407d4 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -1101,7 +1101,7 @@
 
 
 
-
+
   
 
   
@@ -1162,7 +1162,7 @@
   
 
 
-
+
 
   
 
@@ -1199,7 +1199,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index e2d79b8..89b2ff0 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -1229,7 +1229,7 @@
 
 
 
-
+
   
 
   
@@ -1377,7 +1377,7 @@
   
 
 
-
+
 
   
   
@@ -1421,7 +1421,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 84ad3a8..0b5aa4f 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -1287,7 +1287,7 @@
 
 
 
-
+
 
 
 
@@ -1443,7 +1443,7 @@
   
 
 
-
+
 
   
   
@@ -1492,7 +1492,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index ce2008f..dac5bff 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -1349,7 +1349,7 @@
 
 
 
-
+
 
 
 
@@ -1548,7 +1548,7 @@
   
 
 
-
+
 
   
   
@@ -1598,7 +1598,7 @@
 
 
 
-
+
 
 
 
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 74d6f9a..2b38c34 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -1192,7 +1192,7 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
 
anv_batch_emit(>batch, GENX(3DSTATE_HS), hs) {
-  hs.FunctionEnable = true;
+  hs.Enable = true;
   hs.StatisticsEnable = true;
   hs.KernelStartPointer = tcs_bin->kernel.offset;
 
@@ -1222,7 +1222,7 @@ emit_3dstate_hs_te_ds(struct anv_pipeline *pipeline)
}
 
anv_batch_emit(>batch, GENX(3DSTATE_DS), ds) {
-  ds.FunctionEnable = true;
+  ds.Enable = true;
   ds.StatisticsEnable = true;
   ds.KernelStartPointer = tes_bin->kernel.offset;
 
@@ -1275,7 +1275,7 @@ emit_3dstate_gs(struct anv_pipeline *pipeline)
const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
 
anv_batch_emit(>batch, GENX(3DSTATE_GS), gs) {
-  gs.FunctionEnable  = true;
+  gs.Enable  = true;
   gs.StatisticsEnable= true;
   gs.KernelStartPointer  = gs_bin->kernel.offset;
   gs.DispatchMode= gs_prog_data->base.dispatch_mode;
-- 
git-series 0.9.1
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