Hi
I think this email is sent from a script so just wanted to point out:
not available -> now available
If it's just a bog standard typo in a manually written email - just ignore
me
Mike
On Mon, 1 May 2017 at 13:24 Emil Velikov wrote:
> Hello all,
>
> The third release candidate for Mesa 17.1.0 is not available.
>
>
> Andres Gomez (2):
> travis: replace Trusty-based LLVM toolchain apt-get with apt addon
> travis: add the possibility of using the txc-dxtn library
>
> Emil Velikov (15):
> travis: explicitly LD_LIBRARY_PATH the local libraries
> travis: enable apt cache
> travis: automatically manage ccache caching
> travis: remove unused -dev packages
> travis: rework "if test" blocks in the script section
> travis: split out matrix from env
> travis: add separate "scons" and "scons llvm" targets
> travis: add "scons swr" to the build matrix
> travis: add "make swr" to the build matrix
> travis: split the make target to three separate ones
> travis: model scons check target like the make one
> travis: add Gallium state-tracker targets
> travis: enable wayland support
> travis: bump MAKEFLAGS to -j4
> Update version to 17.1.0-rc3
>
> Francisco Jerez (2):
> intel/fs: Use regs_written() in spilling cost heuristic for
> improved accuracy.
> intel/fs: Take into account amount of data read in spilling cost
> heuristic.
>
> Ilia Mirkin (1):
> gallium/targets: fix bool setting on BE architectures
>
> Jason Ekstrand (2):
> anv: Don't place scratch buffers above the 32-bit boundary
> anv/cmd_buffer: Use the device allocator for QueueSubmit
>
> Kenneth Graunke (1):
> i965/vec4: Avoid reswizzling MACH instructions in
> opt_register_coalesce().
>
> Marek Olšák (7):
> radeonsi/gfx9: fix texture buffer objects and image buffers with
> IDXEN==0
> radeonsi/gfx9: fix most things wrong with shader images
> radeonsi/gfx9: fix 1D array shader images
> radeonsi/gfx9: add a workaround for viewing a slice of 3D as a 2D
> image
> radeonsi/gfx9: set MAX_PRIMGRP_IN_WAVE in the correct register
> radeonsi/gfx9: don't set deprecated field PARTIAL_ES_WAVE_ON
> radeonsi: adjust ESGS ring buffer size computation on VI
>
> Nicolai Hähnle (1):
> st/mesa: don't cast the incomplete framebufer to st_framebuffer
>
> Timothy Arceri (3):
> disk_cache: reduce default cache size to 5% of filesystem
> disk_cache: use block size rather than file size
> util/disk_cache: remove percentage based max cache limit
>
> git tag: mesa-17.1.0-rc3
>
> https://mesa.freedesktop.org/archive/mesa-17.1.0-rc3.tar.gz
> MD5: d84e7611ea97c74b6e5c0e8c957ca133 mesa-17.1.0-rc3.tar.gz
> SHA1: f5821fea3c614d643eb82880596936d0c9df34d7 mesa-17.1.0-rc3.tar.gz
> SHA256: 8d162d72b85457b6614865c6c1dab4670300c88904266580330bb1ce81d6023f
> mesa-17.1.0-rc3.tar.gz
> SHA512:
> 704f20fd47672f1e4c9c7e822b7c6e575cbedddb3a813b3f1c27d02e1531a4ac7a28142c5ef0c98dbe6ccd1c3a8062f04fccb360eb82507d89c6d8dd8c33f433
> mesa-17.1.0-rc3.tar.gz
> PGP: https://mesa.freedesktop.org/archive/mesa-17.1.0-rc3.tar.gz.sig
>
> https://mesa.freedesktop.org/archive/mesa-17.1.0-rc3.tar.xz
> MD5: 0630035d846918e5b291b2a893d066b2 mesa-17.1.0-rc3.tar.xz
> SHA1: b8d9bcb63462167de9ee83f2093552fa49679c90 mesa-17.1.0-rc3.tar.xz
> SHA256: 52831657b7ac64b3dd4899f2f6d995c062fc77ac436017470daddfc1ebc0e85e
> mesa-17.1.0-rc3.tar.xz
> SHA512:
> b5f5d2d517fb92fa1d31a44b88cf7c00fbe186747482c2286e97a352c016719c6454a79f777df6a8540997df464820cb1a8c2e3054a26517bb062b25e1a2d114
> mesa-17.1.0-rc3.tar.xz
> PGP: https://mesa.freedesktop.org/archive/mesa-17.1.0-rc3.tar.xz.sig
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