Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9
Quoting Samuel Pitoiset (2018-07-13 03:30:01)
>
>
> On 07/13/2018 12:05 PM, Samuel Pitoiset wrote:
> >
> >
> > On 07/12/2018 09:43 PM, Dylan Baker wrote:
> >> Quoting Samuel Pitoiset (2018-07-11 02:55:55)
> >>> A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
> >>> counters) must immediately precede every timestamp event to
> >>> prevent a GPU hang on GFX9.
> >>>
> >>> Signed-off-by: Samuel Pitoiset
> >>> Cc: 18.1
> >>> ---
> >>> src/amd/vulkan/radv_cmd_buffer.c | 15 +--
> >>> src/amd/vulkan/radv_device.c | 4 ++--
> >>> src/amd/vulkan/radv_private.h | 7 +--
> >>> src/amd/vulkan/radv_query.c | 9 ++---
> >>> src/amd/vulkan/si_cmd_buffer.c | 26 +-
> >>> 5 files changed, 47 insertions(+), 14 deletions(-)
> >>>
> >>> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> >>> b/src/amd/vulkan/radv_cmd_buffer.c
> >>> index 9da42fe03e..325e1993f8 100644
> >>> --- a/src/amd/vulkan/radv_cmd_buffer.c
> >>> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> >>> @@ -319,11 +319,21 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer
> >>> *cmd_buffer)
> >>> }
> >>> if (cmd_buffer->device->physical_device->rad_info.chip_class
> >>> >= GFX9) {
> >>> + unsigned num_db =
> >>> cmd_buffer->device->physical_device->rad_info.num_render_backends;
> >>> + unsigned eop_bug_offset;
> >>> void *fence_ptr;
> >>> +
> >>> radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
> >>>
> >>> _buffer->gfx9_fence_offset,
> >>> _ptr);
> >>> cmd_buffer->gfx9_fence_bo =
> >>> cmd_buffer->upload.upload_bo;
> >>> +
> >>> + /* Allocate a buffer for the EOP bug on GFX9. */
> >>> + radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
> >>> + _bug_offset,
> >>> _ptr);
> >>> + cmd_buffer->gfx9_eop_bug_va =
> >>> +
> >>> radv_buffer_get_va(cmd_buffer->upload.upload_bo);
> >>> + cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
> >>> }
> >>> cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
> >>> @@ -473,7 +483,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer
> >>> *cmd_buffer,
> >>>
> >>> cmd_buffer->device->physical_device->rad_info.chip_class,
> >>> ptr, va,
> >>>
> >>> radv_cmd_buffer_uses_mec(cmd_buffer),
> >>> - flags);
> >>> + flags,
> >>> cmd_buffer->gfx9_eop_bug_va);
> >>> }
> >>> if (unlikely(cmd_buffer->device->trace_bo))
> >>> @@ -4318,7 +4328,8 @@ static void write_event(struct radv_cmd_buffer
> >>> *cmd_buffer,
> >>>
> >>> cmd_buffer->device->physical_device->rad_info.chip_class,
> >>>
> >>> radv_cmd_buffer_uses_mec(cmd_buffer),
> >>>
> >>> V_028A90_BOTTOM_OF_PIPE_TS, 0,
> >>> - EOP_DATA_SEL_VALUE_32BIT,
> >>> va, 2, value);
> >>> + EOP_DATA_SEL_VALUE_32BIT,
> >>> va, 2, value,
> >>> + cmd_buffer->gfx9_eop_bug_va);
> >>> }
> >>> assert(cmd_buffer->cs->cdw <= cdw_max);
> >>> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> >>> index 73c48cef1f..1c0a50c82f 100644
> >>> --- a/src/amd/vulkan/radv_device.c
> >>> +++ b/src/amd/vulkan/radv_device.c
> >>> @@ -2240,7 +2240,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
> >>>
> >>> RADV_CMD_FLAG_INV_SMEM_L1 |
> >>>
> >>> RADV_CMD_FLAG_INV_VMEM_L1 |
> >>>
> >>> RADV_CMD_FLAG_INV_GLOBAL_L2 |
> >>> -
> >>> RADV_CMD_FLAG_START_PIPELINE_STATS);
> >>> +
> >>> RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
> >>> } else if (i == 1) {
> >>> si_cs_emit_cache_flush(cs,
> >>>
> >>> queue->device->physical_device->rad_info.chip_class,
> >>> @@ -2251,7 +2251,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
> >>>
> >>> RADV_CMD_FLAG_INV_SMEM_L1 |
> >>>
> >>> RADV_CMD_FLAG_INV_VMEM_L1 |
> >>>
> >>> RADV_CMD_FLAG_INV_GLOBAL_L2 |
> >>> -
> >>> RADV_CMD_FLAG_START_PIPELINE_STATS);
> >>> +
Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9
On 07/13/2018 12:05 PM, Samuel Pitoiset wrote:
On 07/12/2018 09:43 PM, Dylan Baker wrote:
Quoting Samuel Pitoiset (2018-07-11 02:55:55)
A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
counters) must immediately precede every timestamp event to
prevent a GPU hang on GFX9.
Signed-off-by: Samuel Pitoiset
Cc: 18.1
---
src/amd/vulkan/radv_cmd_buffer.c | 15 +--
src/amd/vulkan/radv_device.c | 4 ++--
src/amd/vulkan/radv_private.h | 7 +--
src/amd/vulkan/radv_query.c | 9 ++---
src/amd/vulkan/si_cmd_buffer.c | 26 +-
5 files changed, 47 insertions(+), 14 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c
b/src/amd/vulkan/radv_cmd_buffer.c
index 9da42fe03e..325e1993f8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -319,11 +319,21 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer
*cmd_buffer)
}
if (cmd_buffer->device->physical_device->rad_info.chip_class
>= GFX9) {
+ unsigned num_db =
cmd_buffer->device->physical_device->rad_info.num_render_backends;
+ unsigned eop_bug_offset;
void *fence_ptr;
+
radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
_buffer->gfx9_fence_offset,
_ptr);
cmd_buffer->gfx9_fence_bo =
cmd_buffer->upload.upload_bo;
+
+ /* Allocate a buffer for the EOP bug on GFX9. */
+ radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
+ _bug_offset,
_ptr);
+ cmd_buffer->gfx9_eop_bug_va =
+
radv_buffer_get_va(cmd_buffer->upload.upload_bo);
+ cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
}
cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
@@ -473,7 +483,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer,
cmd_buffer->device->physical_device->rad_info.chip_class,
ptr, va,
radv_cmd_buffer_uses_mec(cmd_buffer),
- flags);
+ flags,
cmd_buffer->gfx9_eop_bug_va);
}
if (unlikely(cmd_buffer->device->trace_bo))
@@ -4318,7 +4328,8 @@ static void write_event(struct radv_cmd_buffer
*cmd_buffer,
cmd_buffer->device->physical_device->rad_info.chip_class,
radv_cmd_buffer_uses_mec(cmd_buffer),
V_028A90_BOTTOM_OF_PIPE_TS, 0,
- EOP_DATA_SEL_VALUE_32BIT,
va, 2, value);
+ EOP_DATA_SEL_VALUE_32BIT,
va, 2, value,
+ cmd_buffer->gfx9_eop_bug_va);
}
assert(cmd_buffer->cs->cdw <= cdw_max);
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 73c48cef1f..1c0a50c82f 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2240,7 +2240,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
RADV_CMD_FLAG_INV_SMEM_L1 |
RADV_CMD_FLAG_INV_VMEM_L1 |
RADV_CMD_FLAG_INV_GLOBAL_L2 |
-
RADV_CMD_FLAG_START_PIPELINE_STATS);
+
RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
} else if (i == 1) {
si_cs_emit_cache_flush(cs,
queue->device->physical_device->rad_info.chip_class,
@@ -2251,7 +2251,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
RADV_CMD_FLAG_INV_SMEM_L1 |
RADV_CMD_FLAG_INV_VMEM_L1 |
RADV_CMD_FLAG_INV_GLOBAL_L2 |
-
RADV_CMD_FLAG_START_PIPELINE_STATS);
+
RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
}
if (!queue->device->ws->cs_finalize(cs))
diff --git a/src/amd/vulkan/radv_private.h
b/src/amd/vulkan/radv_private.h
index 4e4b3a6037..96218f4be2 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1041,6 +1041,7 @@ struct radv_cmd_buffer {
uint32_t gfx9_fence_offset;
struct radeon_winsys_bo *gfx9_fence_bo;
uint32_t gfx9_fence_idx;
+ uint64_t gfx9_eop_bug_va;
/**
* Whether a query pool has been resetted and we have to
flush caches.
@@ -1072,7 +1073,8 @@
Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9
On 07/12/2018 09:43 PM, Dylan Baker wrote:
Quoting Samuel Pitoiset (2018-07-11 02:55:55)
A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
counters) must immediately precede every timestamp event to
prevent a GPU hang on GFX9.
Signed-off-by: Samuel Pitoiset
Cc: 18.1
---
src/amd/vulkan/radv_cmd_buffer.c | 15 +--
src/amd/vulkan/radv_device.c | 4 ++--
src/amd/vulkan/radv_private.h| 7 +--
src/amd/vulkan/radv_query.c | 9 ++---
src/amd/vulkan/si_cmd_buffer.c | 26 +-
5 files changed, 47 insertions(+), 14 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 9da42fe03e..325e1993f8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -319,11 +319,21 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
}
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ unsigned num_db =
cmd_buffer->device->physical_device->rad_info.num_render_backends;
+ unsigned eop_bug_offset;
void *fence_ptr;
+
radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
_buffer->gfx9_fence_offset,
_ptr);
cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
+
+ /* Allocate a buffer for the EOP bug on GFX9. */
+ radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
+_bug_offset, _ptr);
+ cmd_buffer->gfx9_eop_bug_va =
+ radv_buffer_get_va(cmd_buffer->upload.upload_bo);
+ cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
}
cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
@@ -473,7 +483,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer,
cmd_buffer->device->physical_device->rad_info.chip_class,
ptr, va,
radv_cmd_buffer_uses_mec(cmd_buffer),
- flags);
+ flags, cmd_buffer->gfx9_eop_bug_va);
}
if (unlikely(cmd_buffer->device->trace_bo))
@@ -4318,7 +4328,8 @@ static void write_event(struct radv_cmd_buffer
*cmd_buffer,
cmd_buffer->device->physical_device->rad_info.chip_class,
radv_cmd_buffer_uses_mec(cmd_buffer),
V_028A90_BOTTOM_OF_PIPE_TS, 0,
- EOP_DATA_SEL_VALUE_32BIT, va, 2,
value);
+ EOP_DATA_SEL_VALUE_32BIT, va, 2,
value,
+ cmd_buffer->gfx9_eop_bug_va);
}
assert(cmd_buffer->cs->cdw <= cdw_max);
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 73c48cef1f..1c0a50c82f 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2240,7 +2240,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
RADV_CMD_FLAG_INV_SMEM_L1 |
RADV_CMD_FLAG_INV_VMEM_L1 |
RADV_CMD_FLAG_INV_GLOBAL_L2 |
-
RADV_CMD_FLAG_START_PIPELINE_STATS);
+
RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
} else if (i == 1) {
si_cs_emit_cache_flush(cs,
queue->device->physical_device->rad_info.chip_class,
@@ -2251,7 +2251,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
RADV_CMD_FLAG_INV_SMEM_L1 |
RADV_CMD_FLAG_INV_VMEM_L1 |
RADV_CMD_FLAG_INV_GLOBAL_L2 |
-
RADV_CMD_FLAG_START_PIPELINE_STATS);
+
RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
}
if (!queue->device->ws->cs_finalize(cs))
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 4e4b3a6037..96218f4be2 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1041,6 +1041,7 @@ struct radv_cmd_buffer {
uint32_t gfx9_fence_offset;
struct radeon_winsys_bo *gfx9_fence_bo;
uint32_t gfx9_fence_idx;
+ uint64_t gfx9_eop_bug_va;
/**
* Whether a query pool has been resetted and we have to flush caches.
@@ -1072,7 +1073,8 @@ void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs,
Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9
Quoting Samuel Pitoiset (2018-07-11 02:55:55)
> A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
> counters) must immediately precede every timestamp event to
> prevent a GPU hang on GFX9.
>
> Signed-off-by: Samuel Pitoiset
> Cc: 18.1
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 15 +--
> src/amd/vulkan/radv_device.c | 4 ++--
> src/amd/vulkan/radv_private.h| 7 +--
> src/amd/vulkan/radv_query.c | 9 ++---
> src/amd/vulkan/si_cmd_buffer.c | 26 +-
> 5 files changed, 47 insertions(+), 14 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 9da42fe03e..325e1993f8 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -319,11 +319,21 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer
> *cmd_buffer)
> }
>
> if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
> {
> + unsigned num_db =
> cmd_buffer->device->physical_device->rad_info.num_render_backends;
> + unsigned eop_bug_offset;
> void *fence_ptr;
> +
> radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
> _buffer->gfx9_fence_offset,
> _ptr);
> cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
> +
> + /* Allocate a buffer for the EOP bug on GFX9. */
> + radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
> +_bug_offset, _ptr);
> + cmd_buffer->gfx9_eop_bug_va =
> + radv_buffer_get_va(cmd_buffer->upload.upload_bo);
> + cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
> }
>
> cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
> @@ -473,7 +483,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer
> *cmd_buffer,
>
> cmd_buffer->device->physical_device->rad_info.chip_class,
>ptr, va,
>radv_cmd_buffer_uses_mec(cmd_buffer),
> - flags);
> + flags, cmd_buffer->gfx9_eop_bug_va);
> }
>
> if (unlikely(cmd_buffer->device->trace_bo))
> @@ -4318,7 +4328,8 @@ static void write_event(struct radv_cmd_buffer
> *cmd_buffer,
>
> cmd_buffer->device->physical_device->rad_info.chip_class,
>
> radv_cmd_buffer_uses_mec(cmd_buffer),
>V_028A90_BOTTOM_OF_PIPE_TS, 0,
> - EOP_DATA_SEL_VALUE_32BIT, va, 2,
> value);
> + EOP_DATA_SEL_VALUE_32BIT, va, 2,
> value,
> + cmd_buffer->gfx9_eop_bug_va);
> }
>
> assert(cmd_buffer->cs->cdw <= cdw_max);
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 73c48cef1f..1c0a50c82f 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -2240,7 +2240,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
>RADV_CMD_FLAG_INV_SMEM_L1 |
>RADV_CMD_FLAG_INV_VMEM_L1 |
>RADV_CMD_FLAG_INV_GLOBAL_L2 |
> -
> RADV_CMD_FLAG_START_PIPELINE_STATS);
> +
> RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
> } else if (i == 1) {
> si_cs_emit_cache_flush(cs,
>
> queue->device->physical_device->rad_info.chip_class,
> @@ -2251,7 +2251,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
>RADV_CMD_FLAG_INV_SMEM_L1 |
>RADV_CMD_FLAG_INV_VMEM_L1 |
>RADV_CMD_FLAG_INV_GLOBAL_L2 |
> -
> RADV_CMD_FLAG_START_PIPELINE_STATS);
> +
> RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
> }
>
> if (!queue->device->ws->cs_finalize(cs))
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 4e4b3a6037..96218f4be2 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1041,6 +1041,7 @@ struct radv_cmd_buffer {
> uint32_t gfx9_fence_offset;
> struct radeon_winsys_bo *gfx9_fence_bo;
> uint32_t gfx9_fence_idx;
> + uint64_t gfx9_eop_bug_va;
>
> /**
> * Whether a query pool has been
