On Tuesday, August 28, 2018 10:54:57 AM PDT Anuj Phogat wrote:
> h/w specification requires this bit to be always set.
>
> Suggested-by: Kenneth Graunke
> Signed-off-by: Anuj Phogat
> ---
> src/intel/genxml/gen11.xml| 5 +
> src/intel/vulkan/genX_state.c | 14 ++
> 2 files changed, 19 insertions(+)
>
> diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
> index 1b3befbbfc9..c69d7dc89c2 100644
> --- a/src/intel/genxml/gen11.xml
> +++ b/src/intel/genxml/gen11.xml
> @@ -3640,4 +3640,9 @@
> start="21" end="21" type="bool"/>
>
>
> +
> + type="bool"/>
> + end="17" type="bool"/>
> +
> +
>
> diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
> index d6ccd21524c..2f48a7e1995 100644
> --- a/src/intel/vulkan/genX_state.c
> +++ b/src/intel/vulkan/genX_state.c
> @@ -172,6 +172,20 @@ genX(init_device_state)(struct anv_device *device)
>lri.RegisterOffset = GENX(SAMPLER_MODE_num);
>lri.DataDWord = sampler_mode;
> }
> +
> + /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
> +* HALF_SLICE_CHICKEN7 register.
> +*/
> + uint32_t half_slice_chicken7;
> + anv_pack_struct(_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
> + .EnabledTexelOffsetPrecisionFix = true,
> + .EnabledTexelOffsetPrecisionFixMask = true);
> +
> +anv_batch_emit(, GENX(MI_LOAD_REGISTER_IMM), lri) {
> + lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
> + lri.DataDWord = half_slice_chicken7;
> + }
> +
> #endif
>
> /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
>
Looks like this #endif is for a GEN_GEN == 11 block (thanks diff...), so
Reviewed-by: Kenneth Graunke
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