Previously, all needed pipe controls were flushed out right before either 3DPRIMITIVE or GPGPU_WALKER. This commit moves pipeline flushes to the beginning of state emit for a given draw or dispatch call rather than the end. The result is that any previously pending state is now flushed before we even start setting up new state. Since nothing in the pipeline state emit code dirties any PIPE_CONTROL bits, it's safe to move it higher up and it won't even lead to any additional flushing. One additional flush is added at the end of begin_subpass right before emitting depth and stencil buffer packets. This may lead to some extra flushing but that's likely to happen on a subpass boundary anyway.
The idea behind moving things earlier is so that PIPE_CONTROLs that are inserted due to a hardware workaround will happen closer to where the workaround is applied. For example, the pipe control that happens after doing a HiZ clear now occurs *before* the depth/stencil or any 3D pipeline setup packets for the next draw occur. This appears to maybe help DiRT3 on Sky Lake (though the hang is very hard to reproduce). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107760 --- src/intel/vulkan/genX_cmd_buffer.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index f95e106f923..a03c0ff8a27 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -2525,6 +2525,8 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) genX(flush_pipeline_select_3d)(cmd_buffer); + genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); + if (vb_emit) { const uint32_t num_buffers = __builtin_popcount(vb_emit); const uint32_t num_dwords = 1 + num_buffers * 4; @@ -2642,8 +2644,6 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) gen7_cmd_buffer_emit_scissor(cmd_buffer); genX(cmd_buffer_flush_dynamic_state)(cmd_buffer); - - genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); } static void @@ -3043,10 +3043,12 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer) * sufficient." */ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT; - genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); + } + + genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); + if (cmd_buffer->state.compute.pipeline_dirty) anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch); - } if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) || cmd_buffer->state.compute.pipeline_dirty) { @@ -3073,8 +3075,6 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer) } cmd_buffer->state.compute.pipeline_dirty = false; - - genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); } #if GEN_GEN == 7 @@ -3825,6 +3825,8 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, att_state->pending_load_aspects = 0; } + genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); + cmd_buffer_emit_depth_stencil(cmd_buffer); } -- 2.17.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
