Re: [Mesa-dev] [PATCH] gallium: use "ull" number suffix to keep the QtCreator parser happy
On Saturday, 2017-07-08 23:59:25 +0200, Thomas Helland wrote:
> Yes please!
> I find this much more intuitive, as a bonus =)
>
> Reviewed-by: Thomas Helland
>
Agreed, r-b as well:
Reviewed-by: Eric Engestrom
You missed a couple though, feel free to squash this with your commit:
8<
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index 6992da16d5..1893d4c4a5 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -342,7 +342,7 @@ struct __DRI2throttleExtensionRec {
#define __DRI2_FENCE "DRI2_Fence"
#define __DRI2_FENCE_VERSION 2
-#define __DRI2_FENCE_TIMEOUT_INFINITE 0xllu
+#define __DRI2_FENCE_TIMEOUT_INFINITE 0xull
#define __DRI2_FENCE_FLAG_FLUSH_COMMANDS (1 << 0)
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c
b/src/gallium/drivers/radeonsi/si_cp_dma.c
index e737519eef..5e461b970b 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -215,7 +215,7 @@ static void si_clear_buffer(struct pipe_context *ctx,
struct pipe_resource *dst,
if (!size)
return;
- dma_clear_size = size & ~3llu;
+ dma_clear_size = size & ~3ull;
/* Mark the buffer range of destination as valid (initialized),
* so that transfer_map knows it should wait for the GPU when mapping
diff --git a/src/util/bitscan.h b/src/util/bitscan.h
index 7a605e0370..611e812059 100644
--- a/src/util/bitscan.h
+++ b/src/util/bitscan.h
@@ -136,7 +136,7 @@ u_bit_scan_consecutive_range(unsigned *mask, int *start,
int *count)
static inline void
u_bit_scan_consecutive_range64(uint64_t *mask, int *start, int *count)
{
- if (*mask == ~0llu) {
+ if (*mask == ~0ull) {
*start = 0;
*count = 64;
*mask = 0;
>8
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Re: [Mesa-dev] [PATCH] gallium: use "ull" number suffix to keep the QtCreator parser happy
Yes please!
I find this much more intuitive, as a bonus =)
Reviewed-by: Thomas Helland
2017-07-08 2:36 GMT+02:00 Marek Olšák :
> From: Marek Olšák
>
> It can't parse "llu".
> ---
> src/gallium/drivers/r600/r600_state_common.c| 4 +--
> src/gallium/drivers/radeon/r600_pipe_common.h | 44
> -
> src/gallium/drivers/radeonsi/si_debug.c | 4 +--
> src/gallium/drivers/radeonsi/si_shader.c| 2 +-
> src/gallium/drivers/radeonsi/si_state_shaders.c | 10 +++---
> src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 2 +-
> src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 2 +-
> src/mesa/state_tracker/st_atom.h| 4 +--
> 8 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_state_common.c
> b/src/gallium/drivers/r600/r600_state_common.c
> index 8ace779..4c97efa 100644
> --- a/src/gallium/drivers/r600/r600_state_common.c
> +++ b/src/gallium/drivers/r600/r600_state_common.c
> @@ -840,25 +840,25 @@ static void *r600_create_shader_state(struct
> pipe_context *ctx,
>
> for (i = 0; i < sel->info.num_outputs; i++) {
> unsigned name = sel->info.output_semantic_name[i];
> unsigned index = sel->info.output_semantic_index[i];
>
> switch (name) {
> case TGSI_SEMANTIC_TESSINNER:
> case TGSI_SEMANTIC_TESSOUTER:
> case TGSI_SEMANTIC_PATCH:
> sel->lds_patch_outputs_written_mask |=
> - 1llu <<
> r600_get_lds_unique_index(name, index);
> + 1ull <<
> r600_get_lds_unique_index(name, index);
> break;
> default:
> sel->lds_outputs_written_mask |=
> - 1llu <<
> r600_get_lds_unique_index(name, index);
> + 1ull <<
> r600_get_lds_unique_index(name, index);
> }
> }
> break;
> default:
> break;
> }
>
> return sel;
> }
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index b22a3a7..5c761f3 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -83,42 +83,42 @@
> #define DBG_NO_TGSI(1 << 13)
> #define DBG_NO_ASM (1 << 14)
> #define DBG_PREOPT_IR (1 << 15)
> #define DBG_CHECK_IR (1 << 16)
> #define DBG_NO_OPT_VARIANT (1 << 17)
> #define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
> /* gaps */
> #define DBG_TEST_DMA (1 << 20)
> /* Bits 21-31 are reserved for the r600g driver. */
> /* features */
> -#define DBG_NO_ASYNC_DMA (1llu << 32)
> -#define DBG_NO_HYPERZ (1llu << 33)
> -#define DBG_NO_DISCARD_RANGE (1llu << 34)
> -#define DBG_NO_2D_TILING (1llu << 35)
> -#define DBG_NO_TILING (1llu << 36)
> -#define DBG_SWITCH_ON_EOP (1llu << 37)
> -#define DBG_FORCE_DMA (1llu << 38)
> -#define DBG_PRECOMPILE (1llu << 39)
> -#define DBG_INFO (1llu << 40)
> -#define DBG_NO_WC (1llu << 41)
> -#define DBG_CHECK_VM (1llu << 42)
> -#define DBG_NO_DCC (1llu << 43)
> -#define DBG_NO_DCC_CLEAR (1llu << 44)
> -#define DBG_NO_RB_PLUS (1llu << 45)
> -#define DBG_SI_SCHED (1llu << 46)
> -#define DBG_MONOLITHIC_SHADERS (1llu << 47)
> -#define DBG_NO_CE (1llu << 48)
> -#define DBG_UNSAFE_MATH(1llu << 49)
> -#define DBG_NO_DCC_FB (1llu << 50)
> -#define DBG_TEST_VMFAULT_CP(1llu << 51)
> -#define DBG_TEST_VMFAULT_SDMA (1llu << 52)
> -#define DBG_TEST_VMFAULT_SHADER(1llu << 53)
> +#define DBG_NO_ASYNC_DMA (1ull << 32)
> +#define DBG_NO_HYPERZ (1ull << 33)
> +#define DBG_NO_DISCARD_RANGE (1ull << 34)
> +#define DBG_NO_2D_TILING (1ull << 35)
> +#define DBG_NO_TILING (1ull << 36)
> +#define DBG_SWITCH_ON_EOP (1ull << 37)
> +#define DBG_FORCE_DMA (1ull << 38)
> +#define DBG_PRECOMPILE (1ull << 39)
> +#define DBG_INFO (1ull << 40)
> +#define DBG_NO_WC (1ull << 41)
> +#define DBG_CHECK_VM (1ull << 42)
> +#define DBG_NO_DCC (1ull << 43)
> +#define DBG_NO_DCC_CLEAR (1ull << 44)
> +#define DBG_NO_RB_PLUS (1ull << 45)
> +#define DBG_SI_SCHED (1ull << 46)
> +#define DBG_MONOLITHIC_SHADERS (1ull << 47)
> +#define DBG_NO_CE (1ull << 48)
> +#define DBG_UNSAFE_MATH(1ull << 49)
> +#define DBG_NO_DCC_FB (1ull << 50)
> +#define DBG_TEST_VMFAULT_CP(1ull << 51)
> +#define DBG_TEST_VMFAULT_SDMA (1ull << 52)
> +#define DBG
[Mesa-dev] [PATCH] gallium: use "ull" number suffix to keep the QtCreator parser happy
From: Marek Olšák
It can't parse "llu".
---
src/gallium/drivers/r600/r600_state_common.c| 4 +--
src/gallium/drivers/radeon/r600_pipe_common.h | 44 -
src/gallium/drivers/radeonsi/si_debug.c | 4 +--
src/gallium/drivers/radeonsi/si_shader.c| 2 +-
src/gallium/drivers/radeonsi/si_state_shaders.c | 10 +++---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 2 +-
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 2 +-
src/mesa/state_tracker/st_atom.h| 4 +--
8 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 8ace779..4c97efa 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -840,25 +840,25 @@ static void *r600_create_shader_state(struct pipe_context
*ctx,
for (i = 0; i < sel->info.num_outputs; i++) {
unsigned name = sel->info.output_semantic_name[i];
unsigned index = sel->info.output_semantic_index[i];
switch (name) {
case TGSI_SEMANTIC_TESSINNER:
case TGSI_SEMANTIC_TESSOUTER:
case TGSI_SEMANTIC_PATCH:
sel->lds_patch_outputs_written_mask |=
- 1llu << r600_get_lds_unique_index(name,
index);
+ 1ull << r600_get_lds_unique_index(name,
index);
break;
default:
sel->lds_outputs_written_mask |=
- 1llu << r600_get_lds_unique_index(name,
index);
+ 1ull << r600_get_lds_unique_index(name,
index);
}
}
break;
default:
break;
}
return sel;
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index b22a3a7..5c761f3 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -83,42 +83,42 @@
#define DBG_NO_TGSI(1 << 13)
#define DBG_NO_ASM (1 << 14)
#define DBG_PREOPT_IR (1 << 15)
#define DBG_CHECK_IR (1 << 16)
#define DBG_NO_OPT_VARIANT (1 << 17)
#define DBG_FS_CORRECT_DERIVS_AFTER_KILL (1 << 18)
/* gaps */
#define DBG_TEST_DMA (1 << 20)
/* Bits 21-31 are reserved for the r600g driver. */
/* features */
-#define DBG_NO_ASYNC_DMA (1llu << 32)
-#define DBG_NO_HYPERZ (1llu << 33)
-#define DBG_NO_DISCARD_RANGE (1llu << 34)
-#define DBG_NO_2D_TILING (1llu << 35)
-#define DBG_NO_TILING (1llu << 36)
-#define DBG_SWITCH_ON_EOP (1llu << 37)
-#define DBG_FORCE_DMA (1llu << 38)
-#define DBG_PRECOMPILE (1llu << 39)
-#define DBG_INFO (1llu << 40)
-#define DBG_NO_WC (1llu << 41)
-#define DBG_CHECK_VM (1llu << 42)
-#define DBG_NO_DCC (1llu << 43)
-#define DBG_NO_DCC_CLEAR (1llu << 44)
-#define DBG_NO_RB_PLUS (1llu << 45)
-#define DBG_SI_SCHED (1llu << 46)
-#define DBG_MONOLITHIC_SHADERS (1llu << 47)
-#define DBG_NO_CE (1llu << 48)
-#define DBG_UNSAFE_MATH(1llu << 49)
-#define DBG_NO_DCC_FB (1llu << 50)
-#define DBG_TEST_VMFAULT_CP(1llu << 51)
-#define DBG_TEST_VMFAULT_SDMA (1llu << 52)
-#define DBG_TEST_VMFAULT_SHADER(1llu << 53)
+#define DBG_NO_ASYNC_DMA (1ull << 32)
+#define DBG_NO_HYPERZ (1ull << 33)
+#define DBG_NO_DISCARD_RANGE (1ull << 34)
+#define DBG_NO_2D_TILING (1ull << 35)
+#define DBG_NO_TILING (1ull << 36)
+#define DBG_SWITCH_ON_EOP (1ull << 37)
+#define DBG_FORCE_DMA (1ull << 38)
+#define DBG_PRECOMPILE (1ull << 39)
+#define DBG_INFO (1ull << 40)
+#define DBG_NO_WC (1ull << 41)
+#define DBG_CHECK_VM (1ull << 42)
+#define DBG_NO_DCC (1ull << 43)
+#define DBG_NO_DCC_CLEAR (1ull << 44)
+#define DBG_NO_RB_PLUS (1ull << 45)
+#define DBG_SI_SCHED (1ull << 46)
+#define DBG_MONOLITHIC_SHADERS (1ull << 47)
+#define DBG_NO_CE (1ull << 48)
+#define DBG_UNSAFE_MATH(1ull << 49)
+#define DBG_NO_DCC_FB (1ull << 50)
+#define DBG_TEST_VMFAULT_CP(1ull << 51)
+#define DBG_TEST_VMFAULT_SDMA (1ull << 52)
+#define DBG_TEST_VMFAULT_SHADER(1ull << 53)
#define R600_MAP_BUFFER_ALIGNMENT 64
#define R600_MAX_VIEWPORTS16
#define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
enum r600_coherency {
R600_COHERENCY_NONE, /* no cache flushes needed */
R600_COHERENCY_SHADER,
R600_COHERENCY_CB_META,
diff --git a/src/gallium/driver
