Re: [Mesa-dev] [PATCH] gm107/ir: add ATOM CAS emission

2016-02-16 Thread Ilia Mirkin
Reviewed-by: Ilia Mirkin 

On Tue, Feb 16, 2016 at 12:53 PM, Samuel Pitoiset
 wrote:
> From: Samuel Pitoiset 
>
> This fixes the following dEQP test and the other compswap variants.
>
> dEQP-GLES31.functional.ssbo.atomic.compswap.highp_int
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 42 
> ++
>  1 file changed, 27 insertions(+), 15 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
> index 5dbdeea..025eb19 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
> @@ -2332,22 +2332,34 @@ void
>  CodeEmitterGM107::emitATOM()
>  {
> unsigned dType, subOp;
> -   switch (insn->dType) {
> -   case TYPE_U32: dType = 0; break;
> -   case TYPE_S32: dType = 1; break;
> -   case TYPE_U64: dType = 2; break;
> -   case TYPE_F32: dType = 3; break;
> -   case TYPE_B128: dType = 4; break;
> -   case TYPE_S64: dType = 5; break;
> -   default: assert(!"unexpected dType"); dType = 0; break;
> -   }
> -   if (insn->subOp == NV50_IR_SUBOP_ATOM_EXCH)
> -  subOp = 8;
> -   else
> -  subOp = insn->subOp;
> -   assert(insn->subOp != NV50_IR_SUBOP_ATOM_CAS); /* XXX */
>
> -   emitInsn (0xed00);
> +   if (insn->subOp == NV50_IR_SUBOP_ATOM_CAS) {
> +  switch (insn->dType) {
> +  case TYPE_U32: dType = 0; break;
> +  case TYPE_U64: dType = 1; break;
> +  default: assert(!"unexpected dType"); dType = 0; break;
> +  }
> +  subOp = 15;
> +
> +  emitInsn (0xee00);
> +   } else {
> +  switch (insn->dType) {
> +  case TYPE_U32: dType = 0; break;
> +  case TYPE_S32: dType = 1; break;
> +  case TYPE_U64: dType = 2; break;
> +  case TYPE_F32: dType = 3; break;
> +  case TYPE_B128: dType = 4; break;
> +  case TYPE_S64: dType = 5; break;
> +  default: assert(!"unexpected dType"); dType = 0; break;
> +  }
> +  if (insn->subOp == NV50_IR_SUBOP_ATOM_EXCH)
> + subOp = 8;
> +  else
> + subOp = insn->subOp;
> +
> +  emitInsn (0xed00);
> +   }
> +
> emitField(0x34, 4, subOp);
> emitField(0x31, 3, dType);
> emitField(0x30, 1, insn->src(0).getIndirect(0)->getSize() == 8);
> --
> 2.7.1
>
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[Mesa-dev] [PATCH] gm107/ir: add ATOM CAS emission

2016-02-16 Thread Samuel Pitoiset
From: Samuel Pitoiset 

This fixes the following dEQP test and the other compswap variants.

dEQP-GLES31.functional.ssbo.atomic.compswap.highp_int

Signed-off-by: Samuel Pitoiset 
---
 .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 42 ++
 1 file changed, 27 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 5dbdeea..025eb19 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -2332,22 +2332,34 @@ void
 CodeEmitterGM107::emitATOM()
 {
unsigned dType, subOp;
-   switch (insn->dType) {
-   case TYPE_U32: dType = 0; break;
-   case TYPE_S32: dType = 1; break;
-   case TYPE_U64: dType = 2; break;
-   case TYPE_F32: dType = 3; break;
-   case TYPE_B128: dType = 4; break;
-   case TYPE_S64: dType = 5; break;
-   default: assert(!"unexpected dType"); dType = 0; break;
-   }
-   if (insn->subOp == NV50_IR_SUBOP_ATOM_EXCH)
-  subOp = 8;
-   else
-  subOp = insn->subOp;
-   assert(insn->subOp != NV50_IR_SUBOP_ATOM_CAS); /* XXX */
 
-   emitInsn (0xed00);
+   if (insn->subOp == NV50_IR_SUBOP_ATOM_CAS) {
+  switch (insn->dType) {
+  case TYPE_U32: dType = 0; break;
+  case TYPE_U64: dType = 1; break;
+  default: assert(!"unexpected dType"); dType = 0; break;
+  }
+  subOp = 15;
+
+  emitInsn (0xee00);
+   } else {
+  switch (insn->dType) {
+  case TYPE_U32: dType = 0; break;
+  case TYPE_S32: dType = 1; break;
+  case TYPE_U64: dType = 2; break;
+  case TYPE_F32: dType = 3; break;
+  case TYPE_B128: dType = 4; break;
+  case TYPE_S64: dType = 5; break;
+  default: assert(!"unexpected dType"); dType = 0; break;
+  }
+  if (insn->subOp == NV50_IR_SUBOP_ATOM_EXCH)
+ subOp = 8;
+  else
+ subOp = insn->subOp;
+
+  emitInsn (0xed00);
+   }
+
emitField(0x34, 4, subOp);
emitField(0x31, 3, dType);
emitField(0x30, 1, insn->src(0).getIndirect(0)->getSize() == 8);
-- 
2.7.1

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