Re: [Mesa-dev] [PATCH] intel/isl: Avoid tiling on 16K-wide render targets
On Thu, Aug 09, 2018 at 04:26:06PM +0300, Andres Gomez wrote:
> Ugh!
>
> Unfortunately, as I've commented at:
> https://bugs.freedesktop.org/show_bug.cgi?id=107359
>
> This is now breaking these other CTS tests:
> GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_formats
> GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_origins
> GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_sample_count
> GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_sizes
> GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_read_buffer_different_formats
> GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_read_buffer_different_origins
> GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_read_buffer_different_sizes
> GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit
>
>
Sorry about that, I must not have tested this in CI. I'll send out a
better tested v2.
-Nanley
> On Mon, 2018-07-30 at 19:25 +0300, Andres Gomez wrote:
> > That was quick! ☺
> >
> > On Fri, 2018-07-27 at 16:02 -0700, Nanley Chery wrote:
> > > Fix rendering issues on BDW and SKL.
> > >
> > > Fixes 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
> > > ("i965/miptree: Use the correct BLT pitch")
> >
> > I'd add here some lines listing the tests fixed by this patch.
> >
> > >
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107359
> > > Cc:
> >
> > This is:
> >
> > Tested-by: Andres Gomez
> >
> > > ---
> > >
> > > We could probably add an assert when filling out the surface state, but
> > > I think BLORP would need a non-trivial amount of work done as a
> > > prerequisite. I'm thinking specifically of the cases where we bind a
> > > depth buffer as a render target.
> > >
> > > I won't be able to push anything until about a week from EOD today, so
> > > if this does end up getting reviewed, please feel free to push it.
> > >
> > > src/intel/isl/isl_gen7.c | 19 +++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
> > > index 4fa9851233f..2d85f4b568d 100644
> > > --- a/src/intel/isl/isl_gen7.c
> > > +++ b/src/intel/isl/isl_gen7.c
> > > @@ -294,6 +294,25 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
> > > */
> > > if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb
> > > >= 128)
> > >*flags &= ~ISL_TILING_Y0_BIT;
> > > +
> > > + /* From the BDW and SKL PRMs, Volume 2d,
> > > +* RENDER_SURFACE_STATE::Width - Programming Notes:
> > > +*
> > > +* A known issue exists if a primitive is rendered to the first 2
> > > rows and
> > > +* last 2 columns of a 16K width surface. If any geometry is drawn
> > > inside
> > > +* this square it will be copied to column X=2 and X=3 (arrangement
> > > on Y
> > > +* position will stay the same). If any geometry exceeds the
> > > boundaries of
> > > +* this 2x2 region it will be drawn normally. The issue also only
> > > occurs
> > > +* if the surface has TileMode != Linear.
> > > +*
> > > +* To prevent this rendering corruption, only allow linear tiling for
> > > +* surfaces with widths greater than 16K-2 pixels.
> > > +*/
> > > + if (info->width > 16382 &&
> > > + info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
> > > + (ISL_DEV_GEN(dev) == 8 || dev->info->is_skylake)) {
> > > + *flags &= ISL_TILING_LINEAR_BIT;
> > > + }
> > > }
> > >
> > > void
> --
> Br,
>
> Andres
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Re: [Mesa-dev] [PATCH] intel/isl: Avoid tiling on 16K-wide render targets
Ugh!
Unfortunately, as I've commented at:
https://bugs.freedesktop.org/show_bug.cgi?id=107359
This is now breaking these other CTS tests:
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_formats
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_origins
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_sample_count
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_framebuffers_different_sizes
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_read_buffer_different_formats
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_read_buffer_different_origins
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_error_blitframebuffer_multisampled_read_buffer_different_sizes
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit
On Mon, 2018-07-30 at 19:25 +0300, Andres Gomez wrote:
> That was quick! ☺
>
> On Fri, 2018-07-27 at 16:02 -0700, Nanley Chery wrote:
> > Fix rendering issues on BDW and SKL.
> >
> > Fixes 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
> > ("i965/miptree: Use the correct BLT pitch")
>
> I'd add here some lines listing the tests fixed by this patch.
>
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107359
> > Cc:
>
> This is:
>
> Tested-by: Andres Gomez
>
> > ---
> >
> > We could probably add an assert when filling out the surface state, but
> > I think BLORP would need a non-trivial amount of work done as a
> > prerequisite. I'm thinking specifically of the cases where we bind a
> > depth buffer as a render target.
> >
> > I won't be able to push anything until about a week from EOD today, so
> > if this does end up getting reviewed, please feel free to push it.
> >
> > src/intel/isl/isl_gen7.c | 19 +++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
> > index 4fa9851233f..2d85f4b568d 100644
> > --- a/src/intel/isl/isl_gen7.c
> > +++ b/src/intel/isl/isl_gen7.c
> > @@ -294,6 +294,25 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
> > */
> > if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >=
> > 128)
> >*flags &= ~ISL_TILING_Y0_BIT;
> > +
> > + /* From the BDW and SKL PRMs, Volume 2d,
> > +* RENDER_SURFACE_STATE::Width - Programming Notes:
> > +*
> > +* A known issue exists if a primitive is rendered to the first 2
> > rows and
> > +* last 2 columns of a 16K width surface. If any geometry is drawn
> > inside
> > +* this square it will be copied to column X=2 and X=3 (arrangement
> > on Y
> > +* position will stay the same). If any geometry exceeds the
> > boundaries of
> > +* this 2x2 region it will be drawn normally. The issue also only
> > occurs
> > +* if the surface has TileMode != Linear.
> > +*
> > +* To prevent this rendering corruption, only allow linear tiling for
> > +* surfaces with widths greater than 16K-2 pixels.
> > +*/
> > + if (info->width > 16382 &&
> > + info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
> > + (ISL_DEV_GEN(dev) == 8 || dev->info->is_skylake)) {
> > + *flags &= ISL_TILING_LINEAR_BIT;
> > + }
> > }
> >
> > void
--
Br,
Andres
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Re: [Mesa-dev] [PATCH] intel/isl: Avoid tiling on 16K-wide render targets
That was quick! ☺
On Fri, 2018-07-27 at 16:02 -0700, Nanley Chery wrote:
> Fix rendering issues on BDW and SKL.
>
> Fixes 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
> ("i965/miptree: Use the correct BLT pitch")
I'd add here some lines listing the tests fixed by this patch.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107359
> Cc:
This is:
Tested-by: Andres Gomez
> ---
>
> We could probably add an assert when filling out the surface state, but
> I think BLORP would need a non-trivial amount of work done as a
> prerequisite. I'm thinking specifically of the cases where we bind a
> depth buffer as a render target.
>
> I won't be able to push anything until about a week from EOD today, so
> if this does end up getting reviewed, please feel free to push it.
>
> src/intel/isl/isl_gen7.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
> index 4fa9851233f..2d85f4b568d 100644
> --- a/src/intel/isl/isl_gen7.c
> +++ b/src/intel/isl/isl_gen7.c
> @@ -294,6 +294,25 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
> */
> if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >=
> 128)
>*flags &= ~ISL_TILING_Y0_BIT;
> +
> + /* From the BDW and SKL PRMs, Volume 2d,
> +* RENDER_SURFACE_STATE::Width - Programming Notes:
> +*
> +* A known issue exists if a primitive is rendered to the first 2 rows
> and
> +* last 2 columns of a 16K width surface. If any geometry is drawn
> inside
> +* this square it will be copied to column X=2 and X=3 (arrangement on Y
> +* position will stay the same). If any geometry exceeds the boundaries
> of
> +* this 2x2 region it will be drawn normally. The issue also only occurs
> +* if the surface has TileMode != Linear.
> +*
> +* To prevent this rendering corruption, only allow linear tiling for
> +* surfaces with widths greater than 16K-2 pixels.
> +*/
> + if (info->width > 16382 &&
> + info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
> + (ISL_DEV_GEN(dev) == 8 || dev->info->is_skylake)) {
> + *flags &= ISL_TILING_LINEAR_BIT;
> + }
> }
>
> void
--
Br,
Andres
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[Mesa-dev] [PATCH] intel/isl: Avoid tiling on 16K-wide render targets
Fix rendering issues on BDW and SKL.
Fixes 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
("i965/miptree: Use the correct BLT pitch")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107359
Cc:
---
We could probably add an assert when filling out the surface state, but
I think BLORP would need a non-trivial amount of work done as a
prerequisite. I'm thinking specifically of the cases where we bind a
depth buffer as a render target.
I won't be able to push anything until about a week from EOD today, so
if this does end up getting reviewed, please feel free to push it.
src/intel/isl/isl_gen7.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 4fa9851233f..2d85f4b568d 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -294,6 +294,25 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
*/
if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128)
*flags &= ~ISL_TILING_Y0_BIT;
+
+ /* From the BDW and SKL PRMs, Volume 2d,
+* RENDER_SURFACE_STATE::Width - Programming Notes:
+*
+* A known issue exists if a primitive is rendered to the first 2 rows and
+* last 2 columns of a 16K width surface. If any geometry is drawn inside
+* this square it will be copied to column X=2 and X=3 (arrangement on Y
+* position will stay the same). If any geometry exceeds the boundaries of
+* this 2x2 region it will be drawn normally. The issue also only occurs
+* if the surface has TileMode != Linear.
+*
+* To prevent this rendering corruption, only allow linear tiling for
+* surfaces with widths greater than 16K-2 pixels.
+*/
+ if (info->width > 16382 &&
+ info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
+ (ISL_DEV_GEN(dev) == 8 || dev->info->is_skylake)) {
+ *flags &= ISL_TILING_LINEAR_BIT;
+ }
}
void
--
2.18.0
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