Re: [Mesa-dev] [PATCH] nv50/ir: Change chipset constants to ISA constants and #define to enum.

2017-04-12 Thread Boyan Ding 
2017-04-13 13:45 GMT+08:00 Matthew Mondazzi :
> More relevant ISA constants put in place of chipset compares. This helps 
> better display which features are available to card than previous chipset 
> compares, making future development easier continue with.
>
> Signed-off-by: Matthew Mondazzi 
> ---
>  .../drivers/nouveau/codegen/nv50_ir_driver.h   | 11 ---
>  .../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp  |  2 +-
>  .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp  | 24 +++---
>  .../nouveau/codegen/nv50_ir_lowering_nv50.cpp  |  2 +-
>  .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 38 
> +++---
>  .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   |  2 +-
>  src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp |  8 ++---
>  .../drivers/nouveau/codegen/nv50_ir_target.cpp |  2 +-
>  .../drivers/nouveau/codegen/nv50_ir_target.h   |  2 +-
>  .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  8 ++---
>  10 files changed, 51 insertions(+), 48 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> index 76c815e..12a45fc 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> @@ -75,10 +75,13 @@ struct nv50_ir_prog_symbol
> uint32_t offset;
>  };
>
> -#define NVISA_SM30   0xe0
> -#define NVISA_SM35   0xea
> -#define NVISA_SM50   0x110
> -
> +enum sm_isa {
> +  NVISA_SM10 = 0x84, //
> +  NVISA_SM20 = 0xc0, // Fermi
> +  NVISA_SM30 = 0xe0, // Keplar
> +  NVISA_SM35 = 0xea, // Keplar
> +  NVISA_SM50 = 0x110, // Maxwell
> +};

We use 3-space indentation here.

Boyan

>
>  struct nv50_ir_prog_info
>  {
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
> index cc2a88e..9620151 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
> @@ -635,7 +635,7 @@ CodeEmitterNV50::emitLOAD(const Instruction *i)
>   code[1] |= 0x0400;
>break;
> case FILE_MEMORY_SHARED:
> -  if (targ->getChipset() >= 0x84) {
> +  if (targ->getIsa() >= NVISA_SM10) {
>   assert(offset <= (int32_t)(0x3fff * typeSizeof(i->sType)));
>   code[0] = 0x1001;
>   code[1] = 0x4000;
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> index ed29661..045e6e0 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> @@ -806,7 +806,7 @@ CodeEmitterNVC0::emitSHLADD(const Instruction *i)
>  void
>  CodeEmitterNVC0::emitMADSP(const Instruction *i)
>  {
> -   assert(targ->getChipset() >= NVISA_SM30);
> +   assert(targ->getIsa() >= NVISA_SM30);
>
> emitForm_A(i, HEX64(, 0003));
>
> @@ -1852,7 +1852,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
> case FILE_MEMORY_LOCAL:  opc = 0xc800; break;
> case FILE_MEMORY_SHARED:
>if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
> - if (targ->getChipset() >= NVISA_SM30)
> + if (targ->getIsa() >= NVISA_SM30)
>  opc = 0xb800;
>   else
>  opc = 0xcc00;
> @@ -1868,7 +1868,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
> code[0] = 0x0005;
> code[1] = opc;
>
> -   if (targ->getChipset() >= NVISA_SM30) {
> +   if (targ->getIsa() >= NVISA_SM30) {
>// Unlocked store on shared memory can fail.
>if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
>i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
> @@ -1901,7 +1901,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
> case FILE_MEMORY_LOCAL:  opc = 0xc000; break;
> case FILE_MEMORY_SHARED:
>if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
> - if (targ->getChipset() >= NVISA_SM30)
> + if (targ->getIsa() >= NVISA_SM30)
>  opc = 0xa800;
>   else
>  opc = 0xc400;
> @@ -1944,7 +1944,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
>code[0] |= 63 << 14;
>
> if (p >= 0) {
> -  if (targ->getChipset() >= NVISA_SM30)
> +  if (targ->getIsa() >= NVISA_SM30)
>   defId(i->def(p), 8);
>else
>   defId(i->def(p), 32 + 18);
> @@ -2362,7 +2362,7 @@ CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
>  void
>  CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
>  {
> -   assert(targ->getChipset() < NVISA_SM30);
> +   assert(targ->getIsa() < NVISA_SM30);
>
> if (i->tex.rIndirectSrc < 0) {
>code[1] |= 0x4000;
> @@ -2375,7 +2375,7 @@ CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
>  void
>  CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
>  {
> -   assert(targ->getChipset() < NVISA_SM30);
> +   assert(targ->getIsa() <

Re: [Mesa-dev] [PATCH] nv50/ir: Change chipset constants to ISA constants and #define to enum.

2017-04-12 Thread Ilia Mirkin 
On Thu, Apr 13, 2017 at 1:45 AM, Matthew Mondazzi  wrote:
> More relevant ISA constants put in place of chipset compares. This helps 
> better display which features are available to card than previous chipset 
> compares, making future development easier continue with.
>
> Signed-off-by: Matthew Mondazzi 
> ---
>  .../drivers/nouveau/codegen/nv50_ir_driver.h   | 11 ---
>  .../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp  |  2 +-
>  .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp  | 24 +++---
>  .../nouveau/codegen/nv50_ir_lowering_nv50.cpp  |  2 +-
>  .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 38 
> +++---
>  .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   |  2 +-
>  src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp |  8 ++---
>  .../drivers/nouveau/codegen/nv50_ir_target.cpp |  2 +-
>  .../drivers/nouveau/codegen/nv50_ir_target.h   |  2 +-
>  .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  8 ++---
>  10 files changed, 51 insertions(+), 48 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> index 76c815e..12a45fc 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> @@ -75,10 +75,13 @@ struct nv50_ir_prog_symbol
> uint32_t offset;
>  };
>
> -#define NVISA_SM30   0xe0
> -#define NVISA_SM35   0xea
> -#define NVISA_SM50   0x110

This is not a patch against upstream. If there's a sequence of
patches, you should post them together. If the patches are one logical
change, squash them.

> -
> +enum sm_isa {
> +  NVISA_SM10 = 0x84, //
> +  NVISA_SM20 = 0xc0, // Fermi
> +  NVISA_SM30 = 0xe0, // Keplar
> +  NVISA_SM35 = 0xea, // Keplar
> +  NVISA_SM50 = 0x110, // Maxwell

Leave the values to whatever the enum definition defaults them to.

> +};
>
>  struct nv50_ir_prog_info
>  {
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
> index cc2a88e..9620151 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
> @@ -635,7 +635,7 @@ CodeEmitterNV50::emitLOAD(const Instruction *i)
>   code[1] |= 0x0400;
>break;
> case FILE_MEMORY_SHARED:
> -  if (targ->getChipset() >= 0x84) {
> +  if (targ->getIsa() >= NVISA_SM10) {

Nope. This is to distinguish G80 from G84+. Leave the chipset check.

>   assert(offset <= (int32_t)(0x3fff * typeSizeof(i->sType)));
>   code[0] = 0x1001;
>   code[1] = 0x4000;
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> index ed29661..045e6e0 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> @@ -806,7 +806,7 @@ CodeEmitterNVC0::emitSHLADD(const Instruction *i)
>  void
>  CodeEmitterNVC0::emitMADSP(const Instruction *i)
>  {
> -   assert(targ->getChipset() >= NVISA_SM30);
> +   assert(targ->getIsa() >= NVISA_SM30);
>
> emitForm_A(i, HEX64(, 0003));
>
> @@ -1852,7 +1852,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
> case FILE_MEMORY_LOCAL:  opc = 0xc800; break;
> case FILE_MEMORY_SHARED:
>if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
> - if (targ->getChipset() >= NVISA_SM30)
> + if (targ->getIsa() >= NVISA_SM30)
>  opc = 0xb800;
>   else
>  opc = 0xcc00;
> @@ -1868,7 +1868,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
> code[0] = 0x0005;
> code[1] = opc;
>
> -   if (targ->getChipset() >= NVISA_SM30) {
> +   if (targ->getIsa() >= NVISA_SM30) {
>// Unlocked store on shared memory can fail.
>if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
>i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
> @@ -1901,7 +1901,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
> case FILE_MEMORY_LOCAL:  opc = 0xc000; break;
> case FILE_MEMORY_SHARED:
>if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
> - if (targ->getChipset() >= NVISA_SM30)
> + if (targ->getIsa() >= NVISA_SM30)
>  opc = 0xa800;
>   else
>  opc = 0xc400;
> @@ -1944,7 +1944,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
>code[0] |= 63 << 14;
>
> if (p >= 0) {
> -  if (targ->getChipset() >= NVISA_SM30)
> +  if (targ->getIsa() >= NVISA_SM30)
>   defId(i->def(p), 8);
>else
>   defId(i->def(p), 32 + 18);
> @@ -2362,7 +2362,7 @@ CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
>  void
>  CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
>  {
> -   assert(targ->getChipset() < NVISA_SM30);
> +   assert(targ->getIsa() < NVISA_SM30);
>
> if (i->tex.rIndir

[Mesa-dev] [PATCH] nv50/ir: Change chipset constants to ISA constants and #define to enum.

2017-04-12 Thread Matthew Mondazzi 
More relevant ISA constants put in place of chipset compares. This helps better 
display which features are available to card than previous chipset compares, 
making future development easier continue with.

Signed-off-by: Matthew Mondazzi 
---
 .../drivers/nouveau/codegen/nv50_ir_driver.h   | 11 ---
 .../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp  |  2 +-
 .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp  | 24 +++---
 .../nouveau/codegen/nv50_ir_lowering_nv50.cpp  |  2 +-
 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 38 +++---
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   |  2 +-
 src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp |  8 ++---
 .../drivers/nouveau/codegen/nv50_ir_target.cpp |  2 +-
 .../drivers/nouveau/codegen/nv50_ir_target.h   |  2 +-
 .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  8 ++---
 10 files changed, 51 insertions(+), 48 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 76c815e..12a45fc 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -75,10 +75,13 @@ struct nv50_ir_prog_symbol
uint32_t offset;
 };
 
-#define NVISA_SM30   0xe0
-#define NVISA_SM35   0xea
-#define NVISA_SM50   0x110
-
+enum sm_isa {
+  NVISA_SM10 = 0x84, // 
+  NVISA_SM20 = 0xc0, // Fermi
+  NVISA_SM30 = 0xe0, // Keplar
+  NVISA_SM35 = 0xea, // Keplar
+  NVISA_SM50 = 0x110, // Maxwell
+};
 
 struct nv50_ir_prog_info
 {
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
index cc2a88e..9620151 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
@@ -635,7 +635,7 @@ CodeEmitterNV50::emitLOAD(const Instruction *i)
  code[1] |= 0x0400;
   break;
case FILE_MEMORY_SHARED:
-  if (targ->getChipset() >= 0x84) {
+  if (targ->getIsa() >= NVISA_SM10) {
  assert(offset <= (int32_t)(0x3fff * typeSizeof(i->sType)));
  code[0] = 0x1001;
  code[1] = 0x4000;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index ed29661..045e6e0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -806,7 +806,7 @@ CodeEmitterNVC0::emitSHLADD(const Instruction *i)
 void
 CodeEmitterNVC0::emitMADSP(const Instruction *i)
 {
-   assert(targ->getChipset() >= NVISA_SM30);
+   assert(targ->getIsa() >= NVISA_SM30);
 
emitForm_A(i, HEX64(, 0003));
 
@@ -1852,7 +1852,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
case FILE_MEMORY_LOCAL:  opc = 0xc800; break;
case FILE_MEMORY_SHARED:
   if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
- if (targ->getChipset() >= NVISA_SM30)
+ if (targ->getIsa() >= NVISA_SM30)
 opc = 0xb800;
  else
 opc = 0xcc00;
@@ -1868,7 +1868,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
code[0] = 0x0005;
code[1] = opc;
 
-   if (targ->getChipset() >= NVISA_SM30) {
+   if (targ->getIsa() >= NVISA_SM30) {
   // Unlocked store on shared memory can fail.
   if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
   i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
@@ -1901,7 +1901,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
case FILE_MEMORY_LOCAL:  opc = 0xc000; break;
case FILE_MEMORY_SHARED:
   if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
- if (targ->getChipset() >= NVISA_SM30)
+ if (targ->getIsa() >= NVISA_SM30)
 opc = 0xa800;
  else
 opc = 0xc400;
@@ -1944,7 +1944,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
   code[0] |= 63 << 14;
 
if (p >= 0) {
-  if (targ->getChipset() >= NVISA_SM30)
+  if (targ->getIsa() >= NVISA_SM30)
  defId(i->def(p), 8);
   else
  defId(i->def(p), 32 + 18);
@@ -2362,7 +2362,7 @@ CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
 void
 CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
 {
-   assert(targ->getChipset() < NVISA_SM30);
+   assert(targ->getIsa() < NVISA_SM30);
 
if (i->tex.rIndirectSrc < 0) {
   code[1] |= 0x4000;
@@ -2375,7 +2375,7 @@ CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
 void
 CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
 {
-   assert(targ->getChipset() < NVISA_SM30);
+   assert(targ->getIsa() < NVISA_SM30);
 
code[1] |= (i->tex.target.getDim() - 1) << 12;
if (i->tex.target.isArray() || i->tex.target.isCube() ||
@@ -2390,7 +2390,7 @@ CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
 void
 CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
 {
-   assert(targ->getChipset() < NVISA_SM30);
+   a

Re: [Mesa-dev] [PATCH] nv50/ir: Change chipset constants to ISA constants.

2017-04-11 Thread Pierre Moreau 
I would agree with Ilia on making it an enum (maybe even an enum class?),
rather than a define.
If keeping it as a define, maybe we should also change the value while at it,
and have NVISA_SM30 equal 0x1d or 0x30 (or by numbering from 0 and on), rather
than keeping it linked to a chipset.

Pierre

On 01:03 am - Apr 11 2017, Samuel Pitoiset wrote:
> Karol told me that over IRC. Introducing ->getIsa() looks good to me.
> 
> On 04/11/2017 01:01 AM, Ilia Mirkin wrote:
> > I wanted to flip things over and use smxx notation...
> > 
> > On Apr 10, 2017 6:20 PM, "Samuel Pitoiset"  > > wrote:
> > 
> > Not sure why you get confused here. The chipset names are globally
> > consistent inside the codegen part and we never use SMxx. Maybe add
> > a comment like:
> > 
> > #define NVISA_GK104_CHIPSET0xe0 /* SM30 */
> > 
> > If you really need this?
> > 
> > On 04/10/2017 11:41 PM, Matthew Mondazzi wrote:
> > 
> > Define references to chipset did not actually use chipset,
> > leading to confusion. More relevant ISA constants put in place
> > of chipset compares.
> > 
> > Signed-off-by: Matthew Mondazzi  > >
> > ---
> >.../drivers/nouveau/codegen/nv50_ir_driver.h   |  7 ++--
> >.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp  | 24
> > +--
> >.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 46
> > +++---
> >.../nouveau/codegen/nv50_ir_target_nvc0.cpp|  6 +--
> >4 files changed, 42 insertions(+), 41 deletions(-)
> > 
> > diff --git
> > a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> > b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> > index e7d840d..76c815e 100644
> > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> > @@ -75,9 +75,10 @@ struct nv50_ir_prog_symbol
> >   uint32_t offset;
> >};
> >-#define NVISA_GK104_CHIPSET0xe0
> > -#define NVISA_GK20A_CHIPSET0xea
> > -#define NVISA_GM107_CHIPSET0x110
> > +#define NVISA_SM30   0xe0
> > +#define NVISA_SM35   0xea
> > +#define NVISA_SM50   0x110
> > +
> >  struct nv50_ir_prog_info
> >{
> > diff --git
> > a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> > b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> > index 5467447..ed29661 100644
> > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> > @@ -806,7 +806,7 @@ CodeEmitterNVC0::emitSHLADD(const
> > Instruction *i)
> >void
> >CodeEmitterNVC0::emitMADSP(const Instruction *i)
> >{
> > -   assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
> > +   assert(targ->getChipset() >= NVISA_SM30);
> > emitForm_A(i, HEX64(, 0003));
> >@@ -1852,7 +1852,7 @@ CodeEmitterNVC0::emitSTORE(const
> > Instruction *i)
> >   case FILE_MEMORY_LOCAL:  opc = 0xc800; break;
> >   case FILE_MEMORY_SHARED:
> >  if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
> > - if (targ->getChipset() >= NVISA_GK104_CHIPSET)
> > + if (targ->getChipset() >= NVISA_SM30)
> >opc = 0xb800;
> > else
> >opc = 0xcc00;
> > @@ -1868,7 +1868,7 @@ CodeEmitterNVC0::emitSTORE(const
> > Instruction *i)
> >   code[0] = 0x0005;
> >   code[1] = opc;
> >-   if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
> > +   if (targ->getChipset() >= NVISA_SM30) {
> >  // Unlocked store on shared memory can fail.
> >  if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
> >  i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
> > @@ -1901,7 +1901,7 @@ CodeEmitterNVC0::emitLOAD(const
> > Instruction *i)
> >   case FILE_MEMORY_LOCAL:  opc = 0xc000; break;
> >   case FILE_MEMORY_SHARED:
> >  if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
> > - if (targ->getChipset() >= NVISA_GK104_CHIPSET)
> > + if (targ->getChipset() >= NVISA_SM30)
> >opc = 0xa800;
> > else
> >opc = 0xc400;
> > @@ -1944,7 +1944,7 @@ CodeEmitterNVC0::emitLOAD(const
> > Instruction *i)
> >  code[0] |= 63 << 14;
> > if (p >= 0) {
> > -  if (targ->getChipset() >= NVISA_GK104_CHIPSET)
> >

Re: [Mesa-dev] [PATCH] nv50/ir: Change chipset constants to ISA constants.

2017-04-10 Thread Samuel Pitoiset 

Karol told me that over IRC. Introducing ->getIsa() looks good to me.

On 04/11/2017 01:01 AM, Ilia Mirkin wrote:

I wanted to flip things over and use smxx notation...

On Apr 10, 2017 6:20 PM, "Samuel Pitoiset" > wrote:


Not sure why you get confused here. The chipset names are globally
consistent inside the codegen part and we never use SMxx. Maybe add
a comment like:

#define NVISA_GK104_CHIPSET0xe0 /* SM30 */

If you really need this?

On 04/10/2017 11:41 PM, Matthew Mondazzi wrote:

Define references to chipset did not actually use chipset,
leading to confusion. More relevant ISA constants put in place
of chipset compares.

Signed-off-by: Matthew Mondazzi mailto:msmonda...@gmail.com>>
---
   .../drivers/nouveau/codegen/nv50_ir_driver.h   |  7 ++--
   .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp  | 24
+--
   .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 46
+++---
   .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  6 +--
   4 files changed, 42 insertions(+), 41 deletions(-)

diff --git
a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index e7d840d..76c815e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -75,9 +75,10 @@ struct nv50_ir_prog_symbol
  uint32_t offset;
   };
   -#define NVISA_GK104_CHIPSET0xe0
-#define NVISA_GK20A_CHIPSET0xea
-#define NVISA_GM107_CHIPSET0x110
+#define NVISA_SM30   0xe0
+#define NVISA_SM35   0xea
+#define NVISA_SM50   0x110
+
 struct nv50_ir_prog_info
   {
diff --git
a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 5467447..ed29661 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -806,7 +806,7 @@ CodeEmitterNVC0::emitSHLADD(const
Instruction *i)
   void
   CodeEmitterNVC0::emitMADSP(const Instruction *i)
   {
-   assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() >= NVISA_SM30);
emitForm_A(i, HEX64(, 0003));
   @@ -1852,7 +1852,7 @@ CodeEmitterNVC0::emitSTORE(const
Instruction *i)
  case FILE_MEMORY_LOCAL:  opc = 0xc800; break;
  case FILE_MEMORY_SHARED:
 if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
- if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+ if (targ->getChipset() >= NVISA_SM30)
   opc = 0xb800;
else
   opc = 0xcc00;
@@ -1868,7 +1868,7 @@ CodeEmitterNVC0::emitSTORE(const
Instruction *i)
  code[0] = 0x0005;
  code[1] = opc;
   -   if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
+   if (targ->getChipset() >= NVISA_SM30) {
 // Unlocked store on shared memory can fail.
 if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
 i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
@@ -1901,7 +1901,7 @@ CodeEmitterNVC0::emitLOAD(const
Instruction *i)
  case FILE_MEMORY_LOCAL:  opc = 0xc000; break;
  case FILE_MEMORY_SHARED:
 if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
- if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+ if (targ->getChipset() >= NVISA_SM30)
   opc = 0xa800;
else
   opc = 0xc400;
@@ -1944,7 +1944,7 @@ CodeEmitterNVC0::emitLOAD(const
Instruction *i)
 code[0] |= 63 << 14;
if (p >= 0) {
-  if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+  if (targ->getChipset() >= NVISA_SM30)
defId(i->def(p), 8);
 else
defId(i->def(p), 32 + 18);
@@ -2362,7 +2362,7 @@ CodeEmitterNVC0::emitSUSTGx(const
TexInstruction *i)
   void
   CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
   {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
if (i->tex.rIndirectSrc < 0) {
 code[1] |= 0x4000;
@@ -2375,7 +2375,7 @@ CodeEmitterNVC0::emitSUAddr(const
TexInstruction *i)
   void
   CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
   {
-   asser

Re: [Mesa-dev] [PATCH] nv50/ir: Change chipset constants to ISA constants.

2017-04-10 Thread Ilia Mirkin 
I wanted to flip things over and use smxx notation...

On Apr 10, 2017 6:20 PM, "Samuel Pitoiset" 
wrote:

> Not sure why you get confused here. The chipset names are globally
> consistent inside the codegen part and we never use SMxx. Maybe add a
> comment like:
>
> #define NVISA_GK104_CHIPSET0xe0 /* SM30 */
>
> If you really need this?
>
> On 04/10/2017 11:41 PM, Matthew Mondazzi wrote:
>
>> Define references to chipset did not actually use chipset, leading to
>> confusion. More relevant ISA constants put in place of chipset compares.
>>
>> Signed-off-by: Matthew Mondazzi 
>> ---
>>   .../drivers/nouveau/codegen/nv50_ir_driver.h   |  7 ++--
>>   .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp  | 24 +--
>>   .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 46
>> +++---
>>   .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  6 +--
>>   4 files changed, 42 insertions(+), 41 deletions(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
>> index e7d840d..76c815e 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
>> @@ -75,9 +75,10 @@ struct nv50_ir_prog_symbol
>>  uint32_t offset;
>>   };
>>   -#define NVISA_GK104_CHIPSET0xe0
>> -#define NVISA_GK20A_CHIPSET0xea
>> -#define NVISA_GM107_CHIPSET0x110
>> +#define NVISA_SM30   0xe0
>> +#define NVISA_SM35   0xea
>> +#define NVISA_SM50   0x110
>> +
>> struct nv50_ir_prog_info
>>   {
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> index 5467447..ed29661 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
>> @@ -806,7 +806,7 @@ CodeEmitterNVC0::emitSHLADD(const Instruction *i)
>>   void
>>   CodeEmitterNVC0::emitMADSP(const Instruction *i)
>>   {
>> -   assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
>> +   assert(targ->getChipset() >= NVISA_SM30);
>>emitForm_A(i, HEX64(, 0003));
>>   @@ -1852,7 +1852,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
>>  case FILE_MEMORY_LOCAL:  opc = 0xc800; break;
>>  case FILE_MEMORY_SHARED:
>> if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
>> - if (targ->getChipset() >= NVISA_GK104_CHIPSET)
>> + if (targ->getChipset() >= NVISA_SM30)
>>   opc = 0xb800;
>>else
>>   opc = 0xcc00;
>> @@ -1868,7 +1868,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
>>  code[0] = 0x0005;
>>  code[1] = opc;
>>   -   if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
>> +   if (targ->getChipset() >= NVISA_SM30) {
>> // Unlocked store on shared memory can fail.
>> if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
>> i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
>> @@ -1901,7 +1901,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
>>  case FILE_MEMORY_LOCAL:  opc = 0xc000; break;
>>  case FILE_MEMORY_SHARED:
>> if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
>> - if (targ->getChipset() >= NVISA_GK104_CHIPSET)
>> + if (targ->getChipset() >= NVISA_SM30)
>>   opc = 0xa800;
>>else
>>   opc = 0xc400;
>> @@ -1944,7 +1944,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
>> code[0] |= 63 << 14;
>>if (p >= 0) {
>> -  if (targ->getChipset() >= NVISA_GK104_CHIPSET)
>> +  if (targ->getChipset() >= NVISA_SM30)
>>defId(i->def(p), 8);
>> else
>>defId(i->def(p), 32 + 18);
>> @@ -2362,7 +2362,7 @@ CodeEmitterNVC0::emitSUSTGx(const TexInstruction
>> *i)
>>   void
>>   CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
>>   {
>> -   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
>> +   assert(targ->getChipset() < NVISA_SM30);
>>if (i->tex.rIndirectSrc < 0) {
>> code[1] |= 0x4000;
>> @@ -2375,7 +2375,7 @@ CodeEmitterNVC0::emitSUAddr(const TexInstruction
>> *i)
>>   void
>>   CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
>>   {
>> -   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
>> +   assert(targ->getChipset() < NVISA_SM30);
>>code[1] |= (i->tex.target.getDim() - 1) << 12;
>>  if (i->tex.target.isArray() || i->tex.target.isCube() ||
>> @@ -2390,7 +2390,7 @@ CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
>>   void
>>   CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
>>   {
>> -   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
>> +   assert(targ->getChipset() < NVISA_SM30);
>>code[0] = 0x5;
>>  code[1] = 0xf000;
>> @@ -2413,7 +2413,7 @@ CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
>>   void
>>   CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
>>   {
>> -   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
>> +   as

Re: [Mesa-dev] [PATCH] nv50/ir: Change chipset constants to ISA constants.

2017-04-10 Thread Samuel Pitoiset 
Not sure why you get confused here. The chipset names are globally 
consistent inside the codegen part and we never use SMxx. Maybe add a 
comment like:


#define NVISA_GK104_CHIPSET0xe0 /* SM30 */

If you really need this?

On 04/10/2017 11:41 PM, Matthew Mondazzi wrote:

Define references to chipset did not actually use chipset, leading to 
confusion. More relevant ISA constants put in place of chipset compares.

Signed-off-by: Matthew Mondazzi 
---
  .../drivers/nouveau/codegen/nv50_ir_driver.h   |  7 ++--
  .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp  | 24 +--
  .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 46 +++---
  .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  6 +--
  4 files changed, 42 insertions(+), 41 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index e7d840d..76c815e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -75,9 +75,10 @@ struct nv50_ir_prog_symbol
 uint32_t offset;
  };
  
-#define NVISA_GK104_CHIPSET0xe0

-#define NVISA_GK20A_CHIPSET0xea
-#define NVISA_GM107_CHIPSET0x110
+#define NVISA_SM30   0xe0
+#define NVISA_SM35   0xea
+#define NVISA_SM50   0x110
+
  
  struct nv50_ir_prog_info

  {
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 5467447..ed29661 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -806,7 +806,7 @@ CodeEmitterNVC0::emitSHLADD(const Instruction *i)
  void
  CodeEmitterNVC0::emitMADSP(const Instruction *i)
  {
-   assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() >= NVISA_SM30);
  
 emitForm_A(i, HEX64(, 0003));
  
@@ -1852,7 +1852,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)

 case FILE_MEMORY_LOCAL:  opc = 0xc800; break;
 case FILE_MEMORY_SHARED:
if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
- if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+ if (targ->getChipset() >= NVISA_SM30)
  opc = 0xb800;
   else
  opc = 0xcc00;
@@ -1868,7 +1868,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
 code[0] = 0x0005;
 code[1] = opc;
  
-   if (targ->getChipset() >= NVISA_GK104_CHIPSET) {

+   if (targ->getChipset() >= NVISA_SM30) {
// Unlocked store on shared memory can fail.
if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
@@ -1901,7 +1901,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
 case FILE_MEMORY_LOCAL:  opc = 0xc000; break;
 case FILE_MEMORY_SHARED:
if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
- if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+ if (targ->getChipset() >= NVISA_SM30)
  opc = 0xa800;
   else
  opc = 0xc400;
@@ -1944,7 +1944,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
code[0] |= 63 << 14;
  
 if (p >= 0) {

-  if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+  if (targ->getChipset() >= NVISA_SM30)
   defId(i->def(p), 8);
else
   defId(i->def(p), 32 + 18);
@@ -2362,7 +2362,7 @@ CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
  void
  CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
  {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
  
 if (i->tex.rIndirectSrc < 0) {

code[1] |= 0x4000;
@@ -2375,7 +2375,7 @@ CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
  void
  CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
  {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
  
 code[1] |= (i->tex.target.getDim() - 1) << 12;

 if (i->tex.target.isArray() || i->tex.target.isCube() ||
@@ -2390,7 +2390,7 @@ CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
  void
  CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
  {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
  
 code[0] = 0x5;

 code[1] = 0xf000;
@@ -2413,7 +2413,7 @@ CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
  void
  CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
  {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
  
 code[0] = 0x5;

 code[1] = 0xd400 | (i->subOp << 15);
@@ -2431,7 +2431,7 @@ CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
  void
  CodeEmitterNVC0::emitSUSTx(const TexInstruction *i)
  {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
  
 code[0] = 0x5;

 code[1] = 0xdc00 | (i->subOp << 15);
@@

[Mesa-dev] [PATCH] nv50/ir: Change chipset constants to ISA constants.

2017-04-10 Thread Matthew Mondazzi 
Define references to chipset did not actually use chipset, leading to 
confusion. More relevant ISA constants put in place of chipset compares.

Signed-off-by: Matthew Mondazzi 
---
 .../drivers/nouveau/codegen/nv50_ir_driver.h   |  7 ++--
 .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp  | 24 +--
 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp  | 46 +++---
 .../nouveau/codegen/nv50_ir_target_nvc0.cpp|  6 +--
 4 files changed, 42 insertions(+), 41 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index e7d840d..76c815e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -75,9 +75,10 @@ struct nv50_ir_prog_symbol
uint32_t offset;
 };
 
-#define NVISA_GK104_CHIPSET0xe0
-#define NVISA_GK20A_CHIPSET0xea
-#define NVISA_GM107_CHIPSET0x110
+#define NVISA_SM30   0xe0
+#define NVISA_SM35   0xea
+#define NVISA_SM50   0x110
+
 
 struct nv50_ir_prog_info
 {
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index 5467447..ed29661 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
@@ -806,7 +806,7 @@ CodeEmitterNVC0::emitSHLADD(const Instruction *i)
 void
 CodeEmitterNVC0::emitMADSP(const Instruction *i)
 {
-   assert(targ->getChipset() >= NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() >= NVISA_SM30);
 
emitForm_A(i, HEX64(, 0003));
 
@@ -1852,7 +1852,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
case FILE_MEMORY_LOCAL:  opc = 0xc800; break;
case FILE_MEMORY_SHARED:
   if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
- if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+ if (targ->getChipset() >= NVISA_SM30)
 opc = 0xb800;
  else
 opc = 0xcc00;
@@ -1868,7 +1868,7 @@ CodeEmitterNVC0::emitSTORE(const Instruction *i)
code[0] = 0x0005;
code[1] = opc;
 
-   if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
+   if (targ->getChipset() >= NVISA_SM30) {
   // Unlocked store on shared memory can fail.
   if (i->src(0).getFile() == FILE_MEMORY_SHARED &&
   i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
@@ -1901,7 +1901,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
case FILE_MEMORY_LOCAL:  opc = 0xc000; break;
case FILE_MEMORY_SHARED:
   if (i->subOp == NV50_IR_SUBOP_LOAD_LOCKED) {
- if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+ if (targ->getChipset() >= NVISA_SM30)
 opc = 0xa800;
  else
 opc = 0xc400;
@@ -1944,7 +1944,7 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
   code[0] |= 63 << 14;
 
if (p >= 0) {
-  if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+  if (targ->getChipset() >= NVISA_SM30)
  defId(i->def(p), 8);
   else
  defId(i->def(p), 32 + 18);
@@ -2362,7 +2362,7 @@ CodeEmitterNVC0::emitSUSTGx(const TexInstruction *i)
 void
 CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
 {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
 
if (i->tex.rIndirectSrc < 0) {
   code[1] |= 0x4000;
@@ -2375,7 +2375,7 @@ CodeEmitterNVC0::emitSUAddr(const TexInstruction *i)
 void
 CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
 {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
 
code[1] |= (i->tex.target.getDim() - 1) << 12;
if (i->tex.target.isArray() || i->tex.target.isCube() ||
@@ -2390,7 +2390,7 @@ CodeEmitterNVC0::emitSUDim(const TexInstruction *i)
 void
 CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
 {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
 
code[0] = 0x5;
code[1] = 0xf000;
@@ -2413,7 +2413,7 @@ CodeEmitterNVC0::emitSULEA(const TexInstruction *i)
 void
 CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
 {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
 
code[0] = 0x5;
code[1] = 0xd400 | (i->subOp << 15);
@@ -2431,7 +2431,7 @@ CodeEmitterNVC0::emitSULDB(const TexInstruction *i)
 void
 CodeEmitterNVC0::emitSUSTx(const TexInstruction *i)
 {
-   assert(targ->getChipset() < NVISA_GK104_CHIPSET);
+   assert(targ->getChipset() < NVISA_SM30);
 
code[0] = 0x5;
code[1] = 0xdc00 | (i->subOp << 15);
@@ -2751,14 +2751,14 @@ CodeEmitterNVC0::emitInstruction(Instruction *insn)
   emitMADSP(insn);
   break;
case OP_SULDB:
-  if (targ->getChipset() >= NVISA_GK104_CHIPSET)
+  if (targ->getChipset() >= NVISA_SM30)
  emitSULDGB(insn->asTex());
   else
  emitSULDB(insn->asTex());
   break;
case OP_SUSTB:
case OP