subject:"\[Mesa\-dev\] \[PATCH\] radeonsi\: implement RB\+ for Stoney \(v2\)"

Re: [Mesa-dev] [PATCH] radeonsi: implement RB+ for Stoney (v2)

2015-12-10 Thread Alex Deucher

On Wed, Dec 9, 2015 at 5:35 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> v2: fix dual source blending

Reviewed-by: Alex Deucher 

> ---
>  src/gallium/drivers/radeon/r600_pipe_common.c |   1 +
>  src/gallium/drivers/radeon/r600_pipe_common.h |   3 +
>  src/gallium/drivers/radeon/r600_texture.c |   6 +
>  src/gallium/drivers/radeonsi/si_state.c   | 159 
> +-
>  src/gallium/drivers/radeonsi/sid.h|   3 +
>  5 files changed, 170 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
> b/src/gallium/drivers/radeon/r600_pipe_common.c
> index 8899ba4..ba541ac 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -375,6 +375,7 @@ static const struct debug_named_value 
> common_debug_options[] = {
> { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
> { "nodcc", DBG_NO_DCC, "Disable DCC." },
> { "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
> +   { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
>
> DEBUG_NAMED_VALUE_END /* must be last */
>  };
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index 8c6c0c3..dd23ed5 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -86,6 +86,7 @@
>  #define DBG_CHECK_VM   (1llu << 42)
>  #define DBG_NO_DCC (1llu << 43)
>  #define DBG_NO_DCC_CLEAR   (1llu << 44)
> +#define DBG_NO_RB_PLUS (1llu << 45)
>
>  #define R600_MAP_BUFFER_ALIGNMENT 64
>
> @@ -250,6 +251,8 @@ struct r600_surface {
> unsigned cb_color_fmask_slice;  /* EG and later */
> unsigned cb_color_cmask;/* CB_COLORn_TILE (r600 only) */
> unsigned cb_color_mask; /* R600 only */
> +   unsigned sx_ps_downconvert; /* Stoney only */
> +   unsigned sx_blend_opt_epsilon;  /* Stoney only */
> struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. 
> R600 only */
> struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. 
> R600 only */
>
> diff --git a/src/gallium/drivers/radeon/r600_texture.c 
> b/src/gallium/drivers/radeon/r600_texture.c
> index 774722f..8c145e5 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -1393,6 +1393,7 @@ void evergreen_do_fast_color_clear(struct 
> r600_common_context *rctx,
> return;
>
> for (i = 0; i < fb->nr_cbufs; i++) {
> +   struct r600_surface *surf;
> struct r600_texture *tex;
> unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
>
> @@ -1403,6 +1404,7 @@ void evergreen_do_fast_color_clear(struct 
> r600_common_context *rctx,
> if (!(*buffers & clear_bit))
> continue;
>
> +   surf = (struct r600_surface *)fb->cbufs[i];
> tex = (struct r600_texture *)fb->cbufs[i]->texture;
>
> /* 128-bit formats are unusupported */
> @@ -1449,6 +1451,10 @@ void evergreen_do_fast_color_clear(struct 
> r600_common_context *rctx,
> if (clear_words_needed)
> tex->dirty_level_mask |= 1 << 
> fb->cbufs[i]->u.tex.level;
> } else {
> +   /* RB+ doesn't work with CMASK fast clear. */
> +   if (surf->sx_ps_downconvert)
> +   continue;
> +
> /* ensure CMASK is enabled */
> r600_texture_alloc_cmask_separate(rctx->screen, tex);
> if (tex->cmask.size == 0) {
> diff --git a/src/gallium/drivers/radeonsi/si_state.c 
> b/src/gallium/drivers/radeonsi/si_state.c
> index 2ebfa1c..dcf4a7b 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -347,10 +347,54 @@ static uint32_t si_translate_blend_factor(int 
> blend_fact)
> return 0;
>  }
>
> +static uint32_t si_translate_blend_opt_function(int blend_func)
> +{
> +   switch (blend_func) {
> +   case PIPE_BLEND_ADD:
> +   return V_028760_OPT_COMB_ADD;
> +   case PIPE_BLEND_SUBTRACT:
> +   return V_028760_OPT_COMB_SUBTRACT;
> +   case PIPE_BLEND_REVERSE_SUBTRACT:
> +   return V_028760_OPT_COMB_REVSUBTRACT;
> +   case PIPE_BLEND_MIN:
> +   return V_028760_OPT_COMB_MIN;
> +   case PIPE_BLEND_MAX:
> +   return V_028760_OPT_COMB_MAX;
> +   default:
> +   return V_028760_OPT_COMB_BLEND_DISABLED;
> +   }
> +}
> +
> +static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
> +{
> +   switch (blend_fact) {
> +   case PIPE_BLENDFACTOR_ZERO:
> +

[Mesa-dev] [PATCH] radeonsi: implement RB+ for Stoney (v2)

2015-12-09 Thread Marek Olšák

From: Marek Olšák 

v2: fix dual source blending
---
 src/gallium/drivers/radeon/r600_pipe_common.c |   1 +
 src/gallium/drivers/radeon/r600_pipe_common.h |   3 +
 src/gallium/drivers/radeon/r600_texture.c |   6 +
 src/gallium/drivers/radeonsi/si_state.c   | 159 +-
 src/gallium/drivers/radeonsi/sid.h|   3 +
 5 files changed, 170 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 8899ba4..ba541ac 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -375,6 +375,7 @@ static const struct debug_named_value 
common_debug_options[] = {
{ "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
{ "nodcc", DBG_NO_DCC, "Disable DCC." },
{ "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
+   { "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
 
DEBUG_NAMED_VALUE_END /* must be last */
 };
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 8c6c0c3..dd23ed5 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -86,6 +86,7 @@
 #define DBG_CHECK_VM   (1llu << 42)
 #define DBG_NO_DCC (1llu << 43)
 #define DBG_NO_DCC_CLEAR   (1llu << 44)
+#define DBG_NO_RB_PLUS (1llu << 45)
 
 #define R600_MAP_BUFFER_ALIGNMENT 64
 
@@ -250,6 +251,8 @@ struct r600_surface {
unsigned cb_color_fmask_slice;  /* EG and later */
unsigned cb_color_cmask;/* CB_COLORn_TILE (r600 only) */
unsigned cb_color_mask; /* R600 only */
+   unsigned sx_ps_downconvert; /* Stoney only */
+   unsigned sx_blend_opt_epsilon;  /* Stoney only */
struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. 
R600 only */
struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. 
R600 only */
 
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 774722f..8c145e5 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1393,6 +1393,7 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
return;
 
for (i = 0; i < fb->nr_cbufs; i++) {
+   struct r600_surface *surf;
struct r600_texture *tex;
unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
 
@@ -1403,6 +1404,7 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
if (!(*buffers & clear_bit))
continue;
 
+   surf = (struct r600_surface *)fb->cbufs[i];
tex = (struct r600_texture *)fb->cbufs[i]->texture;
 
/* 128-bit formats are unusupported */
@@ -1449,6 +1451,10 @@ void evergreen_do_fast_color_clear(struct 
r600_common_context *rctx,
if (clear_words_needed)
tex->dirty_level_mask |= 1 << 
fb->cbufs[i]->u.tex.level;
} else {
+   /* RB+ doesn't work with CMASK fast clear. */
+   if (surf->sx_ps_downconvert)
+   continue;
+
/* ensure CMASK is enabled */
r600_texture_alloc_cmask_separate(rctx->screen, tex);
if (tex->cmask.size == 0) {
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 2ebfa1c..dcf4a7b 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -347,10 +347,54 @@ static uint32_t si_translate_blend_factor(int blend_fact)
return 0;
 }
 
+static uint32_t si_translate_blend_opt_function(int blend_func)
+{
+   switch (blend_func) {
+   case PIPE_BLEND_ADD:
+   return V_028760_OPT_COMB_ADD;
+   case PIPE_BLEND_SUBTRACT:
+   return V_028760_OPT_COMB_SUBTRACT;
+   case PIPE_BLEND_REVERSE_SUBTRACT:
+   return V_028760_OPT_COMB_REVSUBTRACT;
+   case PIPE_BLEND_MIN:
+   return V_028760_OPT_COMB_MIN;
+   case PIPE_BLEND_MAX:
+   return V_028760_OPT_COMB_MAX;
+   default:
+   return V_028760_OPT_COMB_BLEND_DISABLED;
+   }
+}
+
+static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
+{
+   switch (blend_fact) {
+   case PIPE_BLENDFACTOR_ZERO:
+   return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
+   case PIPE_BLENDFACTOR_ONE:
+   return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
+   case PIPE_BLENDFACTOR_SRC_COLOR:
+   return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
+   :

Re: [Mesa-dev] [PATCH] radeonsi: implement RB+ for Stoney (v2)

[Mesa-dev] [PATCH] radeonsi: implement RB+ for Stoney (v2)

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