Re: [Mesa-dev] [PATCH 01/14] radeonsi/gfx9: make some PA & DB registers match the closed Vulkan driver

[Marek Olšák]

Ping

On Fri, Apr 28, 2017 at 11:42 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> Cc: 17.1 
> ---
>  src/amd/common/gfx9d.h  |  4 
>  src/gallium/drivers/radeonsi/si_state.c | 21 ++---
>  2 files changed, 22 insertions(+), 3 deletions(-)
>
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[Mesa-dev] [PATCH 01/14] radeonsi/gfx9: make some PA & DB registers match the closed Vulkan driver

[Marek Olšák]

From: Marek Olšák 

Cc: 17.1 
---
 src/amd/common/gfx9d.h  |  4 
 src/gallium/drivers/radeonsi/si_state.c | 21 ++---
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h
index e295a1d..787d0a9 100644
--- a/src/amd/common/gfx9d.h
+++ b/src/amd/common/gfx9d.h
@@ -4067,20 +4067,24 @@
 #define   C_028054_BASE_HI
0xFF00
 #define R_028058_DB_STENCIL_WRITE_BASE  
0x028058
 #define R_02805C_DB_STENCIL_WRITE_BASE_HI   
0x02805C
 #define   S_02805C_BASE_HI(x) 
(((unsigned)(x) & 0xFF) << 0)
 #define   G_02805C_BASE_HI(x) (((x) >> 
0) & 0xFF)
 #define   C_02805C_BASE_HI
0xFF00
 #define R_028060_DB_DFSM_CONTROL
0x028060
 #define   S_028060_PUNCHOUT_MODE(x)   
(((unsigned)(x) & 0x03) << 0)
 #define   G_028060_PUNCHOUT_MODE(x)   (((x) >> 
0) & 0x03)
 #define   C_028060_PUNCHOUT_MODE  
0xFFFC
+#define V_028060_AUTO  0
+#define V_028060_FORCE_ON  1
+#define V_028060_FORCE_OFF 2
+#define V_028060_RESERVED  3
 #define   S_028060_POPS_DRAIN_PS_ON_OVERLAP(x)
(((unsigned)(x) & 0x1) << 2)
 #define   G_028060_POPS_DRAIN_PS_ON_OVERLAP(x)(((x) >> 
2) & 0x1)
 #define   C_028060_POPS_DRAIN_PS_ON_OVERLAP   
0xFFFB
 #define   S_028060_DISALLOW_OVERFLOW(x)   
(((unsigned)(x) & 0x1) << 3)
 #define   G_028060_DISALLOW_OVERFLOW(x)   (((x) >> 
3) & 0x1)
 #define   C_028060_DISALLOW_OVERFLOW  
0xFFF7
 #define R_028064_DB_RENDER_FILTER   
0x028064
 #define   S_028064_PS_INVOKE_MASK(x)  
(((unsigned)(x) & 0x) << 0)
 #define   G_028064_PS_INVOKE_MASK(x)  (((x) >> 
0) & 0x)
 #define   C_028064_PS_INVOKE_MASK 
0x
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 938e7fb..17ac23e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4557,27 +4557,42 @@ static void si_init_config(struct si_context *sctx)
if (sctx->screen->b.has_rbplus)
si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
 
si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
if (sctx->b.chip_class >= CIK)
si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, 
border_color_va >> 40);
si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
  RADEON_PRIO_BORDER_COLORS);
 
if (sctx->b.chip_class >= GFX9) {
-   si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL, 0);
+   unsigned num_se = sscreen->b.info.max_se;
+   unsigned pc_lines = 0;
+
+   switch (sctx->b.family) {
+   case CHIP_VEGA10:
+   pc_lines = 4096;
+   break;
+   default:
+   assert(0);
+   }
+
+   si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
+  S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
/* TODO: We can use this to disable RBs for rendering to GART: 
*/
si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
/* TODO: Enable the binner: */
si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
-  
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC));
-   si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, 0);
+  
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
+  S_028C44_DISABLE_START_OF_PRIM(1));
+   si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
+  S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 
* num_se))) |
+  S_028C48_MAX_PRIM_PER_BATCH(1023));
si_pm4_set_reg(pm4, 
R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
   S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));