--- src/amd/common/ac_llvm_build.c | 1 + src/amd/common/ac_llvm_build.h | 1 + src/amd/common/ac_nir_to_llvm.c | 8 +++----- 3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 1a0d44bcdd..1519262b3d 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd/common/ac_llvm_build.c @@ -60,20 +60,21 @@ ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context, ctx->voidt = LLVMVoidTypeInContext(ctx->context); ctx->i1 = LLVMInt1TypeInContext(ctx->context); ctx->i8 = LLVMInt8TypeInContext(ctx->context); ctx->i16 = LLVMIntTypeInContext(ctx->context, 16); ctx->i32 = LLVMIntTypeInContext(ctx->context, 32); ctx->i64 = LLVMIntTypeInContext(ctx->context, 64); ctx->f16 = LLVMHalfTypeInContext(ctx->context); ctx->f32 = LLVMFloatTypeInContext(ctx->context); ctx->f64 = LLVMDoubleTypeInContext(ctx->context); ctx->v2i32 = LLVMVectorType(ctx->i32, 2); + ctx->v3i32 = LLVMVectorType(ctx->i32, 3); ctx->v4i32 = LLVMVectorType(ctx->i32, 4); ctx->v4f32 = LLVMVectorType(ctx->f32, 4); ctx->v8i32 = LLVMVectorType(ctx->i32, 8); ctx->i32_0 = LLVMConstInt(ctx->i32, 0, false); ctx->i32_1 = LLVMConstInt(ctx->i32, 1, false); ctx->f32_0 = LLVMConstReal(ctx->f32, 0.0); ctx->f32_1 = LLVMConstReal(ctx->f32, 1.0); ctx->i1false = LLVMConstInt(ctx->i1, 0, false); diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h index 7fc336c3f9..f662cc4dd8 100644 --- a/src/amd/common/ac_llvm_build.h +++ b/src/amd/common/ac_llvm_build.h @@ -46,20 +46,21 @@ struct ac_llvm_context { LLVMTypeRef voidt; LLVMTypeRef i1; LLVMTypeRef i8; LLVMTypeRef i16; LLVMTypeRef i32; LLVMTypeRef i64; LLVMTypeRef f16; LLVMTypeRef f32; LLVMTypeRef f64; LLVMTypeRef v2i32; + LLVMTypeRef v3i32; LLVMTypeRef v4i32; LLVMTypeRef v4f32; LLVMTypeRef v8i32; LLVMValueRef i32_0; LLVMValueRef i32_1; LLVMValueRef f32_0; LLVMValueRef f32_1; LLVMValueRef i1true; LLVMValueRef i1false; diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 0bcb0b0525..6a638e3f16 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -127,21 +127,20 @@ struct nir_to_llvm_context { LLVMValueRef esgs_ring; LLVMValueRef gsvs_ring; LLVMValueRef hs_ring_tess_offchip; LLVMValueRef hs_ring_tess_factor; LLVMValueRef prim_mask; LLVMValueRef sample_pos_offset; LLVMValueRef persp_sample, persp_center, persp_centroid; LLVMValueRef linear_sample, linear_center, linear_centroid; - LLVMTypeRef v3i32; LLVMTypeRef v4i32; LLVMTypeRef v8i32; LLVMTypeRef f64; LLVMTypeRef f32; LLVMTypeRef f16; LLVMTypeRef v2f32; LLVMTypeRef v4f32; unsigned uniform_md_kind; LLVMValueRef empty_md; @@ -727,23 +726,23 @@ static void create_function(struct nir_to_llvm_context *ctx, if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) { add_user_sgpr_argument(&args, const_array(ctx->v4i32, 16), &ctx->ring_offsets); /* address of rings */ } switch (stage) { case MESA_SHADER_COMPUTE: radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets); if (ctx->shader_info->info.cs.grid_components_used) add_user_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, ctx->shader_info->info.cs.grid_components_used), &ctx->num_work_groups); /* grid size */ - add_sgpr_argument(&args, LLVMVectorType(ctx->ac.i32, 3), &ctx->workgroup_ids); + add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids); add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size); - add_vgpr_argument(&args, LLVMVectorType(ctx->ac.i32, 3), &ctx->local_invocation_ids); + add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids); break; case MESA_SHADER_VERTEX: radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets); radv_define_vs_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &args); if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index)) add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->view_index); if (ctx->options->key.vs.as_es) add_sgpr_argument(&args, ctx->ac.i32, &ctx->es2gs_offset); // es2gs offset else if (ctx->options->key.vs.as_ls) add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->ls_out_layout); // ls out layout @@ -872,21 +871,21 @@ static void create_function(struct nir_to_llvm_context *ctx, } break; case MESA_SHADER_FRAGMENT: radv_define_common_user_sgprs_phase1(ctx, stage, has_previous_stage, previous_stage, &user_sgpr_info, &args, &desc_sets); if (ctx->shader_info->info.ps.needs_sample_positions) add_user_sgpr_argument(&args, ctx->ac.i32, &ctx->sample_pos_offset); /* sample position offset */ add_sgpr_argument(&args, ctx->ac.i32, &ctx->prim_mask); /* prim mask */ add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_sample); /* persp sample */ add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_center); /* persp center */ add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->persp_centroid); /* persp centroid */ - add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model */ + add_vgpr_argument(&args, ctx->ac.v3i32, NULL); /* persp pull model */ add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_sample); /* linear sample */ add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_center); /* linear center */ add_vgpr_argument(&args, ctx->ac.v2i32, &ctx->linear_centroid); /* linear centroid */ add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex */ add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /* pos x float */ add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /* pos y float */ add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /* pos z float */ add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /* pos w float */ add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.front_face); /* front face */ add_vgpr_argument(&args, ctx->ac.i32, &ctx->abi.ancillary); /* ancillary */ @@ -984,21 +983,20 @@ static void create_function(struct nir_to_llvm_context *ctx, break; default: unreachable("Shader stage not implemented"); } ctx->shader_info->num_user_sgprs = user_sgpr_idx; } static void setup_types(struct nir_to_llvm_context *ctx) { - ctx->v3i32 = LLVMVectorType(ctx->ac.i32, 3); ctx->v4i32 = LLVMVectorType(ctx->ac.i32, 4); ctx->v8i32 = LLVMVectorType(ctx->ac.i32, 8); ctx->f32 = LLVMFloatTypeInContext(ctx->context); ctx->f16 = LLVMHalfTypeInContext(ctx->context); ctx->f64 = LLVMDoubleTypeInContext(ctx->context); ctx->v2f32 = LLVMVectorType(ctx->f32, 2); ctx->v4f32 = LLVMVectorType(ctx->f32, 4); ctx->uniform_md_kind = LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14); -- 2.14.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev