Re: [Mesa-dev] [PATCH 02/15] i965/screen: Add basic support for rendering 10 bpc/depth 30 framebuffers. (v2)
On 10/10/2017 12:51 PM, Tapani Pälli wrote: On 10/06/2017 07:11 PM, Mario Kleiner wrote: Expose formats which are supported at least back to Gen 5 Ironlake, possibly further. Allow creation of 10 bpc winsys buffers for drawables. glxinfo now lists new RGBA 10 10 10 2/0 formats. Works correctly under DRI2 without compositing. v2: Move the BGRA/BGRX1010102 formats before the RGBA/RGBX 32 bit formats, as the code comments require. Thanks Emil! Update num_formats from 3 to 5, to keep the special Android handling intact. Signed-off-by: Mario Kleiner --- src/mesa/drivers/dri/i965/intel_screen.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 712cd40..9c0539d 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1567,7 +1567,13 @@ intelCreateBuffer(__DRIscreen *dri_screen, fb->Visual.samples = num_samples; } - if (mesaVis->redBits == 5) { + if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) { + rgbFormat = mesaVis->redMask == 0x3ff0 ? MESA_FORMAT_B10G10R10A2_UNORM + : MESA_FORMAT_R10G10B10A2_UNORM; + } else if (mesaVis->redBits == 10) { + rgbFormat = mesaVis->redMask == 0x3ff0 ? MESA_FORMAT_B10G10R10X2_UNORM + : MESA_FORMAT_R10G10B10X2_UNORM; + } else if (mesaVis->redBits == 5) { rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM : MESA_FORMAT_B5G6R5_UNORM; } else if (mesaVis->sRGBCapable) { @@ -1949,6 +1955,10 @@ intel_screen_make_configs(__DRIscreen *dri_screen) MESA_FORMAT_B8G8R8A8_UNORM, MESA_FORMAT_B8G8R8X8_UNORM, + /* For 10 bpc, 30 bit depth framebuffers. */ + MESA_FORMAT_B10G10R10A2_UNORM, + MESA_FORMAT_B10G10R10X2_UNORM, + /* The 32-bit RGBA format must not precede the 32-bit BGRA format. * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX * server may disagree on which format the GLXFBConfig represents, @@ -1988,7 +1998,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING)) num_formats = ARRAY_SIZE(formats); else - num_formats = 3; + num_formats = 5; How about following: num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */ (I'm suggesting it here https://patchwork.freedesktop.org/patch/177410/) Not a big deal though, with or without this patch looks correct. Reviewed-by: Tapani Pälli // Tapani Good idea. I've changed that patch accordingly. Thanks for the review. -mario ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 02/15] i965/screen: Add basic support for rendering 10 bpc/depth 30 framebuffers. (v2)
On 10/06/2017 07:11 PM, Mario Kleiner wrote: Expose formats which are supported at least back to Gen 5 Ironlake, possibly further. Allow creation of 10 bpc winsys buffers for drawables. glxinfo now lists new RGBA 10 10 10 2/0 formats. Works correctly under DRI2 without compositing. v2: Move the BGRA/BGRX1010102 formats before the RGBA/RGBX 32 bit formats, as the code comments require. Thanks Emil! Update num_formats from 3 to 5, to keep the special Android handling intact. Signed-off-by: Mario Kleiner --- src/mesa/drivers/dri/i965/intel_screen.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 712cd40..9c0539d 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1567,7 +1567,13 @@ intelCreateBuffer(__DRIscreen *dri_screen, fb->Visual.samples = num_samples; } - if (mesaVis->redBits == 5) { + if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) { + rgbFormat = mesaVis->redMask == 0x3ff0 ? MESA_FORMAT_B10G10R10A2_UNORM + : MESA_FORMAT_R10G10B10A2_UNORM; + } else if (mesaVis->redBits == 10) { + rgbFormat = mesaVis->redMask == 0x3ff0 ? MESA_FORMAT_B10G10R10X2_UNORM + : MESA_FORMAT_R10G10B10X2_UNORM; + } else if (mesaVis->redBits == 5) { rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM : MESA_FORMAT_B5G6R5_UNORM; } else if (mesaVis->sRGBCapable) { @@ -1949,6 +1955,10 @@ intel_screen_make_configs(__DRIscreen *dri_screen) MESA_FORMAT_B8G8R8A8_UNORM, MESA_FORMAT_B8G8R8X8_UNORM, + /* For 10 bpc, 30 bit depth framebuffers. */ + MESA_FORMAT_B10G10R10A2_UNORM, + MESA_FORMAT_B10G10R10X2_UNORM, + /* The 32-bit RGBA format must not precede the 32-bit BGRA format. * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX * server may disagree on which format the GLXFBConfig represents, @@ -1988,7 +1998,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING)) num_formats = ARRAY_SIZE(formats); else - num_formats = 3; + num_formats = 5; How about following: num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */ (I'm suggesting it here https://patchwork.freedesktop.org/patch/177410/) Not a big deal though, with or without this patch looks correct. Reviewed-by: Tapani Pälli // Tapani ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 02/15] i965/screen: Add basic support for rendering 10 bpc/depth 30 framebuffers. (v2)
Expose formats which are supported at least back to Gen 5 Ironlake, possibly further. Allow creation of 10 bpc winsys buffers for drawables. glxinfo now lists new RGBA 10 10 10 2/0 formats. Works correctly under DRI2 without compositing. v2: Move the BGRA/BGRX1010102 formats before the RGBA/RGBX 32 bit formats, as the code comments require. Thanks Emil! Update num_formats from 3 to 5, to keep the special Android handling intact. Signed-off-by: Mario Kleiner --- src/mesa/drivers/dri/i965/intel_screen.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 712cd40..9c0539d 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1567,7 +1567,13 @@ intelCreateBuffer(__DRIscreen *dri_screen, fb->Visual.samples = num_samples; } - if (mesaVis->redBits == 5) { + if (mesaVis->redBits == 10 && mesaVis->alphaBits > 0) { + rgbFormat = mesaVis->redMask == 0x3ff0 ? MESA_FORMAT_B10G10R10A2_UNORM + : MESA_FORMAT_R10G10B10A2_UNORM; + } else if (mesaVis->redBits == 10) { + rgbFormat = mesaVis->redMask == 0x3ff0 ? MESA_FORMAT_B10G10R10X2_UNORM + : MESA_FORMAT_R10G10B10X2_UNORM; + } else if (mesaVis->redBits == 5) { rgbFormat = mesaVis->redMask == 0x1f ? MESA_FORMAT_R5G6B5_UNORM : MESA_FORMAT_B5G6R5_UNORM; } else if (mesaVis->sRGBCapable) { @@ -1949,6 +1955,10 @@ intel_screen_make_configs(__DRIscreen *dri_screen) MESA_FORMAT_B8G8R8A8_UNORM, MESA_FORMAT_B8G8R8X8_UNORM, + /* For 10 bpc, 30 bit depth framebuffers. */ + MESA_FORMAT_B10G10R10A2_UNORM, + MESA_FORMAT_B10G10R10X2_UNORM, + /* The 32-bit RGBA format must not precede the 32-bit BGRA format. * Likewise for RGBX and BGRX. Otherwise, the GLX client and the GLX * server may disagree on which format the GLXFBConfig represents, @@ -1988,7 +1998,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING)) num_formats = ARRAY_SIZE(formats); else - num_formats = 3; + num_formats = 5; /* Generate singlesample configs without accumulation buffer. */ for (unsigned i = 0; i < num_formats; i++) { -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev