Re: [Mesa-dev] [PATCH 02/22] i965/miptree: Switch to isl_surf::samples

2017-07-19 Thread Pohjolainen, Topi 
On Wed, Jul 19, 2017 at 01:26:03PM +0300, Pohjolainen, Topi wrote:
> On Tue, Jul 18, 2017 at 01:29:39PM -0700, Jason Ekstrand wrote:
> > On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
> > topi.pohjolai...@gmail.com> wrote:
> > 
> > > Signed-off-by: Topi Pohjolainen 
> > > ---
> > >  src/mesa/drivers/dri/i965/brw_blorp.c| 16 -
> > >  src/mesa/drivers/dri/i965/brw_context.c  |  2 +-
> > >  src/mesa/drivers/dri/i965/brw_meta_util.c|  2 +-
> > >  src/mesa/drivers/dri/i965/brw_tex_layout.c   |  4 +--
> > >  src/mesa/drivers/dri/i965/brw_wm.c   |  4 +--
> > >  src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
> > >  src/mesa/drivers/dri/i965/intel_blit.c   |  4 +--
> > >  src/mesa/drivers/dri/i965/intel_fbo.c|  4 +--
> > >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 46
> > > 
> > >  src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  6 
> > >  src/mesa/drivers/dri/i965/intel_pixel_copy.c |  2 +-
> > >  11 files changed, 43 insertions(+), 49 deletions(-)
> > >
> > > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> > > b/src/mesa/drivers/dri/i965/brw_blorp.c
> > > index be310de85b..be0d41b04a 100644
> > > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > > @@ -135,7 +135,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
> > > struct isl_surf tmp_surfs[1])
> > >  {
> > > if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
> > > -  const unsigned num_samples = MAX2(1, mt->num_samples);
> > > +  const unsigned num_samples = MAX2(1, mt->surf.samples);
> > >for (unsigned i = 0; i < num_layers; i++) {
> > >   for (unsigned s = 0; s < num_samples; s++) {
> > >  const unsigned phys_layer = (start_layer + i) * num_samples +
> > > s;
> > > @@ -275,7 +275,7 @@ swizzle_to_scs(GLenum swizzle)
> > >   * Note: if the src (or dst) is a 2D multisample array texture on Gen7+
> > > using
> > >   * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer)
> > > is
> > >   * the physical layer holding sample 0.  So, for example, if
> > > - * src_mt->num_samples == 4, then logical layer n corresponds to
> > > src_layer ==
> > > + * src_mt->surf.samples == 4, then logical layer n corresponds to
> > > src_layer ==
> > >   * 4*n.
> > >   */
> > >  void
> > > @@ -296,9 +296,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> > > DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
> > > "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
> > > __func__,
> > > -   src_mt->num_samples, _mesa_get_format_name(src_mt->format),
> > > src_mt,
> > > +   src_mt->surf.samples, _mesa_get_format_name(src_mt->format),
> > > src_mt,
> > > src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
> > > -   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format),
> > > dst_mt,
> > > +   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format),
> > > dst_mt,
> > > dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
> > > mirror_x, mirror_y);
> > >
> > > @@ -318,7 +318,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> > >  * R32_FLOAT, so only the contents of the red channel matters.
> > >  */
> > > if (brw->gen == 6 &&
> > > -   src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
> > > +   src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1 &&
> > > src_mt->format == dst_mt->format &&
> > > (dst_format == MESA_FORMAT_L_FLOAT32 ||
> > >  dst_format == MESA_FORMAT_I_FLOAT32)) {
> > > @@ -375,9 +375,9 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
> > > DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
> > > "to %dx %s mt %p %d %d (%d,%d)\n",
> > > __func__,
> > > -   src_mt->num_samples, _mesa_get_format_name(src_mt->format),
> > > src_mt,
> > > +   src_mt->surf.samples, _mesa_get_format_name(src_mt->format),
> > > src_mt,
> > > src_level, src_layer, src_x, src_y, src_width, src_height,
> > > -   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format),
> > > dst_mt,
> > > +   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format),
> > > dst_mt,
> > > dst_level, dst_layer, dst_x, dst_y);
> > >
> > > struct isl_surf tmp_surfs[2];
> > > @@ -564,7 +564,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
> > > struct intel_mipmap_tree *dst_mt = intel_image->mt;
> > >
> > > /* There is support for only up to eight samples. */
> > > -   if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
> > > +   if (src_mt->surf.samples > 8 || dst_mt->surf.samples > 8)
> > >return false;
> > >
> > > if (_mesa_get_format_base_format(src_rb->Format) !=
> > > diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> > > b/src/mesa/drivers/dri/i965/brw_context.c
> > > index bd26e2332c..fffe310b97 100644
> > > --- a/src/mes

Re: [Mesa-dev] [PATCH 02/22] i965/miptree: Switch to isl_surf::samples

2017-07-19 Thread Pohjolainen, Topi 
On Tue, Jul 18, 2017 at 01:29:39PM -0700, Jason Ekstrand wrote:
> On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
> topi.pohjolai...@gmail.com> wrote:
> 
> > Signed-off-by: Topi Pohjolainen 
> > ---
> >  src/mesa/drivers/dri/i965/brw_blorp.c| 16 -
> >  src/mesa/drivers/dri/i965/brw_context.c  |  2 +-
> >  src/mesa/drivers/dri/i965/brw_meta_util.c|  2 +-
> >  src/mesa/drivers/dri/i965/brw_tex_layout.c   |  4 +--
> >  src/mesa/drivers/dri/i965/brw_wm.c   |  4 +--
> >  src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
> >  src/mesa/drivers/dri/i965/intel_blit.c   |  4 +--
> >  src/mesa/drivers/dri/i965/intel_fbo.c|  4 +--
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 46
> > 
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  6 
> >  src/mesa/drivers/dri/i965/intel_pixel_copy.c |  2 +-
> >  11 files changed, 43 insertions(+), 49 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> > b/src/mesa/drivers/dri/i965/brw_blorp.c
> > index be310de85b..be0d41b04a 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > @@ -135,7 +135,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
> > struct isl_surf tmp_surfs[1])
> >  {
> > if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
> > -  const unsigned num_samples = MAX2(1, mt->num_samples);
> > +  const unsigned num_samples = MAX2(1, mt->surf.samples);
> >for (unsigned i = 0; i < num_layers; i++) {
> >   for (unsigned s = 0; s < num_samples; s++) {
> >  const unsigned phys_layer = (start_layer + i) * num_samples +
> > s;
> > @@ -275,7 +275,7 @@ swizzle_to_scs(GLenum swizzle)
> >   * Note: if the src (or dst) is a 2D multisample array texture on Gen7+
> > using
> >   * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer)
> > is
> >   * the physical layer holding sample 0.  So, for example, if
> > - * src_mt->num_samples == 4, then logical layer n corresponds to
> > src_layer ==
> > + * src_mt->surf.samples == 4, then logical layer n corresponds to
> > src_layer ==
> >   * 4*n.
> >   */
> >  void
> > @@ -296,9 +296,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> > DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
> > "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
> > __func__,
> > -   src_mt->num_samples, _mesa_get_format_name(src_mt->format),
> > src_mt,
> > +   src_mt->surf.samples, _mesa_get_format_name(src_mt->format),
> > src_mt,
> > src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
> > -   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format),
> > dst_mt,
> > +   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format),
> > dst_mt,
> > dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
> > mirror_x, mirror_y);
> >
> > @@ -318,7 +318,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> >  * R32_FLOAT, so only the contents of the red channel matters.
> >  */
> > if (brw->gen == 6 &&
> > -   src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
> > +   src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1 &&
> > src_mt->format == dst_mt->format &&
> > (dst_format == MESA_FORMAT_L_FLOAT32 ||
> >  dst_format == MESA_FORMAT_I_FLOAT32)) {
> > @@ -375,9 +375,9 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
> > DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
> > "to %dx %s mt %p %d %d (%d,%d)\n",
> > __func__,
> > -   src_mt->num_samples, _mesa_get_format_name(src_mt->format),
> > src_mt,
> > +   src_mt->surf.samples, _mesa_get_format_name(src_mt->format),
> > src_mt,
> > src_level, src_layer, src_x, src_y, src_width, src_height,
> > -   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format),
> > dst_mt,
> > +   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format),
> > dst_mt,
> > dst_level, dst_layer, dst_x, dst_y);
> >
> > struct isl_surf tmp_surfs[2];
> > @@ -564,7 +564,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
> > struct intel_mipmap_tree *dst_mt = intel_image->mt;
> >
> > /* There is support for only up to eight samples. */
> > -   if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
> > +   if (src_mt->surf.samples > 8 || dst_mt->surf.samples > 8)
> >return false;
> >
> > if (_mesa_get_format_base_format(src_rb->Format) !=
> > diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> > b/src/mesa/drivers/dri/i965/brw_context.c
> > index bd26e2332c..fffe310b97 100644
> > --- a/src/mesa/drivers/dri/i965/brw_context.c
> > +++ b/src/mesa/drivers/dri/i965/brw_context.c
> > @@ -1218,7 +1218,7 @@ intel_resolve_for_dri2_flush(struct brw_context
> > *brw,
> >rb = intel_get_renderbuffer(fb, buffers[i]);
> >if (rb == NULL || rb->mt == NULL)
> >

Re: [Mesa-dev] [PATCH 02/22] i965/miptree: Switch to isl_surf::samples

2017-07-18 Thread Jason Ekstrand 
On Tue, Jul 18, 2017 at 1:46 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:

> Signed-off-by: Topi Pohjolainen 
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c| 16 -
>  src/mesa/drivers/dri/i965/brw_context.c  |  2 +-
>  src/mesa/drivers/dri/i965/brw_meta_util.c|  2 +-
>  src/mesa/drivers/dri/i965/brw_tex_layout.c   |  4 +--
>  src/mesa/drivers/dri/i965/brw_wm.c   |  4 +--
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
>  src/mesa/drivers/dri/i965/intel_blit.c   |  4 +--
>  src/mesa/drivers/dri/i965/intel_fbo.c|  4 +--
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 46
> 
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  6 
>  src/mesa/drivers/dri/i965/intel_pixel_copy.c |  2 +-
>  11 files changed, 43 insertions(+), 49 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index be310de85b..be0d41b04a 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -135,7 +135,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
> struct isl_surf tmp_surfs[1])
>  {
> if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
> -  const unsigned num_samples = MAX2(1, mt->num_samples);
> +  const unsigned num_samples = MAX2(1, mt->surf.samples);
>for (unsigned i = 0; i < num_layers; i++) {
>   for (unsigned s = 0; s < num_samples; s++) {
>  const unsigned phys_layer = (start_layer + i) * num_samples +
> s;
> @@ -275,7 +275,7 @@ swizzle_to_scs(GLenum swizzle)
>   * Note: if the src (or dst) is a 2D multisample array texture on Gen7+
> using
>   * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer)
> is
>   * the physical layer holding sample 0.  So, for example, if
> - * src_mt->num_samples == 4, then logical layer n corresponds to
> src_layer ==
> + * src_mt->surf.samples == 4, then logical layer n corresponds to
> src_layer ==
>   * 4*n.
>   */
>  void
> @@ -296,9 +296,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
> "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
> __func__,
> -   src_mt->num_samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> +   src_mt->surf.samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
> -   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> +   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
> mirror_x, mirror_y);
>
> @@ -318,7 +318,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
>  * R32_FLOAT, so only the contents of the red channel matters.
>  */
> if (brw->gen == 6 &&
> -   src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
> +   src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1 &&
> src_mt->format == dst_mt->format &&
> (dst_format == MESA_FORMAT_L_FLOAT32 ||
>  dst_format == MESA_FORMAT_I_FLOAT32)) {
> @@ -375,9 +375,9 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
> DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
> "to %dx %s mt %p %d %d (%d,%d)\n",
> __func__,
> -   src_mt->num_samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> +   src_mt->surf.samples, _mesa_get_format_name(src_mt->format),
> src_mt,
> src_level, src_layer, src_x, src_y, src_width, src_height,
> -   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> +   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format),
> dst_mt,
> dst_level, dst_layer, dst_x, dst_y);
>
> struct isl_surf tmp_surfs[2];
> @@ -564,7 +564,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
> struct intel_mipmap_tree *dst_mt = intel_image->mt;
>
> /* There is support for only up to eight samples. */
> -   if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
> +   if (src_mt->surf.samples > 8 || dst_mt->surf.samples > 8)
>return false;
>
> if (_mesa_get_format_base_format(src_rb->Format) !=
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> index bd26e2332c..fffe310b97 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -1218,7 +1218,7 @@ intel_resolve_for_dri2_flush(struct brw_context
> *brw,
>rb = intel_get_renderbuffer(fb, buffers[i]);
>if (rb == NULL || rb->mt == NULL)
>   continue;
> -  if (rb->mt->num_samples <= 1) {
> +  if (rb->mt->surf.samples <= 1) {
>   assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
>  rb->layer_count == 1);
>   intel_miptree_prepare_access(brw, rb->mt, 0, 1, 0, 1, false

[Mesa-dev] [PATCH 02/22] i965/miptree: Switch to isl_surf::samples

2017-07-18 Thread Topi Pohjolainen 
Signed-off-by: Topi Pohjolainen 
---
 src/mesa/drivers/dri/i965/brw_blorp.c| 16 -
 src/mesa/drivers/dri/i965/brw_context.c  |  2 +-
 src/mesa/drivers/dri/i965/brw_meta_util.c|  2 +-
 src/mesa/drivers/dri/i965/brw_tex_layout.c   |  4 +--
 src/mesa/drivers/dri/i965/brw_wm.c   |  4 +--
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  2 +-
 src/mesa/drivers/dri/i965/intel_blit.c   |  4 +--
 src/mesa/drivers/dri/i965/intel_fbo.c|  4 +--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 46 
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  6 
 src/mesa/drivers/dri/i965/intel_pixel_copy.c |  2 +-
 11 files changed, 43 insertions(+), 49 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index be310de85b..be0d41b04a 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -135,7 +135,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
struct isl_surf tmp_surfs[1])
 {
if (mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY) {
-  const unsigned num_samples = MAX2(1, mt->num_samples);
+  const unsigned num_samples = MAX2(1, mt->surf.samples);
   for (unsigned i = 0; i < num_layers; i++) {
  for (unsigned s = 0; s < num_samples; s++) {
 const unsigned phys_layer = (start_layer + i) * num_samples + s;
@@ -275,7 +275,7 @@ swizzle_to_scs(GLenum swizzle)
  * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
  * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
  * the physical layer holding sample 0.  So, for example, if
- * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
+ * src_mt->surf.samples == 4, then logical layer n corresponds to src_layer ==
  * 4*n.
  */
 void
@@ -296,9 +296,9 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
"to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
__func__,
-   src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
+   src_mt->surf.samples, _mesa_get_format_name(src_mt->format), src_mt,
src_level, src_layer, src_x0, src_y0, src_x1, src_y1,
-   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
+   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format), dst_mt,
dst_level, dst_layer, dst_x0, dst_y0, dst_x1, dst_y1,
mirror_x, mirror_y);
 
@@ -318,7 +318,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
 * R32_FLOAT, so only the contents of the red channel matters.
 */
if (brw->gen == 6 &&
-   src_mt->num_samples > 1 && dst_mt->num_samples <= 1 &&
+   src_mt->surf.samples > 1 && dst_mt->surf.samples <= 1 &&
src_mt->format == dst_mt->format &&
(dst_format == MESA_FORMAT_L_FLOAT32 ||
 dst_format == MESA_FORMAT_I_FLOAT32)) {
@@ -375,9 +375,9 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
DBG("%s from %dx %s mt %p %d %d (%d,%d) %dx%d"
"to %dx %s mt %p %d %d (%d,%d)\n",
__func__,
-   src_mt->num_samples, _mesa_get_format_name(src_mt->format), src_mt,
+   src_mt->surf.samples, _mesa_get_format_name(src_mt->format), src_mt,
src_level, src_layer, src_x, src_y, src_width, src_height,
-   dst_mt->num_samples, _mesa_get_format_name(dst_mt->format), dst_mt,
+   dst_mt->surf.samples, _mesa_get_format_name(dst_mt->format), dst_mt,
dst_level, dst_layer, dst_x, dst_y);
 
struct isl_surf tmp_surfs[2];
@@ -564,7 +564,7 @@ brw_blorp_copytexsubimage(struct brw_context *brw,
struct intel_mipmap_tree *dst_mt = intel_image->mt;
 
/* There is support for only up to eight samples. */
-   if (src_mt->num_samples > 8 || dst_mt->num_samples > 8)
+   if (src_mt->surf.samples > 8 || dst_mt->surf.samples > 8)
   return false;
 
if (_mesa_get_format_base_format(src_rb->Format) !=
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index bd26e2332c..fffe310b97 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1218,7 +1218,7 @@ intel_resolve_for_dri2_flush(struct brw_context *brw,
   rb = intel_get_renderbuffer(fb, buffers[i]);
   if (rb == NULL || rb->mt == NULL)
  continue;
-  if (rb->mt->num_samples <= 1) {
+  if (rb->mt->surf.samples <= 1) {
  assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
 rb->layer_count == 1);
  intel_miptree_prepare_access(brw, rb->mt, 0, 1, 0, 1, false, false);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
b/src/mesa/drivers/dri/i965/brw_meta_util.c
index f9fd350918..2d87885e90 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -298,7 +298,7 @@ brw_is_color_fast_clear_compatibl