Re: [Mesa-dev] [PATCH 03/17] intel: Disable 64-bit extensions on platforms without 64-bit types

2018-02-22 Thread Iago Toral 
On Wed, 2018-02-21 at 09:33 -0800, Matt Turner wrote:
> On Wed, Feb 21, 2018 at 2:05 AM, Iago Toral 
> wrote:
> > On Tue, 2018-02-20 at 21:15 -0800, Matt Turner wrote:
> > > Gen11 does not support DF, Q, UQ types in hardware. As a result,
> > > we
> > > have
> > > to disable some GL extensions until they can be reimplemented.
> > > ---
> > >  src/intel/common/gen_device_info.c   | 3 +++
> > >  src/intel/common/gen_device_info.h   | 1 +
> > >  src/mesa/drivers/dri/i965/intel_extensions.c | 9 +
> > >  3 files changed, 9 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/src/intel/common/gen_device_info.c
> > > b/src/intel/common/gen_device_info.c
> > > index 8bf4b6b9bb0..465d4c783a1 100644
> > > --- a/src/intel/common/gen_device_info.c
> > > +++ b/src/intel/common/gen_device_info.c
> > > @@ -138,6 +138,7 @@ static const struct gen_device_info
> > > gen_device_info_snb_gt2 = {
> > > .must_use_separate_stencil = true,   \
> > > .has_llc = true, \
> > > .has_pln = true, \
> > > +   .has_64bit_types = true, \
> > > .has_surface_tile_offset = true, \
> > > .timestamp_frequency = 1250
> > > 
> > > @@ -322,6 +323,7 @@ static const struct gen_device_info
> > > gen_device_info_hsw_gt3 = {
> > > .has_llc = true, \
> > > .has_sample_with_hiz = false,\
> > > .has_pln = true, \
> > > +   .has_64bit_types = true, \
> > > .supports_simd16_3src = true,\
> > > .has_surface_tile_offset = true, \
> > > .max_vs_threads = 504,   \
> > > @@ -756,6 +758,7 @@ static const struct gen_device_info
> > > gen_device_info_cnl_5x8 = {
> > >  #define GEN11_FEATURES(_gt, _slices, _l3)   \
> > > GEN8_FEATURES,   \
> > > GEN11_HW_INFO,   \
> > > +   .has_64bit_types = false,@@ -322,6 +323,7 @@
> > > static
> > > const struct gen_device_info gen_device_info_hsw_gt3 = {
> > > \
> > > .gt = _gt, .num_slices = _slices, .l3_banks = _l3
> > 
> > This seems to only enable 64-bit types on snb_gt2 and hsw_gt3, what
> > about bdw+ platforms? or ivybridge where we also support fp64?
> 
> Sorry, I should have sent the diff with more context. git diff's
> context lines are useless, since we're modifying macros here:
> GEN7_FEATURES, GEN8_FEATURES, and GEN11_FEATURES (which includes
> GEN8_FEATURES).

Ah, that makes more sense, thanks!

This patch is:
Reviewed-by: Iago Toral Quiroga 

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Re: [Mesa-dev] [PATCH 03/17] intel: Disable 64-bit extensions on platforms without 64-bit types

2018-02-21 Thread Matt Turner 
On Wed, Feb 21, 2018 at 2:05 AM, Iago Toral  wrote:
> On Tue, 2018-02-20 at 21:15 -0800, Matt Turner wrote:
>> Gen11 does not support DF, Q, UQ types in hardware. As a result, we
>> have
>> to disable some GL extensions until they can be reimplemented.
>> ---
>>  src/intel/common/gen_device_info.c   | 3 +++
>>  src/intel/common/gen_device_info.h   | 1 +
>>  src/mesa/drivers/dri/i965/intel_extensions.c | 9 +
>>  3 files changed, 9 insertions(+), 4 deletions(-)
>>
>> diff --git a/src/intel/common/gen_device_info.c
>> b/src/intel/common/gen_device_info.c
>> index 8bf4b6b9bb0..465d4c783a1 100644
>> --- a/src/intel/common/gen_device_info.c
>> +++ b/src/intel/common/gen_device_info.c
>> @@ -138,6 +138,7 @@ static const struct gen_device_info
>> gen_device_info_snb_gt2 = {
>> .must_use_separate_stencil = true,   \
>> .has_llc = true, \
>> .has_pln = true, \
>> +   .has_64bit_types = true, \
>> .has_surface_tile_offset = true, \
>> .timestamp_frequency = 1250
>>
>> @@ -322,6 +323,7 @@ static const struct gen_device_info
>> gen_device_info_hsw_gt3 = {
>> .has_llc = true, \
>> .has_sample_with_hiz = false,\
>> .has_pln = true, \
>> +   .has_64bit_types = true, \
>> .supports_simd16_3src = true,\
>> .has_surface_tile_offset = true, \
>> .max_vs_threads = 504,   \
>> @@ -756,6 +758,7 @@ static const struct gen_device_info
>> gen_device_info_cnl_5x8 = {
>>  #define GEN11_FEATURES(_gt, _slices, _l3)   \
>> GEN8_FEATURES,   \
>> GEN11_HW_INFO,   \
>> +   .has_64bit_types = false,@@ -322,6 +323,7 @@ static
>> const struct gen_device_info gen_device_info_hsw_gt3 = {
>> \
>> .gt = _gt, .num_slices = _slices, .l3_banks = _l3
>
> This seems to only enable 64-bit types on snb_gt2 and hsw_gt3, what
> about bdw+ platforms? or ivybridge where we also support fp64?

Sorry, I should have sent the diff with more context. git diff's
context lines are useless, since we're modifying macros here:
GEN7_FEATURES, GEN8_FEATURES, and GEN11_FEATURES (which includes
GEN8_FEATURES).
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Re: [Mesa-dev] [PATCH 03/17] intel: Disable 64-bit extensions on platforms without 64-bit types

2018-02-21 Thread Iago Toral 
On Tue, 2018-02-20 at 21:15 -0800, Matt Turner wrote:
> Gen11 does not support DF, Q, UQ types in hardware. As a result, we
> have
> to disable some GL extensions until they can be reimplemented.
> ---
>  src/intel/common/gen_device_info.c   | 3 +++
>  src/intel/common/gen_device_info.h   | 1 +
>  src/mesa/drivers/dri/i965/intel_extensions.c | 9 +
>  3 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/src/intel/common/gen_device_info.c
> b/src/intel/common/gen_device_info.c
> index 8bf4b6b9bb0..465d4c783a1 100644
> --- a/src/intel/common/gen_device_info.c
> +++ b/src/intel/common/gen_device_info.c
> @@ -138,6 +138,7 @@ static const struct gen_device_info
> gen_device_info_snb_gt2 = {
> .must_use_separate_stencil = true,   \
> .has_llc = true, \
> .has_pln = true, \
> +   .has_64bit_types = true, \
> .has_surface_tile_offset = true, \
> .timestamp_frequency = 1250
>  
> @@ -322,6 +323,7 @@ static const struct gen_device_info
> gen_device_info_hsw_gt3 = {
> .has_llc = true, \
> .has_sample_with_hiz = false,\
> .has_pln = true, \
> +   .has_64bit_types = true, \
> .supports_simd16_3src = true,\
> .has_surface_tile_offset = true, \
> .max_vs_threads = 504,   \
> @@ -756,6 +758,7 @@ static const struct gen_device_info
> gen_device_info_cnl_5x8 = {
>  #define GEN11_FEATURES(_gt, _slices, _l3)   \
> GEN8_FEATURES,   \
> GEN11_HW_INFO,   \
> +   .has_64bit_types = false,@@ -322,6 +323,7 @@ static
> const struct gen_device_info gen_device_info_hsw_gt3 = {
> \
> .gt = _gt, .num_slices = _slices, .l3_banks = _l3

This seems to only enable 64-bit types on snb_gt2 and hsw_gt3, what
about bdw+ platforms? or ivybridge where we also support fp64?

>  static const struct gen_device_info gen_device_info_icl_8x8 = {
> diff --git a/src/intel/common/gen_device_info.h
> b/src/intel/common/gen_device_info.h
> index fd9c17531db..7761eeba7e0 100644
> --- a/src/intel/common/gen_device_info.h
> +++ b/src/intel/common/gen_device_info.h
> @@ -59,6 +59,7 @@ struct gen_device_info
> bool has_llc;
>  
> bool has_pln;
> +   bool has_64bit_types;
> bool has_compr4;
> bool has_surface_tile_offset;
> bool supports_simd16_3src;
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
> b/src/mesa/drivers/dri/i965/intel_extensions.c
> index cc961e051fd..3f5f4dab411 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -217,7 +217,7 @@ intelInitExtensions(struct gl_context *ctx)
>ctx->Extensions.ARB_derivative_control = true;
>ctx->Extensions.ARB_framebuffer_no_attachments = true;
>ctx->Extensions.ARB_gpu_shader5 = true;
> -  ctx->Extensions.ARB_gpu_shader_fp64 = true;
> +  ctx->Extensions.ARB_gpu_shader_fp64 = devinfo-
> >has_64bit_types;
>ctx->Extensions.ARB_shader_atomic_counters = true;
>ctx->Extensions.ARB_shader_atomic_counter_ops = true;
>ctx->Extensions.ARB_shader_clock = true;
> @@ -229,7 +229,7 @@ intelInitExtensions(struct gl_context *ctx)
>ctx->Extensions.ARB_texture_compression_bptc = true;
>ctx->Extensions.ARB_texture_view = true;
>ctx->Extensions.ARB_shader_storage_buffer_object = true;
> -  ctx->Extensions.ARB_vertex_attrib_64bit = true;
> +  ctx->Extensions.ARB_vertex_attrib_64bit = devinfo-
> >has_64bit_types;
>ctx->Extensions.EXT_shader_samples_identical = true;
>ctx->Extensions.OES_primitive_bounding_box = true;
>ctx->Extensions.OES_texture_buffer = true;
> @@ -279,8 +279,9 @@ intelInitExtensions(struct gl_context *ctx)
> }
>  
> if (devinfo->gen >= 8) {
> -  ctx->Extensions.ARB_gpu_shader_int64 = true;
> -  ctx->Extensions.ARB_shader_ballot = true; /* requires
> ARB_gpu_shader_int64 */
> +  ctx->Extensions.ARB_gpu_shader_int64 = devinfo-
> >has_64bit_types;
> +  /* requires ARB_gpu_shader_int64 */
> +  ctx->Extensions.ARB_shader_ballot = devinfo->has_64bit_types;
>ctx->Extensions.ARB_ES3_2_compatibility = true;
> }
>  
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[Mesa-dev] [PATCH 03/17] intel: Disable 64-bit extensions on platforms without 64-bit types

2018-02-20 Thread Matt Turner 
Gen11 does not support DF, Q, UQ types in hardware. As a result, we have
to disable some GL extensions until they can be reimplemented.
---
 src/intel/common/gen_device_info.c   | 3 +++
 src/intel/common/gen_device_info.h   | 1 +
 src/mesa/drivers/dri/i965/intel_extensions.c | 9 +
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/intel/common/gen_device_info.c 
b/src/intel/common/gen_device_info.c
index 8bf4b6b9bb0..465d4c783a1 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -138,6 +138,7 @@ static const struct gen_device_info gen_device_info_snb_gt2 
= {
.must_use_separate_stencil = true,   \
.has_llc = true, \
.has_pln = true, \
+   .has_64bit_types = true, \
.has_surface_tile_offset = true, \
.timestamp_frequency = 1250
 
@@ -322,6 +323,7 @@ static const struct gen_device_info gen_device_info_hsw_gt3 
= {
.has_llc = true, \
.has_sample_with_hiz = false,\
.has_pln = true, \
+   .has_64bit_types = true, \
.supports_simd16_3src = true,\
.has_surface_tile_offset = true, \
.max_vs_threads = 504,   \
@@ -756,6 +758,7 @@ static const struct gen_device_info gen_device_info_cnl_5x8 
= {
 #define GEN11_FEATURES(_gt, _slices, _l3)   \
GEN8_FEATURES,   \
GEN11_HW_INFO,   \
+   .has_64bit_types = false,\
.gt = _gt, .num_slices = _slices, .l3_banks = _l3
 
 static const struct gen_device_info gen_device_info_icl_8x8 = {
diff --git a/src/intel/common/gen_device_info.h 
b/src/intel/common/gen_device_info.h
index fd9c17531db..7761eeba7e0 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -59,6 +59,7 @@ struct gen_device_info
bool has_llc;
 
bool has_pln;
+   bool has_64bit_types;
bool has_compr4;
bool has_surface_tile_offset;
bool supports_simd16_3src;
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index cc961e051fd..3f5f4dab411 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -217,7 +217,7 @@ intelInitExtensions(struct gl_context *ctx)
   ctx->Extensions.ARB_derivative_control = true;
   ctx->Extensions.ARB_framebuffer_no_attachments = true;
   ctx->Extensions.ARB_gpu_shader5 = true;
-  ctx->Extensions.ARB_gpu_shader_fp64 = true;
+  ctx->Extensions.ARB_gpu_shader_fp64 = devinfo->has_64bit_types;
   ctx->Extensions.ARB_shader_atomic_counters = true;
   ctx->Extensions.ARB_shader_atomic_counter_ops = true;
   ctx->Extensions.ARB_shader_clock = true;
@@ -229,7 +229,7 @@ intelInitExtensions(struct gl_context *ctx)
   ctx->Extensions.ARB_texture_compression_bptc = true;
   ctx->Extensions.ARB_texture_view = true;
   ctx->Extensions.ARB_shader_storage_buffer_object = true;
-  ctx->Extensions.ARB_vertex_attrib_64bit = true;
+  ctx->Extensions.ARB_vertex_attrib_64bit = devinfo->has_64bit_types;
   ctx->Extensions.EXT_shader_samples_identical = true;
   ctx->Extensions.OES_primitive_bounding_box = true;
   ctx->Extensions.OES_texture_buffer = true;
@@ -279,8 +279,9 @@ intelInitExtensions(struct gl_context *ctx)
}
 
if (devinfo->gen >= 8) {
-  ctx->Extensions.ARB_gpu_shader_int64 = true;
-  ctx->Extensions.ARB_shader_ballot = true; /* requires 
ARB_gpu_shader_int64 */
+  ctx->Extensions.ARB_gpu_shader_int64 = devinfo->has_64bit_types;
+  /* requires ARB_gpu_shader_int64 */
+  ctx->Extensions.ARB_shader_ballot = devinfo->has_64bit_types;
   ctx->Extensions.ARB_ES3_2_compatibility = true;
}
 
-- 
2.16.1

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