[Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

[Iago Toral Quiroga]

---
 src/compiler/spirv/vtn_alu.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 5f9cc97fdfb..62a5149797a 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -578,7 +578,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
   break;
 
case SpvOpIsInf: {
-  nir_ssa_def *inf = nir_imm_floatN_t(&b->nb, INFINITY, src[0]->bit_size);
+  nir_ssa_def *inf = src[0]->bit_size > 16 ?
+ nir_imm_floatN_t(&b->nb, INFINITY, src[0]->bit_size) :
+ nir_imm_intN_t(&b->nb, 0x7c00, 16);
   val->ssa->def = nir_ieq(&b->nb, nir_fabs(&b->nb, src[0]), inf);
   break;
}
-- 
2.14.1

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Re: [Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

[Jason Ekstrand]

On May 17, 2018 01:47:11 Iago Toral Quiroga  wrote:


---
src/compiler/spirv/vtn_alu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 5f9cc97fdfb..62a5149797a 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -578,7 +578,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
  break;

   case SpvOpIsInf: {
-  nir_ssa_def *inf = nir_imm_floatN_t(&b->nb, INFINITY, src[0]->bit_size);
+  nir_ssa_def *inf = src[0]->bit_size > 16 ?
+ nir_imm_floatN_t(&b->nb, INFINITY, src[0]->bit_size) :
+ nir_imm_intN_t(&b->nb, 0x7c00, 16);


We should just make nir_imm_floatN_t handle 16-bit floats with 
_mesa_float_to_half().



  val->ssa->def = nir_ieq(&b->nb, nir_fabs(&b->nb, src[0]), inf);
  break;
   }
--
2.14.1

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Re: [Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

[Iago Toral]

On Thu, 2018-05-17 at 06:59 -0700, Jason Ekstrand wrote:
> 
> On May 17, 2018 01:47:11 Iago Toral Quiroga 
> wrote:
> 
> > ---
> > src/compiler/spirv/vtn_alu.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/src/compiler/spirv/vtn_alu.c
> > b/src/compiler/spirv/vtn_alu.c
> > index 5f9cc97fdfb..62a5149797a 100644
> > --- a/src/compiler/spirv/vtn_alu.c
> > +++ b/src/compiler/spirv/vtn_alu.c
> > @@ -578,7 +578,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp
> > opcode,
> >   break;
> > 
> >case SpvOpIsInf: {
> > -  nir_ssa_def *inf = nir_imm_floatN_t(&b->nb, INFINITY,
> > src[0]->bit_size);
> > +  nir_ssa_def *inf = src[0]->bit_size > 16 ?
> > + nir_imm_floatN_t(&b->nb, INFINITY, src[0]->bit_size) :
> > + nir_imm_intN_t(&b->nb, 0x7c00, 16);
> 
> We should just make nir_imm_floatN_t handle 16-bit floats with 
> _mesa_float_to_half().

Right, I did that in a later patch and forgot to come back here and fix
 this. Will do that now, thanks!

> >   val->ssa->def = nir_ieq(&b->nb, nir_fabs(&b->nb, src[0]),
> > inf);
> >   break;
> >}
> > --
> > 2.14.1
> > 
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> 
> 
> 
> 
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