subject:"\[Mesa\-dev\] \[PATCH 04\/29\] anv\/blorp\: Rework HiZ ops to look like MCS and CCS"

[Mesa-dev] [PATCH 04/29] anv/blorp: Rework HiZ ops to look like MCS and CCS

2017-11-27 Thread Jason Ekstrand

---
 src/intel/vulkan/anv_blorp.c   | 38 ++
 src/intel/vulkan/anv_private.h |  9 +
 src/intel/vulkan/genX_cmd_buffer.c | 11 ++-
 3 files changed, 33 insertions(+), 25 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index f10adf0..da273d6 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1568,26 +1568,30 @@ anv_image_copy_to_shadow(struct anv_cmd_buffer 
*cmd_buffer,
blorp_batch_finish(&batch);
 }
 
-void
-anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
-const struct anv_image *image,
-enum blorp_hiz_op op)
+static enum blorp_hiz_op
+isl_to_blorp_hiz_op(enum isl_aux_op isl_op)
 {
-   assert(image);
+   switch (isl_op) {
+   case ISL_AUX_OP_FAST_CLEAR:   return BLORP_HIZ_OP_DEPTH_CLEAR;
+   case ISL_AUX_OP_FULL_RESOLVE: return BLORP_HIZ_OP_DEPTH_RESOLVE;
+   case ISL_AUX_OP_AMBIGUATE:return BLORP_HIZ_OP_HIZ_RESOLVE;
+   default:
+  unreachable("Unsupported HiZ aux op");
+   }
+}
 
+void
+anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ VkImageAspectFlagBits aspect, uint32_t level,
+ uint32_t base_layer, uint32_t layer_count,
+ enum isl_aux_op hiz_op)
+{
+   assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
+   assert(base_layer + layer_count <= anv_image_aux_layers(image, aspect, 0));
assert(anv_image_aspect_to_plane(image->aspects,
 VK_IMAGE_ASPECT_DEPTH_BIT) == 0);
 
-   /* Don't resolve depth buffers without an auxiliary HiZ buffer and
-* don't perform such a resolve on gens that don't support it.
-*/
-   if (cmd_buffer->device->info.gen < 8 ||
-   image->planes[0].aux_usage != ISL_AUX_USAGE_HIZ)
-  return;
-
-   assert(op == BLORP_HIZ_OP_HIZ_RESOLVE ||
-  op == BLORP_HIZ_OP_DEPTH_RESOLVE);
-
struct blorp_batch batch;
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
 
@@ -1597,7 +1601,9 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
 ISL_AUX_USAGE_HIZ, &surf);
surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
 
-   blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
+   blorp_hiz_op(&batch, &surf, level, base_layer, layer_count,
+isl_to_blorp_hiz_op(hiz_op));
+
blorp_batch_finish(&batch);
 }
 
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index dc44ab6..5dd95a3 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2530,10 +2530,11 @@ anv_can_sample_with_hiz(const struct gen_device_info * 
const devinfo,
 }
 
 void
-anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
-const struct anv_image *image,
-enum blorp_hiz_op op);
-
+anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ VkImageAspectFlagBits aspect, uint32_t level,
+ uint32_t base_layer, uint32_t layer_count,
+ enum isl_aux_op hiz_op);
 void
 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
  const struct anv_image *image,
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 2e7a2cc..0c1ae83 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -388,19 +388,20 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
   anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
   VK_IMAGE_ASPECT_DEPTH_BIT, final_layout);
 
-   enum blorp_hiz_op hiz_op;
+   enum isl_aux_op hiz_op;
if (hiz_enabled && !enable_hiz) {
-  hiz_op = BLORP_HIZ_OP_DEPTH_RESOLVE;
+  hiz_op = ISL_AUX_OP_FULL_RESOLVE;
} else if (!hiz_enabled && enable_hiz) {
-  hiz_op = BLORP_HIZ_OP_HIZ_RESOLVE;
+  hiz_op = ISL_AUX_OP_AMBIGUATE;
} else {
   assert(hiz_enabled == enable_hiz);
   /* If the same buffer will be used, no resolves are necessary. */
-  hiz_op = BLORP_HIZ_OP_NONE;
+  hiz_op = ISL_AUX_OP_NONE;
}
 
if (hiz_op != BLORP_HIZ_OP_NONE)
-  anv_gen8_hiz_op_resolve(cmd_buffer, image, hiz_op);
+  anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
+   0, 0, 1, hiz_op);
 }
 
 #define MI_PREDICATE_SRC0  0x2400
-- 
2.5.0.400.gff86faf

___
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Re: [Mesa-dev] [PATCH 04/29] anv/blorp: Rework HiZ ops to look like MCS and CCS

2017-12-05 Thread Nanley Chery

On Mon, Nov 27, 2017 at 07:05:54PM -0800, Jason Ekstrand wrote:
> ---
>  src/intel/vulkan/anv_blorp.c   | 38 
> ++
>  src/intel/vulkan/anv_private.h |  9 +
>  src/intel/vulkan/genX_cmd_buffer.c | 11 ++-
>  3 files changed, 33 insertions(+), 25 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index f10adf0..da273d6 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -1568,26 +1568,30 @@ anv_image_copy_to_shadow(struct anv_cmd_buffer 
> *cmd_buffer,
> blorp_batch_finish(&batch);
>  }
>  
> -void
> -anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
> -const struct anv_image *image,
> -enum blorp_hiz_op op)
> +static enum blorp_hiz_op
> +isl_to_blorp_hiz_op(enum isl_aux_op isl_op)
>  {
> -   assert(image);
> +   switch (isl_op) {

Is the NONE case missing?

> +   case ISL_AUX_OP_FAST_CLEAR:   return BLORP_HIZ_OP_DEPTH_CLEAR;
> +   case ISL_AUX_OP_FULL_RESOLVE: return BLORP_HIZ_OP_DEPTH_RESOLVE;
> +   case ISL_AUX_OP_AMBIGUATE:return BLORP_HIZ_OP_HIZ_RESOLVE;
> +   default:
> +  unreachable("Unsupported HiZ aux op");
> +   }
> +}
>  
> +void
> +anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
> + const struct anv_image *image,
> + VkImageAspectFlagBits aspect, uint32_t level,
> + uint32_t base_layer, uint32_t layer_count,
> + enum isl_aux_op hiz_op)
> +{
> +   assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);

Assuming this will handle fast depth/stencil clears, do we want to
future-proof this assert by replacing `==` with `&`?

> +   assert(base_layer + layer_count <= anv_image_aux_layers(image, aspect, 
> 0));
 ^
I think we should replace `0` with `level`.

-Nanley

> assert(anv_image_aspect_to_plane(image->aspects,
>  VK_IMAGE_ASPECT_DEPTH_BIT) == 0);
>  
> -   /* Don't resolve depth buffers without an auxiliary HiZ buffer and
> -* don't perform such a resolve on gens that don't support it.
> -*/
> -   if (cmd_buffer->device->info.gen < 8 ||
> -   image->planes[0].aux_usage != ISL_AUX_USAGE_HIZ)
> -  return;
> -
> -   assert(op == BLORP_HIZ_OP_HIZ_RESOLVE ||
> -  op == BLORP_HIZ_OP_DEPTH_RESOLVE);
> -
> struct blorp_batch batch;
> blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
>  
> @@ -1597,7 +1601,9 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer 
> *cmd_buffer,
>  ISL_AUX_USAGE_HIZ, &surf);
> surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
>  
> -   blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
> +   blorp_hiz_op(&batch, &surf, level, base_layer, layer_count,
> +isl_to_blorp_hiz_op(hiz_op));
> +
> blorp_batch_finish(&batch);
>  }
>  
> diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
> index dc44ab6..5dd95a3 100644
> --- a/src/intel/vulkan/anv_private.h
> +++ b/src/intel/vulkan/anv_private.h
> @@ -2530,10 +2530,11 @@ anv_can_sample_with_hiz(const struct gen_device_info 
> * const devinfo,
>  }
>  
>  void
> -anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
> -const struct anv_image *image,
> -enum blorp_hiz_op op);
> -
> +anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
> + const struct anv_image *image,
> + VkImageAspectFlagBits aspect, uint32_t level,
> + uint32_t base_layer, uint32_t layer_count,
> + enum isl_aux_op hiz_op);
>  void
>  anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
>   const struct anv_image *image,
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 2e7a2cc..0c1ae83 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -388,19 +388,20 @@ transition_depth_buffer(struct anv_cmd_buffer 
> *cmd_buffer,
>anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
>VK_IMAGE_ASPECT_DEPTH_BIT, final_layout);
>  
> -   enum blorp_hiz_op hiz_op;
> +   enum isl_aux_op hiz_op;
> if (hiz_enabled && !enable_hiz) {
> -  hiz_op = BLORP_HIZ_OP_DEPTH_RESOLVE;
> +  hiz_op = ISL_AUX_OP_FULL_RESOLVE;
> } else if (!hiz_enabled && enable_hiz) {
> -  hiz_op = BLORP_HIZ_OP_HIZ_RESOLVE;
> +  hiz_op = ISL_AUX_OP_AMBIGUATE;
> } else {
>assert(hiz_enabled == enable_hiz);
>/* If the same buffer will be used, no resolves are necessary. */
> -  hiz_op = BLORP_HIZ_OP_NONE;
> +  hiz_op = ISL_AUX_OP_NONE;
> }
>  
> if (hiz_op != BLORP_HIZ_OP_NONE)
> -  anv_gen8_hiz_op_resolve(cmd_buffer, image, hiz_op);
> +  anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
> +

Re: [Mesa-dev] [PATCH 04/29] anv/blorp: Rework HiZ ops to look like MCS and CCS

2018-01-12 Thread Jason Ekstrand

On Tue, Dec 5, 2017 at 4:48 PM, Nanley Chery  wrote:

> On Mon, Nov 27, 2017 at 07:05:54PM -0800, Jason Ekstrand wrote:
> > ---
> >  src/intel/vulkan/anv_blorp.c   | 38 ++
> 
> >  src/intel/vulkan/anv_private.h |  9 +
> >  src/intel/vulkan/genX_cmd_buffer.c | 11 ++-
> >  3 files changed, 33 insertions(+), 25 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> > index f10adf0..da273d6 100644
> > --- a/src/intel/vulkan/anv_blorp.c
> > +++ b/src/intel/vulkan/anv_blorp.c
> > @@ -1568,26 +1568,30 @@ anv_image_copy_to_shadow(struct anv_cmd_buffer
> *cmd_buffer,
> > blorp_batch_finish(&batch);
> >  }
> >
> > -void
> > -anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
> > -const struct anv_image *image,
> > -enum blorp_hiz_op op)
> > +static enum blorp_hiz_op
> > +isl_to_blorp_hiz_op(enum isl_aux_op isl_op)
> >  {
> > -   assert(image);
> > +   switch (isl_op) {
>
> Is the NONE case missing?
>

Nope.  calling anv_image_hiz_op with none is considered invalid.


> > +   case ISL_AUX_OP_FAST_CLEAR:   return BLORP_HIZ_OP_DEPTH_CLEAR;
> > +   case ISL_AUX_OP_FULL_RESOLVE: return BLORP_HIZ_OP_DEPTH_RESOLVE;
> > +   case ISL_AUX_OP_AMBIGUATE:return BLORP_HIZ_OP_HIZ_RESOLVE;
> > +   default:
> > +  unreachable("Unsupported HiZ aux op");
> > +   }
> > +}
> >
> > +void
> > +anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
> > + const struct anv_image *image,
> > + VkImageAspectFlagBits aspect, uint32_t level,
> > + uint32_t base_layer, uint32_t layer_count,
> > + enum isl_aux_op hiz_op)
> > +{
> > +   assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
>
> Assuming this will handle fast depth/stencil clears, do we want to
> future-proof this assert by replacing `==` with `&`?
>

I ended up adding a second function for fast depth/stencil clears because
it needs to take an extent.  It's a bit unfortunate but it seemed cleaner
than making callers of anv_image_hiz_op have to worry about extents.


> > +   assert(base_layer + layer_count <= anv_image_aux_layers(image,
> aspect, 0));
>
>^
> I think we should replace `0` with `level`.
>

Sure.  Fixed locally.


> -Nanley
>
> > assert(anv_image_aspect_to_plane(image->aspects,
> >  VK_IMAGE_ASPECT_DEPTH_BIT) == 0);
> >
> > -   /* Don't resolve depth buffers without an auxiliary HiZ buffer and
> > -* don't perform such a resolve on gens that don't support it.
> > -*/
> > -   if (cmd_buffer->device->info.gen < 8 ||
> > -   image->planes[0].aux_usage != ISL_AUX_USAGE_HIZ)
> > -  return;
> > -
> > -   assert(op == BLORP_HIZ_OP_HIZ_RESOLVE ||
> > -  op == BLORP_HIZ_OP_DEPTH_RESOLVE);
> > -
> > struct blorp_batch batch;
> > blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
> >
> > @@ -1597,7 +1601,9 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
> *cmd_buffer,
> >  ISL_AUX_USAGE_HIZ, &surf);
> > surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
> >
> > -   blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
> > +   blorp_hiz_op(&batch, &surf, level, base_layer, layer_count,
> > +isl_to_blorp_hiz_op(hiz_op));
> > +
> > blorp_batch_finish(&batch);
> >  }
> >
> > diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_
> private.h
> > index dc44ab6..5dd95a3 100644
> > --- a/src/intel/vulkan/anv_private.h
> > +++ b/src/intel/vulkan/anv_private.h
> > @@ -2530,10 +2530,11 @@ anv_can_sample_with_hiz(const struct
> gen_device_info * const devinfo,
> >  }
> >
> >  void
> > -anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
> > -const struct anv_image *image,
> > -enum blorp_hiz_op op);
> > -
> > +anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
> > + const struct anv_image *image,
> > + VkImageAspectFlagBits aspect, uint32_t level,
> > + uint32_t base_layer, uint32_t layer_count,
> > + enum isl_aux_op hiz_op);
> >  void
> >  anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
> >   const struct anv_image *image,
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> > index 2e7a2cc..0c1ae83 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -388,19 +388,20 @@ transition_depth_buffer(struct anv_cmd_buffer
> *cmd_buffer,
> >anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
> >VK_IMAGE_ASPECT_DEPTH_BIT, final_layout);
> >
> > -   enum blorp_hiz_op hiz_op;
> > +   enum isl_aux_op hiz_op;
> > if (hiz_enabled && !enable_hiz) {
> > -  hiz_op = BLORP_HIZ_OP_DEPTH_RESOLVE;
> > +  hiz_op = ISL_AUX_OP_FULL_RESOLVE;
> > } else if (!hiz_enabled && e

Re: [Mesa-dev] [PATCH 04/29] anv/blorp: Rework HiZ ops to look like MCS and CCS

2017-11-28 Thread Pohjolainen, Topi

On Mon, Nov 27, 2017 at 07:05:54PM -0800, Jason Ekstrand wrote:
> ---
>  src/intel/vulkan/anv_blorp.c   | 38 
> ++
>  src/intel/vulkan/anv_private.h |  9 +
>  src/intel/vulkan/genX_cmd_buffer.c | 11 ++-
>  3 files changed, 33 insertions(+), 25 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index f10adf0..da273d6 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -1568,26 +1568,30 @@ anv_image_copy_to_shadow(struct anv_cmd_buffer 
> *cmd_buffer,
> blorp_batch_finish(&batch);
>  }
>  
> -void
> -anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
> -const struct anv_image *image,
> -enum blorp_hiz_op op)
> +static enum blorp_hiz_op
> +isl_to_blorp_hiz_op(enum isl_aux_op isl_op)
>  {
> -   assert(image);
> +   switch (isl_op) {
> +   case ISL_AUX_OP_FAST_CLEAR:   return BLORP_HIZ_OP_DEPTH_CLEAR;
> +   case ISL_AUX_OP_FULL_RESOLVE: return BLORP_HIZ_OP_DEPTH_RESOLVE;
> +   case ISL_AUX_OP_AMBIGUATE:return BLORP_HIZ_OP_HIZ_RESOLVE;
> +   default:
> +  unreachable("Unsupported HiZ aux op");
> +   }
> +}
>  
> +void
> +anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
> + const struct anv_image *image,
> + VkImageAspectFlagBits aspect, uint32_t level,
> + uint32_t base_layer, uint32_t layer_count,
> + enum isl_aux_op hiz_op)
> +{
> +   assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
> +   assert(base_layer + layer_count <= anv_image_aux_layers(image, aspect, 
> 0));
> assert(anv_image_aspect_to_plane(image->aspects,
>  VK_IMAGE_ASPECT_DEPTH_BIT) == 0);
>  
> -   /* Don't resolve depth buffers without an auxiliary HiZ buffer and
> -* don't perform such a resolve on gens that don't support it.
> -*/
> -   if (cmd_buffer->device->info.gen < 8 ||
> -   image->planes[0].aux_usage != ISL_AUX_USAGE_HIZ)
> -  return;
> -
> -   assert(op == BLORP_HIZ_OP_HIZ_RESOLVE ||
> -  op == BLORP_HIZ_OP_DEPTH_RESOLVE);
> -
> struct blorp_batch batch;
> blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
>  
> @@ -1597,7 +1601,9 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer 
> *cmd_buffer,
>  ISL_AUX_USAGE_HIZ, &surf);
> surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
>  
> -   blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
> +   blorp_hiz_op(&batch, &surf, level, base_layer, layer_count,
> +isl_to_blorp_hiz_op(hiz_op));
> +
> blorp_batch_finish(&batch);
>  }
>  
> diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
> index dc44ab6..5dd95a3 100644
> --- a/src/intel/vulkan/anv_private.h
> +++ b/src/intel/vulkan/anv_private.h
> @@ -2530,10 +2530,11 @@ anv_can_sample_with_hiz(const struct gen_device_info 
> * const devinfo,
>  }
>  
>  void
> -anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
> -const struct anv_image *image,
> -enum blorp_hiz_op op);
> -
> +anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
> + const struct anv_image *image,
> + VkImageAspectFlagBits aspect, uint32_t level,
> + uint32_t base_layer, uint32_t layer_count,
> + enum isl_aux_op hiz_op);
>  void
>  anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
>   const struct anv_image *image,
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 2e7a2cc..0c1ae83 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -388,19 +388,20 @@ transition_depth_buffer(struct anv_cmd_buffer 
> *cmd_buffer,
>anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
>VK_IMAGE_ASPECT_DEPTH_BIT, final_layout);
>  
> -   enum blorp_hiz_op hiz_op;
> +   enum isl_aux_op hiz_op;
> if (hiz_enabled && !enable_hiz) {
> -  hiz_op = BLORP_HIZ_OP_DEPTH_RESOLVE;
> +  hiz_op = ISL_AUX_OP_FULL_RESOLVE;
> } else if (!hiz_enabled && enable_hiz) {
> -  hiz_op = BLORP_HIZ_OP_HIZ_RESOLVE;
> +  hiz_op = ISL_AUX_OP_AMBIGUATE;
> } else {
>assert(hiz_enabled == enable_hiz);
>/* If the same buffer will be used, no resolves are necessary. */
> -  hiz_op = BLORP_HIZ_OP_NONE;
> +  hiz_op = ISL_AUX_OP_NONE;
> }
>  
> if (hiz_op != BLORP_HIZ_OP_NONE)

ISL_AUX_OP_NONE

> -  anv_gen8_hiz_op_resolve(cmd_buffer, image, hiz_op);
> +  anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
> +   0, 0, 1, hiz_op);
>  }
>  
>  #define MI_PREDICATE_SRC0  0x2400
> -- 
> 2.5.0.400.gff86faf
> 
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.

Re: [Mesa-dev] [PATCH 04/29] anv/blorp: Rework HiZ ops to look like MCS and CCS

2017-11-28 Thread Jason Ekstrand

On Tue, Nov 28, 2017 at 5:56 AM, Pohjolainen, Topi <
topi.pohjolai...@gmail.com> wrote:

> On Mon, Nov 27, 2017 at 07:05:54PM -0800, Jason Ekstrand wrote:
> > ---
> >  src/intel/vulkan/anv_blorp.c   | 38 ++
> 
> >  src/intel/vulkan/anv_private.h |  9 +
> >  src/intel/vulkan/genX_cmd_buffer.c | 11 ++-
> >  3 files changed, 33 insertions(+), 25 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> > index f10adf0..da273d6 100644
> > --- a/src/intel/vulkan/anv_blorp.c
> > +++ b/src/intel/vulkan/anv_blorp.c
> > @@ -1568,26 +1568,30 @@ anv_image_copy_to_shadow(struct anv_cmd_buffer
> *cmd_buffer,
> > blorp_batch_finish(&batch);
> >  }
> >
> > -void
> > -anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
> > -const struct anv_image *image,
> > -enum blorp_hiz_op op)
> > +static enum blorp_hiz_op
> > +isl_to_blorp_hiz_op(enum isl_aux_op isl_op)
> >  {
> > -   assert(image);
> > +   switch (isl_op) {
> > +   case ISL_AUX_OP_FAST_CLEAR:   return BLORP_HIZ_OP_DEPTH_CLEAR;
> > +   case ISL_AUX_OP_FULL_RESOLVE: return BLORP_HIZ_OP_DEPTH_RESOLVE;
> > +   case ISL_AUX_OP_AMBIGUATE:return BLORP_HIZ_OP_HIZ_RESOLVE;
> > +   default:
> > +  unreachable("Unsupported HiZ aux op");
> > +   }
> > +}
> >
> > +void
> > +anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
> > + const struct anv_image *image,
> > + VkImageAspectFlagBits aspect, uint32_t level,
> > + uint32_t base_layer, uint32_t layer_count,
> > + enum isl_aux_op hiz_op)
> > +{
> > +   assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
> > +   assert(base_layer + layer_count <= anv_image_aux_layers(image,
> aspect, 0));
> > assert(anv_image_aspect_to_plane(image->aspects,
> >  VK_IMAGE_ASPECT_DEPTH_BIT) == 0);
> >
> > -   /* Don't resolve depth buffers without an auxiliary HiZ buffer and
> > -* don't perform such a resolve on gens that don't support it.
> > -*/
> > -   if (cmd_buffer->device->info.gen < 8 ||
> > -   image->planes[0].aux_usage != ISL_AUX_USAGE_HIZ)
> > -  return;
> > -
> > -   assert(op == BLORP_HIZ_OP_HIZ_RESOLVE ||
> > -  op == BLORP_HIZ_OP_DEPTH_RESOLVE);
> > -
> > struct blorp_batch batch;
> > blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
> >
> > @@ -1597,7 +1601,9 @@ anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
> *cmd_buffer,
> >  ISL_AUX_USAGE_HIZ, &surf);
> > surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
> >
> > -   blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
> > +   blorp_hiz_op(&batch, &surf, level, base_layer, layer_count,
> > +isl_to_blorp_hiz_op(hiz_op));
> > +
> > blorp_batch_finish(&batch);
> >  }
> >
> > diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_
> private.h
> > index dc44ab6..5dd95a3 100644
> > --- a/src/intel/vulkan/anv_private.h
> > +++ b/src/intel/vulkan/anv_private.h
> > @@ -2530,10 +2530,11 @@ anv_can_sample_with_hiz(const struct
> gen_device_info * const devinfo,
> >  }
> >
> >  void
> > -anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
> > -const struct anv_image *image,
> > -enum blorp_hiz_op op);
> > -
> > +anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
> > + const struct anv_image *image,
> > + VkImageAspectFlagBits aspect, uint32_t level,
> > + uint32_t base_layer, uint32_t layer_count,
> > + enum isl_aux_op hiz_op);
> >  void
> >  anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
> >   const struct anv_image *image,
> > diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> > index 2e7a2cc..0c1ae83 100644
> > --- a/src/intel/vulkan/genX_cmd_buffer.c
> > +++ b/src/intel/vulkan/genX_cmd_buffer.c
> > @@ -388,19 +388,20 @@ transition_depth_buffer(struct anv_cmd_buffer
> *cmd_buffer,
> >anv_layout_to_aux_usage(&cmd_buffer->device->info, image,
> >VK_IMAGE_ASPECT_DEPTH_BIT, final_layout);
> >
> > -   enum blorp_hiz_op hiz_op;
> > +   enum isl_aux_op hiz_op;
> > if (hiz_enabled && !enable_hiz) {
> > -  hiz_op = BLORP_HIZ_OP_DEPTH_RESOLVE;
> > +  hiz_op = ISL_AUX_OP_FULL_RESOLVE;
> > } else if (!hiz_enabled && enable_hiz) {
> > -  hiz_op = BLORP_HIZ_OP_HIZ_RESOLVE;
> > +  hiz_op = ISL_AUX_OP_AMBIGUATE;
> > } else {
> >assert(hiz_enabled == enable_hiz);
> >/* If the same buffer will be used, no resolves are necessary. */
> > -  hiz_op = BLORP_HIZ_OP_NONE;
> > +  hiz_op = ISL_AUX_OP_NONE;
> > }
> >
> > if (hiz_op != BLORP_HIZ_OP_NONE)
>
> ISL_AUX_OP_NONE
>

Thanks!  Fixed locally.  Fortunately, it was never a problem because both
are 0 but it's a g

[Mesa-dev] [PATCH 04/29] anv/blorp: Rework HiZ ops to look like MCS and CCS

Re: [Mesa-dev] [PATCH 04/29] anv/blorp: Rework HiZ ops to look like MCS and CCS

Re: [Mesa-dev] [PATCH 04/29] anv/blorp: Rework HiZ ops to look like MCS and CCS

Re: [Mesa-dev] [PATCH 04/29] anv/blorp: Rework HiZ ops to look like MCS and CCS

Re: [Mesa-dev] [PATCH 04/29] anv/blorp: Rework HiZ ops to look like MCS and CCS

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