This new type exposes the additional precision offered by the
accumulator register and will be used in the next patch to implement the
functionality of the PLN instruction using a pair of MAD instructions.
One weird thing to note: align1 ternary instructions may only have an
accumulator in the dst or src1 normally, but when src0's type is :NF
the accumulator is read.
---
src/intel/compiler/brw_disasm.c | 7 +++
src/intel/compiler/brw_eu_emit.c | 10 --
src/intel/compiler/brw_eu_validate.c | 1 +
src/intel/compiler/brw_reg_type.c| 8
src/intel/compiler/brw_reg_type.h| 2 ++
src/intel/compiler/brw_shader.cpp| 6 ++
6 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 429ed781404..a9a108f8acd 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1035,6 +1035,12 @@ src0_3src(FILE *file, const struct gen_device_info
*devinfo, const brw_inst *ins
reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst);
subreg_nr = brw_inst_3src_a1_src0_subreg_nr(devinfo, inst);
type = brw_inst_3src_a1_src0_type(devinfo, inst);
+ } else if (brw_inst_3src_a1_src0_type(devinfo, inst) ==
+ BRW_REGISTER_TYPE_NF) {
+ _file = BRW_ARCHITECTURE_REGISTER_FILE;
+ reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst);
+ subreg_nr = brw_inst_3src_a1_src0_subreg_nr(devinfo, inst);
+ type = brw_inst_3src_a1_src0_type(devinfo, inst);
} else {
_file = BRW_IMMEDIATE_VALUE;
uint16_t imm_val = brw_inst_3src_a1_src0_imm(devinfo, inst);
@@ -1288,6 +1294,7 @@ imm(FILE *file, const struct gen_device_info *devinfo,
enum brw_reg_type type,
case BRW_REGISTER_TYPE_HF:
string(file, "Half Float IMM");
break;
+ case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
format(file, "*** invalid immediate type %d ", type);
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index c25d8d6eda0..ec871e5aa75 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -771,7 +771,11 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct
brw_reg dest,
to_3src_align1_hstride(src2.hstride));
brw_inst_set_3src_a1_src0_subreg_nr(devinfo, inst, src0.subnr);
- brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
+ if (src0.type == BRW_REGISTER_TYPE_NF) {
+ brw_inst_set_3src_src0_reg_nr(devinfo, inst, BRW_ARF_ACCUMULATOR);
+ } else {
+ brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
+ }
brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
brw_inst_set_3src_src0_negate(devinfo, inst, src0.negate);
@@ -790,7 +794,9 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct
brw_reg dest,
brw_inst_set_3src_src2_negate(devinfo, inst, src2.negate);
assert(src0.file == BRW_GENERAL_REGISTER_FILE ||
- src0.file == BRW_IMMEDIATE_VALUE);
+ src0.file == BRW_IMMEDIATE_VALUE ||
+ (src0.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+ src0.type == BRW_REGISTER_TYPE_NF));
assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
src1.file == BRW_ARCHITECTURE_REGISTER_FILE);
assert(src2.file == BRW_GENERAL_REGISTER_FILE ||
diff --git a/src/intel/compiler/brw_eu_validate.c
b/src/intel/compiler/brw_eu_validate.c
index 6ee6b4ffbe7..d3189d1ef5e 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -277,6 +277,7 @@ static enum brw_reg_type
execution_type_for_type(enum brw_reg_type type)
{
switch (type) {
+ case BRW_REGISTER_TYPE_NF:
case BRW_REGISTER_TYPE_DF:
case BRW_REGISTER_TYPE_F:
case BRW_REGISTER_TYPE_HF:
diff --git a/src/intel/compiler/brw_reg_type.c
b/src/intel/compiler/brw_reg_type.c
index c4f8eedeb4b..3c82eb0a76f 100644
--- a/src/intel/compiler/brw_reg_type.c
+++ b/src/intel/compiler/brw_reg_type.c
@@ -52,6 +52,7 @@ enum hw_reg_type {
GEN11_HW_REG_TYPE_HF = 8,
GEN11_HW_REG_TYPE_F = 9,
GEN11_HW_REG_TYPE_DF = 10,
+ GEN11_HW_REG_TYPE_NF = 11,
};
enum hw_imm_type {
@@ -87,6 +88,8 @@ static const struct hw_type {
enum hw_reg_type reg_type;
enum hw_imm_type imm_type;
} gen4_hw_type[] = {
+ [0 ... BRW_REGISTER_TYPE_LAST] = { INVALID, INVALID },
+
[BRW_REGISTER_TYPE_DF] = { GEN7_HW_REG_TYPE_DF, GEN8_HW_IMM_TYPE_DF },
[BRW_REGISTER_TYPE_F] = { BRW_HW_REG_TYPE_F, BRW_HW_IMM_TYPE_F },
[BRW_REGISTER_TYPE_HF] = { GEN8_HW_REG_TYPE_HF, GEN8_HW_IMM_TYPE_HF },
@@ -103,6 +106,7 @@ static const struct hw_type {
[BRW_REGISTER_TYPE_V] = { INVALID, BRW_HW_IMM_TYPE_V },
[BRW_REGISTER_TYPE_UV] = { INVALID, BRW_HW_IMM_TYPE_UV },
}, gen11_hw_type[] = {
+ [BRW_REGISTER_TYPE_NF]
