[Mesa-dev] [PATCH 05/30] i965/miptree: Rework aux enabling

2017-06-16 Thread Jason Ekstrand 
This commit replaces the complex and confusing set of disable flags with
two fairly straightforward fields which describe the intended auxiliary
surface usage and whether or not the miptree supports fast clears.
Right now, supports_fast_clear can be entirely derived from aux_usage
but that will not always be the case.

This commit makes functional changes.  One of these changes is that it
re-enables multisampled fast-clears which were accidentally disabled in
cec30a666930ddb8476a9452a89364a24979ff62 around a year ago.  It should
also enable CCS_E for window-system buffers which are Y-tiled.  They
will still get a full resolve like CCS_D but we will at least get some
of the advantage of compression.
---
 src/mesa/drivers/dri/i965/brw_blorp.c |   4 +-
 src/mesa/drivers/dri/i965/intel_fbo.c |   2 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  43 +++---
 4 files changed, 120 insertions(+), 119 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 00092ee..9bd25f0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
if (set_write_disables(irb, ctx->Color.ColorMask[buf], color_write_disable))
   can_fast_clear = false;
 
-   if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
+   if (!irb->mt->supports_fast_clear ||
!brw_is_color_fast_clear_compatible(brw, irb->mt, 
&ctx->Color.ClearColor))
   can_fast_clear = false;
 
@@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
*/
   if (!irb->mt->mcs_buf) {
  assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
- if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
+ if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
 /* MCS allocation failed--probably this will only happen in
  * out-of-memory conditions.  But in any case, try to recover
  * by falling back to a non-blorp clear technique.
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index ee4aba9..6a64bcb 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
 
intel_renderbuffer_set_draw_offset(irb);
 
-   if (intel_miptree_wants_hiz_buffer(brw, mt)) {
+   if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
   intel_miptree_alloc_hiz(brw, mt);
   if (!mt->hiz_buf)
 return false;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0f6d542..101317f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
  */
 static enum intel_msaa_layout
 compute_msaa_layout(struct brw_context *brw, mesa_format format,
-enum intel_aux_disable aux_disable)
+uint32_t layout_flags)
 {
/* Prior to Gen7, all MSAA surfaces used IMS layout. */
if (brw->gen < 7)
@@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format 
format,
*/
   if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
  return INTEL_MSAA_LAYOUT_UMS;
-  } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
+  } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
  /* We can't use the CMS layout because it uses an aux buffer, the MCS
   * buffer. So fallback to UMS, which is identical to CMS without the
   * MCS. */
@@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (brw->gen < 7)
   return false;
 
-   if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
-  return false;
-
/* This function applies only to non-multisampled render targets. */
if (mt->num_samples > 1)
   return false;
@@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
   return true;
 }
 
+static bool
+intel_miptree_supports_hiz(struct brw_context *brw,
+   struct intel_mipmap_tree *mt)
+{
+   if (!brw->has_hiz)
+  return false;
+
+   switch (mt->format) {
+   case MESA_FORMAT_Z_FLOAT32:
+   case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
+   case MESA_FORMAT_Z24_UNORM_X8_UINT:
+   case MESA_FORMAT_Z24_UNORM_S8_UINT:
+   case MESA_FORMAT_Z_UNORM16:
+  return true;
+   default:
+  return false;
+   }
+}
+
+
 /* On Gen9 support for color buffer compression was extended to single
  * sampled surfaces. This is a helper considering both auxiliary buffer
  * type and number of samples telling if the given miptree represents
@@ -320,10 +337,9 @@ intel_miptree_create_layout(struct brw_context *brw,
mt-

Re: [Mesa-dev] [PATCH 05/30] i965/miptree: Rework aux enabling

2017-06-21 Thread Pohjolainen, Topi 
On Fri, Jun 16, 2017 at 03:41:27PM -0700, Jason Ekstrand wrote:
> This commit replaces the complex and confusing set of disable flags with
> two fairly straightforward fields which describe the intended auxiliary
> surface usage and whether or not the miptree supports fast clears.
> Right now, supports_fast_clear can be entirely derived from aux_usage
> but that will not always be the case.
> 
> This commit makes functional changes.  One of these changes is that it
> re-enables multisampled fast-clears which were accidentally disabled in
> cec30a666930ddb8476a9452a89364a24979ff62 around a year ago.  It should
> also enable CCS_E for window-system buffers which are Y-tiled.  They
> will still get a full resolve like CCS_D but we will at least get some
> of the advantage of compression.
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c |   4 +-
>  src/mesa/drivers/dri/i965/intel_fbo.c |   2 +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190 
> +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  43 +++---
>  4 files changed, 120 insertions(+), 119 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 00092ee..9bd25f0 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
> gl_framebuffer *fb,
> if (set_write_disables(irb, ctx->Color.ColorMask[buf], 
> color_write_disable))
>can_fast_clear = false;
>  
> -   if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
> +   if (!irb->mt->supports_fast_clear ||
> !brw_is_color_fast_clear_compatible(brw, irb->mt, 
> &ctx->Color.ClearColor))
>can_fast_clear = false;
>  
> @@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
> gl_framebuffer *fb,
> */
>if (!irb->mt->mcs_buf) {
>   assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
> - if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
> + if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
>  /* MCS allocation failed--probably this will only happen in
>   * out-of-memory conditions.  But in any case, try to recover
>   * by falling back to a non-blorp clear technique.
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> index ee4aba9..6a64bcb 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
>  
> intel_renderbuffer_set_draw_offset(irb);
>  
> -   if (intel_miptree_wants_hiz_buffer(brw, mt)) {
> +   if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
>intel_miptree_alloc_hiz(brw, mt);
>if (!mt->hiz_buf)
>return false;
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 0f6d542..101317f 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
>   */
>  static enum intel_msaa_layout
>  compute_msaa_layout(struct brw_context *brw, mesa_format format,
> -enum intel_aux_disable aux_disable)
> +uint32_t layout_flags)
>  {
> /* Prior to Gen7, all MSAA surfaces used IMS layout. */
> if (brw->gen < 7)
> @@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format 
> format,
> */
>if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
>   return INTEL_MSAA_LAYOUT_UMS;
> -  } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
> +  } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
>   /* We can't use the CMS layout because it uses an aux buffer, the 
> MCS
>* buffer. So fallback to UMS, which is identical to CMS without the
>* MCS. */
> @@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> if (brw->gen < 7)
>return false;
>  
> -   if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
> -  return false;
> -
> /* This function applies only to non-multisampled render targets. */
> if (mt->num_samples > 1)
>return false;
> @@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
>return true;
>  }
>  
> +static bool
> +intel_miptree_supports_hiz(struct brw_context *brw,
> +   struct intel_mipmap_tree *mt)
> +{
> +   if (!brw->has_hiz)
> +  return false;
> +
> +   switch (mt->format) {
> +   case MESA_FORMAT_Z_FLOAT32:
> +   case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
> +   case MESA_FORMAT_Z24_UNORM_X8_UINT:
> +   case MESA_FORMAT_Z24_UNORM_S8_UINT:
> +   case MESA_FORMAT_Z_UNORM16:
> +  return true;
> +   default:
> +  return false;
> +   }
> +}

Re: [Mesa-dev] [PATCH 05/30] i965/miptree: Rework aux enabling

2017-06-21 Thread Jason Ekstrand 
On Wed, Jun 21, 2017 at 5:35 AM, Pohjolainen, Topi <
topi.pohjolai...@gmail.com> wrote:

> On Fri, Jun 16, 2017 at 03:41:27PM -0700, Jason Ekstrand wrote:
> > This commit replaces the complex and confusing set of disable flags with
> > two fairly straightforward fields which describe the intended auxiliary
> > surface usage and whether or not the miptree supports fast clears.
> > Right now, supports_fast_clear can be entirely derived from aux_usage
> > but that will not always be the case.
> >
> > This commit makes functional changes.  One of these changes is that it
> > re-enables multisampled fast-clears which were accidentally disabled in
> > cec30a666930ddb8476a9452a89364a24979ff62 around a year ago.  It should
> > also enable CCS_E for window-system buffers which are Y-tiled.  They
> > will still get a full resolve like CCS_D but we will at least get some
> > of the advantage of compression.
> > ---
> >  src/mesa/drivers/dri/i965/brw_blorp.c |   4 +-
> >  src/mesa/drivers/dri/i965/intel_fbo.c |   2 +-
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190
> +-
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  43 +++---
> >  4 files changed, 120 insertions(+), 119 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> > index 00092ee..9bd25f0 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > @@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw,
> struct gl_framebuffer *fb,
> > if (set_write_disables(irb, ctx->Color.ColorMask[buf],
> color_write_disable))
> >can_fast_clear = false;
> >
> > -   if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
> > +   if (!irb->mt->supports_fast_clear ||
> > !brw_is_color_fast_clear_compatible(brw, irb->mt,
> &ctx->Color.ClearColor))
> >can_fast_clear = false;
> >
> > @@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw,
> struct gl_framebuffer *fb,
> > */
> >if (!irb->mt->mcs_buf) {
> >   assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
> > - if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
> > + if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
> >  /* MCS allocation failed--probably this will only happen in
> >   * out-of-memory conditions.  But in any case, try to
> recover
> >   * by falling back to a non-blorp clear technique.
> > diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> > index ee4aba9..6a64bcb 100644
> > --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> > +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> > @@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct
> brw_context *brw,
> >
> > intel_renderbuffer_set_draw_offset(irb);
> >
> > -   if (intel_miptree_wants_hiz_buffer(brw, mt)) {
> > +   if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
> >intel_miptree_alloc_hiz(brw, mt);
> >if (!mt->hiz_buf)
> >return false;
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index 0f6d542..101317f 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
> >   */
> >  static enum intel_msaa_layout
> >  compute_msaa_layout(struct brw_context *brw, mesa_format format,
> > -enum intel_aux_disable aux_disable)
> > +uint32_t layout_flags)
> >  {
> > /* Prior to Gen7, all MSAA surfaces used IMS layout. */
> > if (brw->gen < 7)
> > @@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw,
> mesa_format format,
> > */
> >if (brw->gen == 7 && _mesa_get_format_datatype(format) ==
> GL_INT) {
> >   return INTEL_MSAA_LAYOUT_UMS;
> > -  } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
> > +  } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
> >   /* We can't use the CMS layout because it uses an aux buffer,
> the MCS
> >* buffer. So fallback to UMS, which is identical to CMS
> without the
> >* MCS. */
> > @@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> > if (brw->gen < 7)
> >return false;
> >
> > -   if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
> > -  return false;
> > -
> > /* This function applies only to non-multisampled render targets. */
> > if (mt->num_samples > 1)
> >return false;
> > @@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> >return true;
> >  }
> >
> > +static bool
> > +intel_miptree_supports_hiz(struct brw_context *brw,
> > +   struct intel_mipmap_tree *mt)
> > +{
> > +   if (!brw->has_hiz)
> > +  return false;
> > +
> > +   switch (mt->format) {

Re: [Mesa-dev] [PATCH 05/30] i965/miptree: Rework aux enabling

2017-06-21 Thread Chad Versace 
On Fri 16 Jun 2017, Jason Ekstrand wrote:
> This commit replaces the complex and confusing set of disable flags with
> two fairly straightforward fields which describe the intended auxiliary
> surface usage and whether or not the miptree supports fast clears.
> Right now, supports_fast_clear can be entirely derived from aux_usage
> but that will not always be the case.
> 
> This commit makes functional changes.  One of these changes is that it
> re-enables multisampled fast-clears which were accidentally disabled in
> cec30a666930ddb8476a9452a89364a24979ff62 around a year ago.  It should
> also enable CCS_E for window-system buffers which are Y-tiled.  They
> will still get a full resolve like CCS_D but we will at least get some
> of the advantage of compression.
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c |   4 +-
>  src/mesa/drivers/dri/i965/intel_fbo.c |   2 +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190 
> +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  43 +++---
>  4 files changed, 120 insertions(+), 119 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 00092ee..9bd25f0 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
> gl_framebuffer *fb,
> if (set_write_disables(irb, ctx->Color.ColorMask[buf], 
> color_write_disable))
>can_fast_clear = false;
>  
> -   if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
> +   if (!irb->mt->supports_fast_clear ||
> !brw_is_color_fast_clear_compatible(brw, irb->mt, 
> &ctx->Color.ClearColor))
>can_fast_clear = false;
>  
> @@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
> gl_framebuffer *fb,
> */
>if (!irb->mt->mcs_buf) {
>   assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
> - if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
> + if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
>  /* MCS allocation failed--probably this will only happen in
>   * out-of-memory conditions.  But in any case, try to recover
>   * by falling back to a non-blorp clear technique.
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> index ee4aba9..6a64bcb 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
>  
> intel_renderbuffer_set_draw_offset(irb);
>  
> -   if (intel_miptree_wants_hiz_buffer(brw, mt)) {
> +   if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
>intel_miptree_alloc_hiz(brw, mt);
>if (!mt->hiz_buf)
>return false;
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 0f6d542..101317f 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
>   */
>  static enum intel_msaa_layout
>  compute_msaa_layout(struct brw_context *brw, mesa_format format,
> -enum intel_aux_disable aux_disable)
> +uint32_t layout_flags)
>  {
> /* Prior to Gen7, all MSAA surfaces used IMS layout. */
> if (brw->gen < 7)
> @@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw, mesa_format 
> format,
> */
>if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
>   return INTEL_MSAA_LAYOUT_UMS;
> -  } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
> +  } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
>   /* We can't use the CMS layout because it uses an aux buffer, the 
> MCS
>* buffer. So fallback to UMS, which is identical to CMS without the
>* MCS. */
> @@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> if (brw->gen < 7)
>return false;
>  
> -   if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
> -  return false;
> -
> /* This function applies only to non-multisampled render targets. */
> if (mt->num_samples > 1)
>return false;
> @@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
>return true;
>  }
>  
> +static bool
> +intel_miptree_supports_hiz(struct brw_context *brw,
> +   struct intel_mipmap_tree *mt)
> +{
> +   if (!brw->has_hiz)
> +  return false;
> +
> +   switch (mt->format) {
> +   case MESA_FORMAT_Z_FLOAT32:
> +   case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
> +   case MESA_FORMAT_Z24_UNORM_X8_UINT:
> +   case MESA_FORMAT_Z24_UNORM_S8_UINT:
> +   case MESA_FORMAT_Z_UNORM16:
> +  return true;
> +   default:
> +  return false;
> +   }
> +}
> +
> +
>  /* On Gen9

Re: [Mesa-dev] [PATCH 05/30] i965/miptree: Rework aux enabling

2017-06-21 Thread Chad Versace 
On Fri 16 Jun 2017, Jason Ekstrand wrote:
> This commit replaces the complex and confusing set of disable flags with
> two fairly straightforward fields which describe the intended auxiliary
> surface usage and whether or not the miptree supports fast clears.
> Right now, supports_fast_clear can be entirely derived from aux_usage
> but that will not always be the case.
> 
> This commit makes functional changes.  One of these changes is that it
> re-enables multisampled fast-clears which were accidentally disabled in
> cec30a666930ddb8476a9452a89364a24979ff62 around a year ago.  It should
> also enable CCS_E for window-system buffers which are Y-tiled.  They
> will still get a full resolve like CCS_D but we will at least get some
> of the advantage of compression.
> ---
>  src/mesa/drivers/dri/i965/brw_blorp.c |   4 +-
>  src/mesa/drivers/dri/i965/intel_fbo.c |   2 +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190 
> +-
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  43 +++---
>  4 files changed, 120 insertions(+), 119 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 00092ee..9bd25f0 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
> gl_framebuffer *fb,
> if (set_write_disables(irb, ctx->Color.ColorMask[buf], 
> color_write_disable))
>can_fast_clear = false;
>  
> -   if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
> +   if (!irb->mt->supports_fast_clear ||
> !brw_is_color_fast_clear_compatible(brw, irb->mt, 
> &ctx->Color.ClearColor))
>can_fast_clear = false;
>  
> @@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
> gl_framebuffer *fb,
> */
>if (!irb->mt->mcs_buf) {
>   assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
> - if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
> + if (!intel_miptree_alloc_ccs(brw, irb->mt)) {

The above assert is useless post-patch, because it occurs inside if
(!irb->mt->mcs_buf) and the top of intel_miptree_is_lossless_compressed
looks like this:

/* first check */
if (brw->gen < 9)
return false;

/* second check */
if (!mt->mcs_buf)
return false;

...

Just an observation.
___
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Re: [Mesa-dev] [PATCH 05/30] i965/miptree: Rework aux enabling

2017-06-21 Thread Jason Ekstrand 
On Wed, Jun 21, 2017 at 12:33 PM, Chad Versace 
wrote:

> On Fri 16 Jun 2017, Jason Ekstrand wrote:
> > This commit replaces the complex and confusing set of disable flags with
> > two fairly straightforward fields which describe the intended auxiliary
> > surface usage and whether or not the miptree supports fast clears.
> > Right now, supports_fast_clear can be entirely derived from aux_usage
> > but that will not always be the case.
> >
> > This commit makes functional changes.  One of these changes is that it
> > re-enables multisampled fast-clears which were accidentally disabled in
> > cec30a666930ddb8476a9452a89364a24979ff62 around a year ago.  It should
> > also enable CCS_E for window-system buffers which are Y-tiled.  They
> > will still get a full resolve like CCS_D but we will at least get some
> > of the advantage of compression.
> > ---
> >  src/mesa/drivers/dri/i965/brw_blorp.c |   4 +-
> >  src/mesa/drivers/dri/i965/intel_fbo.c |   2 +-
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190
> +-
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  43 +++---
> >  4 files changed, 120 insertions(+), 119 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> > index 00092ee..9bd25f0 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > @@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw,
> struct gl_framebuffer *fb,
> > if (set_write_disables(irb, ctx->Color.ColorMask[buf],
> color_write_disable))
> >can_fast_clear = false;
> >
> > -   if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
> > +   if (!irb->mt->supports_fast_clear ||
> > !brw_is_color_fast_clear_compatible(brw, irb->mt,
> &ctx->Color.ClearColor))
> >can_fast_clear = false;
> >
> > @@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw,
> struct gl_framebuffer *fb,
> > */
> >if (!irb->mt->mcs_buf) {
> >   assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
> > - if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
> > + if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
> >  /* MCS allocation failed--probably this will only happen in
> >   * out-of-memory conditions.  But in any case, try to
> recover
> >   * by falling back to a non-blorp clear technique.
> > diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
> b/src/mesa/drivers/dri/i965/intel_fbo.c
> > index ee4aba9..6a64bcb 100644
> > --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> > +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> > @@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct
> brw_context *brw,
> >
> > intel_renderbuffer_set_draw_offset(irb);
> >
> > -   if (intel_miptree_wants_hiz_buffer(brw, mt)) {
> > +   if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
> >intel_miptree_alloc_hiz(brw, mt);
> >if (!mt->hiz_buf)
> >return false;
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index 0f6d542..101317f 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
> >   */
> >  static enum intel_msaa_layout
> >  compute_msaa_layout(struct brw_context *brw, mesa_format format,
> > -enum intel_aux_disable aux_disable)
> > +uint32_t layout_flags)
> >  {
> > /* Prior to Gen7, all MSAA surfaces used IMS layout. */
> > if (brw->gen < 7)
> > @@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw,
> mesa_format format,
> > */
> >if (brw->gen == 7 && _mesa_get_format_datatype(format) ==
> GL_INT) {
> >   return INTEL_MSAA_LAYOUT_UMS;
> > -  } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
> > +  } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
> >   /* We can't use the CMS layout because it uses an aux buffer,
> the MCS
> >* buffer. So fallback to UMS, which is identical to CMS
> without the
> >* MCS. */
> > @@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> > if (brw->gen < 7)
> >return false;
> >
> > -   if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
> > -  return false;
> > -
> > /* This function applies only to non-multisampled render targets. */
> > if (mt->num_samples > 1)
> >return false;
> > @@ -215,6 +212,26 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> >return true;
> >  }
> >
> > +static bool
> > +intel_miptree_supports_hiz(struct brw_context *brw,
> > +   struct intel_mipmap_tree *mt)
> > +{
> > +   if (!brw->has_hiz)
> > +  return false;
> > +
> > +   switch (mt->format) {
> > +   case MESA_FORMAT_Z_FLOAT32:
> > +   case MESA_

Re: [Mesa-dev] [PATCH 05/30] i965/miptree: Rework aux enabling

2017-06-21 Thread Chad Versace 
On Wed 21 Jun 2017, Jason Ekstrand wrote:
> On Wed, Jun 21, 2017 at 12:33 PM, Chad Versace <[1]chadvers...@chromium.org>
> wrote:
> 
> On Fri 16 Jun 2017, Jason Ekstrand wrote:
> > This commit replaces the complex and confusing set of disable flags with
> > two fairly straightforward fields which describe the intended auxiliary
> > surface usage and whether or not the miptree supports fast clears.
> > Right now, supports_fast_clear can be entirely derived from aux_usage
> > but that will not always be the case.
> >
> > This commit makes functional changes.  One of these changes is that it
> > re-enables multisampled fast-clears which were accidentally disabled in
> > cec30a666930ddb8476a9452a89364a24979ff62 around a year ago.  It should
> > also enable CCS_E for window-system buffers which are Y-tiled.  They
> > will still get a full resolve like CCS_D but we will at least get some
> > of the advantage of compression.
> > ---
> >  src/mesa/drivers/dri/i965/brw_blorp.c         |   4 +-
> >  src/mesa/drivers/dri/i965/intel_fbo.c         |   2 +-
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 190
> +-
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  43 +++---
> >  4 files changed, 120 insertions(+), 119 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
> b/src/mesa/drivers/dri
> /i965/brw_blorp.c
> > index 00092ee..9bd25f0 100644
> > --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> > +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> > @@ -762,7 +762,7 @@ do_single_blorp_clear(struct brw_context *brw, 
> struct
> gl_framebuffer *fb,
> >     if (set_write_disables(irb, ctx->Color.ColorMask[buf],
> color_write_disable))
> >        can_fast_clear = false;
> >
> > -   if (irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS ||
> > +   if (!irb->mt->supports_fast_clear ||
> >         !brw_is_color_fast_clear_compatible(brw, irb->mt, &ctx->
> Color.ClearColor))
> >        can_fast_clear = false;
> >
> > @@ -785,7 +785,7 @@ do_single_blorp_clear(struct brw_context *brw, 
> struct
> gl_framebuffer *fb,
> >         */
> >        if (!irb->mt->mcs_buf) {
> >           assert(!intel_miptree_is_lossless_compressed(brw, irb->mt));
> > -         if (!intel_miptree_alloc_ccs(brw, irb->mt, false)) {
> > +         if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
> >              /* MCS allocation failed--probably this will only happen in
> >               * out-of-memory conditions.  But in any case, try to
> recover
> >               * by falling back to a non-blorp clear technique.
> > diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
> b/src/mesa/drivers/dri
> /i965/intel_fbo.c
> > index ee4aba9..6a64bcb 100644
> > --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> > +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> > @@ -555,7 +555,7 @@ intel_renderbuffer_update_wrapper(struct brw_context
> *brw,
> >
> >     intel_renderbuffer_set_draw_offset(irb);
> >
> > -   if (intel_miptree_wants_hiz_buffer(brw, mt)) {
> > +   if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
> >        intel_miptree_alloc_hiz(brw, mt);
> >        if (!mt->hiz_buf)
> >        return false;
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/
> drivers/dri/i965/intel_mipmap_tree.c
> > index 0f6d542..101317f 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -64,7 +64,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
> >   */
> >  static enum intel_msaa_layout
> >  compute_msaa_layout(struct brw_context *brw, mesa_format format,
> > -                    enum intel_aux_disable aux_disable)
> > +                    uint32_t layout_flags)
> >  {
> >     /* Prior to Gen7, all MSAA surfaces used IMS layout. */
> >     if (brw->gen < 7)
> > @@ -90,7 +90,7 @@ compute_msaa_layout(struct brw_context *brw,
> mesa_format format,
> >         */
> >        if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT)
> {
> >           return INTEL_MSAA_LAYOUT_UMS;
> > -      } else if (aux_disable & INTEL_AUX_DISABLE_MCS) {
> > +      } else if (layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) {
> >           /* We can't use the CMS layout because it uses an aux buffer,
> the MCS
> >            * buffer. So fallback to UMS, which is identical to CMS
> without the
> >            * MCS. */
> > @@ -148,9 +148,6 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> >     if (brw->gen < 7)
> >        return false;
> >
> > -   if (mt->aux_disable & INTEL_AUX_DISABLE_MCS)
> > -      return false;
> > -
> >     /* This function applies only to no