[Mesa-dev] [PATCH 06/20] radeonsi: add nir support for es epilogue

2017-11-09 Thread Timothy Arceri
---
 src/gallium/drivers/radeonsi/si_shader.c | 32 +---
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index cc68d0ac6f..10b1890b4f 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3185,75 +3185,84 @@ static void si_llvm_emit_ls_epilogue(struct 
ac_shader_abi *abi,
 }
 
 static void si_tgsi_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
 {
struct si_shader_context *ctx = si_shader_context(bld_base);
 
ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
  ctx->outputs[0]);
 }
 
-static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
+static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
+unsigned max_outputs,
+LLVMValueRef *addrs)
 {
-   struct si_shader_context *ctx = si_shader_context(bld_base);
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct si_shader *es = ctx->shader;
struct tgsi_shader_info *info = &es->selector->info;
LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
ctx->param_es2gs_offset);
LLVMValueRef lds_base = NULL;
unsigned chan;
int i;
 
if (ctx->screen->b.chip_class >= GFX9 && info->num_outputs) {
unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
LLVMValueRef wave_idx = unpack_param(ctx, 
ctx->param_merged_wave_info, 24, 4);
vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
 LLVMBuildMul(ctx->ac.builder, wave_idx,
  LLVMConstInt(ctx->i32, 
64, false), ""), "");
lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
LLVMConstInt(ctx->i32, itemsize_dw, 0), 
"");
}
 
for (i = 0; i < info->num_outputs; i++) {
-   LLVMValueRef *out_ptr = ctx->outputs[i];
int param;
 
if (info->output_semantic_name[i] == 
TGSI_SEMANTIC_VIEWPORT_INDEX ||
info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
continue;
 
param = 
si_shader_io_get_unique_index(info->output_semantic_name[i],
  
info->output_semantic_index[i]);
 
for (chan = 0; chan < 4; chan++) {
-   LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
out_ptr[chan], "");
+   LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
addrs[4 * i + chan], "");
out_val = ac_to_integer(&ctx->ac, out_val);
 
/* GFX9 has the ESGS ring in LDS. */
if (ctx->screen->b.chip_class >= GFX9) {
lds_store(ctx, param * 4 + chan, lds_base, 
out_val);
continue;
}
 
ac_build_buffer_store_dword(&ctx->ac,
ctx->esgs_ring,
out_val, 1, NULL, soffset,
(4 * param + chan) * 4,
1, 1, true, true);
}
}
 
if (ctx->screen->b.chip_class >= GFX9)
si_set_es_return_value_for_gs(ctx);
 }
 
+static void si_tgsi_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
+{
+   struct si_shader_context *ctx = si_shader_context(bld_base);
+
+   ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
+ ctx->outputs[0]);
+}
+
 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
 {
if (ctx->screen->b.chip_class >= GFX9)
return unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
else
return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
 }
 
 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
 {
@@ -4430,21 +4439,20 @@ static void create_function(struct si_shader_context 
*ctx)
 
/* VGPRs */
declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
break;
}
 
declare_per_stage_desc_pointers(ctx, &fninfo, true);
declare_vs_specific_input_sgprs(ctx, &fninfo);
 
if (shader->key.as_es) {
-   assert(!shader->selector->nir);
ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, 
ctx->i32);
   

Re: [Mesa-dev] [PATCH 06/20] radeonsi: add nir support for es epilogue

2017-11-10 Thread Marek Olšák
On Fri, Nov 10, 2017 at 4:13 AM, Timothy Arceri  wrote:
> ---
>  src/gallium/drivers/radeonsi/si_shader.c | 32 
> +---
>  1 file changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
> b/src/gallium/drivers/radeonsi/si_shader.c
> index cc68d0ac6f..10b1890b4f 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -3185,75 +3185,84 @@ static void si_llvm_emit_ls_epilogue(struct 
> ac_shader_abi *abi,
>  }
>
>  static void si_tgsi_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
>  {
> struct si_shader_context *ctx = si_shader_context(bld_base);
>
> ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
>   ctx->outputs[0]);
>  }
>
> -static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
> +static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
> +unsigned max_outputs,
> +LLVMValueRef *addrs)
>  {
> -   struct si_shader_context *ctx = si_shader_context(bld_base);
> +   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
> struct si_shader *es = ctx->shader;
> struct tgsi_shader_info *info = &es->selector->info;
> LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
> ctx->param_es2gs_offset);
> LLVMValueRef lds_base = NULL;
> unsigned chan;
> int i;
>
> if (ctx->screen->b.chip_class >= GFX9 && info->num_outputs) {
> unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
> LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
> LLVMValueRef wave_idx = unpack_param(ctx, 
> ctx->param_merged_wave_info, 24, 4);
> vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
>  LLVMBuildMul(ctx->ac.builder, 
> wave_idx,
>   LLVMConstInt(ctx->i32, 
> 64, false), ""), "");
> lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
> LLVMConstInt(ctx->i32, itemsize_dw, 
> 0), "");
> }
>
> for (i = 0; i < info->num_outputs; i++) {
> -   LLVMValueRef *out_ptr = ctx->outputs[i];
> int param;
>
> if (info->output_semantic_name[i] == 
> TGSI_SEMANTIC_VIEWPORT_INDEX ||
> info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
> continue;
>
> param = 
> si_shader_io_get_unique_index(info->output_semantic_name[i],
>   
> info->output_semantic_index[i]);
>
> for (chan = 0; chan < 4; chan++) {
> -   LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
> out_ptr[chan], "");
> +   LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
> addrs[4 * i + chan], "");
> out_val = ac_to_integer(&ctx->ac, out_val);
>
> /* GFX9 has the ESGS ring in LDS. */
> if (ctx->screen->b.chip_class >= GFX9) {
> lds_store(ctx, param * 4 + chan, lds_base, 
> out_val);
> continue;
> }
>
> ac_build_buffer_store_dword(&ctx->ac,
> ctx->esgs_ring,
> out_val, 1, NULL, soffset,
> (4 * param + chan) * 4,
> 1, 1, true, true);
> }
> }
>
> if (ctx->screen->b.chip_class >= GFX9)
> si_set_es_return_value_for_gs(ctx);
>  }
>
> +static void si_tgsi_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
> +{
> +   struct si_shader_context *ctx = si_shader_context(bld_base);
> +
> +   ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
> + ctx->outputs[0]);
> +}

This is exactly the same as si_tgsi_emit_epilogue.

Marek
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